1 // =========================================================================== 2 // This file is autogenerated, please DO NOT modify! 3 // 4 // Generated on 2024-05-23 12:08:57 5 // by user: developer 6 // on machine: swtools 7 // CWD: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/build/lrfbledig/iar/pbe/ieee 8 // Commandline: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_regdef_regs.txt 9 // C&P friendly: /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl -x /home/developer/.conan/data/f65lokilrfbledig/1.3.19-1/library-lprf/eng/package/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/source/ti.com_LOKI_LRFBLEDIG_1.0.xml -f acr --devices CC2340R5:B (2.0) /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_ram_regs.txt /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_regdef_regs.txt 10 // 11 // Relevant file version(s): 12 // 13 // /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/../tools/topsm/regtxtconv.pl 14 // rcs-info: (file not managed or unknown revision control system) 15 // git-hash: 68a752a8737845355f7bdb320d25a59eac685840 16 // 17 // /home/developer/.conan/data/loki-lrf/8.11.00.04/library-lprf/eng/build/0c46501566d33cb4afdce9818f8c3e61ffe04c9a/lrfbledig/pbe/ieee/doc/pbe_ieee_ram_regs.txt 18 // rcs-info: (file not managed or unknown revision control system) 19 // git-hash: 1353f9246ed8136ef80520886e631bb482d0bdfe 20 // 21 // =========================================================================== 22 23 24 #ifndef __PBE_IEEE_RAM_REGS_H 25 #define __PBE_IEEE_RAM_REGS_H 26 27 //****************************************************************************** 28 // REGISTER OFFSETS 29 //****************************************************************************** 30 // Configure synth calibration timeout 31 #define PBE_IEEE_RAM_O_SYNTHCALTIMEOUT 0x00000020U 32 33 // Configure FIFO what statuses to append 34 #define PBE_IEEE_RAM_O_FIFOCFG 0x00000022U 35 36 // 37 #define PBE_IEEE_RAM_O_EXTRABYTES 0x00000024U 38 39 // How long to search for sync before giving up 40 #define PBE_IEEE_RAM_O_RXTIMEOUT 0x00000026U 41 42 // 43 #define PBE_IEEE_RAM_O_PRETXIFS 0x00000028U 44 45 // 46 #define PBE_IEEE_RAM_O_PRERXIFS 0x0000002AU 47 48 // Combined tx/rx/fs configuration 49 #define PBE_IEEE_RAM_O_OPCFG 0x0000002CU 50 51 // 52 #define PBE_IEEE_RAM_O_PATTERN 0x0000002EU 53 54 // Initialization for the whitener, if 0 the whitener is not used 55 #define PBE_IEEE_RAM_O_WHITEINIT 0x00000030U 56 57 // 58 #define PBE_IEEE_RAM_O_PIB 0x00000032U 59 60 // 61 #define PBE_IEEE_RAM_O_FFTYPE 0x00000034U 62 63 // 64 #define PBE_IEEE_RAM_O_NRXNOK 0x00000036U 65 66 // 67 #define PBE_IEEE_RAM_O_NRXIGNORED 0x00000038U 68 69 // 70 #define PBE_IEEE_RAM_O_NRXEMPTY 0x0000003AU 71 72 // 73 #define PBE_IEEE_RAM_O_NRXFIFOFULL 0x0000003CU 74 75 // 76 #define PBE_IEEE_RAM_O_NRXOK 0x0000003EU 77 78 // 79 #define PBE_IEEE_RAM_O_NTX 0x00000040U 80 81 // 82 #define PBE_IEEE_RAM_O_NTXACK 0x00000042U 83 84 // 85 #define PBE_IEEE_RAM_O_NRXTIMEOUT 0x00000044U 86 87 // 88 #define PBE_IEEE_RAM_O_LASTRSSI 0x00000046U 89 90 // 91 #define PBE_IEEE_RAM_O_LASTFREQOFF 0x00000048U 92 93 // 94 #define PBE_IEEE_RAM_O_LASTLQI 0x0000004AU 95 96 // 97 #define PBE_IEEE_RAM_O_LASTTIMESTAMPL 0x0000004CU 98 99 // 100 #define PBE_IEEE_RAM_O_LASTTIMESTAMPH 0x0000004EU 101 102 // Status of receiver and transmitter 103 #define PBE_IEEE_RAM_O_RXSTATUS 0x00000050U 104 105 // General use purpose for storing values 106 #define PBE_IEEE_RAM_O_TMPREG1 0x00000052U 107 108 // General use purpose for storing values 109 #define PBE_IEEE_RAM_O_TMPREG2 0x00000054U 110 111 // General use purpose for storing values 112 #define PBE_IEEE_RAM_O_TMPREG3 0x00000056U 113 114 // General use purpose for storing values 115 #define PBE_IEEE_RAM_O_TMPREG4 0x00000058U 116 117 // Value of last sequence number found 118 #define PBE_IEEE_RAM_O_LSEQNR 0x0000005AU 119 120 // Source matching index 121 #define PBE_IEEE_RAM_O_SRCMATCHIDX 0x0000005CU 122 123 // 124 #define PBE_IEEE_RAM_O_PANID0 0x00000060U 125 126 // 127 #define PBE_IEEE_RAM_O_SHORTADDR0 0x00000062U 128 129 // 130 #define PBE_IEEE_RAM_O_EXTADDR00 0x00000064U 131 132 // 133 #define PBE_IEEE_RAM_O_EXTADDR01 0x00000066U 134 135 // 136 #define PBE_IEEE_RAM_O_EXTADDR02 0x00000068U 137 138 // 139 #define PBE_IEEE_RAM_O_EXTADDR03 0x0000006AU 140 141 // 142 #define PBE_IEEE_RAM_O_FFOPT0 0x0000006CU 143 144 // 145 #define PBE_IEEE_RAM_O_PANID1 0x00000070U 146 147 // 148 #define PBE_IEEE_RAM_O_SHORTADDR1 0x00000072U 149 150 // 151 #define PBE_IEEE_RAM_O_EXTADDR10 0x00000074U 152 153 // 154 #define PBE_IEEE_RAM_O_EXTADDR11 0x00000076U 155 156 // 157 #define PBE_IEEE_RAM_O_EXTADDR12 0x00000078U 158 159 // 160 #define PBE_IEEE_RAM_O_EXTADDR13 0x0000007AU 161 162 // 163 #define PBE_IEEE_RAM_O_FFOPT1 0x0000007CU 164 165 // 166 #define PBE_IEEE_RAM_O_TMPRSSI 0x0000007EU 167 168 // 169 #define PBE_IEEE_RAM_O_ENTRYENABLE00 0x00000080U 170 171 // 172 #define PBE_IEEE_RAM_O_ENTRYENABLE01 0x00000082U 173 174 // 175 #define PBE_IEEE_RAM_O_ENTRYENABLE02 0x00000084U 176 177 // 178 #define PBE_IEEE_RAM_O_ENTRYENABLE03 0x00000086U 179 180 // 181 #define PBE_IEEE_RAM_O_FRAMEPENDING00 0x00000088U 182 183 // 184 #define PBE_IEEE_RAM_O_FRAMEPENDING01 0x0000008AU 185 186 // 187 #define PBE_IEEE_RAM_O_FRAMEPENDING02 0x0000008CU 188 189 // 190 #define PBE_IEEE_RAM_O_FRAMEPENDING03 0x0000008EU 191 192 // 193 #define PBE_IEEE_RAM_O_ENTRYENABLE10 0x00000090U 194 195 // 196 #define PBE_IEEE_RAM_O_ENTRYENABLE11 0x00000092U 197 198 // 199 #define PBE_IEEE_RAM_O_ENTRYENABLE12 0x00000094U 200 201 // 202 #define PBE_IEEE_RAM_O_ENTRYENABLE13 0x00000096U 203 204 // 205 #define PBE_IEEE_RAM_O_FRAMEPENDING10 0x00000098U 206 207 // 208 #define PBE_IEEE_RAM_O_FRAMEPENDING11 0x0000009AU 209 210 // 211 #define PBE_IEEE_RAM_O_FRAMEPENDING12 0x0000009CU 212 213 // 214 #define PBE_IEEE_RAM_O_FRAMEPENDING13 0x0000009EU 215 216 // 217 #define PBE_IEEE_RAM_O_PANCFGED 0x000000A0U 218 219 // 220 #define PBE_IEEE_RAM_O_TMPFCF 0x000000A2U 221 222 // 223 #define PBE_IEEE_RAM_O_CFGAUTOACK 0x000000A4U 224 225 // 226 #define PBE_IEEE_RAM_O_MACCMDID 0x000000A6U 227 228 // 229 #define PBE_IEEE_RAM_O_ACKSTATUS 0x000000A8U 230 231 // 232 #define PBE_IEEE_RAM_O_CORRCNT 0x000000AAU 233 234 // 235 #define PBE_IEEE_RAM_O_PAN0_SRC_MATCH_SHORT_START 0x00000204U 236 237 // 238 #define PBE_IEEE_RAM_O_PAN0_SRC_MATCH_EXT_START 0x00000284U 239 240 // 241 #define PBE_IEEE_RAM_O_PAN1_SRC_MATCH_SHORT_START 0x00000304U 242 243 // 244 #define PBE_IEEE_RAM_O_PAN1_SRC_MATCH_EXT_START 0x00000384U 245 246 //****************************************************************************** 247 // Register: SYNTHCALTIMEOUT 248 //****************************************************************************** 249 // Field: [15:0] val 250 // 251 // SynthCal timeout in 0.25us unit. 0 means infinite (no timeout) 252 #define PBE_IEEE_RAM_SYNTHCALTIMEOUT_VAL_W 16U 253 #define PBE_IEEE_RAM_SYNTHCALTIMEOUT_VAL_M 0xFFFFU 254 #define PBE_IEEE_RAM_SYNTHCALTIMEOUT_VAL_S 0U 255 256 //****************************************************************************** 257 // Register: FIFOCFG 258 //****************************************************************************** 259 // Field: [15:15] appendtimestamp 260 // 261 // Append 16 bit TIMESTAMP 262 #define PBE_IEEE_RAM_FIFOCFG_APPENDTIMESTAMP 0x8000U 263 #define PBE_IEEE_RAM_FIFOCFG_APPENDTIMESTAMP_M 0x8000U 264 #define PBE_IEEE_RAM_FIFOCFG_APPENDTIMESTAMP_S 15U 265 266 // Field: [14:14] appendrssi 267 // 268 // Append 8 bit RSSI 269 #define PBE_IEEE_RAM_FIFOCFG_APPENDRSSI 0x4000U 270 #define PBE_IEEE_RAM_FIFOCFG_APPENDRSSI_M 0x4000U 271 #define PBE_IEEE_RAM_FIFOCFG_APPENDRSSI_S 14U 272 273 // Field: [12:12] appendlqi 274 // 275 // Append 8 bit Modem LQI estimate (Frequency offset) 276 #define PBE_IEEE_RAM_FIFOCFG_APPENDLQI 0x1000U 277 #define PBE_IEEE_RAM_FIFOCFG_APPENDLQI_M 0x1000U 278 #define PBE_IEEE_RAM_FIFOCFG_APPENDLQI_S 12U 279 280 // Field: [11:11] appendstatus 281 // 282 // Append 8 bit status from STATUSBYTE 283 #define PBE_IEEE_RAM_FIFOCFG_APPENDSTATUS 0x0800U 284 #define PBE_IEEE_RAM_FIFOCFG_APPENDSTATUS_M 0x0800U 285 #define PBE_IEEE_RAM_FIFOCFG_APPENDSTATUS_S 11U 286 287 // Field: [10:10] appendcrc 288 // 289 // Append all received crc bits 290 #define PBE_IEEE_RAM_FIFOCFG_APPENDCRC 0x0400U 291 #define PBE_IEEE_RAM_FIFOCFG_APPENDCRC_M 0x0400U 292 #define PBE_IEEE_RAM_FIFOCFG_APPENDCRC_S 10U 293 294 // Field: [8:8] autoflushign 295 // 296 // Automatically removes packets than can be ignored according to the frame filtering in Rx queue. 297 #define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHIGN 0x0100U 298 #define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHIGN_M 0x0100U 299 #define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHIGN_S 8U 300 #define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHIGN_KEEP 0x0000U 301 #define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHIGN_FLUSH 0x0100U 302 303 // Field: [7:7] autoflushcrc 304 // 305 // Automatically removes packets with CRC error from the Rx queue. 306 #define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHCRC 0x0080U 307 #define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHCRC_M 0x0080U 308 #define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHCRC_S 7U 309 #define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHCRC_KEEP 0x0000U 310 #define PBE_IEEE_RAM_FIFOCFG_AUTOFLUSHCRC_FLUSH 0x0080U 311 312 //****************************************************************************** 313 // Register: EXTRABYTES 314 //****************************************************************************** 315 // Field: [15:0] val 316 // 317 // Indicates how many bytes that are required after the PDU to hold the statuses configured in FIFOCFG. 318 #define PBE_IEEE_RAM_EXTRABYTES_VAL_W 16U 319 #define PBE_IEEE_RAM_EXTRABYTES_VAL_M 0xFFFFU 320 #define PBE_IEEE_RAM_EXTRABYTES_VAL_S 0U 321 322 //****************************************************************************** 323 // Register: RXTIMEOUT 324 //****************************************************************************** 325 // Field: [15:0] val 326 // 327 // RX timeout in 0.25us unit. 0 means infinite (no timeout) 328 #define PBE_IEEE_RAM_RXTIMEOUT_VAL_W 16U 329 #define PBE_IEEE_RAM_RXTIMEOUT_VAL_M 0xFFFFU 330 #define PBE_IEEE_RAM_RXTIMEOUT_VAL_S 0U 331 332 //****************************************************************************** 333 // Register: PRETXIFS 334 //****************************************************************************** 335 // Field: [15:0] val 336 // 337 // Base value used after RX to set timer0 for when to start Transmission. 338 #define PBE_IEEE_RAM_PRETXIFS_VAL_W 16U 339 #define PBE_IEEE_RAM_PRETXIFS_VAL_M 0xFFFFU 340 #define PBE_IEEE_RAM_PRETXIFS_VAL_S 0U 341 342 //****************************************************************************** 343 // Register: PRERXIFS 344 //****************************************************************************** 345 // Field: [15:0] val 346 // 347 // Base value used after TX to set timer0 for when to start Receiving. 348 #define PBE_IEEE_RAM_PRERXIFS_VAL_W 16U 349 #define PBE_IEEE_RAM_PRERXIFS_VAL_M 0xFFFFU 350 #define PBE_IEEE_RAM_PRERXIFS_VAL_S 0U 351 352 //****************************************************************************** 353 // Register: OPCFG 354 //****************************************************************************** 355 // Field: [14:14] systim0beh 356 // 357 // Treatment of systim0 during operation 358 #define PBE_IEEE_RAM_OPCFG_SYSTIM0BEH 0x4000U 359 #define PBE_IEEE_RAM_OPCFG_SYSTIM0BEH_M 0x4000U 360 #define PBE_IEEE_RAM_OPCFG_SYSTIM0BEH_S 14U 361 #define PBE_IEEE_RAM_OPCFG_SYSTIM0BEH_NORMAL 0x0000U 362 #define PBE_IEEE_RAM_OPCFG_SYSTIM0BEH_IGNORE 0x4000U 363 364 // Field: [13:13] stop 365 // 366 // Rejected frame behaviour 367 #define PBE_IEEE_RAM_OPCFG_STOP 0x2000U 368 #define PBE_IEEE_RAM_OPCFG_STOP_M 0x2000U 369 #define PBE_IEEE_RAM_OPCFG_STOP_S 13U 370 #define PBE_IEEE_RAM_OPCFG_STOP_SOFTEND 0x0000U 371 #define PBE_IEEE_RAM_OPCFG_STOP_HARDEND 0x2000U 372 373 // Field: [12:12] rxrepeatok 374 // 375 // Rule for what to do after packets with correct CRC 376 #define PBE_IEEE_RAM_OPCFG_RXREPEATOK 0x1000U 377 #define PBE_IEEE_RAM_OPCFG_RXREPEATOK_M 0x1000U 378 #define PBE_IEEE_RAM_OPCFG_RXREPEATOK_S 12U 379 #define PBE_IEEE_RAM_OPCFG_RXREPEATOK_YES 0x0000U 380 #define PBE_IEEE_RAM_OPCFG_RXREPEATOK_NO 0x1000U 381 382 // Field: [11:11] rxrepeatnok 383 // 384 // Rule for what to do after packets with CRC error or address mismatch. 385 #define PBE_IEEE_RAM_OPCFG_RXREPEATNOK 0x0800U 386 #define PBE_IEEE_RAM_OPCFG_RXREPEATNOK_M 0x0800U 387 #define PBE_IEEE_RAM_OPCFG_RXREPEATNOK_S 11U 388 #define PBE_IEEE_RAM_OPCFG_RXREPEATNOK_NO 0x0000U 389 #define PBE_IEEE_RAM_OPCFG_RXREPEATNOK_YES 0x0800U 390 391 // Field: [10:10] txinfinite 392 // 393 // Infinite TX control 394 #define PBE_IEEE_RAM_OPCFG_TXINFINITE 0x0400U 395 #define PBE_IEEE_RAM_OPCFG_TXINFINITE_M 0x0400U 396 #define PBE_IEEE_RAM_OPCFG_TXINFINITE_S 10U 397 #define PBE_IEEE_RAM_OPCFG_TXINFINITE_NO 0x0000U 398 #define PBE_IEEE_RAM_OPCFG_TXINFINITE_YES 0x0400U 399 400 // Field: [9:9] txpattern 401 // 402 // Send fixed pattern 403 #define PBE_IEEE_RAM_OPCFG_TXPATTERN 0x0200U 404 #define PBE_IEEE_RAM_OPCFG_TXPATTERN_M 0x0200U 405 #define PBE_IEEE_RAM_OPCFG_TXPATTERN_S 9U 406 #define PBE_IEEE_RAM_OPCFG_TXPATTERN_NO 0x0000U 407 #define PBE_IEEE_RAM_OPCFG_TXPATTERN_YES 0x0200U 408 409 // Field: [8:7] txfcmd 410 // 411 // Rule for FCMD after TX_DONE 412 #define PBE_IEEE_RAM_OPCFG_TXFCMD_W 2U 413 #define PBE_IEEE_RAM_OPCFG_TXFCMD_M 0x0180U 414 #define PBE_IEEE_RAM_OPCFG_TXFCMD_S 7U 415 #define PBE_IEEE_RAM_OPCFG_TXFCMD_NONE 0x0000U 416 #define PBE_IEEE_RAM_OPCFG_TXFCMD_RETRY 0x0080U 417 #define PBE_IEEE_RAM_OPCFG_TXFCMD_DEALLOC 0x0100U 418 419 // Field: [6:6] start 420 // 421 // Rule for start od operation 422 #define PBE_IEEE_RAM_OPCFG_START 0x0040U 423 #define PBE_IEEE_RAM_OPCFG_START_M 0x0040U 424 #define PBE_IEEE_RAM_OPCFG_START_S 6U 425 #define PBE_IEEE_RAM_OPCFG_START_SYNC 0x0000U 426 #define PBE_IEEE_RAM_OPCFG_START_ASYNC 0x0040U 427 428 // Field: [3:3] nextop 429 // 430 // Enable automatic RX/TX switching, does nothing if OPCFG_SINGLE is selected. This is a feature not used currently. 431 #define PBE_IEEE_RAM_OPCFG_NEXTOP 0x0008U 432 #define PBE_IEEE_RAM_OPCFG_NEXTOP_M 0x0008U 433 #define PBE_IEEE_RAM_OPCFG_NEXTOP_S 3U 434 #define PBE_IEEE_RAM_OPCFG_NEXTOP_SWITCH 0x0000U 435 #define PBE_IEEE_RAM_OPCFG_NEXTOP_SAME 0x0008U 436 437 // Field: [2:2] single 438 // 439 // Only one shall be high of SINGLE or IFSPERIOD. 440 #define PBE_IEEE_RAM_OPCFG_SINGLE 0x0004U 441 #define PBE_IEEE_RAM_OPCFG_SINGLE_M 0x0004U 442 #define PBE_IEEE_RAM_OPCFG_SINGLE_S 2U 443 #define PBE_IEEE_RAM_OPCFG_SINGLE_DIS 0x0000U 444 #define PBE_IEEE_RAM_OPCFG_SINGLE_EN 0x0004U 445 446 // Field: [1:1] ifsperiod 447 // 448 // Only one shall be high of SINGLE or IFSPERIOD. 449 #define PBE_IEEE_RAM_OPCFG_IFSPERIOD 0x0002U 450 #define PBE_IEEE_RAM_OPCFG_IFSPERIOD_M 0x0002U 451 #define PBE_IEEE_RAM_OPCFG_IFSPERIOD_S 1U 452 #define PBE_IEEE_RAM_OPCFG_IFSPERIOD_DIS 0x0000U 453 #define PBE_IEEE_RAM_OPCFG_IFSPERIOD_EN 0x0002U 454 455 // Field: [0:0] rfinterval 456 // 457 // Reserved bit, currently not used 458 #define PBE_IEEE_RAM_OPCFG_RFINTERVAL 0x0001U 459 #define PBE_IEEE_RAM_OPCFG_RFINTERVAL_M 0x0001U 460 #define PBE_IEEE_RAM_OPCFG_RFINTERVAL_S 0U 461 #define PBE_IEEE_RAM_OPCFG_RFINTERVAL_DIS 0x0000U 462 #define PBE_IEEE_RAM_OPCFG_RFINTERVAL_EN 0x0001U 463 464 //****************************************************************************** 465 // Register: PATTERN 466 //****************************************************************************** 467 // Field: [15:0] val 468 // 469 // Data to send if OPCFG.TXPATTERN is 1 470 #define PBE_IEEE_RAM_PATTERN_VAL_W 16U 471 #define PBE_IEEE_RAM_PATTERN_VAL_M 0xFFFFU 472 #define PBE_IEEE_RAM_PATTERN_VAL_S 0U 473 474 //****************************************************************************** 475 // Register: WHITEINIT 476 //****************************************************************************** 477 // Field: [15:0] val 478 // 479 // Whitener initialization value 480 #define PBE_IEEE_RAM_WHITEINIT_VAL_W 16U 481 #define PBE_IEEE_RAM_WHITEINIT_VAL_M 0xFFFFU 482 #define PBE_IEEE_RAM_WHITEINIT_VAL_S 0U 483 484 //****************************************************************************** 485 // Register: PIB 486 //****************************************************************************** 487 // Field: [1:0] panmode 488 // 489 // PAN Information Base sw register 490 #define PBE_IEEE_RAM_PIB_PANMODE_W 2U 491 #define PBE_IEEE_RAM_PIB_PANMODE_M 0x0003U 492 #define PBE_IEEE_RAM_PIB_PANMODE_S 0U 493 #define PBE_IEEE_RAM_PIB_PANMODE_PROMISCUOUS 0x0000U 494 #define PBE_IEEE_RAM_PIB_PANMODE_SINGLE 0x0001U 495 496 //****************************************************************************** 497 // Register: FFTYPE 498 //****************************************************************************** 499 // Field: [15:15] extended1 500 // 501 // Treatment of frames with frame type 111 (Extended) (NOT supported) 502 #define PBE_IEEE_RAM_FFTYPE_EXTENDED1 0x8000U 503 #define PBE_IEEE_RAM_FFTYPE_EXTENDED1_M 0x8000U 504 #define PBE_IEEE_RAM_FFTYPE_EXTENDED1_S 15U 505 506 // Field: [14:14] frag1 507 // 508 // Treatment of frames with frame type 110 (Fragment) (NOT supported) 509 #define PBE_IEEE_RAM_FFTYPE_FRAG1 0x4000U 510 #define PBE_IEEE_RAM_FFTYPE_FRAG1_M 0x4000U 511 #define PBE_IEEE_RAM_FFTYPE_FRAG1_S 14U 512 513 // Field: [13:13] multi1 514 // 515 // Treatment of frames with frame type 101 (Multipurpose) (NOT supported) 516 #define PBE_IEEE_RAM_FFTYPE_MULTI1 0x2000U 517 #define PBE_IEEE_RAM_FFTYPE_MULTI1_M 0x2000U 518 #define PBE_IEEE_RAM_FFTYPE_MULTI1_S 13U 519 520 // Field: [12:12] reserved1 521 // 522 // Treatment of frames with frame type 100 (reserved) (NOT supported) 523 #define PBE_IEEE_RAM_FFTYPE_RESERVED1 0x1000U 524 #define PBE_IEEE_RAM_FFTYPE_RESERVED1_M 0x1000U 525 #define PBE_IEEE_RAM_FFTYPE_RESERVED1_S 12U 526 527 // Field: [11:11] maccmd1 528 // 529 // Treatment of frames with frame type 011 (MAC command) 530 #define PBE_IEEE_RAM_FFTYPE_MACCMD1 0x0800U 531 #define PBE_IEEE_RAM_FFTYPE_MACCMD1_M 0x0800U 532 #define PBE_IEEE_RAM_FFTYPE_MACCMD1_S 11U 533 534 // Field: [10:10] ack1 535 // 536 // Treatment of frames with frame type 010 (ACK) 537 #define PBE_IEEE_RAM_FFTYPE_ACK1 0x0400U 538 #define PBE_IEEE_RAM_FFTYPE_ACK1_M 0x0400U 539 #define PBE_IEEE_RAM_FFTYPE_ACK1_S 10U 540 #define PBE_IEEE_RAM_FFTYPE_ACK1_ACCEPT 0x0400U 541 542 // Field: [9:9] data1 543 // 544 // Treatment of frames with frame type 001 (data) 545 #define PBE_IEEE_RAM_FFTYPE_DATA1 0x0200U 546 #define PBE_IEEE_RAM_FFTYPE_DATA1_M 0x0200U 547 #define PBE_IEEE_RAM_FFTYPE_DATA1_S 9U 548 549 // Field: [8:8] beacon1 550 // 551 // Treatment of frames with frame type 000 (beacon) 552 #define PBE_IEEE_RAM_FFTYPE_BEACON1 0x0100U 553 #define PBE_IEEE_RAM_FFTYPE_BEACON1_M 0x0100U 554 #define PBE_IEEE_RAM_FFTYPE_BEACON1_S 8U 555 556 // Field: [7:7] extended0 557 // 558 // Treatment of frames with frame type 111 (Extended) (NOT supported) 559 #define PBE_IEEE_RAM_FFTYPE_EXTENDED0 0x0080U 560 #define PBE_IEEE_RAM_FFTYPE_EXTENDED0_M 0x0080U 561 #define PBE_IEEE_RAM_FFTYPE_EXTENDED0_S 7U 562 563 // Field: [6:6] frag0 564 // 565 // Treatment of frames with frame type 110 (Fragment) (NOT supported) 566 #define PBE_IEEE_RAM_FFTYPE_FRAG0 0x0040U 567 #define PBE_IEEE_RAM_FFTYPE_FRAG0_M 0x0040U 568 #define PBE_IEEE_RAM_FFTYPE_FRAG0_S 6U 569 570 // Field: [5:5] multi0 571 // 572 // Treatment of frames with frame type 101 (Multipurpose) (NOT supported) 573 #define PBE_IEEE_RAM_FFTYPE_MULTI0 0x0020U 574 #define PBE_IEEE_RAM_FFTYPE_MULTI0_M 0x0020U 575 #define PBE_IEEE_RAM_FFTYPE_MULTI0_S 5U 576 577 // Field: [4:4] reserved0 578 // 579 // Treatment of frames with frame type 100 (reserved) (NOT supported) 580 #define PBE_IEEE_RAM_FFTYPE_RESERVED0 0x0010U 581 #define PBE_IEEE_RAM_FFTYPE_RESERVED0_M 0x0010U 582 #define PBE_IEEE_RAM_FFTYPE_RESERVED0_S 4U 583 584 // Field: [3:3] maccmd0 585 // 586 // Treatment of frames with frame type 011 (MAC command) 587 #define PBE_IEEE_RAM_FFTYPE_MACCMD0 0x0008U 588 #define PBE_IEEE_RAM_FFTYPE_MACCMD0_M 0x0008U 589 #define PBE_IEEE_RAM_FFTYPE_MACCMD0_S 3U 590 591 // Field: [2:2] ack0 592 // 593 // Treatment of frames with frame type 010 (ACK) 594 #define PBE_IEEE_RAM_FFTYPE_ACK0 0x0004U 595 #define PBE_IEEE_RAM_FFTYPE_ACK0_M 0x0004U 596 #define PBE_IEEE_RAM_FFTYPE_ACK0_S 2U 597 #define PBE_IEEE_RAM_FFTYPE_ACK0_ACCEPT 0x0004U 598 599 // Field: [1:1] data0 600 // 601 // Treatment of frames with frame type 001 (data) 602 #define PBE_IEEE_RAM_FFTYPE_DATA0 0x0002U 603 #define PBE_IEEE_RAM_FFTYPE_DATA0_M 0x0002U 604 #define PBE_IEEE_RAM_FFTYPE_DATA0_S 1U 605 606 // Field: [0:0] beacon0 607 // 608 // Treatment of frames with frame type 000 (beacon) 609 #define PBE_IEEE_RAM_FFTYPE_BEACON0 0x0001U 610 #define PBE_IEEE_RAM_FFTYPE_BEACON0_M 0x0001U 611 #define PBE_IEEE_RAM_FFTYPE_BEACON0_S 0U 612 613 //****************************************************************************** 614 // Register: NRXNOK 615 //****************************************************************************** 616 // Field: [15:0] val 617 // 618 // Number of packets received with CRC error 619 #define PBE_IEEE_RAM_NRXNOK_VAL_W 16U 620 #define PBE_IEEE_RAM_NRXNOK_VAL_M 0xFFFFU 621 #define PBE_IEEE_RAM_NRXNOK_VAL_S 0U 622 623 //****************************************************************************** 624 // Register: NRXIGNORED 625 //****************************************************************************** 626 // Field: [15:0] val 627 // 628 // Number of packets received with CRC OK, but to be ignored by the MCU 629 #define PBE_IEEE_RAM_NRXIGNORED_VAL_W 16U 630 #define PBE_IEEE_RAM_NRXIGNORED_VAL_M 0xFFFFU 631 #define PBE_IEEE_RAM_NRXIGNORED_VAL_S 0U 632 633 //****************************************************************************** 634 // Register: NRXEMPTY 635 //****************************************************************************** 636 // Field: [15:0] val 637 // 638 // Number of received packets discarded because the Rx FIFO was full 639 #define PBE_IEEE_RAM_NRXEMPTY_VAL_W 16U 640 #define PBE_IEEE_RAM_NRXEMPTY_VAL_M 0xFFFFU 641 #define PBE_IEEE_RAM_NRXEMPTY_VAL_S 0U 642 643 //****************************************************************************** 644 // Register: NRXFIFOFULL 645 //****************************************************************************** 646 // Field: [15:0] val 647 // 648 // Number of received packets discarded because the Rx FIFO was full 649 #define PBE_IEEE_RAM_NRXFIFOFULL_VAL_W 16U 650 #define PBE_IEEE_RAM_NRXFIFOFULL_VAL_M 0xFFFFU 651 #define PBE_IEEE_RAM_NRXFIFOFULL_VAL_S 0U 652 653 //****************************************************************************** 654 // Register: NRXOK 655 //****************************************************************************** 656 // Field: [15:0] val 657 // 658 // Number of non-empty packets received with CRC OK and not to be ignored by the MCU 659 #define PBE_IEEE_RAM_NRXOK_VAL_W 16U 660 #define PBE_IEEE_RAM_NRXOK_VAL_M 0xFFFFU 661 #define PBE_IEEE_RAM_NRXOK_VAL_S 0U 662 663 //****************************************************************************** 664 // Register: NTX 665 //****************************************************************************** 666 // Field: [15:0] val 667 // 668 // Number of transmitted packets,incremented for every transmitted packet 669 #define PBE_IEEE_RAM_NTX_VAL_W 16U 670 #define PBE_IEEE_RAM_NTX_VAL_M 0xFFFFU 671 #define PBE_IEEE_RAM_NTX_VAL_S 0U 672 673 //****************************************************************************** 674 // Register: NTXACK 675 //****************************************************************************** 676 // Field: [15:0] val 677 // 678 // Number of Imm-Ack transmitted packets, from auto-ack mode,incremented for every transmitted packet 679 #define PBE_IEEE_RAM_NTXACK_VAL_W 16U 680 #define PBE_IEEE_RAM_NTXACK_VAL_M 0xFFFFU 681 #define PBE_IEEE_RAM_NTXACK_VAL_S 0U 682 683 //****************************************************************************** 684 // Register: NRXTIMEOUT 685 //****************************************************************************** 686 // Field: [15:0] val 687 // 688 // Number of RX timeout 689 #define PBE_IEEE_RAM_NRXTIMEOUT_VAL_W 16U 690 #define PBE_IEEE_RAM_NRXTIMEOUT_VAL_M 0xFFFFU 691 #define PBE_IEEE_RAM_NRXTIMEOUT_VAL_S 0U 692 693 //****************************************************************************** 694 // Register: LASTRSSI 695 //****************************************************************************** 696 // Field: [15:0] val 697 // 698 // RSSI of last received packet with crc OK 699 #define PBE_IEEE_RAM_LASTRSSI_VAL_W 16U 700 #define PBE_IEEE_RAM_LASTRSSI_VAL_M 0xFFFFU 701 #define PBE_IEEE_RAM_LASTRSSI_VAL_S 0U 702 703 //****************************************************************************** 704 // Register: LASTFREQOFF 705 //****************************************************************************** 706 // Field: [15:0] val 707 // 708 // FREQOFF of last received packet with crc OK 709 #define PBE_IEEE_RAM_LASTFREQOFF_VAL_W 16U 710 #define PBE_IEEE_RAM_LASTFREQOFF_VAL_M 0xFFFFU 711 #define PBE_IEEE_RAM_LASTFREQOFF_VAL_S 0U 712 713 //****************************************************************************** 714 // Register: LASTLQI 715 //****************************************************************************** 716 // Field: [15:0] val 717 // 718 // LQI of last received packet with crc OK 719 #define PBE_IEEE_RAM_LASTLQI_VAL_W 16U 720 #define PBE_IEEE_RAM_LASTLQI_VAL_M 0xFFFFU 721 #define PBE_IEEE_RAM_LASTLQI_VAL_S 0U 722 723 //****************************************************************************** 724 // Register: LASTTIMESTAMPL 725 //****************************************************************************** 726 // Field: [15:0] val 727 // 728 // Lower part of timestamp. 729 #define PBE_IEEE_RAM_LASTTIMESTAMPL_VAL_W 16U 730 #define PBE_IEEE_RAM_LASTTIMESTAMPL_VAL_M 0xFFFFU 731 #define PBE_IEEE_RAM_LASTTIMESTAMPL_VAL_S 0U 732 733 //****************************************************************************** 734 // Register: LASTTIMESTAMPH 735 //****************************************************************************** 736 // Field: [15:0] val 737 // 738 // Upper part of timestamp. 739 #define PBE_IEEE_RAM_LASTTIMESTAMPH_VAL_W 16U 740 #define PBE_IEEE_RAM_LASTTIMESTAMPH_VAL_M 0xFFFFU 741 #define PBE_IEEE_RAM_LASTTIMESTAMPH_VAL_S 0U 742 743 //****************************************************************************** 744 // Register: RXSTATUS 745 //****************************************************************************** 746 // Field: [2:2] txinprogress 747 // 748 // Status of frame transmission 749 #define PBE_IEEE_RAM_RXSTATUS_TXINPROGRESS 0x0004U 750 #define PBE_IEEE_RAM_RXSTATUS_TXINPROGRESS_M 0x0004U 751 #define PBE_IEEE_RAM_RXSTATUS_TXINPROGRESS_S 2U 752 #define PBE_IEEE_RAM_RXSTATUS_TXINPROGRESS_IDLE 0x0000U 753 #define PBE_IEEE_RAM_RXSTATUS_TXINPROGRESS_TX 0x0004U 754 755 // Field: [1:1] txackinprogress 756 // 757 // Status of auto ACK transmission 758 #define PBE_IEEE_RAM_RXSTATUS_TXACKINPROGRESS 0x0002U 759 #define PBE_IEEE_RAM_RXSTATUS_TXACKINPROGRESS_M 0x0002U 760 #define PBE_IEEE_RAM_RXSTATUS_TXACKINPROGRESS_S 1U 761 #define PBE_IEEE_RAM_RXSTATUS_TXACKINPROGRESS_IDLE 0x0000U 762 #define PBE_IEEE_RAM_RXSTATUS_TXACKINPROGRESS_TXACK 0x0002U 763 764 // Field: [0:0] frameinprogress 765 // 766 // Status of frame reception 767 #define PBE_IEEE_RAM_RXSTATUS_FRAMEINPROGRESS 0x0001U 768 #define PBE_IEEE_RAM_RXSTATUS_FRAMEINPROGRESS_M 0x0001U 769 #define PBE_IEEE_RAM_RXSTATUS_FRAMEINPROGRESS_S 0U 770 #define PBE_IEEE_RAM_RXSTATUS_FRAMEINPROGRESS_IDLE 0x0000U 771 #define PBE_IEEE_RAM_RXSTATUS_FRAMEINPROGRESS_FRAME 0x0001U 772 773 //****************************************************************************** 774 // Register: TMPREG1 775 //****************************************************************************** 776 // Field: [15:0] val 777 // 778 // Value can be anything is necessary to be stored temporary 779 #define PBE_IEEE_RAM_TMPREG1_VAL_W 16U 780 #define PBE_IEEE_RAM_TMPREG1_VAL_M 0xFFFFU 781 #define PBE_IEEE_RAM_TMPREG1_VAL_S 0U 782 783 //****************************************************************************** 784 // Register: TMPREG2 785 //****************************************************************************** 786 // Field: [15:0] val 787 // 788 // Value can be anything is necessary to be stored temporary 789 #define PBE_IEEE_RAM_TMPREG2_VAL_W 16U 790 #define PBE_IEEE_RAM_TMPREG2_VAL_M 0xFFFFU 791 #define PBE_IEEE_RAM_TMPREG2_VAL_S 0U 792 793 //****************************************************************************** 794 // Register: TMPREG3 795 //****************************************************************************** 796 // Field: [15:0] val 797 // 798 // Value can be anything is necessary to be stored temporary 799 #define PBE_IEEE_RAM_TMPREG3_VAL_W 16U 800 #define PBE_IEEE_RAM_TMPREG3_VAL_M 0xFFFFU 801 #define PBE_IEEE_RAM_TMPREG3_VAL_S 0U 802 803 //****************************************************************************** 804 // Register: TMPREG4 805 //****************************************************************************** 806 // Field: [15:0] val 807 // 808 // Value can be anything is necessary to be stored temporary 809 #define PBE_IEEE_RAM_TMPREG4_VAL_W 16U 810 #define PBE_IEEE_RAM_TMPREG4_VAL_M 0xFFFFU 811 #define PBE_IEEE_RAM_TMPREG4_VAL_S 0U 812 813 //****************************************************************************** 814 // Register: LSEQNR 815 //****************************************************************************** 816 // Field: [7:0] val 817 // 818 // Last decoded sequence number 819 #define PBE_IEEE_RAM_LSEQNR_VAL_W 8U 820 #define PBE_IEEE_RAM_LSEQNR_VAL_M 0x00FFU 821 #define PBE_IEEE_RAM_LSEQNR_VAL_S 0U 822 823 //****************************************************************************** 824 // Register: SRCMATCHIDX 825 //****************************************************************************** 826 // Field: [7:0] tblidx 827 // 828 // Store the index from the src table for which there was a match with the src field of the received frame 829 #define PBE_IEEE_RAM_SRCMATCHIDX_TBLIDX_W 8U 830 #define PBE_IEEE_RAM_SRCMATCHIDX_TBLIDX_M 0x00FFU 831 #define PBE_IEEE_RAM_SRCMATCHIDX_TBLIDX_S 0U 832 833 //****************************************************************************** 834 // Register: PANID0 835 //****************************************************************************** 836 // Field: [15:0] val 837 // 838 // Local PAN ID0 839 #define PBE_IEEE_RAM_PANID0_VAL_W 16U 840 #define PBE_IEEE_RAM_PANID0_VAL_M 0xFFFFU 841 #define PBE_IEEE_RAM_PANID0_VAL_S 0U 842 843 //****************************************************************************** 844 // Register: SHORTADDR0 845 //****************************************************************************** 846 // Field: [15:0] val 847 // 848 // Local PAN ID0 short address 849 #define PBE_IEEE_RAM_SHORTADDR0_VAL_W 16U 850 #define PBE_IEEE_RAM_SHORTADDR0_VAL_M 0xFFFFU 851 #define PBE_IEEE_RAM_SHORTADDR0_VAL_S 0U 852 853 //****************************************************************************** 854 // Register: EXTADDR00 855 //****************************************************************************** 856 // Field: [15:0] val 857 // 858 // Local PAN ID0 extended address, bits 15:0 859 #define PBE_IEEE_RAM_EXTADDR00_VAL_W 16U 860 #define PBE_IEEE_RAM_EXTADDR00_VAL_M 0xFFFFU 861 #define PBE_IEEE_RAM_EXTADDR00_VAL_S 0U 862 863 //****************************************************************************** 864 // Register: EXTADDR01 865 //****************************************************************************** 866 // Field: [15:0] val 867 // 868 // Local PAN ID0 extended address, bits 31:16 869 #define PBE_IEEE_RAM_EXTADDR01_VAL_W 16U 870 #define PBE_IEEE_RAM_EXTADDR01_VAL_M 0xFFFFU 871 #define PBE_IEEE_RAM_EXTADDR01_VAL_S 0U 872 873 //****************************************************************************** 874 // Register: EXTADDR02 875 //****************************************************************************** 876 // Field: [15:0] val 877 // 878 // Local PAN ID0 extended address, bits 47:32 879 #define PBE_IEEE_RAM_EXTADDR02_VAL_W 16U 880 #define PBE_IEEE_RAM_EXTADDR02_VAL_M 0xFFFFU 881 #define PBE_IEEE_RAM_EXTADDR02_VAL_S 0U 882 883 //****************************************************************************** 884 // Register: EXTADDR03 885 //****************************************************************************** 886 // Field: [15:0] val 887 // 888 // Local PAN ID0 extended address, bits 63:48 889 #define PBE_IEEE_RAM_EXTADDR03_VAL_W 16U 890 #define PBE_IEEE_RAM_EXTADDR03_VAL_M 0xFFFFU 891 #define PBE_IEEE_RAM_EXTADDR03_VAL_S 0U 892 893 //****************************************************************************** 894 // Register: FFOPT0 895 //****************************************************************************** 896 // Field: [9:8] maxframe 897 // 898 // Reject frames where the frame version field in the FCF is greater than this value 899 #define PBE_IEEE_RAM_FFOPT0_MAXFRAME_W 2U 900 #define PBE_IEEE_RAM_FFOPT0_MAXFRAME_M 0x0300U 901 #define PBE_IEEE_RAM_FFOPT0_MAXFRAME_S 8U 902 903 // Field: [7:7] pancoord 904 // 905 // 906 #define PBE_IEEE_RAM_FFOPT0_PANCOORD 0x0080U 907 #define PBE_IEEE_RAM_FFOPT0_PANCOORD_M 0x0080U 908 #define PBE_IEEE_RAM_FFOPT0_PANCOORD_S 7U 909 #define PBE_IEEE_RAM_FFOPT0_PANCOORD_DISABLED 0x0000U 910 #define PBE_IEEE_RAM_FFOPT0_PANCOORD_EN 0x0080U 911 912 // Field: [6:6] preqonly 913 // 914 // 915 #define PBE_IEEE_RAM_FFOPT0_PREQONLY 0x0040U 916 #define PBE_IEEE_RAM_FFOPT0_PREQONLY_M 0x0040U 917 #define PBE_IEEE_RAM_FFOPT0_PREQONLY_S 6U 918 #define PBE_IEEE_RAM_FFOPT0_PREQONLY_ANY 0x0000U 919 #define PBE_IEEE_RAM_FFOPT0_PREQONLY_DATAREQ 0x0040U 920 921 // Field: [5:5] defpend 922 // 923 // The value of the pending data bit in auto ACK packets that are not subject to auto-pend 924 #define PBE_IEEE_RAM_FFOPT0_DEFPEND 0x0020U 925 #define PBE_IEEE_RAM_FFOPT0_DEFPEND_M 0x0020U 926 #define PBE_IEEE_RAM_FFOPT0_DEFPEND_S 5U 927 928 // Field: [4:4] autopend 929 // 930 // 931 #define PBE_IEEE_RAM_FFOPT0_AUTOPEND 0x0010U 932 #define PBE_IEEE_RAM_FFOPT0_AUTOPEND_M 0x0010U 933 #define PBE_IEEE_RAM_FFOPT0_AUTOPEND_S 4U 934 #define PBE_IEEE_RAM_FFOPT0_AUTOPEND_DISABLE 0x0000U 935 #define PBE_IEEE_RAM_FFOPT0_AUTOPEND_EN 0x0010U 936 937 // Field: [2:2] autoack 938 // 939 // 940 #define PBE_IEEE_RAM_FFOPT0_AUTOACK 0x0004U 941 #define PBE_IEEE_RAM_FFOPT0_AUTOACK_M 0x0004U 942 #define PBE_IEEE_RAM_FFOPT0_AUTOACK_S 2U 943 #define PBE_IEEE_RAM_FFOPT0_AUTOACK_DISABLE 0x0000U 944 #define PBE_IEEE_RAM_FFOPT0_AUTOACK_EN 0x0004U 945 946 // Field: [1:1] unused1 947 // 948 // Unused bitfield 949 #define PBE_IEEE_RAM_FFOPT0_UNUSED1 0x0002U 950 #define PBE_IEEE_RAM_FFOPT0_UNUSED1_M 0x0002U 951 #define PBE_IEEE_RAM_FFOPT0_UNUSED1_S 1U 952 953 // Field: [0:0] unused0 954 // 955 // Unused bitfield 956 #define PBE_IEEE_RAM_FFOPT0_UNUSED0 0x0001U 957 #define PBE_IEEE_RAM_FFOPT0_UNUSED0_M 0x0001U 958 #define PBE_IEEE_RAM_FFOPT0_UNUSED0_S 0U 959 960 //****************************************************************************** 961 // Register: PANID1 962 //****************************************************************************** 963 // Field: [15:0] val 964 // 965 // Local PAN ID1 966 #define PBE_IEEE_RAM_PANID1_VAL_W 16U 967 #define PBE_IEEE_RAM_PANID1_VAL_M 0xFFFFU 968 #define PBE_IEEE_RAM_PANID1_VAL_S 0U 969 970 //****************************************************************************** 971 // Register: SHORTADDR1 972 //****************************************************************************** 973 // Field: [15:0] val 974 // 975 // Local PAN ID1 short address 976 #define PBE_IEEE_RAM_SHORTADDR1_VAL_W 16U 977 #define PBE_IEEE_RAM_SHORTADDR1_VAL_M 0xFFFFU 978 #define PBE_IEEE_RAM_SHORTADDR1_VAL_S 0U 979 980 //****************************************************************************** 981 // Register: EXTADDR10 982 //****************************************************************************** 983 // Field: [15:0] val 984 // 985 // Local PAN ID1 extended address, bits 15:0 986 #define PBE_IEEE_RAM_EXTADDR10_VAL_W 16U 987 #define PBE_IEEE_RAM_EXTADDR10_VAL_M 0xFFFFU 988 #define PBE_IEEE_RAM_EXTADDR10_VAL_S 0U 989 990 //****************************************************************************** 991 // Register: EXTADDR11 992 //****************************************************************************** 993 // Field: [15:0] val 994 // 995 // Local PAN ID1 extended address, bits 31:16 996 #define PBE_IEEE_RAM_EXTADDR11_VAL_W 16U 997 #define PBE_IEEE_RAM_EXTADDR11_VAL_M 0xFFFFU 998 #define PBE_IEEE_RAM_EXTADDR11_VAL_S 0U 999 1000 //****************************************************************************** 1001 // Register: EXTADDR12 1002 //****************************************************************************** 1003 // Field: [15:0] val 1004 // 1005 // Local PAN ID1 extended address, bits 47:32 1006 #define PBE_IEEE_RAM_EXTADDR12_VAL_W 16U 1007 #define PBE_IEEE_RAM_EXTADDR12_VAL_M 0xFFFFU 1008 #define PBE_IEEE_RAM_EXTADDR12_VAL_S 0U 1009 1010 //****************************************************************************** 1011 // Register: EXTADDR13 1012 //****************************************************************************** 1013 // Field: [15:0] val 1014 // 1015 // Local PAN ID1 extended address, bits 63:48 1016 #define PBE_IEEE_RAM_EXTADDR13_VAL_W 16U 1017 #define PBE_IEEE_RAM_EXTADDR13_VAL_M 0xFFFFU 1018 #define PBE_IEEE_RAM_EXTADDR13_VAL_S 0U 1019 1020 //****************************************************************************** 1021 // Register: FFOPT1 1022 //****************************************************************************** 1023 // Field: [9:8] maxframe 1024 // 1025 // Reject frames where the frame version field in the FCF is greater than this value 1026 #define PBE_IEEE_RAM_FFOPT1_MAXFRAME_W 2U 1027 #define PBE_IEEE_RAM_FFOPT1_MAXFRAME_M 0x0300U 1028 #define PBE_IEEE_RAM_FFOPT1_MAXFRAME_S 8U 1029 1030 // Field: [7:7] pancoord 1031 // 1032 // 1033 #define PBE_IEEE_RAM_FFOPT1_PANCOORD 0x0080U 1034 #define PBE_IEEE_RAM_FFOPT1_PANCOORD_M 0x0080U 1035 #define PBE_IEEE_RAM_FFOPT1_PANCOORD_S 7U 1036 #define PBE_IEEE_RAM_FFOPT1_PANCOORD_DISABLED 0x0000U 1037 #define PBE_IEEE_RAM_FFOPT1_PANCOORD_EN 0x0080U 1038 1039 // Field: [6:6] preqonly 1040 // 1041 // 1042 #define PBE_IEEE_RAM_FFOPT1_PREQONLY 0x0040U 1043 #define PBE_IEEE_RAM_FFOPT1_PREQONLY_M 0x0040U 1044 #define PBE_IEEE_RAM_FFOPT1_PREQONLY_S 6U 1045 #define PBE_IEEE_RAM_FFOPT1_PREQONLY_ANY 0x0000U 1046 #define PBE_IEEE_RAM_FFOPT1_PREQONLY_DATAREQ 0x0040U 1047 1048 // Field: [5:5] defpend 1049 // 1050 // The value of the pending data bit in auto ACK packets that are not subject to auto-pend 1051 #define PBE_IEEE_RAM_FFOPT1_DEFPEND 0x0020U 1052 #define PBE_IEEE_RAM_FFOPT1_DEFPEND_M 0x0020U 1053 #define PBE_IEEE_RAM_FFOPT1_DEFPEND_S 5U 1054 1055 // Field: [4:4] autopend 1056 // 1057 // 1058 #define PBE_IEEE_RAM_FFOPT1_AUTOPEND 0x0010U 1059 #define PBE_IEEE_RAM_FFOPT1_AUTOPEND_M 0x0010U 1060 #define PBE_IEEE_RAM_FFOPT1_AUTOPEND_S 4U 1061 #define PBE_IEEE_RAM_FFOPT1_AUTOPEND_DISABLE 0x0000U 1062 #define PBE_IEEE_RAM_FFOPT1_AUTOPEND_EN 0x0010U 1063 1064 // Field: [2:2] autoack 1065 // 1066 // 1067 #define PBE_IEEE_RAM_FFOPT1_AUTOACK 0x0004U 1068 #define PBE_IEEE_RAM_FFOPT1_AUTOACK_M 0x0004U 1069 #define PBE_IEEE_RAM_FFOPT1_AUTOACK_S 2U 1070 #define PBE_IEEE_RAM_FFOPT1_AUTOACK_DISABLE 0x0000U 1071 #define PBE_IEEE_RAM_FFOPT1_AUTOACK_EN 0x0004U 1072 1073 // Field: [1:1] unused1 1074 // 1075 // Unused bitfield 1076 #define PBE_IEEE_RAM_FFOPT1_UNUSED1 0x0002U 1077 #define PBE_IEEE_RAM_FFOPT1_UNUSED1_M 0x0002U 1078 #define PBE_IEEE_RAM_FFOPT1_UNUSED1_S 1U 1079 1080 // Field: [0:0] unused0 1081 // 1082 // Unused bitfield 1083 #define PBE_IEEE_RAM_FFOPT1_UNUSED0 0x0001U 1084 #define PBE_IEEE_RAM_FFOPT1_UNUSED0_M 0x0001U 1085 #define PBE_IEEE_RAM_FFOPT1_UNUSED0_S 0U 1086 1087 //****************************************************************************** 1088 // Register: TMPRSSI 1089 //****************************************************************************** 1090 // Field: [15:0] val 1091 // 1092 // A temporary storage of the signal strength of received signal 1093 #define PBE_IEEE_RAM_TMPRSSI_VAL_W 16U 1094 #define PBE_IEEE_RAM_TMPRSSI_VAL_M 0xFFFFU 1095 #define PBE_IEEE_RAM_TMPRSSI_VAL_S 0U 1096 1097 //****************************************************************************** 1098 // Register: ENTRYENABLE00 1099 //****************************************************************************** 1100 // Field: [15:0] val 1101 // 1102 // Source matching entry enable bits for entry 0-15 of PAN 0 1103 #define PBE_IEEE_RAM_ENTRYENABLE00_VAL_W 16U 1104 #define PBE_IEEE_RAM_ENTRYENABLE00_VAL_M 0xFFFFU 1105 #define PBE_IEEE_RAM_ENTRYENABLE00_VAL_S 0U 1106 1107 //****************************************************************************** 1108 // Register: ENTRYENABLE01 1109 //****************************************************************************** 1110 // Field: [15:0] val 1111 // 1112 // Source matching entry enable bits for entry 16-31 of PAN 0 1113 #define PBE_IEEE_RAM_ENTRYENABLE01_VAL_W 16U 1114 #define PBE_IEEE_RAM_ENTRYENABLE01_VAL_M 0xFFFFU 1115 #define PBE_IEEE_RAM_ENTRYENABLE01_VAL_S 0U 1116 1117 //****************************************************************************** 1118 // Register: ENTRYENABLE02 1119 //****************************************************************************** 1120 // Field: [15:0] val 1121 // 1122 // Source matching entry enable bits for entry 32-47 of PAN 0 1123 #define PBE_IEEE_RAM_ENTRYENABLE02_VAL_W 16U 1124 #define PBE_IEEE_RAM_ENTRYENABLE02_VAL_M 0xFFFFU 1125 #define PBE_IEEE_RAM_ENTRYENABLE02_VAL_S 0U 1126 1127 //****************************************************************************** 1128 // Register: ENTRYENABLE03 1129 //****************************************************************************** 1130 // Field: [15:0] val 1131 // 1132 // Source matching entry enable bits for entry 48-63 of PAN 0 1133 #define PBE_IEEE_RAM_ENTRYENABLE03_VAL_W 16U 1134 #define PBE_IEEE_RAM_ENTRYENABLE03_VAL_M 0xFFFFU 1135 #define PBE_IEEE_RAM_ENTRYENABLE03_VAL_S 0U 1136 1137 //****************************************************************************** 1138 // Register: FRAMEPENDING00 1139 //****************************************************************************** 1140 // Field: [15:0] val 1141 // 1142 // Frame pending bits for source matching entry 0-15 of PAN 0 1143 #define PBE_IEEE_RAM_FRAMEPENDING00_VAL_W 16U 1144 #define PBE_IEEE_RAM_FRAMEPENDING00_VAL_M 0xFFFFU 1145 #define PBE_IEEE_RAM_FRAMEPENDING00_VAL_S 0U 1146 1147 //****************************************************************************** 1148 // Register: FRAMEPENDING01 1149 //****************************************************************************** 1150 // Field: [15:0] val 1151 // 1152 // Frame pending bits for source matching entry 16-31 of PAN 0 1153 #define PBE_IEEE_RAM_FRAMEPENDING01_VAL_W 16U 1154 #define PBE_IEEE_RAM_FRAMEPENDING01_VAL_M 0xFFFFU 1155 #define PBE_IEEE_RAM_FRAMEPENDING01_VAL_S 0U 1156 1157 //****************************************************************************** 1158 // Register: FRAMEPENDING02 1159 //****************************************************************************** 1160 // Field: [15:0] val 1161 // 1162 // Frame pending bits for source matching entry 32-47 of PAN 0 1163 #define PBE_IEEE_RAM_FRAMEPENDING02_VAL_W 16U 1164 #define PBE_IEEE_RAM_FRAMEPENDING02_VAL_M 0xFFFFU 1165 #define PBE_IEEE_RAM_FRAMEPENDING02_VAL_S 0U 1166 1167 //****************************************************************************** 1168 // Register: FRAMEPENDING03 1169 //****************************************************************************** 1170 // Field: [15:0] val 1171 // 1172 // Frame pending bits for source matching entry 48-63 of PAN 0 1173 #define PBE_IEEE_RAM_FRAMEPENDING03_VAL_W 16U 1174 #define PBE_IEEE_RAM_FRAMEPENDING03_VAL_M 0xFFFFU 1175 #define PBE_IEEE_RAM_FRAMEPENDING03_VAL_S 0U 1176 1177 //****************************************************************************** 1178 // Register: ENTRYENABLE10 1179 //****************************************************************************** 1180 // Field: [15:0] val 1181 // 1182 // Source matching entry enable bits for entry 0-15 of PAN 1 1183 #define PBE_IEEE_RAM_ENTRYENABLE10_VAL_W 16U 1184 #define PBE_IEEE_RAM_ENTRYENABLE10_VAL_M 0xFFFFU 1185 #define PBE_IEEE_RAM_ENTRYENABLE10_VAL_S 0U 1186 1187 //****************************************************************************** 1188 // Register: ENTRYENABLE11 1189 //****************************************************************************** 1190 // Field: [15:0] val 1191 // 1192 // Source matching entry enable bits for entry 16-31 of PAN 1 1193 #define PBE_IEEE_RAM_ENTRYENABLE11_VAL_W 16U 1194 #define PBE_IEEE_RAM_ENTRYENABLE11_VAL_M 0xFFFFU 1195 #define PBE_IEEE_RAM_ENTRYENABLE11_VAL_S 0U 1196 1197 //****************************************************************************** 1198 // Register: ENTRYENABLE12 1199 //****************************************************************************** 1200 // Field: [15:0] val 1201 // 1202 // Source matching entry enable bits for entry 32-47 of PAN 1 1203 #define PBE_IEEE_RAM_ENTRYENABLE12_VAL_W 16U 1204 #define PBE_IEEE_RAM_ENTRYENABLE12_VAL_M 0xFFFFU 1205 #define PBE_IEEE_RAM_ENTRYENABLE12_VAL_S 0U 1206 1207 //****************************************************************************** 1208 // Register: ENTRYENABLE13 1209 //****************************************************************************** 1210 // Field: [15:0] val 1211 // 1212 // Source matching entry enable bits for entry 48-63 of PAN 1 1213 #define PBE_IEEE_RAM_ENTRYENABLE13_VAL_W 16U 1214 #define PBE_IEEE_RAM_ENTRYENABLE13_VAL_M 0xFFFFU 1215 #define PBE_IEEE_RAM_ENTRYENABLE13_VAL_S 0U 1216 1217 //****************************************************************************** 1218 // Register: FRAMEPENDING10 1219 //****************************************************************************** 1220 // Field: [15:0] val 1221 // 1222 // Frame pending bits for source matching entry 0-15 of PAN 1 1223 #define PBE_IEEE_RAM_FRAMEPENDING10_VAL_W 16U 1224 #define PBE_IEEE_RAM_FRAMEPENDING10_VAL_M 0xFFFFU 1225 #define PBE_IEEE_RAM_FRAMEPENDING10_VAL_S 0U 1226 1227 //****************************************************************************** 1228 // Register: FRAMEPENDING11 1229 //****************************************************************************** 1230 // Field: [15:0] val 1231 // 1232 // Frame pending bits for source matching entry 16-31 of PAN 1 1233 #define PBE_IEEE_RAM_FRAMEPENDING11_VAL_W 16U 1234 #define PBE_IEEE_RAM_FRAMEPENDING11_VAL_M 0xFFFFU 1235 #define PBE_IEEE_RAM_FRAMEPENDING11_VAL_S 0U 1236 1237 //****************************************************************************** 1238 // Register: FRAMEPENDING12 1239 //****************************************************************************** 1240 // Field: [15:0] val 1241 // 1242 // Frame pending bits for source matching entry 32-47 of PAN 1 1243 #define PBE_IEEE_RAM_FRAMEPENDING12_VAL_W 16U 1244 #define PBE_IEEE_RAM_FRAMEPENDING12_VAL_M 0xFFFFU 1245 #define PBE_IEEE_RAM_FRAMEPENDING12_VAL_S 0U 1246 1247 //****************************************************************************** 1248 // Register: FRAMEPENDING13 1249 //****************************************************************************** 1250 // Field: [15:0] val 1251 // 1252 // Frame pending bits for source matching entry 48-63 of PAN 1 1253 #define PBE_IEEE_RAM_FRAMEPENDING13_VAL_W 16U 1254 #define PBE_IEEE_RAM_FRAMEPENDING13_VAL_M 0xFFFFU 1255 #define PBE_IEEE_RAM_FRAMEPENDING13_VAL_S 0U 1256 1257 //****************************************************************************** 1258 // Register: PANCFGED 1259 //****************************************************************************** 1260 // Field: [15:0] val 1261 // 1262 // PANID of the PAN for which there was a match 1263 #define PBE_IEEE_RAM_PANCFGED_VAL_W 16U 1264 #define PBE_IEEE_RAM_PANCFGED_VAL_M 0xFFFFU 1265 #define PBE_IEEE_RAM_PANCFGED_VAL_S 0U 1266 1267 //****************************************************************************** 1268 // Register: TMPFCF 1269 //****************************************************************************** 1270 // Field: [15:0] val 1271 // 1272 // Frame Control Field received from the frame 1273 #define PBE_IEEE_RAM_TMPFCF_VAL_W 16U 1274 #define PBE_IEEE_RAM_TMPFCF_VAL_M 0xFFFFU 1275 #define PBE_IEEE_RAM_TMPFCF_VAL_S 0U 1276 1277 //****************************************************************************** 1278 // Register: CFGAUTOACK 1279 //****************************************************************************** 1280 // Field: [9:9] ackmode 1281 // 1282 // Control the filtering process of sequence number 1283 #define PBE_IEEE_RAM_CFGAUTOACK_ACKMODE 0x0200U 1284 #define PBE_IEEE_RAM_CFGAUTOACK_ACKMODE_M 0x0200U 1285 #define PBE_IEEE_RAM_CFGAUTOACK_ACKMODE_S 9U 1286 #define PBE_IEEE_RAM_CFGAUTOACK_ACKMODE_NOFILT 0x0000U 1287 #define PBE_IEEE_RAM_CFGAUTOACK_ACKMODE_FILT 0x0200U 1288 1289 // Field: [8:8] flagreq 1290 // 1291 // Control the status flag towards MCU, when timeout occured waiting for Imm-Ack frame 1292 #define PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ 0x0100U 1293 #define PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ_M 0x0100U 1294 #define PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ_S 8U 1295 #define PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ_DIS 0x0000U 1296 #define PBE_IEEE_RAM_CFGAUTOACK_FLAGREQ_EN 0x0100U 1297 1298 // Field: [7:0] expseqnm 1299 // 1300 // Expected sequence number to correlate with the received one 1301 #define PBE_IEEE_RAM_CFGAUTOACK_EXPSEQNM_W 8U 1302 #define PBE_IEEE_RAM_CFGAUTOACK_EXPSEQNM_M 0x00FFU 1303 #define PBE_IEEE_RAM_CFGAUTOACK_EXPSEQNM_S 0U 1304 1305 //****************************************************************************** 1306 // Register: MACCMDID 1307 //****************************************************************************** 1308 // Field: [7:0] val 1309 // 1310 // MAC command frame command ID field received 1311 #define PBE_IEEE_RAM_MACCMDID_VAL_W 8U 1312 #define PBE_IEEE_RAM_MACCMDID_VAL_M 0x00FFU 1313 #define PBE_IEEE_RAM_MACCMDID_VAL_S 0U 1314 1315 //****************************************************************************** 1316 // Register: ACKSTATUS 1317 //****************************************************************************** 1318 // Field: [4:4] crcok 1319 // 1320 // ACKDONE event is raised indicating the frame was received with CRC ok 1321 #define PBE_IEEE_RAM_ACKSTATUS_CRCOK 0x0010U 1322 #define PBE_IEEE_RAM_ACKSTATUS_CRCOK_M 0x0010U 1323 #define PBE_IEEE_RAM_ACKSTATUS_CRCOK_S 4U 1324 1325 // Field: [3:3] ignored 1326 // 1327 // ACKDONE event is raised indicating the frame was received but ignored (seq. number mismatch included) 1328 #define PBE_IEEE_RAM_ACKSTATUS_IGNORED 0x0008U 1329 #define PBE_IEEE_RAM_ACKSTATUS_IGNORED_M 0x0008U 1330 #define PBE_IEEE_RAM_ACKSTATUS_IGNORED_S 3U 1331 1332 // Field: [2:2] otherfrm 1333 // 1334 // ACKDONE event is raised indicating other frame than ACK has been received 1335 #define PBE_IEEE_RAM_ACKSTATUS_OTHERFRM 0x0004U 1336 #define PBE_IEEE_RAM_ACKSTATUS_OTHERFRM_M 0x0004U 1337 #define PBE_IEEE_RAM_ACKSTATUS_OTHERFRM_S 2U 1338 1339 // Field: [1:1] crcerr 1340 // 1341 // ACKDONE event is raised indicating the frame was received with CRC error 1342 #define PBE_IEEE_RAM_ACKSTATUS_CRCERR 0x0002U 1343 #define PBE_IEEE_RAM_ACKSTATUS_CRCERR_M 0x0002U 1344 #define PBE_IEEE_RAM_ACKSTATUS_CRCERR_S 1U 1345 1346 // Field: [0:0] synctimeout 1347 // 1348 // ACKDONE event is raised indicating in the receiving window no ACK arrived 1349 #define PBE_IEEE_RAM_ACKSTATUS_SYNCTIMEOUT 0x0001U 1350 #define PBE_IEEE_RAM_ACKSTATUS_SYNCTIMEOUT_M 0x0001U 1351 #define PBE_IEEE_RAM_ACKSTATUS_SYNCTIMEOUT_S 0U 1352 1353 //****************************************************************************** 1354 // Register: CORRCNT 1355 //****************************************************************************** 1356 // Field: [7:0] val 1357 // 1358 // Counter of MDMPROG events to be used for CCA mode 2 1359 #define PBE_IEEE_RAM_CORRCNT_VAL_W 8U 1360 #define PBE_IEEE_RAM_CORRCNT_VAL_M 0x00FFU 1361 #define PBE_IEEE_RAM_CORRCNT_VAL_S 0U 1362 1363 //****************************************************************************** 1364 // Register: PAN0_SRC_MATCH_SHORT_START 1365 //****************************************************************************** 1366 // Field: [15:0] val 1367 // 1368 // First entry of short source match table for PAN 0 1369 #define PBE_IEEE_RAM_PAN0_SRC_MATCH_SHORT_START_VAL_W 16U 1370 #define PBE_IEEE_RAM_PAN0_SRC_MATCH_SHORT_START_VAL_M 0xFFFFU 1371 #define PBE_IEEE_RAM_PAN0_SRC_MATCH_SHORT_START_VAL_S 0U 1372 1373 //****************************************************************************** 1374 // Register: PAN0_SRC_MATCH_EXT_START 1375 //****************************************************************************** 1376 // Field: [15:0] val 1377 // 1378 // First entry of extended source match table for PAN 0 if present 1379 #define PBE_IEEE_RAM_PAN0_SRC_MATCH_EXT_START_VAL_W 16U 1380 #define PBE_IEEE_RAM_PAN0_SRC_MATCH_EXT_START_VAL_M 0xFFFFU 1381 #define PBE_IEEE_RAM_PAN0_SRC_MATCH_EXT_START_VAL_S 0U 1382 1383 //****************************************************************************** 1384 // Register: PAN1_SRC_MATCH_SHORT_START 1385 //****************************************************************************** 1386 // Field: [15:0] val 1387 // 1388 // First entry of short source match table for PAN 1 1389 #define PBE_IEEE_RAM_PAN1_SRC_MATCH_SHORT_START_VAL_W 16U 1390 #define PBE_IEEE_RAM_PAN1_SRC_MATCH_SHORT_START_VAL_M 0xFFFFU 1391 #define PBE_IEEE_RAM_PAN1_SRC_MATCH_SHORT_START_VAL_S 0U 1392 1393 //****************************************************************************** 1394 // Register: PAN1_SRC_MATCH_EXT_START 1395 //****************************************************************************** 1396 // Field: [15:0] val 1397 // 1398 // First entry of extended source match table for PAN 1 if present 1399 #define PBE_IEEE_RAM_PAN1_SRC_MATCH_EXT_START_VAL_W 16U 1400 #define PBE_IEEE_RAM_PAN1_SRC_MATCH_EXT_START_VAL_M 0xFFFFU 1401 #define PBE_IEEE_RAM_PAN1_SRC_MATCH_EXT_START_VAL_S 0U 1402 1403 1404 #endif // __PBE_IEEE_RAM_REGS_H 1405
