1 /****************************************************************************** 2 * Filename: hw_nvic_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_NVIC_H__ 34 #define __HW_NVIC_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // NVIC component 40 // 41 //***************************************************************************** 42 // Interrupt Set-Enable Register 43 #define NVIC_O_ISER 0x00000100U 44 45 // Interrupt Clear-Enable Register 46 #define NVIC_O_ICER 0x00000180U 47 48 // Interrupt Set-Pending Register 49 #define NVIC_O_ISPR 0x00000200U 50 51 // Interrupt Clear-Pending Register 52 #define NVIC_O_ICPR 0x00000280U 53 54 // Interrupt Priority Register 0 55 #define NVIC_O_IPR0 0x00000400U 56 57 // Interrupt Priority Register 1 58 #define NVIC_O_IPR1 0x00000404U 59 60 // Interrupt Priority Register 2 61 #define NVIC_O_IPR2 0x00000408U 62 63 // Interrupt Priority Register 3 64 #define NVIC_O_IPR3 0x0000040CU 65 66 // Interrupt Priority Register 4 67 #define NVIC_O_IPR4 0x00000410U 68 69 // Interrupt Priority Register 5 70 #define NVIC_O_IPR5 0x00000414U 71 72 // Interrupt Priority Register 6 73 #define NVIC_O_IPR6 0x00000418U 74 75 // Interrupt Priority Register 7 76 #define NVIC_O_IPR7 0x0000041CU 77 78 //***************************************************************************** 79 // 80 // Register: NVIC_O_ISER 81 // 82 //***************************************************************************** 83 // Field: [31:0] SETENA 84 // 85 // Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the 86 // corresponding interrupt. Reading the bit returns its current enable state. 87 // Reset clears the SETENA fields. 88 #define NVIC_ISER_SETENA_W 32U 89 #define NVIC_ISER_SETENA_M 0xFFFFFFFFU 90 #define NVIC_ISER_SETENA_S 0U 91 92 //***************************************************************************** 93 // 94 // Register: NVIC_O_ICER 95 // 96 //***************************************************************************** 97 // Field: [31:0] CLRENA 98 // 99 // Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the 100 // corresponding interrupt. Reading the bit returns its current enable state. 101 // Reset clears the CLRENA field. 102 #define NVIC_ICER_CLRENA_W 32U 103 #define NVIC_ICER_CLRENA_M 0xFFFFFFFFU 104 #define NVIC_ICER_CLRENA_S 0U 105 106 //***************************************************************************** 107 // 108 // Register: NVIC_O_ISPR 109 // 110 //***************************************************************************** 111 // Field: [31:0] SETPEND 112 // 113 // Interrupt set-pending bits for a: Write: 1 = pend interrupt 0 = no effect; 114 // Read: 1 = interrupt is pending 0 = interrupt is not pending. 115 #define NVIC_ISPR_SETPEND_W 32U 116 #define NVIC_ISPR_SETPEND_M 0xFFFFFFFFU 117 #define NVIC_ISPR_SETPEND_S 0U 118 119 //***************************************************************************** 120 // 121 // Register: NVIC_O_ICPR 122 // 123 //***************************************************************************** 124 // Field: [31:0] CLRPEND 125 // 126 // Interrupt clear-pending bits: Write: 1 = clear interrupt pending bit, 0 = no 127 // effect; Read: 1 = interrupt is pending 0 = interrupt is not pending. 128 #define NVIC_ICPR_CLRPEND_W 32U 129 #define NVIC_ICPR_CLRPEND_M 0xFFFFFFFFU 130 #define NVIC_ICPR_CLRPEND_S 0U 131 132 //***************************************************************************** 133 // 134 // Register: NVIC_O_IPR0 135 // 136 //***************************************************************************** 137 // Field: [31:30] IP_3 138 // 139 // Priority of interrupt 3 140 #define NVIC_IPR0_IP_3_W 2U 141 #define NVIC_IPR0_IP_3_M 0xC0000000U 142 #define NVIC_IPR0_IP_3_S 30U 143 144 // Field: [23:22] IP_2 145 // 146 // Priority of interrupt 2 147 #define NVIC_IPR0_IP_2_W 2U 148 #define NVIC_IPR0_IP_2_M 0x00C00000U 149 #define NVIC_IPR0_IP_2_S 22U 150 151 // Field: [15:14] IP_1 152 // 153 // Priority of interrupt 1 154 #define NVIC_IPR0_IP_1_W 2U 155 #define NVIC_IPR0_IP_1_M 0x0000C000U 156 #define NVIC_IPR0_IP_1_S 14U 157 158 // Field: [7:6] IP_0 159 // 160 // Priority of interrupt 0 161 #define NVIC_IPR0_IP_0_W 2U 162 #define NVIC_IPR0_IP_0_M 0x000000C0U 163 #define NVIC_IPR0_IP_0_S 6U 164 165 //***************************************************************************** 166 // 167 // Register: NVIC_O_IPR1 168 // 169 //***************************************************************************** 170 // Field: [31:30] IP_7 171 // 172 // Priority of interrupt 7 173 #define NVIC_IPR1_IP_7_W 2U 174 #define NVIC_IPR1_IP_7_M 0xC0000000U 175 #define NVIC_IPR1_IP_7_S 30U 176 177 // Field: [23:22] IP_6 178 // 179 // Priority of interrupt 6 180 #define NVIC_IPR1_IP_6_W 2U 181 #define NVIC_IPR1_IP_6_M 0x00C00000U 182 #define NVIC_IPR1_IP_6_S 22U 183 184 // Field: [15:14] IP_5 185 // 186 // Priority of interrupt 5 187 #define NVIC_IPR1_IP_5_W 2U 188 #define NVIC_IPR1_IP_5_M 0x0000C000U 189 #define NVIC_IPR1_IP_5_S 14U 190 191 // Field: [7:6] IP_4 192 // 193 // Priority of interrupt 4 194 #define NVIC_IPR1_IP_4_W 2U 195 #define NVIC_IPR1_IP_4_M 0x000000C0U 196 #define NVIC_IPR1_IP_4_S 6U 197 198 //***************************************************************************** 199 // 200 // Register: NVIC_O_IPR2 201 // 202 //***************************************************************************** 203 // Field: [31:30] IP_11 204 // 205 // Priority of interrupt 11 206 #define NVIC_IPR2_IP_11_W 2U 207 #define NVIC_IPR2_IP_11_M 0xC0000000U 208 #define NVIC_IPR2_IP_11_S 30U 209 210 // Field: [23:22] IP_10 211 // 212 // Priority of interrupt 10 213 #define NVIC_IPR2_IP_10_W 2U 214 #define NVIC_IPR2_IP_10_M 0x00C00000U 215 #define NVIC_IPR2_IP_10_S 22U 216 217 // Field: [15:14] IP_9 218 // 219 // Priority of interrupt 9 220 #define NVIC_IPR2_IP_9_W 2U 221 #define NVIC_IPR2_IP_9_M 0x0000C000U 222 #define NVIC_IPR2_IP_9_S 14U 223 224 // Field: [7:6] IP_8 225 // 226 // Priority of interrupt 8 227 #define NVIC_IPR2_IP_8_W 2U 228 #define NVIC_IPR2_IP_8_M 0x000000C0U 229 #define NVIC_IPR2_IP_8_S 6U 230 231 //***************************************************************************** 232 // 233 // Register: NVIC_O_IPR3 234 // 235 //***************************************************************************** 236 // Field: [31:30] IP_15 237 // 238 // Priority of interrupt 15 239 #define NVIC_IPR3_IP_15_W 2U 240 #define NVIC_IPR3_IP_15_M 0xC0000000U 241 #define NVIC_IPR3_IP_15_S 30U 242 243 // Field: [23:22] IP_14 244 // 245 // Priority of interrupt 14 246 #define NVIC_IPR3_IP_14_W 2U 247 #define NVIC_IPR3_IP_14_M 0x00C00000U 248 #define NVIC_IPR3_IP_14_S 22U 249 250 // Field: [15:14] IP_13 251 // 252 // Priority of interrupt 13 253 #define NVIC_IPR3_IP_13_W 2U 254 #define NVIC_IPR3_IP_13_M 0x0000C000U 255 #define NVIC_IPR3_IP_13_S 14U 256 257 // Field: [7:6] IP_12 258 // 259 // Priority of interrupt 12 260 #define NVIC_IPR3_IP_12_W 2U 261 #define NVIC_IPR3_IP_12_M 0x000000C0U 262 #define NVIC_IPR3_IP_12_S 6U 263 264 //***************************************************************************** 265 // 266 // Register: NVIC_O_IPR4 267 // 268 //***************************************************************************** 269 // Field: [31:30] IP_19 270 // 271 // Priority of interrupt 19 272 #define NVIC_IPR4_IP_19_W 2U 273 #define NVIC_IPR4_IP_19_M 0xC0000000U 274 #define NVIC_IPR4_IP_19_S 30U 275 276 // Field: [23:22] IP_18 277 // 278 // Priority of interrupt 18 279 #define NVIC_IPR4_IP_18_W 2U 280 #define NVIC_IPR4_IP_18_M 0x00C00000U 281 #define NVIC_IPR4_IP_18_S 22U 282 283 // Field: [15:14] IP_17 284 // 285 // Priority of interrupt 17 286 #define NVIC_IPR4_IP_17_W 2U 287 #define NVIC_IPR4_IP_17_M 0x0000C000U 288 #define NVIC_IPR4_IP_17_S 14U 289 290 // Field: [7:6] IP_16 291 // 292 // Priority of interrupt 16 293 #define NVIC_IPR4_IP_16_W 2U 294 #define NVIC_IPR4_IP_16_M 0x000000C0U 295 #define NVIC_IPR4_IP_16_S 6U 296 297 //***************************************************************************** 298 // 299 // Register: NVIC_O_IPR5 300 // 301 //***************************************************************************** 302 // Field: [31:30] IP_23 303 // 304 // Priority of interrupt 23 305 #define NVIC_IPR5_IP_23_W 2U 306 #define NVIC_IPR5_IP_23_M 0xC0000000U 307 #define NVIC_IPR5_IP_23_S 30U 308 309 // Field: [23:22] IP_22 310 // 311 // Priority of interrupt 22 312 #define NVIC_IPR5_IP_22_W 2U 313 #define NVIC_IPR5_IP_22_M 0x00C00000U 314 #define NVIC_IPR5_IP_22_S 22U 315 316 // Field: [15:14] IP_21 317 // 318 // Priority of interrupt 21 319 #define NVIC_IPR5_IP_21_W 2U 320 #define NVIC_IPR5_IP_21_M 0x0000C000U 321 #define NVIC_IPR5_IP_21_S 14U 322 323 // Field: [7:6] IP_20 324 // 325 // Priority of interrupt 20 326 #define NVIC_IPR5_IP_20_W 2U 327 #define NVIC_IPR5_IP_20_M 0x000000C0U 328 #define NVIC_IPR5_IP_20_S 6U 329 330 //***************************************************************************** 331 // 332 // Register: NVIC_O_IPR6 333 // 334 //***************************************************************************** 335 // Field: [31:30] IP_27 336 // 337 // Priority of interrupt 27 338 #define NVIC_IPR6_IP_27_W 2U 339 #define NVIC_IPR6_IP_27_M 0xC0000000U 340 #define NVIC_IPR6_IP_27_S 30U 341 342 // Field: [23:22] IP_26 343 // 344 // Priority of interrupt 26 345 #define NVIC_IPR6_IP_26_W 2U 346 #define NVIC_IPR6_IP_26_M 0x00C00000U 347 #define NVIC_IPR6_IP_26_S 22U 348 349 // Field: [15:14] IP_25 350 // 351 // Priority of interrupt 25 352 #define NVIC_IPR6_IP_25_W 2U 353 #define NVIC_IPR6_IP_25_M 0x0000C000U 354 #define NVIC_IPR6_IP_25_S 14U 355 356 // Field: [7:6] IP_24 357 // 358 // Priority of interrupt 24 359 #define NVIC_IPR6_IP_24_W 2U 360 #define NVIC_IPR6_IP_24_M 0x000000C0U 361 #define NVIC_IPR6_IP_24_S 6U 362 363 //***************************************************************************** 364 // 365 // Register: NVIC_O_IPR7 366 // 367 //***************************************************************************** 368 // Field: [31:30] IP_31 369 // 370 // Priority of interrupt 31 371 #define NVIC_IPR7_IP_31_W 2U 372 #define NVIC_IPR7_IP_31_M 0xC0000000U 373 #define NVIC_IPR7_IP_31_S 30U 374 375 // Field: [23:22] IP_30 376 // 377 // Priority of interrupt 30 378 #define NVIC_IPR7_IP_30_W 2U 379 #define NVIC_IPR7_IP_30_M 0x00C00000U 380 #define NVIC_IPR7_IP_30_S 22U 381 382 // Field: [15:14] IP_29 383 // 384 // Priority of interrupt 29 385 #define NVIC_IPR7_IP_29_W 2U 386 #define NVIC_IPR7_IP_29_M 0x0000C000U 387 #define NVIC_IPR7_IP_29_S 14U 388 389 // Field: [7:6] IP_28 390 // 391 // Priority of interrupt 28 392 #define NVIC_IPR7_IP_28_W 2U 393 #define NVIC_IPR7_IP_28_M 0x000000C0U 394 #define NVIC_IPR7_IP_28_S 6U 395 396 397 #endif // __NVIC__ 398
