1 /****************************************************************************** 2 * Filename: hw_lrfds2r_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_LRFDS2R_H__ 34 #define __HW_LRFDS2R_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // LRFDS2R component 40 // 41 //***************************************************************************** 42 // Sample2RAM Config Register 43 #define LRFDS2R_O_CFG 0x00000000U 44 45 // Sample2RAM Start Address Register 46 #define LRFDS2R_O_START 0x00000004U 47 48 // Sample2RAM Stop Address Register 49 #define LRFDS2R_O_STOP 0x00000008U 50 51 // Sample2RAM Status Register 52 #define LRFDS2R_O_STAT 0x0000000CU 53 54 // Sample2RAM Trigger Register 55 #define LRFDS2R_O_TRIG 0x00000010U 56 57 //***************************************************************************** 58 // 59 // Register: LRFDS2R_O_CFG 60 // 61 //***************************************************************************** 62 // Field: [5] LAST0 63 // 64 // When this bit is enabled, then the S2R will write all zeros, whenever it 65 // tries to write the stop address (instead of the regular value) 66 // ENUMs: 67 // EN Writing all zeros to stop address is enabled 68 // DIS Writing all zeros to stop address is disabled 69 #define LRFDS2R_CFG_LAST0 0x00000020U 70 #define LRFDS2R_CFG_LAST0_M 0x00000020U 71 #define LRFDS2R_CFG_LAST0_S 5U 72 #define LRFDS2R_CFG_LAST0_EN 0x00000020U 73 #define LRFDS2R_CFG_LAST0_DIS 0x00000000U 74 75 // Field: [4:3] TRIGMODE 76 // 77 // Trigger mode 78 // ENUMs: 79 // ONEVENT Trigger on event, i.e. fill memory area once, but 80 // wait for an event from the selected sample 81 // source. 82 // PERIODIC Periodic mode, i.e. fill memory area periodically, 83 // continuing at the start address after reaching 84 // the stop address, upon a manual trigger. 85 // ONESHOT One shot mode, i.e. fill memory area once, from 86 // start to stop address, upon a manual trigger. 87 #define LRFDS2R_CFG_TRIGMODE_W 2U 88 #define LRFDS2R_CFG_TRIGMODE_M 0x00000018U 89 #define LRFDS2R_CFG_TRIGMODE_S 3U 90 #define LRFDS2R_CFG_TRIGMODE_ONEVENT 0x00000010U 91 #define LRFDS2R_CFG_TRIGMODE_PERIODIC 0x00000008U 92 #define LRFDS2R_CFG_TRIGMODE_ONESHOT 0x00000000U 93 94 // Field: [2:1] SEL 95 // 96 // Select sample source 97 // ENUMs: 98 // DECSTAGE Samples from decode stage mux. The sample source 99 // is selected in LRFDMDM:DEMDEBUG.DECSTAGEDEBUG 100 // register. 101 // FRONTEND Samples from frontend mux. The sample source is 102 // selected in LRFDMDM:DEMDEBUG.FRONTENDDEBUG 103 // register. 104 // ADCDIG Samples from ADCDIG. 105 // SYNTH Samples from frequency synthesizer's DTST 106 // interface. 107 #define LRFDS2R_CFG_SEL_W 2U 108 #define LRFDS2R_CFG_SEL_M 0x00000006U 109 #define LRFDS2R_CFG_SEL_S 1U 110 #define LRFDS2R_CFG_SEL_DECSTAGE 0x00000006U 111 #define LRFDS2R_CFG_SEL_FRONTEND 0x00000004U 112 #define LRFDS2R_CFG_SEL_ADCDIG 0x00000002U 113 #define LRFDS2R_CFG_SEL_SYNTH 0x00000000U 114 115 // Field: [0] CTL 116 // 117 // Sample2RAM module enable 118 // ENUMs: 119 // EN Enabled 120 // DIS Not enabled 121 #define LRFDS2R_CFG_CTL 0x00000001U 122 #define LRFDS2R_CFG_CTL_M 0x00000001U 123 #define LRFDS2R_CFG_CTL_S 0U 124 #define LRFDS2R_CFG_CTL_EN 0x00000001U 125 #define LRFDS2R_CFG_CTL_DIS 0x00000000U 126 127 //***************************************************************************** 128 // 129 // Register: LRFDS2R_O_START 130 // 131 //***************************************************************************** 132 // Field: [12:0] ADDR 133 // 134 // Memory start address for where to dump the samples. The address is word 135 // oriented starting from the start of the MCERAM, then RFERAM, then PBERAM, 136 // then S2RRAM and then BUFRAM. Also note that S2R has write priority to the 137 // RAMs, so any attempt at simultaneously accessing the RAMs used by S2R while 138 // it is running may be unreliable (no arbitration/stall implemented), and 139 // should be avoided. 140 // 141 // 0 -> 1023 : MCERAM 142 // 1024 -> 2047 : RFERAM 143 // 2048 -> 3071 : PBERAM 144 // 3072 -> 4095 : S2RRAM 145 // 4096 -> 4479 : BUFRAM 146 // ENUMs: 147 // ALLONES All the bits are 1 148 // ALLZEROS All the bits are 0 149 #define LRFDS2R_START_ADDR_W 13U 150 #define LRFDS2R_START_ADDR_M 0x00001FFFU 151 #define LRFDS2R_START_ADDR_S 0U 152 #define LRFDS2R_START_ADDR_ALLONES 0x00001FFFU 153 #define LRFDS2R_START_ADDR_ALLZEROS 0x00000000U 154 155 //***************************************************************************** 156 // 157 // Register: LRFDS2R_O_STOP 158 // 159 //***************************************************************************** 160 // Field: [12:0] ADDR 161 // 162 // Memory start address for where to dump the samples. The address is word 163 // oriented starting from the start of the MCERAM, then RFERAM, then PBERAM, 164 // then S2RRAM and then BUFRAM. Also note that S2R has write priority to the 165 // RAMs, so any attempt at simultaneously accessing the RAMs used by S2R while 166 // it is running may be unreliable (no arbitration/stall implemented), and 167 // should be avoided. 168 // 169 // 0 -> 1023 : MCERAM 170 // 1024 -> 2047 : RFERAM 171 // 2048 -> 3071 : PBERAM 172 // 3072 -> 4095 : S2RRAM 173 // 4096 -> 4479 : BUFRAM 174 // ENUMs: 175 // ALLONES All the bits are 1 176 // ALLZEROS All the bits are 0 177 #define LRFDS2R_STOP_ADDR_W 13U 178 #define LRFDS2R_STOP_ADDR_M 0x00001FFFU 179 #define LRFDS2R_STOP_ADDR_S 0U 180 #define LRFDS2R_STOP_ADDR_ALLONES 0x00001FFFU 181 #define LRFDS2R_STOP_ADDR_ALLZEROS 0x00000000U 182 183 //***************************************************************************** 184 // 185 // Register: LRFDS2R_O_STAT 186 // 187 //***************************************************************************** 188 // Field: [27:16] ADDRCNT 189 // 190 // Current address counter value 191 // ENUMs: 192 // ALLONES All the bits are 1 193 // ALLZEROS All the bits are 0 194 #define LRFDS2R_STAT_ADDRCNT_W 12U 195 #define LRFDS2R_STAT_ADDRCNT_M 0x0FFF0000U 196 #define LRFDS2R_STAT_ADDRCNT_S 16U 197 #define LRFDS2R_STAT_ADDRCNT_ALLONES 0x0FFF0000U 198 #define LRFDS2R_STAT_ADDRCNT_ALLZEROS 0x00000000U 199 200 // Field: [0] RUNNING 201 // 202 // S2R running status 203 // ENUMs: 204 // TRUE Running 205 // FALSE Not running 206 #define LRFDS2R_STAT_RUNNING 0x00000001U 207 #define LRFDS2R_STAT_RUNNING_M 0x00000001U 208 #define LRFDS2R_STAT_RUNNING_S 0U 209 #define LRFDS2R_STAT_RUNNING_TRUE 0x00000001U 210 #define LRFDS2R_STAT_RUNNING_FALSE 0x00000000U 211 212 //***************************************************************************** 213 // 214 // Register: LRFDS2R_O_TRIG 215 // 216 //***************************************************************************** 217 // Field: [0] TRIG 218 // 219 // Trigger a new sample capture (or arm it if the trigger mode is trigger on 220 // event) 221 // ENUMs: 222 // ARM Trigger capture or arm module 223 // NO_EFFECT No effect 224 #define LRFDS2R_TRIG_TRIG 0x00000001U 225 #define LRFDS2R_TRIG_TRIG_M 0x00000001U 226 #define LRFDS2R_TRIG_TRIG_S 0U 227 #define LRFDS2R_TRIG_TRIG_ARM 0x00000001U 228 #define LRFDS2R_TRIG_TRIG_NO_EFFECT 0x00000000U 229 230 231 #endif // __LRFDS2R__ 232
