1 /****************************************************************************** 2 * Filename: hw_lrfdrfe_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_LRFDRFE_H__ 34 #define __HW_LRFDRFE_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // LRFDRFE component 40 // 41 //***************************************************************************** 42 // RF Engine Enable Register 43 #define LRFDRFE_O_ENABLE 0x00000000U 44 45 // RFE Program Source Select Register 46 #define LRFDRFE_O_FWSRC 0x00000004U 47 48 // RF Engine Initialization Register 49 #define LRFDRFE_O_INIT 0x00000008U 50 51 // RF Engine Power-down Register 52 #define LRFDRFE_O_PDREQ 0x0000000CU 53 54 // RFE Event Flag Register 0 55 #define LRFDRFE_O_EVT0 0x00000010U 56 57 // RFE Event Flag Register 1 58 #define LRFDRFE_O_EVT1 0x00000014U 59 60 // RFE Event Mask Register 0 61 #define LRFDRFE_O_EVTMSK0 0x00000018U 62 63 // RFE Event Mask Register 1 64 #define LRFDRFE_O_EVTMSK1 0x0000001CU 65 66 // RFE Event Clear Register 0 67 #define LRFDRFE_O_EVTCLR0 0x00000020U 68 69 // RFE Event Clear Register 1 70 #define LRFDRFE_O_EVTCLR1 0x00000024U 71 72 // Status of the HFXT 73 #define LRFDRFE_O_HFXTSTAT 0x00000028U 74 75 // RF state indication 76 #define LRFDRFE_O_RFSTATE 0x00000030U 77 78 // RFE API Command Register 79 #define LRFDRFE_O_API 0x00000048U 80 81 // RFE Command Parameter 0 82 #define LRFDRFE_O_CMDPAR0 0x0000004CU 83 84 // RFE Command Parameter 1 85 #define LRFDRFE_O_CMDPAR1 0x00000050U 86 87 // RFE Command Status and Message Box Register 88 #define LRFDRFE_O_MSGBOX 0x00000054U 89 90 // RFE-to-MCE Send Data Register 91 #define LRFDRFE_O_MCEDATOUT0 0x00000058U 92 93 // MCE-to-RFE Receive Data Register 94 #define LRFDRFE_O_MCEDATIN0 0x0000005CU 95 96 // RFE-to-MCE Send Command Register 97 #define LRFDRFE_O_MCECMDOUT 0x00000060U 98 99 // MCE-to-RFE Receive Command Register 100 #define LRFDRFE_O_MCECMDIN 0x00000064U 101 102 // RFE-to-PBE Send Data Register 103 #define LRFDRFE_O_PBEDATOUT0 0x00000068U 104 105 // PBE-to-RFE Receive Data Register 106 #define LRFDRFE_O_PBEDATIN0 0x0000006CU 107 108 // RFE-to-PBE Send Command Register 109 #define LRFDRFE_O_PBECMDOUT 0x00000070U 110 111 // PBE-to-RFE Receive Command Register 112 #define LRFDRFE_O_PBECMDIN 0x00000074U 113 114 // RFE FW Strobe Register 115 #define LRFDRFE_O_STRB 0x00000078U 116 117 // Controls automatic comparison of magnitude with threshold 118 #define LRFDRFE_O_MAGNTHRCFG 0x00000080U 119 120 // Threshold to compare the magnacc amplitude with, which accumulator is used 121 // in the compare is controled by MAGNTHRCFG 122 #define LRFDRFE_O_MAGNTHR 0x00000084U 123 124 // RSSI Offset Adjustment Register 125 #define LRFDRFE_O_RSSIOFFSET 0x00000088U 126 127 // Gain Control Register 128 #define LRFDRFE_O_GAINCTL 0x0000008CU 129 130 // Magnitude estimator 0 control register 131 #define LRFDRFE_O_MAGNCTL0 0x00000090U 132 133 // Magnitude estimator 1 control register 134 #define LRFDRFE_O_MAGNCTL1 0x00000094U 135 136 // Spare Value 137 #define LRFDRFE_O_SPARE0 0x00000098U 138 139 // Spare Value 140 #define LRFDRFE_O_SPARE1 0x0000009CU 141 142 // Spare Value 143 #define LRFDRFE_O_SPARE2 0x000000A0U 144 145 // Spare Value 146 #define LRFDRFE_O_SPARE3 0x000000A4U 147 148 // Spare Value 149 #define LRFDRFE_O_SPARE4 0x000000A8U 150 151 // Spare Value 152 #define LRFDRFE_O_SPARE5 0x000000ACU 153 154 // LNA control 155 #define LRFDRFE_O_LNA 0x000000B0U 156 157 // IFAMPRFLDO control 158 #define LRFDRFE_O_IFAMPRFLDO 0x000000B4U 159 160 // PA control register 161 #define LRFDRFE_O_PA0 0x000000B8U 162 163 // PA control register 164 #define LRFDRFE_O_PA1 0x000000BCU 165 166 // ULNA control, TRX only 167 #define LRFDRFE_O_ULNA 0x000000C0U 168 169 // IFADC0 configuration register 170 #define LRFDRFE_O_IFADC0 0x000000C4U 171 172 // IFADC configuration register 173 #define LRFDRFE_O_IFADC1 0x000000C8U 174 175 // IFADC configuration register 176 #define LRFDRFE_O_IFADCLF 0x000000CCU 177 178 // IFADC configuration register 179 #define LRFDRFE_O_IFADCQUANT 0x000000D0U 180 181 // IFADC configuration register 182 #define LRFDRFE_O_IFADCALDO 0x000000D4U 183 184 // IFADCLDO configuration register 185 #define LRFDRFE_O_IFADCDLDO 0x000000D8U 186 187 // IFADCTST configuration register 188 #define LRFDRFE_O_IFADCTST 0x000000DCU 189 190 // Analog test register 191 #define LRFDRFE_O_ATSTREFL 0x000000E0U 192 193 // Analog test register 194 #define LRFDRFE_O_ATSTREFH 0x000000E4U 195 196 // DCO Control 197 #define LRFDRFE_O_DCO 0x000000E8U 198 199 // Divider Control 200 #define LRFDRFE_O_DIV 0x000000ECU 201 202 // LDO control 203 #define LRFDRFE_O_DIVLDO 0x000000F0U 204 205 // LDO control 206 #define LRFDRFE_O_TDCLDO 0x000000F4U 207 208 // LDO control 209 #define LRFDRFE_O_DCOLDO0 0x000000F8U 210 211 // LDO control 212 #define LRFDRFE_O_DCOLDO1 0x000000FCU 213 214 // Predivider configuration 215 #define LRFDRFE_O_PRE0 0x00000100U 216 217 // Predivider configuration 218 #define LRFDRFE_O_PRE1 0x00000104U 219 220 // Predivider configuration 221 #define LRFDRFE_O_PRE2 0x00000108U 222 223 // Predivider configuration 224 #define LRFDRFE_O_PRE3 0x0000010CU 225 226 // Calibration Configuration 0 227 #define LRFDRFE_O_CAL0 0x00000110U 228 229 // Calibration Configuration 1 230 #define LRFDRFE_O_CAL1 0x00000114U 231 232 // Calibration Configuration 2 233 #define LRFDRFE_O_CAL2 0x00000118U 234 235 // Calibration Configuration 3 236 #define LRFDRFE_O_CAL3 0x0000011CU 237 238 // SDM and Delay Configuration 239 #define LRFDRFE_O_MISC0 0x00000120U 240 241 // SDM and Delay Configuration 242 #define LRFDRFE_O_MISC1 0x00000124U 243 244 // Loop Filter Configuration 245 #define LRFDRFE_O_LF0 0x00000128U 246 247 // Loop Filter Configuration 248 #define LRFDRFE_O_LF1 0x0000012CU 249 250 // Phase Configuration 251 #define LRFDRFE_O_PHEDISC 0x00000130U 252 253 // Phase Configuration 254 #define LRFDRFE_O_PHINIT 0x00000134U 255 256 // PLL Monitor Configuration 257 #define LRFDRFE_O_PLLMON0 0x00000138U 258 259 // PLL Monitor Configuration 260 #define LRFDRFE_O_PLLMON1 0x0000013CU 261 262 // Modulator Configuration 263 #define LRFDRFE_O_MOD0 0x00000140U 264 265 // Modulator Configuration 266 #define LRFDRFE_O_MOD1 0x00000144U 267 268 // Digital TX Configuration 0 269 #define LRFDRFE_O_DTX0 0x00000148U 270 271 // Digital TX Configuration 1 272 #define LRFDRFE_O_DTX1 0x0000014CU 273 274 // Digital TX Configuration 2 275 #define LRFDRFE_O_DTX2 0x00000150U 276 277 // Digital TX Configuration 3 278 #define LRFDRFE_O_DTX3 0x00000154U 279 280 // Digital TX Configuration 4 281 #define LRFDRFE_O_DTX4 0x00000158U 282 283 // Digital TX Configuration 5 284 #define LRFDRFE_O_DTX5 0x0000015CU 285 286 // Digital TX Configuration 6 287 #define LRFDRFE_O_DTX6 0x00000160U 288 289 // Digital TX Configuration 7 290 #define LRFDRFE_O_DTX7 0x00000164U 291 292 // Digital TX Configuration 8 293 #define LRFDRFE_O_DTX8 0x00000168U 294 295 // Digital TX Configuration 9 296 #define LRFDRFE_O_DTX9 0x0000016CU 297 298 // Digital TX Configuration 10 299 #define LRFDRFE_O_DTX10 0x00000170U 300 301 // Digital TX Configuration 11 302 #define LRFDRFE_O_DTX11 0x00000174U 303 304 // PLL M0 305 #define LRFDRFE_O_PLLM0L 0x00000178U 306 307 // PLL M0 308 #define LRFDRFE_O_PLLM0H 0x0000017CU 309 310 // PLL M1 311 #define LRFDRFE_O_PLLM1L 0x00000180U 312 313 // PLL M1 314 #define LRFDRFE_O_PLLM1H 0x00000184U 315 316 // Calibration M 317 #define LRFDRFE_O_CALMCRS 0x00000188U 318 319 // Calibration M 320 #define LRFDRFE_O_CALMMID 0x0000018CU 321 322 // REFCLK Prescaler Load Value 323 #define LRFDRFE_O_REFDIV 0x00000190U 324 325 // DLO control register 0 326 #define LRFDRFE_O_DLOCTL0 0x00000198U 327 328 // DLO control register 1 329 #define LRFDRFE_O_DLOCTL1 0x000001A0U 330 331 // DCO Override 332 #define LRFDRFE_O_DCOOVR0 0x000001A8U 333 334 // DCO Override 335 #define LRFDRFE_O_DCOOVR1 0x000001ACU 336 337 // Data test 338 #define LRFDRFE_O_DTST 0x000001B0U 339 340 // FSM and IRQ flags 341 #define LRFDRFE_O_DLOEV 0x000001B4U 342 343 // DTST read 344 #define LRFDRFE_O_DTSTRD 0x000001B8U 345 346 // DCO frequency span 347 #define LRFDRFE_O_FDCOSPANLSB 0x000001BCU 348 349 // DCO frequency span 350 #define LRFDRFE_O_FDCOSPANMSB 0x000001C0U 351 352 // TDC Calibration 353 #define LRFDRFE_O_TDCCAL 0x000001C4U 354 355 // Calibration Code 356 #define LRFDRFE_O_CALRES 0x000001C8U 357 358 // RFE Direct GPI Status 359 #define LRFDRFE_O_GPI 0x000001CCU 360 361 // Math accellerator input value 362 #define LRFDRFE_O_MATHACCELIN 0x000001D0U 363 364 // Lin2Log output register 365 #define LRFDRFE_O_LIN2LOGOUT 0x000001D4U 366 367 // Divide by three output register 368 #define LRFDRFE_O_DIVBY3OUT 0x000001D8U 369 370 // RFE Timer and Counter Control Register 371 #define LRFDRFE_O_TIMCTL 0x000001DCU 372 373 // RFE Counter Increment Configuration 374 #define LRFDRFE_O_TIMINC 0x000001E0U 375 376 // RFE Timer/Counter Period Configuration 377 #define LRFDRFE_O_TIMPER 0x000001E4U 378 379 // RFE Counter Value 380 #define LRFDRFE_O_TIMCNT 0x000001E8U 381 382 // RFE Counter Capture Value 383 #define LRFDRFE_O_TIMCAPT 0x000001ECU 384 385 // RFE Tracer Send Trigger Register 386 #define LRFDRFE_O_TRCCTRL 0x000001F0U 387 388 // RFE Tracer Status Register 389 #define LRFDRFE_O_TRCSTAT 0x000001F4U 390 391 // RFE Tracer Commmand Register 392 #define LRFDRFE_O_TRCCMD 0x000001F8U 393 394 // RFE Tracer Command Parameter Register 0 395 #define LRFDRFE_O_TRCPAR0 0x000001FCU 396 397 // RFE Tracer Command Parameter Register 1 398 #define LRFDRFE_O_TRCPAR1 0x00000200U 399 400 // RFE Direct GPO control register 401 #define LRFDRFE_O_GPOCTL 0x00000204U 402 403 // Analog Isolation Control 404 #define LRFDRFE_O_ANAISOCTL 0x00000208U 405 406 // Divider Control 407 #define LRFDRFE_O_DIVCTL 0x0000020CU 408 409 // RX Frontend control register 410 #define LRFDRFE_O_RXCTRL 0x00000210U 411 412 // Magnitude estimator 0 accumulator value 413 #define LRFDRFE_O_MAGNACC0 0x00000214U 414 415 // Magnitude estimator 1 accumulator value 416 #define LRFDRFE_O_MAGNACC1 0x00000218U 417 418 // RSSI Value Register 419 #define LRFDRFE_O_RSSI 0x0000021CU 420 421 // RSSI Maximum Value Register 422 #define LRFDRFE_O_RSSIMAX 0x00000220U 423 424 // RF front-end gain value 425 #define LRFDRFE_O_RFGAIN 0x00000224U 426 427 // IFADC status 428 #define LRFDRFE_O_IFADCSTAT 0x00000228U 429 430 // Serial Divider Status Register 431 #define LRFDRFE_O_DIVSTA 0x0000022CU 432 433 // Serial Divider Dividend Register 434 #define LRFDRFE_O_DIVIDENDL 0x00000230U 435 436 // Serial Divider Dividend Register 437 #define LRFDRFE_O_DIVIDENDH 0x00000234U 438 439 // Serial Divider Divisor Register 440 #define LRFDRFE_O_DIVISORL 0x00000238U 441 442 // Serial Divider Divisor Register 443 #define LRFDRFE_O_DIVISORH 0x0000023CU 444 445 // Serial Divider Quotient Register 446 #define LRFDRFE_O_QUOTIENTL 0x00000240U 447 448 // Serial Divider Quotient Register 449 #define LRFDRFE_O_QUOTIENTH 0x00000244U 450 451 // Product of DIVISORL_VAL_LSB and DIVISORH_VAL_MSB 452 #define LRFDRFE_O_PRODUCTL 0x00000248U 453 454 // Product of DIVISORL_VAL_LSB and DIVISORH_VAL_MSB 455 #define LRFDRFE_O_PRODUCTH 0x0000024CU 456 457 // Serial Multiplier Status Register 458 #define LRFDRFE_O_MULTSTA 0x00000250U 459 460 // Serial Multiplier Control Register 461 #define LRFDRFE_O_MULTCFG 0x00000258U 462 463 //***************************************************************************** 464 // 465 // Register: LRFDRFE_O_ENABLE 466 // 467 //***************************************************************************** 468 // Field: [3] ACC1 469 // 470 // Enables the Magnitude Accumulator 1 471 // ENUMs: 472 // EN Enable 473 // DIS Disable 474 #define LRFDRFE_ENABLE_ACC1 0x00000008U 475 #define LRFDRFE_ENABLE_ACC1_M 0x00000008U 476 #define LRFDRFE_ENABLE_ACC1_S 3U 477 #define LRFDRFE_ENABLE_ACC1_EN 0x00000008U 478 #define LRFDRFE_ENABLE_ACC1_DIS 0x00000000U 479 480 // Field: [2] ACC0 481 // 482 // Enables the Magnitude Accumulator 0 483 // ENUMs: 484 // EN Enable 485 // DIS Disable 486 #define LRFDRFE_ENABLE_ACC0 0x00000004U 487 #define LRFDRFE_ENABLE_ACC0_M 0x00000004U 488 #define LRFDRFE_ENABLE_ACC0_S 2U 489 #define LRFDRFE_ENABLE_ACC0_EN 0x00000004U 490 #define LRFDRFE_ENABLE_ACC0_DIS 0x00000000U 491 492 // Field: [1] LOCTIM 493 // 494 // Enables the Local timer 495 // ENUMs: 496 // EN Enable 497 // DIS Disable 498 #define LRFDRFE_ENABLE_LOCTIM 0x00000002U 499 #define LRFDRFE_ENABLE_LOCTIM_M 0x00000002U 500 #define LRFDRFE_ENABLE_LOCTIM_S 1U 501 #define LRFDRFE_ENABLE_LOCTIM_EN 0x00000002U 502 #define LRFDRFE_ENABLE_LOCTIM_DIS 0x00000000U 503 504 // Field: [0] TOPSM 505 // 506 // Enables the TOPsm (RFE) 507 // ENUMs: 508 // EN Enable 509 // DIS Disable 510 #define LRFDRFE_ENABLE_TOPSM 0x00000001U 511 #define LRFDRFE_ENABLE_TOPSM_M 0x00000001U 512 #define LRFDRFE_ENABLE_TOPSM_S 0U 513 #define LRFDRFE_ENABLE_TOPSM_EN 0x00000001U 514 #define LRFDRFE_ENABLE_TOPSM_DIS 0x00000000U 515 516 //***************************************************************************** 517 // 518 // Register: LRFDRFE_O_FWSRC 519 // 520 //***************************************************************************** 521 // Field: [2] DATARAM 522 // 523 // Selects RAM to use for data storage 524 // ENUMs: 525 // S2RRAM Use S2RRAM for data 526 // RFERAM Use RFERAM for data 527 #define LRFDRFE_FWSRC_DATARAM 0x00000004U 528 #define LRFDRFE_FWSRC_DATARAM_M 0x00000004U 529 #define LRFDRFE_FWSRC_DATARAM_S 2U 530 #define LRFDRFE_FWSRC_DATARAM_S2RRAM 0x00000004U 531 #define LRFDRFE_FWSRC_DATARAM_RFERAM 0x00000000U 532 533 // Field: [1] FWRAM 534 // 535 // Selects RAM to use for program memory 536 // ENUMs: 537 // S2RRAM Run code from S2RRAM 538 // RFERAM Run code from RFERAM 539 #define LRFDRFE_FWSRC_FWRAM 0x00000002U 540 #define LRFDRFE_FWSRC_FWRAM_M 0x00000002U 541 #define LRFDRFE_FWSRC_FWRAM_S 1U 542 #define LRFDRFE_FWSRC_FWRAM_S2RRAM 0x00000002U 543 #define LRFDRFE_FWSRC_FWRAM_RFERAM 0x00000000U 544 545 // Field: [0] BANK 546 // 547 // Selects 2K bank within the program memory as FW source. 548 // This controls MSB of address line towards program memory. 549 // ENUMs: 550 // ONE Run code from bank 1 551 // ZERO Run code from bank 0 552 #define LRFDRFE_FWSRC_BANK 0x00000001U 553 #define LRFDRFE_FWSRC_BANK_M 0x00000001U 554 #define LRFDRFE_FWSRC_BANK_S 0U 555 #define LRFDRFE_FWSRC_BANK_ONE 0x00000001U 556 #define LRFDRFE_FWSRC_BANK_ZERO 0x00000000U 557 558 //***************************************************************************** 559 // 560 // Register: LRFDRFE_O_INIT 561 // 562 //***************************************************************************** 563 // Field: [3] ACC1 564 // 565 // Synchronous reset to magnitude accumulator 1 566 // ENUMs: 567 // RESET Reset module 568 // NO_EFFECT No effect 569 #define LRFDRFE_INIT_ACC1 0x00000008U 570 #define LRFDRFE_INIT_ACC1_M 0x00000008U 571 #define LRFDRFE_INIT_ACC1_S 3U 572 #define LRFDRFE_INIT_ACC1_RESET 0x00000008U 573 #define LRFDRFE_INIT_ACC1_NO_EFFECT 0x00000000U 574 575 // Field: [2] ACC0 576 // 577 // Synchronous reset to magnitude accumulator 0 578 // ENUMs: 579 // RESET Reset module 580 // NO_EFFECT No effect 581 #define LRFDRFE_INIT_ACC0 0x00000004U 582 #define LRFDRFE_INIT_ACC0_M 0x00000004U 583 #define LRFDRFE_INIT_ACC0_S 2U 584 #define LRFDRFE_INIT_ACC0_RESET 0x00000004U 585 #define LRFDRFE_INIT_ACC0_NO_EFFECT 0x00000000U 586 587 // Field: [1] LOCTIM 588 // 589 // Synchronous reset to local timer 590 // ENUMs: 591 // RESET Reset module 592 // NO_EFFECT No effect 593 #define LRFDRFE_INIT_LOCTIM 0x00000002U 594 #define LRFDRFE_INIT_LOCTIM_M 0x00000002U 595 #define LRFDRFE_INIT_LOCTIM_S 1U 596 #define LRFDRFE_INIT_LOCTIM_RESET 0x00000002U 597 #define LRFDRFE_INIT_LOCTIM_NO_EFFECT 0x00000000U 598 599 // Field: [0] TOPSM 600 // 601 // Synchronous reset to TOPsm (RFE) 602 // ENUMs: 603 // RESET Reset module 604 // NO_EFFECT No effect 605 #define LRFDRFE_INIT_TOPSM 0x00000001U 606 #define LRFDRFE_INIT_TOPSM_M 0x00000001U 607 #define LRFDRFE_INIT_TOPSM_S 0U 608 #define LRFDRFE_INIT_TOPSM_RESET 0x00000001U 609 #define LRFDRFE_INIT_TOPSM_NO_EFFECT 0x00000000U 610 611 //***************************************************************************** 612 // 613 // Register: LRFDRFE_O_PDREQ 614 // 615 //***************************************************************************** 616 // Field: [0] TOPSMPDREQ 617 // 618 // Requests power down for TOPsm core. If the TOPsm has an ongoing memory 619 // access, the hardware will safely gate the clock after the transaction has 620 // completed. 621 // ENUMs: 622 // ONE The bit is 1 623 // ZERO The bit is 0 624 #define LRFDRFE_PDREQ_TOPSMPDREQ 0x00000001U 625 #define LRFDRFE_PDREQ_TOPSMPDREQ_M 0x00000001U 626 #define LRFDRFE_PDREQ_TOPSMPDREQ_S 0U 627 #define LRFDRFE_PDREQ_TOPSMPDREQ_ONE 0x00000001U 628 #define LRFDRFE_PDREQ_TOPSMPDREQ_ZERO 0x00000000U 629 630 //***************************************************************************** 631 // 632 // Register: LRFDRFE_O_EVT0 633 // 634 //***************************************************************************** 635 // Field: [14] MAGNTHR 636 // 637 // Magnitude accumulator amplitude is above MAGNTHR theshold 638 // ENUMs: 639 // ONE The bit is 1 640 // ZERO The bit is 0 641 #define LRFDRFE_EVT0_MAGNTHR 0x00004000U 642 #define LRFDRFE_EVT0_MAGNTHR_M 0x00004000U 643 #define LRFDRFE_EVT0_MAGNTHR_S 14U 644 #define LRFDRFE_EVT0_MAGNTHR_ONE 0x00004000U 645 #define LRFDRFE_EVT0_MAGNTHR_ZERO 0x00000000U 646 647 // Field: [13] S2RSTOP 648 // 649 // S2R has written to LRFDS2R:STOP.ADDR 650 // ENUMs: 651 // ONE The bit is 1 652 // ZERO The bit is 0 653 #define LRFDRFE_EVT0_S2RSTOP 0x00002000U 654 #define LRFDRFE_EVT0_S2RSTOP_M 0x00002000U 655 #define LRFDRFE_EVT0_S2RSTOP_S 13U 656 #define LRFDRFE_EVT0_S2RSTOP_ONE 0x00002000U 657 #define LRFDRFE_EVT0_S2RSTOP_ZERO 0x00000000U 658 659 // Field: [12] SYSTCMP2 660 // 661 // Systimer compare event 662 // ENUMs: 663 // ONE The bit is 1 664 // ZERO The bit is 0 665 #define LRFDRFE_EVT0_SYSTCMP2 0x00001000U 666 #define LRFDRFE_EVT0_SYSTCMP2_M 0x00001000U 667 #define LRFDRFE_EVT0_SYSTCMP2_S 12U 668 #define LRFDRFE_EVT0_SYSTCMP2_ONE 0x00001000U 669 #define LRFDRFE_EVT0_SYSTCMP2_ZERO 0x00000000U 670 671 // Field: [11] SYSTCMP1 672 // 673 // Systimer compare event 674 // ENUMs: 675 // ONE The bit is 1 676 // ZERO The bit is 0 677 #define LRFDRFE_EVT0_SYSTCMP1 0x00000800U 678 #define LRFDRFE_EVT0_SYSTCMP1_M 0x00000800U 679 #define LRFDRFE_EVT0_SYSTCMP1_S 11U 680 #define LRFDRFE_EVT0_SYSTCMP1_ONE 0x00000800U 681 #define LRFDRFE_EVT0_SYSTCMP1_ZERO 0x00000000U 682 683 // Field: [10] SYSTCMP0 684 // 685 // Systimer compare event 686 // ENUMs: 687 // ONE The bit is 1 688 // ZERO The bit is 0 689 #define LRFDRFE_EVT0_SYSTCMP0 0x00000400U 690 #define LRFDRFE_EVT0_SYSTCMP0_M 0x00000400U 691 #define LRFDRFE_EVT0_SYSTCMP0_S 10U 692 #define LRFDRFE_EVT0_SYSTCMP0_ONE 0x00000400U 693 #define LRFDRFE_EVT0_SYSTCMP0_ZERO 0x00000000U 694 695 // Field: [9] PBERFEDAT 696 // 697 // New data from PBE in PBEDATIN0 698 // ENUMs: 699 // ONE The bit is 1 700 // ZERO The bit is 0 701 #define LRFDRFE_EVT0_PBERFEDAT 0x00000200U 702 #define LRFDRFE_EVT0_PBERFEDAT_M 0x00000200U 703 #define LRFDRFE_EVT0_PBERFEDAT_S 9U 704 #define LRFDRFE_EVT0_PBERFEDAT_ONE 0x00000200U 705 #define LRFDRFE_EVT0_PBERFEDAT_ZERO 0x00000000U 706 707 // Field: [8] MDMRFEDAT 708 // 709 // New data from MCE in MCEDATIN0 710 // ENUMs: 711 // ONE The bit is 1 712 // ZERO The bit is 0 713 #define LRFDRFE_EVT0_MDMRFEDAT 0x00000100U 714 #define LRFDRFE_EVT0_MDMRFEDAT_M 0x00000100U 715 #define LRFDRFE_EVT0_MDMRFEDAT_S 8U 716 #define LRFDRFE_EVT0_MDMRFEDAT_ONE 0x00000100U 717 #define LRFDRFE_EVT0_MDMRFEDAT_ZERO 0x00000000U 718 719 // Field: [7] DLO 720 // 721 // Event from DLO state machine 722 // ENUMs: 723 // ONE The bit is 1 724 // ZERO The bit is 0 725 #define LRFDRFE_EVT0_DLO 0x00000080U 726 #define LRFDRFE_EVT0_DLO_M 0x00000080U 727 #define LRFDRFE_EVT0_DLO_S 7U 728 #define LRFDRFE_EVT0_DLO_ONE 0x00000080U 729 #define LRFDRFE_EVT0_DLO_ZERO 0x00000000U 730 731 // Field: [6] PBECMD 732 // 733 // New command from PBE in PBECMDIN 734 // ENUMs: 735 // ONE The bit is 1 736 // ZERO The bit is 0 737 #define LRFDRFE_EVT0_PBECMD 0x00000040U 738 #define LRFDRFE_EVT0_PBECMD_M 0x00000040U 739 #define LRFDRFE_EVT0_PBECMD_S 6U 740 #define LRFDRFE_EVT0_PBECMD_ONE 0x00000040U 741 #define LRFDRFE_EVT0_PBECMD_ZERO 0x00000000U 742 743 // Field: [5] COUNTER 744 // 745 // Counter value reached in local timer 746 // ENUMs: 747 // ONE The bit is 1 748 // ZERO The bit is 0 749 #define LRFDRFE_EVT0_COUNTER 0x00000020U 750 #define LRFDRFE_EVT0_COUNTER_M 0x00000020U 751 #define LRFDRFE_EVT0_COUNTER_S 5U 752 #define LRFDRFE_EVT0_COUNTER_ONE 0x00000020U 753 #define LRFDRFE_EVT0_COUNTER_ZERO 0x00000000U 754 755 // Field: [4] MDMCMD 756 // 757 // New command from MCE in MCECMDIN 758 // ENUMs: 759 // ONE The bit is 1 760 // ZERO The bit is 0 761 #define LRFDRFE_EVT0_MDMCMD 0x00000010U 762 #define LRFDRFE_EVT0_MDMCMD_M 0x00000010U 763 #define LRFDRFE_EVT0_MDMCMD_S 4U 764 #define LRFDRFE_EVT0_MDMCMD_ONE 0x00000010U 765 #define LRFDRFE_EVT0_MDMCMD_ZERO 0x00000000U 766 767 // Field: [3] ACC1 768 // 769 // Accumulation period completed in magnitude accumulator 1 770 // ENUMs: 771 // ONE The bit is 1 772 // ZERO The bit is 0 773 #define LRFDRFE_EVT0_ACC1 0x00000008U 774 #define LRFDRFE_EVT0_ACC1_M 0x00000008U 775 #define LRFDRFE_EVT0_ACC1_S 3U 776 #define LRFDRFE_EVT0_ACC1_ONE 0x00000008U 777 #define LRFDRFE_EVT0_ACC1_ZERO 0x00000000U 778 779 // Field: [2] ACC0 780 // 781 // Accumulation period completed in magnitude accumulator 0 782 // ENUMs: 783 // ONE The bit is 1 784 // ZERO The bit is 0 785 #define LRFDRFE_EVT0_ACC0 0x00000004U 786 #define LRFDRFE_EVT0_ACC0_M 0x00000004U 787 #define LRFDRFE_EVT0_ACC0_S 2U 788 #define LRFDRFE_EVT0_ACC0_ONE 0x00000004U 789 #define LRFDRFE_EVT0_ACC0_ZERO 0x00000000U 790 791 // Field: [1] TIMER 792 // 793 // Timer period expired in local timer 794 // ENUMs: 795 // ONE The bit is 1 796 // ZERO The bit is 0 797 #define LRFDRFE_EVT0_TIMER 0x00000002U 798 #define LRFDRFE_EVT0_TIMER_M 0x00000002U 799 #define LRFDRFE_EVT0_TIMER_S 1U 800 #define LRFDRFE_EVT0_TIMER_ONE 0x00000002U 801 #define LRFDRFE_EVT0_TIMER_ZERO 0x00000000U 802 803 // Field: [0] RFEAPI 804 // 805 // New RFE API availabe in API 806 // ENUMs: 807 // ONE The bit is 1 808 // ZERO The bit is 0 809 #define LRFDRFE_EVT0_RFEAPI 0x00000001U 810 #define LRFDRFE_EVT0_RFEAPI_M 0x00000001U 811 #define LRFDRFE_EVT0_RFEAPI_S 0U 812 #define LRFDRFE_EVT0_RFEAPI_ONE 0x00000001U 813 #define LRFDRFE_EVT0_RFEAPI_ZERO 0x00000000U 814 815 //***************************************************************************** 816 // 817 // Register: LRFDRFE_O_EVT1 818 // 819 //***************************************************************************** 820 // Field: [13] PREREFCLK 821 // 822 // Prescaled REFCLK event, controlled by DCOCTL0.LOOPUPD 823 // ENUMs: 824 // ONE The bit is 1 825 // ZERO The bit is 0 826 #define LRFDRFE_EVT1_PREREFCLK 0x00002000U 827 #define LRFDRFE_EVT1_PREREFCLK_M 0x00002000U 828 #define LRFDRFE_EVT1_PREREFCLK_S 13U 829 #define LRFDRFE_EVT1_PREREFCLK_ONE 0x00002000U 830 #define LRFDRFE_EVT1_PREREFCLK_ZERO 0x00000000U 831 832 // Field: [12] REFCLK 833 // 834 // REFCLK event from DLO 835 // ENUMs: 836 // ONE The bit is 1 837 // ZERO The bit is 0 838 #define LRFDRFE_EVT1_REFCLK 0x00001000U 839 #define LRFDRFE_EVT1_REFCLK_M 0x00001000U 840 #define LRFDRFE_EVT1_REFCLK_S 12U 841 #define LRFDRFE_EVT1_REFCLK_ONE 0x00001000U 842 #define LRFDRFE_EVT1_REFCLK_ZERO 0x00000000U 843 844 // Field: [11] FBLWTHR 845 // 846 // Finecode below programmed threshold event from DLO state machine 847 // ENUMs: 848 // ONE The bit is 1 849 // ZERO The bit is 0 850 #define LRFDRFE_EVT1_FBLWTHR 0x00000800U 851 #define LRFDRFE_EVT1_FBLWTHR_M 0x00000800U 852 #define LRFDRFE_EVT1_FBLWTHR_S 11U 853 #define LRFDRFE_EVT1_FBLWTHR_ONE 0x00000800U 854 #define LRFDRFE_EVT1_FBLWTHR_ZERO 0x00000000U 855 856 // Field: [10] FABVTHR 857 // 858 // Finecode above programmed threshold event from DLO state machine 859 // ENUMs: 860 // ONE The bit is 1 861 // ZERO The bit is 0 862 #define LRFDRFE_EVT1_FABVTHR 0x00000400U 863 #define LRFDRFE_EVT1_FABVTHR_M 0x00000400U 864 #define LRFDRFE_EVT1_FABVTHR_S 10U 865 #define LRFDRFE_EVT1_FABVTHR_ONE 0x00000400U 866 #define LRFDRFE_EVT1_FABVTHR_ZERO 0x00000000U 867 868 // Field: [9] LOCK 869 // 870 // Lock event from DLO state machine 871 // ENUMs: 872 // ONE The bit is 1 873 // ZERO The bit is 0 874 #define LRFDRFE_EVT1_LOCK 0x00000200U 875 #define LRFDRFE_EVT1_LOCK_M 0x00000200U 876 #define LRFDRFE_EVT1_LOCK_S 9U 877 #define LRFDRFE_EVT1_LOCK_ONE 0x00000200U 878 #define LRFDRFE_EVT1_LOCK_ZERO 0x00000000U 879 880 // Field: [8] LOL 881 // 882 // Loss of lock event from DLO state machine 883 // ENUMs: 884 // ONE The bit is 1 885 // ZERO The bit is 0 886 #define LRFDRFE_EVT1_LOL 0x00000100U 887 #define LRFDRFE_EVT1_LOL_M 0x00000100U 888 #define LRFDRFE_EVT1_LOL_S 8U 889 #define LRFDRFE_EVT1_LOL_ONE 0x00000100U 890 #define LRFDRFE_EVT1_LOL_ZERO 0x00000000U 891 892 // Field: [7] GPI7 893 // 894 // External input event line GPI7 from IOC 895 // ENUMs: 896 // ONE The bit is 1 897 // ZERO The bit is 0 898 #define LRFDRFE_EVT1_GPI7 0x00000080U 899 #define LRFDRFE_EVT1_GPI7_M 0x00000080U 900 #define LRFDRFE_EVT1_GPI7_S 7U 901 #define LRFDRFE_EVT1_GPI7_ONE 0x00000080U 902 #define LRFDRFE_EVT1_GPI7_ZERO 0x00000000U 903 904 // Field: [6] GPI6 905 // 906 // External input event line GPI6 from IOC 907 // ENUMs: 908 // ONE The bit is 1 909 // ZERO The bit is 0 910 #define LRFDRFE_EVT1_GPI6 0x00000040U 911 #define LRFDRFE_EVT1_GPI6_M 0x00000040U 912 #define LRFDRFE_EVT1_GPI6_S 6U 913 #define LRFDRFE_EVT1_GPI6_ONE 0x00000040U 914 #define LRFDRFE_EVT1_GPI6_ZERO 0x00000000U 915 916 // Field: [5] GPI5 917 // 918 // External input event line GPI5 from IOC 919 // ENUMs: 920 // ONE The bit is 1 921 // ZERO The bit is 0 922 #define LRFDRFE_EVT1_GPI5 0x00000020U 923 #define LRFDRFE_EVT1_GPI5_M 0x00000020U 924 #define LRFDRFE_EVT1_GPI5_S 5U 925 #define LRFDRFE_EVT1_GPI5_ONE 0x00000020U 926 #define LRFDRFE_EVT1_GPI5_ZERO 0x00000000U 927 928 // Field: [4] GPI4 929 // 930 // External input event line GPI4 from IOC 931 // ENUMs: 932 // ONE The bit is 1 933 // ZERO The bit is 0 934 #define LRFDRFE_EVT1_GPI4 0x00000010U 935 #define LRFDRFE_EVT1_GPI4_M 0x00000010U 936 #define LRFDRFE_EVT1_GPI4_S 4U 937 #define LRFDRFE_EVT1_GPI4_ONE 0x00000010U 938 #define LRFDRFE_EVT1_GPI4_ZERO 0x00000000U 939 940 // Field: [3] GPI3 941 // 942 // External input event line GPI3 from IOC 943 // ENUMs: 944 // ONE The bit is 1 945 // ZERO The bit is 0 946 #define LRFDRFE_EVT1_GPI3 0x00000008U 947 #define LRFDRFE_EVT1_GPI3_M 0x00000008U 948 #define LRFDRFE_EVT1_GPI3_S 3U 949 #define LRFDRFE_EVT1_GPI3_ONE 0x00000008U 950 #define LRFDRFE_EVT1_GPI3_ZERO 0x00000000U 951 952 // Field: [2] GPI2 953 // 954 // External input event line GPI2 from IOC 955 // ENUMs: 956 // ONE The bit is 1 957 // ZERO The bit is 0 958 #define LRFDRFE_EVT1_GPI2 0x00000004U 959 #define LRFDRFE_EVT1_GPI2_M 0x00000004U 960 #define LRFDRFE_EVT1_GPI2_S 2U 961 #define LRFDRFE_EVT1_GPI2_ONE 0x00000004U 962 #define LRFDRFE_EVT1_GPI2_ZERO 0x00000000U 963 964 // Field: [1] GPI1 965 // 966 // External input event line GPI1 from IOC 967 // ENUMs: 968 // ONE The bit is 1 969 // ZERO The bit is 0 970 #define LRFDRFE_EVT1_GPI1 0x00000002U 971 #define LRFDRFE_EVT1_GPI1_M 0x00000002U 972 #define LRFDRFE_EVT1_GPI1_S 1U 973 #define LRFDRFE_EVT1_GPI1_ONE 0x00000002U 974 #define LRFDRFE_EVT1_GPI1_ZERO 0x00000000U 975 976 // Field: [0] GPI0 977 // 978 // External input event line GPI0 from IOC 979 // ENUMs: 980 // ONE The bit is 1 981 // ZERO The bit is 0 982 #define LRFDRFE_EVT1_GPI0 0x00000001U 983 #define LRFDRFE_EVT1_GPI0_M 0x00000001U 984 #define LRFDRFE_EVT1_GPI0_S 0U 985 #define LRFDRFE_EVT1_GPI0_ONE 0x00000001U 986 #define LRFDRFE_EVT1_GPI0_ZERO 0x00000000U 987 988 //***************************************************************************** 989 // 990 // Register: LRFDRFE_O_EVTMSK0 991 // 992 //***************************************************************************** 993 // Field: [14] MAGNTHR 994 // 995 // Enable mask for event EVT0.MAGNTHR 996 // ENUMs: 997 // EN The bit is 1 998 // DIS The bit is 0 999 #define LRFDRFE_EVTMSK0_MAGNTHR 0x00004000U 1000 #define LRFDRFE_EVTMSK0_MAGNTHR_M 0x00004000U 1001 #define LRFDRFE_EVTMSK0_MAGNTHR_S 14U 1002 #define LRFDRFE_EVTMSK0_MAGNTHR_EN 0x00004000U 1003 #define LRFDRFE_EVTMSK0_MAGNTHR_DIS 0x00000000U 1004 1005 // Field: [13] S2RSTOP 1006 // 1007 // Enable mask for event EVT0.S2RSTOP 1008 // ENUMs: 1009 // EN The bit is 1 1010 // DIS The bit is 0 1011 #define LRFDRFE_EVTMSK0_S2RSTOP 0x00002000U 1012 #define LRFDRFE_EVTMSK0_S2RSTOP_M 0x00002000U 1013 #define LRFDRFE_EVTMSK0_S2RSTOP_S 13U 1014 #define LRFDRFE_EVTMSK0_S2RSTOP_EN 0x00002000U 1015 #define LRFDRFE_EVTMSK0_S2RSTOP_DIS 0x00000000U 1016 1017 // Field: [12] SYSTCMP2 1018 // 1019 // Enable mask for event EVT0.SYSTCMP2 1020 // ENUMs: 1021 // EN The bit is 1 1022 // DIS The bit is 0 1023 #define LRFDRFE_EVTMSK0_SYSTCMP2 0x00001000U 1024 #define LRFDRFE_EVTMSK0_SYSTCMP2_M 0x00001000U 1025 #define LRFDRFE_EVTMSK0_SYSTCMP2_S 12U 1026 #define LRFDRFE_EVTMSK0_SYSTCMP2_EN 0x00001000U 1027 #define LRFDRFE_EVTMSK0_SYSTCMP2_DIS 0x00000000U 1028 1029 // Field: [11] SYSTCMP1 1030 // 1031 // Enable mask for event EVT0.SYSTCMP1 1032 // ENUMs: 1033 // EN The bit is 1 1034 // DIS The bit is 0 1035 #define LRFDRFE_EVTMSK0_SYSTCMP1 0x00000800U 1036 #define LRFDRFE_EVTMSK0_SYSTCMP1_M 0x00000800U 1037 #define LRFDRFE_EVTMSK0_SYSTCMP1_S 11U 1038 #define LRFDRFE_EVTMSK0_SYSTCMP1_EN 0x00000800U 1039 #define LRFDRFE_EVTMSK0_SYSTCMP1_DIS 0x00000000U 1040 1041 // Field: [10] SYSTCMP0 1042 // 1043 // Enable mask for event EVT0.SYSTCMP0 1044 // ENUMs: 1045 // EN The bit is 1 1046 // DIS The bit is 0 1047 #define LRFDRFE_EVTMSK0_SYSTCMP0 0x00000400U 1048 #define LRFDRFE_EVTMSK0_SYSTCMP0_M 0x00000400U 1049 #define LRFDRFE_EVTMSK0_SYSTCMP0_S 10U 1050 #define LRFDRFE_EVTMSK0_SYSTCMP0_EN 0x00000400U 1051 #define LRFDRFE_EVTMSK0_SYSTCMP0_DIS 0x00000000U 1052 1053 // Field: [9] PBERFEDAT 1054 // 1055 // Enable mask for event EVT0.PBERFEDAT 1056 // ENUMs: 1057 // EN The bit is 1 1058 // DIS The bit is 0 1059 #define LRFDRFE_EVTMSK0_PBERFEDAT 0x00000200U 1060 #define LRFDRFE_EVTMSK0_PBERFEDAT_M 0x00000200U 1061 #define LRFDRFE_EVTMSK0_PBERFEDAT_S 9U 1062 #define LRFDRFE_EVTMSK0_PBERFEDAT_EN 0x00000200U 1063 #define LRFDRFE_EVTMSK0_PBERFEDAT_DIS 0x00000000U 1064 1065 // Field: [8] MDMRFEDAT 1066 // 1067 // Enable mask for event EVT0.MDMRFEDAT 1068 // ENUMs: 1069 // EN The bit is 1 1070 // DIS The bit is 0 1071 #define LRFDRFE_EVTMSK0_MDMRFEDAT 0x00000100U 1072 #define LRFDRFE_EVTMSK0_MDMRFEDAT_M 0x00000100U 1073 #define LRFDRFE_EVTMSK0_MDMRFEDAT_S 8U 1074 #define LRFDRFE_EVTMSK0_MDMRFEDAT_EN 0x00000100U 1075 #define LRFDRFE_EVTMSK0_MDMRFEDAT_DIS 0x00000000U 1076 1077 // Field: [7] DLO 1078 // 1079 // Enable mask for event EVT0.DLO 1080 // ENUMs: 1081 // EN The bit is 1 1082 // DIS The bit is 0 1083 #define LRFDRFE_EVTMSK0_DLO 0x00000080U 1084 #define LRFDRFE_EVTMSK0_DLO_M 0x00000080U 1085 #define LRFDRFE_EVTMSK0_DLO_S 7U 1086 #define LRFDRFE_EVTMSK0_DLO_EN 0x00000080U 1087 #define LRFDRFE_EVTMSK0_DLO_DIS 0x00000000U 1088 1089 // Field: [6] PBECMD 1090 // 1091 // Enable mask for event EVT0.PBECMD 1092 // ENUMs: 1093 // EN The bit is 1 1094 // DIS The bit is 0 1095 #define LRFDRFE_EVTMSK0_PBECMD 0x00000040U 1096 #define LRFDRFE_EVTMSK0_PBECMD_M 0x00000040U 1097 #define LRFDRFE_EVTMSK0_PBECMD_S 6U 1098 #define LRFDRFE_EVTMSK0_PBECMD_EN 0x00000040U 1099 #define LRFDRFE_EVTMSK0_PBECMD_DIS 0x00000000U 1100 1101 // Field: [5] COUNTER 1102 // 1103 // Enable mask for event EVT0.COUNTER 1104 // ENUMs: 1105 // EN The bit is 1 1106 // DIS The bit is 0 1107 #define LRFDRFE_EVTMSK0_COUNTER 0x00000020U 1108 #define LRFDRFE_EVTMSK0_COUNTER_M 0x00000020U 1109 #define LRFDRFE_EVTMSK0_COUNTER_S 5U 1110 #define LRFDRFE_EVTMSK0_COUNTER_EN 0x00000020U 1111 #define LRFDRFE_EVTMSK0_COUNTER_DIS 0x00000000U 1112 1113 // Field: [4] MDMCMD 1114 // 1115 // Enable mask for event EVT0.MDMCMD 1116 // ENUMs: 1117 // EN The bit is 1 1118 // DIS The bit is 0 1119 #define LRFDRFE_EVTMSK0_MDMCMD 0x00000010U 1120 #define LRFDRFE_EVTMSK0_MDMCMD_M 0x00000010U 1121 #define LRFDRFE_EVTMSK0_MDMCMD_S 4U 1122 #define LRFDRFE_EVTMSK0_MDMCMD_EN 0x00000010U 1123 #define LRFDRFE_EVTMSK0_MDMCMD_DIS 0x00000000U 1124 1125 // Field: [3] ACC1 1126 // 1127 // Enable mask for event EVT0.ACC1 1128 // ENUMs: 1129 // EN The bit is 1 1130 // DIS The bit is 0 1131 #define LRFDRFE_EVTMSK0_ACC1 0x00000008U 1132 #define LRFDRFE_EVTMSK0_ACC1_M 0x00000008U 1133 #define LRFDRFE_EVTMSK0_ACC1_S 3U 1134 #define LRFDRFE_EVTMSK0_ACC1_EN 0x00000008U 1135 #define LRFDRFE_EVTMSK0_ACC1_DIS 0x00000000U 1136 1137 // Field: [2] ACC0 1138 // 1139 // Enable mask for event EVT0.ACC0 1140 // ENUMs: 1141 // EN The bit is 1 1142 // DIS The bit is 0 1143 #define LRFDRFE_EVTMSK0_ACC0 0x00000004U 1144 #define LRFDRFE_EVTMSK0_ACC0_M 0x00000004U 1145 #define LRFDRFE_EVTMSK0_ACC0_S 2U 1146 #define LRFDRFE_EVTMSK0_ACC0_EN 0x00000004U 1147 #define LRFDRFE_EVTMSK0_ACC0_DIS 0x00000000U 1148 1149 // Field: [1] TIMER 1150 // 1151 // Enable mask for event EVT0.TIMER 1152 // ENUMs: 1153 // EN The bit is 1 1154 // DIS The bit is 0 1155 #define LRFDRFE_EVTMSK0_TIMER 0x00000002U 1156 #define LRFDRFE_EVTMSK0_TIMER_M 0x00000002U 1157 #define LRFDRFE_EVTMSK0_TIMER_S 1U 1158 #define LRFDRFE_EVTMSK0_TIMER_EN 0x00000002U 1159 #define LRFDRFE_EVTMSK0_TIMER_DIS 0x00000000U 1160 1161 // Field: [0] RFEAPI 1162 // 1163 // Enable mask for event EVT0.RFEAPI 1164 // ENUMs: 1165 // EN The bit is 1 1166 // DIS The bit is 0 1167 #define LRFDRFE_EVTMSK0_RFEAPI 0x00000001U 1168 #define LRFDRFE_EVTMSK0_RFEAPI_M 0x00000001U 1169 #define LRFDRFE_EVTMSK0_RFEAPI_S 0U 1170 #define LRFDRFE_EVTMSK0_RFEAPI_EN 0x00000001U 1171 #define LRFDRFE_EVTMSK0_RFEAPI_DIS 0x00000000U 1172 1173 //***************************************************************************** 1174 // 1175 // Register: LRFDRFE_O_EVTMSK1 1176 // 1177 //***************************************************************************** 1178 // Field: [13] PREREFCLK 1179 // 1180 // Enable mask for event EVT1.PREREFCLK 1181 // ENUMs: 1182 // EN The bit is 1 1183 // DIS The bit is 0 1184 #define LRFDRFE_EVTMSK1_PREREFCLK 0x00002000U 1185 #define LRFDRFE_EVTMSK1_PREREFCLK_M 0x00002000U 1186 #define LRFDRFE_EVTMSK1_PREREFCLK_S 13U 1187 #define LRFDRFE_EVTMSK1_PREREFCLK_EN 0x00002000U 1188 #define LRFDRFE_EVTMSK1_PREREFCLK_DIS 0x00000000U 1189 1190 // Field: [12] REFCLK 1191 // 1192 // Enable mask for event EVT1.REFCLK 1193 // ENUMs: 1194 // EN The bit is 1 1195 // DIS The bit is 0 1196 #define LRFDRFE_EVTMSK1_REFCLK 0x00001000U 1197 #define LRFDRFE_EVTMSK1_REFCLK_M 0x00001000U 1198 #define LRFDRFE_EVTMSK1_REFCLK_S 12U 1199 #define LRFDRFE_EVTMSK1_REFCLK_EN 0x00001000U 1200 #define LRFDRFE_EVTMSK1_REFCLK_DIS 0x00000000U 1201 1202 // Field: [11] FBLWTHR 1203 // 1204 // Enable mask for event EVT1.FBLWTHR 1205 // ENUMs: 1206 // EN The bit is 1 1207 // DIS The bit is 0 1208 #define LRFDRFE_EVTMSK1_FBLWTHR 0x00000800U 1209 #define LRFDRFE_EVTMSK1_FBLWTHR_M 0x00000800U 1210 #define LRFDRFE_EVTMSK1_FBLWTHR_S 11U 1211 #define LRFDRFE_EVTMSK1_FBLWTHR_EN 0x00000800U 1212 #define LRFDRFE_EVTMSK1_FBLWTHR_DIS 0x00000000U 1213 1214 // Field: [10] FABVTHR 1215 // 1216 // Enable mask for event EVT1.FABVTHR 1217 // ENUMs: 1218 // EN The bit is 1 1219 // DIS The bit is 0 1220 #define LRFDRFE_EVTMSK1_FABVTHR 0x00000400U 1221 #define LRFDRFE_EVTMSK1_FABVTHR_M 0x00000400U 1222 #define LRFDRFE_EVTMSK1_FABVTHR_S 10U 1223 #define LRFDRFE_EVTMSK1_FABVTHR_EN 0x00000400U 1224 #define LRFDRFE_EVTMSK1_FABVTHR_DIS 0x00000000U 1225 1226 // Field: [9] LOCK 1227 // 1228 // Enable mask for event EVT1.LOCK 1229 // ENUMs: 1230 // EN The bit is 1 1231 // DIS The bit is 0 1232 #define LRFDRFE_EVTMSK1_LOCK 0x00000200U 1233 #define LRFDRFE_EVTMSK1_LOCK_M 0x00000200U 1234 #define LRFDRFE_EVTMSK1_LOCK_S 9U 1235 #define LRFDRFE_EVTMSK1_LOCK_EN 0x00000200U 1236 #define LRFDRFE_EVTMSK1_LOCK_DIS 0x00000000U 1237 1238 // Field: [8] LOL 1239 // 1240 // Enable mask for event EVT1.LOL 1241 // ENUMs: 1242 // EN The bit is 1 1243 // DIS The bit is 0 1244 #define LRFDRFE_EVTMSK1_LOL 0x00000100U 1245 #define LRFDRFE_EVTMSK1_LOL_M 0x00000100U 1246 #define LRFDRFE_EVTMSK1_LOL_S 8U 1247 #define LRFDRFE_EVTMSK1_LOL_EN 0x00000100U 1248 #define LRFDRFE_EVTMSK1_LOL_DIS 0x00000000U 1249 1250 // Field: [7] GPI7 1251 // 1252 // Enable mask for event EVT1.GPI7 1253 // ENUMs: 1254 // EN The bit is 1 1255 // DIS The bit is 0 1256 #define LRFDRFE_EVTMSK1_GPI7 0x00000080U 1257 #define LRFDRFE_EVTMSK1_GPI7_M 0x00000080U 1258 #define LRFDRFE_EVTMSK1_GPI7_S 7U 1259 #define LRFDRFE_EVTMSK1_GPI7_EN 0x00000080U 1260 #define LRFDRFE_EVTMSK1_GPI7_DIS 0x00000000U 1261 1262 // Field: [6] GPI6 1263 // 1264 // Enable mask for event EVT1.GPI6 1265 // ENUMs: 1266 // EN The bit is 1 1267 // DIS The bit is 0 1268 #define LRFDRFE_EVTMSK1_GPI6 0x00000040U 1269 #define LRFDRFE_EVTMSK1_GPI6_M 0x00000040U 1270 #define LRFDRFE_EVTMSK1_GPI6_S 6U 1271 #define LRFDRFE_EVTMSK1_GPI6_EN 0x00000040U 1272 #define LRFDRFE_EVTMSK1_GPI6_DIS 0x00000000U 1273 1274 // Field: [5] GPI5 1275 // 1276 // Enable mask for event EVT1.GPI5 1277 // ENUMs: 1278 // EN The bit is 1 1279 // DIS The bit is 0 1280 #define LRFDRFE_EVTMSK1_GPI5 0x00000020U 1281 #define LRFDRFE_EVTMSK1_GPI5_M 0x00000020U 1282 #define LRFDRFE_EVTMSK1_GPI5_S 5U 1283 #define LRFDRFE_EVTMSK1_GPI5_EN 0x00000020U 1284 #define LRFDRFE_EVTMSK1_GPI5_DIS 0x00000000U 1285 1286 // Field: [4] GPI4 1287 // 1288 // Enable mask for event EVT1.GPI4 1289 // ENUMs: 1290 // EN The bit is 1 1291 // DIS The bit is 0 1292 #define LRFDRFE_EVTMSK1_GPI4 0x00000010U 1293 #define LRFDRFE_EVTMSK1_GPI4_M 0x00000010U 1294 #define LRFDRFE_EVTMSK1_GPI4_S 4U 1295 #define LRFDRFE_EVTMSK1_GPI4_EN 0x00000010U 1296 #define LRFDRFE_EVTMSK1_GPI4_DIS 0x00000000U 1297 1298 // Field: [3] GPI3 1299 // 1300 // Enable mask for event EVT1.GPI3 1301 // ENUMs: 1302 // EN The bit is 1 1303 // DIS The bit is 0 1304 #define LRFDRFE_EVTMSK1_GPI3 0x00000008U 1305 #define LRFDRFE_EVTMSK1_GPI3_M 0x00000008U 1306 #define LRFDRFE_EVTMSK1_GPI3_S 3U 1307 #define LRFDRFE_EVTMSK1_GPI3_EN 0x00000008U 1308 #define LRFDRFE_EVTMSK1_GPI3_DIS 0x00000000U 1309 1310 // Field: [2] GPI2 1311 // 1312 // Enable mask for event EVT1.GPI2 1313 // ENUMs: 1314 // EN The bit is 1 1315 // DIS The bit is 0 1316 #define LRFDRFE_EVTMSK1_GPI2 0x00000004U 1317 #define LRFDRFE_EVTMSK1_GPI2_M 0x00000004U 1318 #define LRFDRFE_EVTMSK1_GPI2_S 2U 1319 #define LRFDRFE_EVTMSK1_GPI2_EN 0x00000004U 1320 #define LRFDRFE_EVTMSK1_GPI2_DIS 0x00000000U 1321 1322 // Field: [1] GPI1 1323 // 1324 // Enable mask for event EVT1.GPI1 1325 // ENUMs: 1326 // EN The bit is 1 1327 // DIS The bit is 0 1328 #define LRFDRFE_EVTMSK1_GPI1 0x00000002U 1329 #define LRFDRFE_EVTMSK1_GPI1_M 0x00000002U 1330 #define LRFDRFE_EVTMSK1_GPI1_S 1U 1331 #define LRFDRFE_EVTMSK1_GPI1_EN 0x00000002U 1332 #define LRFDRFE_EVTMSK1_GPI1_DIS 0x00000000U 1333 1334 // Field: [0] GPI0 1335 // 1336 // Enable mask for event EVT1.GPI0 1337 // ENUMs: 1338 // EN The bit is 1 1339 // DIS The bit is 0 1340 #define LRFDRFE_EVTMSK1_GPI0 0x00000001U 1341 #define LRFDRFE_EVTMSK1_GPI0_M 0x00000001U 1342 #define LRFDRFE_EVTMSK1_GPI0_S 0U 1343 #define LRFDRFE_EVTMSK1_GPI0_EN 0x00000001U 1344 #define LRFDRFE_EVTMSK1_GPI0_DIS 0x00000000U 1345 1346 //***************************************************************************** 1347 // 1348 // Register: LRFDRFE_O_EVTCLR0 1349 // 1350 //***************************************************************************** 1351 // Field: [14] MAGNTHR 1352 // 1353 // Clear event EVT0.MAGNTHR 1354 // ENUMs: 1355 // ONE The bit is 1 1356 // ZERO The bit is 0 1357 #define LRFDRFE_EVTCLR0_MAGNTHR 0x00004000U 1358 #define LRFDRFE_EVTCLR0_MAGNTHR_M 0x00004000U 1359 #define LRFDRFE_EVTCLR0_MAGNTHR_S 14U 1360 #define LRFDRFE_EVTCLR0_MAGNTHR_ONE 0x00004000U 1361 #define LRFDRFE_EVTCLR0_MAGNTHR_ZERO 0x00000000U 1362 1363 // Field: [13] S2RSTOP 1364 // 1365 // Clear event EVT0.S2RSTOP 1366 // ENUMs: 1367 // ONE The bit is 1 1368 // ZERO The bit is 0 1369 #define LRFDRFE_EVTCLR0_S2RSTOP 0x00002000U 1370 #define LRFDRFE_EVTCLR0_S2RSTOP_M 0x00002000U 1371 #define LRFDRFE_EVTCLR0_S2RSTOP_S 13U 1372 #define LRFDRFE_EVTCLR0_S2RSTOP_ONE 0x00002000U 1373 #define LRFDRFE_EVTCLR0_S2RSTOP_ZERO 0x00000000U 1374 1375 // Field: [12] SYSTCMP2 1376 // 1377 // Clear event EVT0.SYSTCMP2 1378 // ENUMs: 1379 // ONE The bit is 1 1380 // ZERO The bit is 0 1381 #define LRFDRFE_EVTCLR0_SYSTCMP2 0x00001000U 1382 #define LRFDRFE_EVTCLR0_SYSTCMP2_M 0x00001000U 1383 #define LRFDRFE_EVTCLR0_SYSTCMP2_S 12U 1384 #define LRFDRFE_EVTCLR0_SYSTCMP2_ONE 0x00001000U 1385 #define LRFDRFE_EVTCLR0_SYSTCMP2_ZERO 0x00000000U 1386 1387 // Field: [11] SYSTCMP1 1388 // 1389 // Clear event EVT0.SYSTCMP1 1390 // ENUMs: 1391 // ONE The bit is 1 1392 // ZERO The bit is 0 1393 #define LRFDRFE_EVTCLR0_SYSTCMP1 0x00000800U 1394 #define LRFDRFE_EVTCLR0_SYSTCMP1_M 0x00000800U 1395 #define LRFDRFE_EVTCLR0_SYSTCMP1_S 11U 1396 #define LRFDRFE_EVTCLR0_SYSTCMP1_ONE 0x00000800U 1397 #define LRFDRFE_EVTCLR0_SYSTCMP1_ZERO 0x00000000U 1398 1399 // Field: [10] SYSTCMP0 1400 // 1401 // Clear event EVT0.SYSTCMP0 1402 // ENUMs: 1403 // ONE The bit is 1 1404 // ZERO The bit is 0 1405 #define LRFDRFE_EVTCLR0_SYSTCMP0 0x00000400U 1406 #define LRFDRFE_EVTCLR0_SYSTCMP0_M 0x00000400U 1407 #define LRFDRFE_EVTCLR0_SYSTCMP0_S 10U 1408 #define LRFDRFE_EVTCLR0_SYSTCMP0_ONE 0x00000400U 1409 #define LRFDRFE_EVTCLR0_SYSTCMP0_ZERO 0x00000000U 1410 1411 // Field: [9] PBERFEDAT 1412 // 1413 // Clear event EVT0.PBERFEDAT 1414 // ENUMs: 1415 // ONE The bit is 1 1416 // ZERO The bit is 0 1417 #define LRFDRFE_EVTCLR0_PBERFEDAT 0x00000200U 1418 #define LRFDRFE_EVTCLR0_PBERFEDAT_M 0x00000200U 1419 #define LRFDRFE_EVTCLR0_PBERFEDAT_S 9U 1420 #define LRFDRFE_EVTCLR0_PBERFEDAT_ONE 0x00000200U 1421 #define LRFDRFE_EVTCLR0_PBERFEDAT_ZERO 0x00000000U 1422 1423 // Field: [8] MDMRFEDAT 1424 // 1425 // Clear event EVT0.MDMRFEDAT 1426 // ENUMs: 1427 // ONE The bit is 1 1428 // ZERO The bit is 0 1429 #define LRFDRFE_EVTCLR0_MDMRFEDAT 0x00000100U 1430 #define LRFDRFE_EVTCLR0_MDMRFEDAT_M 0x00000100U 1431 #define LRFDRFE_EVTCLR0_MDMRFEDAT_S 8U 1432 #define LRFDRFE_EVTCLR0_MDMRFEDAT_ONE 0x00000100U 1433 #define LRFDRFE_EVTCLR0_MDMRFEDAT_ZERO 0x00000000U 1434 1435 // Field: [7] DLO 1436 // 1437 // Clear event EVT0.DLO 1438 // ENUMs: 1439 // ONE The bit is 1 1440 // ZERO The bit is 0 1441 #define LRFDRFE_EVTCLR0_DLO 0x00000080U 1442 #define LRFDRFE_EVTCLR0_DLO_M 0x00000080U 1443 #define LRFDRFE_EVTCLR0_DLO_S 7U 1444 #define LRFDRFE_EVTCLR0_DLO_ONE 0x00000080U 1445 #define LRFDRFE_EVTCLR0_DLO_ZERO 0x00000000U 1446 1447 // Field: [6] PBECMD 1448 // 1449 // Clear event EVT0.PBECMD 1450 // ENUMs: 1451 // ONE The bit is 1 1452 // ZERO The bit is 0 1453 #define LRFDRFE_EVTCLR0_PBECMD 0x00000040U 1454 #define LRFDRFE_EVTCLR0_PBECMD_M 0x00000040U 1455 #define LRFDRFE_EVTCLR0_PBECMD_S 6U 1456 #define LRFDRFE_EVTCLR0_PBECMD_ONE 0x00000040U 1457 #define LRFDRFE_EVTCLR0_PBECMD_ZERO 0x00000000U 1458 1459 // Field: [5] COUNTER 1460 // 1461 // Clear event EVT0.COUNTER 1462 // ENUMs: 1463 // ONE The bit is 1 1464 // ZERO The bit is 0 1465 #define LRFDRFE_EVTCLR0_COUNTER 0x00000020U 1466 #define LRFDRFE_EVTCLR0_COUNTER_M 0x00000020U 1467 #define LRFDRFE_EVTCLR0_COUNTER_S 5U 1468 #define LRFDRFE_EVTCLR0_COUNTER_ONE 0x00000020U 1469 #define LRFDRFE_EVTCLR0_COUNTER_ZERO 0x00000000U 1470 1471 // Field: [4] MDMCMD 1472 // 1473 // Clear event EVT0.MDMCMD 1474 // ENUMs: 1475 // ONE The bit is 1 1476 // ZERO The bit is 0 1477 #define LRFDRFE_EVTCLR0_MDMCMD 0x00000010U 1478 #define LRFDRFE_EVTCLR0_MDMCMD_M 0x00000010U 1479 #define LRFDRFE_EVTCLR0_MDMCMD_S 4U 1480 #define LRFDRFE_EVTCLR0_MDMCMD_ONE 0x00000010U 1481 #define LRFDRFE_EVTCLR0_MDMCMD_ZERO 0x00000000U 1482 1483 // Field: [3] ACC1 1484 // 1485 // Clear event EVT0.ACC1 1486 // ENUMs: 1487 // ONE The bit is 1 1488 // ZERO The bit is 0 1489 #define LRFDRFE_EVTCLR0_ACC1 0x00000008U 1490 #define LRFDRFE_EVTCLR0_ACC1_M 0x00000008U 1491 #define LRFDRFE_EVTCLR0_ACC1_S 3U 1492 #define LRFDRFE_EVTCLR0_ACC1_ONE 0x00000008U 1493 #define LRFDRFE_EVTCLR0_ACC1_ZERO 0x00000000U 1494 1495 // Field: [2] ACC0 1496 // 1497 // Clear event EVT0.ACC0 1498 // ENUMs: 1499 // ONE The bit is 1 1500 // ZERO The bit is 0 1501 #define LRFDRFE_EVTCLR0_ACC0 0x00000004U 1502 #define LRFDRFE_EVTCLR0_ACC0_M 0x00000004U 1503 #define LRFDRFE_EVTCLR0_ACC0_S 2U 1504 #define LRFDRFE_EVTCLR0_ACC0_ONE 0x00000004U 1505 #define LRFDRFE_EVTCLR0_ACC0_ZERO 0x00000000U 1506 1507 // Field: [1] TIMER 1508 // 1509 // Clear event EVT0.TIMER 1510 // ENUMs: 1511 // ONE The bit is 1 1512 // ZERO The bit is 0 1513 #define LRFDRFE_EVTCLR0_TIMER 0x00000002U 1514 #define LRFDRFE_EVTCLR0_TIMER_M 0x00000002U 1515 #define LRFDRFE_EVTCLR0_TIMER_S 1U 1516 #define LRFDRFE_EVTCLR0_TIMER_ONE 0x00000002U 1517 #define LRFDRFE_EVTCLR0_TIMER_ZERO 0x00000000U 1518 1519 // Field: [0] RFEAPI 1520 // 1521 // Clear event EVT0.RFEAPI 1522 // ENUMs: 1523 // ONE The bit is 1 1524 // ZERO The bit is 0 1525 #define LRFDRFE_EVTCLR0_RFEAPI 0x00000001U 1526 #define LRFDRFE_EVTCLR0_RFEAPI_M 0x00000001U 1527 #define LRFDRFE_EVTCLR0_RFEAPI_S 0U 1528 #define LRFDRFE_EVTCLR0_RFEAPI_ONE 0x00000001U 1529 #define LRFDRFE_EVTCLR0_RFEAPI_ZERO 0x00000000U 1530 1531 //***************************************************************************** 1532 // 1533 // Register: LRFDRFE_O_EVTCLR1 1534 // 1535 //***************************************************************************** 1536 // Field: [13] PREREFCLK 1537 // 1538 // Clear event EVT1.PREREFCLK 1539 // ENUMs: 1540 // ONE The bit is 1 1541 // ZERO The bit is 0 1542 #define LRFDRFE_EVTCLR1_PREREFCLK 0x00002000U 1543 #define LRFDRFE_EVTCLR1_PREREFCLK_M 0x00002000U 1544 #define LRFDRFE_EVTCLR1_PREREFCLK_S 13U 1545 #define LRFDRFE_EVTCLR1_PREREFCLK_ONE 0x00002000U 1546 #define LRFDRFE_EVTCLR1_PREREFCLK_ZERO 0x00000000U 1547 1548 // Field: [12] REFCLK 1549 // 1550 // Clear event EVT1.REFCLK 1551 // ENUMs: 1552 // ONE The bit is 1 1553 // ZERO The bit is 0 1554 #define LRFDRFE_EVTCLR1_REFCLK 0x00001000U 1555 #define LRFDRFE_EVTCLR1_REFCLK_M 0x00001000U 1556 #define LRFDRFE_EVTCLR1_REFCLK_S 12U 1557 #define LRFDRFE_EVTCLR1_REFCLK_ONE 0x00001000U 1558 #define LRFDRFE_EVTCLR1_REFCLK_ZERO 0x00000000U 1559 1560 // Field: [11] FBLWTHR 1561 // 1562 // Clear event EVT1.FBLWTHR 1563 // ENUMs: 1564 // ONE The bit is 1 1565 // ZERO The bit is 0 1566 #define LRFDRFE_EVTCLR1_FBLWTHR 0x00000800U 1567 #define LRFDRFE_EVTCLR1_FBLWTHR_M 0x00000800U 1568 #define LRFDRFE_EVTCLR1_FBLWTHR_S 11U 1569 #define LRFDRFE_EVTCLR1_FBLWTHR_ONE 0x00000800U 1570 #define LRFDRFE_EVTCLR1_FBLWTHR_ZERO 0x00000000U 1571 1572 // Field: [10] FABVTHR 1573 // 1574 // Clear event EVT1.FABVTHR 1575 // ENUMs: 1576 // ONE The bit is 1 1577 // ZERO The bit is 0 1578 #define LRFDRFE_EVTCLR1_FABVTHR 0x00000400U 1579 #define LRFDRFE_EVTCLR1_FABVTHR_M 0x00000400U 1580 #define LRFDRFE_EVTCLR1_FABVTHR_S 10U 1581 #define LRFDRFE_EVTCLR1_FABVTHR_ONE 0x00000400U 1582 #define LRFDRFE_EVTCLR1_FABVTHR_ZERO 0x00000000U 1583 1584 // Field: [9] LOCK 1585 // 1586 // Clear event EVT1.LOCK 1587 // ENUMs: 1588 // ONE The bit is 1 1589 // ZERO The bit is 0 1590 #define LRFDRFE_EVTCLR1_LOCK 0x00000200U 1591 #define LRFDRFE_EVTCLR1_LOCK_M 0x00000200U 1592 #define LRFDRFE_EVTCLR1_LOCK_S 9U 1593 #define LRFDRFE_EVTCLR1_LOCK_ONE 0x00000200U 1594 #define LRFDRFE_EVTCLR1_LOCK_ZERO 0x00000000U 1595 1596 // Field: [8] LOL 1597 // 1598 // Clear event EVT1.LOL 1599 // ENUMs: 1600 // ONE The bit is 1 1601 // ZERO The bit is 0 1602 #define LRFDRFE_EVTCLR1_LOL 0x00000100U 1603 #define LRFDRFE_EVTCLR1_LOL_M 0x00000100U 1604 #define LRFDRFE_EVTCLR1_LOL_S 8U 1605 #define LRFDRFE_EVTCLR1_LOL_ONE 0x00000100U 1606 #define LRFDRFE_EVTCLR1_LOL_ZERO 0x00000000U 1607 1608 // Field: [7] GPI7 1609 // 1610 // Clear event EVT1.GPI7 1611 // ENUMs: 1612 // ONE The bit is 1 1613 // ZERO The bit is 0 1614 #define LRFDRFE_EVTCLR1_GPI7 0x00000080U 1615 #define LRFDRFE_EVTCLR1_GPI7_M 0x00000080U 1616 #define LRFDRFE_EVTCLR1_GPI7_S 7U 1617 #define LRFDRFE_EVTCLR1_GPI7_ONE 0x00000080U 1618 #define LRFDRFE_EVTCLR1_GPI7_ZERO 0x00000000U 1619 1620 // Field: [6] GPI6 1621 // 1622 // Clear event EVT1.GPI6 1623 // ENUMs: 1624 // ONE The bit is 1 1625 // ZERO The bit is 0 1626 #define LRFDRFE_EVTCLR1_GPI6 0x00000040U 1627 #define LRFDRFE_EVTCLR1_GPI6_M 0x00000040U 1628 #define LRFDRFE_EVTCLR1_GPI6_S 6U 1629 #define LRFDRFE_EVTCLR1_GPI6_ONE 0x00000040U 1630 #define LRFDRFE_EVTCLR1_GPI6_ZERO 0x00000000U 1631 1632 // Field: [5] GPI5 1633 // 1634 // Clear event EVT1.GPI5 1635 // ENUMs: 1636 // ONE The bit is 1 1637 // ZERO The bit is 0 1638 #define LRFDRFE_EVTCLR1_GPI5 0x00000020U 1639 #define LRFDRFE_EVTCLR1_GPI5_M 0x00000020U 1640 #define LRFDRFE_EVTCLR1_GPI5_S 5U 1641 #define LRFDRFE_EVTCLR1_GPI5_ONE 0x00000020U 1642 #define LRFDRFE_EVTCLR1_GPI5_ZERO 0x00000000U 1643 1644 // Field: [4] GPI4 1645 // 1646 // Clear event EVT1.GPI4 1647 // ENUMs: 1648 // ONE The bit is 1 1649 // ZERO The bit is 0 1650 #define LRFDRFE_EVTCLR1_GPI4 0x00000010U 1651 #define LRFDRFE_EVTCLR1_GPI4_M 0x00000010U 1652 #define LRFDRFE_EVTCLR1_GPI4_S 4U 1653 #define LRFDRFE_EVTCLR1_GPI4_ONE 0x00000010U 1654 #define LRFDRFE_EVTCLR1_GPI4_ZERO 0x00000000U 1655 1656 // Field: [3] GPI3 1657 // 1658 // Clear event EVT1.GPI3 1659 // ENUMs: 1660 // ONE The bit is 1 1661 // ZERO The bit is 0 1662 #define LRFDRFE_EVTCLR1_GPI3 0x00000008U 1663 #define LRFDRFE_EVTCLR1_GPI3_M 0x00000008U 1664 #define LRFDRFE_EVTCLR1_GPI3_S 3U 1665 #define LRFDRFE_EVTCLR1_GPI3_ONE 0x00000008U 1666 #define LRFDRFE_EVTCLR1_GPI3_ZERO 0x00000000U 1667 1668 // Field: [2] GPI2 1669 // 1670 // Clear event EVT1.GPI2 1671 // ENUMs: 1672 // ONE The bit is 1 1673 // ZERO The bit is 0 1674 #define LRFDRFE_EVTCLR1_GPI2 0x00000004U 1675 #define LRFDRFE_EVTCLR1_GPI2_M 0x00000004U 1676 #define LRFDRFE_EVTCLR1_GPI2_S 2U 1677 #define LRFDRFE_EVTCLR1_GPI2_ONE 0x00000004U 1678 #define LRFDRFE_EVTCLR1_GPI2_ZERO 0x00000000U 1679 1680 // Field: [1] GPI1 1681 // 1682 // Clear event EVT1.GPI1 1683 // ENUMs: 1684 // ONE The bit is 1 1685 // ZERO The bit is 0 1686 #define LRFDRFE_EVTCLR1_GPI1 0x00000002U 1687 #define LRFDRFE_EVTCLR1_GPI1_M 0x00000002U 1688 #define LRFDRFE_EVTCLR1_GPI1_S 1U 1689 #define LRFDRFE_EVTCLR1_GPI1_ONE 0x00000002U 1690 #define LRFDRFE_EVTCLR1_GPI1_ZERO 0x00000000U 1691 1692 // Field: [0] GPI0 1693 // 1694 // Clear event EVT1.GPI0 1695 // ENUMs: 1696 // ONE The bit is 1 1697 // ZERO The bit is 0 1698 #define LRFDRFE_EVTCLR1_GPI0 0x00000001U 1699 #define LRFDRFE_EVTCLR1_GPI0_M 0x00000001U 1700 #define LRFDRFE_EVTCLR1_GPI0_S 0U 1701 #define LRFDRFE_EVTCLR1_GPI0_ONE 0x00000001U 1702 #define LRFDRFE_EVTCLR1_GPI0_ZERO 0x00000000U 1703 1704 //***************************************************************************** 1705 // 1706 // Register: LRFDRFE_O_HFXTSTAT 1707 // 1708 //***************************************************************************** 1709 // Field: [0] STAT 1710 // 1711 // HFXT RF qualification 1712 // ENUMs: 1713 // QUAL Clock signal is qualified 1714 // NONQUAL Clock signal is not qualified 1715 #define LRFDRFE_HFXTSTAT_STAT 0x00000001U 1716 #define LRFDRFE_HFXTSTAT_STAT_M 0x00000001U 1717 #define LRFDRFE_HFXTSTAT_STAT_S 0U 1718 #define LRFDRFE_HFXTSTAT_STAT_QUAL 0x00000001U 1719 #define LRFDRFE_HFXTSTAT_STAT_NONQUAL 0x00000000U 1720 1721 //***************************************************************************** 1722 // 1723 // Register: LRFDRFE_O_RFSTATE 1724 // 1725 //***************************************************************************** 1726 // Field: [3:0] VAL 1727 // 1728 // Radio Status 1729 // ENUMs: 1730 // RX RX is active 1731 // TX TX is active 1732 // SYNTH Synth is running 1733 // IDLE Radio is idle 1734 #define LRFDRFE_RFSTATE_VAL_W 4U 1735 #define LRFDRFE_RFSTATE_VAL_M 0x0000000FU 1736 #define LRFDRFE_RFSTATE_VAL_S 0U 1737 #define LRFDRFE_RFSTATE_VAL_RX 0x00000003U 1738 #define LRFDRFE_RFSTATE_VAL_TX 0x00000002U 1739 #define LRFDRFE_RFSTATE_VAL_SYNTH 0x00000001U 1740 #define LRFDRFE_RFSTATE_VAL_IDLE 0x00000000U 1741 1742 //***************************************************************************** 1743 // 1744 // Register: LRFDRFE_O_API 1745 // 1746 //***************************************************************************** 1747 // Field: [7:4] PROTOCOLID 1748 // 1749 // Protocol ID 1750 // ENUMs: 1751 // ALLONES All the bits are 1 1752 // ALLZEROS All the bits are 0 1753 #define LRFDRFE_API_PROTOCOLID_W 4U 1754 #define LRFDRFE_API_PROTOCOLID_M 0x000000F0U 1755 #define LRFDRFE_API_PROTOCOLID_S 4U 1756 #define LRFDRFE_API_PROTOCOLID_ALLONES 0x000000F0U 1757 #define LRFDRFE_API_PROTOCOLID_ALLZEROS 0x00000000U 1758 1759 // Field: [3:0] RFECMD 1760 // 1761 // RFE Command 1762 // ENUMs: 1763 // ALLONES All the bits are 1 1764 // ALLZEROS All bits are 0 1765 #define LRFDRFE_API_RFECMD_W 4U 1766 #define LRFDRFE_API_RFECMD_M 0x0000000FU 1767 #define LRFDRFE_API_RFECMD_S 0U 1768 #define LRFDRFE_API_RFECMD_ALLONES 0x0000000FU 1769 #define LRFDRFE_API_RFECMD_ALLZEROS 0x00000000U 1770 1771 //***************************************************************************** 1772 // 1773 // Register: LRFDRFE_O_CMDPAR0 1774 // 1775 //***************************************************************************** 1776 // Field: [15:0] VAL 1777 // 1778 // Parameter 0 1779 // ENUMs: 1780 // ALLONES All the bits are 1 1781 // ALLZEROS All the bits are 0 1782 #define LRFDRFE_CMDPAR0_VAL_W 16U 1783 #define LRFDRFE_CMDPAR0_VAL_M 0x0000FFFFU 1784 #define LRFDRFE_CMDPAR0_VAL_S 0U 1785 #define LRFDRFE_CMDPAR0_VAL_ALLONES 0x0000FFFFU 1786 #define LRFDRFE_CMDPAR0_VAL_ALLZEROS 0x00000000U 1787 1788 //***************************************************************************** 1789 // 1790 // Register: LRFDRFE_O_CMDPAR1 1791 // 1792 //***************************************************************************** 1793 // Field: [15:0] VAL 1794 // 1795 // Parameter 1 1796 // ENUMs: 1797 // ALLONES All the bits are 1 1798 // ALLZEROS All the bits are 0 1799 #define LRFDRFE_CMDPAR1_VAL_W 16U 1800 #define LRFDRFE_CMDPAR1_VAL_M 0x0000FFFFU 1801 #define LRFDRFE_CMDPAR1_VAL_S 0U 1802 #define LRFDRFE_CMDPAR1_VAL_ALLONES 0x0000FFFFU 1803 #define LRFDRFE_CMDPAR1_VAL_ALLZEROS 0x00000000U 1804 1805 //***************************************************************************** 1806 // 1807 // Register: LRFDRFE_O_MSGBOX 1808 // 1809 //***************************************************************************** 1810 // Field: [7:0] VAL 1811 // 1812 // RFE status as responser to API execution. 1813 // 1814 // Field is readable to PBE in LRFDPBE:RFEMSGBOX. 1815 // ENUMs: 1816 // ALLONES All the bits are 1 1817 // ALLZEROS All the bits are 0 1818 #define LRFDRFE_MSGBOX_VAL_W 8U 1819 #define LRFDRFE_MSGBOX_VAL_M 0x000000FFU 1820 #define LRFDRFE_MSGBOX_VAL_S 0U 1821 #define LRFDRFE_MSGBOX_VAL_ALLONES 0x000000FFU 1822 #define LRFDRFE_MSGBOX_VAL_ALLZEROS 0x00000000U 1823 1824 //***************************************************************************** 1825 // 1826 // Register: LRFDRFE_O_MCEDATOUT0 1827 // 1828 //***************************************************************************** 1829 // Field: [15:0] VAL 1830 // 1831 // Data to send to MCE. 1832 // 1833 // Write VAL to send data to MCE. A write triggers an LRFDMDM:EVT0.RFEDAT event 1834 // in MCE. MCE reads VAL in LRFDMDM:RFEDATIN0. 1835 // ENUMs: 1836 // ALLONES All the bits are 1 1837 // ALLZEROS All the bits are 0 1838 #define LRFDRFE_MCEDATOUT0_VAL_W 16U 1839 #define LRFDRFE_MCEDATOUT0_VAL_M 0x0000FFFFU 1840 #define LRFDRFE_MCEDATOUT0_VAL_S 0U 1841 #define LRFDRFE_MCEDATOUT0_VAL_ALLONES 0x0000FFFFU 1842 #define LRFDRFE_MCEDATOUT0_VAL_ALLZEROS 0x00000000U 1843 1844 //***************************************************************************** 1845 // 1846 // Register: LRFDRFE_O_MCEDATIN0 1847 // 1848 //***************************************************************************** 1849 // Field: [15:0] VAL 1850 // 1851 // Data received from MCE. 1852 // 1853 // Read data that MCE writes to LRFDMDM:RFEDATAOUT0. A write to 1854 // LRFDMDM:RFEDATAOUT0 sets EVT0.MDMRFEDAT event. 1855 // ENUMs: 1856 // ALLONES All the bits are 1 1857 // ALLZEROS All the bits are 0 1858 #define LRFDRFE_MCEDATIN0_VAL_W 16U 1859 #define LRFDRFE_MCEDATIN0_VAL_M 0x0000FFFFU 1860 #define LRFDRFE_MCEDATIN0_VAL_S 0U 1861 #define LRFDRFE_MCEDATIN0_VAL_ALLONES 0x0000FFFFU 1862 #define LRFDRFE_MCEDATIN0_VAL_ALLZEROS 0x00000000U 1863 1864 //***************************************************************************** 1865 // 1866 // Register: LRFDRFE_O_MCECMDOUT 1867 // 1868 //***************************************************************************** 1869 // Field: [3:0] VAL 1870 // 1871 // Command to send to the MCE. 1872 // 1873 // A write to this register tiggers LRFDMDM:EVT1.RFECMD MCE event, and the 1874 // command becomes readable to MCE in LRFDMDM:RFECMDIN. 1875 // ENUMs: 1876 // ALLONES All the bits are 1 1877 // ALLZEROS All the bits are 0 1878 #define LRFDRFE_MCECMDOUT_VAL_W 4U 1879 #define LRFDRFE_MCECMDOUT_VAL_M 0x0000000FU 1880 #define LRFDRFE_MCECMDOUT_VAL_S 0U 1881 #define LRFDRFE_MCECMDOUT_VAL_ALLONES 0x0000000FU 1882 #define LRFDRFE_MCECMDOUT_VAL_ALLZEROS 0x00000000U 1883 1884 //***************************************************************************** 1885 // 1886 // Register: LRFDRFE_O_MCECMDIN 1887 // 1888 //***************************************************************************** 1889 // Field: [3:0] VAL 1890 // 1891 // Command received from MCE. 1892 // 1893 // MCE writes LRFDMDM:RFECMDOUT to send a command to RFE. This action sets 1894 // EVT0.MDMCMD RFE event. RFE reads command from MCECMDIN. 1895 // ENUMs: 1896 // ALLONES All the bits are 1 1897 // ALLZEROS All the bits are 0 1898 #define LRFDRFE_MCECMDIN_VAL_W 4U 1899 #define LRFDRFE_MCECMDIN_VAL_M 0x0000000FU 1900 #define LRFDRFE_MCECMDIN_VAL_S 0U 1901 #define LRFDRFE_MCECMDIN_VAL_ALLONES 0x0000000FU 1902 #define LRFDRFE_MCECMDIN_VAL_ALLZEROS 0x00000000U 1903 1904 //***************************************************************************** 1905 // 1906 // Register: LRFDRFE_O_PBEDATOUT0 1907 // 1908 //***************************************************************************** 1909 // Field: [15:0] VAL 1910 // 1911 // Data to send to PBE. 1912 // 1913 // Write VAL to send data to PBE. A write triggers an LRFDPBE:EVT0.RFEDAT event 1914 // in PBE. PBE reads VAL in LRFDPBE:RFEDATIN0. 1915 // ENUMs: 1916 // ALLONES All the bits are 1 1917 // ALLZEROS All the bits are 0 1918 #define LRFDRFE_PBEDATOUT0_VAL_W 16U 1919 #define LRFDRFE_PBEDATOUT0_VAL_M 0x0000FFFFU 1920 #define LRFDRFE_PBEDATOUT0_VAL_S 0U 1921 #define LRFDRFE_PBEDATOUT0_VAL_ALLONES 0x0000FFFFU 1922 #define LRFDRFE_PBEDATOUT0_VAL_ALLZEROS 0x00000000U 1923 1924 //***************************************************************************** 1925 // 1926 // Register: LRFDRFE_O_PBEDATIN0 1927 // 1928 //***************************************************************************** 1929 // Field: [15:0] VAL 1930 // 1931 // Data received from PBE. 1932 // 1933 // Read data that PBE writes to LRFDPBE:RFEDATAOUT0. A write to 1934 // LRFDPBE:RFEDATAOUT0 sets EVT0.PBERFEDAT event. 1935 // ENUMs: 1936 // ALLONES All the bits are 1 1937 // ALLZEROS All the bits are 0 1938 #define LRFDRFE_PBEDATIN0_VAL_W 16U 1939 #define LRFDRFE_PBEDATIN0_VAL_M 0x0000FFFFU 1940 #define LRFDRFE_PBEDATIN0_VAL_S 0U 1941 #define LRFDRFE_PBEDATIN0_VAL_ALLONES 0x0000FFFFU 1942 #define LRFDRFE_PBEDATIN0_VAL_ALLZEROS 0x00000000U 1943 1944 //***************************************************************************** 1945 // 1946 // Register: LRFDRFE_O_PBECMDOUT 1947 // 1948 //***************************************************************************** 1949 // Field: [3:0] VAL 1950 // 1951 // Command to send to the PBE. 1952 // 1953 // A write to this register tiggers LRFDPBE:EVT0.RFECMD PBE event, and the 1954 // command becomes readable to PBE in LRFDPBE:RFECMDIN. 1955 // 1956 // 1957 // Command to send to the PBE. Writing to this register will trigger an event 1958 // in the PBE, and the command value written here will be readable in 1959 // LRFDPBE:RFECMDIN register. 1960 // ENUMs: 1961 // ALLONES All the bits are 1 1962 // ALLZEROS All the bits are 0 1963 #define LRFDRFE_PBECMDOUT_VAL_W 4U 1964 #define LRFDRFE_PBECMDOUT_VAL_M 0x0000000FU 1965 #define LRFDRFE_PBECMDOUT_VAL_S 0U 1966 #define LRFDRFE_PBECMDOUT_VAL_ALLONES 0x0000000FU 1967 #define LRFDRFE_PBECMDOUT_VAL_ALLZEROS 0x00000000U 1968 1969 //***************************************************************************** 1970 // 1971 // Register: LRFDRFE_O_PBECMDIN 1972 // 1973 //***************************************************************************** 1974 // Field: [3:0] VAL 1975 // 1976 // Command received from PBE. 1977 // 1978 // PBE writes LRFDPBE:RFECMDOUT to send a command to RFE. This action sets 1979 // EVT0.PBECMD RFE event. RFE reads command from PBECMDIN. 1980 // ENUMs: 1981 // ALLONES All the bits are 1 1982 // ALLZEROS All the bits are 0 1983 #define LRFDRFE_PBECMDIN_VAL_W 4U 1984 #define LRFDRFE_PBECMDIN_VAL_M 0x0000000FU 1985 #define LRFDRFE_PBECMDIN_VAL_S 0U 1986 #define LRFDRFE_PBECMDIN_VAL_ALLONES 0x0000000FU 1987 #define LRFDRFE_PBECMDIN_VAL_ALLZEROS 0x00000000U 1988 1989 //***************************************************************************** 1990 // 1991 // Register: LRFDRFE_O_STRB 1992 // 1993 //***************************************************************************** 1994 // Field: [7] S2RTRG 1995 // 1996 // LRFDS2R arm/trigger 1997 // ENUMs: 1998 // ONE The bit is 1 1999 // ZERO The bit is 0 2000 #define LRFDRFE_STRB_S2RTRG 0x00000080U 2001 #define LRFDRFE_STRB_S2RTRG_M 0x00000080U 2002 #define LRFDRFE_STRB_S2RTRG_S 7U 2003 #define LRFDRFE_STRB_S2RTRG_ONE 0x00000080U 2004 #define LRFDRFE_STRB_S2RTRG_ZERO 0x00000000U 2005 2006 // Field: [6] DMATRG 2007 // 2008 // DMA transfer trigger 2009 // ENUMs: 2010 // ONE The bit is 1 2011 // ZERO The bit is 0 2012 #define LRFDRFE_STRB_DMATRG 0x00000040U 2013 #define LRFDRFE_STRB_DMATRG_M 0x00000040U 2014 #define LRFDRFE_STRB_DMATRG_S 6U 2015 #define LRFDRFE_STRB_DMATRG_ONE 0x00000040U 2016 #define LRFDRFE_STRB_DMATRG_ZERO 0x00000000U 2017 2018 // Field: [5] SYSTCPT2 2019 // 2020 // Systimer capture event 2 2021 // ENUMs: 2022 // ONE The bit is 1 2023 // ZERO The bit is 0 2024 #define LRFDRFE_STRB_SYSTCPT2 0x00000020U 2025 #define LRFDRFE_STRB_SYSTCPT2_M 0x00000020U 2026 #define LRFDRFE_STRB_SYSTCPT2_S 5U 2027 #define LRFDRFE_STRB_SYSTCPT2_ONE 0x00000020U 2028 #define LRFDRFE_STRB_SYSTCPT2_ZERO 0x00000000U 2029 2030 // Field: [4] SYSTCPT1 2031 // 2032 // Systimer capture event 1 2033 // ENUMs: 2034 // ONE The bit is 1 2035 // ZERO The bit is 0 2036 #define LRFDRFE_STRB_SYSTCPT1 0x00000010U 2037 #define LRFDRFE_STRB_SYSTCPT1_M 0x00000010U 2038 #define LRFDRFE_STRB_SYSTCPT1_S 4U 2039 #define LRFDRFE_STRB_SYSTCPT1_ONE 0x00000010U 2040 #define LRFDRFE_STRB_SYSTCPT1_ZERO 0x00000000U 2041 2042 // Field: [3] SYSTCPT0 2043 // 2044 // Systimer capture event 0 2045 // ENUMs: 2046 // ONE The bit is 1 2047 // ZERO The bit is 0 2048 #define LRFDRFE_STRB_SYSTCPT0 0x00000008U 2049 #define LRFDRFE_STRB_SYSTCPT0_M 0x00000008U 2050 #define LRFDRFE_STRB_SYSTCPT0_S 3U 2051 #define LRFDRFE_STRB_SYSTCPT0_ONE 0x00000008U 2052 #define LRFDRFE_STRB_SYSTCPT0_ZERO 0x00000000U 2053 2054 // Field: [2] EVT1 2055 // 2056 // Event 1 2057 // ENUMs: 2058 // ONE The bit is 1 2059 // ZERO The bit is 0 2060 #define LRFDRFE_STRB_EVT1 0x00000004U 2061 #define LRFDRFE_STRB_EVT1_M 0x00000004U 2062 #define LRFDRFE_STRB_EVT1_S 2U 2063 #define LRFDRFE_STRB_EVT1_ONE 0x00000004U 2064 #define LRFDRFE_STRB_EVT1_ZERO 0x00000000U 2065 2066 // Field: [1] EVT0 2067 // 2068 // Event 0 2069 // ENUMs: 2070 // ONE The bit is 1 2071 // ZERO The bit is 0 2072 #define LRFDRFE_STRB_EVT0 0x00000002U 2073 #define LRFDRFE_STRB_EVT0_M 0x00000002U 2074 #define LRFDRFE_STRB_EVT0_S 1U 2075 #define LRFDRFE_STRB_EVT0_ONE 0x00000002U 2076 #define LRFDRFE_STRB_EVT0_ZERO 0x00000000U 2077 2078 // Field: [0] CMDDONE 2079 // 2080 // Command done indication 2081 // ENUMs: 2082 // YES The bit is 1 2083 // NO The bit is 0 2084 #define LRFDRFE_STRB_CMDDONE 0x00000001U 2085 #define LRFDRFE_STRB_CMDDONE_M 0x00000001U 2086 #define LRFDRFE_STRB_CMDDONE_S 0U 2087 #define LRFDRFE_STRB_CMDDONE_YES 0x00000001U 2088 #define LRFDRFE_STRB_CMDDONE_NO 0x00000000U 2089 2090 //***************************************************************************** 2091 // 2092 // Register: LRFDRFE_O_MAGNTHRCFG 2093 // 2094 //***************************************************************************** 2095 // Field: [1] SEL 2096 // 2097 // Selects what MAGNACC is used in the compare with the threshold in MAGNTHR. 2098 // ENUMs: 2099 // MAGNACC1 Use MAGNACC1 in the compare against the theshold 2100 // in MANGTHR 2101 // MAGNACC0 Use MAGNACC0 in the compare against the theshold 2102 // in MANGTHR 2103 #define LRFDRFE_MAGNTHRCFG_SEL 0x00000002U 2104 #define LRFDRFE_MAGNTHRCFG_SEL_M 0x00000002U 2105 #define LRFDRFE_MAGNTHRCFG_SEL_S 1U 2106 #define LRFDRFE_MAGNTHRCFG_SEL_MAGNACC1 0x00000002U 2107 #define LRFDRFE_MAGNTHRCFG_SEL_MAGNACC0 0x00000000U 2108 2109 // Field: [0] CTL 2110 // 2111 // Controls automatic comparison of magnitude with threshold 2112 // ENUMs: 2113 // EN Enable automatic comparison of magntude with 2114 // threshold (input of lin2log is driven by HW) 2115 // DIS Disable automatic comparison with threshold (input 2116 // of lin2log is driven by FW) 2117 #define LRFDRFE_MAGNTHRCFG_CTL 0x00000001U 2118 #define LRFDRFE_MAGNTHRCFG_CTL_M 0x00000001U 2119 #define LRFDRFE_MAGNTHRCFG_CTL_S 0U 2120 #define LRFDRFE_MAGNTHRCFG_CTL_EN 0x00000001U 2121 #define LRFDRFE_MAGNTHRCFG_CTL_DIS 0x00000000U 2122 2123 //***************************************************************************** 2124 // 2125 // Register: LRFDRFE_O_MAGNTHR 2126 // 2127 //***************************************************************************** 2128 // Field: [7:0] VAL 2129 // 2130 // Magnitude threshold value 2131 // ENUMs: 2132 // ALLONES All the bits are 1 2133 // ALLZEROS All the bits are 0 2134 #define LRFDRFE_MAGNTHR_VAL_W 8U 2135 #define LRFDRFE_MAGNTHR_VAL_M 0x000000FFU 2136 #define LRFDRFE_MAGNTHR_VAL_S 0U 2137 #define LRFDRFE_MAGNTHR_VAL_ALLONES 0x000000FFU 2138 #define LRFDRFE_MAGNTHR_VAL_ALLZEROS 0x00000000U 2139 2140 //***************************************************************************** 2141 // 2142 // Register: LRFDRFE_O_RSSIOFFSET 2143 // 2144 //***************************************************************************** 2145 // Field: [7:0] VAL 2146 // 2147 // Offset to convert to dBm (unsigned). This is used by the RFE to adjust its 2148 // RSSI calculations. 2149 // ENUMs: 2150 // ALLONES All the bits are 1 2151 // ALLZEROS All the bits are 0 2152 #define LRFDRFE_RSSIOFFSET_VAL_W 8U 2153 #define LRFDRFE_RSSIOFFSET_VAL_M 0x000000FFU 2154 #define LRFDRFE_RSSIOFFSET_VAL_S 0U 2155 #define LRFDRFE_RSSIOFFSET_VAL_ALLONES 0x000000FFU 2156 #define LRFDRFE_RSSIOFFSET_VAL_ALLZEROS 0x00000000U 2157 2158 //***************************************************************************** 2159 // 2160 // Register: LRFDRFE_O_GAINCTL 2161 // 2162 //***************************************************************************** 2163 // Field: [3:2] BDE2DVGA 2164 // 2165 // DVGA settings for BDE2. 2166 // 2167 // The DVGA control for BDE2 is shared with the MCE in its 2168 // LRFDMDM:DEMMISC3.BDE2DVGA field. 2169 // Software should determine who uses them. Please note that if both processors 2170 // attempt to control it, the resulting setting will be the two settings ORed 2171 // together. 2172 // ENUMs: 2173 // GAIN8 Gain 8 2174 // GAIN4 Gain 4 2175 // GAIN2 Gain 2 2176 // GAIN1 Gain 1 2177 #define LRFDRFE_GAINCTL_BDE2DVGA_W 2U 2178 #define LRFDRFE_GAINCTL_BDE2DVGA_M 0x0000000CU 2179 #define LRFDRFE_GAINCTL_BDE2DVGA_S 2U 2180 #define LRFDRFE_GAINCTL_BDE2DVGA_GAIN8 0x0000000CU 2181 #define LRFDRFE_GAINCTL_BDE2DVGA_GAIN4 0x00000008U 2182 #define LRFDRFE_GAINCTL_BDE2DVGA_GAIN2 0x00000004U 2183 #define LRFDRFE_GAINCTL_BDE2DVGA_GAIN1 0x00000000U 2184 2185 // Field: [1:0] BDE1DVGA 2186 // 2187 // DVGA settings for BDE1. 2188 // 2189 // The DVGA control for BDE1 is shared with the MCE in its 2190 // LRFDMDM:DEMMISC3.BDE1DVGA field. 2191 // Software should determine who uses them. Please note that if both processors 2192 // attempt to control it, the resulting setting will be the two settings ORed 2193 // together. 2194 // ENUMs: 2195 // GAIN8 Gain 8 2196 // GAIN4 Gain 4 2197 // GAIN2 Gain 2 2198 // GAIN1 Gain 1 2199 #define LRFDRFE_GAINCTL_BDE1DVGA_W 2U 2200 #define LRFDRFE_GAINCTL_BDE1DVGA_M 0x00000003U 2201 #define LRFDRFE_GAINCTL_BDE1DVGA_S 0U 2202 #define LRFDRFE_GAINCTL_BDE1DVGA_GAIN8 0x00000003U 2203 #define LRFDRFE_GAINCTL_BDE1DVGA_GAIN4 0x00000002U 2204 #define LRFDRFE_GAINCTL_BDE1DVGA_GAIN2 0x00000001U 2205 #define LRFDRFE_GAINCTL_BDE1DVGA_GAIN1 0x00000000U 2206 2207 //***************************************************************************** 2208 // 2209 // Register: LRFDRFE_O_MAGNCTL0 2210 // 2211 //***************************************************************************** 2212 // Field: [12] PERMODE 2213 // 2214 // Measurement type 2215 // ENUMs: 2216 // PERIODIC Periodic mode 2217 // ONESHOT One-shot mode 2218 #define LRFDRFE_MAGNCTL0_PERMODE 0x00001000U 2219 #define LRFDRFE_MAGNCTL0_PERMODE_M 0x00001000U 2220 #define LRFDRFE_MAGNCTL0_PERMODE_S 12U 2221 #define LRFDRFE_MAGNCTL0_PERMODE_PERIODIC 0x00001000U 2222 #define LRFDRFE_MAGNCTL0_PERMODE_ONESHOT 0x00000000U 2223 2224 // Field: [11:8] SCL 2225 // 2226 // Scaling factor 2227 // 2228 // Scaling factor = 1/2^(SCL). 2229 // ENUMs: 2230 // DIV256 1/256 2231 // DIV128 1/128 2232 // DIV64 1/64 2233 // DIV32 1/32 2234 // DIV16 1/16 2235 // DIV8 2236 // DIV4 2237 // DIV2 2238 // DIV1 1/1 (no scaling) 2239 #define LRFDRFE_MAGNCTL0_SCL_W 4U 2240 #define LRFDRFE_MAGNCTL0_SCL_M 0x00000F00U 2241 #define LRFDRFE_MAGNCTL0_SCL_S 8U 2242 #define LRFDRFE_MAGNCTL0_SCL_DIV256 0x00000800U 2243 #define LRFDRFE_MAGNCTL0_SCL_DIV128 0x00000700U 2244 #define LRFDRFE_MAGNCTL0_SCL_DIV64 0x00000600U 2245 #define LRFDRFE_MAGNCTL0_SCL_DIV32 0x00000500U 2246 #define LRFDRFE_MAGNCTL0_SCL_DIV16 0x00000400U 2247 #define LRFDRFE_MAGNCTL0_SCL_DIV8 0x00000300U 2248 #define LRFDRFE_MAGNCTL0_SCL_DIV4 0x00000200U 2249 #define LRFDRFE_MAGNCTL0_SCL_DIV2 0x00000100U 2250 #define LRFDRFE_MAGNCTL0_SCL_DIV1 0x00000000U 2251 2252 // Field: [7:0] PER 2253 // 2254 // Accumulation period in incoming samples 2255 // ENUMs: 2256 // ALLONES All the bits are 1 2257 // ALLZEROS All the bits are 0 2258 #define LRFDRFE_MAGNCTL0_PER_W 8U 2259 #define LRFDRFE_MAGNCTL0_PER_M 0x000000FFU 2260 #define LRFDRFE_MAGNCTL0_PER_S 0U 2261 #define LRFDRFE_MAGNCTL0_PER_ALLONES 0x000000FFU 2262 #define LRFDRFE_MAGNCTL0_PER_ALLZEROS 0x00000000U 2263 2264 //***************************************************************************** 2265 // 2266 // Register: LRFDRFE_O_MAGNCTL1 2267 // 2268 //***************************************************************************** 2269 // Field: [12] PERMODE 2270 // 2271 // Measurement type 2272 // ENUMs: 2273 // PERIODIC Periodic mode 2274 // ONESHOT One-shot mode 2275 #define LRFDRFE_MAGNCTL1_PERMODE 0x00001000U 2276 #define LRFDRFE_MAGNCTL1_PERMODE_M 0x00001000U 2277 #define LRFDRFE_MAGNCTL1_PERMODE_S 12U 2278 #define LRFDRFE_MAGNCTL1_PERMODE_PERIODIC 0x00001000U 2279 #define LRFDRFE_MAGNCTL1_PERMODE_ONESHOT 0x00000000U 2280 2281 // Field: [11:8] SCL 2282 // 2283 // Scaling factor 2284 // 2285 // Scaling factor = 1/2^(SCL). 2286 // ENUMs: 2287 // DIV256 1/256 2288 // DIV128 1/128 2289 // DIV64 1/64 2290 // DIV32 1/32 2291 // DIV16 1/16 2292 // DIV8 2293 // DIV4 2294 // DIV2 2295 // DIV1 1/1 (no scaling) 2296 #define LRFDRFE_MAGNCTL1_SCL_W 4U 2297 #define LRFDRFE_MAGNCTL1_SCL_M 0x00000F00U 2298 #define LRFDRFE_MAGNCTL1_SCL_S 8U 2299 #define LRFDRFE_MAGNCTL1_SCL_DIV256 0x00000800U 2300 #define LRFDRFE_MAGNCTL1_SCL_DIV128 0x00000700U 2301 #define LRFDRFE_MAGNCTL1_SCL_DIV64 0x00000600U 2302 #define LRFDRFE_MAGNCTL1_SCL_DIV32 0x00000500U 2303 #define LRFDRFE_MAGNCTL1_SCL_DIV16 0x00000400U 2304 #define LRFDRFE_MAGNCTL1_SCL_DIV8 0x00000300U 2305 #define LRFDRFE_MAGNCTL1_SCL_DIV4 0x00000200U 2306 #define LRFDRFE_MAGNCTL1_SCL_DIV2 0x00000100U 2307 #define LRFDRFE_MAGNCTL1_SCL_DIV1 0x00000000U 2308 2309 // Field: [7:0] PER 2310 // 2311 // Accumulation period in incoming samples 2312 // ENUMs: 2313 // ALLONES All the bits are 1 2314 // ALLZEROS All the bits are 0 2315 #define LRFDRFE_MAGNCTL1_PER_W 8U 2316 #define LRFDRFE_MAGNCTL1_PER_M 0x000000FFU 2317 #define LRFDRFE_MAGNCTL1_PER_S 0U 2318 #define LRFDRFE_MAGNCTL1_PER_ALLONES 0x000000FFU 2319 #define LRFDRFE_MAGNCTL1_PER_ALLZEROS 0x00000000U 2320 2321 //***************************************************************************** 2322 // 2323 // Register: LRFDRFE_O_SPARE0 2324 // 2325 //***************************************************************************** 2326 // Field: [15:0] VAL 2327 // 2328 // Spare register for use by firmware 2329 // ENUMs: 2330 // ALLONES All the bits are 1 2331 // ALLZEROS All the bits are 0 2332 #define LRFDRFE_SPARE0_VAL_W 16U 2333 #define LRFDRFE_SPARE0_VAL_M 0x0000FFFFU 2334 #define LRFDRFE_SPARE0_VAL_S 0U 2335 #define LRFDRFE_SPARE0_VAL_ALLONES 0x0000FFFFU 2336 #define LRFDRFE_SPARE0_VAL_ALLZEROS 0x00000000U 2337 2338 //***************************************************************************** 2339 // 2340 // Register: LRFDRFE_O_SPARE1 2341 // 2342 //***************************************************************************** 2343 // Field: [15:0] VAL 2344 // 2345 // Spare register for use by firmware 2346 // ENUMs: 2347 // ALLONES All the bits are 1 2348 // ALLZEROS All the bits are 0 2349 #define LRFDRFE_SPARE1_VAL_W 16U 2350 #define LRFDRFE_SPARE1_VAL_M 0x0000FFFFU 2351 #define LRFDRFE_SPARE1_VAL_S 0U 2352 #define LRFDRFE_SPARE1_VAL_ALLONES 0x0000FFFFU 2353 #define LRFDRFE_SPARE1_VAL_ALLZEROS 0x00000000U 2354 2355 //***************************************************************************** 2356 // 2357 // Register: LRFDRFE_O_SPARE2 2358 // 2359 //***************************************************************************** 2360 // Field: [15:0] VAL 2361 // 2362 // Spare register for use by firmware 2363 // ENUMs: 2364 // ALLONES All the bits are 1 2365 // ALLZEROS All the bits are 0 2366 #define LRFDRFE_SPARE2_VAL_W 16U 2367 #define LRFDRFE_SPARE2_VAL_M 0x0000FFFFU 2368 #define LRFDRFE_SPARE2_VAL_S 0U 2369 #define LRFDRFE_SPARE2_VAL_ALLONES 0x0000FFFFU 2370 #define LRFDRFE_SPARE2_VAL_ALLZEROS 0x00000000U 2371 2372 //***************************************************************************** 2373 // 2374 // Register: LRFDRFE_O_SPARE3 2375 // 2376 //***************************************************************************** 2377 // Field: [15:0] VAL 2378 // 2379 // Spare register for use by firmware 2380 // ENUMs: 2381 // ALLONES All the bits are 1 2382 // ALLZEROS All the bits are 0 2383 #define LRFDRFE_SPARE3_VAL_W 16U 2384 #define LRFDRFE_SPARE3_VAL_M 0x0000FFFFU 2385 #define LRFDRFE_SPARE3_VAL_S 0U 2386 #define LRFDRFE_SPARE3_VAL_ALLONES 0x0000FFFFU 2387 #define LRFDRFE_SPARE3_VAL_ALLZEROS 0x00000000U 2388 2389 //***************************************************************************** 2390 // 2391 // Register: LRFDRFE_O_SPARE4 2392 // 2393 //***************************************************************************** 2394 // Field: [15:0] VAL 2395 // 2396 // Spare register for use by firmware 2397 // ENUMs: 2398 // ALLONES All the bits are 1 2399 // ALLZEROS All the bits are 0 2400 #define LRFDRFE_SPARE4_VAL_W 16U 2401 #define LRFDRFE_SPARE4_VAL_M 0x0000FFFFU 2402 #define LRFDRFE_SPARE4_VAL_S 0U 2403 #define LRFDRFE_SPARE4_VAL_ALLONES 0x0000FFFFU 2404 #define LRFDRFE_SPARE4_VAL_ALLZEROS 0x00000000U 2405 2406 //***************************************************************************** 2407 // 2408 // Register: LRFDRFE_O_SPARE5 2409 // 2410 //***************************************************************************** 2411 // Field: [15:0] VAL 2412 // 2413 // Spare register for use by firmware 2414 // ENUMs: 2415 // ALLONES All the bits are 1 2416 // ALLZEROS All the bits are 0 2417 #define LRFDRFE_SPARE5_VAL_W 16U 2418 #define LRFDRFE_SPARE5_VAL_M 0x0000FFFFU 2419 #define LRFDRFE_SPARE5_VAL_S 0U 2420 #define LRFDRFE_SPARE5_VAL_ALLONES 0x0000FFFFU 2421 #define LRFDRFE_SPARE5_VAL_ALLZEROS 0x00000000U 2422 2423 //***************************************************************************** 2424 // 2425 // Register: LRFDRFE_O_LNA 2426 // 2427 //***************************************************************************** 2428 // Field: [15:8] SPARE 2429 // 2430 // Spare bits to analog reserved for future use 2431 // ENUMs: 2432 // EN Enable IFAMP 2433 // DIS Disable IFAMP 2434 #define LRFDRFE_LNA_SPARE_W 8U 2435 #define LRFDRFE_LNA_SPARE_M 0x0000FF00U 2436 #define LRFDRFE_LNA_SPARE_S 8U 2437 #define LRFDRFE_LNA_SPARE_EN 0x00000100U 2438 #define LRFDRFE_LNA_SPARE_DIS 0x00000000U 2439 2440 // Field: [7:4] TRIM 2441 // 2442 // LNA trim 2443 // ENUMs: 2444 // ONES All bits are one 2445 // ZEROS All bits are zero 2446 #define LRFDRFE_LNA_TRIM_W 4U 2447 #define LRFDRFE_LNA_TRIM_M 0x000000F0U 2448 #define LRFDRFE_LNA_TRIM_S 4U 2449 #define LRFDRFE_LNA_TRIM_ONES 0x000000F0U 2450 #define LRFDRFE_LNA_TRIM_ZEROS 0x00000000U 2451 2452 // Field: [3] BIAS 2453 // 2454 // BIAS current selection 2455 // ENUMs: 2456 // INT IPTAT bias currents are from bias circuit inside 2457 // LRF_FRONTEND 2458 // BGAP IPTAT bias currents are from bandgap 2459 #define LRFDRFE_LNA_BIAS 0x00000008U 2460 #define LRFDRFE_LNA_BIAS_M 0x00000008U 2461 #define LRFDRFE_LNA_BIAS_S 3U 2462 #define LRFDRFE_LNA_BIAS_INT 0x00000008U 2463 #define LRFDRFE_LNA_BIAS_BGAP 0x00000000U 2464 2465 // Field: [2:1] IB 2466 // 2467 // LNA bias current control 2468 // 2469 // IB is trimmed at probe. Default is 1. 2470 // ENUMs: 2471 // MAX Maximum IB 2472 // MIN Minimum IB 2473 #define LRFDRFE_LNA_IB_W 2U 2474 #define LRFDRFE_LNA_IB_M 0x00000006U 2475 #define LRFDRFE_LNA_IB_S 1U 2476 #define LRFDRFE_LNA_IB_MAX 0x00000006U 2477 #define LRFDRFE_LNA_IB_MIN 0x00000000U 2478 2479 // Field: [0] EN 2480 // 2481 // LNA enable 2482 // ENUMs: 2483 // ON Enable LNA 2484 // OFF Disable LNA 2485 #define LRFDRFE_LNA_EN 0x00000001U 2486 #define LRFDRFE_LNA_EN_M 0x00000001U 2487 #define LRFDRFE_LNA_EN_S 0U 2488 #define LRFDRFE_LNA_EN_ON 0x00000001U 2489 #define LRFDRFE_LNA_EN_OFF 0x00000000U 2490 2491 //***************************************************************************** 2492 // 2493 // Register: LRFDRFE_O_IFAMPRFLDO 2494 // 2495 //***************************************************************************** 2496 // Field: [15:9] TRIM 2497 // 2498 // RFLDO output voltage trim 2499 // 2500 // Default value: 84 (1.3V), 127 = Bypass. 2501 // ENUMs: 2502 // BYPASS Regulator is in bypass mode 2503 // MAX Maximum output voltage 2504 // MIN Minimum output voltage 2505 #define LRFDRFE_IFAMPRFLDO_TRIM_W 7U 2506 #define LRFDRFE_IFAMPRFLDO_TRIM_M 0x0000FE00U 2507 #define LRFDRFE_IFAMPRFLDO_TRIM_S 9U 2508 #define LRFDRFE_IFAMPRFLDO_TRIM_BYPASS 0x0000FE00U 2509 #define LRFDRFE_IFAMPRFLDO_TRIM_MAX 0x0000FC00U 2510 #define LRFDRFE_IFAMPRFLDO_TRIM_MIN 0x00000000U 2511 2512 // Field: [8] EN 2513 // 2514 // Regulator enable 2515 // ENUMs: 2516 // EN Enable regulator 2517 // DIS Disable regulator 2518 #define LRFDRFE_IFAMPRFLDO_EN 0x00000100U 2519 #define LRFDRFE_IFAMPRFLDO_EN_M 0x00000100U 2520 #define LRFDRFE_IFAMPRFLDO_EN_S 8U 2521 #define LRFDRFE_IFAMPRFLDO_EN_EN 0x00000100U 2522 #define LRFDRFE_IFAMPRFLDO_EN_DIS 0x00000000U 2523 2524 // Field: [7:4] AAFCAP 2525 // 2526 // AAF capacitor control 2527 // ENUMs: 2528 // MAX Largest capacitance on IFAMP output. Low BW 2529 // MIN Smallest capacitance on IFAMP output. High BW. 2530 #define LRFDRFE_IFAMPRFLDO_AAFCAP_W 4U 2531 #define LRFDRFE_IFAMPRFLDO_AAFCAP_M 0x000000F0U 2532 #define LRFDRFE_IFAMPRFLDO_AAFCAP_S 4U 2533 #define LRFDRFE_IFAMPRFLDO_AAFCAP_MAX 0x000000F0U 2534 #define LRFDRFE_IFAMPRFLDO_AAFCAP_MIN 0x00000000U 2535 2536 // Field: [3:1] IFAMPIB 2537 // 2538 // IFAMP bias current control 2539 // 2540 // Default is 2. 2541 // ENUMs: 2542 // MAX Max IB 2543 // MIN Minimum IB 2544 #define LRFDRFE_IFAMPRFLDO_IFAMPIB_W 3U 2545 #define LRFDRFE_IFAMPRFLDO_IFAMPIB_M 0x0000000EU 2546 #define LRFDRFE_IFAMPRFLDO_IFAMPIB_S 1U 2547 #define LRFDRFE_IFAMPRFLDO_IFAMPIB_MAX 0x0000000EU 2548 #define LRFDRFE_IFAMPRFLDO_IFAMPIB_MIN 0x00000000U 2549 2550 // Field: [0] IFAMP 2551 // 2552 // IFAMP enable 2553 // ENUMs: 2554 // EN Enable IFAMP 2555 // DIS Disable IFAMP 2556 #define LRFDRFE_IFAMPRFLDO_IFAMP 0x00000001U 2557 #define LRFDRFE_IFAMPRFLDO_IFAMP_M 0x00000001U 2558 #define LRFDRFE_IFAMPRFLDO_IFAMP_S 0U 2559 #define LRFDRFE_IFAMPRFLDO_IFAMP_EN 0x00000001U 2560 #define LRFDRFE_IFAMPRFLDO_IFAMP_DIS 0x00000000U 2561 2562 //***************************************************************************** 2563 // 2564 // Register: LRFDRFE_O_PA0 2565 // 2566 //***************************************************************************** 2567 // Field: [15] SPARE15 2568 // 2569 // Reserved 2570 // ENUMs: 2571 // ONE Bit is one 2572 // ZERO Bit is 0 2573 #define LRFDRFE_PA0_SPARE15 0x00008000U 2574 #define LRFDRFE_PA0_SPARE15_M 0x00008000U 2575 #define LRFDRFE_PA0_SPARE15_S 15U 2576 #define LRFDRFE_PA0_SPARE15_ONE 0x00008000U 2577 #define LRFDRFE_PA0_SPARE15_ZERO 0x00000000U 2578 2579 // Field: [14] MODE 2580 // 2581 // PA power mode 2582 // ENUMs: 2583 // HIGH High power mode, max 8 dBm 2584 // LOW Low power mode, max 3 dBm 2585 #define LRFDRFE_PA0_MODE 0x00004000U 2586 #define LRFDRFE_PA0_MODE_M 0x00004000U 2587 #define LRFDRFE_PA0_MODE_S 14U 2588 #define LRFDRFE_PA0_MODE_HIGH 0x00004000U 2589 #define LRFDRFE_PA0_MODE_LOW 0x00000000U 2590 2591 // Field: [13:11] GAIN 2592 // 2593 // Gain control in 8dBm PA 1st stage 2594 // ENUMs: 2595 // MAX Maximum gain 2596 // MIN Minimum gain 2597 #define LRFDRFE_PA0_GAIN_W 3U 2598 #define LRFDRFE_PA0_GAIN_M 0x00003800U 2599 #define LRFDRFE_PA0_GAIN_S 11U 2600 #define LRFDRFE_PA0_GAIN_MAX 0x00003800U 2601 #define LRFDRFE_PA0_GAIN_MIN 0x00000000U 2602 2603 // Field: [10:5] IB 2604 // 2605 // PA power control 2606 // ENUMs: 2607 // MAX Maximum output power 2608 // MIN Minimum output power 2609 #define LRFDRFE_PA0_IB_W 6U 2610 #define LRFDRFE_PA0_IB_M 0x000007E0U 2611 #define LRFDRFE_PA0_IB_S 5U 2612 #define LRFDRFE_PA0_IB_MAX 0x000007E0U 2613 #define LRFDRFE_PA0_IB_MIN 0x00000000U 2614 2615 // Field: [4:0] TRIM 2616 // 2617 // Bias Current Trim 2618 // 2619 // Setting shall provide constant output power over process and temperature. 2620 // Current changes linearily with setting. 2621 // 2622 // Default value: 16 2623 // ENUMs: 2624 // MAX Maximum bias current 2625 // MIN Minimum bias current 2626 #define LRFDRFE_PA0_TRIM_W 5U 2627 #define LRFDRFE_PA0_TRIM_M 0x0000001FU 2628 #define LRFDRFE_PA0_TRIM_S 0U 2629 #define LRFDRFE_PA0_TRIM_MAX 0x0000001FU 2630 #define LRFDRFE_PA0_TRIM_MIN 0x00000000U 2631 2632 //***************************************************************************** 2633 // 2634 // Register: LRFDRFE_O_PA1 2635 // 2636 //***************************************************************************** 2637 // Field: [15:7] SPARE 2638 // 2639 // Spare bits to analog, reserved for future use. 2640 // ENUMs: 2641 // MAX Longest ramp time 2642 // MIN Shortest ramp time 2643 #define LRFDRFE_PA1_SPARE_W 9U 2644 #define LRFDRFE_PA1_SPARE_M 0x0000FF80U 2645 #define LRFDRFE_PA1_SPARE_S 7U 2646 #define LRFDRFE_PA1_SPARE_MAX 0x00000180U 2647 #define LRFDRFE_PA1_SPARE_MIN 0x00000000U 2648 2649 // Field: [6] MIXATST 2650 // 2651 // Control of mixer outputs through ATEST 2652 // ENUMs: 2653 // EN Mixers are available on ATEST 2654 // DIS Mixers are not available on ATEST 2655 #define LRFDRFE_PA1_MIXATST 0x00000040U 2656 #define LRFDRFE_PA1_MIXATST_M 0x00000040U 2657 #define LRFDRFE_PA1_MIXATST_S 6U 2658 #define LRFDRFE_PA1_MIXATST_EN 0x00000040U 2659 #define LRFDRFE_PA1_MIXATST_DIS 0x00000000U 2660 2661 // Field: [5] LDOITST 2662 // 2663 // Control of current test signal through ITEST 2664 // ENUMs: 2665 // EN Current test signal is available through ITEST 2666 // DIS Current test signal not available through ITEST 2667 #define LRFDRFE_PA1_LDOITST 0x00000020U 2668 #define LRFDRFE_PA1_LDOITST_M 0x00000020U 2669 #define LRFDRFE_PA1_LDOITST_S 5U 2670 #define LRFDRFE_PA1_LDOITST_EN 0x00000020U 2671 #define LRFDRFE_PA1_LDOITST_DIS 0x00000000U 2672 2673 // Field: [4] LDOATST 2674 // 2675 // Control of LDO output voltage through ATEST 2676 // ENUMs: 2677 // EN LDO output voltage is available through ATEST 2678 // DIS LDO output voltage not available through ATEST 2679 #define LRFDRFE_PA1_LDOATST 0x00000010U 2680 #define LRFDRFE_PA1_LDOATST_M 0x00000010U 2681 #define LRFDRFE_PA1_LDOATST_S 4U 2682 #define LRFDRFE_PA1_LDOATST_EN 0x00000010U 2683 #define LRFDRFE_PA1_LDOATST_DIS 0x00000000U 2684 2685 // Field: [3:2] RC 2686 // 2687 // Adjustment of on/off PA ramp time. 2688 // ENUMs: 2689 // MAX Longest ramp time 2690 // MIN Shortest ramp time 2691 #define LRFDRFE_PA1_RC_W 2U 2692 #define LRFDRFE_PA1_RC_M 0x0000000CU 2693 #define LRFDRFE_PA1_RC_S 2U 2694 #define LRFDRFE_PA1_RC_MAX 0x0000000CU 2695 #define LRFDRFE_PA1_RC_MIN 0x00000000U 2696 2697 // Field: [1] RAMP 2698 // 2699 // PA RAMP control 2700 // 2701 // Field can be set together with EN to ramp PA on. 2702 // Field must be cleared before EN to ramp PA down. 2703 // ENUMs: 2704 // UP Ramp up 2705 // DOWN Ramp down 2706 #define LRFDRFE_PA1_RAMP 0x00000002U 2707 #define LRFDRFE_PA1_RAMP_M 0x00000002U 2708 #define LRFDRFE_PA1_RAMP_S 1U 2709 #define LRFDRFE_PA1_RAMP_UP 0x00000002U 2710 #define LRFDRFE_PA1_RAMP_DOWN 0x00000000U 2711 2712 // Field: [0] EN 2713 // 2714 // PA enable 2715 // ENUMs: 2716 // EN Enable PA 2717 // DIS Disable PA 2718 #define LRFDRFE_PA1_EN 0x00000001U 2719 #define LRFDRFE_PA1_EN_M 0x00000001U 2720 #define LRFDRFE_PA1_EN_S 0U 2721 #define LRFDRFE_PA1_EN_EN 0x00000001U 2722 #define LRFDRFE_PA1_EN_DIS 0x00000000U 2723 2724 //***************************************************************************** 2725 // 2726 // Register: LRFDRFE_O_ULNA 2727 // 2728 //***************************************************************************** 2729 // Field: [15:0] SPARE 2730 // 2731 // Reserved for future use 2732 // ENUMs: 2733 // ALLONES All the bits are 1 2734 // ALLZEROS All the bits are 0 2735 #define LRFDRFE_ULNA_SPARE_W 16U 2736 #define LRFDRFE_ULNA_SPARE_M 0x0000FFFFU 2737 #define LRFDRFE_ULNA_SPARE_S 0U 2738 #define LRFDRFE_ULNA_SPARE_ALLONES 0x0000FFFFU 2739 #define LRFDRFE_ULNA_SPARE_ALLZEROS 0x00000000U 2740 2741 //***************************************************************************** 2742 // 2743 // Register: LRFDRFE_O_IFADC0 2744 // 2745 //***************************************************************************** 2746 // Field: [15] EXTCLK 2747 // 2748 // IFADC external clock control 2749 // 2750 // IFADC can use external clock from pad. 2751 // ENUMs: 2752 // EN The bit is 1 2753 // DIS The bit is 0 2754 #define LRFDRFE_IFADC0_EXTCLK 0x00008000U 2755 #define LRFDRFE_IFADC0_EXTCLK_M 0x00008000U 2756 #define LRFDRFE_IFADC0_EXTCLK_S 15U 2757 #define LRFDRFE_IFADC0_EXTCLK_EN 0x00008000U 2758 #define LRFDRFE_IFADC0_EXTCLK_DIS 0x00000000U 2759 2760 // Field: [14:12] DITHERTRIM 2761 // 2762 // Dither current trim 2763 // ENUMs: 2764 // ONES All the bits are 1 2765 // ZEROS All the bits are 0 2766 #define LRFDRFE_IFADC0_DITHERTRIM_W 3U 2767 #define LRFDRFE_IFADC0_DITHERTRIM_M 0x00007000U 2768 #define LRFDRFE_IFADC0_DITHERTRIM_S 12U 2769 #define LRFDRFE_IFADC0_DITHERTRIM_ONES 0x00007000U 2770 #define LRFDRFE_IFADC0_DITHERTRIM_ZEROS 0x00000000U 2771 2772 // Field: [11:10] DITHEREN 2773 // 2774 // Dither control 2775 // 2776 // Enable a random noise generator to inject weak pseudo random noise into the 2777 // ADC loop to randomize and smooth out possible idle tones. 2778 // NOTE: This field may only change during DTC-reset or while the clock is 2779 // inactive! 2780 // ENUMs: 2781 // ENG All the bits are 1 2782 // ENSD All the bits are 1 2783 // ENS All the bits are 1 2784 // DIS All the bits are 0 2785 #define LRFDRFE_IFADC0_DITHEREN_W 2U 2786 #define LRFDRFE_IFADC0_DITHEREN_M 0x00000C00U 2787 #define LRFDRFE_IFADC0_DITHEREN_S 10U 2788 #define LRFDRFE_IFADC0_DITHEREN_ENG 0x00000C00U 2789 #define LRFDRFE_IFADC0_DITHEREN_ENSD 0x00000800U 2790 #define LRFDRFE_IFADC0_DITHEREN_ENS 0x00000400U 2791 #define LRFDRFE_IFADC0_DITHEREN_DIS 0x00000000U 2792 2793 // Field: [9] ADCIEN 2794 // 2795 // I modulator control 2796 // ENUMs: 2797 // EN The bit is 1 2798 // DIS The bit is 0 2799 #define LRFDRFE_IFADC0_ADCIEN 0x00000200U 2800 #define LRFDRFE_IFADC0_ADCIEN_M 0x00000200U 2801 #define LRFDRFE_IFADC0_ADCIEN_S 9U 2802 #define LRFDRFE_IFADC0_ADCIEN_EN 0x00000200U 2803 #define LRFDRFE_IFADC0_ADCIEN_DIS 0x00000000U 2804 2805 // Field: [8] ADCQEN 2806 // 2807 // Q modulator control 2808 // ENUMs: 2809 // EN The bit is 1 2810 // DIS The bit is 0 2811 #define LRFDRFE_IFADC0_ADCQEN 0x00000100U 2812 #define LRFDRFE_IFADC0_ADCQEN_M 0x00000100U 2813 #define LRFDRFE_IFADC0_ADCQEN_S 8U 2814 #define LRFDRFE_IFADC0_ADCQEN_EN 0x00000100U 2815 #define LRFDRFE_IFADC0_ADCQEN_DIS 0x00000000U 2816 2817 // Field: [7:4] INT2ADJ 2818 // 2819 // GM trim 2820 // 2821 // Trims the gm cell for the second integrator. Larger value means lower gm. 2822 // ENUMs: 2823 // ONES All the bits are 1 2824 // ZEROS All the bits are 0 2825 #define LRFDRFE_IFADC0_INT2ADJ_W 4U 2826 #define LRFDRFE_IFADC0_INT2ADJ_M 0x000000F0U 2827 #define LRFDRFE_IFADC0_INT2ADJ_S 4U 2828 #define LRFDRFE_IFADC0_INT2ADJ_ONES 0x000000F0U 2829 #define LRFDRFE_IFADC0_INT2ADJ_ZEROS 0x00000000U 2830 2831 // Field: [3:2] AAFCAP 2832 // 2833 // AAF bandwidth trim 2834 // ENUMs: 2835 // ENG All the bits are 1 2836 // ENSD All the bits are 1 2837 // ENS All the bits are 1 2838 // DIS All the bits are 0 2839 #define LRFDRFE_IFADC0_AAFCAP_W 2U 2840 #define LRFDRFE_IFADC0_AAFCAP_M 0x0000000CU 2841 #define LRFDRFE_IFADC0_AAFCAP_S 2U 2842 #define LRFDRFE_IFADC0_AAFCAP_ENG 0x0000000CU 2843 #define LRFDRFE_IFADC0_AAFCAP_ENSD 0x00000008U 2844 #define LRFDRFE_IFADC0_AAFCAP_ENS 0x00000004U 2845 #define LRFDRFE_IFADC0_AAFCAP_DIS 0x00000000U 2846 2847 //***************************************************************************** 2848 // 2849 // Register: LRFDRFE_O_IFADC1 2850 // 2851 //***************************************************************************** 2852 // Field: [15] NRZ 2853 // 2854 // Internal feedback DAC mode 2855 // ENUMs: 2856 // EN The feedback DAC uses NRZ mode. (Default) 2857 // DIS The feedback DAC uses RZ mode 2858 #define LRFDRFE_IFADC1_NRZ 0x00008000U 2859 #define LRFDRFE_IFADC1_NRZ_M 0x00008000U 2860 #define LRFDRFE_IFADC1_NRZ_S 15U 2861 #define LRFDRFE_IFADC1_NRZ_EN 0x00008000U 2862 #define LRFDRFE_IFADC1_NRZ_DIS 0x00000000U 2863 2864 // Field: [14:9] TRIM 2865 // 2866 // Feedback DAC trim 2867 // 2868 // Larger trim means larger current. 2869 // ENUMs: 2870 // ONES All the bits are 1 2871 // ZEROS All the bits are 0 2872 #define LRFDRFE_IFADC1_TRIM_W 6U 2873 #define LRFDRFE_IFADC1_TRIM_M 0x00007E00U 2874 #define LRFDRFE_IFADC1_TRIM_S 9U 2875 #define LRFDRFE_IFADC1_TRIM_ONES 0x00007E00U 2876 #define LRFDRFE_IFADC1_TRIM_ZEROS 0x00000000U 2877 2878 // Field: [7] RSTN 2879 // 2880 // IFADC DTC reset 2881 // ENUMs: 2882 // DIS DTCs are not reset 2883 // EN DTCs are reset 2884 #define LRFDRFE_IFADC1_RSTN 0x00000080U 2885 #define LRFDRFE_IFADC1_RSTN_M 0x00000080U 2886 #define LRFDRFE_IFADC1_RSTN_S 7U 2887 #define LRFDRFE_IFADC1_RSTN_DIS 0x00000080U 2888 #define LRFDRFE_IFADC1_RSTN_EN 0x00000000U 2889 2890 // Field: [6] CLKGEN 2891 // 2892 // IFADC clock generator 2893 // ENUMs: 2894 // EN Internal clock generator module is enabled 2895 // DIS Internal clock generator module is disabled 2896 #define LRFDRFE_IFADC1_CLKGEN 0x00000040U 2897 #define LRFDRFE_IFADC1_CLKGEN_M 0x00000040U 2898 #define LRFDRFE_IFADC1_CLKGEN_S 6U 2899 #define LRFDRFE_IFADC1_CLKGEN_EN 0x00000040U 2900 #define LRFDRFE_IFADC1_CLKGEN_DIS 0x00000000U 2901 2902 // Field: [5] ADCDIGCLK 2903 // 2904 // IFADC clock to decimator 2905 // ENUMs: 2906 // EN Clock to decimator enabled 2907 // DIS Clock to decimator disabled 2908 #define LRFDRFE_IFADC1_ADCDIGCLK 0x00000020U 2909 #define LRFDRFE_IFADC1_ADCDIGCLK_M 0x00000020U 2910 #define LRFDRFE_IFADC1_ADCDIGCLK_S 5U 2911 #define LRFDRFE_IFADC1_ADCDIGCLK_EN 0x00000020U 2912 #define LRFDRFE_IFADC1_ADCDIGCLK_DIS 0x00000000U 2913 2914 // Field: [4] ADCLFSROUT 2915 // 2916 // ADC test mode 2917 // ENUMs: 2918 // EN The LFSR test output is connected to the ADC 2919 // output 2920 // DIS The quantizer output is connected to the ADC 2921 // output 2922 #define LRFDRFE_IFADC1_ADCLFSROUT 0x00000010U 2923 #define LRFDRFE_IFADC1_ADCLFSROUT_M 0x00000010U 2924 #define LRFDRFE_IFADC1_ADCLFSROUT_S 4U 2925 #define LRFDRFE_IFADC1_ADCLFSROUT_EN 0x00000010U 2926 #define LRFDRFE_IFADC1_ADCLFSROUT_DIS 0x00000000U 2927 2928 // Field: [3:1] LPFTSTMODE 2929 // 2930 // Currently not in use. For future test mode implementations. 2931 // ENUMs: 2932 // EN All the bits are 1 2933 // DIS All the bits are 0 2934 #define LRFDRFE_IFADC1_LPFTSTMODE_W 3U 2935 #define LRFDRFE_IFADC1_LPFTSTMODE_M 0x0000000EU 2936 #define LRFDRFE_IFADC1_LPFTSTMODE_S 1U 2937 #define LRFDRFE_IFADC1_LPFTSTMODE_EN 0x00000002U 2938 #define LRFDRFE_IFADC1_LPFTSTMODE_DIS 0x00000000U 2939 2940 // Field: [0] INVCLKOUT 2941 // 2942 // Control phase inversion of IFADC clock output 2943 // ENUMs: 2944 // EN Invert IFADC output clock phase (default) 2945 // DIS Keep default IFADC output clock phase 2946 #define LRFDRFE_IFADC1_INVCLKOUT 0x00000001U 2947 #define LRFDRFE_IFADC1_INVCLKOUT_M 0x00000001U 2948 #define LRFDRFE_IFADC1_INVCLKOUT_S 0U 2949 #define LRFDRFE_IFADC1_INVCLKOUT_EN 0x00000001U 2950 #define LRFDRFE_IFADC1_INVCLKOUT_DIS 0x00000000U 2951 2952 //***************************************************************************** 2953 // 2954 // Register: LRFDRFE_O_IFADCLF 2955 // 2956 //***************************************************************************** 2957 // Field: [15:12] FF3 2958 // 2959 // GM trim for the third feedforward cell 2960 // 2961 // Larger trim means lower gm. 2962 // ENUMs: 2963 // ONES All the bits are 1 2964 // ZEROS All the bits are 0 2965 #define LRFDRFE_IFADCLF_FF3_W 4U 2966 #define LRFDRFE_IFADCLF_FF3_M 0x0000F000U 2967 #define LRFDRFE_IFADCLF_FF3_S 12U 2968 #define LRFDRFE_IFADCLF_FF3_ONES 0x0000F000U 2969 #define LRFDRFE_IFADCLF_FF3_ZEROS 0x00000000U 2970 2971 // Field: [11:8] FF2 2972 // 2973 // GM trim for the second feedforward cell 2974 // 2975 // Larger trim means lower gm. 2976 // ENUMs: 2977 // ONES All the bits are 1 2978 // ZEROS All the bits are 0 2979 #define LRFDRFE_IFADCLF_FF2_W 4U 2980 #define LRFDRFE_IFADCLF_FF2_M 0x00000F00U 2981 #define LRFDRFE_IFADCLF_FF2_S 8U 2982 #define LRFDRFE_IFADCLF_FF2_ONES 0x00000F00U 2983 #define LRFDRFE_IFADCLF_FF2_ZEROS 0x00000000U 2984 2985 // Field: [7:4] FF1 2986 // 2987 // GM trim for the first feedforward cell 2988 // 2989 // Larger trim means lower gm. 2990 // ENUMs: 2991 // ONES All the bits are 1 2992 // ZEROS All the bits are 0 2993 #define LRFDRFE_IFADCLF_FF1_W 4U 2994 #define LRFDRFE_IFADCLF_FF1_M 0x000000F0U 2995 #define LRFDRFE_IFADCLF_FF1_S 4U 2996 #define LRFDRFE_IFADCLF_FF1_ONES 0x000000F0U 2997 #define LRFDRFE_IFADCLF_FF1_ZEROS 0x00000000U 2998 2999 // Field: [3:0] INT3 3000 // 3001 // GM trim for the third integrator 3002 // 3003 // Larger trim means lower gm. 3004 // ENUMs: 3005 // ONES All the bits are 1 3006 // ZEROS All the bits are 0 3007 #define LRFDRFE_IFADCLF_INT3_W 4U 3008 #define LRFDRFE_IFADCLF_INT3_M 0x0000000FU 3009 #define LRFDRFE_IFADCLF_INT3_S 0U 3010 #define LRFDRFE_IFADCLF_INT3_ONES 0x0000000FU 3011 #define LRFDRFE_IFADCLF_INT3_ZEROS 0x00000000U 3012 3013 //***************************************************************************** 3014 // 3015 // Register: LRFDRFE_O_IFADCQUANT 3016 // 3017 //***************************************************************************** 3018 // Field: [15:14] CLKDLYTRIM 3019 // 3020 // Currently not in use. 2 bit signal to program the clock delay in the clock 3021 // generator circuit. 3022 // ENUMs: 3023 // ONES All the bits are one 3024 // ZEROS All the bits are zero 3025 #define LRFDRFE_IFADCQUANT_CLKDLYTRIM_W 2U 3026 #define LRFDRFE_IFADCQUANT_CLKDLYTRIM_M 0x0000C000U 3027 #define LRFDRFE_IFADCQUANT_CLKDLYTRIM_S 14U 3028 #define LRFDRFE_IFADCQUANT_CLKDLYTRIM_ONES 0x0000C000U 3029 #define LRFDRFE_IFADCQUANT_CLKDLYTRIM_ZEROS 0x00000000U 3030 3031 // Field: [13:9] DBGCALVALIN 3032 // 3033 // Input test calibration value to quantizer calibration block, used in debug 3034 // mode. 3035 // ENUMs: 3036 // ONES All the bits are ONES 3037 // ZEROS All the bits are 0 3038 #define LRFDRFE_IFADCQUANT_DBGCALVALIN_W 5U 3039 #define LRFDRFE_IFADCQUANT_DBGCALVALIN_M 0x00003E00U 3040 #define LRFDRFE_IFADCQUANT_DBGCALVALIN_S 9U 3041 #define LRFDRFE_IFADCQUANT_DBGCALVALIN_ONES 0x00003E00U 3042 #define LRFDRFE_IFADCQUANT_DBGCALVALIN_ZEROS 0x00000000U 3043 3044 // Field: [8] DBGCALLEG 3045 // 3046 // Select which leg to observe in calibration debug mode 3047 // ENUMs: 3048 // NEG Negative leg 3049 // POS Positive leg 3050 #define LRFDRFE_IFADCQUANT_DBGCALLEG 0x00000100U 3051 #define LRFDRFE_IFADCQUANT_DBGCALLEG_M 0x00000100U 3052 #define LRFDRFE_IFADCQUANT_DBGCALLEG_S 8U 3053 #define LRFDRFE_IFADCQUANT_DBGCALLEG_NEG 0x00000100U 3054 #define LRFDRFE_IFADCQUANT_DBGCALLEG_POS 0x00000000U 3055 3056 // Field: [7:6] DBGCALMQ 3057 // 3058 // Quantizer calibration mode for Q modulator 3059 // 3060 // This signal should have a large stability window, and is for internal use 3061 // only! 3062 // ENUMs: 3063 // DBGCAL_QMODB UNCLEAR_Enable quantizer calibration mode. 3064 // DBGCAL_QMODP Enable quantizer calibration mode for Positive 3065 // comparator in Q modulator. 3066 // DBGCAL_QMODN Enable quantizer calibration mode for Negative 3067 // comparator in Q modulator. 3068 // DBGCAL_QMODZ Disable quantizer calibration mode.(Default) 3069 #define LRFDRFE_IFADCQUANT_DBGCALMQ_W 2U 3070 #define LRFDRFE_IFADCQUANT_DBGCALMQ_M 0x000000C0U 3071 #define LRFDRFE_IFADCQUANT_DBGCALMQ_S 6U 3072 #define LRFDRFE_IFADCQUANT_DBGCALMQ_DBGCAL_QMODB 0x000000C0U 3073 #define LRFDRFE_IFADCQUANT_DBGCALMQ_DBGCAL_QMODP 0x00000080U 3074 #define LRFDRFE_IFADCQUANT_DBGCALMQ_DBGCAL_QMODN 0x00000040U 3075 #define LRFDRFE_IFADCQUANT_DBGCALMQ_DBGCAL_QMODZ 0x00000000U 3076 3077 // Field: [5:4] DBGCALMI 3078 // 3079 // Quantizer calibration mode for I modulator. 3080 // 3081 // This signal should have a large stability window, and is for internal use 3082 // only! 3083 // ENUMs: 3084 // DBGCAL_IMODB UNCLEAR_Enable quantizer calibration mode. 3085 // DBGCAL_IMODP Enable quantizer calibration mode for Positive 3086 // comparator in I modulator. 3087 // DBGCAL_IMODN Enable quantizer calibration mode for Negative 3088 // comparator in I modulator. 3089 // DBGCAL_IMODZ Disable quantizer calibration mode.(Default) 3090 #define LRFDRFE_IFADCQUANT_DBGCALMI_W 2U 3091 #define LRFDRFE_IFADCQUANT_DBGCALMI_M 0x00000030U 3092 #define LRFDRFE_IFADCQUANT_DBGCALMI_S 4U 3093 #define LRFDRFE_IFADCQUANT_DBGCALMI_DBGCAL_IMODB 0x00000030U 3094 #define LRFDRFE_IFADCQUANT_DBGCALMI_DBGCAL_IMODP 0x00000020U 3095 #define LRFDRFE_IFADCQUANT_DBGCALMI_DBGCAL_IMODN 0x00000010U 3096 #define LRFDRFE_IFADCQUANT_DBGCALMI_DBGCAL_IMODZ 0x00000000U 3097 3098 // Field: [3] AUTOCAL 3099 // 3100 // Auto calibration 3101 // ENUMs: 3102 // EN Enable the auto calibration logic (Default) 3103 // DIS Disable the auto calibration logic 3104 #define LRFDRFE_IFADCQUANT_AUTOCAL 0x00000008U 3105 #define LRFDRFE_IFADCQUANT_AUTOCAL_M 0x00000008U 3106 #define LRFDRFE_IFADCQUANT_AUTOCAL_S 3U 3107 #define LRFDRFE_IFADCQUANT_AUTOCAL_EN 0x00000008U 3108 #define LRFDRFE_IFADCQUANT_AUTOCAL_DIS 0x00000000U 3109 3110 // Field: [2:0] QUANTTHR 3111 // 3112 // Quantizer treshold voltage trim 3113 // ENUMs: 3114 // ONES All the bits are 1 3115 // ZEROS All the bits are 0 3116 #define LRFDRFE_IFADCQUANT_QUANTTHR_W 3U 3117 #define LRFDRFE_IFADCQUANT_QUANTTHR_M 0x00000007U 3118 #define LRFDRFE_IFADCQUANT_QUANTTHR_S 0U 3119 #define LRFDRFE_IFADCQUANT_QUANTTHR_ONES 0x00000007U 3120 #define LRFDRFE_IFADCQUANT_QUANTTHR_ZEROS 0x00000000U 3121 3122 //***************************************************************************** 3123 // 3124 // Register: LRFDRFE_O_IFADCALDO 3125 // 3126 //***************************************************************************** 3127 // Field: [15] ATESTVSSANA 3128 // 3129 // Connect VSSANA to atest 3130 // ENUMs: 3131 // EN Connected 3132 // DIS Not connected 3133 #define LRFDRFE_IFADCALDO_ATESTVSSANA 0x00008000U 3134 #define LRFDRFE_IFADCALDO_ATESTVSSANA_M 0x00008000U 3135 #define LRFDRFE_IFADCALDO_ATESTVSSANA_S 15U 3136 #define LRFDRFE_IFADCALDO_ATESTVSSANA_EN 0x00008000U 3137 #define LRFDRFE_IFADCALDO_ATESTVSSANA_DIS 0x00000000U 3138 3139 // Field: [13:8] TRIMOUT 3140 // 3141 // Select which leg to observe in calibration debug mode 3142 // ENUMs: 3143 // ONES All the bits are one 3144 // ZEROS All the bits are zero 3145 #define LRFDRFE_IFADCALDO_TRIMOUT_W 6U 3146 #define LRFDRFE_IFADCALDO_TRIMOUT_M 0x00003F00U 3147 #define LRFDRFE_IFADCALDO_TRIMOUT_S 8U 3148 #define LRFDRFE_IFADCALDO_TRIMOUT_ONES 0x00003F00U 3149 #define LRFDRFE_IFADCALDO_TRIMOUT_ZEROS 0x00000000U 3150 3151 // Field: [7] DUMMY 3152 // 3153 // Enable dummy load to improve performance for low load currents 3154 // ENUMs: 3155 // EN Enabled 3156 // DIS Disabled 3157 #define LRFDRFE_IFADCALDO_DUMMY 0x00000080U 3158 #define LRFDRFE_IFADCALDO_DUMMY_M 0x00000080U 3159 #define LRFDRFE_IFADCALDO_DUMMY_S 7U 3160 #define LRFDRFE_IFADCALDO_DUMMY_EN 0x00000080U 3161 #define LRFDRFE_IFADCALDO_DUMMY_DIS 0x00000000U 3162 3163 // Field: [6] ATESTOUT 3164 // 3165 // Connect LDO output voltage to ATEST 3166 // ENUMs: 3167 // EN Enabled 3168 // DIS Disabled 3169 #define LRFDRFE_IFADCALDO_ATESTOUT 0x00000040U 3170 #define LRFDRFE_IFADCALDO_ATESTOUT_M 0x00000040U 3171 #define LRFDRFE_IFADCALDO_ATESTOUT_S 6U 3172 #define LRFDRFE_IFADCALDO_ATESTOUT_EN 0x00000040U 3173 #define LRFDRFE_IFADCALDO_ATESTOUT_DIS 0x00000000U 3174 3175 // Field: [5] ATSTLDOFB 3176 // 3177 // Connect LDO feedback to ATEST 3178 // ENUMs: 3179 // EN Enabled 3180 // DIS Disabled 3181 #define LRFDRFE_IFADCALDO_ATSTLDOFB 0x00000020U 3182 #define LRFDRFE_IFADCALDO_ATSTLDOFB_M 0x00000020U 3183 #define LRFDRFE_IFADCALDO_ATSTLDOFB_S 5U 3184 #define LRFDRFE_IFADCALDO_ATSTLDOFB_EN 0x00000020U 3185 #define LRFDRFE_IFADCALDO_ATSTLDOFB_DIS 0x00000000U 3186 3187 // Field: [4] ATESTERRAMP 3188 // 3189 // Connect the error amplifier output to ATEST 3190 // ENUMs: 3191 // EN Enabled 3192 // DIS Disabled 3193 #define LRFDRFE_IFADCALDO_ATESTERRAMP 0x00000010U 3194 #define LRFDRFE_IFADCALDO_ATESTERRAMP_M 0x00000010U 3195 #define LRFDRFE_IFADCALDO_ATESTERRAMP_S 4U 3196 #define LRFDRFE_IFADCALDO_ATESTERRAMP_EN 0x00000010U 3197 #define LRFDRFE_IFADCALDO_ATESTERRAMP_DIS 0x00000000U 3198 3199 // Field: [3] ITEST 3200 // 3201 // Connect test current to ATEST 3202 // ENUMs: 3203 // EN Enabled 3204 // DIS Disabled 3205 #define LRFDRFE_IFADCALDO_ITEST 0x00000008U 3206 #define LRFDRFE_IFADCALDO_ITEST_M 0x00000008U 3207 #define LRFDRFE_IFADCALDO_ITEST_S 3U 3208 #define LRFDRFE_IFADCALDO_ITEST_EN 0x00000008U 3209 #define LRFDRFE_IFADCALDO_ITEST_DIS 0x00000000U 3210 3211 // Field: [2] BYPASS 3212 // 3213 // Bypass LDO and short LDO output with vddana1p5v. The LDO needs to be enabled 3214 // to use bypass. 3215 // ENUMs: 3216 // EN Enabled 3217 // DIS Disabled 3218 #define LRFDRFE_IFADCALDO_BYPASS 0x00000004U 3219 #define LRFDRFE_IFADCALDO_BYPASS_M 0x00000004U 3220 #define LRFDRFE_IFADCALDO_BYPASS_S 2U 3221 #define LRFDRFE_IFADCALDO_BYPASS_EN 0x00000004U 3222 #define LRFDRFE_IFADCALDO_BYPASS_DIS 0x00000000U 3223 3224 // Field: [1] CLAMP 3225 // 3226 // Clamp the LDO output with diodes to ground 3227 // 3228 // Not used by analog when CTL or BYPASS are set. 3229 // ENUMs: 3230 // EN Enabled 3231 // DIS Disabled. The LDO output is shorted to ground when 3232 // disabled. 3233 #define LRFDRFE_IFADCALDO_CLAMP 0x00000002U 3234 #define LRFDRFE_IFADCALDO_CLAMP_M 0x00000002U 3235 #define LRFDRFE_IFADCALDO_CLAMP_S 1U 3236 #define LRFDRFE_IFADCALDO_CLAMP_EN 0x00000002U 3237 #define LRFDRFE_IFADCALDO_CLAMP_DIS 0x00000000U 3238 3239 // Field: [0] CTL 3240 // 3241 // Enable regulator for supplying analog domain of the adc 3242 // ENUMs: 3243 // EN Enabled 3244 // DIS Disabled 3245 #define LRFDRFE_IFADCALDO_CTL 0x00000001U 3246 #define LRFDRFE_IFADCALDO_CTL_M 0x00000001U 3247 #define LRFDRFE_IFADCALDO_CTL_S 0U 3248 #define LRFDRFE_IFADCALDO_CTL_EN 0x00000001U 3249 #define LRFDRFE_IFADCALDO_CTL_DIS 0x00000000U 3250 3251 //***************************************************************************** 3252 // 3253 // Register: LRFDRFE_O_IFADCDLDO 3254 // 3255 //***************************************************************************** 3256 // Field: [13:8] TRIMOUT 3257 // 3258 // Select which leg to observe in calibration debug mode 3259 // ENUMs: 3260 // ONES All the bits are one 3261 // ZEROS All the bits are zero 3262 #define LRFDRFE_IFADCDLDO_TRIMOUT_W 6U 3263 #define LRFDRFE_IFADCDLDO_TRIMOUT_M 0x00003F00U 3264 #define LRFDRFE_IFADCDLDO_TRIMOUT_S 8U 3265 #define LRFDRFE_IFADCDLDO_TRIMOUT_ONES 0x00003F00U 3266 #define LRFDRFE_IFADCDLDO_TRIMOUT_ZEROS 0x00000000U 3267 3268 // Field: [7] DUMMY 3269 // 3270 // Enable dummy load to improve performance for low load currents 3271 // ENUMs: 3272 // EN Enabled 3273 // DIS Disabled 3274 #define LRFDRFE_IFADCDLDO_DUMMY 0x00000080U 3275 #define LRFDRFE_IFADCDLDO_DUMMY_M 0x00000080U 3276 #define LRFDRFE_IFADCDLDO_DUMMY_S 7U 3277 #define LRFDRFE_IFADCDLDO_DUMMY_EN 0x00000080U 3278 #define LRFDRFE_IFADCDLDO_DUMMY_DIS 0x00000000U 3279 3280 // Field: [6] ATESTOUT 3281 // 3282 // Connect LDO output voltage to ATEST 3283 // ENUMs: 3284 // EN Enabled 3285 // DIS Disabled 3286 #define LRFDRFE_IFADCDLDO_ATESTOUT 0x00000040U 3287 #define LRFDRFE_IFADCDLDO_ATESTOUT_M 0x00000040U 3288 #define LRFDRFE_IFADCDLDO_ATESTOUT_S 6U 3289 #define LRFDRFE_IFADCDLDO_ATESTOUT_EN 0x00000040U 3290 #define LRFDRFE_IFADCDLDO_ATESTOUT_DIS 0x00000000U 3291 3292 // Field: [5] ATSTBGP 3293 // 3294 // Connect bandgap voltage to ATEST 3295 // ENUMs: 3296 // EN Enabled 3297 // DIS Disabled 3298 #define LRFDRFE_IFADCDLDO_ATSTBGP 0x00000020U 3299 #define LRFDRFE_IFADCDLDO_ATSTBGP_M 0x00000020U 3300 #define LRFDRFE_IFADCDLDO_ATSTBGP_S 5U 3301 #define LRFDRFE_IFADCDLDO_ATSTBGP_EN 0x00000020U 3302 #define LRFDRFE_IFADCDLDO_ATSTBGP_DIS 0x00000000U 3303 3304 // Field: [4] ATESTERRAMP 3305 // 3306 // Connect the error amplifier output to ATEST 3307 // ENUMs: 3308 // EN Enabled 3309 // DIS Disabled 3310 #define LRFDRFE_IFADCDLDO_ATESTERRAMP 0x00000010U 3311 #define LRFDRFE_IFADCDLDO_ATESTERRAMP_M 0x00000010U 3312 #define LRFDRFE_IFADCDLDO_ATESTERRAMP_S 4U 3313 #define LRFDRFE_IFADCDLDO_ATESTERRAMP_EN 0x00000010U 3314 #define LRFDRFE_IFADCDLDO_ATESTERRAMP_DIS 0x00000000U 3315 3316 // Field: [3] ITEST 3317 // 3318 // Connect test current to ATEST 3319 // ENUMs: 3320 // EN Enabled 3321 // DIS Disabled 3322 #define LRFDRFE_IFADCDLDO_ITEST 0x00000008U 3323 #define LRFDRFE_IFADCDLDO_ITEST_M 0x00000008U 3324 #define LRFDRFE_IFADCDLDO_ITEST_S 3U 3325 #define LRFDRFE_IFADCDLDO_ITEST_EN 0x00000008U 3326 #define LRFDRFE_IFADCDLDO_ITEST_DIS 0x00000000U 3327 3328 // Field: [2] BYPASS 3329 // 3330 // Bypass LDO and short LDO output with vddana1p5v. The LDO needs to be enabled 3331 // to use bypass. 3332 // ENUMs: 3333 // EN Enabled 3334 // DIS Disabled 3335 #define LRFDRFE_IFADCDLDO_BYPASS 0x00000004U 3336 #define LRFDRFE_IFADCDLDO_BYPASS_M 0x00000004U 3337 #define LRFDRFE_IFADCDLDO_BYPASS_S 2U 3338 #define LRFDRFE_IFADCDLDO_BYPASS_EN 0x00000004U 3339 #define LRFDRFE_IFADCDLDO_BYPASS_DIS 0x00000000U 3340 3341 // Field: [1] CLAMP 3342 // 3343 // Clamp the LDO output with diodes to ground 3344 // 3345 // Not used by analog when CTL or BYPASS are set. 3346 // ENUMs: 3347 // EN Enabled 3348 // DIS Disabled. The LDO output is shorted to ground when 3349 // disabled. 3350 #define LRFDRFE_IFADCDLDO_CLAMP 0x00000002U 3351 #define LRFDRFE_IFADCDLDO_CLAMP_M 0x00000002U 3352 #define LRFDRFE_IFADCDLDO_CLAMP_S 1U 3353 #define LRFDRFE_IFADCDLDO_CLAMP_EN 0x00000002U 3354 #define LRFDRFE_IFADCDLDO_CLAMP_DIS 0x00000000U 3355 3356 // Field: [0] CTL 3357 // 3358 // Enable regulator for supplying digital domain of the adc 3359 // ENUMs: 3360 // EN Enabled 3361 // DIS Disabled 3362 #define LRFDRFE_IFADCDLDO_CTL 0x00000001U 3363 #define LRFDRFE_IFADCDLDO_CTL_M 0x00000001U 3364 #define LRFDRFE_IFADCDLDO_CTL_S 0U 3365 #define LRFDRFE_IFADCDLDO_CTL_EN 0x00000001U 3366 #define LRFDRFE_IFADCDLDO_CTL_DIS 0x00000000U 3367 3368 //***************************************************************************** 3369 // 3370 // Register: LRFDRFE_O_IFADCTST 3371 // 3372 //***************************************************************************** 3373 // Field: [7] EXTCURR 3374 // 3375 // Drive an external current 3376 // ENUMs: 3377 // EN Enabled 3378 // DIS Disabled 3379 #define LRFDRFE_IFADCTST_EXTCURR 0x00000080U 3380 #define LRFDRFE_IFADCTST_EXTCURR_M 0x00000080U 3381 #define LRFDRFE_IFADCTST_EXTCURR_S 7U 3382 #define LRFDRFE_IFADCTST_EXTCURR_EN 0x00000080U 3383 #define LRFDRFE_IFADCTST_EXTCURR_DIS 0x00000000U 3384 3385 // Field: [6] QCALDBIQ 3386 // 3387 // Comparator select for calibration data output 3388 // 3389 // Also look at the description of IFADCQUANT. 3390 // ENUMs: 3391 // COMP1 I comparator 3392 // COMP0 Q Comparator 3393 #define LRFDRFE_IFADCTST_QCALDBIQ 0x00000040U 3394 #define LRFDRFE_IFADCTST_QCALDBIQ_M 0x00000040U 3395 #define LRFDRFE_IFADCTST_QCALDBIQ_S 6U 3396 #define LRFDRFE_IFADCTST_QCALDBIQ_COMP1 0x00000040U 3397 #define LRFDRFE_IFADCTST_QCALDBIQ_COMP0 0x00000000U 3398 3399 // Field: [5] QCALDBC 3400 // 3401 // Select which quantizer comparator to mux out calibration data from 3402 // ENUMs: 3403 // COMP1 I comparator 3404 // COMP0 Q Comparator 3405 #define LRFDRFE_IFADCTST_QCALDBC 0x00000020U 3406 #define LRFDRFE_IFADCTST_QCALDBC_M 0x00000020U 3407 #define LRFDRFE_IFADCTST_QCALDBC_S 5U 3408 #define LRFDRFE_IFADCTST_QCALDBC_COMP1 0x00000020U 3409 #define LRFDRFE_IFADCTST_QCALDBC_COMP0 0x00000000U 3410 3411 // Field: [4:0] SEL 3412 // 3413 // Select which internal net to probe via atb. This bus goes to a 6-32 bit 3414 // decoder. 3415 // ENUMs: 3416 // EXTCLKN1 External ADC clock through ADC_TEST_N (N1 3417 // internally). The the clock should be a 200MHz 3418 // sine wave (it is divided internally to 100MHz). 3419 // NONE ADC_TEST_P and ADC_TEST_N tristated (Default) 3420 #define LRFDRFE_IFADCTST_SEL_W 5U 3421 #define LRFDRFE_IFADCTST_SEL_M 0x0000001FU 3422 #define LRFDRFE_IFADCTST_SEL_S 0U 3423 #define LRFDRFE_IFADCTST_SEL_EXTCLKN1 0x0000001FU 3424 #define LRFDRFE_IFADCTST_SEL_NONE 0x00000000U 3425 3426 //***************************************************************************** 3427 // 3428 // Register: LRFDRFE_O_ATSTREFL 3429 // 3430 //***************************************************************************** 3431 // Field: [15:0] MUXLSB 3432 // 3433 // ATEST mux 0 control 3434 // ENUMs: 3435 // IFADC_ATB IFADC ATB 3436 // LDO_VTEST LDO_VTEST vtest out, current 3437 // LDO_ITEST LDO_ITEST itest out, current 3438 // PA_PEAK_OUTN PA peak detector output n 3439 // PA_PEAK_OUTP PA peak detector output p 3440 // MIX_OUTQN MIX outqn, voltage 3441 // MIX_OUTQP MIX outqp, voltage 3442 // MIX_OUTIN MIX outin, voltage 3443 // MIX_OUTIP MIX outip, voltage 3444 // FE_OUTIN_2 Frontend IF outin, voltage 3445 // FE_OUTIP_2 Frontend IF outip, voltage 3446 // FE_OUTQN Frontend IF outqn, voltage 3447 // FE_OUTQP Frontend IF outqp, voltage 3448 // FE_OUTIN Frontend IF outin, voltage 3449 // FE_OUTIP Frontend IF outip, voltage 3450 // DIS No atest selected 3451 #define LRFDRFE_ATSTREFL_MUXLSB_W 16U 3452 #define LRFDRFE_ATSTREFL_MUXLSB_M 0x0000FFFFU 3453 #define LRFDRFE_ATSTREFL_MUXLSB_S 0U 3454 #define LRFDRFE_ATSTREFL_MUXLSB_IFADC_ATB 0x00008000U 3455 #define LRFDRFE_ATSTREFL_MUXLSB_LDO_VTEST 0x00004000U 3456 #define LRFDRFE_ATSTREFL_MUXLSB_LDO_ITEST 0x00002000U 3457 #define LRFDRFE_ATSTREFL_MUXLSB_PA_PEAK_OUTN 0x00000800U 3458 #define LRFDRFE_ATSTREFL_MUXLSB_PA_PEAK_OUTP 0x00000400U 3459 #define LRFDRFE_ATSTREFL_MUXLSB_MIX_OUTQN 0x00000200U 3460 #define LRFDRFE_ATSTREFL_MUXLSB_MIX_OUTQP 0x00000100U 3461 #define LRFDRFE_ATSTREFL_MUXLSB_MIX_OUTIN 0x00000080U 3462 #define LRFDRFE_ATSTREFL_MUXLSB_MIX_OUTIP 0x00000040U 3463 #define LRFDRFE_ATSTREFL_MUXLSB_FE_OUTIN_2 0x00000020U 3464 #define LRFDRFE_ATSTREFL_MUXLSB_FE_OUTIP_2 0x00000010U 3465 #define LRFDRFE_ATSTREFL_MUXLSB_FE_OUTQN 0x00000008U 3466 #define LRFDRFE_ATSTREFL_MUXLSB_FE_OUTQP 0x00000004U 3467 #define LRFDRFE_ATSTREFL_MUXLSB_FE_OUTIN 0x00000002U 3468 #define LRFDRFE_ATSTREFL_MUXLSB_FE_OUTIP 0x00000001U 3469 #define LRFDRFE_ATSTREFL_MUXLSB_DIS 0x00000000U 3470 3471 //***************************************************************************** 3472 // 3473 // Register: LRFDRFE_O_ATSTREFH 3474 // 3475 //***************************************************************************** 3476 // Field: [15] VREFBPDIS 3477 // 3478 // Bandgap reference bypass control 3479 // ENUMs: 3480 // BPDIS Bandgap reference bypass disabled 3481 // BPEN Bandgap reference bypass enabled. 3482 #define LRFDRFE_ATSTREFH_VREFBPDIS 0x00008000U 3483 #define LRFDRFE_ATSTREFH_VREFBPDIS_M 0x00008000U 3484 #define LRFDRFE_ATSTREFH_VREFBPDIS_S 15U 3485 #define LRFDRFE_ATSTREFH_VREFBPDIS_BPDIS 0x00008000U 3486 #define LRFDRFE_ATSTREFH_VREFBPDIS_BPEN 0x00000000U 3487 3488 // Field: [14:10] IREFTRIM 3489 // 3490 // LRF bias current trim 3491 // ENUMs: 3492 // ONES All bits are ones 3493 // ZEROS All bits are zero 3494 #define LRFDRFE_ATSTREFH_IREFTRIM_W 5U 3495 #define LRFDRFE_ATSTREFH_IREFTRIM_M 0x00007C00U 3496 #define LRFDRFE_ATSTREFH_IREFTRIM_S 10U 3497 #define LRFDRFE_ATSTREFH_IREFTRIM_ONES 0x00007C00U 3498 #define LRFDRFE_ATSTREFH_IREFTRIM_ZEROS 0x00000000U 3499 3500 // Field: [9] BIAS 3501 // 3502 // LRF reference system control 3503 // ENUMs: 3504 // EN Enabled 3505 // DIS Disabled 3506 #define LRFDRFE_ATSTREFH_BIAS 0x00000200U 3507 #define LRFDRFE_ATSTREFH_BIAS_M 0x00000200U 3508 #define LRFDRFE_ATSTREFH_BIAS_S 9U 3509 #define LRFDRFE_ATSTREFH_BIAS_EN 0x00000200U 3510 #define LRFDRFE_ATSTREFH_BIAS_DIS 0x00000000U 3511 3512 // Field: [8] OUTPUT2 3513 // 3514 // ATEST output 2 control 3515 // ENUMs: 3516 // EN The output is enabled 3517 // DIS Output is disabled 3518 #define LRFDRFE_ATSTREFH_OUTPUT2 0x00000100U 3519 #define LRFDRFE_ATSTREFH_OUTPUT2_M 0x00000100U 3520 #define LRFDRFE_ATSTREFH_OUTPUT2_S 8U 3521 #define LRFDRFE_ATSTREFH_OUTPUT2_EN 0x00000100U 3522 #define LRFDRFE_ATSTREFH_OUTPUT2_DIS 0x00000000U 3523 3524 // Field: [7] OUTPUT1 3525 // 3526 // ATEST output 1 control 3527 // ENUMs: 3528 // EN The output is enabled 3529 // DIS Output is disabled 3530 #define LRFDRFE_ATSTREFH_OUTPUT1 0x00000080U 3531 #define LRFDRFE_ATSTREFH_OUTPUT1_M 0x00000080U 3532 #define LRFDRFE_ATSTREFH_OUTPUT1_S 7U 3533 #define LRFDRFE_ATSTREFH_OUTPUT1_EN 0x00000080U 3534 #define LRFDRFE_ATSTREFH_OUTPUT1_DIS 0x00000000U 3535 3536 // Field: [6:0] MUXMSB 3537 // 3538 // ATEST mux 2 control 3539 // ENUMs: 3540 // DIVBUF_NMOS_BIAS DIVBUF DC bias voltage for nmos switches 3541 // DIVBUF_PMOS_BIAS DIVBUF DC bias voltage for pmos switches 3542 // REFSYS_IREF REFSYS 4 uA output 3543 // IFADC_ATB IFADC ATB 3544 // DIS No atest selected 3545 #define LRFDRFE_ATSTREFH_MUXMSB_W 7U 3546 #define LRFDRFE_ATSTREFH_MUXMSB_M 0x0000007FU 3547 #define LRFDRFE_ATSTREFH_MUXMSB_S 0U 3548 #define LRFDRFE_ATSTREFH_MUXMSB_DIVBUF_NMOS_BIAS 0x00000010U 3549 #define LRFDRFE_ATSTREFH_MUXMSB_DIVBUF_PMOS_BIAS 0x00000008U 3550 #define LRFDRFE_ATSTREFH_MUXMSB_REFSYS_IREF 0x00000004U 3551 #define LRFDRFE_ATSTREFH_MUXMSB_IFADC_ATB 0x00000001U 3552 #define LRFDRFE_ATSTREFH_MUXMSB_DIS 0x00000000U 3553 3554 //***************************************************************************** 3555 // 3556 // Register: LRFDRFE_O_DCO 3557 // 3558 //***************************************************************************** 3559 // Field: [10:9] MTDCSPARE 3560 // 3561 // Spare bits to MTDC 3562 // ENUMs: 3563 // DIS DIVIDER = 4 (for test purposes only) 3564 // EN DIVIDER = 2 3565 #define LRFDRFE_DCO_MTDCSPARE_W 2U 3566 #define LRFDRFE_DCO_MTDCSPARE_M 0x00000600U 3567 #define LRFDRFE_DCO_MTDCSPARE_S 9U 3568 #define LRFDRFE_DCO_MTDCSPARE_DIS 0x00000200U 3569 #define LRFDRFE_DCO_MTDCSPARE_EN 0x00000000U 3570 3571 // Field: [8:7] SPARE7 3572 // 3573 // Spare 3574 // ENUMs: 3575 // ONE Bit is one 3576 // ZERO Bit is zero 3577 #define LRFDRFE_DCO_SPARE7_W 2U 3578 #define LRFDRFE_DCO_SPARE7_M 0x00000180U 3579 #define LRFDRFE_DCO_SPARE7_S 7U 3580 #define LRFDRFE_DCO_SPARE7_ONE 0x00000080U 3581 #define LRFDRFE_DCO_SPARE7_ZERO 0x00000000U 3582 3583 // Field: [6:3] TAILRESTRIM 3584 // 3585 // Trim bits to set DCO-amplitude. 3586 // 3587 // 0x0: Disable DCO 3588 // 0x1: Min DCO amplitude (min-current) 3589 // 0xF: Max DCO amplitude (max current) 3590 // ENUMs: 3591 // ALLONES All the bits are 1 3592 // ALLZEROS All the bits are 0 3593 #define LRFDRFE_DCO_TAILRESTRIM_W 4U 3594 #define LRFDRFE_DCO_TAILRESTRIM_M 0x00000078U 3595 #define LRFDRFE_DCO_TAILRESTRIM_S 3U 3596 #define LRFDRFE_DCO_TAILRESTRIM_ALLONES 0x00000078U 3597 #define LRFDRFE_DCO_TAILRESTRIM_ALLZEROS 0x00000000U 3598 3599 // Field: [2] RTRIMCAP 3600 // 3601 // RTRIM resistor cap control 3602 // 3603 // Field enables cap across RTRIM resistor. This can improve phase-noise in 3604 // some conditions, but can also result in DCO-instability (Not used). 3605 // 3606 // INTERNAL NOTE: 3607 // renamed from EN_BIAS_CAP 3608 // ENUMs: 3609 // EN Enable 3610 // DIS Disable(default) 3611 #define LRFDRFE_DCO_RTRIMCAP 0x00000004U 3612 #define LRFDRFE_DCO_RTRIMCAP_M 0x00000004U 3613 #define LRFDRFE_DCO_RTRIMCAP_S 2U 3614 #define LRFDRFE_DCO_RTRIMCAP_EN 0x00000004U 3615 #define LRFDRFE_DCO_RTRIMCAP_DIS 0x00000000U 3616 3617 // Field: [1] CNRCAP 3618 // 3619 // Corner-lots frequency tuning control 3620 // ENUMs: 3621 // _50MHZ 50 MHz 3622 // DEFAULT Default 3623 #define LRFDRFE_DCO_CNRCAP 0x00000002U 3624 #define LRFDRFE_DCO_CNRCAP_M 0x00000002U 3625 #define LRFDRFE_DCO_CNRCAP_S 1U 3626 #define LRFDRFE_DCO_CNRCAP__50MHZ 0x00000002U 3627 #define LRFDRFE_DCO_CNRCAP_DEFAULT 0x00000000U 3628 3629 // Field: [0] CRSCAPCM 3630 // 3631 // Coarse cap common mode control 3632 // 3633 // INTERNAL NOTE: 3634 // *renamed from CAP_CM 3635 // ENUMs: 3636 // REDUCED Reduced common mode for greater reliability 3637 // DEFAULT Default 3638 #define LRFDRFE_DCO_CRSCAPCM 0x00000001U 3639 #define LRFDRFE_DCO_CRSCAPCM_M 0x00000001U 3640 #define LRFDRFE_DCO_CRSCAPCM_S 0U 3641 #define LRFDRFE_DCO_CRSCAPCM_REDUCED 0x00000001U 3642 #define LRFDRFE_DCO_CRSCAPCM_DEFAULT 0x00000000U 3643 3644 //***************************************************************************** 3645 // 3646 // Register: LRFDRFE_O_DIV 3647 // 3648 //***************************************************************************** 3649 // Field: [15] PDET 3650 // 3651 // Adds 50mV to PM and NM bias voltages 3652 // ENUMs: 3653 // EN Peak detektor mode enabled, used in production 3654 // test 3655 // DIS Peak detector mode disabled, normal functional 3656 // mode 3657 #define LRFDRFE_DIV_PDET 0x00008000U 3658 #define LRFDRFE_DIV_PDET_M 0x00008000U 3659 #define LRFDRFE_DIV_PDET_S 15U 3660 #define LRFDRFE_DIV_PDET_EN 0x00008000U 3661 #define LRFDRFE_DIV_PDET_DIS 0x00000000U 3662 3663 // Field: [14:12] NMIREFTRIM 3664 // 3665 // Trim code for NMOS-Bias Voltage in the divider. 3666 // 3667 // 0x0: Min Speed 3668 // 0x7: Max Speed 3669 // 3670 // Default value: 0x4 3671 // ENUMs: 3672 // ALLONES All the bits are 1 3673 // ALLZEROS All the bits are 0 3674 #define LRFDRFE_DIV_NMIREFTRIM_W 3U 3675 #define LRFDRFE_DIV_NMIREFTRIM_M 0x00007000U 3676 #define LRFDRFE_DIV_NMIREFTRIM_S 12U 3677 #define LRFDRFE_DIV_NMIREFTRIM_ALLONES 0x00007000U 3678 #define LRFDRFE_DIV_NMIREFTRIM_ALLZEROS 0x00000000U 3679 3680 // Field: [11:9] PMIREFTRIM 3681 // 3682 // Trim code for PMOS-Bias Voltage in the divider. 3683 // 3684 // 0x0: Min Speed 3685 // 0x7: Max Speed 3686 // 3687 // Default value: 0x4 3688 // ENUMs: 3689 // ALLONES All the bits are 1 3690 // ALLZEROS All the bits are 0 3691 #define LRFDRFE_DIV_PMIREFTRIM_W 3U 3692 #define LRFDRFE_DIV_PMIREFTRIM_M 0x00000E00U 3693 #define LRFDRFE_DIV_PMIREFTRIM_S 9U 3694 #define LRFDRFE_DIV_PMIREFTRIM_ALLONES 0x00000E00U 3695 #define LRFDRFE_DIV_PMIREFTRIM_ALLZEROS 0x00000000U 3696 3697 // Field: [8] TXBBOOST 3698 // 3699 // Not connected 3700 // ENUMs: 3701 // INCREASED High drive strength 3702 // DEFAULT Default drive strength 3703 #define LRFDRFE_DIV_TXBBOOST 0x00000100U 3704 #define LRFDRFE_DIV_TXBBOOST_M 0x00000100U 3705 #define LRFDRFE_DIV_TXBBOOST_S 8U 3706 #define LRFDRFE_DIV_TXBBOOST_INCREASED 0x00000100U 3707 #define LRFDRFE_DIV_TXBBOOST_DEFAULT 0x00000000U 3708 3709 // Field: [7] S1GFRC 3710 // 3711 // Not connected 3712 // ENUMs: 3713 // EN Enable force S1G power switch 3714 // DIS Disable force S1G power switch 3715 #define LRFDRFE_DIV_S1GFRC 0x00000080U 3716 #define LRFDRFE_DIV_S1GFRC_M 0x00000080U 3717 #define LRFDRFE_DIV_S1GFRC_S 7U 3718 #define LRFDRFE_DIV_S1GFRC_EN 0x00000080U 3719 #define LRFDRFE_DIV_S1GFRC_DIS 0x00000000U 3720 3721 // Field: [6:5] BUFGAIN 3722 // 3723 // Not connected 3724 // ENUMs: 3725 // _60_PST 60% of maximum gain 3726 // DONT_USE Same as _80_PST 3727 // _80_PST 80% of maximum gain 3728 // MAX Maximum gain (default) 3729 #define LRFDRFE_DIV_BUFGAIN_W 2U 3730 #define LRFDRFE_DIV_BUFGAIN_M 0x00000060U 3731 #define LRFDRFE_DIV_BUFGAIN_S 5U 3732 #define LRFDRFE_DIV_BUFGAIN__60_PST 0x00000060U 3733 #define LRFDRFE_DIV_BUFGAIN_DONT_USE 0x00000040U 3734 #define LRFDRFE_DIV_BUFGAIN__80_PST 0x00000020U 3735 #define LRFDRFE_DIV_BUFGAIN_MAX 0x00000000U 3736 3737 // Field: [4] BIAS 3738 // 3739 // Not connected 3740 // ENUMs: 3741 // DEFAULT Default bias 3742 // ALTERNATIVE Alternative bias (for test purposes) 3743 #define LRFDRFE_DIV_BIAS 0x00000010U 3744 #define LRFDRFE_DIV_BIAS_M 0x00000010U 3745 #define LRFDRFE_DIV_BIAS_S 4U 3746 #define LRFDRFE_DIV_BIAS_DEFAULT 0x00000010U 3747 #define LRFDRFE_DIV_BIAS_ALTERNATIVE 0x00000000U 3748 3749 // Field: [3] OUT 3750 // 3751 // Divider output 3752 // 3753 // Enable divider outputs to either sub-1GHz front-end or to 2.4 GHz front-end 3754 // when any of the following equals ENABLE: 3755 // - DIVCTL.RXPH0DIV 3756 // - DIVCTL.RXPH90DIV 3757 // - DIVCTL.TXPH0DIV 3758 // - DIVCTL.TXPH180DIV 3759 // ENUMs: 3760 // FE_2G4 Enable outputs going to 2.4GHz front-end 3761 // FE_S1G Enable outputs going to sub-1GHz front-end 3762 #define LRFDRFE_DIV_OUT 0x00000008U 3763 #define LRFDRFE_DIV_OUT_M 0x00000008U 3764 #define LRFDRFE_DIV_OUT_S 3U 3765 #define LRFDRFE_DIV_OUT_FE_2G4 0x00000008U 3766 #define LRFDRFE_DIV_OUT_FE_S1G 0x00000000U 3767 3768 // Field: [2:0] RATIO 3769 // 3770 // Divider ratio 3771 // 3772 // Field sets the divider ratio between DCO frequency, FDCO, and radio 3773 // frequency, FRF. 3774 // 3775 // FRF = FDCO / DIVIDER 3776 // ENUMs: 3777 // DIV30 DIVIDER = 30 3778 // DIV15 DIVIDER = 15 3779 // DIV10 DIVIDER = 10 3780 // DIV5 DIVIDER = 5 3781 // DIV12 DIVIDER = 12 3782 // DIV6 DIVIDER = 6 3783 // DIV4 DIVIDER = 4 (for test purposes only) 3784 // DIV2 DIVIDER = 2 3785 #define LRFDRFE_DIV_RATIO_W 3U 3786 #define LRFDRFE_DIV_RATIO_M 0x00000007U 3787 #define LRFDRFE_DIV_RATIO_S 0U 3788 #define LRFDRFE_DIV_RATIO_DIV30 0x00000007U 3789 #define LRFDRFE_DIV_RATIO_DIV15 0x00000006U 3790 #define LRFDRFE_DIV_RATIO_DIV10 0x00000005U 3791 #define LRFDRFE_DIV_RATIO_DIV5 0x00000004U 3792 #define LRFDRFE_DIV_RATIO_DIV12 0x00000003U 3793 #define LRFDRFE_DIV_RATIO_DIV6 0x00000002U 3794 #define LRFDRFE_DIV_RATIO_DIV4 0x00000001U 3795 #define LRFDRFE_DIV_RATIO_DIV2 0x00000000U 3796 3797 //***************************************************************************** 3798 // 3799 // Register: LRFDRFE_O_DIVLDO 3800 // 3801 //***************************************************************************** 3802 // Field: [15] SPARE15 3803 // 3804 // Spare bit 3805 // ENUMs: 3806 // ONES All bits are one 3807 // ZEROS All bits are zero 3808 #define LRFDRFE_DIVLDO_SPARE15 0x00008000U 3809 #define LRFDRFE_DIVLDO_SPARE15_M 0x00008000U 3810 #define LRFDRFE_DIVLDO_SPARE15_S 15U 3811 #define LRFDRFE_DIVLDO_SPARE15_ONES 0x00008000U 3812 #define LRFDRFE_DIVLDO_SPARE15_ZEROS 0x00000000U 3813 3814 // Field: [14:8] VOUTTRIM 3815 // 3816 // VOUT trim code 3817 // ENUMs: 3818 // ONES All bits are one 3819 // ZEROS All bits are zero 3820 #define LRFDRFE_DIVLDO_VOUTTRIM_W 7U 3821 #define LRFDRFE_DIVLDO_VOUTTRIM_M 0x00007F00U 3822 #define LRFDRFE_DIVLDO_VOUTTRIM_S 8U 3823 #define LRFDRFE_DIVLDO_VOUTTRIM_ONES 0x00007F00U 3824 #define LRFDRFE_DIVLDO_VOUTTRIM_ZEROS 0x00000000U 3825 3826 // Field: [7] ITST 3827 // 3828 // ITEST block control 3829 // ENUMs: 3830 // EN Regulator is enabled 3831 // DIS Regulator is disabled 3832 #define LRFDRFE_DIVLDO_ITST 0x00000080U 3833 #define LRFDRFE_DIVLDO_ITST_M 0x00000080U 3834 #define LRFDRFE_DIVLDO_ITST_S 7U 3835 #define LRFDRFE_DIVLDO_ITST_EN 0x00000080U 3836 #define LRFDRFE_DIVLDO_ITST_DIS 0x00000000U 3837 3838 // Field: [6:4] TMUX 3839 // 3840 // TMUX control bits 3841 // ENUMs: 3842 // VDDR ATEST output is VDDR 3843 // LDO_OUT ATEST output is LDO output 3844 // GND ATEST output is grounded 3845 // OFF Normal mode 3846 #define LRFDRFE_DIVLDO_TMUX_W 3U 3847 #define LRFDRFE_DIVLDO_TMUX_M 0x00000070U 3848 #define LRFDRFE_DIVLDO_TMUX_S 4U 3849 #define LRFDRFE_DIVLDO_TMUX_VDDR 0x00000040U 3850 #define LRFDRFE_DIVLDO_TMUX_LDO_OUT 0x00000020U 3851 #define LRFDRFE_DIVLDO_TMUX_GND 0x00000010U 3852 #define LRFDRFE_DIVLDO_TMUX_OFF 0x00000000U 3853 3854 // Field: [3] SPARE3 3855 // 3856 // Spare bit 3857 // ENUMs: 3858 // ONE The bit is 1 3859 // ZERO The bit is 0 3860 #define LRFDRFE_DIVLDO_SPARE3 0x00000008U 3861 #define LRFDRFE_DIVLDO_SPARE3_M 0x00000008U 3862 #define LRFDRFE_DIVLDO_SPARE3_S 3U 3863 #define LRFDRFE_DIVLDO_SPARE3_ONE 0x00000008U 3864 #define LRFDRFE_DIVLDO_SPARE3_ZERO 0x00000000U 3865 3866 // Field: [2] MODE 3867 // 3868 // High BW operation control 3869 // ENUMs: 3870 // FAST Regulator in high bandwidth mode 3871 // NORM Regular low bandwidth of LDO 3872 #define LRFDRFE_DIVLDO_MODE 0x00000004U 3873 #define LRFDRFE_DIVLDO_MODE_M 0x00000004U 3874 #define LRFDRFE_DIVLDO_MODE_S 2U 3875 #define LRFDRFE_DIVLDO_MODE_FAST 0x00000004U 3876 #define LRFDRFE_DIVLDO_MODE_NORM 0x00000000U 3877 3878 // Field: [1] BYPASS 3879 // 3880 // Regulator bypass 3881 // ENUMs: 3882 // EN Regulator is bypassed 3883 // DIS No bypass 3884 #define LRFDRFE_DIVLDO_BYPASS 0x00000002U 3885 #define LRFDRFE_DIVLDO_BYPASS_M 0x00000002U 3886 #define LRFDRFE_DIVLDO_BYPASS_S 1U 3887 #define LRFDRFE_DIVLDO_BYPASS_EN 0x00000002U 3888 #define LRFDRFE_DIVLDO_BYPASS_DIS 0x00000000U 3889 3890 // Field: [0] CTL 3891 // 3892 // Regulator control 3893 // ENUMs: 3894 // EN Regulator is enabled 3895 // DIS Regulator is disabled 3896 #define LRFDRFE_DIVLDO_CTL 0x00000001U 3897 #define LRFDRFE_DIVLDO_CTL_M 0x00000001U 3898 #define LRFDRFE_DIVLDO_CTL_S 0U 3899 #define LRFDRFE_DIVLDO_CTL_EN 0x00000001U 3900 #define LRFDRFE_DIVLDO_CTL_DIS 0x00000000U 3901 3902 //***************************************************************************** 3903 // 3904 // Register: LRFDRFE_O_TDCLDO 3905 // 3906 //***************************************************************************** 3907 // Field: [15] ITESTCTL 3908 // 3909 // ITEST control 3910 // 3911 // When enabled, it is possible to check current thorugh PASSFET. Scaled down 3912 // 110:1 3913 // ENUMs: 3914 // EN ITEST enabled 3915 // DIS ITEST Disabled 3916 #define LRFDRFE_TDCLDO_ITESTCTL 0x00008000U 3917 #define LRFDRFE_TDCLDO_ITESTCTL_M 0x00008000U 3918 #define LRFDRFE_TDCLDO_ITESTCTL_S 15U 3919 #define LRFDRFE_TDCLDO_ITESTCTL_EN 0x00008000U 3920 #define LRFDRFE_TDCLDO_ITESTCTL_DIS 0x00000000U 3921 3922 // Field: [14:8] VOUTTRIM 3923 // 3924 // VOUT trim code 3925 // ENUMs: 3926 // ONES All bits are one 3927 // ZEROS All bits are zero 3928 #define LRFDRFE_TDCLDO_VOUTTRIM_W 7U 3929 #define LRFDRFE_TDCLDO_VOUTTRIM_M 0x00007F00U 3930 #define LRFDRFE_TDCLDO_VOUTTRIM_S 8U 3931 #define LRFDRFE_TDCLDO_VOUTTRIM_ONES 0x00007F00U 3932 #define LRFDRFE_TDCLDO_VOUTTRIM_ZEROS 0x00000000U 3933 3934 // Field: [7] ITESTBUFCTL 3935 // 3936 // ITEST BUFF block control 3937 // 3938 // When enabled, it is possible to check current through buffer, scaled down 3939 // 12:1. 3940 // ENUMs: 3941 // EN ITEST mode in buffer is enabled 3942 // DIS ITEST mode in buffer is disabled 3943 #define LRFDRFE_TDCLDO_ITESTBUFCTL 0x00000080U 3944 #define LRFDRFE_TDCLDO_ITESTBUFCTL_M 0x00000080U 3945 #define LRFDRFE_TDCLDO_ITESTBUFCTL_S 7U 3946 #define LRFDRFE_TDCLDO_ITESTBUFCTL_EN 0x00000080U 3947 #define LRFDRFE_TDCLDO_ITESTBUFCTL_DIS 0x00000000U 3948 3949 // Field: [6:4] TMUX 3950 // 3951 // TMUX control bits 3952 // ENUMs: 3953 // VSSA ATEST output is VSSA 3954 // LDO_OUT ATEST output is LDO output 3955 // VDDA ATEST output is VDDA 3956 // OFF Normal mode 3957 #define LRFDRFE_TDCLDO_TMUX_W 3U 3958 #define LRFDRFE_TDCLDO_TMUX_M 0x00000070U 3959 #define LRFDRFE_TDCLDO_TMUX_S 4U 3960 #define LRFDRFE_TDCLDO_TMUX_VSSA 0x00000040U 3961 #define LRFDRFE_TDCLDO_TMUX_LDO_OUT 0x00000020U 3962 #define LRFDRFE_TDCLDO_TMUX_VDDA 0x00000010U 3963 #define LRFDRFE_TDCLDO_TMUX_OFF 0x00000000U 3964 3965 // Field: [3] PDSEL 3966 // 3967 // Selects between resistor or diode stack PD 3968 // ENUMs: 3969 // DIODE Diode stack 3970 // R R (default) 3971 #define LRFDRFE_TDCLDO_PDSEL 0x00000008U 3972 #define LRFDRFE_TDCLDO_PDSEL_M 0x00000008U 3973 #define LRFDRFE_TDCLDO_PDSEL_S 3U 3974 #define LRFDRFE_TDCLDO_PDSEL_DIODE 0x00000008U 3975 #define LRFDRFE_TDCLDO_PDSEL_R 0x00000000U 3976 3977 // Field: [2] MODE 3978 // 3979 // High BW operation control 3980 // 3981 // Increase BW of slow loop (by increasing quiescent current). 3982 // ENUMs: 3983 // FAST Regulator in high bandwidth mode 3984 // NORM Regular low bandwidth of LDO 3985 #define LRFDRFE_TDCLDO_MODE 0x00000004U 3986 #define LRFDRFE_TDCLDO_MODE_M 0x00000004U 3987 #define LRFDRFE_TDCLDO_MODE_S 2U 3988 #define LRFDRFE_TDCLDO_MODE_FAST 0x00000004U 3989 #define LRFDRFE_TDCLDO_MODE_NORM 0x00000000U 3990 3991 // Field: [1] BYPASS 3992 // 3993 // Regulator bypass 3994 // ENUMs: 3995 // EN Regulator is bypassed 3996 // DIS No bypass 3997 #define LRFDRFE_TDCLDO_BYPASS 0x00000002U 3998 #define LRFDRFE_TDCLDO_BYPASS_M 0x00000002U 3999 #define LRFDRFE_TDCLDO_BYPASS_S 1U 4000 #define LRFDRFE_TDCLDO_BYPASS_EN 0x00000002U 4001 #define LRFDRFE_TDCLDO_BYPASS_DIS 0x00000000U 4002 4003 // Field: [0] CTL 4004 // 4005 // Regulator control 4006 // ENUMs: 4007 // EN Regulator is enabled 4008 // DIS Regulator is disabled 4009 #define LRFDRFE_TDCLDO_CTL 0x00000001U 4010 #define LRFDRFE_TDCLDO_CTL_M 0x00000001U 4011 #define LRFDRFE_TDCLDO_CTL_S 0U 4012 #define LRFDRFE_TDCLDO_CTL_EN 0x00000001U 4013 #define LRFDRFE_TDCLDO_CTL_DIS 0x00000000U 4014 4015 //***************************************************************************** 4016 // 4017 // Register: LRFDRFE_O_DCOLDO0 4018 // 4019 //***************************************************************************** 4020 // Field: [15:14] ITST 4021 // 4022 // ITEST block control 4023 // ENUMs: 4024 // BOTH Enable both pass transistors 4025 // SECOND Enable second pass transistor 4026 // FIRST Enable first pass transistor 4027 // DIS Regulator is disabled 4028 #define LRFDRFE_DCOLDO0_ITST_W 2U 4029 #define LRFDRFE_DCOLDO0_ITST_M 0x0000C000U 4030 #define LRFDRFE_DCOLDO0_ITST_S 14U 4031 #define LRFDRFE_DCOLDO0_ITST_BOTH 0x0000C000U 4032 #define LRFDRFE_DCOLDO0_ITST_SECOND 0x00008000U 4033 #define LRFDRFE_DCOLDO0_ITST_FIRST 0x00004000U 4034 #define LRFDRFE_DCOLDO0_ITST_DIS 0x00000000U 4035 4036 // Field: [13:8] SECONDTRIM 4037 // 4038 // Trim for second LDO 4039 // ENUMs: 4040 // ONES All bits are one 4041 // ZEROS All bits are zero 4042 #define LRFDRFE_DCOLDO0_SECONDTRIM_W 6U 4043 #define LRFDRFE_DCOLDO0_SECONDTRIM_M 0x00003F00U 4044 #define LRFDRFE_DCOLDO0_SECONDTRIM_S 8U 4045 #define LRFDRFE_DCOLDO0_SECONDTRIM_ONES 0x00003F00U 4046 #define LRFDRFE_DCOLDO0_SECONDTRIM_ZEROS 0x00000000U 4047 4048 // Field: [7:4] FIRSTTRIM 4049 // 4050 // TRIM for first LDO 4051 // ENUMs: 4052 // ONES All bits are one 4053 // ZEROS All bits are zero 4054 #define LRFDRFE_DCOLDO0_FIRSTTRIM_W 4U 4055 #define LRFDRFE_DCOLDO0_FIRSTTRIM_M 0x000000F0U 4056 #define LRFDRFE_DCOLDO0_FIRSTTRIM_S 4U 4057 #define LRFDRFE_DCOLDO0_FIRSTTRIM_ONES 0x000000F0U 4058 #define LRFDRFE_DCOLDO0_FIRSTTRIM_ZEROS 0x00000000U 4059 4060 // Field: [3] PDN 4061 // 4062 // Pulldown control 4063 // ENUMs: 4064 // EN Pulldown 4065 // DIS No Pulldown 4066 #define LRFDRFE_DCOLDO0_PDN 0x00000008U 4067 #define LRFDRFE_DCOLDO0_PDN_M 0x00000008U 4068 #define LRFDRFE_DCOLDO0_PDN_S 3U 4069 #define LRFDRFE_DCOLDO0_PDN_EN 0x00000008U 4070 #define LRFDRFE_DCOLDO0_PDN_DIS 0x00000000U 4071 4072 // Field: [2] BYPFIRST 4073 // 4074 // Bypass first regulator 4075 // ENUMs: 4076 // EN Regulator is bypassed 4077 // DIS No bypass 4078 #define LRFDRFE_DCOLDO0_BYPFIRST 0x00000004U 4079 #define LRFDRFE_DCOLDO0_BYPFIRST_M 0x00000004U 4080 #define LRFDRFE_DCOLDO0_BYPFIRST_S 2U 4081 #define LRFDRFE_DCOLDO0_BYPFIRST_EN 0x00000004U 4082 #define LRFDRFE_DCOLDO0_BYPFIRST_DIS 0x00000000U 4083 4084 // Field: [1] BYPBOTH 4085 // 4086 // Bypass LDO (both) 4087 // ENUMs: 4088 // EN Regulator is bypassed 4089 // DIS No bypass 4090 #define LRFDRFE_DCOLDO0_BYPBOTH 0x00000002U 4091 #define LRFDRFE_DCOLDO0_BYPBOTH_M 0x00000002U 4092 #define LRFDRFE_DCOLDO0_BYPBOTH_S 1U 4093 #define LRFDRFE_DCOLDO0_BYPBOTH_EN 0x00000002U 4094 #define LRFDRFE_DCOLDO0_BYPBOTH_DIS 0x00000000U 4095 4096 // Field: [0] CTL 4097 // 4098 // Regulator control 4099 // ENUMs: 4100 // EN Regulator is enabled 4101 // DIS Regulator is disabled 4102 #define LRFDRFE_DCOLDO0_CTL 0x00000001U 4103 #define LRFDRFE_DCOLDO0_CTL_M 0x00000001U 4104 #define LRFDRFE_DCOLDO0_CTL_S 0U 4105 #define LRFDRFE_DCOLDO0_CTL_EN 0x00000001U 4106 #define LRFDRFE_DCOLDO0_CTL_DIS 0x00000000U 4107 4108 //***************************************************************************** 4109 // 4110 // Register: LRFDRFE_O_DCOLDO1 4111 // 4112 //***************************************************************************** 4113 // Field: [10] REFSRC 4114 // 4115 // Select clock source to PLL 4116 // ENUMs: 4117 // BAW PLL clock source is BAW 4118 // XTAL PLL clock source is XTAL 4119 #define LRFDRFE_DCOLDO1_REFSRC 0x00000400U 4120 #define LRFDRFE_DCOLDO1_REFSRC_M 0x00000400U 4121 #define LRFDRFE_DCOLDO1_REFSRC_S 10U 4122 #define LRFDRFE_DCOLDO1_REFSRC_BAW 0x00000400U 4123 #define LRFDRFE_DCOLDO1_REFSRC_XTAL 0x00000000U 4124 4125 // Field: [9:8] DIVATST 4126 // 4127 // Divider ATEST control 4128 // ENUMs: 4129 // ONES All bits are one 4130 // ZEROS All bits are zero 4131 #define LRFDRFE_DCOLDO1_DIVATST_W 2U 4132 #define LRFDRFE_DCOLDO1_DIVATST_M 0x00000300U 4133 #define LRFDRFE_DCOLDO1_DIVATST_S 8U 4134 #define LRFDRFE_DCOLDO1_DIVATST_ONES 0x00000300U 4135 #define LRFDRFE_DCOLDO1_DIVATST_ZEROS 0x00000000U 4136 4137 // Field: [7] PERFM 4138 // 4139 // Performance mode control 4140 // 4141 // When enabled, the LDO uses more current to reduce flicker noise. 4142 // ENUMs: 4143 // EN Enabled (performance) 4144 // DIS Disabled (normal) 4145 #define LRFDRFE_DCOLDO1_PERFM 0x00000080U 4146 #define LRFDRFE_DCOLDO1_PERFM_M 0x00000080U 4147 #define LRFDRFE_DCOLDO1_PERFM_S 7U 4148 #define LRFDRFE_DCOLDO1_PERFM_EN 0x00000080U 4149 #define LRFDRFE_DCOLDO1_PERFM_DIS 0x00000000U 4150 4151 // Field: [6] CHRGFILT 4152 // 4153 // Charge the filters 4154 // ENUMs: 4155 // EN Charging enabled 4156 // DIS Charging disabled, normal operation 4157 #define LRFDRFE_DCOLDO1_CHRGFILT 0x00000040U 4158 #define LRFDRFE_DCOLDO1_CHRGFILT_M 0x00000040U 4159 #define LRFDRFE_DCOLDO1_CHRGFILT_S 6U 4160 #define LRFDRFE_DCOLDO1_CHRGFILT_EN 0x00000040U 4161 #define LRFDRFE_DCOLDO1_CHRGFILT_DIS 0x00000000U 4162 4163 // Field: [5:0] ATST 4164 // 4165 // ATEST block control 4166 // ENUMs: 4167 // VSSANA VSSANA 4168 // FIRST_OUT First LDO output 4169 // LDO_OUT LDO output 4170 #define LRFDRFE_DCOLDO1_ATST_W 6U 4171 #define LRFDRFE_DCOLDO1_ATST_M 0x0000003FU 4172 #define LRFDRFE_DCOLDO1_ATST_S 0U 4173 #define LRFDRFE_DCOLDO1_ATST_VSSANA 0x00000020U 4174 #define LRFDRFE_DCOLDO1_ATST_FIRST_OUT 0x00000001U 4175 #define LRFDRFE_DCOLDO1_ATST_LDO_OUT 0x00000000U 4176 4177 //***************************************************************************** 4178 // 4179 // Register: LRFDRFE_O_PRE0 4180 // 4181 //***************************************************************************** 4182 // Field: [15:14] SPARE14 4183 // 4184 // SPARE14 4185 // ENUMs: 4186 // ALLONES All the bits are 1 4187 // ALLZEROS All the bits are 0 4188 #define LRFDRFE_PRE0_SPARE14_W 2U 4189 #define LRFDRFE_PRE0_SPARE14_M 0x0000C000U 4190 #define LRFDRFE_PRE0_SPARE14_S 14U 4191 #define LRFDRFE_PRE0_SPARE14_ALLONES 0x0000C000U 4192 #define LRFDRFE_PRE0_SPARE14_ALLZEROS 0x00000000U 4193 4194 // Field: [13:8] PLLDIV1 4195 // 4196 // PLL reference frequency divider 1 4197 // 4198 // The value of DLOCTL0.LOOPUPD decides if this reference frequency is used. 4199 // 4200 // FREFCLK = FXTAL / PLLDIV1 4201 // 4202 // Examples: 4203 // 0: Illegal setting 4204 // 1: Illegal setting 4205 // 2: Divide by 2 4206 // ... 4207 // 63: Divide by 63 4208 // 4209 // FREFCLK must be higher than or equal to 1 MHz in closed-loop state. 4210 // ENUMs: 4211 // ALLONES All the bits are 1 4212 // ALLZEROS All the bits are 0 4213 #define LRFDRFE_PRE0_PLLDIV1_W 6U 4214 #define LRFDRFE_PRE0_PLLDIV1_M 0x00003F00U 4215 #define LRFDRFE_PRE0_PLLDIV1_S 8U 4216 #define LRFDRFE_PRE0_PLLDIV1_ALLONES 0x00003F00U 4217 #define LRFDRFE_PRE0_PLLDIV1_ALLZEROS 0x00000000U 4218 4219 // Field: [7:6] SPARE6 4220 // 4221 // SPARE6 4222 // ENUMs: 4223 // ALLONES All the bits are 1 4224 // ALLZEROS All the bits are 0 4225 #define LRFDRFE_PRE0_SPARE6_W 2U 4226 #define LRFDRFE_PRE0_SPARE6_M 0x000000C0U 4227 #define LRFDRFE_PRE0_SPARE6_S 6U 4228 #define LRFDRFE_PRE0_SPARE6_ALLONES 0x000000C0U 4229 #define LRFDRFE_PRE0_SPARE6_ALLZEROS 0x00000000U 4230 4231 // Field: [5:0] PLLDIV0 4232 // 4233 // PLL reference frequency divider 0 4234 // 4235 // The value of DLOCTL0.LOOPUPD decides if this reference frequency is used. 4236 // 4237 // FREFCLK = FXTAL / PLLDIV0 4238 // 4239 // Examples: 4240 // 0: Illegal setting 4241 // 1: Illegal setting 4242 // 2: Divide by 2 4243 // ... 4244 // 63: Divide by 63 4245 // 4246 // FREFCLK must be higher than or equal to 1 MHz in closed-loop state. 4247 // ENUMs: 4248 // ALLONES All the bits are 1 4249 // ALLZEROS All the bits are 0 4250 #define LRFDRFE_PRE0_PLLDIV0_W 6U 4251 #define LRFDRFE_PRE0_PLLDIV0_M 0x0000003FU 4252 #define LRFDRFE_PRE0_PLLDIV0_S 0U 4253 #define LRFDRFE_PRE0_PLLDIV0_ALLONES 0x0000003FU 4254 #define LRFDRFE_PRE0_PLLDIV0_ALLZEROS 0x00000000U 4255 4256 //***************************************************************************** 4257 // 4258 // Register: LRFDRFE_O_PRE1 4259 // 4260 //***************************************************************************** 4261 // Field: [15:14] IIRBW 4262 // 4263 // Loop IIR filter bandwidth 4264 // ENUMs: 4265 // K16 K=16 4266 // K8 4267 // K4 4268 // K2 4269 #define LRFDRFE_PRE1_IIRBW_W 2U 4270 #define LRFDRFE_PRE1_IIRBW_M 0x0000C000U 4271 #define LRFDRFE_PRE1_IIRBW_S 14U 4272 #define LRFDRFE_PRE1_IIRBW_K16 0x0000C000U 4273 #define LRFDRFE_PRE1_IIRBW_K8 0x00008000U 4274 #define LRFDRFE_PRE1_IIRBW_K4 0x00004000U 4275 #define LRFDRFE_PRE1_IIRBW_K2 0x00000000U 4276 4277 // Field: [13] IIRORD 4278 // 4279 // IIR order 4280 // ENUMs: 4281 // SECOND Select second order IIR filter 4282 // FIRST Select first order IIR filter 4283 #define LRFDRFE_PRE1_IIRORD 0x00002000U 4284 #define LRFDRFE_PRE1_IIRORD_M 0x00002000U 4285 #define LRFDRFE_PRE1_IIRORD_S 13U 4286 #define LRFDRFE_PRE1_IIRORD_SECOND 0x00002000U 4287 #define LRFDRFE_PRE1_IIRORD_FIRST 0x00000000U 4288 4289 // Field: [12:8] IIRDIV 4290 // 4291 // IIR divider 4292 // 4293 // FIIRCLK = FCKVD64 / (IIRDIV+1) 4294 // 4295 // Examples: 4296 // 4297 // 0: Clock is ckvd64/1 4298 // 1: Clock is ckvd64/2 4299 // ... 4300 // 31: Clock is ckvd64/32 4301 // 4302 // INTERNAL NOTE: 4303 // * See the implementation spec for formula. 4304 // ENUMs: 4305 // ALLONES All the bits are 1 4306 // ALLZEROS All the bits are 0 4307 #define LRFDRFE_PRE1_IIRDIV_W 5U 4308 #define LRFDRFE_PRE1_IIRDIV_M 0x00001F00U 4309 #define LRFDRFE_PRE1_IIRDIV_S 8U 4310 #define LRFDRFE_PRE1_IIRDIV_ALLONES 0x00001F00U 4311 #define LRFDRFE_PRE1_IIRDIV_ALLZEROS 0x00000000U 4312 4313 // Field: [6] CALHSDDC 4314 // 4315 // TDC calibration setting for HSDDC 4316 // ENUMs: 4317 // GATE Duty-cycling given by HSDDC 4318 // NOGATE No duty-cycling 4319 #define LRFDRFE_PRE1_CALHSDDC 0x00000040U 4320 #define LRFDRFE_PRE1_CALHSDDC_M 0x00000040U 4321 #define LRFDRFE_PRE1_CALHSDDC_S 6U 4322 #define LRFDRFE_PRE1_CALHSDDC_GATE 0x00000040U 4323 #define LRFDRFE_PRE1_CALHSDDC_NOGATE 0x00000000U 4324 4325 // Field: [5:0] HSDDC 4326 // 4327 // TDC high-speed digital duty cycle 4328 // 4329 // The TDC high-speed clock can always run or be duty cycled to save current 4330 // consumption. The minimum ON-time equals the reference clock source period 4331 // (PER). In this case, the clock starts to toggle 1/2 * PER before positive 4332 // edge of reference clock. If the clock runs for two periods, it starts to 4333 // toggle 1.5 * PER before the positve edge of the reference clock. In any 4334 // case, it toggles during the high time of reference clock source. 4335 // 4336 // The field value must not be set higher than the minimum binary value of the 4337 // active reference clock divider. 4338 // 4339 // Encoding: 4340 // 0: Enable clock to TDC always 4341 // 1: Enable clock to TDC always 4342 // 2: Enable clock to TDC for 1 PER 4343 // 3. Enable clock to TDC for 2 PER 4344 // ... 4345 // 63: Enable clock to TDC for 62 PER 4346 // 4347 // INTERNAL NOTE: 4348 // * Value of 2 shall be used to save current consumption as long as there is 4349 // no or acceptable power noise/TDC modulation generated by this setting. 4350 // ENUMs: 4351 // ALLONES All the bits are 1 4352 // ALLZEROS All the bits are 0 4353 #define LRFDRFE_PRE1_HSDDC_W 6U 4354 #define LRFDRFE_PRE1_HSDDC_M 0x0000003FU 4355 #define LRFDRFE_PRE1_HSDDC_S 0U 4356 #define LRFDRFE_PRE1_HSDDC_ALLONES 0x0000003FU 4357 #define LRFDRFE_PRE1_HSDDC_ALLZEROS 0x00000000U 4358 4359 //***************************************************************************** 4360 // 4361 // Register: LRFDRFE_O_PRE2 4362 // 4363 //***************************************************************************** 4364 // Field: [15:12] MIDCALDIVLSB 4365 // 4366 // Mid calibration divider LSB 4367 // 4368 // This field determines the reference frequency used during the mid SAR 4369 // calibration stages, according to: 4370 // 4371 // FREFCLK = FXTAL / MIDCALDIV 4372 // 4373 // Field encoding is unsigned integer: 4374 // 0-7: Illegal setting 4375 // 8: Divide by 8 4376 // 9: Divide by 9 4377 // .. 4378 // 1023: Divide by 1023 4379 // ENUMs: 4380 // ALLONES All the bits are 1 4381 // ALLZEROS All the bits are 0 4382 #define LRFDRFE_PRE2_MIDCALDIVLSB_W 4U 4383 #define LRFDRFE_PRE2_MIDCALDIVLSB_M 0x0000F000U 4384 #define LRFDRFE_PRE2_MIDCALDIVLSB_S 12U 4385 #define LRFDRFE_PRE2_MIDCALDIVLSB_ALLONES 0x0000F000U 4386 #define LRFDRFE_PRE2_MIDCALDIVLSB_ALLZEROS 0x00000000U 4387 4388 // Field: [11:6] CRSCALDIV 4389 // 4390 // Coarse calibration divider 4391 // 4392 // This field determines the reference frequency used during the coarse SAR 4393 // calibration stages, according to: 4394 // 4395 // FREFCLK = FXTAL / CRSCALDIV 4396 // 4397 // Field encoding is unsigned integer: 4398 // 0-7: Illegal setting 4399 // 8: Divide by 8 4400 // 9: Divide by 9 4401 // .. 4402 // 63: Divide by 63 4403 // ENUMs: 4404 // ALLONES All the bits are 1 4405 // ALLZEROS All the bits are 0 4406 #define LRFDRFE_PRE2_CRSCALDIV_W 6U 4407 #define LRFDRFE_PRE2_CRSCALDIV_M 0x00000FC0U 4408 #define LRFDRFE_PRE2_CRSCALDIV_S 6U 4409 #define LRFDRFE_PRE2_CRSCALDIV_ALLONES 0x00000FC0U 4410 #define LRFDRFE_PRE2_CRSCALDIV_ALLZEROS 0x00000000U 4411 4412 // Field: [5:0] FSMDIV 4413 // 4414 // FSM divider 4415 // 4416 // This field determines the clock frequency for FSM traversal through states 4417 // that does not affect calibration, according to: 4418 // 4419 // FFSM = FXTAL / FSMDIV 4420 // 4421 // Field encoding is unsigned integer: 4422 // 0-3: Illegal setting 4423 // 4: Divide by 4 4424 // 5: Divide by 5 4425 // .. 4426 // 63: Divide by 63 4427 // ENUMs: 4428 // ALLONES All the bits are 1 4429 // ALLZEROS All the bits are 0 4430 #define LRFDRFE_PRE2_FSMDIV_W 6U 4431 #define LRFDRFE_PRE2_FSMDIV_M 0x0000003FU 4432 #define LRFDRFE_PRE2_FSMDIV_S 0U 4433 #define LRFDRFE_PRE2_FSMDIV_ALLONES 0x0000003FU 4434 #define LRFDRFE_PRE2_FSMDIV_ALLZEROS 0x00000000U 4435 4436 //***************************************************************************** 4437 // 4438 // Register: LRFDRFE_O_PRE3 4439 // 4440 //***************************************************************************** 4441 // Field: [15:5] FINECALDIV 4442 // 4443 // Fine calibration divider 4444 // 4445 // This field determines the reference frequency used to measure the DCO gain 4446 // (KDCO), according to: 4447 // 4448 // FREFCLK = FXTAL / FINECALDIV 4449 // 4450 // Field encoding is unsigned integer: 4451 // 0-7: Illegal setting 4452 // 8: Divide by 8 4453 // 9: Divide by 9 4454 // .. 4455 // 4095: Divide by 4095 4456 // 4457 // Use a lower reference frequency to increases the KDCO estimation accuracy at 4458 // the cost of increased calibration time. The KDCO estimation takes 4459 // approximately 2 periods of the configured frequency. 4460 // ENUMs: 4461 // ALLONES All the bits are 1 4462 // ALLZEROS All the bits are 0 4463 #define LRFDRFE_PRE3_FINECALDIV_W 11U 4464 #define LRFDRFE_PRE3_FINECALDIV_M 0x0000FFE0U 4465 #define LRFDRFE_PRE3_FINECALDIV_S 5U 4466 #define LRFDRFE_PRE3_FINECALDIV_ALLONES 0x0000FFE0U 4467 #define LRFDRFE_PRE3_FINECALDIV_ALLZEROS 0x00000000U 4468 4469 // Field: [4:0] MIDCALDIVMSB 4470 // 4471 // Mid calibration divider MSB 4472 // 4473 // This field determines the reference frequency used during the mid SAR 4474 // calibration stages, according to: 4475 // 4476 // FREFCLK = FXTAL / MIDCALDIV 4477 // 4478 // Field encoding is unsigned integer: 4479 // 0-7: Illegal setting 4480 // 8: Divide by 8 4481 // 9: Divide by 9 4482 // .. 4483 // 1023: Divide by 1023 4484 // ENUMs: 4485 // ALLONES All the bits are 1 4486 // ALLZEROS All the bits are 0 4487 #define LRFDRFE_PRE3_MIDCALDIVMSB_W 5U 4488 #define LRFDRFE_PRE3_MIDCALDIVMSB_M 0x0000001FU 4489 #define LRFDRFE_PRE3_MIDCALDIVMSB_S 0U 4490 #define LRFDRFE_PRE3_MIDCALDIVMSB_ALLONES 0x0000001FU 4491 #define LRFDRFE_PRE3_MIDCALDIVMSB_ALLZEROS 0x00000000U 4492 4493 //***************************************************************************** 4494 // 4495 // Register: LRFDRFE_O_CAL0 4496 // 4497 //***************************************************************************** 4498 // Field: [15] SPARE15 4499 // 4500 // SPARE15 4501 // ENUMs: 4502 // ONE The bit is 1 4503 // ZERO The bit is 0 4504 #define LRFDRFE_CAL0_SPARE15 0x00008000U 4505 #define LRFDRFE_CAL0_SPARE15_M 0x00008000U 4506 #define LRFDRFE_CAL0_SPARE15_S 15U 4507 #define LRFDRFE_CAL0_SPARE15_ONE 0x00008000U 4508 #define LRFDRFE_CAL0_SPARE15_ZERO 0x00000000U 4509 4510 // Field: [14:8] FCSTART 4511 // 4512 // Fine code start 4513 // 4514 // Fine code applied to DCO during all calibration states except during KDCO 4515 // estimation. The start code is then applied to DCO at start of phase 4516 // aquisition in state PLL_ST. Ensure that value is the aritmetic mean of 4517 // CAL1.FCBOT and CAL1.FCTOP. 4518 // 4519 // Field encoding is <7u>. 4520 // 4521 // INTERNAL NOTE: 4522 // * The value specified as start code will not be applied when moving from 4523 // open-loop to closed-loop PLL mode. 4524 // ENUMs: 4525 // ALLONES All the bits are 1 4526 // ALLZEROS All the bits are 0 4527 #define LRFDRFE_CAL0_FCSTART_W 7U 4528 #define LRFDRFE_CAL0_FCSTART_M 0x00007F00U 4529 #define LRFDRFE_CAL0_FCSTART_S 8U 4530 #define LRFDRFE_CAL0_FCSTART_ALLONES 0x00007F00U 4531 #define LRFDRFE_CAL0_FCSTART_ALLZEROS 0x00000000U 4532 4533 // Field: [7] CRS 4534 // 4535 // Coarse calibration control 4536 // ENUMs: 4537 // EN Enable coarse calibration 4538 // DIS Disable coarse calibration 4539 #define LRFDRFE_CAL0_CRS 0x00000080U 4540 #define LRFDRFE_CAL0_CRS_M 0x00000080U 4541 #define LRFDRFE_CAL0_CRS_S 7U 4542 #define LRFDRFE_CAL0_CRS_EN 0x00000080U 4543 #define LRFDRFE_CAL0_CRS_DIS 0x00000000U 4544 4545 // Field: [6] MID 4546 // 4547 // Mid calibration control 4548 // ENUMs: 4549 // EN Enable mid calibration 4550 // DIS Disable mid calibration 4551 #define LRFDRFE_CAL0_MID 0x00000040U 4552 #define LRFDRFE_CAL0_MID_M 0x00000040U 4553 #define LRFDRFE_CAL0_MID_S 6U 4554 #define LRFDRFE_CAL0_MID_EN 0x00000040U 4555 #define LRFDRFE_CAL0_MID_DIS 0x00000000U 4556 4557 // Field: [5] KTDC 4558 // 4559 // KTDC estimation control 4560 // 4561 // It's necessary to estimate the TDC gain to compute its' inverse, 4562 // CAL2.KTDCINV. The latter is used to normalize TDC integer result into 4563 // fractional CKVD periods. 4564 // ENUMs: 4565 // EN Enable TDC estimation 4566 // DIS Disable TDC estimation 4567 #define LRFDRFE_CAL0_KTDC 0x00000020U 4568 #define LRFDRFE_CAL0_KTDC_M 0x00000020U 4569 #define LRFDRFE_CAL0_KTDC_S 5U 4570 #define LRFDRFE_CAL0_KTDC_EN 0x00000020U 4571 #define LRFDRFE_CAL0_KTDC_DIS 0x00000000U 4572 4573 // Field: [4] KDCO 4574 // 4575 // KDCO estimation control 4576 // ENUMs: 4577 // EN Enable KDCO estimation 4578 // DIS Disable KDCO estimation 4579 #define LRFDRFE_CAL0_KDCO 0x00000010U 4580 #define LRFDRFE_CAL0_KDCO_M 0x00000010U 4581 #define LRFDRFE_CAL0_KDCO_S 4U 4582 #define LRFDRFE_CAL0_KDCO_EN 0x00000010U 4583 #define LRFDRFE_CAL0_KDCO_DIS 0x00000000U 4584 4585 // Field: [3:2] TDCAVG 4586 // 4587 // TDC average control 4588 // 4589 // During TDC calibration the TDC measures a pulse of DLOCTL0.TDCSTOP duration. 4590 // The measurement is repeated 2^CAL0.TDCAVG times by the FSM and the 4591 // individual TDC results are accumulated and the final result is available in 4592 // TDCCAL.VAL. 4593 // ENUMs: 4594 // REPEAT_8_TIMES Repeat measurement 8 times 4595 // REPEAT_4_TIMES Repeat measurement 4 times 4596 // REPEAT_2_TIMES Repeat measurement 2 times 4597 // REPEAT_1_TIME Repeat measurement 1 time 4598 #define LRFDRFE_CAL0_TDCAVG_W 2U 4599 #define LRFDRFE_CAL0_TDCAVG_M 0x0000000CU 4600 #define LRFDRFE_CAL0_TDCAVG_S 2U 4601 #define LRFDRFE_CAL0_TDCAVG_REPEAT_8_TIMES 0x0000000CU 4602 #define LRFDRFE_CAL0_TDCAVG_REPEAT_4_TIMES 0x00000008U 4603 #define LRFDRFE_CAL0_TDCAVG_REPEAT_2_TIMES 0x00000004U 4604 #define LRFDRFE_CAL0_TDCAVG_REPEAT_1_TIME 0x00000000U 4605 4606 // Field: [1:0] TDC_SPARE 4607 // 4608 // TDC spare bits 4609 // ENUMs: 4610 // ALLONES All the bits are 1 4611 // ALLZEROS All the bits are 0 4612 #define LRFDRFE_CAL0_TDC_SPARE_W 2U 4613 #define LRFDRFE_CAL0_TDC_SPARE_M 0x00000003U 4614 #define LRFDRFE_CAL0_TDC_SPARE_S 0U 4615 #define LRFDRFE_CAL0_TDC_SPARE_ALLONES 0x00000003U 4616 #define LRFDRFE_CAL0_TDC_SPARE_ALLZEROS 0x00000000U 4617 4618 //***************************************************************************** 4619 // 4620 // Register: LRFDRFE_O_CAL1 4621 // 4622 //***************************************************************************** 4623 // Field: [15] SPARE15 4624 // 4625 // SPARE15 4626 // ENUMs: 4627 // ONE The bit is 1 4628 // ZERO The bit is 0 4629 #define LRFDRFE_CAL1_SPARE15 0x00008000U 4630 #define LRFDRFE_CAL1_SPARE15_M 0x00008000U 4631 #define LRFDRFE_CAL1_SPARE15_S 15U 4632 #define LRFDRFE_CAL1_SPARE15_ONE 0x00008000U 4633 #define LRFDRFE_CAL1_SPARE15_ZERO 0x00000000U 4634 4635 // Field: [14:8] FCTOP 4636 // 4637 // Fine code top 4638 // 4639 // Fine code applied to DCO during KDCO estimation in FSM state FINE_TOP_ST. 4640 // Ensure that CAL0.FCSTART value is the aritmetic mean of CAL1.FCBOT and this 4641 // value. 4642 // 4643 // Field encoding is <7u>. 4644 // ENUMs: 4645 // ALLONES All the bits are 1 4646 // ALLZEROS All the bits are 0 4647 #define LRFDRFE_CAL1_FCTOP_W 7U 4648 #define LRFDRFE_CAL1_FCTOP_M 0x00007F00U 4649 #define LRFDRFE_CAL1_FCTOP_S 8U 4650 #define LRFDRFE_CAL1_FCTOP_ALLONES 0x00007F00U 4651 #define LRFDRFE_CAL1_FCTOP_ALLZEROS 0x00000000U 4652 4653 // Field: [7] SPARE7 4654 // 4655 // SPARE7 4656 // ENUMs: 4657 // ONE The bit is 1 4658 // ZERO The bit is 0 4659 #define LRFDRFE_CAL1_SPARE7 0x00000080U 4660 #define LRFDRFE_CAL1_SPARE7_M 0x00000080U 4661 #define LRFDRFE_CAL1_SPARE7_S 7U 4662 #define LRFDRFE_CAL1_SPARE7_ONE 0x00000080U 4663 #define LRFDRFE_CAL1_SPARE7_ZERO 0x00000000U 4664 4665 // Field: [6:0] FCBOT 4666 // 4667 // Fine code bottom 4668 // 4669 // Fine code applied to DCO during KDCO estimation in FSM state FINE_BOT_ST. 4670 // Ensure that CAL0.FCSTART value is the aritmetic mean of this value and 4671 // CAL1.FCTOP. 4672 // 4673 // Field encoding is <7u>. 4674 // ENUMs: 4675 // ALLONES All the bits are 1 4676 // ALLZEROS All the bits are 0 4677 #define LRFDRFE_CAL1_FCBOT_W 7U 4678 #define LRFDRFE_CAL1_FCBOT_M 0x0000007FU 4679 #define LRFDRFE_CAL1_FCBOT_S 0U 4680 #define LRFDRFE_CAL1_FCBOT_ALLONES 0x0000007FU 4681 #define LRFDRFE_CAL1_FCBOT_ALLZEROS 0x00000000U 4682 4683 //***************************************************************************** 4684 // 4685 // Register: LRFDRFE_O_CAL2 4686 // 4687 //***************************************************************************** 4688 // Field: [15:0] KTDCINV 4689 // 4690 // KTDC inverse 4691 // 4692 // FW updates field with the inverse KTDC value before it enables KDCO 4693 // estimation. KTDC value is availble in TDCCAL.VAL. 4694 // 4695 // One CKVD clock period is normalized to phase of 2^16, hence FW calculates 4696 // field value according to: 4697 // 4698 // KTDCINV = 2^(16+CAL0.TDCAVG+DLOCTL0.TDCSTOP)/TDCCAL.VAL 4699 // 4700 // Encoding is <0.16u>. 4701 // ENUMs: 4702 // ALLONES All the bits are 1 4703 // ALLZEROS All the bits are 0 4704 #define LRFDRFE_CAL2_KTDCINV_W 16U 4705 #define LRFDRFE_CAL2_KTDCINV_M 0x0000FFFFU 4706 #define LRFDRFE_CAL2_KTDCINV_S 0U 4707 #define LRFDRFE_CAL2_KTDCINV_ALLONES 0x0000FFFFU 4708 #define LRFDRFE_CAL2_KTDCINV_ALLZEROS 0x00000000U 4709 4710 //***************************************************************************** 4711 // 4712 // Register: LRFDRFE_O_CAL3 4713 // 4714 //***************************************************************************** 4715 // Field: [15:0] DTXGAIN 4716 // 4717 // Addition path gain 4718 // 4719 // The modulator resolution is given by: 4720 // 4721 // MOD_RES = FRF / 2^(21+MOD0.CANPTHGAIN) Hz/LSB 4722 // 4723 // This resolution is achieved when DC gain in addition and cancellation paths 4724 // are equal. To achieve this condition, the addtion path gain must account for 4725 // the estimated KDCO according to: 4726 // 4727 // DTXGAIN = 2^14 * MOD_RES / KDCO = FRF / KDCO / 2^(7+MOD0.CANPTHGAIN) 4728 // 4729 // Encoding is <2.14u>. 4730 // 4731 // INTERNAL NOTE: 4732 // * The shortest calibration time (1 MHz Fref) for KDCO estimation will give 4733 // around 0.2% uncertainty on the KDCO estimate, worst case. The resolution of 4734 // this field is 2^-14, and hence resolution is not limiting the quality. For 4735 // 25 kHz calibration time, the resolution is also better than the uncertainty. 4736 // ENUMs: 4737 // ALLONES All the bits are 1 4738 // ALLZEROS All the bits are 0 4739 #define LRFDRFE_CAL3_DTXGAIN_W 16U 4740 #define LRFDRFE_CAL3_DTXGAIN_M 0x0000FFFFU 4741 #define LRFDRFE_CAL3_DTXGAIN_S 0U 4742 #define LRFDRFE_CAL3_DTXGAIN_ALLONES 0x0000FFFFU 4743 #define LRFDRFE_CAL3_DTXGAIN_ALLZEROS 0x00000000U 4744 4745 //***************************************************************************** 4746 // 4747 // Register: LRFDRFE_O_MISC0 4748 // 4749 //***************************************************************************** 4750 // Field: [13] PHCPT 4751 // 4752 // Phase capture mode 4753 // 4754 // Field decides if the phase capture mechanism is synchronous to phase valid 4755 // signal or not. Default is synchronous mode (0). 4756 // ENUMs: 4757 // ASYNC Phase capture mode is asyncrhonous 4758 // SYNC Phase capture mode is synchronous 4759 #define LRFDRFE_MISC0_PHCPT 0x00002000U 4760 #define LRFDRFE_MISC0_PHCPT_M 0x00002000U 4761 #define LRFDRFE_MISC0_PHCPT_S 13U 4762 #define LRFDRFE_MISC0_PHCPT_ASYNC 0x00002000U 4763 #define LRFDRFE_MISC0_PHCPT_SYNC 0x00000000U 4764 4765 // Field: [12] TDCCALCORR 4766 // 4767 // Detect and correct errors in TDC value during calibration 4768 // 4769 // Value shall remain static after DLOCTL0.RSTN equals 1. 4770 // ENUMs: 4771 // EN Enable TDC error correction inside DLO. 4772 // DIS Disable TDC error correction inside DLO. 4773 #define LRFDRFE_MISC0_TDCCALCORR 0x00001000U 4774 #define LRFDRFE_MISC0_TDCCALCORR_M 0x00001000U 4775 #define LRFDRFE_MISC0_TDCCALCORR_S 12U 4776 #define LRFDRFE_MISC0_TDCCALCORR_EN 0x00001000U 4777 #define LRFDRFE_MISC0_TDCCALCORR_DIS 0x00000000U 4778 4779 // Field: [11] TDCMSBCORR 4780 // 4781 // TDC MSB error correction control 4782 // 4783 // Value shall remain static after DLOCTL0.RSTN equals 1. 4784 // ENUMs: 4785 // EN Enable TDC error correction inside DLO. 4786 // DIS Disable TDC error correction inside DLO. 4787 #define LRFDRFE_MISC0_TDCMSBCORR 0x00000800U 4788 #define LRFDRFE_MISC0_TDCMSBCORR_M 0x00000800U 4789 #define LRFDRFE_MISC0_TDCMSBCORR_S 11U 4790 #define LRFDRFE_MISC0_TDCMSBCORR_EN 0x00000800U 4791 #define LRFDRFE_MISC0_TDCMSBCORR_DIS 0x00000000U 4792 4793 // Field: [10] SDMDEM 4794 // 4795 // SDM dynamic element matching control 4796 // ENUMs: 4797 // EN Enable dynamic element matching (recommended) 4798 // DIS Disable dynamic element matching 4799 #define LRFDRFE_MISC0_SDMDEM 0x00000400U 4800 #define LRFDRFE_MISC0_SDMDEM_M 0x00000400U 4801 #define LRFDRFE_MISC0_SDMDEM_S 10U 4802 #define LRFDRFE_MISC0_SDMDEM_EN 0x00000400U 4803 #define LRFDRFE_MISC0_SDMDEM_DIS 0x00000000U 4804 4805 // Field: [9:8] DLYSDM 4806 // 4807 // SDM delay match configuration 4808 // 4809 // Fine tune latency for integer part of fine code. The delay should match 4810 // delay through SDM. 4811 // ENUMs: 4812 // CKVD16_3_PER Delay integer fine code by 3 CKVD16 clock periods 4813 // CKVD16_2_PER Delay integer fine code by 2 CKVD16 clock periods 4814 // CKVD16_1_PER Delay integer fine code by 1 CKVD16 clock period 4815 // CKVD16_0_PER Delay integer fine code by 0 CKVD16 clock periods 4816 #define LRFDRFE_MISC0_DLYSDM_W 2U 4817 #define LRFDRFE_MISC0_DLYSDM_M 0x00000300U 4818 #define LRFDRFE_MISC0_DLYSDM_S 8U 4819 #define LRFDRFE_MISC0_DLYSDM_CKVD16_3_PER 0x00000300U 4820 #define LRFDRFE_MISC0_DLYSDM_CKVD16_2_PER 0x00000200U 4821 #define LRFDRFE_MISC0_DLYSDM_CKVD16_1_PER 0x00000100U 4822 #define LRFDRFE_MISC0_DLYSDM_CKVD16_0_PER 0x00000000U 4823 4824 // Field: [6] DLYPHVALID 4825 // 4826 // Phase valid delay 4827 // ENUMs: 4828 // CKVD16_1_PER Delays the variable phase capture and hence the 4829 // phase error calculation with 1 CKVD16 clock 4830 // period. 4831 // CKVD16_0_PER No additional delay on variable phase capture. 4832 #define LRFDRFE_MISC0_DLYPHVALID 0x00000040U 4833 #define LRFDRFE_MISC0_DLYPHVALID_M 0x00000040U 4834 #define LRFDRFE_MISC0_DLYPHVALID_S 6U 4835 #define LRFDRFE_MISC0_DLYPHVALID_CKVD16_1_PER 0x00000040U 4836 #define LRFDRFE_MISC0_DLYPHVALID_CKVD16_0_PER 0x00000000U 4837 4838 // Field: [5:4] DLYCANCRS 4839 // 4840 // Cancellation path coarse delay 4841 // 4842 // Coarse tune latency for cancellation path in relation to the addition path 4843 // (when modulating). The final delay is the sum of coarse delay and fine 4844 // delay. 4845 // ENUMs: 4846 // CKVD64_3_PER Delay by 3 CKVD64 clock periods 4847 // CKVD64_2_PER Delay by 2 CKVD64 clock periods 4848 // CKVD64_1_PER Delay by 1 CKVD64 clock period 4849 // CKVD64_0_PER Delay by 0 CKVD64 clock periods 4850 #define LRFDRFE_MISC0_DLYCANCRS_W 2U 4851 #define LRFDRFE_MISC0_DLYCANCRS_M 0x00000030U 4852 #define LRFDRFE_MISC0_DLYCANCRS_S 4U 4853 #define LRFDRFE_MISC0_DLYCANCRS_CKVD64_3_PER 0x00000030U 4854 #define LRFDRFE_MISC0_DLYCANCRS_CKVD64_2_PER 0x00000020U 4855 #define LRFDRFE_MISC0_DLYCANCRS_CKVD64_1_PER 0x00000010U 4856 #define LRFDRFE_MISC0_DLYCANCRS_CKVD64_0_PER 0x00000000U 4857 4858 // Field: [3:2] DLYCANFINE 4859 // 4860 // Cancellation path fine delay 4861 // 4862 // Fine tune latency for cancellation path in relation to the addition path 4863 // (when modulating). The final delay is the sum of coarse delay and fine 4864 // delay. 4865 // ENUMs: 4866 // CKVD16_4_PER Delay by 4 CKVD16 clock periods 4867 // CKVD16_3_PER Delay by 3 CKVD16 clock periods 4868 // CKVD16_2_PER Delay by 2 CKVD16 clock period 4869 // CKVD16_1_PER Delay by 1 CKVD16 clock periods 4870 #define LRFDRFE_MISC0_DLYCANFINE_W 2U 4871 #define LRFDRFE_MISC0_DLYCANFINE_M 0x0000000CU 4872 #define LRFDRFE_MISC0_DLYCANFINE_S 2U 4873 #define LRFDRFE_MISC0_DLYCANFINE_CKVD16_4_PER 0x0000000CU 4874 #define LRFDRFE_MISC0_DLYCANFINE_CKVD16_3_PER 0x00000008U 4875 #define LRFDRFE_MISC0_DLYCANFINE_CKVD16_2_PER 0x00000004U 4876 #define LRFDRFE_MISC0_DLYCANFINE_CKVD16_1_PER 0x00000000U 4877 4878 // Field: [1:0] DLYADD 4879 // 4880 // Addition path delay 4881 // 4882 // Field specifies additional latency on the modulation data towards antenna. 4883 // ENUMs: 4884 // CKVD64_3_PER Delay by 3 CKVD64 clock periods 4885 // CKVD64_2_PER Delay by 2 CKVD64 clock periods 4886 // CKVD64_1_PER Delay by 1 CKVD64 clock period 4887 // CKVD64_0_PER Delay by 0 CKVD64 clock periods 4888 #define LRFDRFE_MISC0_DLYADD_W 2U 4889 #define LRFDRFE_MISC0_DLYADD_M 0x00000003U 4890 #define LRFDRFE_MISC0_DLYADD_S 0U 4891 #define LRFDRFE_MISC0_DLYADD_CKVD64_3_PER 0x00000003U 4892 #define LRFDRFE_MISC0_DLYADD_CKVD64_2_PER 0x00000002U 4893 #define LRFDRFE_MISC0_DLYADD_CKVD64_1_PER 0x00000001U 4894 #define LRFDRFE_MISC0_DLYADD_CKVD64_0_PER 0x00000000U 4895 4896 //***************************************************************************** 4897 // 4898 // Register: LRFDRFE_O_MISC1 4899 // 4900 //***************************************************************************** 4901 // Field: [14] FCDEMCLK 4902 // 4903 // Bitmask to enable additive terms in INL correction 4904 // 4905 // See implementation spec for details 4906 // ENUMs: 4907 // CKVD64 ckvd64 clock used for update upper and lower DWA 4908 // DEM 4909 // CKCD16 ckvd16 clock used for update upper and lower DWA 4910 // DEM 4911 #define LRFDRFE_MISC1_FCDEMCLK 0x00004000U 4912 #define LRFDRFE_MISC1_FCDEMCLK_M 0x00004000U 4913 #define LRFDRFE_MISC1_FCDEMCLK_S 14U 4914 #define LRFDRFE_MISC1_FCDEMCLK_CKVD64 0x00004000U 4915 #define LRFDRFE_MISC1_FCDEMCLK_CKCD16 0x00000000U 4916 4917 // Field: [13:12] FCDEMUPD 4918 // 4919 // Configures dynamic element matching of fine code 4920 // ENUMs: 4921 // SDM_XOR_PH_ERR phase_error[0] xor SDM[1] 4922 // SDM SDM[1] (this value depends on DEM for SDM) 4923 // PH_ERR phase_error[0]. (Phase error is 6.11s ) 4924 // DEFAULT Default: Update both DWAs always at rising edge of 4925 // selected clock 4926 #define LRFDRFE_MISC1_FCDEMUPD_W 2U 4927 #define LRFDRFE_MISC1_FCDEMUPD_M 0x00003000U 4928 #define LRFDRFE_MISC1_FCDEMUPD_S 12U 4929 #define LRFDRFE_MISC1_FCDEMUPD_SDM_XOR_PH_ERR 0x00003000U 4930 #define LRFDRFE_MISC1_FCDEMUPD_SDM 0x00002000U 4931 #define LRFDRFE_MISC1_FCDEMUPD_PH_ERR 0x00001000U 4932 #define LRFDRFE_MISC1_FCDEMUPD_DEFAULT 0x00000000U 4933 4934 // Field: [11:6] TDCINL 4935 // 4936 // Bitmask to enable additive terms in INL correction 4937 // 4938 // See implementation spec for details 4939 // ENUMs: 4940 // ONES All bits are one 4941 // ZEROS All bits are zero 4942 #define LRFDRFE_MISC1_TDCINL_W 6U 4943 #define LRFDRFE_MISC1_TDCINL_M 0x00000FC0U 4944 #define LRFDRFE_MISC1_TDCINL_S 6U 4945 #define LRFDRFE_MISC1_TDCINL_ONES 0x00000FC0U 4946 #define LRFDRFE_MISC1_TDCINL_ZEROS 0x00000000U 4947 4948 // Field: [5] TDCINLCTL 4949 // 4950 // Enables INL correction of TDC 4951 // ENUMs: 4952 // EN Enables INL correction of TDC 4953 // DIS Disabled INL correction 4954 #define LRFDRFE_MISC1_TDCINLCTL 0x00000020U 4955 #define LRFDRFE_MISC1_TDCINLCTL_M 0x00000020U 4956 #define LRFDRFE_MISC1_TDCINLCTL_S 5U 4957 #define LRFDRFE_MISC1_TDCINLCTL_EN 0x00000020U 4958 #define LRFDRFE_MISC1_TDCINLCTL_DIS 0x00000000U 4959 4960 // Field: [4] PHINIT 4961 // 4962 // Decides if there is known phase relationship between reference clock and RF 4963 // ENUMs: 4964 // UNKNOWN Unknown phase 4965 // KNOWN Known phase 4966 #define LRFDRFE_MISC1_PHINIT 0x00000010U 4967 #define LRFDRFE_MISC1_PHINIT_M 0x00000010U 4968 #define LRFDRFE_MISC1_PHINIT_S 4U 4969 #define LRFDRFE_MISC1_PHINIT_UNKNOWN 0x00000010U 4970 #define LRFDRFE_MISC1_PHINIT_KNOWN 0x00000000U 4971 4972 // Field: [3] SDMOOVRCTL 4973 // 4974 // Force SDMOOVR towards DCO 4975 // ENUMs: 4976 // EN Enable SDM output override 4977 // DIS Disable SDM output override 4978 #define LRFDRFE_MISC1_SDMOOVRCTL 0x00000008U 4979 #define LRFDRFE_MISC1_SDMOOVRCTL_M 0x00000008U 4980 #define LRFDRFE_MISC1_SDMOOVRCTL_S 3U 4981 #define LRFDRFE_MISC1_SDMOOVRCTL_EN 0x00000008U 4982 #define LRFDRFE_MISC1_SDMOOVRCTL_DIS 0x00000000U 4983 4984 // Field: [2:0] SDMOOVR 4985 // 4986 // SDM output code override 4987 // 4988 // When MISC1.SDMOOVRCTL = EN, field value overrides the 3-bit SDM output to 4989 // DCO. 4990 // When MISC1.SDMOOVRCTL = DIS, SDM takes 8-bit input and modulates the 3-bit 4991 // output to DCO. 4992 // ENUMs: 4993 // ALLONES All the bits are 1 4994 // ALLZEROS All the bits are 0 4995 #define LRFDRFE_MISC1_SDMOOVR_W 3U 4996 #define LRFDRFE_MISC1_SDMOOVR_M 0x00000007U 4997 #define LRFDRFE_MISC1_SDMOOVR_S 0U 4998 #define LRFDRFE_MISC1_SDMOOVR_ALLONES 0x00000007U 4999 #define LRFDRFE_MISC1_SDMOOVR_ALLZEROS 0x00000000U 5000 5001 //***************************************************************************** 5002 // 5003 // Register: LRFDRFE_O_LF0 5004 // 5005 //***************************************************************************** 5006 // Field: [12] KIPREC 5007 // 5008 // FIR integral gain precision 5009 // 5010 // When numerical value of KI is lower than 16-1/256, high precision can be 5011 // enabled. 5012 // FIR loop filter gets reinitialized with the current value whenever: 5013 // - DLO moves from calibration operation to closed-loop state. 5014 // - DLO moves from open-loop operation to closed-loop operation. 5015 // - DLO is in closed-loop operation and there is a change on loop control set. 5016 // See DLOCTL0.LOOPUPD. 5017 // ENUMs: 5018 // HIGH KI encoding is <4.08> 5019 // LOW KI encoding is <12.0u> 5020 #define LRFDRFE_LF0_KIPREC 0x00001000U 5021 #define LRFDRFE_LF0_KIPREC_M 0x00001000U 5022 #define LRFDRFE_LF0_KIPREC_S 12U 5023 #define LRFDRFE_LF0_KIPREC_HIGH 0x00001000U 5024 #define LRFDRFE_LF0_KIPREC_LOW 0x00000000U 5025 5026 // Field: [11:0] KI 5027 // 5028 // FIR integral gain 5029 // 5030 // Field sets the integral gain in the FIR loop filter. 5031 // 5032 // FIR_KI = pi^2 * f3db^2 / (FREF * KDCO * DF^2) 5033 // 5034 // where DF is the desired damping factor. Lower damping factor gives lower 5035 // phase margin in the loop. Typically damping factors in the range 0.75 to 1 5036 // is used. Note that equations above become more accurate when DF > 1. 5037 // 5038 // Encoding is given by KIPREC setting. Examples: 5039 // 5040 // When KIPREC = 0: 5041 // 5042 // 0x000: KI = 0 5043 // 0x001: KI = 1 5044 // 0xFFF: KI = 4095 5045 // 5046 // When KIPREC = 1: 5047 // 5048 // 0x000: KI = 0x0.00 = 0.0 5049 // 0x001: KI = 0x0.01 = 0.00390625 5050 // 0x002: KI = 0x0.02 = 0.0078125 5051 // 0x004: KI = 0x0.40 = 0.25 5052 // 0x008: KI = 0x0.80 = 0.5 5053 // 0xFF0: KI = 0xF.F0 = 15.9375 5054 // 0xFFF: KI = 0xF.FF = 15.99609375 5055 // 5056 // FIR loop filter gets reinitialized with the current value whenever: 5057 // - DLO moves from calibration operation to closed-loop state. 5058 // - DLO moves from open-loop operation to closed-loop operation. 5059 // - DLO is in closed-loop operation and there is a change on loop control set. 5060 // See DLOCTL0.LOOPUPD. 5061 // ENUMs: 5062 // ALLONES All the bits are 1 5063 // ALLZEROS All the bits are 0 5064 #define LRFDRFE_LF0_KI_W 12U 5065 #define LRFDRFE_LF0_KI_M 0x00000FFFU 5066 #define LRFDRFE_LF0_KI_S 0U 5067 #define LRFDRFE_LF0_KI_ALLONES 0x00000FFFU 5068 #define LRFDRFE_LF0_KI_ALLZEROS 0x00000000U 5069 5070 //***************************************************************************** 5071 // 5072 // Register: LRFDRFE_O_LF1 5073 // 5074 //***************************************************************************** 5075 // Field: [13:0] KP 5076 // 5077 // FIR proportional gain 5078 // 5079 // Field sets the proportional gain in FIR loop filter. 5080 // 5081 // FIR_KP = 2*pi* f3db / KDCO 5082 // 5083 // Encoding is <14.0u>: 5084 // 0x0000: Minimum proportional gain 5085 // 0x3FFF: Maximum proportional gain 5086 // 5087 // FIR loop filter gets reinitialized with the current value whenever DLO moves 5088 // from calibration or open-loop operation to closed-loop operation. 5089 // ENUMs: 5090 // ALLONES All the bits are 1 5091 // ALLZEROS All the bits are 0 5092 #define LRFDRFE_LF1_KP_W 14U 5093 #define LRFDRFE_LF1_KP_M 0x00003FFFU 5094 #define LRFDRFE_LF1_KP_S 0U 5095 #define LRFDRFE_LF1_KP_ALLONES 0x00003FFFU 5096 #define LRFDRFE_LF1_KP_ALLZEROS 0x00000000U 5097 5098 //***************************************************************************** 5099 // 5100 // Register: LRFDRFE_O_PHEDISC 5101 // 5102 //***************************************************************************** 5103 // Field: [13:10] CNT 5104 // 5105 // Phase error discard count 5106 // 5107 // When phase error discarding is enabled, FIR loop filter does not update if: 5108 // 5109 // abs(phase error) > PHEDISC_THR / 64 5110 // 5111 // Update loop if this happens for CNT consecutive REFCLK periods. 5112 // 5113 // Set DLOCTL1.PHEDISC = EN to enable phase error discarding. 5114 // ENUMs: 5115 // ALLONES All the bits are 1 5116 // ALLZEROS All the bits are 0 5117 #define LRFDRFE_PHEDISC_CNT_W 4U 5118 #define LRFDRFE_PHEDISC_CNT_M 0x00003C00U 5119 #define LRFDRFE_PHEDISC_CNT_S 10U 5120 #define LRFDRFE_PHEDISC_CNT_ALLONES 0x00003C00U 5121 #define LRFDRFE_PHEDISC_CNT_ALLZEROS 0x00000000U 5122 5123 // Field: [9:0] THR 5124 // 5125 // Phase error discard threshold 5126 // 5127 // When phase error discarding is enabled, FIR loop filter does not update if: 5128 // 5129 // abs(phase error) > PHEDISC_THR / 64 5130 // 5131 // Update loop if this happens for CNT consecutive REFCLK periods. 5132 // 5133 // Set DLOCTL1.PHEDISC = EN to enable phase error discarding. 5134 // ENUMs: 5135 // ALLONES All the bits are 1 5136 // ALLZEROS All the bits are 0 5137 #define LRFDRFE_PHEDISC_THR_W 10U 5138 #define LRFDRFE_PHEDISC_THR_M 0x000003FFU 5139 #define LRFDRFE_PHEDISC_THR_S 0U 5140 #define LRFDRFE_PHEDISC_THR_ALLONES 0x000003FFU 5141 #define LRFDRFE_PHEDISC_THR_ALLZEROS 0x00000000U 5142 5143 //***************************************************************************** 5144 // 5145 // Register: LRFDRFE_O_PHINIT 5146 // 5147 //***************************************************************************** 5148 // Field: [7:0] OFF 5149 // 5150 // Reference phase offset 5151 // 5152 // Field initializes phase offset between CKVD and reference clock. 5153 // 5154 // Encoding of field is <0.8u>. 5155 // 5156 // Examples: 5157 // 0x40: 25% of CKVD clock period 5158 // 0x80: 50% of CKVD clock period 5159 // 0xC0: 75% of CKVD clock period 5160 // ENUMs: 5161 // ALLONES All the bits are 1 5162 // ALLZEROS All the bits are 0 5163 #define LRFDRFE_PHINIT_OFF_W 8U 5164 #define LRFDRFE_PHINIT_OFF_M 0x000000FFU 5165 #define LRFDRFE_PHINIT_OFF_S 0U 5166 #define LRFDRFE_PHINIT_OFF_ALLONES 0x000000FFU 5167 #define LRFDRFE_PHINIT_OFF_ALLZEROS 0x00000000U 5168 5169 //***************************************************************************** 5170 // 5171 // Register: LRFDRFE_O_PLLMON0 5172 // 5173 //***************************************************************************** 5174 // Field: [15:14] PHELOLCNT 5175 // 5176 // Phase error lock loss count 5177 // 5178 // Loss of lock is indicated when abs(phase error) > PHELOLTHR / 2: 5179 // 5180 // - for PHELOLCNT consecutive periods of REFCLK . 5181 // - and loop filter fincode overflows or underflows. 5182 // 5183 // When either of these conditions occur DLOEV.LOL flag gets set in REFCLK 5184 // domain, and synthesizer IRQ to modem is asserted. See DLOCTL1.PLLMON for 5185 // further description. 5186 // ENUMs: 5187 // REFCLK_128_PER Threshold count is 128 REFCLK periods 5188 // REFCLK_64_PER Threshold count is 64 REFCLK periods 5189 // REFCLK_32_PER Threshold count is 32 REFCLK periods 5190 // REFCLK_16_PER Threshold count is 16 REFCLK periods 5191 #define LRFDRFE_PLLMON0_PHELOLCNT_W 2U 5192 #define LRFDRFE_PLLMON0_PHELOLCNT_M 0x0000C000U 5193 #define LRFDRFE_PLLMON0_PHELOLCNT_S 14U 5194 #define LRFDRFE_PLLMON0_PHELOLCNT_REFCLK_128_PER 0x0000C000U 5195 #define LRFDRFE_PLLMON0_PHELOLCNT_REFCLK_64_PER 0x00008000U 5196 #define LRFDRFE_PLLMON0_PHELOLCNT_REFCLK_32_PER 0x00004000U 5197 #define LRFDRFE_PLLMON0_PHELOLCNT_REFCLK_16_PER 0x00000000U 5198 5199 // Field: [13:8] PHELOLTHR 5200 // 5201 // Phase error lock loss threshold 5202 // 5203 // Loss of lock is indicated when abs(phase error) > PHELOLTHR / 2: 5204 // 5205 // - for PLLMON0.PHELOLCNT consecutive periods of REFCLK . 5206 // - and loop filter fincode overflows or underflows. 5207 // 5208 // When either of these conditions occur DLOEV.LOL flag gets set in REFCLK 5209 // domain, and synthesizer IRQ to modem is asserted. See DLOCTL1.PLLMON for 5210 // further description. 5211 // ENUMs: 5212 // ALLONES All the bits are 1 5213 // ALLZEROS All the bits are 0 5214 #define LRFDRFE_PLLMON0_PHELOLTHR_W 6U 5215 #define LRFDRFE_PLLMON0_PHELOLTHR_M 0x00003F00U 5216 #define LRFDRFE_PLLMON0_PHELOLTHR_S 8U 5217 #define LRFDRFE_PLLMON0_PHELOLTHR_ALLONES 0x00003F00U 5218 #define LRFDRFE_PLLMON0_PHELOLTHR_ALLZEROS 0x00000000U 5219 5220 // Field: [6:0] FCTHR 5221 // 5222 // Fine code threshold 5223 // 5224 // Field sets two symmetric thresholds, with encoding <7.8u>: 5225 // FCLWTHR = {FCTHR, 8'b0} 5226 // FCUPTHR = {8'b0111111 - FCTHR), 8'b1} 5227 // 5228 // The PLL monitor compares the final 15-bit fine code sent to DCO and SDM to 5229 // these thresholds: 5230 // 5231 // When fine code > FCUPTHR, DLOEV.FCABVTHR flag gets set in REFCLK domain. 5232 // When fine code < FCLWTHR, DLOEV.FCBLWTHR flag gets set in REFCLK domain. 5233 // 5234 // In both cases synthesizer IRQ to modem is asserted. See DLOCTL1.PLLMON for 5235 // further description. 5236 // 5237 // INTERNAL NOTE: 5238 // * default value should be 0 so that detector is effectively disabled for any 5239 // fine code. 5240 // ENUMs: 5241 // ALLONES All the bits are 1 5242 // ALLZEROS All the bits are 0 5243 #define LRFDRFE_PLLMON0_FCTHR_W 7U 5244 #define LRFDRFE_PLLMON0_FCTHR_M 0x0000007FU 5245 #define LRFDRFE_PLLMON0_FCTHR_S 0U 5246 #define LRFDRFE_PLLMON0_FCTHR_ALLONES 0x0000007FU 5247 #define LRFDRFE_PLLMON0_FCTHR_ALLZEROS 0x00000000U 5248 5249 //***************************************************************************** 5250 // 5251 // Register: LRFDRFE_O_PLLMON1 5252 // 5253 //***************************************************************************** 5254 // Field: [12:8] PHELOCKCNT 5255 // 5256 // Phase error lock count 5257 // 5258 // Declare lock for PLL if: 5259 // 5260 // abs(phase error) < PHELOCKTHR / 64 5261 // 5262 // for PHELOCKCNT*4 consecutive periods of default REFCLK. When this happens 5263 // DLOEV.LOCK flag gets set in REFCLK domain, and synthesizer IRQ to modem is 5264 // asserted. See DLOCTL1.PLLMON for further description. 5265 // ENUMs: 5266 // ALLONES All the bits are 1 5267 // ALLZEROS All the bits are 0 5268 #define LRFDRFE_PLLMON1_PHELOCKCNT_W 5U 5269 #define LRFDRFE_PLLMON1_PHELOCKCNT_M 0x00001F00U 5270 #define LRFDRFE_PLLMON1_PHELOCKCNT_S 8U 5271 #define LRFDRFE_PLLMON1_PHELOCKCNT_ALLONES 0x00001F00U 5272 #define LRFDRFE_PLLMON1_PHELOCKCNT_ALLZEROS 0x00000000U 5273 5274 // Field: [7:0] PHELOCKTHR 5275 // 5276 // Phase error lock threshold 5277 // 5278 // Declare lock for PLL if: 5279 // 5280 // abs(phase error) < PHELOCKTHR / 64 5281 // 5282 // for PHELOCKCNT *4 consecutive periods of default REFCLK.When this happens 5283 // DLOEV.LOCK flag gets set in REFCLK domain, and synthesizer IRQ to modem is 5284 // asserted. See DLOCTL1.PLLMON for further description. 5285 // ENUMs: 5286 // ALLONES All the bits are 1 5287 // ALLZEROS All the bits are 0 5288 #define LRFDRFE_PLLMON1_PHELOCKTHR_W 8U 5289 #define LRFDRFE_PLLMON1_PHELOCKTHR_M 0x000000FFU 5290 #define LRFDRFE_PLLMON1_PHELOCKTHR_S 0U 5291 #define LRFDRFE_PLLMON1_PHELOCKTHR_ALLONES 0x000000FFU 5292 #define LRFDRFE_PLLMON1_PHELOCKTHR_ALLZEROS 0x00000000U 5293 5294 //***************************************************************************** 5295 // 5296 // Register: LRFDRFE_O_MOD0 5297 // 5298 //***************************************************************************** 5299 // Field: [12:11] SCHEME 5300 // 5301 // Scheme 5302 // 5303 // Field sets the modulation scheme of the DLO 5304 // ENUMs: 5305 // TWO_POINT_MOD_FRF 2-point modulation with FRF resolution 5306 // 5307 // MOD_RES = FRF / 5308 // 2^(21+CANPTHGAIN) 5309 // 5310 // Scheme supports both open 5311 // -and closed-loop operation. Scheme allows wider 5312 // modulation bandwiths than INLOOP_MOD_FRF. 5313 // INLOOP_MOD_FRF In-loop modulation with FRF resolution 5314 // 5315 // MOD_RES = FRF / 5316 // 2^(21+CANPTHGAIN) 5317 // INLOOP_MOD_FREF In-loop modulation with FREF resolution 5318 // 5319 // MOD_RES = FREF / 5320 // (DIVIDER/2) / 2^(15+CANPTHGAIN) 5321 // 5322 // DIV.RATIO determines 5323 // DIVIDER configuration. Scheme only supports 5324 // closed-loop operation. 5325 // NC No connect 5326 // 5327 // Modulator output does not 5328 // add to frequencey control word from PLL. 5329 #define LRFDRFE_MOD0_SCHEME_W 2U 5330 #define LRFDRFE_MOD0_SCHEME_M 0x00001800U 5331 #define LRFDRFE_MOD0_SCHEME_S 11U 5332 #define LRFDRFE_MOD0_SCHEME_TWO_POINT_MOD_FRF 0x00001800U 5333 #define LRFDRFE_MOD0_SCHEME_INLOOP_MOD_FRF 0x00001000U 5334 #define LRFDRFE_MOD0_SCHEME_INLOOP_MOD_FREF 0x00000800U 5335 #define LRFDRFE_MOD0_SCHEME_NC 0x00000000U 5336 5337 // Field: [10:8] SYMSHP 5338 // 5339 // Symbol shaper 5340 // ENUMs: 5341 // CHIRP Chirp modulation 5342 // SHAPEDZIGBEE Use Shaped 802.15.4 modulation 5343 // PCWSPSK Use piecewise linear PSK shaper defined by 5344 // SHAPECFG* registers. 5345 // ZIGBEE Use unshaped zigbee 5346 // SHAPEDFSK Use generic 3 symbol shaper defined by SHAPECFG* 5347 // registers. 5348 #define LRFDRFE_MOD0_SYMSHP_W 3U 5349 #define LRFDRFE_MOD0_SYMSHP_M 0x00000700U 5350 #define LRFDRFE_MOD0_SYMSHP_S 8U 5351 #define LRFDRFE_MOD0_SYMSHP_CHIRP 0x00000400U 5352 #define LRFDRFE_MOD0_SYMSHP_SHAPEDZIGBEE 0x00000300U 5353 #define LRFDRFE_MOD0_SYMSHP_PCWSPSK 0x00000200U 5354 #define LRFDRFE_MOD0_SYMSHP_ZIGBEE 0x00000100U 5355 #define LRFDRFE_MOD0_SYMSHP_SHAPEDFSK 0x00000000U 5356 5357 // Field: [7:6] CANPTHGAIN 5358 // 5359 // Cancellation path gain 5360 // 5361 // The cancellation phase is scaled by a configurable gain, which effectively 5362 // sets the modulator frequency control word resolution. To calculate the 5363 // resolution, use the binary value of this field in equations in SCHEME. 5364 // ENUMs: 5365 // TWO_POW_M_18 POW(2,-18) 5366 // TWO_POW_M_17 POW(2,-17) 5367 // TWO_POW_M_16 POW(2,-16) 5368 // TWO_POW_M_15 POW(2,-15) 5369 #define LRFDRFE_MOD0_CANPTHGAIN_W 2U 5370 #define LRFDRFE_MOD0_CANPTHGAIN_M 0x000000C0U 5371 #define LRFDRFE_MOD0_CANPTHGAIN_S 6U 5372 #define LRFDRFE_MOD0_CANPTHGAIN_TWO_POW_M_18 0x000000C0U 5373 #define LRFDRFE_MOD0_CANPTHGAIN_TWO_POW_M_17 0x00000080U 5374 #define LRFDRFE_MOD0_CANPTHGAIN_TWO_POW_M_16 0x00000040U 5375 #define LRFDRFE_MOD0_CANPTHGAIN_TWO_POW_M_15 0x00000000U 5376 5377 // Field: [5:4] SHPGAIN 5378 // 5379 // Shape gain 5380 // 5381 // Field sets the scaling factor for shape elements in DTX0 - DTX5. Both the 5382 // scaling factor and shape element values are generated offline for a certain 5383 // frequency deviation. 5384 // 5385 // INTERNAL NOTE: 5386 // * Please refer to 5387 // https://spsemea.itg.ti.com/sites/lpw/proj/CC26xx/Architecture/Radio%20System/cc26xx_modem_spec.doc 5388 // for how the SHPGAIN and shape elements together defines the frequency 5389 // deviation for different modes. 5390 // * The scaling factor is is really as follows: 5391 // X1 = DIV_BY_4 5392 // X2 = DIV_BY_2 5393 // X4 = DIV_BY_1 5394 // X8 = DIV_BY_0P5 5395 // Will not update to reflect this as the matlab gain output === SHPGAIN. 5396 // ENUMs: 5397 // X8 Shape gain = 8 5398 // X4 Shape gain = 4 5399 // X2 Shape gain = 2 5400 // X1 Shape gain = 1 5401 #define LRFDRFE_MOD0_SHPGAIN_W 2U 5402 #define LRFDRFE_MOD0_SHPGAIN_M 0x00000030U 5403 #define LRFDRFE_MOD0_SHPGAIN_S 4U 5404 #define LRFDRFE_MOD0_SHPGAIN_X8 0x00000030U 5405 #define LRFDRFE_MOD0_SHPGAIN_X4 0x00000020U 5406 #define LRFDRFE_MOD0_SHPGAIN_X2 0x00000010U 5407 #define LRFDRFE_MOD0_SHPGAIN_X1 0x00000000U 5408 5409 // Field: [3:2] INTPFACT 5410 // 5411 // Interpolation factor 5412 // 5413 // Field sets the interpolation factor of the shape filter. 5414 // 5415 // INTERNAL NOTE: 5416 // Please refer to 5417 // https://spsemea.itg.ti.com/sites/lpw/proj/CC26xx/Architecture/Radio%20System/cc26xx_modem_spec.doc 5418 // for more detailed description. 5419 // ENUMs: 5420 // ILLEGAL1 Illegal, unsupported setting 5421 // INTP_BY_32 Interpolate by 32 5422 // INTP_BY_16 Interpolate by 16 5423 // ILLEGAL0 Illegal, unsupported setting 5424 #define LRFDRFE_MOD0_INTPFACT_W 2U 5425 #define LRFDRFE_MOD0_INTPFACT_M 0x0000000CU 5426 #define LRFDRFE_MOD0_INTPFACT_S 2U 5427 #define LRFDRFE_MOD0_INTPFACT_ILLEGAL1 0x0000000CU 5428 #define LRFDRFE_MOD0_INTPFACT_INTP_BY_32 0x00000008U 5429 #define LRFDRFE_MOD0_INTPFACT_INTP_BY_16 0x00000004U 5430 #define LRFDRFE_MOD0_INTPFACT_ILLEGAL0 0x00000000U 5431 5432 //***************************************************************************** 5433 // 5434 // Register: LRFDRFE_O_MOD1 5435 // 5436 //***************************************************************************** 5437 // Field: [11:0] FOFF 5438 // 5439 // Frequency Offset 5440 // 5441 // Field configures the optional intermediate frequency (IF) used in TX or RX. 5442 // 5443 // IF = FRF / 2^(21+CANPTHGAIN) * FOFF 5444 // 5445 // Encoding is <12.0s>. 5446 // ENUMs: 5447 // ALLONES All the bits are 1 5448 // ALLZEROS All the bits are 0 5449 #define LRFDRFE_MOD1_FOFF_W 12U 5450 #define LRFDRFE_MOD1_FOFF_M 0x00000FFFU 5451 #define LRFDRFE_MOD1_FOFF_S 0U 5452 #define LRFDRFE_MOD1_FOFF_ALLONES 0x00000FFFU 5453 #define LRFDRFE_MOD1_FOFF_ALLZEROS 0x00000000U 5454 5455 //***************************************************************************** 5456 // 5457 // Register: LRFDRFE_O_DTX0 5458 // 5459 //***************************************************************************** 5460 // Field: [15:8] SHP1 5461 // 5462 // Shape element 1 5463 // ENUMs: 5464 // ALLONES All the bits are 1 5465 // ALLZEROS All the bits are 0 5466 #define LRFDRFE_DTX0_SHP1_W 8U 5467 #define LRFDRFE_DTX0_SHP1_M 0x0000FF00U 5468 #define LRFDRFE_DTX0_SHP1_S 8U 5469 #define LRFDRFE_DTX0_SHP1_ALLONES 0x0000FF00U 5470 #define LRFDRFE_DTX0_SHP1_ALLZEROS 0x00000000U 5471 5472 // Field: [7:0] SHP0 5473 // 5474 // Shape element 0 5475 // ENUMs: 5476 // ALLONES All the bits are 1 5477 // ALLZEROS All the bits are 0 5478 #define LRFDRFE_DTX0_SHP0_W 8U 5479 #define LRFDRFE_DTX0_SHP0_M 0x000000FFU 5480 #define LRFDRFE_DTX0_SHP0_S 0U 5481 #define LRFDRFE_DTX0_SHP0_ALLONES 0x000000FFU 5482 #define LRFDRFE_DTX0_SHP0_ALLZEROS 0x00000000U 5483 5484 //***************************************************************************** 5485 // 5486 // Register: LRFDRFE_O_DTX1 5487 // 5488 //***************************************************************************** 5489 // Field: [15:8] SHP3 5490 // 5491 // Shape element 3 5492 // ENUMs: 5493 // ALLONES All the bits are 1 5494 // ALLZEROS All the bits are 0 5495 #define LRFDRFE_DTX1_SHP3_W 8U 5496 #define LRFDRFE_DTX1_SHP3_M 0x0000FF00U 5497 #define LRFDRFE_DTX1_SHP3_S 8U 5498 #define LRFDRFE_DTX1_SHP3_ALLONES 0x0000FF00U 5499 #define LRFDRFE_DTX1_SHP3_ALLZEROS 0x00000000U 5500 5501 // Field: [7:0] SHP2 5502 // 5503 // Shape element 2 5504 // ENUMs: 5505 // ALLONES All the bits are 1 5506 // ALLZEROS All the bits are 0 5507 #define LRFDRFE_DTX1_SHP2_W 8U 5508 #define LRFDRFE_DTX1_SHP2_M 0x000000FFU 5509 #define LRFDRFE_DTX1_SHP2_S 0U 5510 #define LRFDRFE_DTX1_SHP2_ALLONES 0x000000FFU 5511 #define LRFDRFE_DTX1_SHP2_ALLZEROS 0x00000000U 5512 5513 //***************************************************************************** 5514 // 5515 // Register: LRFDRFE_O_DTX2 5516 // 5517 //***************************************************************************** 5518 // Field: [15:8] SHP5 5519 // 5520 // Shape element 5 5521 // ENUMs: 5522 // ALLONES All the bits are 1 5523 // ALLZEROS All the bits are 0 5524 #define LRFDRFE_DTX2_SHP5_W 8U 5525 #define LRFDRFE_DTX2_SHP5_M 0x0000FF00U 5526 #define LRFDRFE_DTX2_SHP5_S 8U 5527 #define LRFDRFE_DTX2_SHP5_ALLONES 0x0000FF00U 5528 #define LRFDRFE_DTX2_SHP5_ALLZEROS 0x00000000U 5529 5530 // Field: [7:0] SHP4 5531 // 5532 // Shape element 4 5533 // ENUMs: 5534 // ALLONES All the bits are 1 5535 // ALLZEROS All the bits are 0 5536 #define LRFDRFE_DTX2_SHP4_W 8U 5537 #define LRFDRFE_DTX2_SHP4_M 0x000000FFU 5538 #define LRFDRFE_DTX2_SHP4_S 0U 5539 #define LRFDRFE_DTX2_SHP4_ALLONES 0x000000FFU 5540 #define LRFDRFE_DTX2_SHP4_ALLZEROS 0x00000000U 5541 5542 //***************************************************************************** 5543 // 5544 // Register: LRFDRFE_O_DTX3 5545 // 5546 //***************************************************************************** 5547 // Field: [15:8] SHP7 5548 // 5549 // Shape element 7 5550 // ENUMs: 5551 // ALLONES All the bits are 1 5552 // ALLZEROS All the bits are 0 5553 #define LRFDRFE_DTX3_SHP7_W 8U 5554 #define LRFDRFE_DTX3_SHP7_M 0x0000FF00U 5555 #define LRFDRFE_DTX3_SHP7_S 8U 5556 #define LRFDRFE_DTX3_SHP7_ALLONES 0x0000FF00U 5557 #define LRFDRFE_DTX3_SHP7_ALLZEROS 0x00000000U 5558 5559 // Field: [7:0] SHP6 5560 // 5561 // Shape element 6 5562 // ENUMs: 5563 // ALLONES All the bits are 1 5564 // ALLZEROS All the bits are 0 5565 #define LRFDRFE_DTX3_SHP6_W 8U 5566 #define LRFDRFE_DTX3_SHP6_M 0x000000FFU 5567 #define LRFDRFE_DTX3_SHP6_S 0U 5568 #define LRFDRFE_DTX3_SHP6_ALLONES 0x000000FFU 5569 #define LRFDRFE_DTX3_SHP6_ALLZEROS 0x00000000U 5570 5571 //***************************************************************************** 5572 // 5573 // Register: LRFDRFE_O_DTX4 5574 // 5575 //***************************************************************************** 5576 // Field: [15:8] SHP9 5577 // 5578 // Shape element 9 5579 // ENUMs: 5580 // ALLONES All the bits are 1 5581 // ALLZEROS All the bits are 0 5582 #define LRFDRFE_DTX4_SHP9_W 8U 5583 #define LRFDRFE_DTX4_SHP9_M 0x0000FF00U 5584 #define LRFDRFE_DTX4_SHP9_S 8U 5585 #define LRFDRFE_DTX4_SHP9_ALLONES 0x0000FF00U 5586 #define LRFDRFE_DTX4_SHP9_ALLZEROS 0x00000000U 5587 5588 // Field: [7:0] SHP8 5589 // 5590 // Shape element 8 5591 // ENUMs: 5592 // ALLONES All the bits are 1 5593 // ALLZEROS All the bits are 0 5594 #define LRFDRFE_DTX4_SHP8_W 8U 5595 #define LRFDRFE_DTX4_SHP8_M 0x000000FFU 5596 #define LRFDRFE_DTX4_SHP8_S 0U 5597 #define LRFDRFE_DTX4_SHP8_ALLONES 0x000000FFU 5598 #define LRFDRFE_DTX4_SHP8_ALLZEROS 0x00000000U 5599 5600 //***************************************************************************** 5601 // 5602 // Register: LRFDRFE_O_DTX5 5603 // 5604 //***************************************************************************** 5605 // Field: [15:8] SHP11 5606 // 5607 // Shape element 11 5608 // ENUMs: 5609 // ALLONES All the bits are 1 5610 // ALLZEROS All the bits are 0 5611 #define LRFDRFE_DTX5_SHP11_W 8U 5612 #define LRFDRFE_DTX5_SHP11_M 0x0000FF00U 5613 #define LRFDRFE_DTX5_SHP11_S 8U 5614 #define LRFDRFE_DTX5_SHP11_ALLONES 0x0000FF00U 5615 #define LRFDRFE_DTX5_SHP11_ALLZEROS 0x00000000U 5616 5617 // Field: [7:0] SHP10 5618 // 5619 // Shape element 10 5620 // ENUMs: 5621 // ALLONES All the bits are 1 5622 // ALLZEROS All the bits are 0 5623 #define LRFDRFE_DTX5_SHP10_W 8U 5624 #define LRFDRFE_DTX5_SHP10_M 0x000000FFU 5625 #define LRFDRFE_DTX5_SHP10_S 0U 5626 #define LRFDRFE_DTX5_SHP10_ALLONES 0x000000FFU 5627 #define LRFDRFE_DTX5_SHP10_ALLZEROS 0x00000000U 5628 5629 //***************************************************************************** 5630 // 5631 // Register: LRFDRFE_O_DTX6 5632 // 5633 //***************************************************************************** 5634 // Field: [15:8] SHP13 5635 // 5636 // Shape element 13 5637 // ENUMs: 5638 // ALLONES All the bits are 1 5639 // ALLZEROS All the bits are 0 5640 #define LRFDRFE_DTX6_SHP13_W 8U 5641 #define LRFDRFE_DTX6_SHP13_M 0x0000FF00U 5642 #define LRFDRFE_DTX6_SHP13_S 8U 5643 #define LRFDRFE_DTX6_SHP13_ALLONES 0x0000FF00U 5644 #define LRFDRFE_DTX6_SHP13_ALLZEROS 0x00000000U 5645 5646 // Field: [7:0] SHP12 5647 // 5648 // Shape element 12 5649 // ENUMs: 5650 // ALLONES All the bits are 1 5651 // ALLZEROS All the bits are 0 5652 #define LRFDRFE_DTX6_SHP12_W 8U 5653 #define LRFDRFE_DTX6_SHP12_M 0x000000FFU 5654 #define LRFDRFE_DTX6_SHP12_S 0U 5655 #define LRFDRFE_DTX6_SHP12_ALLONES 0x000000FFU 5656 #define LRFDRFE_DTX6_SHP12_ALLZEROS 0x00000000U 5657 5658 //***************************************************************************** 5659 // 5660 // Register: LRFDRFE_O_DTX7 5661 // 5662 //***************************************************************************** 5663 // Field: [15:8] SHP15 5664 // 5665 // Shape element 15 5666 // ENUMs: 5667 // ALLONES All the bits are 1 5668 // ALLZEROS All the bits are 0 5669 #define LRFDRFE_DTX7_SHP15_W 8U 5670 #define LRFDRFE_DTX7_SHP15_M 0x0000FF00U 5671 #define LRFDRFE_DTX7_SHP15_S 8U 5672 #define LRFDRFE_DTX7_SHP15_ALLONES 0x0000FF00U 5673 #define LRFDRFE_DTX7_SHP15_ALLZEROS 0x00000000U 5674 5675 // Field: [7:0] SHP14 5676 // 5677 // Shape element 14 5678 // ENUMs: 5679 // ALLONES All the bits are 1 5680 // ALLZEROS All the bits are 0 5681 #define LRFDRFE_DTX7_SHP14_W 8U 5682 #define LRFDRFE_DTX7_SHP14_M 0x000000FFU 5683 #define LRFDRFE_DTX7_SHP14_S 0U 5684 #define LRFDRFE_DTX7_SHP14_ALLONES 0x000000FFU 5685 #define LRFDRFE_DTX7_SHP14_ALLZEROS 0x00000000U 5686 5687 //***************************************************************************** 5688 // 5689 // Register: LRFDRFE_O_DTX8 5690 // 5691 //***************************************************************************** 5692 // Field: [15:8] SHP17 5693 // 5694 // Shape element 17 5695 // ENUMs: 5696 // ALLONES All the bits are 1 5697 // ALLZEROS All the bits are 0 5698 #define LRFDRFE_DTX8_SHP17_W 8U 5699 #define LRFDRFE_DTX8_SHP17_M 0x0000FF00U 5700 #define LRFDRFE_DTX8_SHP17_S 8U 5701 #define LRFDRFE_DTX8_SHP17_ALLONES 0x0000FF00U 5702 #define LRFDRFE_DTX8_SHP17_ALLZEROS 0x00000000U 5703 5704 // Field: [7:0] SHP16 5705 // 5706 // Shape element 16 5707 // ENUMs: 5708 // ALLONES All the bits are 1 5709 // ALLZEROS All the bits are 0 5710 #define LRFDRFE_DTX8_SHP16_W 8U 5711 #define LRFDRFE_DTX8_SHP16_M 0x000000FFU 5712 #define LRFDRFE_DTX8_SHP16_S 0U 5713 #define LRFDRFE_DTX8_SHP16_ALLONES 0x000000FFU 5714 #define LRFDRFE_DTX8_SHP16_ALLZEROS 0x00000000U 5715 5716 //***************************************************************************** 5717 // 5718 // Register: LRFDRFE_O_DTX9 5719 // 5720 //***************************************************************************** 5721 // Field: [15:8] SHP19 5722 // 5723 // Shape element 19 5724 // ENUMs: 5725 // ALLONES All the bits are 1 5726 // ALLZEROS All the bits are 0 5727 #define LRFDRFE_DTX9_SHP19_W 8U 5728 #define LRFDRFE_DTX9_SHP19_M 0x0000FF00U 5729 #define LRFDRFE_DTX9_SHP19_S 8U 5730 #define LRFDRFE_DTX9_SHP19_ALLONES 0x0000FF00U 5731 #define LRFDRFE_DTX9_SHP19_ALLZEROS 0x00000000U 5732 5733 // Field: [7:0] SHP18 5734 // 5735 // Shape element 18 5736 // ENUMs: 5737 // ALLONES All the bits are 1 5738 // ALLZEROS All the bits are 0 5739 #define LRFDRFE_DTX9_SHP18_W 8U 5740 #define LRFDRFE_DTX9_SHP18_M 0x000000FFU 5741 #define LRFDRFE_DTX9_SHP18_S 0U 5742 #define LRFDRFE_DTX9_SHP18_ALLONES 0x000000FFU 5743 #define LRFDRFE_DTX9_SHP18_ALLZEROS 0x00000000U 5744 5745 //***************************************************************************** 5746 // 5747 // Register: LRFDRFE_O_DTX10 5748 // 5749 //***************************************************************************** 5750 // Field: [15:8] SHP21 5751 // 5752 // Shape element 21 5753 // ENUMs: 5754 // ALLONES All the bits are 1 5755 // ALLZEROS All the bits are 0 5756 #define LRFDRFE_DTX10_SHP21_W 8U 5757 #define LRFDRFE_DTX10_SHP21_M 0x0000FF00U 5758 #define LRFDRFE_DTX10_SHP21_S 8U 5759 #define LRFDRFE_DTX10_SHP21_ALLONES 0x0000FF00U 5760 #define LRFDRFE_DTX10_SHP21_ALLZEROS 0x00000000U 5761 5762 // Field: [7:0] SHP20 5763 // 5764 // Shape element 20 5765 // ENUMs: 5766 // ALLONES All the bits are 1 5767 // ALLZEROS All the bits are 0 5768 #define LRFDRFE_DTX10_SHP20_W 8U 5769 #define LRFDRFE_DTX10_SHP20_M 0x000000FFU 5770 #define LRFDRFE_DTX10_SHP20_S 0U 5771 #define LRFDRFE_DTX10_SHP20_ALLONES 0x000000FFU 5772 #define LRFDRFE_DTX10_SHP20_ALLZEROS 0x00000000U 5773 5774 //***************************************************************************** 5775 // 5776 // Register: LRFDRFE_O_DTX11 5777 // 5778 //***************************************************************************** 5779 // Field: [15:8] SHP23 5780 // 5781 // Shape element 23 5782 // ENUMs: 5783 // ALLONES All the bits are 1 5784 // ALLZEROS All the bits are 0 5785 #define LRFDRFE_DTX11_SHP23_W 8U 5786 #define LRFDRFE_DTX11_SHP23_M 0x0000FF00U 5787 #define LRFDRFE_DTX11_SHP23_S 8U 5788 #define LRFDRFE_DTX11_SHP23_ALLONES 0x0000FF00U 5789 #define LRFDRFE_DTX11_SHP23_ALLZEROS 0x00000000U 5790 5791 // Field: [7:0] SHP22 5792 // 5793 // Shape element 22 5794 // ENUMs: 5795 // ALLONES All the bits are 1 5796 // ALLZEROS All the bits are 0 5797 #define LRFDRFE_DTX11_SHP22_W 8U 5798 #define LRFDRFE_DTX11_SHP22_M 0x000000FFU 5799 #define LRFDRFE_DTX11_SHP22_S 0U 5800 #define LRFDRFE_DTX11_SHP22_ALLONES 0x000000FFU 5801 #define LRFDRFE_DTX11_SHP22_ALLZEROS 0x00000000U 5802 5803 //***************************************************************************** 5804 // 5805 // Register: LRFDRFE_O_PLLM0L 5806 // 5807 //***************************************************************************** 5808 // Field: [15:2] VALLSB 5809 // 5810 // PLLM0 value 5811 // 5812 // Field sets the desired output frequency of the PLL, FRF, using the default 5813 // PLL reference frequency, according to: 5814 // 5815 // M-value = FRF * (DIVIDER/2) / FREF0 5816 // 5817 // Field encoding is <12.18u> 5818 // 5819 // PRE0.PLLDIV0 determines FREF0. DIV.RATIO determines DIVIDER. 5820 // 5821 // INTERNAL NOTE: 5822 // * 2.1 GHz =< FRF * ((DIV.RATIO//2) <= 2.8 GHz 5823 // ENUMs: 5824 // ALLONES All the bits are 1 5825 // ALLZEROS All the bits are 0 5826 #define LRFDRFE_PLLM0L_VALLSB_W 14U 5827 #define LRFDRFE_PLLM0L_VALLSB_M 0x0000FFFCU 5828 #define LRFDRFE_PLLM0L_VALLSB_S 2U 5829 #define LRFDRFE_PLLM0L_VALLSB_ALLONES 0x0000FFFCU 5830 #define LRFDRFE_PLLM0L_VALLSB_ALLZEROS 0x00000000U 5831 5832 // Field: [1:0] SPARE0 5833 // 5834 // SPARE0 5835 // ENUMs: 5836 // ALLONES All the bits are 1 5837 // ALLZEROS All the bits are 0 5838 #define LRFDRFE_PLLM0L_SPARE0_W 2U 5839 #define LRFDRFE_PLLM0L_SPARE0_M 0x00000003U 5840 #define LRFDRFE_PLLM0L_SPARE0_S 0U 5841 #define LRFDRFE_PLLM0L_SPARE0_ALLONES 0x00000003U 5842 #define LRFDRFE_PLLM0L_SPARE0_ALLZEROS 0x00000000U 5843 5844 //***************************************************************************** 5845 // 5846 // Register: LRFDRFE_O_PLLM0H 5847 // 5848 //***************************************************************************** 5849 // Field: [15:0] VALMSB 5850 // 5851 // PLLM0 value 5852 // 5853 // Field sets the desired output frequency of the PLL, FRF, using the default 5854 // PLL reference frequency, according to: 5855 // 5856 // M-value = FRF * (DIVIDER/2) / FREF0 5857 // 5858 // Field encoding is <12.18u> 5859 // 5860 // PRE0.PLLDIV0 determines FREF0. DIV.RATIO determines DIVIDER. 5861 // 5862 // INTERNAL NOTE: 5863 // * 2.1 GHz =< FRF * ((DIV.RATIO//2) <= 2.8 GHz 5864 // ENUMs: 5865 // ALLONES All the bits are 1 5866 // ALLZEROS All the bits are 0 5867 #define LRFDRFE_PLLM0H_VALMSB_W 16U 5868 #define LRFDRFE_PLLM0H_VALMSB_M 0x0000FFFFU 5869 #define LRFDRFE_PLLM0H_VALMSB_S 0U 5870 #define LRFDRFE_PLLM0H_VALMSB_ALLONES 0x0000FFFFU 5871 #define LRFDRFE_PLLM0H_VALMSB_ALLZEROS 0x00000000U 5872 5873 //***************************************************************************** 5874 // 5875 // Register: LRFDRFE_O_PLLM1L 5876 // 5877 //***************************************************************************** 5878 // Field: [15:2] VALLSB 5879 // 5880 // PLLM1 value 5881 // 5882 // Field sets the desired output frequency of the PLL, FRF, using the default 5883 // PLL reference frequency, according to: 5884 // 5885 // M-value = FRF * (DIVIDER/2) / FREF1 5886 // 5887 // Field encoding is <12.18u> 5888 // 5889 // PRE0.PLLDIV1 determines FREF1. DIV.RATIO determines DIVIDER. 5890 // 5891 // INTERNAL NOTE: 5892 // * 2.1 GHz =< FRF * ((DIV.RATIO//2) <= 2.8 GHz 5893 // ENUMs: 5894 // ALLONES All the bits are 1 5895 // ALLZEROS All the bits are 0 5896 #define LRFDRFE_PLLM1L_VALLSB_W 14U 5897 #define LRFDRFE_PLLM1L_VALLSB_M 0x0000FFFCU 5898 #define LRFDRFE_PLLM1L_VALLSB_S 2U 5899 #define LRFDRFE_PLLM1L_VALLSB_ALLONES 0x0000FFFCU 5900 #define LRFDRFE_PLLM1L_VALLSB_ALLZEROS 0x00000000U 5901 5902 // Field: [1:0] SPARE0 5903 // 5904 // SPARE0 5905 // ENUMs: 5906 // ALLONES All the bits are 1 5907 // ALLZEROS All the bits are 0 5908 #define LRFDRFE_PLLM1L_SPARE0_W 2U 5909 #define LRFDRFE_PLLM1L_SPARE0_M 0x00000003U 5910 #define LRFDRFE_PLLM1L_SPARE0_S 0U 5911 #define LRFDRFE_PLLM1L_SPARE0_ALLONES 0x00000003U 5912 #define LRFDRFE_PLLM1L_SPARE0_ALLZEROS 0x00000000U 5913 5914 //***************************************************************************** 5915 // 5916 // Register: LRFDRFE_O_PLLM1H 5917 // 5918 //***************************************************************************** 5919 // Field: [15:0] VALMSB 5920 // 5921 // PLLM1 value 5922 // 5923 // Field sets the desired output frequency of the PLL, FRF, using the default 5924 // PLL reference frequency, according to: 5925 // 5926 // M-value = FRF * (DIVIDER/2) / FREF1 5927 // 5928 // Field encoding is <12.18u> 5929 // 5930 // PRE0.PLLDIV1 determines FREF1. DIV.RATIO determines DIVIDER. 5931 // 5932 // INTERNAL NOTE: 5933 // * 2.1 GHz =< FRF * ((DIV.RATIO//2) <= 2.8 GHz 5934 // ENUMs: 5935 // ALLONES All the bits are 1 5936 // ALLZEROS All the bits are 0 5937 #define LRFDRFE_PLLM1H_VALMSB_W 16U 5938 #define LRFDRFE_PLLM1H_VALMSB_M 0x0000FFFFU 5939 #define LRFDRFE_PLLM1H_VALMSB_S 0U 5940 #define LRFDRFE_PLLM1H_VALMSB_ALLONES 0x0000FFFFU 5941 #define LRFDRFE_PLLM1H_VALMSB_ALLZEROS 0x00000000U 5942 5943 //***************************************************************************** 5944 // 5945 // Register: LRFDRFE_O_CALMCRS 5946 // 5947 //***************************************************************************** 5948 // Field: [15:0] VAL 5949 // 5950 // Coarse SAR m-value 5951 // 5952 // Field sets the desired output frequency of the PLL, FRF, during coarse SAR, 5953 // according to: 5954 // 5955 // VAL = FRF * (DIVIDER/2) / COARSE_CALIB_FREF 5956 // 5957 // Field encoding is <16u>. 5958 // 5959 // PRE2.CRSCALDIV determines COARSE_CALIB_FREF. DIV.RATIO determines DIVIDER. 5960 // ENUMs: 5961 // ALLONES All the bits are 1 5962 // ALLZEROS All the bits are 0 5963 #define LRFDRFE_CALMCRS_VAL_W 16U 5964 #define LRFDRFE_CALMCRS_VAL_M 0x0000FFFFU 5965 #define LRFDRFE_CALMCRS_VAL_S 0U 5966 #define LRFDRFE_CALMCRS_VAL_ALLONES 0x0000FFFFU 5967 #define LRFDRFE_CALMCRS_VAL_ALLZEROS 0x00000000U 5968 5969 //***************************************************************************** 5970 // 5971 // Register: LRFDRFE_O_CALMMID 5972 // 5973 //***************************************************************************** 5974 // Field: [15:0] VAL 5975 // 5976 // Mid SAR m-value 5977 // 5978 // Field sets the desired output frequency of the PLL, FRF, during mid SAR, 5979 // according to: 5980 // 5981 // VAL = FRF * (DIVIDER/2) / MID_CALIB_FREF 5982 // 5983 // Field encoding is <16u>. 5984 // 5985 // PRE2.MIDCALDIVLSB and PRE3.MIDCALDIVMSB determines MID_CALIB_FREF. 5986 // DIV.RATIO determines DIVIDER. 5987 // ENUMs: 5988 // ALLONES All the bits are 1 5989 // ALLZEROS All the bits are 0 5990 #define LRFDRFE_CALMMID_VAL_W 16U 5991 #define LRFDRFE_CALMMID_VAL_M 0x0000FFFFU 5992 #define LRFDRFE_CALMMID_VAL_S 0U 5993 #define LRFDRFE_CALMMID_VAL_ALLONES 0x0000FFFFU 5994 #define LRFDRFE_CALMMID_VAL_ALLZEROS 0x00000000U 5995 5996 //***************************************************************************** 5997 // 5998 // Register: LRFDRFE_O_REFDIV 5999 // 6000 //***************************************************************************** 6001 // Field: [15:0] LOAD 6002 // 6003 // Load value for 16-bit REFCLK prescaler 6004 // 6005 // The REFCLK prescaler is used when DLOCTL0.LOOPUPD bit-2 = 1. 6006 // ENUMs: 6007 // ALLONES All the bits are 1 6008 // ALLZEROS All the bits are 0 6009 #define LRFDRFE_REFDIV_LOAD_W 16U 6010 #define LRFDRFE_REFDIV_LOAD_M 0x0000FFFFU 6011 #define LRFDRFE_REFDIV_LOAD_S 0U 6012 #define LRFDRFE_REFDIV_LOAD_ALLONES 0x0000FFFFU 6013 #define LRFDRFE_REFDIV_LOAD_ALLZEROS 0x00000000U 6014 6015 //***************************************************************************** 6016 // 6017 // Register: LRFDRFE_O_DLOCTL0 6018 // 6019 //***************************************************************************** 6020 // Field: [10:8] TDCSTOP 6021 // 6022 // TDC stop configuration 6023 // 6024 // During TDC calibration the value specifies the pulse duration used to 6025 // calculate the TDC gain as number of CKVD periods (2 / FDCO). Value 6026 // effectively sets the resolution of the FW-calculated CAL2.KTDCINV. 6027 // 6028 // Otherwise, the TDC stop delay is programmable in units of CKVD clock 6029 // periods. The stop delay is either static or randomly decided per reference 6030 // clock period. The latter is referred to as TDC stop-time dithering. 6031 // 6032 // 000: TDC stops when flop 0 becomes 1. During TDC calibration pulse length is 6033 // 1 CKVD period. 6034 // 001: TDC stops when flop 1 becomes 1. During TDC calibration pulse length is 6035 // 2 CKVD periods. 6036 // 010: TDC stops when flop 2 becomes 1. During TDC calibration pulse length is 6037 // 3 CKVD periods. 6038 // 011: TDC stops when flop 3 becomes 1. During TDC calibration pulse length is 6039 // 4 CKVD periods. 6040 // 1xx: TDC stops when a randomly chosen flop becomes 1. Do not use for TDC 6041 // calibration. 6042 // ENUMs: 6043 // OPEN Open-loop operation 6044 // CLOSED Closed-loop operation 6045 #define LRFDRFE_DLOCTL0_TDCSTOP_W 3U 6046 #define LRFDRFE_DLOCTL0_TDCSTOP_M 0x00000700U 6047 #define LRFDRFE_DLOCTL0_TDCSTOP_S 8U 6048 #define LRFDRFE_DLOCTL0_TDCSTOP_OPEN 0x00000100U 6049 #define LRFDRFE_DLOCTL0_TDCSTOP_CLOSED 0x00000000U 6050 6051 // Field: [7] DTSTXTAL 6052 // 6053 // XTALBAW DTST interface control 6054 // 6055 // Configure DTST interface in DTST when interface is disabled. 6056 // ENUMs: 6057 // ONE Enable XTALBAW DTST interface 6058 // ZERO Disable XTALBAW DTST interface 6059 #define LRFDRFE_DLOCTL0_DTSTXTAL 0x00000080U 6060 #define LRFDRFE_DLOCTL0_DTSTXTAL_M 0x00000080U 6061 #define LRFDRFE_DLOCTL0_DTSTXTAL_S 7U 6062 #define LRFDRFE_DLOCTL0_DTSTXTAL_ONE 0x00000080U 6063 #define LRFDRFE_DLOCTL0_DTSTXTAL_ZERO 0x00000000U 6064 6065 // Field: [6:4] LOOPUPD 6066 // 6067 // Loop update control 6068 // 6069 // The PLL frequency and loop dynamics are controlled through a set of 6070 // configurations of coarse and mid codes, TCD gain, reference clock divider, 6071 // and feedback divider(PLLM). Registers for PLLM and reference clock dividers 6072 // are duplicated to support REFCLK dithering, and/or loop BW gearing. These 6073 // are set 0 and set 1. It is also possible to update all configurations at 6074 // certain events to move the frequency around in the tuning range, and adjust 6075 // the loop bandwidth at the same time. Basically: 6076 // - bit-0: Static control set select (manual switch-FW) 6077 // 0 : select control set 0. 6078 // 1 : select control set 1. 6079 // - bit-1: Dithering select (automatic switch-LFSR) 6080 // 0: Functionality unused. 6081 // 1: LFSR single bit output is used to select control set according to 6082 // bit-0 select rules. Average F_REFCLK to be used in Ki equation is the 6083 // harmonic mean, F_REFCLK = 2/[1/F_REFCLK0 + 1/F_REFCLK1]. 6084 // - bit-2: Timer select (automatic switch-prescaler) 6085 // 0: Functionality unused. 6086 // 1: On every REFDIV.LOAD REFCLK event DLO toggles the control set select. 6087 // FW can update the one not used. 6088 // 6089 // There are restrictions on legal settings and transitions. 6090 // 6091 // INTERNAL NOTE: 6092 // See the implementation specification for explicit details and rules when 6093 // using this register. 6094 // ENUMs: 6095 // ALT Use alternate REF (PLLM1) 6096 // DEF Use default FREF (PLLM0) 6097 #define LRFDRFE_DLOCTL0_LOOPUPD_W 3U 6098 #define LRFDRFE_DLOCTL0_LOOPUPD_M 0x00000070U 6099 #define LRFDRFE_DLOCTL0_LOOPUPD_S 4U 6100 #define LRFDRFE_DLOCTL0_LOOPUPD_ALT 0x00000010U 6101 #define LRFDRFE_DLOCTL0_LOOPUPD_DEF 0x00000000U 6102 6103 // Field: [3] PH3 6104 // 6105 // Lock aquisition / calibration phase 3 control 6106 // ENUMs: 6107 // START Close the loop to aquire phase lock, i.e. phase 3 6108 // of calibration routine. 6109 // HALT Halt DLO FSM after DCO frequency span measurement 6110 // 6111 // When DLO and RFE runs 6112 // KDCO estimation, RFE must compute KDCO from the 6113 // frequency span, and calculate loop filter 6114 // settings to use before lock aquisition. 6115 #define LRFDRFE_DLOCTL0_PH3 0x00000008U 6116 #define LRFDRFE_DLOCTL0_PH3_M 0x00000008U 6117 #define LRFDRFE_DLOCTL0_PH3_S 3U 6118 #define LRFDRFE_DLOCTL0_PH3_START 0x00000008U 6119 #define LRFDRFE_DLOCTL0_PH3_HALT 0x00000000U 6120 6121 // Field: [2] PH2 6122 // 6123 // KDCO estimation / calibration phase 2 control 6124 // ENUMs: 6125 // START Start KDCO estimation, i.e. phase 2 of calibration 6126 // routine. 6127 // HALT Halt DLO FSM after TDC calibration measurement 6128 // 6129 // When DLO and RFE runs TDC 6130 // calibration, RFE must use calibration 6131 // measurement to calculcate CAL2.KTDCINV. 6132 #define LRFDRFE_DLOCTL0_PH2 0x00000004U 6133 #define LRFDRFE_DLOCTL0_PH2_M 0x00000004U 6134 #define LRFDRFE_DLOCTL0_PH2_S 2U 6135 #define LRFDRFE_DLOCTL0_PH2_START 0x00000004U 6136 #define LRFDRFE_DLOCTL0_PH2_HALT 0x00000000U 6137 6138 // Field: [1] LOOPMODE 6139 // 6140 // Loop mode control 6141 // ENUMs: 6142 // OPEN Open-loop operation 6143 // CLOSED Closed-loop operation 6144 #define LRFDRFE_DLOCTL0_LOOPMODE 0x00000002U 6145 #define LRFDRFE_DLOCTL0_LOOPMODE_M 0x00000002U 6146 #define LRFDRFE_DLOCTL0_LOOPMODE_S 1U 6147 #define LRFDRFE_DLOCTL0_LOOPMODE_OPEN 0x00000002U 6148 #define LRFDRFE_DLOCTL0_LOOPMODE_CLOSED 0x00000000U 6149 6150 // Field: [0] RSTN 6151 // 6152 // DLO reset 6153 // 6154 // DLO active low reset. The DLO has several static inputs that all needs to be 6155 // set prior to releasing reset. 6156 // 6157 // INTERNAL NOTE: 6158 // * Consult with LRFDLO implementation specification to see classification of 6159 // static, pseudo-static, and dynamic inputs. 6160 // ENUMs: 6161 // ACTIVE DLO is not held in reset 6162 // RESET DLO is reset 6163 #define LRFDRFE_DLOCTL0_RSTN 0x00000001U 6164 #define LRFDRFE_DLOCTL0_RSTN_M 0x00000001U 6165 #define LRFDRFE_DLOCTL0_RSTN_S 0U 6166 #define LRFDRFE_DLOCTL0_RSTN_ACTIVE 0x00000001U 6167 #define LRFDRFE_DLOCTL0_RSTN_RESET 0x00000000U 6168 6169 //***************************************************************************** 6170 // 6171 // Register: LRFDRFE_O_DLOCTL1 6172 // 6173 //***************************************************************************** 6174 // Field: [15] DCO 6175 // 6176 // DCO control 6177 // ENUMs: 6178 // EN Enable DCO 6179 // DIS Disable DCO 6180 #define LRFDRFE_DLOCTL1_DCO 0x00008000U 6181 #define LRFDRFE_DLOCTL1_DCO_M 0x00008000U 6182 #define LRFDRFE_DLOCTL1_DCO_S 15U 6183 #define LRFDRFE_DLOCTL1_DCO_EN 0x00008000U 6184 #define LRFDRFE_DLOCTL1_DCO_DIS 0x00000000U 6185 6186 // Field: [7] FCDEM 6187 // 6188 // Finecode dynamic element match control 6189 // ENUMs: 6190 // EN Enable DEM 6191 // DIS Disable DEM 6192 #define LRFDRFE_DLOCTL1_FCDEM 0x00000080U 6193 #define LRFDRFE_DLOCTL1_FCDEM_M 0x00000080U 6194 #define LRFDRFE_DLOCTL1_FCDEM_S 7U 6195 #define LRFDRFE_DLOCTL1_FCDEM_EN 0x00000080U 6196 #define LRFDRFE_DLOCTL1_FCDEM_DIS 0x00000000U 6197 6198 // Field: [6] DTSTCKVD 6199 // 6200 // CKVD DTST interface control 6201 // 6202 // Configure DTST interface in DTST when interface is disabled. 6203 // ENUMs: 6204 // ONE Enable CKVD DTST interface 6205 // ZERO Disable CKVD DTST interface 6206 #define LRFDRFE_DLOCTL1_DTSTCKVD 0x00000040U 6207 #define LRFDRFE_DLOCTL1_DTSTCKVD_M 0x00000040U 6208 #define LRFDRFE_DLOCTL1_DTSTCKVD_S 6U 6209 #define LRFDRFE_DLOCTL1_DTSTCKVD_ONE 0x00000040U 6210 #define LRFDRFE_DLOCTL1_DTSTCKVD_ZERO 0x00000000U 6211 6212 // Field: [5] PHEDISC 6213 // 6214 // Phase error discarding control 6215 // 6216 // Feature discards large phase errors from propagating into the loop filter. 6217 // PHEDISC configures the behavior. 6218 // ENUMs: 6219 // EN Enable phase error discard function 6220 // DIS Disable phase error discard function 6221 #define LRFDRFE_DLOCTL1_PHEDISC 0x00000020U 6222 #define LRFDRFE_DLOCTL1_PHEDISC_M 0x00000020U 6223 #define LRFDRFE_DLOCTL1_PHEDISC_S 5U 6224 #define LRFDRFE_DLOCTL1_PHEDISC_EN 0x00000020U 6225 #define LRFDRFE_DLOCTL1_PHEDISC_DIS 0x00000000U 6226 6227 // Field: [4] PLLMON 6228 // 6229 // PLL monitor control 6230 // 6231 // The PLL monitor detects the following PLL states in the variable clock 6232 // domain: 6233 // - Lock (static) 6234 // - Loss of lock (dynamic) 6235 // - Fine code above threshold (static) 6236 // - Fine code below threshold (static) 6237 // 6238 // The monitor signals the occurence of these conditions to the reference clock 6239 // domain. This domain does positive edge detection for lock and loss-of-lock 6240 // events, and synchronizes the threshold events. The IRQ to modem is high 6241 // whenever reference clock domain events are high. 6242 // 6243 // The lock and loss-of-lock flags are cleared individually in the reference 6244 // clock domain. Disable the PLL monitor to reset the all event flags in the 6245 // variable clock domain. PLL Lock and Loss of Lock flags are automatically 6246 // cleared in the variable clock domain when transitioning from open-loop to 6247 // closed-loop operation. 6248 // 6249 // To clear Lock and Loss of Lock flags using this field, the DLO must operate 6250 // in closed-loop mode, and a new value must be stable for at least 2 REFCLK 6251 // periods. 6252 // 6253 // Keep PLL monitor disabled during the calibration states. 6254 // ENUMs: 6255 // EN Enable PLL monitor 6256 // DIS Disable and reset PLL monitor 6257 #define LRFDRFE_DLOCTL1_PLLMON 0x00000010U 6258 #define LRFDRFE_DLOCTL1_PLLMON_M 0x00000010U 6259 #define LRFDRFE_DLOCTL1_PLLMON_S 4U 6260 #define LRFDRFE_DLOCTL1_PLLMON_EN 0x00000010U 6261 #define LRFDRFE_DLOCTL1_PLLMON_DIS 0x00000000U 6262 6263 // Field: [3] IIR 6264 // 6265 // IIR control 6266 // 6267 // Do not enable during lock aquisition. 6268 // ENUMs: 6269 // EN Enable IIR filter 6270 // DIS Disable IIR filter 6271 #define LRFDRFE_DLOCTL1_IIR 0x00000008U 6272 #define LRFDRFE_DLOCTL1_IIR_M 0x00000008U 6273 #define LRFDRFE_DLOCTL1_IIR_S 3U 6274 #define LRFDRFE_DLOCTL1_IIR_EN 0x00000008U 6275 #define LRFDRFE_DLOCTL1_IIR_DIS 0x00000000U 6276 6277 // Field: [2] MOD 6278 // 6279 // Modulator control 6280 // 6281 // Enable of MODISF (Modulator's Interpolating Shaping Filter) 6282 // ENUMs: 6283 // EN Enable MODISF 6284 // DIS Disable MODISF 6285 #define LRFDRFE_DLOCTL1_MOD 0x00000004U 6286 #define LRFDRFE_DLOCTL1_MOD_M 0x00000004U 6287 #define LRFDRFE_DLOCTL1_MOD_S 2U 6288 #define LRFDRFE_DLOCTL1_MOD_EN 0x00000004U 6289 #define LRFDRFE_DLOCTL1_MOD_DIS 0x00000000U 6290 6291 // Field: [1] MODINIT 6292 // 6293 // Modulator Initialization 6294 // ENUMs: 6295 // ACTIVATE Activate MODISF initialization 6296 // DEACTIVATE Deactivate MODISF initialization 6297 #define LRFDRFE_DLOCTL1_MODINIT 0x00000002U 6298 #define LRFDRFE_DLOCTL1_MODINIT_M 0x00000002U 6299 #define LRFDRFE_DLOCTL1_MODINIT_S 1U 6300 #define LRFDRFE_DLOCTL1_MODINIT_ACTIVATE 0x00000002U 6301 #define LRFDRFE_DLOCTL1_MODINIT_DEACTIVATE 0x00000000U 6302 6303 // Field: [0] MTDCRSTN 6304 // 6305 // MTDC reset 6306 // ENUMs: 6307 // ACTIVE Release MTDC reset 6308 // RESET Reset MTDC 6309 #define LRFDRFE_DLOCTL1_MTDCRSTN 0x00000001U 6310 #define LRFDRFE_DLOCTL1_MTDCRSTN_M 0x00000001U 6311 #define LRFDRFE_DLOCTL1_MTDCRSTN_S 0U 6312 #define LRFDRFE_DLOCTL1_MTDCRSTN_ACTIVE 0x00000001U 6313 #define LRFDRFE_DLOCTL1_MTDCRSTN_RESET 0x00000000U 6314 6315 //***************************************************************************** 6316 // 6317 // Register: LRFDRFE_O_DCOOVR0 6318 // 6319 //***************************************************************************** 6320 // Field: [13:8] MIDCODE 6321 // 6322 // Mid code override 6323 // 6324 // When MIDCTL equals EN, field value overrides the DCO mid code, which sets 6325 // the DCO mid row and column control. Special encoding: 6326 // MIDCODE[5:4]: 6327 // 00: DCO mid row = 15 6328 // 01: DCO mid row = 7 6329 // 10: DCO mid row = 3 6330 // 11: DCO mid row = 1 6331 // 6332 // DCO mid column = 15-to_integer(MIDCODE[3:0]) 6333 // ENUMs: 6334 // ALLONES All the bits are 1 6335 // ALLZEROS All the bits are 0 6336 #define LRFDRFE_DCOOVR0_MIDCODE_W 6U 6337 #define LRFDRFE_DCOOVR0_MIDCODE_M 0x00003F00U 6338 #define LRFDRFE_DCOOVR0_MIDCODE_S 8U 6339 #define LRFDRFE_DCOOVR0_MIDCODE_ALLONES 0x00003F00U 6340 #define LRFDRFE_DCOOVR0_MIDCODE_ALLZEROS 0x00000000U 6341 6342 // Field: [7:4] CRSCODE 6343 // 6344 // Coarse code override 6345 // 6346 // When CRSCTL equals EN, field value overrides the DCO coarse control. This is 6347 // required during debug and when coarse calibration is skipped, or we want to 6348 // use other values during startup of ALO. Encoding is <4.0u>: 6349 // 6350 // 0xFF: min frequency 6351 // … 6352 // 0x00: max frequency 6353 // ENUMs: 6354 // ALLONES All the bits are 1 6355 // ALLZEROS All the bits are 0 6356 #define LRFDRFE_DCOOVR0_CRSCODE_W 4U 6357 #define LRFDRFE_DCOOVR0_CRSCODE_M 0x000000F0U 6358 #define LRFDRFE_DCOOVR0_CRSCODE_S 4U 6359 #define LRFDRFE_DCOOVR0_CRSCODE_ALLONES 0x000000F0U 6360 #define LRFDRFE_DCOOVR0_CRSCODE_ALLZEROS 0x00000000U 6361 6362 // Field: [3] FINECTL 6363 // 6364 // Fine code override control 6365 // ENUMs: 6366 // EN Enable fine code override 6367 // DIS Disable fine code override 6368 #define LRFDRFE_DCOOVR0_FINECTL 0x00000008U 6369 #define LRFDRFE_DCOOVR0_FINECTL_M 0x00000008U 6370 #define LRFDRFE_DCOOVR0_FINECTL_S 3U 6371 #define LRFDRFE_DCOOVR0_FINECTL_EN 0x00000008U 6372 #define LRFDRFE_DCOOVR0_FINECTL_DIS 0x00000000U 6373 6374 // Field: [2] SDMICTL 6375 // 6376 // SDM input code override control 6377 // ENUMs: 6378 // EN Enable SDM input code override 6379 // DIS Disable SDM input code override 6380 #define LRFDRFE_DCOOVR0_SDMICTL 0x00000004U 6381 #define LRFDRFE_DCOOVR0_SDMICTL_M 0x00000004U 6382 #define LRFDRFE_DCOOVR0_SDMICTL_S 2U 6383 #define LRFDRFE_DCOOVR0_SDMICTL_EN 0x00000004U 6384 #define LRFDRFE_DCOOVR0_SDMICTL_DIS 0x00000000U 6385 6386 // Field: [1] MIDCTL 6387 // 6388 // Mid code override control 6389 // ENUMs: 6390 // EN Enable mid code override 6391 // DIS Disable mid code override 6392 #define LRFDRFE_DCOOVR0_MIDCTL 0x00000002U 6393 #define LRFDRFE_DCOOVR0_MIDCTL_M 0x00000002U 6394 #define LRFDRFE_DCOOVR0_MIDCTL_S 1U 6395 #define LRFDRFE_DCOOVR0_MIDCTL_EN 0x00000002U 6396 #define LRFDRFE_DCOOVR0_MIDCTL_DIS 0x00000000U 6397 6398 // Field: [0] CRSCTL 6399 // 6400 // Coarse code override 6401 // ENUMs: 6402 // EN Enable coarse code override 6403 // DIS Disable coarse code override 6404 #define LRFDRFE_DCOOVR0_CRSCTL 0x00000001U 6405 #define LRFDRFE_DCOOVR0_CRSCTL_M 0x00000001U 6406 #define LRFDRFE_DCOOVR0_CRSCTL_S 0U 6407 #define LRFDRFE_DCOOVR0_CRSCTL_EN 0x00000001U 6408 #define LRFDRFE_DCOOVR0_CRSCTL_DIS 0x00000000U 6409 6410 //***************************************************************************** 6411 // 6412 // Register: LRFDRFE_O_DCOOVR1 6413 // 6414 //***************************************************************************** 6415 // Field: [14:8] FINECODE 6416 // 6417 // Fine code override 6418 // 6419 // When DCOOVR0.FINECTL equals EN, field value overrides the integer part of 6420 // DCO fine code . 6421 // 6422 // Encoding is <7.0u>: 6423 // 0x00: Min 6424 // ... 6425 // 0x7F: MAX 6426 // ENUMs: 6427 // ALLONES All the bits are 1 6428 // ALLZEROS All the bits are 0 6429 #define LRFDRFE_DCOOVR1_FINECODE_W 7U 6430 #define LRFDRFE_DCOOVR1_FINECODE_M 0x00007F00U 6431 #define LRFDRFE_DCOOVR1_FINECODE_S 8U 6432 #define LRFDRFE_DCOOVR1_FINECODE_ALLONES 0x00007F00U 6433 #define LRFDRFE_DCOOVR1_FINECODE_ALLZEROS 0x00000000U 6434 6435 // Field: [7:0] SDMICODE 6436 // 6437 // SDM input code override 6438 // 6439 // When DCOOVR0.SDMICTL equals EN, field value overrides the fractional part of 6440 // DCO fine code to SDM. Encoding is <0.8u>: 6441 // 0x00: 0 6442 // ... 6443 // 0x7F: 0.99609375 6444 // 6445 // The fractional value is added to the integer part. 6446 // ENUMs: 6447 // ALLONES All the bits are 1 6448 // ALLZEROS All the bits are 0 6449 #define LRFDRFE_DCOOVR1_SDMICODE_W 8U 6450 #define LRFDRFE_DCOOVR1_SDMICODE_M 0x000000FFU 6451 #define LRFDRFE_DCOOVR1_SDMICODE_S 0U 6452 #define LRFDRFE_DCOOVR1_SDMICODE_ALLONES 0x000000FFU 6453 #define LRFDRFE_DCOOVR1_SDMICODE_ALLZEROS 0x00000000U 6454 6455 //***************************************************************************** 6456 // 6457 // Register: LRFDRFE_O_DTST 6458 // 6459 //***************************************************************************** 6460 // Field: [14:11] SPARE11 6461 // 6462 // SPARE111 6463 // ENUMs: 6464 // ALLONES All the bits are 1 6465 // ALLZEROS All the bits are 0 6466 #define LRFDRFE_DTST_SPARE11_W 4U 6467 #define LRFDRFE_DTST_SPARE11_M 0x00007800U 6468 #define LRFDRFE_DTST_SPARE11_S 11U 6469 #define LRFDRFE_DTST_SPARE11_ALLONES 0x00007800U 6470 #define LRFDRFE_DTST_SPARE11_ALLZEROS 0x00000000U 6471 6472 // Field: [10:8] VARTGLDLY 6473 // 6474 // Variable domain toggle delay 6475 // 6476 // Field sets delay on toggle launch compared to data launch. CLK equals launch 6477 // clock for signal selected in SIG. It can be eiter CKVD16 or reference clock. 6478 // ENUMs: 6479 // CLK_7_PER Toggle lags data by 7 CKVD16 periods. 6480 // CLK_6_PER Toggle lags data by 6 CKVD16 periods. 6481 // CLK_5_PER Toggle lags data by 5 CKVD16 periods. 6482 // CLK_4_PER Toggle lags data by 4 CKVD16 periods. 6483 // CLK_3_PER Toggle lags data by 3 CKVD16 periods. 6484 // CLK_2_PER Toggle lags data by 2 CKVD16 periods. 6485 // CLK_1_PER Toggle lags data by 1 CKVD16 periods. 6486 // CLK_0_PER Toggle lags data by 0 CKVD16 periods. 6487 #define LRFDRFE_DTST_VARTGLDLY_W 3U 6488 #define LRFDRFE_DTST_VARTGLDLY_M 0x00000700U 6489 #define LRFDRFE_DTST_VARTGLDLY_S 8U 6490 #define LRFDRFE_DTST_VARTGLDLY_CLK_7_PER 0x00000700U 6491 #define LRFDRFE_DTST_VARTGLDLY_CLK_6_PER 0x00000600U 6492 #define LRFDRFE_DTST_VARTGLDLY_CLK_5_PER 0x00000500U 6493 #define LRFDRFE_DTST_VARTGLDLY_CLK_4_PER 0x00000400U 6494 #define LRFDRFE_DTST_VARTGLDLY_CLK_3_PER 0x00000300U 6495 #define LRFDRFE_DTST_VARTGLDLY_CLK_2_PER 0x00000200U 6496 #define LRFDRFE_DTST_VARTGLDLY_CLK_1_PER 0x00000100U 6497 #define LRFDRFE_DTST_VARTGLDLY_CLK_0_PER 0x00000000U 6498 6499 // Field: [7] REFTGLDLY 6500 // 6501 // Reference domain toggle delay 6502 // 6503 // Field sets delay on toggle launch compared to data launch. CLK equals launch 6504 // clock for signal selected in SIG. It can be eiter CKVD16 or reference clock. 6505 // ENUMs: 6506 // CLK_1_PER Toggle lags data by 1 HFXT/BAW periods. 6507 // CLK_0_PER Toggle lags data by 0 HFXT/BAW periods. 6508 #define LRFDRFE_DTST_REFTGLDLY 0x00000080U 6509 #define LRFDRFE_DTST_REFTGLDLY_M 0x00000080U 6510 #define LRFDRFE_DTST_REFTGLDLY_S 7U 6511 #define LRFDRFE_DTST_REFTGLDLY_CLK_1_PER 0x00000080U 6512 #define LRFDRFE_DTST_REFTGLDLY_CLK_0_PER 0x00000000U 6513 6514 // Field: [6] TRNSEQ 6515 // 6516 // Trainer sequence control 6517 // 6518 // When trainer sequence is enabled, dtst data will not reflect SIG 6519 // configuration. Instead, it will toggle between 0x5555 and 0xAAAA for every 6520 // update uof the data specified by SIG. 6521 // ENUMs: 6522 // EN Enable trainer sequence 6523 // DIS Disable trainer sequence 6524 #define LRFDRFE_DTST_TRNSEQ 0x00000040U 6525 #define LRFDRFE_DTST_TRNSEQ_M 0x00000040U 6526 #define LRFDRFE_DTST_TRNSEQ_S 6U 6527 #define LRFDRFE_DTST_TRNSEQ_EN 0x00000040U 6528 #define LRFDRFE_DTST_TRNSEQ_DIS 0x00000000U 6529 6530 // Field: [5] SPARE5 6531 // 6532 // SPARE5 6533 // ENUMs: 6534 // ONE The bit is 1 6535 // ZERO The bit is 0 6536 #define LRFDRFE_DTST_SPARE5 0x00000020U 6537 #define LRFDRFE_DTST_SPARE5_M 0x00000020U 6538 #define LRFDRFE_DTST_SPARE5_S 5U 6539 #define LRFDRFE_DTST_SPARE5_ONE 0x00000020U 6540 #define LRFDRFE_DTST_SPARE5_ZERO 0x00000000U 6541 6542 // Field: [4:0] SIG 6543 // 6544 // Signal Configuration 6545 // 6546 // Selects which signal to route to DTST data port. Any change to MSB may 6547 // cause modem to detect false toggle. Hence, the first sample must be 6548 // discarded in modem after a change to MSB. 6549 // 6550 // Whenever signal po_tdc_stop_dly_sel is sampled, discard the first three 6551 // samples. 6552 // 6553 // All bits in dtst_data vector originates from the same reference clock edge, 6554 // unless otherwise noted. 6555 // ENUMs: 6556 // VAR_NC_15 dtst_data = 0x0000 6557 // VAR_NC_14 dtst_data = 0x0000 6558 // VAR_NC_13 dtst_data = 0x0000 6559 // VAR_NC_12 dtst_data = 0x0000 6560 // VAR_NC_11 dtst_data = 0x0000 6561 // VAR_LOOP_UPD_FINECODE dtst_data : 6562 // 6563 // [15] : 6564 // (u_pll/pll_loop_update) 6565 // [14:0] : 6566 // u_pll/po_ckvd16_finecode_pll 6567 // VAR_LOCK_FINECODE dtst_data : 6568 // 6569 // [15] : 6570 // (u_pll/po_ckvd48_pllmon_lock XOR 6571 // u_pll/po_ckvd48_pllmon_lol) 6572 // [14:0] : 6573 // u_pll/po_ckvd16_finecode_pll 6574 // VAR_MPX_CAN dtst_data : 6575 // 6576 // [15] : u_mpx/freq_can[16] 6577 // [14:0] : 6578 // u_mpx/freq_can[14:0] 6579 // 6580 // Format is 1.15s. This 6581 // field holds how much phase DTX adds to DCO per 6582 // reference frequency. This is a slice of the 6583 // signals that goes to u_pll which is 3.18s. 6584 // Hence, wrapping can occur. 6585 // VAR_TDCSTOP_STATUS_TDC dtst_data : 6586 // 6587 // [15:14] : 6588 // po_tdc_stop_dly_sel 6589 // [13] : 6590 // u_pll/pi_tdc_msb_error 6591 // [12] : 6592 // u_pll/pll_loop_update 6593 // [11] : 6594 // (u_pll/po_ckvd48_pllmon_lock XOR 6595 // u_pll/po_ckvd48_pllmon_lol) 6596 // [10:0]: 6597 // u_pll/pi_tdc_data 6598 // 6599 // Note that [12:11] are 6600 // samples from previous reference clock edge. 6601 // VAR_TDCSTOP_PHERR dtst_data : 6602 // 6603 // [15:14] : 6604 // po_tdc_stop_dly_sel 6605 // [13] 6606 // u_pll/phase_error[16] 6607 // [12:0]: 6608 // u_pll/phase_error[12:0] 6609 // 6610 // [13:0] : phase_error. 6611 // Format is 3.11s. 6612 // VAR_PH_COMP_PHERR_TDCSTOPdtst_data : 6613 // 6614 // [15:14] : 6615 // po_tdc_stop_dly_sel 6616 // [13] : 6617 // u_pll/phase_error[16] 6618 // [12:9]: 6619 // u_pll/phase_error[11:8] 6620 // [8:0] : 6621 // u_pll/var_phase[14: 6] 6622 // 6623 // [13:9] : phase error. 6624 // Format is 2.3s. 6625 // [8:0] : variable phase. 6626 // Format is 4.5u. 6627 // VAR_PH_TDCCORR dtst_data : 6628 // 6629 // [15] ; 6630 // u_pll/pi_tdc_msb_error 6631 // [14:11] : 6632 // u_pll/pi_pi_cnt_lsb 6633 // [10:0] : 6634 // u_pll/tdc_data_corr 6635 // VAR_PH_RAW dtst_data : 6636 // 6637 // [15] ; 6638 // u_pll/pi_tdc_msb_error 6639 // [14:11] : 6640 // u_pll/pi_pi_cnt_lsb 6641 // [10:0] : 6642 // u_pll/pi_tdc_data 6643 // VAR_PHERR_LOWER dtst_data : 6644 // 6645 // [15] : 6646 // u_pll/phase_error[16] 6647 // [14:0] : 6648 // u_pll/phase_error[14:0] 6649 // 6650 // Format is 5.11s. Phase 6651 // error wraps if if too large. 6652 // VAR_PHERR_UPPER dtst_data = u_pll/phase_error[16:1] 6653 // 6654 // Format is 6.10s. 6655 // VAR_NC_0 dtst_data = 0x0000 6656 // REF_NC_15 dtst_data = 0x0000 6657 // REF_NC_14 dtst_data = 0x0000 6658 // REF_NC_13 dtst_data = 0x0000 6659 // REF_NC_12 dtst_data = 0x0000 6660 // REF_NC_11 dtst_data = 0x0000 6661 // REF_NC_10 dtst_data = 0x0000 6662 // REF_NC_9 dtst_data = 0x0000 6663 // REF_NC_8 dtst_data = 0x0000 6664 // REF_NC_7 dtst_data = 0x0000 6665 // REF_NC_6 dtst_data = 0x0000 6666 // REF_NC_5 dtst_data = 0x0000 6667 // REF_NC_4 dtst_data = 0x0000 6668 // REF_NC_3 dtst_data = 0x0000 6669 // REF_FERR_MAG dtst_data = u_fsm/po_dtst_fsm_ferr_mag 6670 // 6671 // Format is14.2u. The 6672 // signal is only updated for frequency 6673 // measurements that affect the calibration 6674 // result. 6675 // REF_FSMCAL dtst_data : 6676 // 6677 // [15] : '0' 6678 // [14] : 6679 // u_fsm/pi_pll_lock_ind 6680 // [13:10] : 6681 // u_fsm/po_dsts_fsm_state 6682 // [9:6] : 6683 // u_fsm/po_dtst_fsm_coarse 6684 // [5:0] : 6685 // u_fsm/po_dtst_fsm_mid 6686 // REF_NC_0 dtst_data = 0x0000 6687 #define LRFDRFE_DTST_SIG_W 5U 6688 #define LRFDRFE_DTST_SIG_M 0x0000001FU 6689 #define LRFDRFE_DTST_SIG_S 0U 6690 #define LRFDRFE_DTST_SIG_VAR_NC_15 0x0000001FU 6691 #define LRFDRFE_DTST_SIG_VAR_NC_14 0x0000001EU 6692 #define LRFDRFE_DTST_SIG_VAR_NC_13 0x0000001DU 6693 #define LRFDRFE_DTST_SIG_VAR_NC_12 0x0000001CU 6694 #define LRFDRFE_DTST_SIG_VAR_NC_11 0x0000001BU 6695 #define LRFDRFE_DTST_SIG_VAR_LOOP_UPD_FINECODE 0x0000001AU 6696 #define LRFDRFE_DTST_SIG_VAR_LOCK_FINECODE 0x00000019U 6697 #define LRFDRFE_DTST_SIG_VAR_MPX_CAN 0x00000018U 6698 #define LRFDRFE_DTST_SIG_VAR_TDCSTOP_STATUS_TDC 0x00000017U 6699 #define LRFDRFE_DTST_SIG_VAR_TDCSTOP_PHERR 0x00000016U 6700 #define LRFDRFE_DTST_SIG_VAR_PH_COMP_PHERR_TDCSTOP 0x00000015U 6701 #define LRFDRFE_DTST_SIG_VAR_PH_TDCCORR 0x00000014U 6702 #define LRFDRFE_DTST_SIG_VAR_PH_RAW 0x00000013U 6703 #define LRFDRFE_DTST_SIG_VAR_PHERR_LOWER 0x00000012U 6704 #define LRFDRFE_DTST_SIG_VAR_PHERR_UPPER 0x00000011U 6705 #define LRFDRFE_DTST_SIG_VAR_NC_0 0x00000010U 6706 #define LRFDRFE_DTST_SIG_REF_NC_15 0x0000000FU 6707 #define LRFDRFE_DTST_SIG_REF_NC_14 0x0000000EU 6708 #define LRFDRFE_DTST_SIG_REF_NC_13 0x0000000DU 6709 #define LRFDRFE_DTST_SIG_REF_NC_12 0x0000000CU 6710 #define LRFDRFE_DTST_SIG_REF_NC_11 0x0000000BU 6711 #define LRFDRFE_DTST_SIG_REF_NC_10 0x0000000AU 6712 #define LRFDRFE_DTST_SIG_REF_NC_9 0x00000009U 6713 #define LRFDRFE_DTST_SIG_REF_NC_8 0x00000008U 6714 #define LRFDRFE_DTST_SIG_REF_NC_7 0x00000007U 6715 #define LRFDRFE_DTST_SIG_REF_NC_6 0x00000006U 6716 #define LRFDRFE_DTST_SIG_REF_NC_5 0x00000005U 6717 #define LRFDRFE_DTST_SIG_REF_NC_4 0x00000004U 6718 #define LRFDRFE_DTST_SIG_REF_NC_3 0x00000003U 6719 #define LRFDRFE_DTST_SIG_REF_FERR_MAG 0x00000002U 6720 #define LRFDRFE_DTST_SIG_REF_FSMCAL 0x00000001U 6721 #define LRFDRFE_DTST_SIG_REF_NC_0 0x00000000U 6722 6723 //***************************************************************************** 6724 // 6725 // Register: LRFDRFE_O_DLOEV 6726 // 6727 //***************************************************************************** 6728 // Field: [7] LOCK 6729 // 6730 // Lock 6731 // 6732 // PLLMON1.PHELOCKCNT and PLLMON1.PHELOCKTHR configures the behaviour. 6733 // ENUMs: 6734 // ONE The bit is 1 6735 // ZERO The bit is 0 6736 #define LRFDRFE_DLOEV_LOCK 0x00000080U 6737 #define LRFDRFE_DLOEV_LOCK_M 0x00000080U 6738 #define LRFDRFE_DLOEV_LOCK_S 7U 6739 #define LRFDRFE_DLOEV_LOCK_ONE 0x00000080U 6740 #define LRFDRFE_DLOEV_LOCK_ZERO 0x00000000U 6741 6742 // Field: [6] LOL 6743 // 6744 // Loss of lock 6745 // 6746 // PLLMON0.PHELOLCNT and PLLMON0.PHELOLTHR configures the behaviour. 6747 // ENUMs: 6748 // ONE The bit is 1 6749 // ZERO The bit is 0 6750 #define LRFDRFE_DLOEV_LOL 0x00000040U 6751 #define LRFDRFE_DLOEV_LOL_M 0x00000040U 6752 #define LRFDRFE_DLOEV_LOL_S 6U 6753 #define LRFDRFE_DLOEV_LOL_ONE 0x00000040U 6754 #define LRFDRFE_DLOEV_LOL_ZERO 0x00000000U 6755 6756 // Field: [5] FCABVTHR 6757 // 6758 // Finecode above threshold 6759 // 6760 // PLLMON0.FCTHR sets threshold. 6761 // ENUMs: 6762 // ONE The bit is 1 6763 // ZERO The bit is 0 6764 #define LRFDRFE_DLOEV_FCABVTHR 0x00000020U 6765 #define LRFDRFE_DLOEV_FCABVTHR_M 0x00000020U 6766 #define LRFDRFE_DLOEV_FCABVTHR_S 5U 6767 #define LRFDRFE_DLOEV_FCABVTHR_ONE 0x00000020U 6768 #define LRFDRFE_DLOEV_FCABVTHR_ZERO 0x00000000U 6769 6770 // Field: [4] FCBLWTHR 6771 // 6772 // Finecode below threshold 6773 // 6774 // PLLMON0.FCTHR sets threshold. 6775 // ENUMs: 6776 // ONE The bit is 1 6777 // ZERO The bit is 0 6778 #define LRFDRFE_DLOEV_FCBLWTHR 0x00000010U 6779 #define LRFDRFE_DLOEV_FCBLWTHR_M 0x00000010U 6780 #define LRFDRFE_DLOEV_FCBLWTHR_S 4U 6781 #define LRFDRFE_DLOEV_FCBLWTHR_ONE 0x00000010U 6782 #define LRFDRFE_DLOEV_FCBLWTHR_ZERO 0x00000000U 6783 6784 // Field: [3:0] STATE 6785 // 6786 // DLO FSM state 6787 // 6788 // INTERNAL NOTE: 6789 // See implementation specification for details. 6790 // ENUMs: 6791 // ALLONES All the bits are 1 6792 // ALLZEROS All the bits are 0 6793 #define LRFDRFE_DLOEV_STATE_W 4U 6794 #define LRFDRFE_DLOEV_STATE_M 0x0000000FU 6795 #define LRFDRFE_DLOEV_STATE_S 0U 6796 #define LRFDRFE_DLOEV_STATE_ALLONES 0x0000000FU 6797 #define LRFDRFE_DLOEV_STATE_ALLZEROS 0x00000000U 6798 6799 //***************************************************************************** 6800 // 6801 // Register: LRFDRFE_O_DTSTRD 6802 // 6803 //***************************************************************************** 6804 // Field: [15:0] DATA 6805 // 6806 // Data selected by DTST.SIG when the DTST interface is enabled. 6807 // ENUMs: 6808 // ALLONES All the bits are 1 6809 // ALLZEROS All the bits are 0 6810 #define LRFDRFE_DTSTRD_DATA_W 16U 6811 #define LRFDRFE_DTSTRD_DATA_M 0x0000FFFFU 6812 #define LRFDRFE_DTSTRD_DATA_S 0U 6813 #define LRFDRFE_DTSTRD_DATA_ALLONES 0x0000FFFFU 6814 #define LRFDRFE_DTSTRD_DATA_ALLZEROS 0x00000000U 6815 6816 //***************************************************************************** 6817 // 6818 // Register: LRFDRFE_O_FDCOSPANLSB 6819 // 6820 //***************************************************************************** 6821 // Field: [15:0] VAL 6822 // 6823 // DCO frequency span 6824 // ENUMs: 6825 // ALLONES All the bits are 1 6826 // ALLZEROS All the bits are 0 6827 #define LRFDRFE_FDCOSPANLSB_VAL_W 16U 6828 #define LRFDRFE_FDCOSPANLSB_VAL_M 0x0000FFFFU 6829 #define LRFDRFE_FDCOSPANLSB_VAL_S 0U 6830 #define LRFDRFE_FDCOSPANLSB_VAL_ALLONES 0x0000FFFFU 6831 #define LRFDRFE_FDCOSPANLSB_VAL_ALLZEROS 0x00000000U 6832 6833 //***************************************************************************** 6834 // 6835 // Register: LRFDRFE_O_FDCOSPANMSB 6836 // 6837 //***************************************************************************** 6838 // Field: [2:0] VAL 6839 // 6840 // DCO frequency span 6841 // ENUMs: 6842 // ALLONES All the bits are 1 6843 // ALLZEROS All the bits are 0 6844 #define LRFDRFE_FDCOSPANMSB_VAL_W 3U 6845 #define LRFDRFE_FDCOSPANMSB_VAL_M 0x00000007U 6846 #define LRFDRFE_FDCOSPANMSB_VAL_S 0U 6847 #define LRFDRFE_FDCOSPANMSB_VAL_ALLONES 0x00000007U 6848 #define LRFDRFE_FDCOSPANMSB_VAL_ALLZEROS 0x00000000U 6849 6850 //***************************************************************************** 6851 // 6852 // Register: LRFDRFE_O_TDCCAL 6853 // 6854 //***************************************************************************** 6855 // Field: [15:0] VAL 6856 // 6857 // Value 6858 // 6859 // Sum of inverter delays calculated by HW at the end of the TDC calibration. 6860 // The number of delays summed is controlled by CAL0.TDCAVG and 6861 // DLOCTL0.TDCSTOP. FW uses value to calculate CAL2.KTDCINV. 6862 // ENUMs: 6863 // ALLONES All the bits are 1 6864 // ALLZEROS All the bits are 0 6865 #define LRFDRFE_TDCCAL_VAL_W 16U 6866 #define LRFDRFE_TDCCAL_VAL_M 0x0000FFFFU 6867 #define LRFDRFE_TDCCAL_VAL_S 0U 6868 #define LRFDRFE_TDCCAL_VAL_ALLONES 0x0000FFFFU 6869 #define LRFDRFE_TDCCAL_VAL_ALLZEROS 0x00000000U 6870 6871 //***************************************************************************** 6872 // 6873 // Register: LRFDRFE_O_CALRES 6874 // 6875 //***************************************************************************** 6876 // Field: [9:4] MIDCODE 6877 // 6878 // Calibrated mid code 6879 // ENUMs: 6880 // ALLONES All the bits are 1 6881 // ALLZEROS All the bits are 0 6882 #define LRFDRFE_CALRES_MIDCODE_W 6U 6883 #define LRFDRFE_CALRES_MIDCODE_M 0x000003F0U 6884 #define LRFDRFE_CALRES_MIDCODE_S 4U 6885 #define LRFDRFE_CALRES_MIDCODE_ALLONES 0x000003F0U 6886 #define LRFDRFE_CALRES_MIDCODE_ALLZEROS 0x00000000U 6887 6888 // Field: [3:0] CRSCODE 6889 // 6890 // Calibrated coarse code 6891 // ENUMs: 6892 // ALLONES All the bits are 1 6893 // ALLZEROS All the bits are 0 6894 #define LRFDRFE_CALRES_CRSCODE_W 4U 6895 #define LRFDRFE_CALRES_CRSCODE_M 0x0000000FU 6896 #define LRFDRFE_CALRES_CRSCODE_S 0U 6897 #define LRFDRFE_CALRES_CRSCODE_ALLONES 0x0000000FU 6898 #define LRFDRFE_CALRES_CRSCODE_ALLZEROS 0x00000000U 6899 6900 //***************************************************************************** 6901 // 6902 // Register: LRFDRFE_O_GPI 6903 // 6904 //***************************************************************************** 6905 // Field: [7] GPI7 6906 // 6907 // Control GPI7 6908 // ENUMs: 6909 // ONE The bit is 1 6910 // ZERO The bit is 0 6911 #define LRFDRFE_GPI_GPI7 0x00000080U 6912 #define LRFDRFE_GPI_GPI7_M 0x00000080U 6913 #define LRFDRFE_GPI_GPI7_S 7U 6914 #define LRFDRFE_GPI_GPI7_ONE 0x00000080U 6915 #define LRFDRFE_GPI_GPI7_ZERO 0x00000000U 6916 6917 // Field: [6] GPI6 6918 // 6919 // Control GPI6 6920 // ENUMs: 6921 // ONE The bit is 1 6922 // ZERO The bit is 0 6923 #define LRFDRFE_GPI_GPI6 0x00000040U 6924 #define LRFDRFE_GPI_GPI6_M 0x00000040U 6925 #define LRFDRFE_GPI_GPI6_S 6U 6926 #define LRFDRFE_GPI_GPI6_ONE 0x00000040U 6927 #define LRFDRFE_GPI_GPI6_ZERO 0x00000000U 6928 6929 // Field: [5] GPI5 6930 // 6931 // Control GPI5 6932 // ENUMs: 6933 // ONE The bit is 1 6934 // ZERO The bit is 0 6935 #define LRFDRFE_GPI_GPI5 0x00000020U 6936 #define LRFDRFE_GPI_GPI5_M 0x00000020U 6937 #define LRFDRFE_GPI_GPI5_S 5U 6938 #define LRFDRFE_GPI_GPI5_ONE 0x00000020U 6939 #define LRFDRFE_GPI_GPI5_ZERO 0x00000000U 6940 6941 // Field: [4] GPI4 6942 // 6943 // Control GPI4 6944 // ENUMs: 6945 // ONE The bit is 1 6946 // ZERO The bit is 0 6947 #define LRFDRFE_GPI_GPI4 0x00000010U 6948 #define LRFDRFE_GPI_GPI4_M 0x00000010U 6949 #define LRFDRFE_GPI_GPI4_S 4U 6950 #define LRFDRFE_GPI_GPI4_ONE 0x00000010U 6951 #define LRFDRFE_GPI_GPI4_ZERO 0x00000000U 6952 6953 // Field: [3] GPI3 6954 // 6955 // Control GPI3 6956 // ENUMs: 6957 // ONE The bit is 1 6958 // ZERO The bit is 0 6959 #define LRFDRFE_GPI_GPI3 0x00000008U 6960 #define LRFDRFE_GPI_GPI3_M 0x00000008U 6961 #define LRFDRFE_GPI_GPI3_S 3U 6962 #define LRFDRFE_GPI_GPI3_ONE 0x00000008U 6963 #define LRFDRFE_GPI_GPI3_ZERO 0x00000000U 6964 6965 // Field: [2] GPI2 6966 // 6967 // Control GPI2 6968 // ENUMs: 6969 // ONE The bit is 1 6970 // ZERO The bit is 0 6971 #define LRFDRFE_GPI_GPI2 0x00000004U 6972 #define LRFDRFE_GPI_GPI2_M 0x00000004U 6973 #define LRFDRFE_GPI_GPI2_S 2U 6974 #define LRFDRFE_GPI_GPI2_ONE 0x00000004U 6975 #define LRFDRFE_GPI_GPI2_ZERO 0x00000000U 6976 6977 // Field: [1] GPI1 6978 // 6979 // Control GPI1 6980 // ENUMs: 6981 // ONE The bit is 1 6982 // ZERO The bit is 0 6983 #define LRFDRFE_GPI_GPI1 0x00000002U 6984 #define LRFDRFE_GPI_GPI1_M 0x00000002U 6985 #define LRFDRFE_GPI_GPI1_S 1U 6986 #define LRFDRFE_GPI_GPI1_ONE 0x00000002U 6987 #define LRFDRFE_GPI_GPI1_ZERO 0x00000000U 6988 6989 // Field: [0] GPI0 6990 // 6991 // Control GPI0 6992 // ENUMs: 6993 // ONE The bit is 1 6994 // ZERO The bit is 0 6995 #define LRFDRFE_GPI_GPI0 0x00000001U 6996 #define LRFDRFE_GPI_GPI0_M 0x00000001U 6997 #define LRFDRFE_GPI_GPI0_S 0U 6998 #define LRFDRFE_GPI_GPI0_ONE 0x00000001U 6999 #define LRFDRFE_GPI_GPI0_ZERO 0x00000000U 7000 7001 //***************************************************************************** 7002 // 7003 // Register: LRFDRFE_O_MATHACCELIN 7004 // 7005 //***************************************************************************** 7006 // Field: [15:0] VAL 7007 // 7008 // Input value in linear units 7009 // ENUMs: 7010 // ALLONES All the bits are 1 7011 // ALLZEROS All the bits are 0 7012 #define LRFDRFE_MATHACCELIN_VAL_W 16U 7013 #define LRFDRFE_MATHACCELIN_VAL_M 0x0000FFFFU 7014 #define LRFDRFE_MATHACCELIN_VAL_S 0U 7015 #define LRFDRFE_MATHACCELIN_VAL_ALLONES 0x0000FFFFU 7016 #define LRFDRFE_MATHACCELIN_VAL_ALLZEROS 0x00000000U 7017 7018 //***************************************************************************** 7019 // 7020 // Register: LRFDRFE_O_LIN2LOGOUT 7021 // 7022 //***************************************************************************** 7023 // Field: [6:0] LOGVAL 7024 // 7025 // Logarithmic output value 7026 // 7027 // Logaritmic value of MATHACCELIN.VAL. 7028 // ENUMs: 7029 // ALLONES All the bits are 1 7030 // ALLZEROS All the bits are 0 7031 #define LRFDRFE_LIN2LOGOUT_LOGVAL_W 7U 7032 #define LRFDRFE_LIN2LOGOUT_LOGVAL_M 0x0000007FU 7033 #define LRFDRFE_LIN2LOGOUT_LOGVAL_S 0U 7034 #define LRFDRFE_LIN2LOGOUT_LOGVAL_ALLONES 0x0000007FU 7035 #define LRFDRFE_LIN2LOGOUT_LOGVAL_ALLZEROS 0x00000000U 7036 7037 //***************************************************************************** 7038 // 7039 // Register: LRFDRFE_O_DIVBY3OUT 7040 // 7041 //***************************************************************************** 7042 // Field: [3:0] DIV3 7043 // 7044 // Divider output value 7045 // 7046 // Calculation performed: MATHACCELIN.VAL/3 7047 // 7048 // Supports input values <= 46, higher values are saturated. 7049 // ENUMs: 7050 // ALLONES All the bits are 1 7051 // ALLZEROS All the bits are 0 7052 #define LRFDRFE_DIVBY3OUT_DIV3_W 4U 7053 #define LRFDRFE_DIVBY3OUT_DIV3_M 0x0000000FU 7054 #define LRFDRFE_DIVBY3OUT_DIV3_S 0U 7055 #define LRFDRFE_DIVBY3OUT_DIV3_ALLONES 0x0000000FU 7056 #define LRFDRFE_DIVBY3OUT_DIV3_ALLZEROS 0x00000000U 7057 7058 //***************************************************************************** 7059 // 7060 // Register: LRFDRFE_O_TIMCTL 7061 // 7062 //***************************************************************************** 7063 // Field: [13:8] CPTSRC 7064 // 7065 // Event capture source 7066 // 7067 // Index selects the corresponding event from RFE event bus, EVT0 and EVT1. 7068 // ENUMs: 7069 // ALLONES All the bits are 1 7070 // ALLZEROS All the bits are 0 7071 #define LRFDRFE_TIMCTL_CPTSRC_W 6U 7072 #define LRFDRFE_TIMCTL_CPTSRC_M 0x00003F00U 7073 #define LRFDRFE_TIMCTL_CPTSRC_S 8U 7074 #define LRFDRFE_TIMCTL_CPTSRC_ALLONES 0x00003F00U 7075 #define LRFDRFE_TIMCTL_CPTSRC_ALLZEROS 0x00000000U 7076 7077 // Field: [7] CPTCTL 7078 // 7079 // Counter capture control 7080 // 7081 // Upon selected capture event, the counter value will be captured into 7082 // TIMCAPT. 7083 // ENUMs: 7084 // EN Enable counter capture mode 7085 // DIS Disable counter capture mode 7086 #define LRFDRFE_TIMCTL_CPTCTL 0x00000080U 7087 #define LRFDRFE_TIMCTL_CPTCTL_M 0x00000080U 7088 #define LRFDRFE_TIMCTL_CPTCTL_S 7U 7089 #define LRFDRFE_TIMCTL_CPTCTL_EN 0x00000080U 7090 #define LRFDRFE_TIMCTL_CPTCTL_DIS 0x00000000U 7091 7092 // Field: [6:5] CNTRSRC 7093 // 7094 // Counter event source 7095 // ENUMs: 7096 // FREF Count FREF ticks 7097 // MAGN1 Use magnitude estimator 1 data enable 7098 // MAGN0 Use magnitude estimator 0 data enable 7099 // CLK Use clock 7100 #define LRFDRFE_TIMCTL_CNTRSRC_W 2U 7101 #define LRFDRFE_TIMCTL_CNTRSRC_M 0x00000060U 7102 #define LRFDRFE_TIMCTL_CNTRSRC_S 5U 7103 #define LRFDRFE_TIMCTL_CNTRSRC_FREF 0x00000060U 7104 #define LRFDRFE_TIMCTL_CNTRSRC_MAGN1 0x00000040U 7105 #define LRFDRFE_TIMCTL_CNTRSRC_MAGN0 0x00000020U 7106 #define LRFDRFE_TIMCTL_CNTRSRC_CLK 0x00000000U 7107 7108 // Field: [4] CNTRCLR 7109 // 7110 // Counter clear value in TIMCNT. 7111 // ENUMs: 7112 // ONE Clear counter value 7113 // ZERO No action 7114 #define LRFDRFE_TIMCTL_CNTRCLR 0x00000010U 7115 #define LRFDRFE_TIMCTL_CNTRCLR_M 0x00000010U 7116 #define LRFDRFE_TIMCTL_CNTRCLR_S 4U 7117 #define LRFDRFE_TIMCTL_CNTRCLR_ONE 0x00000010U 7118 #define LRFDRFE_TIMCTL_CNTRCLR_ZERO 0x00000000U 7119 7120 // Field: [3] CNTRCTL 7121 // 7122 // 16-bit counter control 7123 // 7124 // The counter will continue from its current value. 7125 // ENUMs: 7126 // EN Enable counter 7127 // DIS Disable counter 7128 #define LRFDRFE_TIMCTL_CNTRCTL 0x00000008U 7129 #define LRFDRFE_TIMCTL_CNTRCTL_M 0x00000008U 7130 #define LRFDRFE_TIMCTL_CNTRCTL_S 3U 7131 #define LRFDRFE_TIMCTL_CNTRCTL_EN 0x00000008U 7132 #define LRFDRFE_TIMCTL_CNTRCTL_DIS 0x00000000U 7133 7134 // Field: [2:1] TIMSRC 7135 // 7136 // Timer tick source 7137 // ENUMs: 7138 // FREF Count FREF ticks 7139 // MAGN1 Use magnitude estimator 1 data enable 7140 // MAGN0 Use magnitude estimator 0 data enable 7141 // CLK Use clock 7142 #define LRFDRFE_TIMCTL_TIMSRC_W 2U 7143 #define LRFDRFE_TIMCTL_TIMSRC_M 0x00000006U 7144 #define LRFDRFE_TIMCTL_TIMSRC_S 1U 7145 #define LRFDRFE_TIMCTL_TIMSRC_FREF 0x00000006U 7146 #define LRFDRFE_TIMCTL_TIMSRC_MAGN1 0x00000004U 7147 #define LRFDRFE_TIMCTL_TIMSRC_MAGN0 0x00000002U 7148 #define LRFDRFE_TIMCTL_TIMSRC_CLK 0x00000000U 7149 7150 // Field: [0] TIMCTL 7151 // 7152 // 16-bit timer control 7153 // 7154 // It will generate a timer interrupt after TIMPER timer ticks. Note that the 7155 // internal timer value is not readable from the RFE. If this is needed the 7156 // counter should be used instead of the timer. 7157 // ENUMs: 7158 // EN Enable timer 7159 // DIS Disable timer and clear internal timer value 7160 #define LRFDRFE_TIMCTL_TIMCTL 0x00000001U 7161 #define LRFDRFE_TIMCTL_TIMCTL_M 0x00000001U 7162 #define LRFDRFE_TIMCTL_TIMCTL_S 0U 7163 #define LRFDRFE_TIMCTL_TIMCTL_EN 0x00000001U 7164 #define LRFDRFE_TIMCTL_TIMCTL_DIS 0x00000000U 7165 7166 //***************************************************************************** 7167 // 7168 // Register: LRFDRFE_O_TIMINC 7169 // 7170 //***************************************************************************** 7171 // Field: [15:0] VAL 7172 // 7173 // Programmable increment for the counter 7174 // ENUMs: 7175 // ALLONES All the bits are 1 7176 // ALLZEROS All the bits are 0 7177 #define LRFDRFE_TIMINC_VAL_W 16U 7178 #define LRFDRFE_TIMINC_VAL_M 0x0000FFFFU 7179 #define LRFDRFE_TIMINC_VAL_S 0U 7180 #define LRFDRFE_TIMINC_VAL_ALLONES 0x0000FFFFU 7181 #define LRFDRFE_TIMINC_VAL_ALLZEROS 0x00000000U 7182 7183 //***************************************************************************** 7184 // 7185 // Register: LRFDRFE_O_TIMPER 7186 // 7187 //***************************************************************************** 7188 // Field: [15:0] VAL 7189 // 7190 // Configurable 16 bit period that can be used for either the timer or the 7191 // counter. In timer context, when timer value reach the timer period (i.e. it 7192 // expires) a TIMER_IRQ event will occur, and the timer will restart from zero 7193 // (until the timer is manually disabled). In counter context, a COUNTER_IRQ 7194 // event will occur when the counter is equal to or higher than the period 7195 // value. 7196 // ENUMs: 7197 // ALLONES All the bits are 1 7198 // ALLZEROS All the bits are 0 7199 #define LRFDRFE_TIMPER_VAL_W 16U 7200 #define LRFDRFE_TIMPER_VAL_M 0x0000FFFFU 7201 #define LRFDRFE_TIMPER_VAL_S 0U 7202 #define LRFDRFE_TIMPER_VAL_ALLONES 0x0000FFFFU 7203 #define LRFDRFE_TIMPER_VAL_ALLZEROS 0x00000000U 7204 7205 //***************************************************************************** 7206 // 7207 // Register: LRFDRFE_O_TIMCNT 7208 // 7209 //***************************************************************************** 7210 // Field: [15:0] VAL 7211 // 7212 // 16 bit value of counter 7213 // ENUMs: 7214 // ALLONES All the bits are 1 7215 // ALLZEROS All the bits are 0 7216 #define LRFDRFE_TIMCNT_VAL_W 16U 7217 #define LRFDRFE_TIMCNT_VAL_M 0x0000FFFFU 7218 #define LRFDRFE_TIMCNT_VAL_S 0U 7219 #define LRFDRFE_TIMCNT_VAL_ALLONES 0x0000FFFFU 7220 #define LRFDRFE_TIMCNT_VAL_ALLZEROS 0x00000000U 7221 7222 //***************************************************************************** 7223 // 7224 // Register: LRFDRFE_O_TIMCAPT 7225 // 7226 //***************************************************************************** 7227 // Field: [15:0] VALUE 7228 // 7229 // Captured value of counter 7230 // ENUMs: 7231 // ALLONES All the bits are 1 7232 // ALLZEROS All the bits are 0 7233 #define LRFDRFE_TIMCAPT_VALUE_W 16U 7234 #define LRFDRFE_TIMCAPT_VALUE_M 0x0000FFFFU 7235 #define LRFDRFE_TIMCAPT_VALUE_S 0U 7236 #define LRFDRFE_TIMCAPT_VALUE_ALLONES 0x0000FFFFU 7237 #define LRFDRFE_TIMCAPT_VALUE_ALLZEROS 0x00000000U 7238 7239 //***************************************************************************** 7240 // 7241 // Register: LRFDRFE_O_TRCCTRL 7242 // 7243 //***************************************************************************** 7244 // Field: [0] SEND 7245 // 7246 // Sends a command to the tracer 7247 // ENUMs: 7248 // ONE The bit is 1 7249 // ZERO The bit is 0 7250 #define LRFDRFE_TRCCTRL_SEND 0x00000001U 7251 #define LRFDRFE_TRCCTRL_SEND_M 0x00000001U 7252 #define LRFDRFE_TRCCTRL_SEND_S 0U 7253 #define LRFDRFE_TRCCTRL_SEND_ONE 0x00000001U 7254 #define LRFDRFE_TRCCTRL_SEND_ZERO 0x00000000U 7255 7256 //***************************************************************************** 7257 // 7258 // Register: LRFDRFE_O_TRCSTAT 7259 // 7260 //***************************************************************************** 7261 // Field: [0] BUSY 7262 // 7263 // Tracer busy status 7264 // ENUMs: 7265 // ONE The bit is 1 7266 // ZERO The bit is 0 7267 #define LRFDRFE_TRCSTAT_BUSY 0x00000001U 7268 #define LRFDRFE_TRCSTAT_BUSY_M 0x00000001U 7269 #define LRFDRFE_TRCSTAT_BUSY_S 0U 7270 #define LRFDRFE_TRCSTAT_BUSY_ONE 0x00000001U 7271 #define LRFDRFE_TRCSTAT_BUSY_ZERO 0x00000000U 7272 7273 //***************************************************************************** 7274 // 7275 // Register: LRFDRFE_O_TRCCMD 7276 // 7277 //***************************************************************************** 7278 // Field: [9:8] PARCNT 7279 // 7280 // Number of parameters 7281 // ENUMs: 7282 // ALLONES All the bits are 1 7283 // ALLZEROS All the bits are 0 7284 #define LRFDRFE_TRCCMD_PARCNT_W 2U 7285 #define LRFDRFE_TRCCMD_PARCNT_M 0x00000300U 7286 #define LRFDRFE_TRCCMD_PARCNT_S 8U 7287 #define LRFDRFE_TRCCMD_PARCNT_ALLONES 0x00000300U 7288 #define LRFDRFE_TRCCMD_PARCNT_ALLZEROS 0x00000000U 7289 7290 // Field: [7:0] PKTHDR 7291 // 7292 // Packet header 7293 // ENUMs: 7294 // ALLONES All the bits are 1 7295 // ALLZEROS All the bits are 0 7296 #define LRFDRFE_TRCCMD_PKTHDR_W 8U 7297 #define LRFDRFE_TRCCMD_PKTHDR_M 0x000000FFU 7298 #define LRFDRFE_TRCCMD_PKTHDR_S 0U 7299 #define LRFDRFE_TRCCMD_PKTHDR_ALLONES 0x000000FFU 7300 #define LRFDRFE_TRCCMD_PKTHDR_ALLZEROS 0x00000000U 7301 7302 //***************************************************************************** 7303 // 7304 // Register: LRFDRFE_O_TRCPAR0 7305 // 7306 //***************************************************************************** 7307 // Field: [15:0] VAL 7308 // 7309 // Parameter 0 7310 // ENUMs: 7311 // ALLONES All the bits are 1 7312 // ALLZEROS All the bits are 0 7313 #define LRFDRFE_TRCPAR0_VAL_W 16U 7314 #define LRFDRFE_TRCPAR0_VAL_M 0x0000FFFFU 7315 #define LRFDRFE_TRCPAR0_VAL_S 0U 7316 #define LRFDRFE_TRCPAR0_VAL_ALLONES 0x0000FFFFU 7317 #define LRFDRFE_TRCPAR0_VAL_ALLZEROS 0x00000000U 7318 7319 //***************************************************************************** 7320 // 7321 // Register: LRFDRFE_O_TRCPAR1 7322 // 7323 //***************************************************************************** 7324 // Field: [15:0] VAL 7325 // 7326 // Parameter 1 7327 // ENUMs: 7328 // ALLONES All the bits are 1 7329 // ALLZEROS All the bits are 0 7330 #define LRFDRFE_TRCPAR1_VAL_W 16U 7331 #define LRFDRFE_TRCPAR1_VAL_M 0x0000FFFFU 7332 #define LRFDRFE_TRCPAR1_VAL_S 0U 7333 #define LRFDRFE_TRCPAR1_VAL_ALLONES 0x0000FFFFU 7334 #define LRFDRFE_TRCPAR1_VAL_ALLZEROS 0x00000000U 7335 7336 //***************************************************************************** 7337 // 7338 // Register: LRFDRFE_O_GPOCTL 7339 // 7340 //***************************************************************************** 7341 // Field: [15] SEL7 7342 // 7343 // Select GPO7 source 7344 // ENUMs: 7345 // HW The pin is controlled by its HW source 7346 // SW The pin is controlled by GPOCTRL.GPO7 7347 #define LRFDRFE_GPOCTL_SEL7 0x00008000U 7348 #define LRFDRFE_GPOCTL_SEL7_M 0x00008000U 7349 #define LRFDRFE_GPOCTL_SEL7_S 15U 7350 #define LRFDRFE_GPOCTL_SEL7_HW 0x00008000U 7351 #define LRFDRFE_GPOCTL_SEL7_SW 0x00000000U 7352 7353 // Field: [14] SEL6 7354 // 7355 // Select GPO6 source 7356 // ENUMs: 7357 // HW The pin is controlled by its HW source 7358 // SW The pin is controlled by GPOCTRL.GPO6 7359 #define LRFDRFE_GPOCTL_SEL6 0x00004000U 7360 #define LRFDRFE_GPOCTL_SEL6_M 0x00004000U 7361 #define LRFDRFE_GPOCTL_SEL6_S 14U 7362 #define LRFDRFE_GPOCTL_SEL6_HW 0x00004000U 7363 #define LRFDRFE_GPOCTL_SEL6_SW 0x00000000U 7364 7365 // Field: [13] SEL5 7366 // 7367 // Select GPO5 source 7368 // ENUMs: 7369 // HW The pin is controlled by its HW source 7370 // SW The pin is controlled by GPOCTRL.GPO5 7371 #define LRFDRFE_GPOCTL_SEL5 0x00002000U 7372 #define LRFDRFE_GPOCTL_SEL5_M 0x00002000U 7373 #define LRFDRFE_GPOCTL_SEL5_S 13U 7374 #define LRFDRFE_GPOCTL_SEL5_HW 0x00002000U 7375 #define LRFDRFE_GPOCTL_SEL5_SW 0x00000000U 7376 7377 // Field: [12] SEL4 7378 // 7379 // Select GPO4 source 7380 // ENUMs: 7381 // HW The pin is controlled by its HW source 7382 // SW The pin is controlled by GPOCTRL.GPO4 7383 #define LRFDRFE_GPOCTL_SEL4 0x00001000U 7384 #define LRFDRFE_GPOCTL_SEL4_M 0x00001000U 7385 #define LRFDRFE_GPOCTL_SEL4_S 12U 7386 #define LRFDRFE_GPOCTL_SEL4_HW 0x00001000U 7387 #define LRFDRFE_GPOCTL_SEL4_SW 0x00000000U 7388 7389 // Field: [11] SEL3 7390 // 7391 // Select GPO3 source 7392 // ENUMs: 7393 // HW The pin is controlled by its HW source 7394 // SW The pin is controlled by GPOCTRL.GPO3 7395 #define LRFDRFE_GPOCTL_SEL3 0x00000800U 7396 #define LRFDRFE_GPOCTL_SEL3_M 0x00000800U 7397 #define LRFDRFE_GPOCTL_SEL3_S 11U 7398 #define LRFDRFE_GPOCTL_SEL3_HW 0x00000800U 7399 #define LRFDRFE_GPOCTL_SEL3_SW 0x00000000U 7400 7401 // Field: [10] SEL2 7402 // 7403 // Select GPO2 source 7404 // ENUMs: 7405 // HW The pin is controlled by its HW source 7406 // SW The pin is controlled by GPOCTRL.GPO2 7407 #define LRFDRFE_GPOCTL_SEL2 0x00000400U 7408 #define LRFDRFE_GPOCTL_SEL2_M 0x00000400U 7409 #define LRFDRFE_GPOCTL_SEL2_S 10U 7410 #define LRFDRFE_GPOCTL_SEL2_HW 0x00000400U 7411 #define LRFDRFE_GPOCTL_SEL2_SW 0x00000000U 7412 7413 // Field: [9] SEL1 7414 // 7415 // Select GPO1 source 7416 // ENUMs: 7417 // HW The pin is controlled by its HW source 7418 // SW The pin is controlled by GPOCTRL.GPO1 7419 #define LRFDRFE_GPOCTL_SEL1 0x00000200U 7420 #define LRFDRFE_GPOCTL_SEL1_M 0x00000200U 7421 #define LRFDRFE_GPOCTL_SEL1_S 9U 7422 #define LRFDRFE_GPOCTL_SEL1_HW 0x00000200U 7423 #define LRFDRFE_GPOCTL_SEL1_SW 0x00000000U 7424 7425 // Field: [8] SEL0 7426 // 7427 // Select GPO0 source 7428 // ENUMs: 7429 // HW The pin is controlled by its HW source 7430 // SW The pin is controlled by GPOCTRL.GPO0 7431 #define LRFDRFE_GPOCTL_SEL0 0x00000100U 7432 #define LRFDRFE_GPOCTL_SEL0_M 0x00000100U 7433 #define LRFDRFE_GPOCTL_SEL0_S 8U 7434 #define LRFDRFE_GPOCTL_SEL0_HW 0x00000100U 7435 #define LRFDRFE_GPOCTL_SEL0_SW 0x00000000U 7436 7437 // Field: [7] GPO7 7438 // 7439 // Control GPO7 7440 // ENUMs: 7441 // ONE The bit is 1 7442 // ZERO The bit is 0 7443 #define LRFDRFE_GPOCTL_GPO7 0x00000080U 7444 #define LRFDRFE_GPOCTL_GPO7_M 0x00000080U 7445 #define LRFDRFE_GPOCTL_GPO7_S 7U 7446 #define LRFDRFE_GPOCTL_GPO7_ONE 0x00000080U 7447 #define LRFDRFE_GPOCTL_GPO7_ZERO 0x00000000U 7448 7449 // Field: [6] GPO6 7450 // 7451 // Control GPO6 7452 // ENUMs: 7453 // ONE The bit is 1 7454 // ZERO The bit is 0 7455 #define LRFDRFE_GPOCTL_GPO6 0x00000040U 7456 #define LRFDRFE_GPOCTL_GPO6_M 0x00000040U 7457 #define LRFDRFE_GPOCTL_GPO6_S 6U 7458 #define LRFDRFE_GPOCTL_GPO6_ONE 0x00000040U 7459 #define LRFDRFE_GPOCTL_GPO6_ZERO 0x00000000U 7460 7461 // Field: [5] GPO5 7462 // 7463 // Control GPO5 7464 // ENUMs: 7465 // ONE The bit is 1 7466 // ZERO The bit is 0 7467 #define LRFDRFE_GPOCTL_GPO5 0x00000020U 7468 #define LRFDRFE_GPOCTL_GPO5_M 0x00000020U 7469 #define LRFDRFE_GPOCTL_GPO5_S 5U 7470 #define LRFDRFE_GPOCTL_GPO5_ONE 0x00000020U 7471 #define LRFDRFE_GPOCTL_GPO5_ZERO 0x00000000U 7472 7473 // Field: [4] GPO4 7474 // 7475 // Control GPO4 7476 // ENUMs: 7477 // ONE The bit is 1 7478 // ZERO The bit is 0 7479 #define LRFDRFE_GPOCTL_GPO4 0x00000010U 7480 #define LRFDRFE_GPOCTL_GPO4_M 0x00000010U 7481 #define LRFDRFE_GPOCTL_GPO4_S 4U 7482 #define LRFDRFE_GPOCTL_GPO4_ONE 0x00000010U 7483 #define LRFDRFE_GPOCTL_GPO4_ZERO 0x00000000U 7484 7485 // Field: [3] GPO3 7486 // 7487 // Control GPO3 7488 // ENUMs: 7489 // ONE The bit is 1 7490 // ZERO The bit is 0 7491 #define LRFDRFE_GPOCTL_GPO3 0x00000008U 7492 #define LRFDRFE_GPOCTL_GPO3_M 0x00000008U 7493 #define LRFDRFE_GPOCTL_GPO3_S 3U 7494 #define LRFDRFE_GPOCTL_GPO3_ONE 0x00000008U 7495 #define LRFDRFE_GPOCTL_GPO3_ZERO 0x00000000U 7496 7497 // Field: [2] GPO2 7498 // 7499 // Control GPO2 7500 // ENUMs: 7501 // ONE The bit is 1 7502 // ZERO The bit is 0 7503 #define LRFDRFE_GPOCTL_GPO2 0x00000004U 7504 #define LRFDRFE_GPOCTL_GPO2_M 0x00000004U 7505 #define LRFDRFE_GPOCTL_GPO2_S 2U 7506 #define LRFDRFE_GPOCTL_GPO2_ONE 0x00000004U 7507 #define LRFDRFE_GPOCTL_GPO2_ZERO 0x00000000U 7508 7509 // Field: [1] GPO1 7510 // 7511 // Control GPO1 7512 // ENUMs: 7513 // ONE The bit is 1 7514 // ZERO The bit is 0 7515 #define LRFDRFE_GPOCTL_GPO1 0x00000002U 7516 #define LRFDRFE_GPOCTL_GPO1_M 0x00000002U 7517 #define LRFDRFE_GPOCTL_GPO1_S 1U 7518 #define LRFDRFE_GPOCTL_GPO1_ONE 0x00000002U 7519 #define LRFDRFE_GPOCTL_GPO1_ZERO 0x00000000U 7520 7521 // Field: [0] GPO0 7522 // 7523 // Control GPO0 7524 // ENUMs: 7525 // ONE The bit is 1 7526 // ZERO The bit is 0 7527 #define LRFDRFE_GPOCTL_GPO0 0x00000001U 7528 #define LRFDRFE_GPOCTL_GPO0_M 0x00000001U 7529 #define LRFDRFE_GPOCTL_GPO0_S 0U 7530 #define LRFDRFE_GPOCTL_GPO0_ONE 0x00000001U 7531 #define LRFDRFE_GPOCTL_GPO0_ZERO 0x00000000U 7532 7533 //***************************************************************************** 7534 // 7535 // Register: LRFDRFE_O_ANAISOCTL 7536 // 7537 //***************************************************************************** 7538 // Field: [4] ADCDIGRSTN 7539 // 7540 // Active low reset of ADC clock domain within Modem 7541 // ENUMs: 7542 // ACTIVE Don't reset 7543 // RESET Reset 7544 #define LRFDRFE_ANAISOCTL_ADCDIGRSTN 0x00000010U 7545 #define LRFDRFE_ANAISOCTL_ADCDIGRSTN_M 0x00000010U 7546 #define LRFDRFE_ANAISOCTL_ADCDIGRSTN_S 4U 7547 #define LRFDRFE_ANAISOCTL_ADCDIGRSTN_ACTIVE 0x00000010U 7548 #define LRFDRFE_ANAISOCTL_ADCDIGRSTN_RESET 0x00000000U 7549 7550 // Field: [3] IFADC2SVTISO 7551 // 7552 // Isolation between IFADC and Modem 7553 // ENUMs: 7554 // ISOLATE Isolate 7555 // CONNECT Don't isolate 7556 #define LRFDRFE_ANAISOCTL_IFADC2SVTISO 0x00000008U 7557 #define LRFDRFE_ANAISOCTL_IFADC2SVTISO_M 0x00000008U 7558 #define LRFDRFE_ANAISOCTL_IFADC2SVTISO_S 3U 7559 #define LRFDRFE_ANAISOCTL_IFADC2SVTISO_ISOLATE 0x00000008U 7560 #define LRFDRFE_ANAISOCTL_IFADC2SVTISO_CONNECT 0x00000000U 7561 7562 // Field: [2] DIV2IFADCISO 7563 // 7564 // Isolation between DIVBUF and IFADC 7565 // ENUMs: 7566 // ISOLATE Isolate 7567 // CONNECT Don't isolate 7568 #define LRFDRFE_ANAISOCTL_DIV2IFADCISO 0x00000004U 7569 #define LRFDRFE_ANAISOCTL_DIV2IFADCISO_M 0x00000004U 7570 #define LRFDRFE_ANAISOCTL_DIV2IFADCISO_S 2U 7571 #define LRFDRFE_ANAISOCTL_DIV2IFADCISO_ISOLATE 0x00000004U 7572 #define LRFDRFE_ANAISOCTL_DIV2IFADCISO_CONNECT 0x00000000U 7573 7574 // Field: [1] MTDC2SVTISO 7575 // 7576 // Isolation between MTDC and Modem 7577 // ENUMs: 7578 // ISOLATE Isolate 7579 // CONNECT Don't isolate 7580 #define LRFDRFE_ANAISOCTL_MTDC2SVTISO 0x00000002U 7581 #define LRFDRFE_ANAISOCTL_MTDC2SVTISO_M 0x00000002U 7582 #define LRFDRFE_ANAISOCTL_MTDC2SVTISO_S 1U 7583 #define LRFDRFE_ANAISOCTL_MTDC2SVTISO_ISOLATE 0x00000002U 7584 #define LRFDRFE_ANAISOCTL_MTDC2SVTISO_CONNECT 0x00000000U 7585 7586 // Field: [0] DIV2MTDCISO 7587 // 7588 // Isolation between DIVBUF and MTDC 7589 // ENUMs: 7590 // ISOLATE Isolate 7591 // CONNECT Don't isolate 7592 #define LRFDRFE_ANAISOCTL_DIV2MTDCISO 0x00000001U 7593 #define LRFDRFE_ANAISOCTL_DIV2MTDCISO_M 0x00000001U 7594 #define LRFDRFE_ANAISOCTL_DIV2MTDCISO_S 0U 7595 #define LRFDRFE_ANAISOCTL_DIV2MTDCISO_ISOLATE 0x00000001U 7596 #define LRFDRFE_ANAISOCTL_DIV2MTDCISO_CONNECT 0x00000000U 7597 7598 //***************************************************************************** 7599 // 7600 // Register: LRFDRFE_O_DIVCTL 7601 // 7602 //***************************************************************************** 7603 // Field: [15] DIV2PH180 7604 // 7605 // DIV2 PH180 path control 7606 // 7607 // Enable DIV2 PH180 path 7608 // INTERNAL NOTE: 7609 // renamed from EN_DIV2_PH180 7610 // ENUMs: 7611 // EN Enable path 7612 // DIS Disable path 7613 #define LRFDRFE_DIVCTL_DIV2PH180 0x00008000U 7614 #define LRFDRFE_DIVCTL_DIV2PH180_M 0x00008000U 7615 #define LRFDRFE_DIVCTL_DIV2PH180_S 15U 7616 #define LRFDRFE_DIVCTL_DIV2PH180_EN 0x00008000U 7617 #define LRFDRFE_DIVCTL_DIV2PH180_DIS 0x00000000U 7618 7619 // Field: [14] DIV2PH0 7620 // 7621 // DIV2 PH0 path control 7622 // 7623 // Enable DIV2 PH0 path 7624 // INTERNAL NOTE: 7625 // renamed from EN_DIV2_PH0 7626 // ENUMs: 7627 // EN Enable path 7628 // DIS Disable path 7629 #define LRFDRFE_DIVCTL_DIV2PH0 0x00004000U 7630 #define LRFDRFE_DIVCTL_DIV2PH0_M 0x00004000U 7631 #define LRFDRFE_DIVCTL_DIV2PH0_S 14U 7632 #define LRFDRFE_DIVCTL_DIV2PH0_EN 0x00004000U 7633 #define LRFDRFE_DIVCTL_DIV2PH0_DIS 0x00000000U 7634 7635 // Field: [13] DIV2PH270 7636 // 7637 // DIV2 PH270 path control 7638 // 7639 // Enable DIV2 PH270 path 7640 // 7641 // INTERNAL NOTE: 7642 // renamed from EN_DIV2_PH270 7643 // ENUMs: 7644 // EN Enable path 7645 // DIS Disable path 7646 #define LRFDRFE_DIVCTL_DIV2PH270 0x00002000U 7647 #define LRFDRFE_DIVCTL_DIV2PH270_M 0x00002000U 7648 #define LRFDRFE_DIVCTL_DIV2PH270_S 13U 7649 #define LRFDRFE_DIVCTL_DIV2PH270_EN 0x00002000U 7650 #define LRFDRFE_DIVCTL_DIV2PH270_DIS 0x00000000U 7651 7652 // Field: [12] DIV2PH90 7653 // 7654 // DIV2 PH90 path control 7655 // 7656 // Enable DIV2 PH90 path 7657 // INTERNAL NOTE: 7658 // renamed from EN_DIV2_PH90 7659 // ENUMs: 7660 // EN Enable path 7661 // DIS Disable path 7662 #define LRFDRFE_DIVCTL_DIV2PH90 0x00001000U 7663 #define LRFDRFE_DIVCTL_DIV2PH90_M 0x00001000U 7664 #define LRFDRFE_DIVCTL_DIV2PH90_S 12U 7665 #define LRFDRFE_DIVCTL_DIV2PH90_EN 0x00001000U 7666 #define LRFDRFE_DIVCTL_DIV2PH90_DIS 0x00000000U 7667 7668 // Field: [11] SPARE11 7669 // 7670 // Reserved 7671 // ENUMs: 7672 // ONE Bit is one 7673 // ZERO Bit is 0 7674 #define LRFDRFE_DIVCTL_SPARE11 0x00000800U 7675 #define LRFDRFE_DIVCTL_SPARE11_M 0x00000800U 7676 #define LRFDRFE_DIVCTL_SPARE11_S 11U 7677 #define LRFDRFE_DIVCTL_SPARE11_ONE 0x00000800U 7678 #define LRFDRFE_DIVCTL_SPARE11_ZERO 0x00000000U 7679 7680 // Field: [10] S1G20DBMMUX 7681 // 7682 // Not connected 7683 // ENUMs: 7684 // DISABLE Disable mux 7685 // ENABLEN Enable mux 7686 #define LRFDRFE_DIVCTL_S1G20DBMMUX 0x00000400U 7687 #define LRFDRFE_DIVCTL_S1G20DBMMUX_M 0x00000400U 7688 #define LRFDRFE_DIVCTL_S1G20DBMMUX_S 10U 7689 #define LRFDRFE_DIVCTL_S1G20DBMMUX_DISABLE 0x00000400U 7690 #define LRFDRFE_DIVCTL_S1G20DBMMUX_ENABLEN 0x00000000U 7691 7692 // Field: [9] ADCDIV 7693 // 7694 // ADC divider control 7695 // 7696 // Field enables divider that generates IFADC clock. 7697 // 7698 // INTERNAL NOTE: 7699 // Renamed from EN_ADC 7700 // ENUMs: 7701 // EN Enable divider 7702 // DIS Disable divider 7703 #define LRFDRFE_DIVCTL_ADCDIV 0x00000200U 7704 #define LRFDRFE_DIVCTL_ADCDIV_M 0x00000200U 7705 #define LRFDRFE_DIVCTL_ADCDIV_S 9U 7706 #define LRFDRFE_DIVCTL_ADCDIV_EN 0x00000200U 7707 #define LRFDRFE_DIVCTL_ADCDIV_DIS 0x00000000U 7708 7709 // Field: [8] ENSYNTH 7710 // 7711 // Enables CKVD clock to MTDC 7712 // ENUMs: 7713 // EN Clock is enabled 7714 // DIS Clock is disabled 7715 #define LRFDRFE_DIVCTL_ENSYNTH 0x00000100U 7716 #define LRFDRFE_DIVCTL_ENSYNTH_M 0x00000100U 7717 #define LRFDRFE_DIVCTL_ENSYNTH_S 8U 7718 #define LRFDRFE_DIVCTL_ENSYNTH_EN 0x00000100U 7719 #define LRFDRFE_DIVCTL_ENSYNTH_DIS 0x00000000U 7720 7721 // Field: [7] TXPH18020DBMDIV 7722 // 7723 // Not connected 7724 // ENUMs: 7725 // EN Enable divider 7726 // DIS Disable divider 7727 #define LRFDRFE_DIVCTL_TXPH18020DBMDIV 0x00000080U 7728 #define LRFDRFE_DIVCTL_TXPH18020DBMDIV_M 0x00000080U 7729 #define LRFDRFE_DIVCTL_TXPH18020DBMDIV_S 7U 7730 #define LRFDRFE_DIVCTL_TXPH18020DBMDIV_EN 0x00000080U 7731 #define LRFDRFE_DIVCTL_TXPH18020DBMDIV_DIS 0x00000000U 7732 7733 // Field: [6] TXPH020DBMDIV 7734 // 7735 // Not connected 7736 // ENUMs: 7737 // EN Enable divider 7738 // DIS Disable divider 7739 #define LRFDRFE_DIVCTL_TXPH020DBMDIV 0x00000040U 7740 #define LRFDRFE_DIVCTL_TXPH020DBMDIV_M 0x00000040U 7741 #define LRFDRFE_DIVCTL_TXPH020DBMDIV_S 6U 7742 #define LRFDRFE_DIVCTL_TXPH020DBMDIV_EN 0x00000040U 7743 #define LRFDRFE_DIVCTL_TXPH020DBMDIV_DIS 0x00000000U 7744 7745 // Field: [5] TXPH180DIV 7746 // 7747 // TX 180-phase divider control 7748 // 7749 // Field enables divider that generates inverted TX RF signal to PA. 7750 // 7751 // INTERNAL NOTE: 7752 // renamed from EN_TX_PH180, there is no such thing as a TX clock 7753 // ENUMs: 7754 // EN Enable divider 7755 // DIS Disable divider 7756 #define LRFDRFE_DIVCTL_TXPH180DIV 0x00000020U 7757 #define LRFDRFE_DIVCTL_TXPH180DIV_M 0x00000020U 7758 #define LRFDRFE_DIVCTL_TXPH180DIV_S 5U 7759 #define LRFDRFE_DIVCTL_TXPH180DIV_EN 0x00000020U 7760 #define LRFDRFE_DIVCTL_TXPH180DIV_DIS 0x00000000U 7761 7762 // Field: [4] TXPH0DIV 7763 // 7764 // TX 0-phase divider control 7765 // 7766 // Field enables divider that generates TX RF signal to PA. 7767 // 7768 // INTERNAL NOTE: 7769 // renamed from EN_TX_PH0, there is no such thing as a TX clock 7770 // ENUMs: 7771 // EN Enable divider 7772 // DIS Disable divider 7773 #define LRFDRFE_DIVCTL_TXPH0DIV 0x00000010U 7774 #define LRFDRFE_DIVCTL_TXPH0DIV_M 0x00000010U 7775 #define LRFDRFE_DIVCTL_TXPH0DIV_S 4U 7776 #define LRFDRFE_DIVCTL_TXPH0DIV_EN 0x00000010U 7777 #define LRFDRFE_DIVCTL_TXPH0DIV_DIS 0x00000000U 7778 7779 // Field: [3] RXPH90DIV 7780 // 7781 // RX quadrature-phase LO divider control 7782 // 7783 // Field enables quadrature-phase RX LO divider. 7784 // 7785 // INTERNAL NOTE: 7786 // renamed form EN_RX_Q, Oddgeir mentioned that original text was wrong wrt 7787 // phase. 7788 // ENUMs: 7789 // EN Enable divider 7790 // DIS Disable divider 7791 #define LRFDRFE_DIVCTL_RXPH90DIV 0x00000008U 7792 #define LRFDRFE_DIVCTL_RXPH90DIV_M 0x00000008U 7793 #define LRFDRFE_DIVCTL_RXPH90DIV_S 3U 7794 #define LRFDRFE_DIVCTL_RXPH90DIV_EN 0x00000008U 7795 #define LRFDRFE_DIVCTL_RXPH90DIV_DIS 0x00000000U 7796 7797 // Field: [2] RXPH0DIV 7798 // 7799 // RX in-phase LO divider control 7800 // 7801 // Field enables in-phase RX LO divider. 7802 // 7803 // INTERNAL NOTE: 7804 // renamed form EN_RX_I, Oddgeir mentioned that original text was wrong wrt 7805 // phase. 7806 // ENUMs: 7807 // EN Enable divider 7808 // DIS Disable divider 7809 #define LRFDRFE_DIVCTL_RXPH0DIV 0x00000004U 7810 #define LRFDRFE_DIVCTL_RXPH0DIV_M 0x00000004U 7811 #define LRFDRFE_DIVCTL_RXPH0DIV_S 2U 7812 #define LRFDRFE_DIVCTL_RXPH0DIV_EN 0x00000004U 7813 #define LRFDRFE_DIVCTL_RXPH0DIV_DIS 0x00000000U 7814 7815 // Field: [1] Spare1 7816 // 7817 // Not connected, not used in LRF 7818 // ENUMs: 7819 // ONE The bit is 1 7820 // ZERO The bit is 0 7821 #define LRFDRFE_DIVCTL_SPARE1 0x00000002U 7822 #define LRFDRFE_DIVCTL_SPARE1_M 0x00000002U 7823 #define LRFDRFE_DIVCTL_SPARE1_S 1U 7824 #define LRFDRFE_DIVCTL_SPARE1_ONE 0x00000002U 7825 #define LRFDRFE_DIVCTL_SPARE1_ZERO 0x00000000U 7826 7827 // Field: [0] EN 7828 // 7829 // Divider enable 7830 // ENUMs: 7831 // ON Enable divider 7832 // OFF Disable divider 7833 #define LRFDRFE_DIVCTL_EN 0x00000001U 7834 #define LRFDRFE_DIVCTL_EN_M 0x00000001U 7835 #define LRFDRFE_DIVCTL_EN_S 0U 7836 #define LRFDRFE_DIVCTL_EN_ON 0x00000001U 7837 #define LRFDRFE_DIVCTL_EN_OFF 0x00000000U 7838 7839 //***************************************************************************** 7840 // 7841 // Register: LRFDRFE_O_RXCTRL 7842 // 7843 //***************************************************************************** 7844 // Field: [12] SPARE 7845 // 7846 // Reserved for future use 7847 // ENUMs: 7848 // ONE The bit is 1 7849 // ZERO The bit is 0 7850 #define LRFDRFE_RXCTRL_SPARE 0x00001000U 7851 #define LRFDRFE_RXCTRL_SPARE_M 0x00001000U 7852 #define LRFDRFE_RXCTRL_SPARE_S 12U 7853 #define LRFDRFE_RXCTRL_SPARE_ONE 0x00001000U 7854 #define LRFDRFE_RXCTRL_SPARE_ZERO 0x00000000U 7855 7856 // Field: [11:9] ATTN 7857 // 7858 // Attenuator Control 7859 // ENUMs: 7860 // _21DB 21dB attenuation 7861 // _18DB 18dB attenuation 7862 // _15DB 15dB attenuation 7863 // _12DB 12dB attenuation 7864 // _9DB 9dB attenuation 7865 // _6DB 6dB attenuation 7866 // _3DB 3dB attenuation 7867 // NOATT No attenuation 7868 #define LRFDRFE_RXCTRL_ATTN_W 3U 7869 #define LRFDRFE_RXCTRL_ATTN_M 0x00000E00U 7870 #define LRFDRFE_RXCTRL_ATTN_S 9U 7871 #define LRFDRFE_RXCTRL_ATTN__21DB 0x00000E00U 7872 #define LRFDRFE_RXCTRL_ATTN__18DB 0x00000C00U 7873 #define LRFDRFE_RXCTRL_ATTN__15DB 0x00000A00U 7874 #define LRFDRFE_RXCTRL_ATTN__12DB 0x00000800U 7875 #define LRFDRFE_RXCTRL_ATTN__9DB 0x00000600U 7876 #define LRFDRFE_RXCTRL_ATTN__6DB 0x00000400U 7877 #define LRFDRFE_RXCTRL_ATTN__3DB 0x00000200U 7878 #define LRFDRFE_RXCTRL_ATTN_NOATT 0x00000000U 7879 7880 // Field: [8:4] IFAMPGC 7881 // 7882 // IFAMP Gain Control 7883 // ENUMs: 7884 // MAX Set IFAMP gain to MAX 7885 // MIN3DB Set gain to MAX - 3 dB 7886 // MIN6DB Set gain to MAX - 6 dB 7887 // MIN9DB Set gain to MAX - 9 dB 7888 // MIN12DB Set gain to MAX - 12 dB 7889 // MIN15DB Set gain to MAX - 15 dB 7890 #define LRFDRFE_RXCTRL_IFAMPGC_W 5U 7891 #define LRFDRFE_RXCTRL_IFAMPGC_M 0x000001F0U 7892 #define LRFDRFE_RXCTRL_IFAMPGC_S 4U 7893 #define LRFDRFE_RXCTRL_IFAMPGC_MAX 0x000001F0U 7894 #define LRFDRFE_RXCTRL_IFAMPGC_MIN3DB 0x000000F0U 7895 #define LRFDRFE_RXCTRL_IFAMPGC_MIN6DB 0x00000070U 7896 #define LRFDRFE_RXCTRL_IFAMPGC_MIN9DB 0x00000030U 7897 #define LRFDRFE_RXCTRL_IFAMPGC_MIN12DB 0x00000010U 7898 #define LRFDRFE_RXCTRL_IFAMPGC_MIN15DB 0x00000000U 7899 7900 // Field: [3:0] LNAGAIN 7901 // 7902 // LNA Gain Control 7903 // ENUMs: 7904 // MAX Set gain to MAX 7905 // MIN3DB Set gain to MAX - 3 dB 7906 // MIN6DB Set gain to MAX - 6 dB 7907 // MIN9DB Set gain to MAX - 9 dB 7908 // MIN12DB Set gain to MAX - 12 dB 7909 #define LRFDRFE_RXCTRL_LNAGAIN_W 4U 7910 #define LRFDRFE_RXCTRL_LNAGAIN_M 0x0000000FU 7911 #define LRFDRFE_RXCTRL_LNAGAIN_S 0U 7912 #define LRFDRFE_RXCTRL_LNAGAIN_MAX 0x0000000FU 7913 #define LRFDRFE_RXCTRL_LNAGAIN_MIN3DB 0x00000007U 7914 #define LRFDRFE_RXCTRL_LNAGAIN_MIN6DB 0x00000003U 7915 #define LRFDRFE_RXCTRL_LNAGAIN_MIN9DB 0x00000001U 7916 #define LRFDRFE_RXCTRL_LNAGAIN_MIN12DB 0x00000000U 7917 7918 //***************************************************************************** 7919 // 7920 // Register: LRFDRFE_O_MAGNACC0 7921 // 7922 //***************************************************************************** 7923 // Field: [15:0] VAL 7924 // 7925 // Accumulated magnitude over the period 7926 // ENUMs: 7927 // ALLONES All the bits are 1 7928 // ALLZEROS All the bits are 0 7929 #define LRFDRFE_MAGNACC0_VAL_W 16U 7930 #define LRFDRFE_MAGNACC0_VAL_M 0x0000FFFFU 7931 #define LRFDRFE_MAGNACC0_VAL_S 0U 7932 #define LRFDRFE_MAGNACC0_VAL_ALLONES 0x0000FFFFU 7933 #define LRFDRFE_MAGNACC0_VAL_ALLZEROS 0x00000000U 7934 7935 //***************************************************************************** 7936 // 7937 // Register: LRFDRFE_O_MAGNACC1 7938 // 7939 //***************************************************************************** 7940 // Field: [15:0] VAL 7941 // 7942 // Accumulated magnitude over the period 7943 // ENUMs: 7944 // ALLONES All the bits are 1 7945 // ALLZEROS All the bits are 0 7946 #define LRFDRFE_MAGNACC1_VAL_W 16U 7947 #define LRFDRFE_MAGNACC1_VAL_M 0x0000FFFFU 7948 #define LRFDRFE_MAGNACC1_VAL_S 0U 7949 #define LRFDRFE_MAGNACC1_VAL_ALLONES 0x0000FFFFU 7950 #define LRFDRFE_MAGNACC1_VAL_ALLZEROS 0x00000000U 7951 7952 //***************************************************************************** 7953 // 7954 // Register: LRFDRFE_O_RSSI 7955 // 7956 //***************************************************************************** 7957 // Field: [7:0] VAL 7958 // 7959 // Current RSSI value (signed). If this register reads as -128 (0x80) it means 7960 // that the value is not yet valid. 7961 // ENUMs: 7962 // ALLONES All the bits are 1 7963 // ALLZEROS All the bits are 0 7964 #define LRFDRFE_RSSI_VAL_W 8U 7965 #define LRFDRFE_RSSI_VAL_M 0x000000FFU 7966 #define LRFDRFE_RSSI_VAL_S 0U 7967 #define LRFDRFE_RSSI_VAL_ALLONES 0x000000FFU 7968 #define LRFDRFE_RSSI_VAL_ALLZEROS 0x00000000U 7969 7970 //***************************************************************************** 7971 // 7972 // Register: LRFDRFE_O_RSSIMAX 7973 // 7974 //***************************************************************************** 7975 // Field: [7:0] VAL 7976 // 7977 // Maximum RSSI value since start of measurements cycle. If this field reads as 7978 // -128 (0x80) it means that the value is not yet valid. 7979 // ENUMs: 7980 // ALLONES All the bits are 1 7981 // ALLZEROS All the bits are 0 7982 #define LRFDRFE_RSSIMAX_VAL_W 8U 7983 #define LRFDRFE_RSSIMAX_VAL_M 0x000000FFU 7984 #define LRFDRFE_RSSIMAX_VAL_S 0U 7985 #define LRFDRFE_RSSIMAX_VAL_ALLONES 0x000000FFU 7986 #define LRFDRFE_RSSIMAX_VAL_ALLZEROS 0x00000000U 7987 7988 //***************************************************************************** 7989 // 7990 // Register: LRFDRFE_O_RFGAIN 7991 // 7992 //***************************************************************************** 7993 // Field: [7:0] DBGAIN 7994 // 7995 // Current RF front-end gain, in dB 7996 // ENUMs: 7997 // ALLONES All the bits are 1 7998 // ALLZEROS All the bits are 0 7999 #define LRFDRFE_RFGAIN_DBGAIN_W 8U 8000 #define LRFDRFE_RFGAIN_DBGAIN_M 0x000000FFU 8001 #define LRFDRFE_RFGAIN_DBGAIN_S 0U 8002 #define LRFDRFE_RFGAIN_DBGAIN_ALLONES 0x000000FFU 8003 #define LRFDRFE_RFGAIN_DBGAIN_ALLZEROS 0x00000000U 8004 8005 //***************************************************************************** 8006 // 8007 // Register: LRFDRFE_O_IFADCSTAT 8008 // 8009 //***************************************************************************** 8010 // Field: [6:2] QUANTCALVAL 8011 // 8012 // Result of quantizer calibration. Valid only when calibration is done 8013 // ENUMs: 8014 // COMP1 I comparator 8015 // COMP0 Q Comparator 8016 #define LRFDRFE_IFADCSTAT_QUANTCALVAL_W 5U 8017 #define LRFDRFE_IFADCSTAT_QUANTCALVAL_M 0x0000007CU 8018 #define LRFDRFE_IFADCSTAT_QUANTCALVAL_S 2U 8019 #define LRFDRFE_IFADCSTAT_QUANTCALVAL_COMP1 0x00000004U 8020 #define LRFDRFE_IFADCSTAT_QUANTCALVAL_COMP0 0x00000000U 8021 8022 // Field: [1] QUANTCALDONE 8023 // 8024 // Status of the quantizer calibration 8025 // ENUMs: 8026 // READY Calibration is complete 8027 // NOT_READY Calibration is not finished 8028 #define LRFDRFE_IFADCSTAT_QUANTCALDONE 0x00000002U 8029 #define LRFDRFE_IFADCSTAT_QUANTCALDONE_M 0x00000002U 8030 #define LRFDRFE_IFADCSTAT_QUANTCALDONE_S 1U 8031 #define LRFDRFE_IFADCSTAT_QUANTCALDONE_READY 0x00000002U 8032 #define LRFDRFE_IFADCSTAT_QUANTCALDONE_NOT_READY 0x00000000U 8033 8034 //***************************************************************************** 8035 // 8036 // Register: LRFDRFE_O_DIVSTA 8037 // 8038 //***************************************************************************** 8039 // Field: [0] STAT 8040 // 8041 // Indicates status of serial divider 8042 // ENUMs: 8043 // BUSY Serial divider is busy and result is not available 8044 // yet 8045 // IDLE Serial divider is idle 8046 #define LRFDRFE_DIVSTA_STAT 0x00000001U 8047 #define LRFDRFE_DIVSTA_STAT_M 0x00000001U 8048 #define LRFDRFE_DIVSTA_STAT_S 0U 8049 #define LRFDRFE_DIVSTA_STAT_BUSY 0x00000001U 8050 #define LRFDRFE_DIVSTA_STAT_IDLE 0x00000000U 8051 8052 //***************************************************************************** 8053 // 8054 // Register: LRFDRFE_O_DIVIDENDL 8055 // 8056 //***************************************************************************** 8057 // Field: [15:0] VALLSB 8058 // 8059 // Dividend input (write only, reads as 0x0). 8060 // ENUMs: 8061 // ALLONES All the bits are 1 8062 // ALLZEROS All the bits are 0 8063 #define LRFDRFE_DIVIDENDL_VALLSB_W 16U 8064 #define LRFDRFE_DIVIDENDL_VALLSB_M 0x0000FFFFU 8065 #define LRFDRFE_DIVIDENDL_VALLSB_S 0U 8066 #define LRFDRFE_DIVIDENDL_VALLSB_ALLONES 0x0000FFFFU 8067 #define LRFDRFE_DIVIDENDL_VALLSB_ALLZEROS 0x00000000U 8068 8069 //***************************************************************************** 8070 // 8071 // Register: LRFDRFE_O_DIVIDENDH 8072 // 8073 //***************************************************************************** 8074 // Field: [15:0] VALMSB 8075 // 8076 // Dividend input (write only, reads as 0x0). 8077 // ENUMs: 8078 // ALLONES All the bits are 1 8079 // ALLZEROS All the bits are 0 8080 #define LRFDRFE_DIVIDENDH_VALMSB_W 16U 8081 #define LRFDRFE_DIVIDENDH_VALMSB_M 0x0000FFFFU 8082 #define LRFDRFE_DIVIDENDH_VALMSB_S 0U 8083 #define LRFDRFE_DIVIDENDH_VALMSB_ALLONES 0x0000FFFFU 8084 #define LRFDRFE_DIVIDENDH_VALMSB_ALLZEROS 0x00000000U 8085 8086 //***************************************************************************** 8087 // 8088 // Register: LRFDRFE_O_DIVISORL 8089 // 8090 //***************************************************************************** 8091 // Field: [15:0] VALLSB 8092 // 8093 // Divisor input. 8094 // ENUMs: 8095 // ALLONES All the bits are 1 8096 // ALLZEROS All the bits are 0 8097 #define LRFDRFE_DIVISORL_VALLSB_W 16U 8098 #define LRFDRFE_DIVISORL_VALLSB_M 0x0000FFFFU 8099 #define LRFDRFE_DIVISORL_VALLSB_S 0U 8100 #define LRFDRFE_DIVISORL_VALLSB_ALLONES 0x0000FFFFU 8101 #define LRFDRFE_DIVISORL_VALLSB_ALLZEROS 0x00000000U 8102 8103 //***************************************************************************** 8104 // 8105 // Register: LRFDRFE_O_DIVISORH 8106 // 8107 //***************************************************************************** 8108 // Field: [15:0] VALMSB 8109 // 8110 // Divisor input 8111 // ENUMs: 8112 // ALLONES All the bits are 1 8113 // ALLZEROS All the bits are 0 8114 #define LRFDRFE_DIVISORH_VALMSB_W 16U 8115 #define LRFDRFE_DIVISORH_VALMSB_M 0x0000FFFFU 8116 #define LRFDRFE_DIVISORH_VALMSB_S 0U 8117 #define LRFDRFE_DIVISORH_VALMSB_ALLONES 0x0000FFFFU 8118 #define LRFDRFE_DIVISORH_VALMSB_ALLZEROS 0x00000000U 8119 8120 //***************************************************************************** 8121 // 8122 // Register: LRFDRFE_O_QUOTIENTL 8123 // 8124 //***************************************************************************** 8125 // Field: [15:0] VALLSB 8126 // 8127 // Quotient output 8128 // ENUMs: 8129 // ALLONES All the bits are 1 8130 // ALLZEROS All the bits are 0 8131 #define LRFDRFE_QUOTIENTL_VALLSB_W 16U 8132 #define LRFDRFE_QUOTIENTL_VALLSB_M 0x0000FFFFU 8133 #define LRFDRFE_QUOTIENTL_VALLSB_S 0U 8134 #define LRFDRFE_QUOTIENTL_VALLSB_ALLONES 0x0000FFFFU 8135 #define LRFDRFE_QUOTIENTL_VALLSB_ALLZEROS 0x00000000U 8136 8137 //***************************************************************************** 8138 // 8139 // Register: LRFDRFE_O_QUOTIENTH 8140 // 8141 //***************************************************************************** 8142 // Field: [15:0] VALMSB 8143 // 8144 // Quotient output 8145 // ENUMs: 8146 // ALLONES All the bits are 1 8147 // ALLZEROS All the bits are 0 8148 #define LRFDRFE_QUOTIENTH_VALMSB_W 16U 8149 #define LRFDRFE_QUOTIENTH_VALMSB_M 0x0000FFFFU 8150 #define LRFDRFE_QUOTIENTH_VALMSB_S 0U 8151 #define LRFDRFE_QUOTIENTH_VALMSB_ALLONES 0x0000FFFFU 8152 #define LRFDRFE_QUOTIENTH_VALMSB_ALLZEROS 0x00000000U 8153 8154 //***************************************************************************** 8155 // 8156 // Register: LRFDRFE_O_PRODUCTL 8157 // 8158 //***************************************************************************** 8159 // Field: [15:0] VALLSB 8160 // 8161 // Product of DIVISORL_VALLSB and DIVISORH_VALMSB 8162 // ENUMs: 8163 // ALLONES All the bits are 1 8164 // ALLZEROS All the bits are 0 8165 #define LRFDRFE_PRODUCTL_VALLSB_W 16U 8166 #define LRFDRFE_PRODUCTL_VALLSB_M 0x0000FFFFU 8167 #define LRFDRFE_PRODUCTL_VALLSB_S 0U 8168 #define LRFDRFE_PRODUCTL_VALLSB_ALLONES 0x0000FFFFU 8169 #define LRFDRFE_PRODUCTL_VALLSB_ALLZEROS 0x00000000U 8170 8171 //***************************************************************************** 8172 // 8173 // Register: LRFDRFE_O_PRODUCTH 8174 // 8175 //***************************************************************************** 8176 // Field: [15:0] VALMSB 8177 // 8178 // Upper 16-bit of DIVISORL.VALLSB multiplied by DIVISORH.VALMSB 8179 // ENUMs: 8180 // ALLONES All the bits are 1 8181 // ALLZEROS All the bits are 0 8182 #define LRFDRFE_PRODUCTH_VALMSB_W 16U 8183 #define LRFDRFE_PRODUCTH_VALMSB_M 0x0000FFFFU 8184 #define LRFDRFE_PRODUCTH_VALMSB_S 0U 8185 #define LRFDRFE_PRODUCTH_VALMSB_ALLONES 0x0000FFFFU 8186 #define LRFDRFE_PRODUCTH_VALMSB_ALLZEROS 0x00000000U 8187 8188 //***************************************************************************** 8189 // 8190 // Register: LRFDRFE_O_MULTSTA 8191 // 8192 //***************************************************************************** 8193 // Field: [0] STAT 8194 // 8195 // Multiplier result ready / HW multiplier idle 8196 // ENUMs: 8197 // BUSY Multiplier is busy, result is not ready yet 8198 // IDLE Multiplier is idle 8199 #define LRFDRFE_MULTSTA_STAT 0x00000001U 8200 #define LRFDRFE_MULTSTA_STAT_M 0x00000001U 8201 #define LRFDRFE_MULTSTA_STAT_S 0U 8202 #define LRFDRFE_MULTSTA_STAT_BUSY 0x00000001U 8203 #define LRFDRFE_MULTSTA_STAT_IDLE 0x00000000U 8204 8205 //***************************************************************************** 8206 // 8207 // Register: LRFDRFE_O_MULTCFG 8208 // 8209 //***************************************************************************** 8210 // Field: [0] MODE 8211 // 8212 // Controls unsigned / signed mode of serial multiplier 8213 // ENUMs: 8214 // SIGNED Multiplier assumes inputs are signed numbers 8215 // UNSIGNED Multiplier assumes inputs are unsigned numbers 8216 #define LRFDRFE_MULTCFG_MODE 0x00000001U 8217 #define LRFDRFE_MULTCFG_MODE_M 0x00000001U 8218 #define LRFDRFE_MULTCFG_MODE_S 0U 8219 #define LRFDRFE_MULTCFG_MODE_SIGNED 0x00000001U 8220 #define LRFDRFE_MULTCFG_MODE_UNSIGNED 0x00000000U 8221 8222 8223 #endif // __LRFDRFE__ 8224
