1 /****************************************************************************** 2 * Filename: hw_lrfdrfe32_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_LRFDRFE32_H__ 34 #define __HW_LRFDRFE32_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // LRFDRFE32 component 40 // 41 //***************************************************************************** 42 // RF Engine Enable Register 43 #define LRFDRFE32_O_FWSRC_ENABLE 0x00000000U 44 45 // RF Engine Initialization Register 46 #define LRFDRFE32_O_PDREQ_INIT 0x00000004U 47 48 // RFE Event Flag Register 0 49 #define LRFDRFE32_O_EVT1_EVT0 0x00000008U 50 51 // RFE Event Mask Register 0 52 #define LRFDRFE32_O_EVTMSK1_EVTMSK0 0x0000000CU 53 54 // RFE Event Clear Register 0 55 #define LRFDRFE32_O_EVTCLR1_EVTCLR0 0x00000010U 56 57 // Status of the HFXT 58 #define LRFDRFE32_O_HFXTSTAT 0x00000014U 59 60 // RF state indication 61 #define LRFDRFE32_O_RFSTATE 0x00000018U 62 63 // RFE API Command Register 64 #define LRFDRFE32_O_CMDPAR0_API 0x00000024U 65 66 // RFE Command Parameter 1 67 #define LRFDRFE32_O_MSGBOX_CMDPAR1 0x00000028U 68 69 // RFE-to-MCE Send Data Register 70 #define LRFDRFE32_O_MCEDATIN0_MCEDATOUT0 0x0000002CU 71 72 // RFE-to-MCE Send Command Register 73 #define LRFDRFE32_O_MCECMDIN_MCECMDOUT 0x00000030U 74 75 // RFE-to-PBE Send Data Register 76 #define LRFDRFE32_O_PBEDATIN0_PBEDATOUT0 0x00000034U 77 78 // RFE-to-PBE Send Command Register 79 #define LRFDRFE32_O_PBECMDIN_PBECMDOUT 0x00000038U 80 81 // RFE FW Strobe Register 82 #define LRFDRFE32_O_STRB 0x0000003CU 83 84 // Controls automatic comparison of magnitude with threshold 85 #define LRFDRFE32_O_MAGNTHR_MAGNTHRCFG 0x00000040U 86 87 // RSSI Offset Adjustment Register 88 #define LRFDRFE32_O_GAINCTL_RSSIOFFSET 0x00000044U 89 90 // Magnitude estimator 0 control register 91 #define LRFDRFE32_O_MAGNCTL1_MAGNCTL0 0x00000048U 92 93 // Spare Value 94 #define LRFDRFE32_O_SPARE1_SPARE0 0x0000004CU 95 96 // Spare Value 97 #define LRFDRFE32_O_SPARE3_SPARE2 0x00000050U 98 99 // Spare Value 100 #define LRFDRFE32_O_SPARE5_SPARE4 0x00000054U 101 102 // LNA control 103 #define LRFDRFE32_O_IFAMPRFLDO_LNA 0x00000058U 104 105 // PA control register 106 #define LRFDRFE32_O_PA1_PA0 0x0000005CU 107 108 // ULNA control, TRX only 109 #define LRFDRFE32_O_IFADC0_ULNA 0x00000060U 110 111 // IFADC configuration register 112 #define LRFDRFE32_O_IFADCLF_IFADC1 0x00000064U 113 114 // IFADC configuration register 115 #define LRFDRFE32_O_IFADCALDO_IFADCQUANT 0x00000068U 116 117 // IFADCLDO configuration register 118 #define LRFDRFE32_O_IFADCTST_IFADCDLDO 0x0000006CU 119 120 // Analog test register 121 #define LRFDRFE32_O_ATSTREF 0x00000070U 122 123 // DCO Control 124 #define LRFDRFE32_O_DIV_DCO 0x00000074U 125 126 // LDO control 127 #define LRFDRFE32_O_TDCLDO_DIVLDO 0x00000078U 128 129 // LDO control 130 #define LRFDRFE32_O_DCOLDO1_DCOLDO0 0x0000007CU 131 132 // Predivider configuration 133 #define LRFDRFE32_O_PRE1_PRE0 0x00000080U 134 135 // Predivider configuration 136 #define LRFDRFE32_O_PRE3_PRE2 0x00000084U 137 138 // Calibration Configuration 0 139 #define LRFDRFE32_O_CAL1_CAL0 0x00000088U 140 141 // Calibration Configuration 2 142 #define LRFDRFE32_O_CAL3_CAL2 0x0000008CU 143 144 // SDM and Delay Configuration 145 #define LRFDRFE32_O_MISC1_MISC0 0x00000090U 146 147 // Loop Filter Configuration 148 #define LRFDRFE32_O_LF1_LF0 0x00000094U 149 150 // Phase Configuration 151 #define LRFDRFE32_O_PHINIT_PHEDISC 0x00000098U 152 153 // PLL Monitor Configuration 154 #define LRFDRFE32_O_PLLMON1_PLLMON0 0x0000009CU 155 156 // Modulator Configuration 157 #define LRFDRFE32_O_MOD1_MOD0 0x000000A0U 158 159 // Digital TX Configuration 0 160 #define LRFDRFE32_O_DTX1_DTX0 0x000000A4U 161 162 // Digital TX Configuration 2 163 #define LRFDRFE32_O_DTX3_DTX2 0x000000A8U 164 165 // Digital TX Configuration 4 166 #define LRFDRFE32_O_DTX5_DTX4 0x000000ACU 167 168 // Digital TX Configuration 6 169 #define LRFDRFE32_O_DTX7_DTX6 0x000000B0U 170 171 // Digital TX Configuration 8 172 #define LRFDRFE32_O_DTX9_DTX8 0x000000B4U 173 174 // Digital TX Configuration 10 175 #define LRFDRFE32_O_DTX11_DTX10 0x000000B8U 176 177 // PLL M0 178 #define LRFDRFE32_O_PLLM0 0x000000BCU 179 180 // PLL M1 181 #define LRFDRFE32_O_PLLM1 0x000000C0U 182 183 // Calibration M 184 #define LRFDRFE32_O_CALMMID_CALMCRS 0x000000C4U 185 186 // REFCLK Prescaler Load Value 187 #define LRFDRFE32_O_REFDIV 0x000000C8U 188 189 // DLO control register 0 190 #define LRFDRFE32_O_DLOCTL0 0x000000CCU 191 192 // DLO control register 1 193 #define LRFDRFE32_O_DLOCTL1 0x000000D0U 194 195 // DCO Override 196 #define LRFDRFE32_O_DCOOVR1_DCOOVR0 0x000000D4U 197 198 // Data test 199 #define LRFDRFE32_O_DLOEV_DTST 0x000000D8U 200 201 // DTST read 202 #define LRFDRFE32_O_FDCOSPANLSB_DTSTRD 0x000000DCU 203 204 // DCO frequency span 205 #define LRFDRFE32_O_TDCCAL_FDCOSPANMSB 0x000000E0U 206 207 // Calibration Code 208 #define LRFDRFE32_O_GPI_CALRES 0x000000E4U 209 210 // Math accellerator input value 211 #define LRFDRFE32_O_LIN2LOGOUT_MATHACCELIN 0x000000E8U 212 213 // Divide by three output register 214 #define LRFDRFE32_O_TIMCTL_DIVBY3OUT 0x000000ECU 215 216 // RFE Counter Increment Configuration 217 #define LRFDRFE32_O_TIMPER_TIMINC 0x000000F0U 218 219 // RFE Counter Value 220 #define LRFDRFE32_O_TIMCAPT_TIMCNT 0x000000F4U 221 222 // RFE Tracer Send Trigger Register 223 #define LRFDRFE32_O_TRCSTAT_TRCCTRL 0x000000F8U 224 225 // RFE Tracer Commmand Register 226 #define LRFDRFE32_O_TRCPAR0_TRCCMD 0x000000FCU 227 228 // RFE Tracer Command Parameter Register 1 229 #define LRFDRFE32_O_GPOCTL_TRCPAR1 0x00000100U 230 231 // Analog Isolation Control 232 #define LRFDRFE32_O_DIVCTL_ANAISOCTL 0x00000104U 233 234 // RX Frontend control register 235 #define LRFDRFE32_O_MAGNACC0_RXCTRL 0x00000108U 236 237 // Magnitude estimator 1 accumulator value 238 #define LRFDRFE32_O_RSSI_MAGNACC1 0x0000010CU 239 240 // RSSI Maximum Value Register 241 #define LRFDRFE32_O_RFGAIN_RSSIMAX 0x00000110U 242 243 // IFADC status 244 #define LRFDRFE32_O_DIVSTA_IFADCSTAT 0x00000114U 245 246 // Serial Divider Dividend Register 247 #define LRFDRFE32_O_DIVIDEND 0x00000118U 248 249 // Serial Divider Divisor Register 250 #define LRFDRFE32_O_DIVISOR 0x0000011CU 251 252 // Serial Divider Quotient Register 253 #define LRFDRFE32_O_QUOTIENT 0x00000120U 254 255 // Product of DIVISORL_VAL_LSB and DIVISORH_VAL_MSB 256 #define LRFDRFE32_O_PRODUCT 0x00000124U 257 258 // Serial Multiplier Status Register 259 #define LRFDRFE32_O_MULTSTA 0x00000128U 260 261 // Serial Multiplier Control Register 262 #define LRFDRFE32_O_MULTCFG 0x0000012CU 263 264 //***************************************************************************** 265 // 266 // Register: LRFDRFE32_O_FWSRC_ENABLE 267 // 268 //***************************************************************************** 269 // Field: [18] DATARAM 270 // 271 // ENUMs: 272 // S2RRAM Use S2RRAM for data 273 // RFERAM Use RFERAM for data 274 #define LRFDRFE32_FWSRC_ENABLE_DATARAM 0x00040000U 275 #define LRFDRFE32_FWSRC_ENABLE_DATARAM_M 0x00040000U 276 #define LRFDRFE32_FWSRC_ENABLE_DATARAM_S 18U 277 #define LRFDRFE32_FWSRC_ENABLE_DATARAM_S2RRAM 0x00040000U 278 #define LRFDRFE32_FWSRC_ENABLE_DATARAM_RFERAM 0x00000000U 279 280 // Field: [17] FWRAM 281 // 282 // ENUMs: 283 // S2RRAM Run code from S2RRAM 284 // RFERAM Run code from RFERAM 285 #define LRFDRFE32_FWSRC_ENABLE_FWRAM 0x00020000U 286 #define LRFDRFE32_FWSRC_ENABLE_FWRAM_M 0x00020000U 287 #define LRFDRFE32_FWSRC_ENABLE_FWRAM_S 17U 288 #define LRFDRFE32_FWSRC_ENABLE_FWRAM_S2RRAM 0x00020000U 289 #define LRFDRFE32_FWSRC_ENABLE_FWRAM_RFERAM 0x00000000U 290 291 // Field: [16] BANK 292 // 293 // ENUMs: 294 // ONE Run code from bank 1 295 // ZERO Run code from bank 0 296 #define LRFDRFE32_FWSRC_ENABLE_BANK 0x00010000U 297 #define LRFDRFE32_FWSRC_ENABLE_BANK_M 0x00010000U 298 #define LRFDRFE32_FWSRC_ENABLE_BANK_S 16U 299 #define LRFDRFE32_FWSRC_ENABLE_BANK_ONE 0x00010000U 300 #define LRFDRFE32_FWSRC_ENABLE_BANK_ZERO 0x00000000U 301 302 // Field: [3] ACC1 303 // 304 // ENUMs: 305 // EN Enable 306 // DIS Disable 307 #define LRFDRFE32_FWSRC_ENABLE_ACC1 0x00000008U 308 #define LRFDRFE32_FWSRC_ENABLE_ACC1_M 0x00000008U 309 #define LRFDRFE32_FWSRC_ENABLE_ACC1_S 3U 310 #define LRFDRFE32_FWSRC_ENABLE_ACC1_EN 0x00000008U 311 #define LRFDRFE32_FWSRC_ENABLE_ACC1_DIS 0x00000000U 312 313 // Field: [2] ACC0 314 // 315 // ENUMs: 316 // EN Enable 317 // DIS Disable 318 #define LRFDRFE32_FWSRC_ENABLE_ACC0 0x00000004U 319 #define LRFDRFE32_FWSRC_ENABLE_ACC0_M 0x00000004U 320 #define LRFDRFE32_FWSRC_ENABLE_ACC0_S 2U 321 #define LRFDRFE32_FWSRC_ENABLE_ACC0_EN 0x00000004U 322 #define LRFDRFE32_FWSRC_ENABLE_ACC0_DIS 0x00000000U 323 324 // Field: [1] LOCTIM 325 // 326 // ENUMs: 327 // EN Enable 328 // DIS Disable 329 #define LRFDRFE32_FWSRC_ENABLE_LOCTIM 0x00000002U 330 #define LRFDRFE32_FWSRC_ENABLE_LOCTIM_M 0x00000002U 331 #define LRFDRFE32_FWSRC_ENABLE_LOCTIM_S 1U 332 #define LRFDRFE32_FWSRC_ENABLE_LOCTIM_EN 0x00000002U 333 #define LRFDRFE32_FWSRC_ENABLE_LOCTIM_DIS 0x00000000U 334 335 // Field: [0] TOPSM 336 // 337 // ENUMs: 338 // EN Enable 339 // DIS Disable 340 #define LRFDRFE32_FWSRC_ENABLE_TOPSM 0x00000001U 341 #define LRFDRFE32_FWSRC_ENABLE_TOPSM_M 0x00000001U 342 #define LRFDRFE32_FWSRC_ENABLE_TOPSM_S 0U 343 #define LRFDRFE32_FWSRC_ENABLE_TOPSM_EN 0x00000001U 344 #define LRFDRFE32_FWSRC_ENABLE_TOPSM_DIS 0x00000000U 345 346 //***************************************************************************** 347 // 348 // Register: LRFDRFE32_O_PDREQ_INIT 349 // 350 //***************************************************************************** 351 // Field: [16] TOPSMPDREQ 352 // 353 // ENUMs: 354 // ONE The bit is 1 355 // ZERO The bit is 0 356 #define LRFDRFE32_PDREQ_INIT_TOPSMPDREQ 0x00010000U 357 #define LRFDRFE32_PDREQ_INIT_TOPSMPDREQ_M 0x00010000U 358 #define LRFDRFE32_PDREQ_INIT_TOPSMPDREQ_S 16U 359 #define LRFDRFE32_PDREQ_INIT_TOPSMPDREQ_ONE 0x00010000U 360 #define LRFDRFE32_PDREQ_INIT_TOPSMPDREQ_ZERO 0x00000000U 361 362 // Field: [3] ACC1 363 // 364 // ENUMs: 365 // RESET Reset module 366 // NO_EFFECT No effect 367 #define LRFDRFE32_PDREQ_INIT_ACC1 0x00000008U 368 #define LRFDRFE32_PDREQ_INIT_ACC1_M 0x00000008U 369 #define LRFDRFE32_PDREQ_INIT_ACC1_S 3U 370 #define LRFDRFE32_PDREQ_INIT_ACC1_RESET 0x00000008U 371 #define LRFDRFE32_PDREQ_INIT_ACC1_NO_EFFECT 0x00000000U 372 373 // Field: [2] ACC0 374 // 375 // ENUMs: 376 // RESET Reset module 377 // NO_EFFECT No effect 378 #define LRFDRFE32_PDREQ_INIT_ACC0 0x00000004U 379 #define LRFDRFE32_PDREQ_INIT_ACC0_M 0x00000004U 380 #define LRFDRFE32_PDREQ_INIT_ACC0_S 2U 381 #define LRFDRFE32_PDREQ_INIT_ACC0_RESET 0x00000004U 382 #define LRFDRFE32_PDREQ_INIT_ACC0_NO_EFFECT 0x00000000U 383 384 // Field: [1] LOCTIM 385 // 386 // ENUMs: 387 // RESET Reset module 388 // NO_EFFECT No effect 389 #define LRFDRFE32_PDREQ_INIT_LOCTIM 0x00000002U 390 #define LRFDRFE32_PDREQ_INIT_LOCTIM_M 0x00000002U 391 #define LRFDRFE32_PDREQ_INIT_LOCTIM_S 1U 392 #define LRFDRFE32_PDREQ_INIT_LOCTIM_RESET 0x00000002U 393 #define LRFDRFE32_PDREQ_INIT_LOCTIM_NO_EFFECT 0x00000000U 394 395 // Field: [0] TOPSM 396 // 397 // ENUMs: 398 // RESET Reset module 399 // NO_EFFECT No effect 400 #define LRFDRFE32_PDREQ_INIT_TOPSM 0x00000001U 401 #define LRFDRFE32_PDREQ_INIT_TOPSM_M 0x00000001U 402 #define LRFDRFE32_PDREQ_INIT_TOPSM_S 0U 403 #define LRFDRFE32_PDREQ_INIT_TOPSM_RESET 0x00000001U 404 #define LRFDRFE32_PDREQ_INIT_TOPSM_NO_EFFECT 0x00000000U 405 406 //***************************************************************************** 407 // 408 // Register: LRFDRFE32_O_EVT1_EVT0 409 // 410 //***************************************************************************** 411 // Field: [29] PREREFCLK 412 // 413 // ENUMs: 414 // ONE The bit is 1 415 // ZERO The bit is 0 416 #define LRFDRFE32_EVT1_EVT0_PREREFCLK 0x20000000U 417 #define LRFDRFE32_EVT1_EVT0_PREREFCLK_M 0x20000000U 418 #define LRFDRFE32_EVT1_EVT0_PREREFCLK_S 29U 419 #define LRFDRFE32_EVT1_EVT0_PREREFCLK_ONE 0x20000000U 420 #define LRFDRFE32_EVT1_EVT0_PREREFCLK_ZERO 0x00000000U 421 422 // Field: [28] REFCLK 423 // 424 // ENUMs: 425 // ONE The bit is 1 426 // ZERO The bit is 0 427 #define LRFDRFE32_EVT1_EVT0_REFCLK 0x10000000U 428 #define LRFDRFE32_EVT1_EVT0_REFCLK_M 0x10000000U 429 #define LRFDRFE32_EVT1_EVT0_REFCLK_S 28U 430 #define LRFDRFE32_EVT1_EVT0_REFCLK_ONE 0x10000000U 431 #define LRFDRFE32_EVT1_EVT0_REFCLK_ZERO 0x00000000U 432 433 // Field: [27] FBLWTHR 434 // 435 // ENUMs: 436 // ONE The bit is 1 437 // ZERO The bit is 0 438 #define LRFDRFE32_EVT1_EVT0_FBLWTHR 0x08000000U 439 #define LRFDRFE32_EVT1_EVT0_FBLWTHR_M 0x08000000U 440 #define LRFDRFE32_EVT1_EVT0_FBLWTHR_S 27U 441 #define LRFDRFE32_EVT1_EVT0_FBLWTHR_ONE 0x08000000U 442 #define LRFDRFE32_EVT1_EVT0_FBLWTHR_ZERO 0x00000000U 443 444 // Field: [26] FABVTHR 445 // 446 // ENUMs: 447 // ONE The bit is 1 448 // ZERO The bit is 0 449 #define LRFDRFE32_EVT1_EVT0_FABVTHR 0x04000000U 450 #define LRFDRFE32_EVT1_EVT0_FABVTHR_M 0x04000000U 451 #define LRFDRFE32_EVT1_EVT0_FABVTHR_S 26U 452 #define LRFDRFE32_EVT1_EVT0_FABVTHR_ONE 0x04000000U 453 #define LRFDRFE32_EVT1_EVT0_FABVTHR_ZERO 0x00000000U 454 455 // Field: [25] LOCK 456 // 457 // ENUMs: 458 // ONE The bit is 1 459 // ZERO The bit is 0 460 #define LRFDRFE32_EVT1_EVT0_LOCK 0x02000000U 461 #define LRFDRFE32_EVT1_EVT0_LOCK_M 0x02000000U 462 #define LRFDRFE32_EVT1_EVT0_LOCK_S 25U 463 #define LRFDRFE32_EVT1_EVT0_LOCK_ONE 0x02000000U 464 #define LRFDRFE32_EVT1_EVT0_LOCK_ZERO 0x00000000U 465 466 // Field: [24] LOL 467 // 468 // ENUMs: 469 // ONE The bit is 1 470 // ZERO The bit is 0 471 #define LRFDRFE32_EVT1_EVT0_LOL 0x01000000U 472 #define LRFDRFE32_EVT1_EVT0_LOL_M 0x01000000U 473 #define LRFDRFE32_EVT1_EVT0_LOL_S 24U 474 #define LRFDRFE32_EVT1_EVT0_LOL_ONE 0x01000000U 475 #define LRFDRFE32_EVT1_EVT0_LOL_ZERO 0x00000000U 476 477 // Field: [23] GPI7 478 // 479 // ENUMs: 480 // ONE The bit is 1 481 // ZERO The bit is 0 482 #define LRFDRFE32_EVT1_EVT0_GPI7 0x00800000U 483 #define LRFDRFE32_EVT1_EVT0_GPI7_M 0x00800000U 484 #define LRFDRFE32_EVT1_EVT0_GPI7_S 23U 485 #define LRFDRFE32_EVT1_EVT0_GPI7_ONE 0x00800000U 486 #define LRFDRFE32_EVT1_EVT0_GPI7_ZERO 0x00000000U 487 488 // Field: [22] GPI6 489 // 490 // ENUMs: 491 // ONE The bit is 1 492 // ZERO The bit is 0 493 #define LRFDRFE32_EVT1_EVT0_GPI6 0x00400000U 494 #define LRFDRFE32_EVT1_EVT0_GPI6_M 0x00400000U 495 #define LRFDRFE32_EVT1_EVT0_GPI6_S 22U 496 #define LRFDRFE32_EVT1_EVT0_GPI6_ONE 0x00400000U 497 #define LRFDRFE32_EVT1_EVT0_GPI6_ZERO 0x00000000U 498 499 // Field: [21] GPI5 500 // 501 // ENUMs: 502 // ONE The bit is 1 503 // ZERO The bit is 0 504 #define LRFDRFE32_EVT1_EVT0_GPI5 0x00200000U 505 #define LRFDRFE32_EVT1_EVT0_GPI5_M 0x00200000U 506 #define LRFDRFE32_EVT1_EVT0_GPI5_S 21U 507 #define LRFDRFE32_EVT1_EVT0_GPI5_ONE 0x00200000U 508 #define LRFDRFE32_EVT1_EVT0_GPI5_ZERO 0x00000000U 509 510 // Field: [20] GPI4 511 // 512 // ENUMs: 513 // ONE The bit is 1 514 // ZERO The bit is 0 515 #define LRFDRFE32_EVT1_EVT0_GPI4 0x00100000U 516 #define LRFDRFE32_EVT1_EVT0_GPI4_M 0x00100000U 517 #define LRFDRFE32_EVT1_EVT0_GPI4_S 20U 518 #define LRFDRFE32_EVT1_EVT0_GPI4_ONE 0x00100000U 519 #define LRFDRFE32_EVT1_EVT0_GPI4_ZERO 0x00000000U 520 521 // Field: [19] GPI3 522 // 523 // ENUMs: 524 // ONE The bit is 1 525 // ZERO The bit is 0 526 #define LRFDRFE32_EVT1_EVT0_GPI3 0x00080000U 527 #define LRFDRFE32_EVT1_EVT0_GPI3_M 0x00080000U 528 #define LRFDRFE32_EVT1_EVT0_GPI3_S 19U 529 #define LRFDRFE32_EVT1_EVT0_GPI3_ONE 0x00080000U 530 #define LRFDRFE32_EVT1_EVT0_GPI3_ZERO 0x00000000U 531 532 // Field: [18] GPI2 533 // 534 // ENUMs: 535 // ONE The bit is 1 536 // ZERO The bit is 0 537 #define LRFDRFE32_EVT1_EVT0_GPI2 0x00040000U 538 #define LRFDRFE32_EVT1_EVT0_GPI2_M 0x00040000U 539 #define LRFDRFE32_EVT1_EVT0_GPI2_S 18U 540 #define LRFDRFE32_EVT1_EVT0_GPI2_ONE 0x00040000U 541 #define LRFDRFE32_EVT1_EVT0_GPI2_ZERO 0x00000000U 542 543 // Field: [17] GPI1 544 // 545 // ENUMs: 546 // ONE The bit is 1 547 // ZERO The bit is 0 548 #define LRFDRFE32_EVT1_EVT0_GPI1 0x00020000U 549 #define LRFDRFE32_EVT1_EVT0_GPI1_M 0x00020000U 550 #define LRFDRFE32_EVT1_EVT0_GPI1_S 17U 551 #define LRFDRFE32_EVT1_EVT0_GPI1_ONE 0x00020000U 552 #define LRFDRFE32_EVT1_EVT0_GPI1_ZERO 0x00000000U 553 554 // Field: [16] GPI0 555 // 556 // ENUMs: 557 // ONE The bit is 1 558 // ZERO The bit is 0 559 #define LRFDRFE32_EVT1_EVT0_GPI0 0x00010000U 560 #define LRFDRFE32_EVT1_EVT0_GPI0_M 0x00010000U 561 #define LRFDRFE32_EVT1_EVT0_GPI0_S 16U 562 #define LRFDRFE32_EVT1_EVT0_GPI0_ONE 0x00010000U 563 #define LRFDRFE32_EVT1_EVT0_GPI0_ZERO 0x00000000U 564 565 // Field: [14] MAGNTHR 566 // 567 // ENUMs: 568 // ONE The bit is 1 569 // ZERO The bit is 0 570 #define LRFDRFE32_EVT1_EVT0_MAGNTHR 0x00004000U 571 #define LRFDRFE32_EVT1_EVT0_MAGNTHR_M 0x00004000U 572 #define LRFDRFE32_EVT1_EVT0_MAGNTHR_S 14U 573 #define LRFDRFE32_EVT1_EVT0_MAGNTHR_ONE 0x00004000U 574 #define LRFDRFE32_EVT1_EVT0_MAGNTHR_ZERO 0x00000000U 575 576 // Field: [13] S2RSTOP 577 // 578 // ENUMs: 579 // ONE The bit is 1 580 // ZERO The bit is 0 581 #define LRFDRFE32_EVT1_EVT0_S2RSTOP 0x00002000U 582 #define LRFDRFE32_EVT1_EVT0_S2RSTOP_M 0x00002000U 583 #define LRFDRFE32_EVT1_EVT0_S2RSTOP_S 13U 584 #define LRFDRFE32_EVT1_EVT0_S2RSTOP_ONE 0x00002000U 585 #define LRFDRFE32_EVT1_EVT0_S2RSTOP_ZERO 0x00000000U 586 587 // Field: [12] SYSTCMP2 588 // 589 // ENUMs: 590 // ONE The bit is 1 591 // ZERO The bit is 0 592 #define LRFDRFE32_EVT1_EVT0_SYSTCMP2 0x00001000U 593 #define LRFDRFE32_EVT1_EVT0_SYSTCMP2_M 0x00001000U 594 #define LRFDRFE32_EVT1_EVT0_SYSTCMP2_S 12U 595 #define LRFDRFE32_EVT1_EVT0_SYSTCMP2_ONE 0x00001000U 596 #define LRFDRFE32_EVT1_EVT0_SYSTCMP2_ZERO 0x00000000U 597 598 // Field: [11] SYSTCMP1 599 // 600 // ENUMs: 601 // ONE The bit is 1 602 // ZERO The bit is 0 603 #define LRFDRFE32_EVT1_EVT0_SYSTCMP1 0x00000800U 604 #define LRFDRFE32_EVT1_EVT0_SYSTCMP1_M 0x00000800U 605 #define LRFDRFE32_EVT1_EVT0_SYSTCMP1_S 11U 606 #define LRFDRFE32_EVT1_EVT0_SYSTCMP1_ONE 0x00000800U 607 #define LRFDRFE32_EVT1_EVT0_SYSTCMP1_ZERO 0x00000000U 608 609 // Field: [10] SYSTCMP0 610 // 611 // ENUMs: 612 // ONE The bit is 1 613 // ZERO The bit is 0 614 #define LRFDRFE32_EVT1_EVT0_SYSTCMP0 0x00000400U 615 #define LRFDRFE32_EVT1_EVT0_SYSTCMP0_M 0x00000400U 616 #define LRFDRFE32_EVT1_EVT0_SYSTCMP0_S 10U 617 #define LRFDRFE32_EVT1_EVT0_SYSTCMP0_ONE 0x00000400U 618 #define LRFDRFE32_EVT1_EVT0_SYSTCMP0_ZERO 0x00000000U 619 620 // Field: [9] PBERFEDAT 621 // 622 // ENUMs: 623 // ONE The bit is 1 624 // ZERO The bit is 0 625 #define LRFDRFE32_EVT1_EVT0_PBERFEDAT 0x00000200U 626 #define LRFDRFE32_EVT1_EVT0_PBERFEDAT_M 0x00000200U 627 #define LRFDRFE32_EVT1_EVT0_PBERFEDAT_S 9U 628 #define LRFDRFE32_EVT1_EVT0_PBERFEDAT_ONE 0x00000200U 629 #define LRFDRFE32_EVT1_EVT0_PBERFEDAT_ZERO 0x00000000U 630 631 // Field: [8] MDMRFEDAT 632 // 633 // ENUMs: 634 // ONE The bit is 1 635 // ZERO The bit is 0 636 #define LRFDRFE32_EVT1_EVT0_MDMRFEDAT 0x00000100U 637 #define LRFDRFE32_EVT1_EVT0_MDMRFEDAT_M 0x00000100U 638 #define LRFDRFE32_EVT1_EVT0_MDMRFEDAT_S 8U 639 #define LRFDRFE32_EVT1_EVT0_MDMRFEDAT_ONE 0x00000100U 640 #define LRFDRFE32_EVT1_EVT0_MDMRFEDAT_ZERO 0x00000000U 641 642 // Field: [7] DLO 643 // 644 // ENUMs: 645 // ONE The bit is 1 646 // ZERO The bit is 0 647 #define LRFDRFE32_EVT1_EVT0_DLO 0x00000080U 648 #define LRFDRFE32_EVT1_EVT0_DLO_M 0x00000080U 649 #define LRFDRFE32_EVT1_EVT0_DLO_S 7U 650 #define LRFDRFE32_EVT1_EVT0_DLO_ONE 0x00000080U 651 #define LRFDRFE32_EVT1_EVT0_DLO_ZERO 0x00000000U 652 653 // Field: [6] PBECMD 654 // 655 // ENUMs: 656 // ONE The bit is 1 657 // ZERO The bit is 0 658 #define LRFDRFE32_EVT1_EVT0_PBECMD 0x00000040U 659 #define LRFDRFE32_EVT1_EVT0_PBECMD_M 0x00000040U 660 #define LRFDRFE32_EVT1_EVT0_PBECMD_S 6U 661 #define LRFDRFE32_EVT1_EVT0_PBECMD_ONE 0x00000040U 662 #define LRFDRFE32_EVT1_EVT0_PBECMD_ZERO 0x00000000U 663 664 // Field: [5] COUNTER 665 // 666 // ENUMs: 667 // ONE The bit is 1 668 // ZERO The bit is 0 669 #define LRFDRFE32_EVT1_EVT0_COUNTER 0x00000020U 670 #define LRFDRFE32_EVT1_EVT0_COUNTER_M 0x00000020U 671 #define LRFDRFE32_EVT1_EVT0_COUNTER_S 5U 672 #define LRFDRFE32_EVT1_EVT0_COUNTER_ONE 0x00000020U 673 #define LRFDRFE32_EVT1_EVT0_COUNTER_ZERO 0x00000000U 674 675 // Field: [4] MDMCMD 676 // 677 // ENUMs: 678 // ONE The bit is 1 679 // ZERO The bit is 0 680 #define LRFDRFE32_EVT1_EVT0_MDMCMD 0x00000010U 681 #define LRFDRFE32_EVT1_EVT0_MDMCMD_M 0x00000010U 682 #define LRFDRFE32_EVT1_EVT0_MDMCMD_S 4U 683 #define LRFDRFE32_EVT1_EVT0_MDMCMD_ONE 0x00000010U 684 #define LRFDRFE32_EVT1_EVT0_MDMCMD_ZERO 0x00000000U 685 686 // Field: [3] ACC1 687 // 688 // ENUMs: 689 // ONE The bit is 1 690 // ZERO The bit is 0 691 #define LRFDRFE32_EVT1_EVT0_ACC1 0x00000008U 692 #define LRFDRFE32_EVT1_EVT0_ACC1_M 0x00000008U 693 #define LRFDRFE32_EVT1_EVT0_ACC1_S 3U 694 #define LRFDRFE32_EVT1_EVT0_ACC1_ONE 0x00000008U 695 #define LRFDRFE32_EVT1_EVT0_ACC1_ZERO 0x00000000U 696 697 // Field: [2] ACC0 698 // 699 // ENUMs: 700 // ONE The bit is 1 701 // ZERO The bit is 0 702 #define LRFDRFE32_EVT1_EVT0_ACC0 0x00000004U 703 #define LRFDRFE32_EVT1_EVT0_ACC0_M 0x00000004U 704 #define LRFDRFE32_EVT1_EVT0_ACC0_S 2U 705 #define LRFDRFE32_EVT1_EVT0_ACC0_ONE 0x00000004U 706 #define LRFDRFE32_EVT1_EVT0_ACC0_ZERO 0x00000000U 707 708 // Field: [1] TIMER 709 // 710 // ENUMs: 711 // ONE The bit is 1 712 // ZERO The bit is 0 713 #define LRFDRFE32_EVT1_EVT0_TIMER 0x00000002U 714 #define LRFDRFE32_EVT1_EVT0_TIMER_M 0x00000002U 715 #define LRFDRFE32_EVT1_EVT0_TIMER_S 1U 716 #define LRFDRFE32_EVT1_EVT0_TIMER_ONE 0x00000002U 717 #define LRFDRFE32_EVT1_EVT0_TIMER_ZERO 0x00000000U 718 719 // Field: [0] RFEAPI 720 // 721 // ENUMs: 722 // ONE The bit is 1 723 // ZERO The bit is 0 724 #define LRFDRFE32_EVT1_EVT0_RFEAPI 0x00000001U 725 #define LRFDRFE32_EVT1_EVT0_RFEAPI_M 0x00000001U 726 #define LRFDRFE32_EVT1_EVT0_RFEAPI_S 0U 727 #define LRFDRFE32_EVT1_EVT0_RFEAPI_ONE 0x00000001U 728 #define LRFDRFE32_EVT1_EVT0_RFEAPI_ZERO 0x00000000U 729 730 //***************************************************************************** 731 // 732 // Register: LRFDRFE32_O_EVTMSK1_EVTMSK0 733 // 734 //***************************************************************************** 735 // Field: [29] PREREFCLK 736 // 737 // ENUMs: 738 // EN The bit is 1 739 // DIS The bit is 0 740 #define LRFDRFE32_EVTMSK1_EVTMSK0_PREREFCLK 0x20000000U 741 #define LRFDRFE32_EVTMSK1_EVTMSK0_PREREFCLK_M 0x20000000U 742 #define LRFDRFE32_EVTMSK1_EVTMSK0_PREREFCLK_S 29U 743 #define LRFDRFE32_EVTMSK1_EVTMSK0_PREREFCLK_EN 0x20000000U 744 #define LRFDRFE32_EVTMSK1_EVTMSK0_PREREFCLK_DIS 0x00000000U 745 746 // Field: [28] REFCLK 747 // 748 // ENUMs: 749 // EN The bit is 1 750 // DIS The bit is 0 751 #define LRFDRFE32_EVTMSK1_EVTMSK0_REFCLK 0x10000000U 752 #define LRFDRFE32_EVTMSK1_EVTMSK0_REFCLK_M 0x10000000U 753 #define LRFDRFE32_EVTMSK1_EVTMSK0_REFCLK_S 28U 754 #define LRFDRFE32_EVTMSK1_EVTMSK0_REFCLK_EN 0x10000000U 755 #define LRFDRFE32_EVTMSK1_EVTMSK0_REFCLK_DIS 0x00000000U 756 757 // Field: [27] FBLWTHR 758 // 759 // ENUMs: 760 // EN The bit is 1 761 // DIS The bit is 0 762 #define LRFDRFE32_EVTMSK1_EVTMSK0_FBLWTHR 0x08000000U 763 #define LRFDRFE32_EVTMSK1_EVTMSK0_FBLWTHR_M 0x08000000U 764 #define LRFDRFE32_EVTMSK1_EVTMSK0_FBLWTHR_S 27U 765 #define LRFDRFE32_EVTMSK1_EVTMSK0_FBLWTHR_EN 0x08000000U 766 #define LRFDRFE32_EVTMSK1_EVTMSK0_FBLWTHR_DIS 0x00000000U 767 768 // Field: [26] FABVTHR 769 // 770 // ENUMs: 771 // EN The bit is 1 772 // DIS The bit is 0 773 #define LRFDRFE32_EVTMSK1_EVTMSK0_FABVTHR 0x04000000U 774 #define LRFDRFE32_EVTMSK1_EVTMSK0_FABVTHR_M 0x04000000U 775 #define LRFDRFE32_EVTMSK1_EVTMSK0_FABVTHR_S 26U 776 #define LRFDRFE32_EVTMSK1_EVTMSK0_FABVTHR_EN 0x04000000U 777 #define LRFDRFE32_EVTMSK1_EVTMSK0_FABVTHR_DIS 0x00000000U 778 779 // Field: [25] LOCK 780 // 781 // ENUMs: 782 // EN The bit is 1 783 // DIS The bit is 0 784 #define LRFDRFE32_EVTMSK1_EVTMSK0_LOCK 0x02000000U 785 #define LRFDRFE32_EVTMSK1_EVTMSK0_LOCK_M 0x02000000U 786 #define LRFDRFE32_EVTMSK1_EVTMSK0_LOCK_S 25U 787 #define LRFDRFE32_EVTMSK1_EVTMSK0_LOCK_EN 0x02000000U 788 #define LRFDRFE32_EVTMSK1_EVTMSK0_LOCK_DIS 0x00000000U 789 790 // Field: [24] LOL 791 // 792 // ENUMs: 793 // EN The bit is 1 794 // DIS The bit is 0 795 #define LRFDRFE32_EVTMSK1_EVTMSK0_LOL 0x01000000U 796 #define LRFDRFE32_EVTMSK1_EVTMSK0_LOL_M 0x01000000U 797 #define LRFDRFE32_EVTMSK1_EVTMSK0_LOL_S 24U 798 #define LRFDRFE32_EVTMSK1_EVTMSK0_LOL_EN 0x01000000U 799 #define LRFDRFE32_EVTMSK1_EVTMSK0_LOL_DIS 0x00000000U 800 801 // Field: [23] GPI7 802 // 803 // ENUMs: 804 // EN The bit is 1 805 // DIS The bit is 0 806 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI7 0x00800000U 807 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI7_M 0x00800000U 808 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI7_S 23U 809 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI7_EN 0x00800000U 810 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI7_DIS 0x00000000U 811 812 // Field: [22] GPI6 813 // 814 // ENUMs: 815 // EN The bit is 1 816 // DIS The bit is 0 817 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI6 0x00400000U 818 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI6_M 0x00400000U 819 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI6_S 22U 820 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI6_EN 0x00400000U 821 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI6_DIS 0x00000000U 822 823 // Field: [21] GPI5 824 // 825 // ENUMs: 826 // EN The bit is 1 827 // DIS The bit is 0 828 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI5 0x00200000U 829 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI5_M 0x00200000U 830 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI5_S 21U 831 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI5_EN 0x00200000U 832 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI5_DIS 0x00000000U 833 834 // Field: [20] GPI4 835 // 836 // ENUMs: 837 // EN The bit is 1 838 // DIS The bit is 0 839 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI4 0x00100000U 840 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI4_M 0x00100000U 841 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI4_S 20U 842 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI4_EN 0x00100000U 843 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI4_DIS 0x00000000U 844 845 // Field: [19] GPI3 846 // 847 // ENUMs: 848 // EN The bit is 1 849 // DIS The bit is 0 850 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI3 0x00080000U 851 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI3_M 0x00080000U 852 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI3_S 19U 853 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI3_EN 0x00080000U 854 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI3_DIS 0x00000000U 855 856 // Field: [18] GPI2 857 // 858 // ENUMs: 859 // EN The bit is 1 860 // DIS The bit is 0 861 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI2 0x00040000U 862 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI2_M 0x00040000U 863 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI2_S 18U 864 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI2_EN 0x00040000U 865 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI2_DIS 0x00000000U 866 867 // Field: [17] GPI1 868 // 869 // ENUMs: 870 // EN The bit is 1 871 // DIS The bit is 0 872 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI1 0x00020000U 873 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI1_M 0x00020000U 874 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI1_S 17U 875 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI1_EN 0x00020000U 876 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI1_DIS 0x00000000U 877 878 // Field: [16] GPI0 879 // 880 // ENUMs: 881 // EN The bit is 1 882 // DIS The bit is 0 883 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI0 0x00010000U 884 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI0_M 0x00010000U 885 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI0_S 16U 886 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI0_EN 0x00010000U 887 #define LRFDRFE32_EVTMSK1_EVTMSK0_GPI0_DIS 0x00000000U 888 889 // Field: [14] MAGNTHR 890 // 891 // ENUMs: 892 // EN The bit is 1 893 // DIS The bit is 0 894 #define LRFDRFE32_EVTMSK1_EVTMSK0_MAGNTHR 0x00004000U 895 #define LRFDRFE32_EVTMSK1_EVTMSK0_MAGNTHR_M 0x00004000U 896 #define LRFDRFE32_EVTMSK1_EVTMSK0_MAGNTHR_S 14U 897 #define LRFDRFE32_EVTMSK1_EVTMSK0_MAGNTHR_EN 0x00004000U 898 #define LRFDRFE32_EVTMSK1_EVTMSK0_MAGNTHR_DIS 0x00000000U 899 900 // Field: [13] S2RSTOP 901 // 902 // ENUMs: 903 // EN The bit is 1 904 // DIS The bit is 0 905 #define LRFDRFE32_EVTMSK1_EVTMSK0_S2RSTOP 0x00002000U 906 #define LRFDRFE32_EVTMSK1_EVTMSK0_S2RSTOP_M 0x00002000U 907 #define LRFDRFE32_EVTMSK1_EVTMSK0_S2RSTOP_S 13U 908 #define LRFDRFE32_EVTMSK1_EVTMSK0_S2RSTOP_EN 0x00002000U 909 #define LRFDRFE32_EVTMSK1_EVTMSK0_S2RSTOP_DIS 0x00000000U 910 911 // Field: [12] SYSTCMP2 912 // 913 // ENUMs: 914 // EN The bit is 1 915 // DIS The bit is 0 916 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP2 0x00001000U 917 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP2_M 0x00001000U 918 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP2_S 12U 919 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP2_EN 0x00001000U 920 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP2_DIS 0x00000000U 921 922 // Field: [11] SYSTCMP1 923 // 924 // ENUMs: 925 // EN The bit is 1 926 // DIS The bit is 0 927 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP1 0x00000800U 928 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP1_M 0x00000800U 929 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP1_S 11U 930 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP1_EN 0x00000800U 931 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP1_DIS 0x00000000U 932 933 // Field: [10] SYSTCMP0 934 // 935 // ENUMs: 936 // EN The bit is 1 937 // DIS The bit is 0 938 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP0 0x00000400U 939 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP0_M 0x00000400U 940 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP0_S 10U 941 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP0_EN 0x00000400U 942 #define LRFDRFE32_EVTMSK1_EVTMSK0_SYSTCMP0_DIS 0x00000000U 943 944 // Field: [9] PBERFEDAT 945 // 946 // ENUMs: 947 // EN The bit is 1 948 // DIS The bit is 0 949 #define LRFDRFE32_EVTMSK1_EVTMSK0_PBERFEDAT 0x00000200U 950 #define LRFDRFE32_EVTMSK1_EVTMSK0_PBERFEDAT_M 0x00000200U 951 #define LRFDRFE32_EVTMSK1_EVTMSK0_PBERFEDAT_S 9U 952 #define LRFDRFE32_EVTMSK1_EVTMSK0_PBERFEDAT_EN 0x00000200U 953 #define LRFDRFE32_EVTMSK1_EVTMSK0_PBERFEDAT_DIS 0x00000000U 954 955 // Field: [8] MDMRFEDAT 956 // 957 // ENUMs: 958 // EN The bit is 1 959 // DIS The bit is 0 960 #define LRFDRFE32_EVTMSK1_EVTMSK0_MDMRFEDAT 0x00000100U 961 #define LRFDRFE32_EVTMSK1_EVTMSK0_MDMRFEDAT_M 0x00000100U 962 #define LRFDRFE32_EVTMSK1_EVTMSK0_MDMRFEDAT_S 8U 963 #define LRFDRFE32_EVTMSK1_EVTMSK0_MDMRFEDAT_EN 0x00000100U 964 #define LRFDRFE32_EVTMSK1_EVTMSK0_MDMRFEDAT_DIS 0x00000000U 965 966 // Field: [7] DLO 967 // 968 // ENUMs: 969 // EN The bit is 1 970 // DIS The bit is 0 971 #define LRFDRFE32_EVTMSK1_EVTMSK0_DLO 0x00000080U 972 #define LRFDRFE32_EVTMSK1_EVTMSK0_DLO_M 0x00000080U 973 #define LRFDRFE32_EVTMSK1_EVTMSK0_DLO_S 7U 974 #define LRFDRFE32_EVTMSK1_EVTMSK0_DLO_EN 0x00000080U 975 #define LRFDRFE32_EVTMSK1_EVTMSK0_DLO_DIS 0x00000000U 976 977 // Field: [6] PBECMD 978 // 979 // ENUMs: 980 // EN The bit is 1 981 // DIS The bit is 0 982 #define LRFDRFE32_EVTMSK1_EVTMSK0_PBECMD 0x00000040U 983 #define LRFDRFE32_EVTMSK1_EVTMSK0_PBECMD_M 0x00000040U 984 #define LRFDRFE32_EVTMSK1_EVTMSK0_PBECMD_S 6U 985 #define LRFDRFE32_EVTMSK1_EVTMSK0_PBECMD_EN 0x00000040U 986 #define LRFDRFE32_EVTMSK1_EVTMSK0_PBECMD_DIS 0x00000000U 987 988 // Field: [5] COUNTER 989 // 990 // ENUMs: 991 // EN The bit is 1 992 // DIS The bit is 0 993 #define LRFDRFE32_EVTMSK1_EVTMSK0_COUNTER 0x00000020U 994 #define LRFDRFE32_EVTMSK1_EVTMSK0_COUNTER_M 0x00000020U 995 #define LRFDRFE32_EVTMSK1_EVTMSK0_COUNTER_S 5U 996 #define LRFDRFE32_EVTMSK1_EVTMSK0_COUNTER_EN 0x00000020U 997 #define LRFDRFE32_EVTMSK1_EVTMSK0_COUNTER_DIS 0x00000000U 998 999 // Field: [4] MDMCMD 1000 // 1001 // ENUMs: 1002 // EN The bit is 1 1003 // DIS The bit is 0 1004 #define LRFDRFE32_EVTMSK1_EVTMSK0_MDMCMD 0x00000010U 1005 #define LRFDRFE32_EVTMSK1_EVTMSK0_MDMCMD_M 0x00000010U 1006 #define LRFDRFE32_EVTMSK1_EVTMSK0_MDMCMD_S 4U 1007 #define LRFDRFE32_EVTMSK1_EVTMSK0_MDMCMD_EN 0x00000010U 1008 #define LRFDRFE32_EVTMSK1_EVTMSK0_MDMCMD_DIS 0x00000000U 1009 1010 // Field: [3] ACC1 1011 // 1012 // ENUMs: 1013 // EN The bit is 1 1014 // DIS The bit is 0 1015 #define LRFDRFE32_EVTMSK1_EVTMSK0_ACC1 0x00000008U 1016 #define LRFDRFE32_EVTMSK1_EVTMSK0_ACC1_M 0x00000008U 1017 #define LRFDRFE32_EVTMSK1_EVTMSK0_ACC1_S 3U 1018 #define LRFDRFE32_EVTMSK1_EVTMSK0_ACC1_EN 0x00000008U 1019 #define LRFDRFE32_EVTMSK1_EVTMSK0_ACC1_DIS 0x00000000U 1020 1021 // Field: [2] ACC0 1022 // 1023 // ENUMs: 1024 // EN The bit is 1 1025 // DIS The bit is 0 1026 #define LRFDRFE32_EVTMSK1_EVTMSK0_ACC0 0x00000004U 1027 #define LRFDRFE32_EVTMSK1_EVTMSK0_ACC0_M 0x00000004U 1028 #define LRFDRFE32_EVTMSK1_EVTMSK0_ACC0_S 2U 1029 #define LRFDRFE32_EVTMSK1_EVTMSK0_ACC0_EN 0x00000004U 1030 #define LRFDRFE32_EVTMSK1_EVTMSK0_ACC0_DIS 0x00000000U 1031 1032 // Field: [1] TIMER 1033 // 1034 // ENUMs: 1035 // EN The bit is 1 1036 // DIS The bit is 0 1037 #define LRFDRFE32_EVTMSK1_EVTMSK0_TIMER 0x00000002U 1038 #define LRFDRFE32_EVTMSK1_EVTMSK0_TIMER_M 0x00000002U 1039 #define LRFDRFE32_EVTMSK1_EVTMSK0_TIMER_S 1U 1040 #define LRFDRFE32_EVTMSK1_EVTMSK0_TIMER_EN 0x00000002U 1041 #define LRFDRFE32_EVTMSK1_EVTMSK0_TIMER_DIS 0x00000000U 1042 1043 // Field: [0] RFEAPI 1044 // 1045 // ENUMs: 1046 // EN The bit is 1 1047 // DIS The bit is 0 1048 #define LRFDRFE32_EVTMSK1_EVTMSK0_RFEAPI 0x00000001U 1049 #define LRFDRFE32_EVTMSK1_EVTMSK0_RFEAPI_M 0x00000001U 1050 #define LRFDRFE32_EVTMSK1_EVTMSK0_RFEAPI_S 0U 1051 #define LRFDRFE32_EVTMSK1_EVTMSK0_RFEAPI_EN 0x00000001U 1052 #define LRFDRFE32_EVTMSK1_EVTMSK0_RFEAPI_DIS 0x00000000U 1053 1054 //***************************************************************************** 1055 // 1056 // Register: LRFDRFE32_O_EVTCLR1_EVTCLR0 1057 // 1058 //***************************************************************************** 1059 // Field: [29] PREREFCLK 1060 // 1061 // ENUMs: 1062 // ONE The bit is 1 1063 // ZERO The bit is 0 1064 #define LRFDRFE32_EVTCLR1_EVTCLR0_PREREFCLK 0x20000000U 1065 #define LRFDRFE32_EVTCLR1_EVTCLR0_PREREFCLK_M 0x20000000U 1066 #define LRFDRFE32_EVTCLR1_EVTCLR0_PREREFCLK_S 29U 1067 #define LRFDRFE32_EVTCLR1_EVTCLR0_PREREFCLK_ONE 0x20000000U 1068 #define LRFDRFE32_EVTCLR1_EVTCLR0_PREREFCLK_ZERO 0x00000000U 1069 1070 // Field: [28] REFCLK 1071 // 1072 // ENUMs: 1073 // ONE The bit is 1 1074 // ZERO The bit is 0 1075 #define LRFDRFE32_EVTCLR1_EVTCLR0_REFCLK 0x10000000U 1076 #define LRFDRFE32_EVTCLR1_EVTCLR0_REFCLK_M 0x10000000U 1077 #define LRFDRFE32_EVTCLR1_EVTCLR0_REFCLK_S 28U 1078 #define LRFDRFE32_EVTCLR1_EVTCLR0_REFCLK_ONE 0x10000000U 1079 #define LRFDRFE32_EVTCLR1_EVTCLR0_REFCLK_ZERO 0x00000000U 1080 1081 // Field: [27] FBLWTHR 1082 // 1083 // ENUMs: 1084 // ONE The bit is 1 1085 // ZERO The bit is 0 1086 #define LRFDRFE32_EVTCLR1_EVTCLR0_FBLWTHR 0x08000000U 1087 #define LRFDRFE32_EVTCLR1_EVTCLR0_FBLWTHR_M 0x08000000U 1088 #define LRFDRFE32_EVTCLR1_EVTCLR0_FBLWTHR_S 27U 1089 #define LRFDRFE32_EVTCLR1_EVTCLR0_FBLWTHR_ONE 0x08000000U 1090 #define LRFDRFE32_EVTCLR1_EVTCLR0_FBLWTHR_ZERO 0x00000000U 1091 1092 // Field: [26] FABVTHR 1093 // 1094 // ENUMs: 1095 // ONE The bit is 1 1096 // ZERO The bit is 0 1097 #define LRFDRFE32_EVTCLR1_EVTCLR0_FABVTHR 0x04000000U 1098 #define LRFDRFE32_EVTCLR1_EVTCLR0_FABVTHR_M 0x04000000U 1099 #define LRFDRFE32_EVTCLR1_EVTCLR0_FABVTHR_S 26U 1100 #define LRFDRFE32_EVTCLR1_EVTCLR0_FABVTHR_ONE 0x04000000U 1101 #define LRFDRFE32_EVTCLR1_EVTCLR0_FABVTHR_ZERO 0x00000000U 1102 1103 // Field: [25] LOCK 1104 // 1105 // ENUMs: 1106 // ONE The bit is 1 1107 // ZERO The bit is 0 1108 #define LRFDRFE32_EVTCLR1_EVTCLR0_LOCK 0x02000000U 1109 #define LRFDRFE32_EVTCLR1_EVTCLR0_LOCK_M 0x02000000U 1110 #define LRFDRFE32_EVTCLR1_EVTCLR0_LOCK_S 25U 1111 #define LRFDRFE32_EVTCLR1_EVTCLR0_LOCK_ONE 0x02000000U 1112 #define LRFDRFE32_EVTCLR1_EVTCLR0_LOCK_ZERO 0x00000000U 1113 1114 // Field: [24] LOL 1115 // 1116 // ENUMs: 1117 // ONE The bit is 1 1118 // ZERO The bit is 0 1119 #define LRFDRFE32_EVTCLR1_EVTCLR0_LOL 0x01000000U 1120 #define LRFDRFE32_EVTCLR1_EVTCLR0_LOL_M 0x01000000U 1121 #define LRFDRFE32_EVTCLR1_EVTCLR0_LOL_S 24U 1122 #define LRFDRFE32_EVTCLR1_EVTCLR0_LOL_ONE 0x01000000U 1123 #define LRFDRFE32_EVTCLR1_EVTCLR0_LOL_ZERO 0x00000000U 1124 1125 // Field: [23] GPI7 1126 // 1127 // ENUMs: 1128 // ONE The bit is 1 1129 // ZERO The bit is 0 1130 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI7 0x00800000U 1131 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI7_M 0x00800000U 1132 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI7_S 23U 1133 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI7_ONE 0x00800000U 1134 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI7_ZERO 0x00000000U 1135 1136 // Field: [22] GPI6 1137 // 1138 // ENUMs: 1139 // ONE The bit is 1 1140 // ZERO The bit is 0 1141 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI6 0x00400000U 1142 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI6_M 0x00400000U 1143 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI6_S 22U 1144 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI6_ONE 0x00400000U 1145 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI6_ZERO 0x00000000U 1146 1147 // Field: [21] GPI5 1148 // 1149 // ENUMs: 1150 // ONE The bit is 1 1151 // ZERO The bit is 0 1152 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI5 0x00200000U 1153 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI5_M 0x00200000U 1154 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI5_S 21U 1155 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI5_ONE 0x00200000U 1156 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI5_ZERO 0x00000000U 1157 1158 // Field: [20] GPI4 1159 // 1160 // ENUMs: 1161 // ONE The bit is 1 1162 // ZERO The bit is 0 1163 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI4 0x00100000U 1164 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI4_M 0x00100000U 1165 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI4_S 20U 1166 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI4_ONE 0x00100000U 1167 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI4_ZERO 0x00000000U 1168 1169 // Field: [19] GPI3 1170 // 1171 // ENUMs: 1172 // ONE The bit is 1 1173 // ZERO The bit is 0 1174 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI3 0x00080000U 1175 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI3_M 0x00080000U 1176 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI3_S 19U 1177 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI3_ONE 0x00080000U 1178 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI3_ZERO 0x00000000U 1179 1180 // Field: [18] GPI2 1181 // 1182 // ENUMs: 1183 // ONE The bit is 1 1184 // ZERO The bit is 0 1185 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI2 0x00040000U 1186 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI2_M 0x00040000U 1187 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI2_S 18U 1188 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI2_ONE 0x00040000U 1189 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI2_ZERO 0x00000000U 1190 1191 // Field: [17] GPI1 1192 // 1193 // ENUMs: 1194 // ONE The bit is 1 1195 // ZERO The bit is 0 1196 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI1 0x00020000U 1197 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI1_M 0x00020000U 1198 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI1_S 17U 1199 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI1_ONE 0x00020000U 1200 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI1_ZERO 0x00000000U 1201 1202 // Field: [16] GPI0 1203 // 1204 // ENUMs: 1205 // ONE The bit is 1 1206 // ZERO The bit is 0 1207 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI0 0x00010000U 1208 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI0_M 0x00010000U 1209 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI0_S 16U 1210 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI0_ONE 0x00010000U 1211 #define LRFDRFE32_EVTCLR1_EVTCLR0_GPI0_ZERO 0x00000000U 1212 1213 // Field: [14] MAGNTHR 1214 // 1215 // ENUMs: 1216 // ONE The bit is 1 1217 // ZERO The bit is 0 1218 #define LRFDRFE32_EVTCLR1_EVTCLR0_MAGNTHR 0x00004000U 1219 #define LRFDRFE32_EVTCLR1_EVTCLR0_MAGNTHR_M 0x00004000U 1220 #define LRFDRFE32_EVTCLR1_EVTCLR0_MAGNTHR_S 14U 1221 #define LRFDRFE32_EVTCLR1_EVTCLR0_MAGNTHR_ONE 0x00004000U 1222 #define LRFDRFE32_EVTCLR1_EVTCLR0_MAGNTHR_ZERO 0x00000000U 1223 1224 // Field: [13] S2RSTOP 1225 // 1226 // ENUMs: 1227 // ONE The bit is 1 1228 // ZERO The bit is 0 1229 #define LRFDRFE32_EVTCLR1_EVTCLR0_S2RSTOP 0x00002000U 1230 #define LRFDRFE32_EVTCLR1_EVTCLR0_S2RSTOP_M 0x00002000U 1231 #define LRFDRFE32_EVTCLR1_EVTCLR0_S2RSTOP_S 13U 1232 #define LRFDRFE32_EVTCLR1_EVTCLR0_S2RSTOP_ONE 0x00002000U 1233 #define LRFDRFE32_EVTCLR1_EVTCLR0_S2RSTOP_ZERO 0x00000000U 1234 1235 // Field: [12] SYSTCMP2 1236 // 1237 // ENUMs: 1238 // ONE The bit is 1 1239 // ZERO The bit is 0 1240 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP2 0x00001000U 1241 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP2_M 0x00001000U 1242 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP2_S 12U 1243 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP2_ONE 0x00001000U 1244 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP2_ZERO 0x00000000U 1245 1246 // Field: [11] SYSTCMP1 1247 // 1248 // ENUMs: 1249 // ONE The bit is 1 1250 // ZERO The bit is 0 1251 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP1 0x00000800U 1252 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP1_M 0x00000800U 1253 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP1_S 11U 1254 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP1_ONE 0x00000800U 1255 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP1_ZERO 0x00000000U 1256 1257 // Field: [10] SYSTCMP0 1258 // 1259 // ENUMs: 1260 // ONE The bit is 1 1261 // ZERO The bit is 0 1262 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP0 0x00000400U 1263 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP0_M 0x00000400U 1264 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP0_S 10U 1265 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP0_ONE 0x00000400U 1266 #define LRFDRFE32_EVTCLR1_EVTCLR0_SYSTCMP0_ZERO 0x00000000U 1267 1268 // Field: [9] PBERFEDAT 1269 // 1270 // ENUMs: 1271 // ONE The bit is 1 1272 // ZERO The bit is 0 1273 #define LRFDRFE32_EVTCLR1_EVTCLR0_PBERFEDAT 0x00000200U 1274 #define LRFDRFE32_EVTCLR1_EVTCLR0_PBERFEDAT_M 0x00000200U 1275 #define LRFDRFE32_EVTCLR1_EVTCLR0_PBERFEDAT_S 9U 1276 #define LRFDRFE32_EVTCLR1_EVTCLR0_PBERFEDAT_ONE 0x00000200U 1277 #define LRFDRFE32_EVTCLR1_EVTCLR0_PBERFEDAT_ZERO 0x00000000U 1278 1279 // Field: [8] MDMRFEDAT 1280 // 1281 // ENUMs: 1282 // ONE The bit is 1 1283 // ZERO The bit is 0 1284 #define LRFDRFE32_EVTCLR1_EVTCLR0_MDMRFEDAT 0x00000100U 1285 #define LRFDRFE32_EVTCLR1_EVTCLR0_MDMRFEDAT_M 0x00000100U 1286 #define LRFDRFE32_EVTCLR1_EVTCLR0_MDMRFEDAT_S 8U 1287 #define LRFDRFE32_EVTCLR1_EVTCLR0_MDMRFEDAT_ONE 0x00000100U 1288 #define LRFDRFE32_EVTCLR1_EVTCLR0_MDMRFEDAT_ZERO 0x00000000U 1289 1290 // Field: [7] DLO 1291 // 1292 // ENUMs: 1293 // ONE The bit is 1 1294 // ZERO The bit is 0 1295 #define LRFDRFE32_EVTCLR1_EVTCLR0_DLO 0x00000080U 1296 #define LRFDRFE32_EVTCLR1_EVTCLR0_DLO_M 0x00000080U 1297 #define LRFDRFE32_EVTCLR1_EVTCLR0_DLO_S 7U 1298 #define LRFDRFE32_EVTCLR1_EVTCLR0_DLO_ONE 0x00000080U 1299 #define LRFDRFE32_EVTCLR1_EVTCLR0_DLO_ZERO 0x00000000U 1300 1301 // Field: [6] PBECMD 1302 // 1303 // ENUMs: 1304 // ONE The bit is 1 1305 // ZERO The bit is 0 1306 #define LRFDRFE32_EVTCLR1_EVTCLR0_PBECMD 0x00000040U 1307 #define LRFDRFE32_EVTCLR1_EVTCLR0_PBECMD_M 0x00000040U 1308 #define LRFDRFE32_EVTCLR1_EVTCLR0_PBECMD_S 6U 1309 #define LRFDRFE32_EVTCLR1_EVTCLR0_PBECMD_ONE 0x00000040U 1310 #define LRFDRFE32_EVTCLR1_EVTCLR0_PBECMD_ZERO 0x00000000U 1311 1312 // Field: [5] COUNTER 1313 // 1314 // ENUMs: 1315 // ONE The bit is 1 1316 // ZERO The bit is 0 1317 #define LRFDRFE32_EVTCLR1_EVTCLR0_COUNTER 0x00000020U 1318 #define LRFDRFE32_EVTCLR1_EVTCLR0_COUNTER_M 0x00000020U 1319 #define LRFDRFE32_EVTCLR1_EVTCLR0_COUNTER_S 5U 1320 #define LRFDRFE32_EVTCLR1_EVTCLR0_COUNTER_ONE 0x00000020U 1321 #define LRFDRFE32_EVTCLR1_EVTCLR0_COUNTER_ZERO 0x00000000U 1322 1323 // Field: [4] MDMCMD 1324 // 1325 // ENUMs: 1326 // ONE The bit is 1 1327 // ZERO The bit is 0 1328 #define LRFDRFE32_EVTCLR1_EVTCLR0_MDMCMD 0x00000010U 1329 #define LRFDRFE32_EVTCLR1_EVTCLR0_MDMCMD_M 0x00000010U 1330 #define LRFDRFE32_EVTCLR1_EVTCLR0_MDMCMD_S 4U 1331 #define LRFDRFE32_EVTCLR1_EVTCLR0_MDMCMD_ONE 0x00000010U 1332 #define LRFDRFE32_EVTCLR1_EVTCLR0_MDMCMD_ZERO 0x00000000U 1333 1334 // Field: [3] ACC1 1335 // 1336 // ENUMs: 1337 // ONE The bit is 1 1338 // ZERO The bit is 0 1339 #define LRFDRFE32_EVTCLR1_EVTCLR0_ACC1 0x00000008U 1340 #define LRFDRFE32_EVTCLR1_EVTCLR0_ACC1_M 0x00000008U 1341 #define LRFDRFE32_EVTCLR1_EVTCLR0_ACC1_S 3U 1342 #define LRFDRFE32_EVTCLR1_EVTCLR0_ACC1_ONE 0x00000008U 1343 #define LRFDRFE32_EVTCLR1_EVTCLR0_ACC1_ZERO 0x00000000U 1344 1345 // Field: [2] ACC0 1346 // 1347 // ENUMs: 1348 // ONE The bit is 1 1349 // ZERO The bit is 0 1350 #define LRFDRFE32_EVTCLR1_EVTCLR0_ACC0 0x00000004U 1351 #define LRFDRFE32_EVTCLR1_EVTCLR0_ACC0_M 0x00000004U 1352 #define LRFDRFE32_EVTCLR1_EVTCLR0_ACC0_S 2U 1353 #define LRFDRFE32_EVTCLR1_EVTCLR0_ACC0_ONE 0x00000004U 1354 #define LRFDRFE32_EVTCLR1_EVTCLR0_ACC0_ZERO 0x00000000U 1355 1356 // Field: [1] TIMER 1357 // 1358 // ENUMs: 1359 // ONE The bit is 1 1360 // ZERO The bit is 0 1361 #define LRFDRFE32_EVTCLR1_EVTCLR0_TIMER 0x00000002U 1362 #define LRFDRFE32_EVTCLR1_EVTCLR0_TIMER_M 0x00000002U 1363 #define LRFDRFE32_EVTCLR1_EVTCLR0_TIMER_S 1U 1364 #define LRFDRFE32_EVTCLR1_EVTCLR0_TIMER_ONE 0x00000002U 1365 #define LRFDRFE32_EVTCLR1_EVTCLR0_TIMER_ZERO 0x00000000U 1366 1367 // Field: [0] RFEAPI 1368 // 1369 // ENUMs: 1370 // ONE The bit is 1 1371 // ZERO The bit is 0 1372 #define LRFDRFE32_EVTCLR1_EVTCLR0_RFEAPI 0x00000001U 1373 #define LRFDRFE32_EVTCLR1_EVTCLR0_RFEAPI_M 0x00000001U 1374 #define LRFDRFE32_EVTCLR1_EVTCLR0_RFEAPI_S 0U 1375 #define LRFDRFE32_EVTCLR1_EVTCLR0_RFEAPI_ONE 0x00000001U 1376 #define LRFDRFE32_EVTCLR1_EVTCLR0_RFEAPI_ZERO 0x00000000U 1377 1378 //***************************************************************************** 1379 // 1380 // Register: LRFDRFE32_O_HFXTSTAT 1381 // 1382 //***************************************************************************** 1383 // Field: [0] STAT 1384 // 1385 // ENUMs: 1386 // QUAL Clock signal is qualified 1387 // NONQUAL Clock signal is not qualified 1388 #define LRFDRFE32_HFXTSTAT_STAT 0x00000001U 1389 #define LRFDRFE32_HFXTSTAT_STAT_M 0x00000001U 1390 #define LRFDRFE32_HFXTSTAT_STAT_S 0U 1391 #define LRFDRFE32_HFXTSTAT_STAT_QUAL 0x00000001U 1392 #define LRFDRFE32_HFXTSTAT_STAT_NONQUAL 0x00000000U 1393 1394 //***************************************************************************** 1395 // 1396 // Register: LRFDRFE32_O_RFSTATE 1397 // 1398 //***************************************************************************** 1399 // Field: [3:0] VAL 1400 // 1401 // ENUMs: 1402 // RX RX is active 1403 // TX TX is active 1404 // SYNTH Synth is running 1405 // IDLE Radio is idle 1406 #define LRFDRFE32_RFSTATE_VAL_W 4U 1407 #define LRFDRFE32_RFSTATE_VAL_M 0x0000000FU 1408 #define LRFDRFE32_RFSTATE_VAL_S 0U 1409 #define LRFDRFE32_RFSTATE_VAL_RX 0x00000003U 1410 #define LRFDRFE32_RFSTATE_VAL_TX 0x00000002U 1411 #define LRFDRFE32_RFSTATE_VAL_SYNTH 0x00000001U 1412 #define LRFDRFE32_RFSTATE_VAL_IDLE 0x00000000U 1413 1414 //***************************************************************************** 1415 // 1416 // Register: LRFDRFE32_O_CMDPAR0_API 1417 // 1418 //***************************************************************************** 1419 // Field: [31:16] VAL 1420 // 1421 // ENUMs: 1422 // ALLONES All the bits are 1 1423 // ALLZEROS All the bits are 0 1424 #define LRFDRFE32_CMDPAR0_API_VAL_W 16U 1425 #define LRFDRFE32_CMDPAR0_API_VAL_M 0xFFFF0000U 1426 #define LRFDRFE32_CMDPAR0_API_VAL_S 16U 1427 #define LRFDRFE32_CMDPAR0_API_VAL_ALLONES 0xFFFF0000U 1428 #define LRFDRFE32_CMDPAR0_API_VAL_ALLZEROS 0x00000000U 1429 1430 // Field: [7:4] PROTOCOLID 1431 // 1432 // ENUMs: 1433 // ALLONES All the bits are 1 1434 // ALLZEROS All the bits are 0 1435 #define LRFDRFE32_CMDPAR0_API_PROTOCOLID_W 4U 1436 #define LRFDRFE32_CMDPAR0_API_PROTOCOLID_M 0x000000F0U 1437 #define LRFDRFE32_CMDPAR0_API_PROTOCOLID_S 4U 1438 #define LRFDRFE32_CMDPAR0_API_PROTOCOLID_ALLONES 0x000000F0U 1439 #define LRFDRFE32_CMDPAR0_API_PROTOCOLID_ALLZEROS 0x00000000U 1440 1441 // Field: [3:0] RFECMD 1442 // 1443 // ENUMs: 1444 // ALLONES All the bits are 1 1445 // ALLZEROS All bits are 0 1446 #define LRFDRFE32_CMDPAR0_API_RFECMD_W 4U 1447 #define LRFDRFE32_CMDPAR0_API_RFECMD_M 0x0000000FU 1448 #define LRFDRFE32_CMDPAR0_API_RFECMD_S 0U 1449 #define LRFDRFE32_CMDPAR0_API_RFECMD_ALLONES 0x0000000FU 1450 #define LRFDRFE32_CMDPAR0_API_RFECMD_ALLZEROS 0x00000000U 1451 1452 //***************************************************************************** 1453 // 1454 // Register: LRFDRFE32_O_MSGBOX_CMDPAR1 1455 // 1456 //***************************************************************************** 1457 // Field: [23:16] MSGBOX_VAL 1458 // 1459 // ENUMs: 1460 // ALLONES All the bits are 1 1461 // ALLZEROS All the bits are 0 1462 #define LRFDRFE32_MSGBOX_CMDPAR1_MSGBOX_VAL_W 8U 1463 #define LRFDRFE32_MSGBOX_CMDPAR1_MSGBOX_VAL_M 0x00FF0000U 1464 #define LRFDRFE32_MSGBOX_CMDPAR1_MSGBOX_VAL_S 16U 1465 #define LRFDRFE32_MSGBOX_CMDPAR1_MSGBOX_VAL_ALLONES 0x00FF0000U 1466 #define LRFDRFE32_MSGBOX_CMDPAR1_MSGBOX_VAL_ALLZEROS 0x00000000U 1467 1468 // Field: [15:0] CMDPAR1_VAL 1469 // 1470 // ENUMs: 1471 // ALLONES All the bits are 1 1472 // ALLZEROS All the bits are 0 1473 #define LRFDRFE32_MSGBOX_CMDPAR1_CMDPAR1_VAL_W 16U 1474 #define LRFDRFE32_MSGBOX_CMDPAR1_CMDPAR1_VAL_M 0x0000FFFFU 1475 #define LRFDRFE32_MSGBOX_CMDPAR1_CMDPAR1_VAL_S 0U 1476 #define LRFDRFE32_MSGBOX_CMDPAR1_CMDPAR1_VAL_ALLONES 0x0000FFFFU 1477 #define LRFDRFE32_MSGBOX_CMDPAR1_CMDPAR1_VAL_ALLZEROS 0x00000000U 1478 1479 //***************************************************************************** 1480 // 1481 // Register: LRFDRFE32_O_MCEDATIN0_MCEDATOUT0 1482 // 1483 //***************************************************************************** 1484 // Field: [31:16] MCEDATIN0_VAL 1485 // 1486 // ENUMs: 1487 // ALLONES All the bits are 1 1488 // ALLZEROS All the bits are 0 1489 #define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATIN0_VAL_W 16U 1490 #define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATIN0_VAL_M 0xFFFF0000U 1491 #define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATIN0_VAL_S 16U 1492 #define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATIN0_VAL_ALLONES 0xFFFF0000U 1493 #define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATIN0_VAL_ALLZEROS 0x00000000U 1494 1495 // Field: [15:0] MCEDATOUT0_VAL 1496 // 1497 // ENUMs: 1498 // ALLONES All the bits are 1 1499 // ALLZEROS All the bits are 0 1500 #define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATOUT0_VAL_W 16U 1501 #define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATOUT0_VAL_M 0x0000FFFFU 1502 #define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATOUT0_VAL_S 0U 1503 #define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATOUT0_VAL_ALLONES 0x0000FFFFU 1504 #define LRFDRFE32_MCEDATIN0_MCEDATOUT0_MCEDATOUT0_VAL_ALLZEROS 0x00000000U 1505 1506 //***************************************************************************** 1507 // 1508 // Register: LRFDRFE32_O_MCECMDIN_MCECMDOUT 1509 // 1510 //***************************************************************************** 1511 // Field: [19:16] MCECMDIN_VAL 1512 // 1513 // ENUMs: 1514 // ALLONES All the bits are 1 1515 // ALLZEROS All the bits are 0 1516 #define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDIN_VAL_W 4U 1517 #define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDIN_VAL_M 0x000F0000U 1518 #define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDIN_VAL_S 16U 1519 #define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDIN_VAL_ALLONES 0x000F0000U 1520 #define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDIN_VAL_ALLZEROS 0x00000000U 1521 1522 // Field: [3:0] MCECMDOUT_VAL 1523 // 1524 // ENUMs: 1525 // ALLONES All the bits are 1 1526 // ALLZEROS All the bits are 0 1527 #define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDOUT_VAL_W 4U 1528 #define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDOUT_VAL_M 0x0000000FU 1529 #define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDOUT_VAL_S 0U 1530 #define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDOUT_VAL_ALLONES 0x0000000FU 1531 #define LRFDRFE32_MCECMDIN_MCECMDOUT_MCECMDOUT_VAL_ALLZEROS 0x00000000U 1532 1533 //***************************************************************************** 1534 // 1535 // Register: LRFDRFE32_O_PBEDATIN0_PBEDATOUT0 1536 // 1537 //***************************************************************************** 1538 // Field: [31:16] PBEDATIN0_VAL 1539 // 1540 // ENUMs: 1541 // ALLONES All the bits are 1 1542 // ALLZEROS All the bits are 0 1543 #define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_W 16U 1544 #define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_M 0xFFFF0000U 1545 #define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_S 16U 1546 #define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_ALLONES 0xFFFF0000U 1547 #define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATIN0_VAL_ALLZEROS 0x00000000U 1548 1549 // Field: [15:0] PBEDATOUT0_VAL 1550 // 1551 // ENUMs: 1552 // ALLONES All the bits are 1 1553 // ALLZEROS All the bits are 0 1554 #define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_W 16U 1555 #define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_M 0x0000FFFFU 1556 #define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_S 0U 1557 #define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_ALLONES 0x0000FFFFU 1558 #define LRFDRFE32_PBEDATIN0_PBEDATOUT0_PBEDATOUT0_VAL_ALLZEROS 0x00000000U 1559 1560 //***************************************************************************** 1561 // 1562 // Register: LRFDRFE32_O_PBECMDIN_PBECMDOUT 1563 // 1564 //***************************************************************************** 1565 // Field: [19:16] PBECMDIN_VAL 1566 // 1567 // ENUMs: 1568 // ALLONES All the bits are 1 1569 // ALLZEROS All the bits are 0 1570 #define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_W 4U 1571 #define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_M 0x000F0000U 1572 #define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_S 16U 1573 #define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_ALLONES 0x000F0000U 1574 #define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDIN_VAL_ALLZEROS 0x00000000U 1575 1576 // Field: [3:0] PBECMDOUT_VAL 1577 // 1578 // ENUMs: 1579 // ALLONES All the bits are 1 1580 // ALLZEROS All the bits are 0 1581 #define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_W 4U 1582 #define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_M 0x0000000FU 1583 #define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_S 0U 1584 #define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_ALLONES 0x0000000FU 1585 #define LRFDRFE32_PBECMDIN_PBECMDOUT_PBECMDOUT_VAL_ALLZEROS 0x00000000U 1586 1587 //***************************************************************************** 1588 // 1589 // Register: LRFDRFE32_O_STRB 1590 // 1591 //***************************************************************************** 1592 // Field: [7] S2RTRG 1593 // 1594 // ENUMs: 1595 // ONE The bit is 1 1596 // ZERO The bit is 0 1597 #define LRFDRFE32_STRB_S2RTRG 0x00000080U 1598 #define LRFDRFE32_STRB_S2RTRG_M 0x00000080U 1599 #define LRFDRFE32_STRB_S2RTRG_S 7U 1600 #define LRFDRFE32_STRB_S2RTRG_ONE 0x00000080U 1601 #define LRFDRFE32_STRB_S2RTRG_ZERO 0x00000000U 1602 1603 // Field: [6] DMATRG 1604 // 1605 // ENUMs: 1606 // ONE The bit is 1 1607 // ZERO The bit is 0 1608 #define LRFDRFE32_STRB_DMATRG 0x00000040U 1609 #define LRFDRFE32_STRB_DMATRG_M 0x00000040U 1610 #define LRFDRFE32_STRB_DMATRG_S 6U 1611 #define LRFDRFE32_STRB_DMATRG_ONE 0x00000040U 1612 #define LRFDRFE32_STRB_DMATRG_ZERO 0x00000000U 1613 1614 // Field: [5] SYSTCPT2 1615 // 1616 // ENUMs: 1617 // ONE The bit is 1 1618 // ZERO The bit is 0 1619 #define LRFDRFE32_STRB_SYSTCPT2 0x00000020U 1620 #define LRFDRFE32_STRB_SYSTCPT2_M 0x00000020U 1621 #define LRFDRFE32_STRB_SYSTCPT2_S 5U 1622 #define LRFDRFE32_STRB_SYSTCPT2_ONE 0x00000020U 1623 #define LRFDRFE32_STRB_SYSTCPT2_ZERO 0x00000000U 1624 1625 // Field: [4] SYSTCPT1 1626 // 1627 // ENUMs: 1628 // ONE The bit is 1 1629 // ZERO The bit is 0 1630 #define LRFDRFE32_STRB_SYSTCPT1 0x00000010U 1631 #define LRFDRFE32_STRB_SYSTCPT1_M 0x00000010U 1632 #define LRFDRFE32_STRB_SYSTCPT1_S 4U 1633 #define LRFDRFE32_STRB_SYSTCPT1_ONE 0x00000010U 1634 #define LRFDRFE32_STRB_SYSTCPT1_ZERO 0x00000000U 1635 1636 // Field: [3] SYSTCPT0 1637 // 1638 // ENUMs: 1639 // ONE The bit is 1 1640 // ZERO The bit is 0 1641 #define LRFDRFE32_STRB_SYSTCPT0 0x00000008U 1642 #define LRFDRFE32_STRB_SYSTCPT0_M 0x00000008U 1643 #define LRFDRFE32_STRB_SYSTCPT0_S 3U 1644 #define LRFDRFE32_STRB_SYSTCPT0_ONE 0x00000008U 1645 #define LRFDRFE32_STRB_SYSTCPT0_ZERO 0x00000000U 1646 1647 // Field: [2] EVT1 1648 // 1649 // ENUMs: 1650 // ONE The bit is 1 1651 // ZERO The bit is 0 1652 #define LRFDRFE32_STRB_EVT1 0x00000004U 1653 #define LRFDRFE32_STRB_EVT1_M 0x00000004U 1654 #define LRFDRFE32_STRB_EVT1_S 2U 1655 #define LRFDRFE32_STRB_EVT1_ONE 0x00000004U 1656 #define LRFDRFE32_STRB_EVT1_ZERO 0x00000000U 1657 1658 // Field: [1] EVT0 1659 // 1660 // ENUMs: 1661 // ONE The bit is 1 1662 // ZERO The bit is 0 1663 #define LRFDRFE32_STRB_EVT0 0x00000002U 1664 #define LRFDRFE32_STRB_EVT0_M 0x00000002U 1665 #define LRFDRFE32_STRB_EVT0_S 1U 1666 #define LRFDRFE32_STRB_EVT0_ONE 0x00000002U 1667 #define LRFDRFE32_STRB_EVT0_ZERO 0x00000000U 1668 1669 // Field: [0] CMDDONE 1670 // 1671 // ENUMs: 1672 // YES The bit is 1 1673 // NO The bit is 0 1674 #define LRFDRFE32_STRB_CMDDONE 0x00000001U 1675 #define LRFDRFE32_STRB_CMDDONE_M 0x00000001U 1676 #define LRFDRFE32_STRB_CMDDONE_S 0U 1677 #define LRFDRFE32_STRB_CMDDONE_YES 0x00000001U 1678 #define LRFDRFE32_STRB_CMDDONE_NO 0x00000000U 1679 1680 //***************************************************************************** 1681 // 1682 // Register: LRFDRFE32_O_MAGNTHR_MAGNTHRCFG 1683 // 1684 //***************************************************************************** 1685 // Field: [23:16] VAL 1686 // 1687 // ENUMs: 1688 // ALLONES All the bits are 1 1689 // ALLZEROS All the bits are 0 1690 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_VAL_W 8U 1691 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_VAL_M 0x00FF0000U 1692 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_VAL_S 16U 1693 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_VAL_ALLONES 0x00FF0000U 1694 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_VAL_ALLZEROS 0x00000000U 1695 1696 // Field: [1] SEL 1697 // 1698 // ENUMs: 1699 // MAGNACC1 Use MAGNACC1 in the compare against the theshold 1700 // in MANGTHR 1701 // MAGNACC0 Use MAGNACC0 in the compare against the theshold 1702 // in MANGTHR 1703 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_SEL 0x00000002U 1704 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_SEL_M 0x00000002U 1705 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_SEL_S 1U 1706 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_SEL_MAGNACC1 0x00000002U 1707 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_SEL_MAGNACC0 0x00000000U 1708 1709 // Field: [0] CTL 1710 // 1711 // ENUMs: 1712 // EN Enable automatic comparison of magntude with 1713 // threshold (input of lin2log is driven by HW) 1714 // DIS Disable automatic comparison with threshold (input 1715 // of lin2log is driven by FW) 1716 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_CTL 0x00000001U 1717 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_CTL_M 0x00000001U 1718 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_CTL_S 0U 1719 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_CTL_EN 0x00000001U 1720 #define LRFDRFE32_MAGNTHR_MAGNTHRCFG_CTL_DIS 0x00000000U 1721 1722 //***************************************************************************** 1723 // 1724 // Register: LRFDRFE32_O_GAINCTL_RSSIOFFSET 1725 // 1726 //***************************************************************************** 1727 // Field: [19:18] BDE2DVGA 1728 // 1729 // ENUMs: 1730 // GAIN8 Gain 8 1731 // GAIN4 Gain 4 1732 // GAIN2 Gain 2 1733 // GAIN1 Gain 1 1734 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_W 2U 1735 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_M 0x000C0000U 1736 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_S 18U 1737 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_GAIN8 0x000C0000U 1738 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_GAIN4 0x00080000U 1739 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_GAIN2 0x00040000U 1740 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE2DVGA_GAIN1 0x00000000U 1741 1742 // Field: [17:16] BDE1DVGA 1743 // 1744 // ENUMs: 1745 // GAIN8 Gain 8 1746 // GAIN4 Gain 4 1747 // GAIN2 Gain 2 1748 // GAIN1 Gain 1 1749 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_W 2U 1750 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_M 0x00030000U 1751 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_S 16U 1752 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_GAIN8 0x00030000U 1753 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_GAIN4 0x00020000U 1754 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_GAIN2 0x00010000U 1755 #define LRFDRFE32_GAINCTL_RSSIOFFSET_BDE1DVGA_GAIN1 0x00000000U 1756 1757 // Field: [7:0] VAL 1758 // 1759 // ENUMs: 1760 // ALLONES All the bits are 1 1761 // ALLZEROS All the bits are 0 1762 #define LRFDRFE32_GAINCTL_RSSIOFFSET_VAL_W 8U 1763 #define LRFDRFE32_GAINCTL_RSSIOFFSET_VAL_M 0x000000FFU 1764 #define LRFDRFE32_GAINCTL_RSSIOFFSET_VAL_S 0U 1765 #define LRFDRFE32_GAINCTL_RSSIOFFSET_VAL_ALLONES 0x000000FFU 1766 #define LRFDRFE32_GAINCTL_RSSIOFFSET_VAL_ALLZEROS 0x00000000U 1767 1768 //***************************************************************************** 1769 // 1770 // Register: LRFDRFE32_O_MAGNCTL1_MAGNCTL0 1771 // 1772 //***************************************************************************** 1773 // Field: [28] MAGNCTL1_PERMODE 1774 // 1775 // ENUMs: 1776 // PERIODIC Periodic mode 1777 // ONESHOT One-shot mode 1778 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PERMODE 0x10000000U 1779 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PERMODE_M 0x10000000U 1780 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PERMODE_S 28U 1781 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PERMODE_PERIODIC 0x10000000U 1782 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PERMODE_ONESHOT 0x00000000U 1783 1784 // Field: [27:24] MAGNCTL1_SCL 1785 // 1786 // ENUMs: 1787 // DIV256 1/256 1788 // DIV128 1/128 1789 // DIV64 1/64 1790 // DIV32 1/32 1791 // DIV16 1/16 1792 // DIV8 1793 // DIV4 1794 // DIV2 1795 // DIV1 1/1 (no scaling) 1796 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_W 4U 1797 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_M 0x0F000000U 1798 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_S 24U 1799 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV256 0x08000000U 1800 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV128 0x07000000U 1801 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV64 0x06000000U 1802 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV32 0x05000000U 1803 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV16 0x04000000U 1804 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV8 0x03000000U 1805 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV4 0x02000000U 1806 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV2 0x01000000U 1807 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_SCL_DIV1 0x00000000U 1808 1809 // Field: [23:16] MAGNCTL1_PER 1810 // 1811 // ENUMs: 1812 // ALLONES All the bits are 1 1813 // ALLZEROS All the bits are 0 1814 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PER_W 8U 1815 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PER_M 0x00FF0000U 1816 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PER_S 16U 1817 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PER_ALLONES 0x00FF0000U 1818 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL1_PER_ALLZEROS 0x00000000U 1819 1820 // Field: [12] MAGNCTL0_PERMODE 1821 // 1822 // ENUMs: 1823 // PERIODIC Periodic mode 1824 // ONESHOT One-shot mode 1825 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PERMODE 0x00001000U 1826 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PERMODE_M 0x00001000U 1827 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PERMODE_S 12U 1828 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PERMODE_PERIODIC 0x00001000U 1829 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PERMODE_ONESHOT 0x00000000U 1830 1831 // Field: [11:8] MAGNCTL0_SCL 1832 // 1833 // ENUMs: 1834 // DIV256 1/256 1835 // DIV128 1/128 1836 // DIV64 1/64 1837 // DIV32 1/32 1838 // DIV16 1/16 1839 // DIV8 1840 // DIV4 1841 // DIV2 1842 // DIV1 1/1 (no scaling) 1843 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_W 4U 1844 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_M 0x00000F00U 1845 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_S 8U 1846 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV256 0x00000800U 1847 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV128 0x00000700U 1848 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV64 0x00000600U 1849 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV32 0x00000500U 1850 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV16 0x00000400U 1851 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV8 0x00000300U 1852 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV4 0x00000200U 1853 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV2 0x00000100U 1854 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_SCL_DIV1 0x00000000U 1855 1856 // Field: [7:0] MAGNCTL0_PER 1857 // 1858 // ENUMs: 1859 // ALLONES All the bits are 1 1860 // ALLZEROS All the bits are 0 1861 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PER_W 8U 1862 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PER_M 0x000000FFU 1863 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PER_S 0U 1864 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PER_ALLONES 0x000000FFU 1865 #define LRFDRFE32_MAGNCTL1_MAGNCTL0_MAGNCTL0_PER_ALLZEROS 0x00000000U 1866 1867 //***************************************************************************** 1868 // 1869 // Register: LRFDRFE32_O_SPARE1_SPARE0 1870 // 1871 //***************************************************************************** 1872 // Field: [31:16] SPARE1_VAL 1873 // 1874 // ENUMs: 1875 // ALLONES All the bits are 1 1876 // ALLZEROS All the bits are 0 1877 #define LRFDRFE32_SPARE1_SPARE0_SPARE1_VAL_W 16U 1878 #define LRFDRFE32_SPARE1_SPARE0_SPARE1_VAL_M 0xFFFF0000U 1879 #define LRFDRFE32_SPARE1_SPARE0_SPARE1_VAL_S 16U 1880 #define LRFDRFE32_SPARE1_SPARE0_SPARE1_VAL_ALLONES 0xFFFF0000U 1881 #define LRFDRFE32_SPARE1_SPARE0_SPARE1_VAL_ALLZEROS 0x00000000U 1882 1883 // Field: [15:0] SPARE0_VAL 1884 // 1885 // ENUMs: 1886 // ALLONES All the bits are 1 1887 // ALLZEROS All the bits are 0 1888 #define LRFDRFE32_SPARE1_SPARE0_SPARE0_VAL_W 16U 1889 #define LRFDRFE32_SPARE1_SPARE0_SPARE0_VAL_M 0x0000FFFFU 1890 #define LRFDRFE32_SPARE1_SPARE0_SPARE0_VAL_S 0U 1891 #define LRFDRFE32_SPARE1_SPARE0_SPARE0_VAL_ALLONES 0x0000FFFFU 1892 #define LRFDRFE32_SPARE1_SPARE0_SPARE0_VAL_ALLZEROS 0x00000000U 1893 1894 //***************************************************************************** 1895 // 1896 // Register: LRFDRFE32_O_SPARE3_SPARE2 1897 // 1898 //***************************************************************************** 1899 // Field: [31:16] SPARE3_VAL 1900 // 1901 // ENUMs: 1902 // ALLONES All the bits are 1 1903 // ALLZEROS All the bits are 0 1904 #define LRFDRFE32_SPARE3_SPARE2_SPARE3_VAL_W 16U 1905 #define LRFDRFE32_SPARE3_SPARE2_SPARE3_VAL_M 0xFFFF0000U 1906 #define LRFDRFE32_SPARE3_SPARE2_SPARE3_VAL_S 16U 1907 #define LRFDRFE32_SPARE3_SPARE2_SPARE3_VAL_ALLONES 0xFFFF0000U 1908 #define LRFDRFE32_SPARE3_SPARE2_SPARE3_VAL_ALLZEROS 0x00000000U 1909 1910 // Field: [15:0] SPARE2_VAL 1911 // 1912 // ENUMs: 1913 // ALLONES All the bits are 1 1914 // ALLZEROS All the bits are 0 1915 #define LRFDRFE32_SPARE3_SPARE2_SPARE2_VAL_W 16U 1916 #define LRFDRFE32_SPARE3_SPARE2_SPARE2_VAL_M 0x0000FFFFU 1917 #define LRFDRFE32_SPARE3_SPARE2_SPARE2_VAL_S 0U 1918 #define LRFDRFE32_SPARE3_SPARE2_SPARE2_VAL_ALLONES 0x0000FFFFU 1919 #define LRFDRFE32_SPARE3_SPARE2_SPARE2_VAL_ALLZEROS 0x00000000U 1920 1921 //***************************************************************************** 1922 // 1923 // Register: LRFDRFE32_O_SPARE5_SPARE4 1924 // 1925 //***************************************************************************** 1926 // Field: [31:16] SPARE5_VAL 1927 // 1928 // ENUMs: 1929 // ALLONES All the bits are 1 1930 // ALLZEROS All the bits are 0 1931 #define LRFDRFE32_SPARE5_SPARE4_SPARE5_VAL_W 16U 1932 #define LRFDRFE32_SPARE5_SPARE4_SPARE5_VAL_M 0xFFFF0000U 1933 #define LRFDRFE32_SPARE5_SPARE4_SPARE5_VAL_S 16U 1934 #define LRFDRFE32_SPARE5_SPARE4_SPARE5_VAL_ALLONES 0xFFFF0000U 1935 #define LRFDRFE32_SPARE5_SPARE4_SPARE5_VAL_ALLZEROS 0x00000000U 1936 1937 // Field: [15:0] SPARE4_VAL 1938 // 1939 // ENUMs: 1940 // ALLONES All the bits are 1 1941 // ALLZEROS All the bits are 0 1942 #define LRFDRFE32_SPARE5_SPARE4_SPARE4_VAL_W 16U 1943 #define LRFDRFE32_SPARE5_SPARE4_SPARE4_VAL_M 0x0000FFFFU 1944 #define LRFDRFE32_SPARE5_SPARE4_SPARE4_VAL_S 0U 1945 #define LRFDRFE32_SPARE5_SPARE4_SPARE4_VAL_ALLONES 0x0000FFFFU 1946 #define LRFDRFE32_SPARE5_SPARE4_SPARE4_VAL_ALLZEROS 0x00000000U 1947 1948 //***************************************************************************** 1949 // 1950 // Register: LRFDRFE32_O_IFAMPRFLDO_LNA 1951 // 1952 //***************************************************************************** 1953 // Field: [31:25] IFAMPRFLDO_TRIM 1954 // 1955 // ENUMs: 1956 // BYPASS Regulator is in bypass mode 1957 // MAX Maximum output voltage 1958 // MIN Minimum output voltage 1959 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_TRIM_W 7U 1960 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_TRIM_M 0xFE000000U 1961 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_TRIM_S 25U 1962 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_TRIM_BYPASS 0xFE000000U 1963 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_TRIM_MAX 0xFC000000U 1964 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_TRIM_MIN 0x00000000U 1965 1966 // Field: [24] IFAMPRFLDO_EN 1967 // 1968 // ENUMs: 1969 // EN Enable regulator 1970 // DIS Disable regulator 1971 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_EN 0x01000000U 1972 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_EN_M 0x01000000U 1973 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_EN_S 24U 1974 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_EN_EN 0x01000000U 1975 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_EN_DIS 0x00000000U 1976 1977 // Field: [23:20] IFAMPRFLDO_AAFCAP 1978 // 1979 // ENUMs: 1980 // MAX Largest capacitance on IFAMP output. Low BW 1981 // MIN Smallest capacitance on IFAMP output. High BW. 1982 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_AAFCAP_W 4U 1983 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_AAFCAP_M 0x00F00000U 1984 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_AAFCAP_S 20U 1985 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_AAFCAP_MAX 0x00F00000U 1986 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_AAFCAP_MIN 0x00000000U 1987 1988 // Field: [19:17] IFAMPRFLDO_IFAMPIB 1989 // 1990 // ENUMs: 1991 // MAX Max IB 1992 // MIN Minimum IB 1993 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMPIB_W 3U 1994 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMPIB_M 0x000E0000U 1995 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMPIB_S 17U 1996 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMPIB_MAX 0x000E0000U 1997 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMPIB_MIN 0x00000000U 1998 1999 // Field: [16] IFAMPRFLDO_IFAMP 2000 // 2001 // ENUMs: 2002 // EN Enable IFAMP 2003 // DIS Disable IFAMP 2004 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMP 0x00010000U 2005 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMP_M 0x00010000U 2006 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMP_S 16U 2007 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMP_EN 0x00010000U 2008 #define LRFDRFE32_IFAMPRFLDO_LNA_IFAMPRFLDO_IFAMP_DIS 0x00000000U 2009 2010 // Field: [15:8] LNA_SPARE 2011 // 2012 // ENUMs: 2013 // EN Enable IFAMP 2014 // DIS Disable IFAMP 2015 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_SPARE_W 8U 2016 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_SPARE_M 0x0000FF00U 2017 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_SPARE_S 8U 2018 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_SPARE_EN 0x00000100U 2019 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_SPARE_DIS 0x00000000U 2020 2021 // Field: [7:4] LNA_TRIM 2022 // 2023 // ENUMs: 2024 // ONES All bits are one 2025 // ZEROS All bits are zero 2026 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_TRIM_W 4U 2027 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_TRIM_M 0x000000F0U 2028 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_TRIM_S 4U 2029 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_TRIM_ONES 0x000000F0U 2030 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_TRIM_ZEROS 0x00000000U 2031 2032 // Field: [3] LNA_BIAS 2033 // 2034 // ENUMs: 2035 // INT IPTAT bias currents are from bias circuit inside 2036 // LRF_FRONTEND 2037 // BGAP IPTAT bias currents are from bandgap 2038 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_BIAS 0x00000008U 2039 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_BIAS_M 0x00000008U 2040 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_BIAS_S 3U 2041 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_BIAS_INT 0x00000008U 2042 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_BIAS_BGAP 0x00000000U 2043 2044 // Field: [2:1] LNA_IB 2045 // 2046 // ENUMs: 2047 // MAX Maximum IB 2048 // MIN Minimum IB 2049 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_IB_W 2U 2050 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_IB_M 0x00000006U 2051 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_IB_S 1U 2052 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_IB_MAX 0x00000006U 2053 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_IB_MIN 0x00000000U 2054 2055 // Field: [0] LNA_EN 2056 // 2057 // ENUMs: 2058 // ON Enable LNA 2059 // OFF Disable LNA 2060 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_EN 0x00000001U 2061 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_EN_M 0x00000001U 2062 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_EN_S 0U 2063 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_EN_ON 0x00000001U 2064 #define LRFDRFE32_IFAMPRFLDO_LNA_LNA_EN_OFF 0x00000000U 2065 2066 //***************************************************************************** 2067 // 2068 // Register: LRFDRFE32_O_PA1_PA0 2069 // 2070 //***************************************************************************** 2071 // Field: [31:23] SPARE 2072 // 2073 // ENUMs: 2074 // MAX Longest ramp time 2075 // MIN Shortest ramp time 2076 #define LRFDRFE32_PA1_PA0_SPARE_W 9U 2077 #define LRFDRFE32_PA1_PA0_SPARE_M 0xFF800000U 2078 #define LRFDRFE32_PA1_PA0_SPARE_S 23U 2079 #define LRFDRFE32_PA1_PA0_SPARE_MAX 0x01800000U 2080 #define LRFDRFE32_PA1_PA0_SPARE_MIN 0x00000000U 2081 2082 // Field: [22] MIXATST 2083 // 2084 // ENUMs: 2085 // EN Mixers are available on ATEST 2086 // DIS Mixers are not available on ATEST 2087 #define LRFDRFE32_PA1_PA0_MIXATST 0x00400000U 2088 #define LRFDRFE32_PA1_PA0_MIXATST_M 0x00400000U 2089 #define LRFDRFE32_PA1_PA0_MIXATST_S 22U 2090 #define LRFDRFE32_PA1_PA0_MIXATST_EN 0x00400000U 2091 #define LRFDRFE32_PA1_PA0_MIXATST_DIS 0x00000000U 2092 2093 // Field: [21] LDOITST 2094 // 2095 // ENUMs: 2096 // EN Current test signal is available through ITEST 2097 // DIS Current test signal not available through ITEST 2098 #define LRFDRFE32_PA1_PA0_LDOITST 0x00200000U 2099 #define LRFDRFE32_PA1_PA0_LDOITST_M 0x00200000U 2100 #define LRFDRFE32_PA1_PA0_LDOITST_S 21U 2101 #define LRFDRFE32_PA1_PA0_LDOITST_EN 0x00200000U 2102 #define LRFDRFE32_PA1_PA0_LDOITST_DIS 0x00000000U 2103 2104 // Field: [20] LDOATST 2105 // 2106 // ENUMs: 2107 // EN LDO output voltage is available through ATEST 2108 // DIS LDO output voltage not available through ATEST 2109 #define LRFDRFE32_PA1_PA0_LDOATST 0x00100000U 2110 #define LRFDRFE32_PA1_PA0_LDOATST_M 0x00100000U 2111 #define LRFDRFE32_PA1_PA0_LDOATST_S 20U 2112 #define LRFDRFE32_PA1_PA0_LDOATST_EN 0x00100000U 2113 #define LRFDRFE32_PA1_PA0_LDOATST_DIS 0x00000000U 2114 2115 // Field: [19:18] RC 2116 // 2117 // ENUMs: 2118 // MAX Longest ramp time 2119 // MIN Shortest ramp time 2120 #define LRFDRFE32_PA1_PA0_RC_W 2U 2121 #define LRFDRFE32_PA1_PA0_RC_M 0x000C0000U 2122 #define LRFDRFE32_PA1_PA0_RC_S 18U 2123 #define LRFDRFE32_PA1_PA0_RC_MAX 0x000C0000U 2124 #define LRFDRFE32_PA1_PA0_RC_MIN 0x00000000U 2125 2126 // Field: [17] RAMP 2127 // 2128 // ENUMs: 2129 // UP Ramp up 2130 // DOWN Ramp down 2131 #define LRFDRFE32_PA1_PA0_RAMP 0x00020000U 2132 #define LRFDRFE32_PA1_PA0_RAMP_M 0x00020000U 2133 #define LRFDRFE32_PA1_PA0_RAMP_S 17U 2134 #define LRFDRFE32_PA1_PA0_RAMP_UP 0x00020000U 2135 #define LRFDRFE32_PA1_PA0_RAMP_DOWN 0x00000000U 2136 2137 // Field: [16] EN 2138 // 2139 // ENUMs: 2140 // EN Enable PA 2141 // DIS Disable PA 2142 #define LRFDRFE32_PA1_PA0_EN 0x00010000U 2143 #define LRFDRFE32_PA1_PA0_EN_M 0x00010000U 2144 #define LRFDRFE32_PA1_PA0_EN_S 16U 2145 #define LRFDRFE32_PA1_PA0_EN_EN 0x00010000U 2146 #define LRFDRFE32_PA1_PA0_EN_DIS 0x00000000U 2147 2148 // Field: [15] SPARE15 2149 // 2150 // ENUMs: 2151 // ONE Bit is one 2152 // ZERO Bit is 0 2153 #define LRFDRFE32_PA1_PA0_SPARE15 0x00008000U 2154 #define LRFDRFE32_PA1_PA0_SPARE15_M 0x00008000U 2155 #define LRFDRFE32_PA1_PA0_SPARE15_S 15U 2156 #define LRFDRFE32_PA1_PA0_SPARE15_ONE 0x00008000U 2157 #define LRFDRFE32_PA1_PA0_SPARE15_ZERO 0x00000000U 2158 2159 // Field: [14] MODE 2160 // 2161 // ENUMs: 2162 // HIGH High power mode, max 8 dBm 2163 // LOW Low power mode, max 3 dBm 2164 #define LRFDRFE32_PA1_PA0_MODE 0x00004000U 2165 #define LRFDRFE32_PA1_PA0_MODE_M 0x00004000U 2166 #define LRFDRFE32_PA1_PA0_MODE_S 14U 2167 #define LRFDRFE32_PA1_PA0_MODE_HIGH 0x00004000U 2168 #define LRFDRFE32_PA1_PA0_MODE_LOW 0x00000000U 2169 2170 // Field: [13:11] GAIN 2171 // 2172 // ENUMs: 2173 // MAX Maximum gain 2174 // MIN Minimum gain 2175 #define LRFDRFE32_PA1_PA0_GAIN_W 3U 2176 #define LRFDRFE32_PA1_PA0_GAIN_M 0x00003800U 2177 #define LRFDRFE32_PA1_PA0_GAIN_S 11U 2178 #define LRFDRFE32_PA1_PA0_GAIN_MAX 0x00003800U 2179 #define LRFDRFE32_PA1_PA0_GAIN_MIN 0x00000000U 2180 2181 // Field: [10:5] IB 2182 // 2183 // ENUMs: 2184 // MAX Maximum output power 2185 // MIN Minimum output power 2186 #define LRFDRFE32_PA1_PA0_IB_W 6U 2187 #define LRFDRFE32_PA1_PA0_IB_M 0x000007E0U 2188 #define LRFDRFE32_PA1_PA0_IB_S 5U 2189 #define LRFDRFE32_PA1_PA0_IB_MAX 0x000007E0U 2190 #define LRFDRFE32_PA1_PA0_IB_MIN 0x00000000U 2191 2192 // Field: [4:0] TRIM 2193 // 2194 // ENUMs: 2195 // MAX Maximum bias current 2196 // MIN Minimum bias current 2197 #define LRFDRFE32_PA1_PA0_TRIM_W 5U 2198 #define LRFDRFE32_PA1_PA0_TRIM_M 0x0000001FU 2199 #define LRFDRFE32_PA1_PA0_TRIM_S 0U 2200 #define LRFDRFE32_PA1_PA0_TRIM_MAX 0x0000001FU 2201 #define LRFDRFE32_PA1_PA0_TRIM_MIN 0x00000000U 2202 2203 //***************************************************************************** 2204 // 2205 // Register: LRFDRFE32_O_IFADC0_ULNA 2206 // 2207 //***************************************************************************** 2208 // Field: [31] EXTCLK 2209 // 2210 // ENUMs: 2211 // EN The bit is 1 2212 // DIS The bit is 0 2213 #define LRFDRFE32_IFADC0_ULNA_EXTCLK 0x80000000U 2214 #define LRFDRFE32_IFADC0_ULNA_EXTCLK_M 0x80000000U 2215 #define LRFDRFE32_IFADC0_ULNA_EXTCLK_S 31U 2216 #define LRFDRFE32_IFADC0_ULNA_EXTCLK_EN 0x80000000U 2217 #define LRFDRFE32_IFADC0_ULNA_EXTCLK_DIS 0x00000000U 2218 2219 // Field: [30:28] DITHERTRIM 2220 // 2221 // ENUMs: 2222 // ONES All the bits are 1 2223 // ZEROS All the bits are 0 2224 #define LRFDRFE32_IFADC0_ULNA_DITHERTRIM_W 3U 2225 #define LRFDRFE32_IFADC0_ULNA_DITHERTRIM_M 0x70000000U 2226 #define LRFDRFE32_IFADC0_ULNA_DITHERTRIM_S 28U 2227 #define LRFDRFE32_IFADC0_ULNA_DITHERTRIM_ONES 0x70000000U 2228 #define LRFDRFE32_IFADC0_ULNA_DITHERTRIM_ZEROS 0x00000000U 2229 2230 // Field: [27:26] DITHEREN 2231 // 2232 // ENUMs: 2233 // ENG All the bits are 1 2234 // ENSD All the bits are 1 2235 // ENS All the bits are 1 2236 // DIS All the bits are 0 2237 #define LRFDRFE32_IFADC0_ULNA_DITHEREN_W 2U 2238 #define LRFDRFE32_IFADC0_ULNA_DITHEREN_M 0x0C000000U 2239 #define LRFDRFE32_IFADC0_ULNA_DITHEREN_S 26U 2240 #define LRFDRFE32_IFADC0_ULNA_DITHEREN_ENG 0x0C000000U 2241 #define LRFDRFE32_IFADC0_ULNA_DITHEREN_ENSD 0x08000000U 2242 #define LRFDRFE32_IFADC0_ULNA_DITHEREN_ENS 0x04000000U 2243 #define LRFDRFE32_IFADC0_ULNA_DITHEREN_DIS 0x00000000U 2244 2245 // Field: [25] ADCIEN 2246 // 2247 // ENUMs: 2248 // EN The bit is 1 2249 // DIS The bit is 0 2250 #define LRFDRFE32_IFADC0_ULNA_ADCIEN 0x02000000U 2251 #define LRFDRFE32_IFADC0_ULNA_ADCIEN_M 0x02000000U 2252 #define LRFDRFE32_IFADC0_ULNA_ADCIEN_S 25U 2253 #define LRFDRFE32_IFADC0_ULNA_ADCIEN_EN 0x02000000U 2254 #define LRFDRFE32_IFADC0_ULNA_ADCIEN_DIS 0x00000000U 2255 2256 // Field: [24] ADCQEN 2257 // 2258 // ENUMs: 2259 // EN The bit is 1 2260 // DIS The bit is 0 2261 #define LRFDRFE32_IFADC0_ULNA_ADCQEN 0x01000000U 2262 #define LRFDRFE32_IFADC0_ULNA_ADCQEN_M 0x01000000U 2263 #define LRFDRFE32_IFADC0_ULNA_ADCQEN_S 24U 2264 #define LRFDRFE32_IFADC0_ULNA_ADCQEN_EN 0x01000000U 2265 #define LRFDRFE32_IFADC0_ULNA_ADCQEN_DIS 0x00000000U 2266 2267 // Field: [23:20] INT2ADJ 2268 // 2269 // ENUMs: 2270 // ONES All the bits are 1 2271 // ZEROS All the bits are 0 2272 #define LRFDRFE32_IFADC0_ULNA_INT2ADJ_W 4U 2273 #define LRFDRFE32_IFADC0_ULNA_INT2ADJ_M 0x00F00000U 2274 #define LRFDRFE32_IFADC0_ULNA_INT2ADJ_S 20U 2275 #define LRFDRFE32_IFADC0_ULNA_INT2ADJ_ONES 0x00F00000U 2276 #define LRFDRFE32_IFADC0_ULNA_INT2ADJ_ZEROS 0x00000000U 2277 2278 // Field: [19:18] AAFCAP 2279 // 2280 // ENUMs: 2281 // ENG All the bits are 1 2282 // ENSD All the bits are 1 2283 // ENS All the bits are 1 2284 // DIS All the bits are 0 2285 #define LRFDRFE32_IFADC0_ULNA_AAFCAP_W 2U 2286 #define LRFDRFE32_IFADC0_ULNA_AAFCAP_M 0x000C0000U 2287 #define LRFDRFE32_IFADC0_ULNA_AAFCAP_S 18U 2288 #define LRFDRFE32_IFADC0_ULNA_AAFCAP_ENG 0x000C0000U 2289 #define LRFDRFE32_IFADC0_ULNA_AAFCAP_ENSD 0x00080000U 2290 #define LRFDRFE32_IFADC0_ULNA_AAFCAP_ENS 0x00040000U 2291 #define LRFDRFE32_IFADC0_ULNA_AAFCAP_DIS 0x00000000U 2292 2293 // Field: [15:0] SPARE 2294 // 2295 // ENUMs: 2296 // ALLONES All the bits are 1 2297 // ALLZEROS All the bits are 0 2298 #define LRFDRFE32_IFADC0_ULNA_SPARE_W 16U 2299 #define LRFDRFE32_IFADC0_ULNA_SPARE_M 0x0000FFFFU 2300 #define LRFDRFE32_IFADC0_ULNA_SPARE_S 0U 2301 #define LRFDRFE32_IFADC0_ULNA_SPARE_ALLONES 0x0000FFFFU 2302 #define LRFDRFE32_IFADC0_ULNA_SPARE_ALLZEROS 0x00000000U 2303 2304 //***************************************************************************** 2305 // 2306 // Register: LRFDRFE32_O_IFADCLF_IFADC1 2307 // 2308 //***************************************************************************** 2309 // Field: [31:28] FF3 2310 // 2311 // ENUMs: 2312 // ONES All the bits are 1 2313 // ZEROS All the bits are 0 2314 #define LRFDRFE32_IFADCLF_IFADC1_FF3_W 4U 2315 #define LRFDRFE32_IFADCLF_IFADC1_FF3_M 0xF0000000U 2316 #define LRFDRFE32_IFADCLF_IFADC1_FF3_S 28U 2317 #define LRFDRFE32_IFADCLF_IFADC1_FF3_ONES 0xF0000000U 2318 #define LRFDRFE32_IFADCLF_IFADC1_FF3_ZEROS 0x00000000U 2319 2320 // Field: [27:24] FF2 2321 // 2322 // ENUMs: 2323 // ONES All the bits are 1 2324 // ZEROS All the bits are 0 2325 #define LRFDRFE32_IFADCLF_IFADC1_FF2_W 4U 2326 #define LRFDRFE32_IFADCLF_IFADC1_FF2_M 0x0F000000U 2327 #define LRFDRFE32_IFADCLF_IFADC1_FF2_S 24U 2328 #define LRFDRFE32_IFADCLF_IFADC1_FF2_ONES 0x0F000000U 2329 #define LRFDRFE32_IFADCLF_IFADC1_FF2_ZEROS 0x00000000U 2330 2331 // Field: [23:20] FF1 2332 // 2333 // ENUMs: 2334 // ONES All the bits are 1 2335 // ZEROS All the bits are 0 2336 #define LRFDRFE32_IFADCLF_IFADC1_FF1_W 4U 2337 #define LRFDRFE32_IFADCLF_IFADC1_FF1_M 0x00F00000U 2338 #define LRFDRFE32_IFADCLF_IFADC1_FF1_S 20U 2339 #define LRFDRFE32_IFADCLF_IFADC1_FF1_ONES 0x00F00000U 2340 #define LRFDRFE32_IFADCLF_IFADC1_FF1_ZEROS 0x00000000U 2341 2342 // Field: [19:16] INT3 2343 // 2344 // ENUMs: 2345 // ONES All the bits are 1 2346 // ZEROS All the bits are 0 2347 #define LRFDRFE32_IFADCLF_IFADC1_INT3_W 4U 2348 #define LRFDRFE32_IFADCLF_IFADC1_INT3_M 0x000F0000U 2349 #define LRFDRFE32_IFADCLF_IFADC1_INT3_S 16U 2350 #define LRFDRFE32_IFADCLF_IFADC1_INT3_ONES 0x000F0000U 2351 #define LRFDRFE32_IFADCLF_IFADC1_INT3_ZEROS 0x00000000U 2352 2353 // Field: [15] NRZ 2354 // 2355 // ENUMs: 2356 // EN The feedback DAC uses NRZ mode. (Default) 2357 // DIS The feedback DAC uses RZ mode 2358 #define LRFDRFE32_IFADCLF_IFADC1_NRZ 0x00008000U 2359 #define LRFDRFE32_IFADCLF_IFADC1_NRZ_M 0x00008000U 2360 #define LRFDRFE32_IFADCLF_IFADC1_NRZ_S 15U 2361 #define LRFDRFE32_IFADCLF_IFADC1_NRZ_EN 0x00008000U 2362 #define LRFDRFE32_IFADCLF_IFADC1_NRZ_DIS 0x00000000U 2363 2364 // Field: [14:9] TRIM 2365 // 2366 // ENUMs: 2367 // ONES All the bits are 1 2368 // ZEROS All the bits are 0 2369 #define LRFDRFE32_IFADCLF_IFADC1_TRIM_W 6U 2370 #define LRFDRFE32_IFADCLF_IFADC1_TRIM_M 0x00007E00U 2371 #define LRFDRFE32_IFADCLF_IFADC1_TRIM_S 9U 2372 #define LRFDRFE32_IFADCLF_IFADC1_TRIM_ONES 0x00007E00U 2373 #define LRFDRFE32_IFADCLF_IFADC1_TRIM_ZEROS 0x00000000U 2374 2375 // Field: [7] RSTN 2376 // 2377 // ENUMs: 2378 // DIS DTCs are not reset 2379 // EN DTCs are reset 2380 #define LRFDRFE32_IFADCLF_IFADC1_RSTN 0x00000080U 2381 #define LRFDRFE32_IFADCLF_IFADC1_RSTN_M 0x00000080U 2382 #define LRFDRFE32_IFADCLF_IFADC1_RSTN_S 7U 2383 #define LRFDRFE32_IFADCLF_IFADC1_RSTN_DIS 0x00000080U 2384 #define LRFDRFE32_IFADCLF_IFADC1_RSTN_EN 0x00000000U 2385 2386 // Field: [6] CLKGEN 2387 // 2388 // ENUMs: 2389 // EN Internal clock generator module is enabled 2390 // DIS Internal clock generator module is disabled 2391 #define LRFDRFE32_IFADCLF_IFADC1_CLKGEN 0x00000040U 2392 #define LRFDRFE32_IFADCLF_IFADC1_CLKGEN_M 0x00000040U 2393 #define LRFDRFE32_IFADCLF_IFADC1_CLKGEN_S 6U 2394 #define LRFDRFE32_IFADCLF_IFADC1_CLKGEN_EN 0x00000040U 2395 #define LRFDRFE32_IFADCLF_IFADC1_CLKGEN_DIS 0x00000000U 2396 2397 // Field: [5] ADCDIGCLK 2398 // 2399 // ENUMs: 2400 // EN Clock to decimator enabled 2401 // DIS Clock to decimator disabled 2402 #define LRFDRFE32_IFADCLF_IFADC1_ADCDIGCLK 0x00000020U 2403 #define LRFDRFE32_IFADCLF_IFADC1_ADCDIGCLK_M 0x00000020U 2404 #define LRFDRFE32_IFADCLF_IFADC1_ADCDIGCLK_S 5U 2405 #define LRFDRFE32_IFADCLF_IFADC1_ADCDIGCLK_EN 0x00000020U 2406 #define LRFDRFE32_IFADCLF_IFADC1_ADCDIGCLK_DIS 0x00000000U 2407 2408 // Field: [4] ADCLFSROUT 2409 // 2410 // ENUMs: 2411 // EN The LFSR test output is connected to the ADC 2412 // output 2413 // DIS The quantizer output is connected to the ADC 2414 // output 2415 #define LRFDRFE32_IFADCLF_IFADC1_ADCLFSROUT 0x00000010U 2416 #define LRFDRFE32_IFADCLF_IFADC1_ADCLFSROUT_M 0x00000010U 2417 #define LRFDRFE32_IFADCLF_IFADC1_ADCLFSROUT_S 4U 2418 #define LRFDRFE32_IFADCLF_IFADC1_ADCLFSROUT_EN 0x00000010U 2419 #define LRFDRFE32_IFADCLF_IFADC1_ADCLFSROUT_DIS 0x00000000U 2420 2421 // Field: [3:1] LPFTSTMODE 2422 // 2423 // ENUMs: 2424 // EN All the bits are 1 2425 // DIS All the bits are 0 2426 #define LRFDRFE32_IFADCLF_IFADC1_LPFTSTMODE_W 3U 2427 #define LRFDRFE32_IFADCLF_IFADC1_LPFTSTMODE_M 0x0000000EU 2428 #define LRFDRFE32_IFADCLF_IFADC1_LPFTSTMODE_S 1U 2429 #define LRFDRFE32_IFADCLF_IFADC1_LPFTSTMODE_EN 0x00000002U 2430 #define LRFDRFE32_IFADCLF_IFADC1_LPFTSTMODE_DIS 0x00000000U 2431 2432 // Field: [0] INVCLKOUT 2433 // 2434 // ENUMs: 2435 // EN Invert IFADC output clock phase (default) 2436 // DIS Keep default IFADC output clock phase 2437 #define LRFDRFE32_IFADCLF_IFADC1_INVCLKOUT 0x00000001U 2438 #define LRFDRFE32_IFADCLF_IFADC1_INVCLKOUT_M 0x00000001U 2439 #define LRFDRFE32_IFADCLF_IFADC1_INVCLKOUT_S 0U 2440 #define LRFDRFE32_IFADCLF_IFADC1_INVCLKOUT_EN 0x00000001U 2441 #define LRFDRFE32_IFADCLF_IFADC1_INVCLKOUT_DIS 0x00000000U 2442 2443 //***************************************************************************** 2444 // 2445 // Register: LRFDRFE32_O_IFADCALDO_IFADCQUANT 2446 // 2447 //***************************************************************************** 2448 // Field: [31] ATESTVSSANA 2449 // 2450 // ENUMs: 2451 // EN Connected 2452 // DIS Not connected 2453 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTVSSANA 0x80000000U 2454 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTVSSANA_M 0x80000000U 2455 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTVSSANA_S 31U 2456 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTVSSANA_EN 0x80000000U 2457 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTVSSANA_DIS 0x00000000U 2458 2459 // Field: [29:24] TRIMOUT 2460 // 2461 // ENUMs: 2462 // ONES All the bits are one 2463 // ZEROS All the bits are zero 2464 #define LRFDRFE32_IFADCALDO_IFADCQUANT_TRIMOUT_W 6U 2465 #define LRFDRFE32_IFADCALDO_IFADCQUANT_TRIMOUT_M 0x3F000000U 2466 #define LRFDRFE32_IFADCALDO_IFADCQUANT_TRIMOUT_S 24U 2467 #define LRFDRFE32_IFADCALDO_IFADCQUANT_TRIMOUT_ONES 0x3F000000U 2468 #define LRFDRFE32_IFADCALDO_IFADCQUANT_TRIMOUT_ZEROS 0x00000000U 2469 2470 // Field: [23] DUMMY 2471 // 2472 // ENUMs: 2473 // EN Enabled 2474 // DIS Disabled 2475 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DUMMY 0x00800000U 2476 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DUMMY_M 0x00800000U 2477 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DUMMY_S 23U 2478 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DUMMY_EN 0x00800000U 2479 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DUMMY_DIS 0x00000000U 2480 2481 // Field: [22] ATESTOUT 2482 // 2483 // ENUMs: 2484 // EN Enabled 2485 // DIS Disabled 2486 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTOUT 0x00400000U 2487 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTOUT_M 0x00400000U 2488 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTOUT_S 22U 2489 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTOUT_EN 0x00400000U 2490 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTOUT_DIS 0x00000000U 2491 2492 // Field: [21] ATSTLDOFB 2493 // 2494 // ENUMs: 2495 // EN Enabled 2496 // DIS Disabled 2497 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATSTLDOFB 0x00200000U 2498 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATSTLDOFB_M 0x00200000U 2499 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATSTLDOFB_S 21U 2500 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATSTLDOFB_EN 0x00200000U 2501 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATSTLDOFB_DIS 0x00000000U 2502 2503 // Field: [20] ATESTERRAMP 2504 // 2505 // ENUMs: 2506 // EN Enabled 2507 // DIS Disabled 2508 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTERRAMP 0x00100000U 2509 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTERRAMP_M 0x00100000U 2510 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTERRAMP_S 20U 2511 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTERRAMP_EN 0x00100000U 2512 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ATESTERRAMP_DIS 0x00000000U 2513 2514 // Field: [19] ITEST 2515 // 2516 // ENUMs: 2517 // EN Enabled 2518 // DIS Disabled 2519 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ITEST 0x00080000U 2520 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ITEST_M 0x00080000U 2521 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ITEST_S 19U 2522 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ITEST_EN 0x00080000U 2523 #define LRFDRFE32_IFADCALDO_IFADCQUANT_ITEST_DIS 0x00000000U 2524 2525 // Field: [18] BYPASS 2526 // 2527 // ENUMs: 2528 // EN Enabled 2529 // DIS Disabled 2530 #define LRFDRFE32_IFADCALDO_IFADCQUANT_BYPASS 0x00040000U 2531 #define LRFDRFE32_IFADCALDO_IFADCQUANT_BYPASS_M 0x00040000U 2532 #define LRFDRFE32_IFADCALDO_IFADCQUANT_BYPASS_S 18U 2533 #define LRFDRFE32_IFADCALDO_IFADCQUANT_BYPASS_EN 0x00040000U 2534 #define LRFDRFE32_IFADCALDO_IFADCQUANT_BYPASS_DIS 0x00000000U 2535 2536 // Field: [17] CLAMP 2537 // 2538 // ENUMs: 2539 // EN Enabled 2540 // DIS Disabled. The LDO output is shorted to ground when 2541 // disabled. 2542 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CLAMP 0x00020000U 2543 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CLAMP_M 0x00020000U 2544 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CLAMP_S 17U 2545 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CLAMP_EN 0x00020000U 2546 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CLAMP_DIS 0x00000000U 2547 2548 // Field: [16] CTL 2549 // 2550 // ENUMs: 2551 // EN Enabled 2552 // DIS Disabled 2553 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CTL 0x00010000U 2554 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CTL_M 0x00010000U 2555 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CTL_S 16U 2556 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CTL_EN 0x00010000U 2557 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CTL_DIS 0x00000000U 2558 2559 // Field: [15:14] CLKDLYTRIM 2560 // 2561 // ENUMs: 2562 // ONES All the bits are one 2563 // ZEROS All the bits are zero 2564 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CLKDLYTRIM_W 2U 2565 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CLKDLYTRIM_M 0x0000C000U 2566 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CLKDLYTRIM_S 14U 2567 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CLKDLYTRIM_ONES 0x0000C000U 2568 #define LRFDRFE32_IFADCALDO_IFADCQUANT_CLKDLYTRIM_ZEROS 0x00000000U 2569 2570 // Field: [13:9] DBGCALVALIN 2571 // 2572 // ENUMs: 2573 // ONES All the bits are ONES 2574 // ZEROS All the bits are 0 2575 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALVALIN_W 5U 2576 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALVALIN_M 0x00003E00U 2577 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALVALIN_S 9U 2578 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALVALIN_ONES 0x00003E00U 2579 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALVALIN_ZEROS 0x00000000U 2580 2581 // Field: [8] DBGCALLEG 2582 // 2583 // ENUMs: 2584 // NEG Negative leg 2585 // POS Positive leg 2586 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALLEG 0x00000100U 2587 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALLEG_M 0x00000100U 2588 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALLEG_S 8U 2589 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALLEG_NEG 0x00000100U 2590 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALLEG_POS 0x00000000U 2591 2592 // Field: [7:6] DBGCALMQ 2593 // 2594 // ENUMs: 2595 // DBGCAL_QMODB UNCLEAR_Enable quantizer calibration mode. 2596 // DBGCAL_QMODP Enable quantizer calibration mode for Positive 2597 // comparator in Q modulator. 2598 // DBGCAL_QMODN Enable quantizer calibration mode for Negative 2599 // comparator in Q modulator. 2600 // DBGCAL_QMODZ Disable quantizer calibration mode.(Default) 2601 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_W 2U 2602 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_M 0x000000C0U 2603 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_S 6U 2604 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_DBGCAL_QMODB 0x000000C0U 2605 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_DBGCAL_QMODP 0x00000080U 2606 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_DBGCAL_QMODN 0x00000040U 2607 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMQ_DBGCAL_QMODZ 0x00000000U 2608 2609 // Field: [5:4] DBGCALMI 2610 // 2611 // ENUMs: 2612 // DBGCAL_IMODB UNCLEAR_Enable quantizer calibration mode. 2613 // DBGCAL_IMODP Enable quantizer calibration mode for Positive 2614 // comparator in I modulator. 2615 // DBGCAL_IMODN Enable quantizer calibration mode for Negative 2616 // comparator in I modulator. 2617 // DBGCAL_IMODZ Disable quantizer calibration mode.(Default) 2618 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_W 2U 2619 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_M 0x00000030U 2620 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_S 4U 2621 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_DBGCAL_IMODB 0x00000030U 2622 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_DBGCAL_IMODP 0x00000020U 2623 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_DBGCAL_IMODN 0x00000010U 2624 #define LRFDRFE32_IFADCALDO_IFADCQUANT_DBGCALMI_DBGCAL_IMODZ 0x00000000U 2625 2626 // Field: [3] AUTOCAL 2627 // 2628 // ENUMs: 2629 // EN Enable the auto calibration logic (Default) 2630 // DIS Disable the auto calibration logic 2631 #define LRFDRFE32_IFADCALDO_IFADCQUANT_AUTOCAL 0x00000008U 2632 #define LRFDRFE32_IFADCALDO_IFADCQUANT_AUTOCAL_M 0x00000008U 2633 #define LRFDRFE32_IFADCALDO_IFADCQUANT_AUTOCAL_S 3U 2634 #define LRFDRFE32_IFADCALDO_IFADCQUANT_AUTOCAL_EN 0x00000008U 2635 #define LRFDRFE32_IFADCALDO_IFADCQUANT_AUTOCAL_DIS 0x00000000U 2636 2637 // Field: [2:0] QUANTTHR 2638 // 2639 // ENUMs: 2640 // ONES All the bits are 1 2641 // ZEROS All the bits are 0 2642 #define LRFDRFE32_IFADCALDO_IFADCQUANT_QUANTTHR_W 3U 2643 #define LRFDRFE32_IFADCALDO_IFADCQUANT_QUANTTHR_M 0x00000007U 2644 #define LRFDRFE32_IFADCALDO_IFADCQUANT_QUANTTHR_S 0U 2645 #define LRFDRFE32_IFADCALDO_IFADCQUANT_QUANTTHR_ONES 0x00000007U 2646 #define LRFDRFE32_IFADCALDO_IFADCQUANT_QUANTTHR_ZEROS 0x00000000U 2647 2648 //***************************************************************************** 2649 // 2650 // Register: LRFDRFE32_O_IFADCTST_IFADCDLDO 2651 // 2652 //***************************************************************************** 2653 // Field: [23] EXTCURR 2654 // 2655 // ENUMs: 2656 // EN Enabled 2657 // DIS Disabled 2658 #define LRFDRFE32_IFADCTST_IFADCDLDO_EXTCURR 0x00800000U 2659 #define LRFDRFE32_IFADCTST_IFADCDLDO_EXTCURR_M 0x00800000U 2660 #define LRFDRFE32_IFADCTST_IFADCDLDO_EXTCURR_S 23U 2661 #define LRFDRFE32_IFADCTST_IFADCDLDO_EXTCURR_EN 0x00800000U 2662 #define LRFDRFE32_IFADCTST_IFADCDLDO_EXTCURR_DIS 0x00000000U 2663 2664 // Field: [22] QCALDBIQ 2665 // 2666 // ENUMs: 2667 // COMP1 I comparator 2668 // COMP0 Q Comparator 2669 #define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBIQ 0x00400000U 2670 #define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBIQ_M 0x00400000U 2671 #define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBIQ_S 22U 2672 #define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBIQ_COMP1 0x00400000U 2673 #define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBIQ_COMP0 0x00000000U 2674 2675 // Field: [21] QCALDBC 2676 // 2677 // ENUMs: 2678 // COMP1 I comparator 2679 // COMP0 Q Comparator 2680 #define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBC 0x00200000U 2681 #define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBC_M 0x00200000U 2682 #define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBC_S 21U 2683 #define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBC_COMP1 0x00200000U 2684 #define LRFDRFE32_IFADCTST_IFADCDLDO_QCALDBC_COMP0 0x00000000U 2685 2686 // Field: [20:16] SEL 2687 // 2688 // ENUMs: 2689 // EXTCLKN1 External ADC clock through ADC_TEST_N (N1 2690 // internally). The the clock should be a 200MHz 2691 // sine wave (it is divided internally to 100MHz). 2692 // NONE ADC_TEST_P and ADC_TEST_N tristated (Default) 2693 #define LRFDRFE32_IFADCTST_IFADCDLDO_SEL_W 5U 2694 #define LRFDRFE32_IFADCTST_IFADCDLDO_SEL_M 0x001F0000U 2695 #define LRFDRFE32_IFADCTST_IFADCDLDO_SEL_S 16U 2696 #define LRFDRFE32_IFADCTST_IFADCDLDO_SEL_EXTCLKN1 0x001F0000U 2697 #define LRFDRFE32_IFADCTST_IFADCDLDO_SEL_NONE 0x00000000U 2698 2699 // Field: [13:8] TRIMOUT 2700 // 2701 // ENUMs: 2702 // ONES All the bits are one 2703 // ZEROS All the bits are zero 2704 #define LRFDRFE32_IFADCTST_IFADCDLDO_TRIMOUT_W 6U 2705 #define LRFDRFE32_IFADCTST_IFADCDLDO_TRIMOUT_M 0x00003F00U 2706 #define LRFDRFE32_IFADCTST_IFADCDLDO_TRIMOUT_S 8U 2707 #define LRFDRFE32_IFADCTST_IFADCDLDO_TRIMOUT_ONES 0x00003F00U 2708 #define LRFDRFE32_IFADCTST_IFADCDLDO_TRIMOUT_ZEROS 0x00000000U 2709 2710 // Field: [7] DUMMY 2711 // 2712 // ENUMs: 2713 // EN Enabled 2714 // DIS Disabled 2715 #define LRFDRFE32_IFADCTST_IFADCDLDO_DUMMY 0x00000080U 2716 #define LRFDRFE32_IFADCTST_IFADCDLDO_DUMMY_M 0x00000080U 2717 #define LRFDRFE32_IFADCTST_IFADCDLDO_DUMMY_S 7U 2718 #define LRFDRFE32_IFADCTST_IFADCDLDO_DUMMY_EN 0x00000080U 2719 #define LRFDRFE32_IFADCTST_IFADCDLDO_DUMMY_DIS 0x00000000U 2720 2721 // Field: [6] ATESTOUT 2722 // 2723 // ENUMs: 2724 // EN Enabled 2725 // DIS Disabled 2726 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTOUT 0x00000040U 2727 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTOUT_M 0x00000040U 2728 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTOUT_S 6U 2729 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTOUT_EN 0x00000040U 2730 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTOUT_DIS 0x00000000U 2731 2732 // Field: [5] ATSTBGP 2733 // 2734 // ENUMs: 2735 // EN Enabled 2736 // DIS Disabled 2737 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATSTBGP 0x00000020U 2738 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATSTBGP_M 0x00000020U 2739 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATSTBGP_S 5U 2740 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATSTBGP_EN 0x00000020U 2741 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATSTBGP_DIS 0x00000000U 2742 2743 // Field: [4] ATESTERRAMP 2744 // 2745 // ENUMs: 2746 // EN Enabled 2747 // DIS Disabled 2748 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTERRAMP 0x00000010U 2749 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTERRAMP_M 0x00000010U 2750 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTERRAMP_S 4U 2751 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTERRAMP_EN 0x00000010U 2752 #define LRFDRFE32_IFADCTST_IFADCDLDO_ATESTERRAMP_DIS 0x00000000U 2753 2754 // Field: [3] ITEST 2755 // 2756 // ENUMs: 2757 // EN Enabled 2758 // DIS Disabled 2759 #define LRFDRFE32_IFADCTST_IFADCDLDO_ITEST 0x00000008U 2760 #define LRFDRFE32_IFADCTST_IFADCDLDO_ITEST_M 0x00000008U 2761 #define LRFDRFE32_IFADCTST_IFADCDLDO_ITEST_S 3U 2762 #define LRFDRFE32_IFADCTST_IFADCDLDO_ITEST_EN 0x00000008U 2763 #define LRFDRFE32_IFADCTST_IFADCDLDO_ITEST_DIS 0x00000000U 2764 2765 // Field: [2] BYPASS 2766 // 2767 // ENUMs: 2768 // EN Enabled 2769 // DIS Disabled 2770 #define LRFDRFE32_IFADCTST_IFADCDLDO_BYPASS 0x00000004U 2771 #define LRFDRFE32_IFADCTST_IFADCDLDO_BYPASS_M 0x00000004U 2772 #define LRFDRFE32_IFADCTST_IFADCDLDO_BYPASS_S 2U 2773 #define LRFDRFE32_IFADCTST_IFADCDLDO_BYPASS_EN 0x00000004U 2774 #define LRFDRFE32_IFADCTST_IFADCDLDO_BYPASS_DIS 0x00000000U 2775 2776 // Field: [1] CLAMP 2777 // 2778 // ENUMs: 2779 // EN Enabled 2780 // DIS Disabled. The LDO output is shorted to ground when 2781 // disabled. 2782 #define LRFDRFE32_IFADCTST_IFADCDLDO_CLAMP 0x00000002U 2783 #define LRFDRFE32_IFADCTST_IFADCDLDO_CLAMP_M 0x00000002U 2784 #define LRFDRFE32_IFADCTST_IFADCDLDO_CLAMP_S 1U 2785 #define LRFDRFE32_IFADCTST_IFADCDLDO_CLAMP_EN 0x00000002U 2786 #define LRFDRFE32_IFADCTST_IFADCDLDO_CLAMP_DIS 0x00000000U 2787 2788 // Field: [0] CTL 2789 // 2790 // ENUMs: 2791 // EN Enabled 2792 // DIS Disabled 2793 #define LRFDRFE32_IFADCTST_IFADCDLDO_CTL 0x00000001U 2794 #define LRFDRFE32_IFADCTST_IFADCDLDO_CTL_M 0x00000001U 2795 #define LRFDRFE32_IFADCTST_IFADCDLDO_CTL_S 0U 2796 #define LRFDRFE32_IFADCTST_IFADCDLDO_CTL_EN 0x00000001U 2797 #define LRFDRFE32_IFADCTST_IFADCDLDO_CTL_DIS 0x00000000U 2798 2799 //***************************************************************************** 2800 // 2801 // Register: LRFDRFE32_O_ATSTREF 2802 // 2803 //***************************************************************************** 2804 // Field: [31] VREFBPDIS 2805 // 2806 // ENUMs: 2807 // BPDIS Bandgap reference bypass disabled 2808 // BPEN Bandgap reference bypass enabled. 2809 #define LRFDRFE32_ATSTREF_VREFBPDIS 0x80000000U 2810 #define LRFDRFE32_ATSTREF_VREFBPDIS_M 0x80000000U 2811 #define LRFDRFE32_ATSTREF_VREFBPDIS_S 31U 2812 #define LRFDRFE32_ATSTREF_VREFBPDIS_BPDIS 0x80000000U 2813 #define LRFDRFE32_ATSTREF_VREFBPDIS_BPEN 0x00000000U 2814 2815 // Field: [30:26] IREFTRIM 2816 // 2817 // ENUMs: 2818 // ONES All bits are ones 2819 // ZEROS All bits are zero 2820 #define LRFDRFE32_ATSTREF_IREFTRIM_W 5U 2821 #define LRFDRFE32_ATSTREF_IREFTRIM_M 0x7C000000U 2822 #define LRFDRFE32_ATSTREF_IREFTRIM_S 26U 2823 #define LRFDRFE32_ATSTREF_IREFTRIM_ONES 0x7C000000U 2824 #define LRFDRFE32_ATSTREF_IREFTRIM_ZEROS 0x00000000U 2825 2826 // Field: [25] BIAS 2827 // 2828 // ENUMs: 2829 // EN Enabled 2830 // DIS Disabled 2831 #define LRFDRFE32_ATSTREF_BIAS 0x02000000U 2832 #define LRFDRFE32_ATSTREF_BIAS_M 0x02000000U 2833 #define LRFDRFE32_ATSTREF_BIAS_S 25U 2834 #define LRFDRFE32_ATSTREF_BIAS_EN 0x02000000U 2835 #define LRFDRFE32_ATSTREF_BIAS_DIS 0x00000000U 2836 2837 // Field: [24] OUTPUT2 2838 // 2839 // ENUMs: 2840 // EN The output is enabled 2841 // DIS Output is disabled 2842 #define LRFDRFE32_ATSTREF_OUTPUT2 0x01000000U 2843 #define LRFDRFE32_ATSTREF_OUTPUT2_M 0x01000000U 2844 #define LRFDRFE32_ATSTREF_OUTPUT2_S 24U 2845 #define LRFDRFE32_ATSTREF_OUTPUT2_EN 0x01000000U 2846 #define LRFDRFE32_ATSTREF_OUTPUT2_DIS 0x00000000U 2847 2848 // Field: [23] OUTPUT1 2849 // 2850 // ENUMs: 2851 // EN The output is enabled 2852 // DIS Output is disabled 2853 #define LRFDRFE32_ATSTREF_OUTPUT1 0x00800000U 2854 #define LRFDRFE32_ATSTREF_OUTPUT1_M 0x00800000U 2855 #define LRFDRFE32_ATSTREF_OUTPUT1_S 23U 2856 #define LRFDRFE32_ATSTREF_OUTPUT1_EN 0x00800000U 2857 #define LRFDRFE32_ATSTREF_OUTPUT1_DIS 0x00000000U 2858 2859 // Field: [22:0] MUX 2860 // 2861 // ENUMs: 2862 // IFADC_ATB IFADC ATB 2863 // LDO_VTEST LDO_VTEST vtest out, current 2864 // LDO_ITEST LDO_ITEST itest out, current 2865 // PA_PEAK_OUTN PA peak detector output n 2866 // PA_PEAK_OUTP PA peak detector output p 2867 // MIX_OUTQN MIX outqn, voltage 2868 // MIX_OUTQP MIX outqp, voltage 2869 // MIX_OUTIN MIX outin, voltage 2870 // MIX_OUTIP MIX outip, voltage 2871 // FE_OUTIN_2 Frontend IF outin, voltage 2872 // FE_OUTIP_2 Frontend IF outip, voltage 2873 // FE_OUTQN Frontend IF outqn, voltage 2874 // FE_OUTQP Frontend IF outqp, voltage 2875 // FE_OUTIN Frontend IF outin, voltage 2876 // FE_OUTIP Frontend IF outip, voltage 2877 // DIS No atest selected 2878 #define LRFDRFE32_ATSTREF_MUX_W 23U 2879 #define LRFDRFE32_ATSTREF_MUX_M 0x007FFFFFU 2880 #define LRFDRFE32_ATSTREF_MUX_S 0U 2881 #define LRFDRFE32_ATSTREF_MUX_IFADC_ATB 0x00008000U 2882 #define LRFDRFE32_ATSTREF_MUX_LDO_VTEST 0x00004000U 2883 #define LRFDRFE32_ATSTREF_MUX_LDO_ITEST 0x00002000U 2884 #define LRFDRFE32_ATSTREF_MUX_PA_PEAK_OUTN 0x00000800U 2885 #define LRFDRFE32_ATSTREF_MUX_PA_PEAK_OUTP 0x00000400U 2886 #define LRFDRFE32_ATSTREF_MUX_MIX_OUTQN 0x00000200U 2887 #define LRFDRFE32_ATSTREF_MUX_MIX_OUTQP 0x00000100U 2888 #define LRFDRFE32_ATSTREF_MUX_MIX_OUTIN 0x00000080U 2889 #define LRFDRFE32_ATSTREF_MUX_MIX_OUTIP 0x00000040U 2890 #define LRFDRFE32_ATSTREF_MUX_FE_OUTIN_2 0x00000020U 2891 #define LRFDRFE32_ATSTREF_MUX_FE_OUTIP_2 0x00000010U 2892 #define LRFDRFE32_ATSTREF_MUX_FE_OUTQN 0x00000008U 2893 #define LRFDRFE32_ATSTREF_MUX_FE_OUTQP 0x00000004U 2894 #define LRFDRFE32_ATSTREF_MUX_FE_OUTIN 0x00000002U 2895 #define LRFDRFE32_ATSTREF_MUX_FE_OUTIP 0x00000001U 2896 #define LRFDRFE32_ATSTREF_MUX_DIS 0x00000000U 2897 2898 //***************************************************************************** 2899 // 2900 // Register: LRFDRFE32_O_DIV_DCO 2901 // 2902 //***************************************************************************** 2903 // Field: [31] PDET 2904 // 2905 // ENUMs: 2906 // EN Peak detektor mode enabled, used in production 2907 // test 2908 // DIS Peak detector mode disabled, normal functional 2909 // mode 2910 #define LRFDRFE32_DIV_DCO_PDET 0x80000000U 2911 #define LRFDRFE32_DIV_DCO_PDET_M 0x80000000U 2912 #define LRFDRFE32_DIV_DCO_PDET_S 31U 2913 #define LRFDRFE32_DIV_DCO_PDET_EN 0x80000000U 2914 #define LRFDRFE32_DIV_DCO_PDET_DIS 0x00000000U 2915 2916 // Field: [30:28] NMIREFTRIM 2917 // 2918 // ENUMs: 2919 // ALLONES All the bits are 1 2920 // ALLZEROS All the bits are 0 2921 #define LRFDRFE32_DIV_DCO_NMIREFTRIM_W 3U 2922 #define LRFDRFE32_DIV_DCO_NMIREFTRIM_M 0x70000000U 2923 #define LRFDRFE32_DIV_DCO_NMIREFTRIM_S 28U 2924 #define LRFDRFE32_DIV_DCO_NMIREFTRIM_ALLONES 0x70000000U 2925 #define LRFDRFE32_DIV_DCO_NMIREFTRIM_ALLZEROS 0x00000000U 2926 2927 // Field: [27:25] PMIREFTRIM 2928 // 2929 // ENUMs: 2930 // ALLONES All the bits are 1 2931 // ALLZEROS All the bits are 0 2932 #define LRFDRFE32_DIV_DCO_PMIREFTRIM_W 3U 2933 #define LRFDRFE32_DIV_DCO_PMIREFTRIM_M 0x0E000000U 2934 #define LRFDRFE32_DIV_DCO_PMIREFTRIM_S 25U 2935 #define LRFDRFE32_DIV_DCO_PMIREFTRIM_ALLONES 0x0E000000U 2936 #define LRFDRFE32_DIV_DCO_PMIREFTRIM_ALLZEROS 0x00000000U 2937 2938 // Field: [24] TXBBOOST 2939 // 2940 // ENUMs: 2941 // INCREASED High drive strength 2942 // DEFAULT Default drive strength 2943 #define LRFDRFE32_DIV_DCO_TXBBOOST 0x01000000U 2944 #define LRFDRFE32_DIV_DCO_TXBBOOST_M 0x01000000U 2945 #define LRFDRFE32_DIV_DCO_TXBBOOST_S 24U 2946 #define LRFDRFE32_DIV_DCO_TXBBOOST_INCREASED 0x01000000U 2947 #define LRFDRFE32_DIV_DCO_TXBBOOST_DEFAULT 0x00000000U 2948 2949 // Field: [23] S1GFRC 2950 // 2951 // ENUMs: 2952 // EN Enable force S1G power switch 2953 // DIS Disable force S1G power switch 2954 #define LRFDRFE32_DIV_DCO_S1GFRC 0x00800000U 2955 #define LRFDRFE32_DIV_DCO_S1GFRC_M 0x00800000U 2956 #define LRFDRFE32_DIV_DCO_S1GFRC_S 23U 2957 #define LRFDRFE32_DIV_DCO_S1GFRC_EN 0x00800000U 2958 #define LRFDRFE32_DIV_DCO_S1GFRC_DIS 0x00000000U 2959 2960 // Field: [22:21] BUFGAIN 2961 // 2962 // ENUMs: 2963 // _60_PST 60% of maximum gain 2964 // DONT_USE Same as _80_PST 2965 // _80_PST 80% of maximum gain 2966 // MAX Maximum gain (default) 2967 #define LRFDRFE32_DIV_DCO_BUFGAIN_W 2U 2968 #define LRFDRFE32_DIV_DCO_BUFGAIN_M 0x00600000U 2969 #define LRFDRFE32_DIV_DCO_BUFGAIN_S 21U 2970 #define LRFDRFE32_DIV_DCO_BUFGAIN__60_PST 0x00600000U 2971 #define LRFDRFE32_DIV_DCO_BUFGAIN_DONT_USE 0x00400000U 2972 #define LRFDRFE32_DIV_DCO_BUFGAIN__80_PST 0x00200000U 2973 #define LRFDRFE32_DIV_DCO_BUFGAIN_MAX 0x00000000U 2974 2975 // Field: [20] BIAS 2976 // 2977 // ENUMs: 2978 // DEFAULT Default bias 2979 // ALTERNATIVE Alternative bias (for test purposes) 2980 #define LRFDRFE32_DIV_DCO_BIAS 0x00100000U 2981 #define LRFDRFE32_DIV_DCO_BIAS_M 0x00100000U 2982 #define LRFDRFE32_DIV_DCO_BIAS_S 20U 2983 #define LRFDRFE32_DIV_DCO_BIAS_DEFAULT 0x00100000U 2984 #define LRFDRFE32_DIV_DCO_BIAS_ALTERNATIVE 0x00000000U 2985 2986 // Field: [19] OUT 2987 // 2988 // ENUMs: 2989 // FE_2G4 Enable outputs going to 2.4GHz front-end 2990 // FE_S1G Enable outputs going to sub-1GHz front-end 2991 #define LRFDRFE32_DIV_DCO_OUT 0x00080000U 2992 #define LRFDRFE32_DIV_DCO_OUT_M 0x00080000U 2993 #define LRFDRFE32_DIV_DCO_OUT_S 19U 2994 #define LRFDRFE32_DIV_DCO_OUT_FE_2G4 0x00080000U 2995 #define LRFDRFE32_DIV_DCO_OUT_FE_S1G 0x00000000U 2996 2997 // Field: [18:16] RATIO 2998 // 2999 // ENUMs: 3000 // DIV30 DIVIDER = 30 3001 // DIV15 DIVIDER = 15 3002 // DIV10 DIVIDER = 10 3003 // DIV5 DIVIDER = 5 3004 // DIV12 DIVIDER = 12 3005 // DIV6 DIVIDER = 6 3006 // DIV4 DIVIDER = 4 (for test purposes only) 3007 // DIV2 DIVIDER = 2 3008 #define LRFDRFE32_DIV_DCO_RATIO_W 3U 3009 #define LRFDRFE32_DIV_DCO_RATIO_M 0x00070000U 3010 #define LRFDRFE32_DIV_DCO_RATIO_S 16U 3011 #define LRFDRFE32_DIV_DCO_RATIO_DIV30 0x00070000U 3012 #define LRFDRFE32_DIV_DCO_RATIO_DIV15 0x00060000U 3013 #define LRFDRFE32_DIV_DCO_RATIO_DIV10 0x00050000U 3014 #define LRFDRFE32_DIV_DCO_RATIO_DIV5 0x00040000U 3015 #define LRFDRFE32_DIV_DCO_RATIO_DIV12 0x00030000U 3016 #define LRFDRFE32_DIV_DCO_RATIO_DIV6 0x00020000U 3017 #define LRFDRFE32_DIV_DCO_RATIO_DIV4 0x00010000U 3018 #define LRFDRFE32_DIV_DCO_RATIO_DIV2 0x00000000U 3019 3020 // Field: [10:9] MTDCSPARE 3021 // 3022 // ENUMs: 3023 // DIS DIVIDER = 4 (for test purposes only) 3024 // EN DIVIDER = 2 3025 #define LRFDRFE32_DIV_DCO_MTDCSPARE_W 2U 3026 #define LRFDRFE32_DIV_DCO_MTDCSPARE_M 0x00000600U 3027 #define LRFDRFE32_DIV_DCO_MTDCSPARE_S 9U 3028 #define LRFDRFE32_DIV_DCO_MTDCSPARE_DIS 0x00000200U 3029 #define LRFDRFE32_DIV_DCO_MTDCSPARE_EN 0x00000000U 3030 3031 // Field: [8:7] SPARE7 3032 // 3033 // ENUMs: 3034 // ONE Bit is one 3035 // ZERO Bit is zero 3036 #define LRFDRFE32_DIV_DCO_SPARE7_W 2U 3037 #define LRFDRFE32_DIV_DCO_SPARE7_M 0x00000180U 3038 #define LRFDRFE32_DIV_DCO_SPARE7_S 7U 3039 #define LRFDRFE32_DIV_DCO_SPARE7_ONE 0x00000080U 3040 #define LRFDRFE32_DIV_DCO_SPARE7_ZERO 0x00000000U 3041 3042 // Field: [6:3] TAILRESTRIM 3043 // 3044 // ENUMs: 3045 // ALLONES All the bits are 1 3046 // ALLZEROS All the bits are 0 3047 #define LRFDRFE32_DIV_DCO_TAILRESTRIM_W 4U 3048 #define LRFDRFE32_DIV_DCO_TAILRESTRIM_M 0x00000078U 3049 #define LRFDRFE32_DIV_DCO_TAILRESTRIM_S 3U 3050 #define LRFDRFE32_DIV_DCO_TAILRESTRIM_ALLONES 0x00000078U 3051 #define LRFDRFE32_DIV_DCO_TAILRESTRIM_ALLZEROS 0x00000000U 3052 3053 // Field: [2] RTRIMCAP 3054 // 3055 // ENUMs: 3056 // EN Enable 3057 // DIS Disable(default) 3058 #define LRFDRFE32_DIV_DCO_RTRIMCAP 0x00000004U 3059 #define LRFDRFE32_DIV_DCO_RTRIMCAP_M 0x00000004U 3060 #define LRFDRFE32_DIV_DCO_RTRIMCAP_S 2U 3061 #define LRFDRFE32_DIV_DCO_RTRIMCAP_EN 0x00000004U 3062 #define LRFDRFE32_DIV_DCO_RTRIMCAP_DIS 0x00000000U 3063 3064 // Field: [1] CNRCAP 3065 // 3066 // ENUMs: 3067 // _50MHZ 50 MHz 3068 // DEFAULT Default 3069 #define LRFDRFE32_DIV_DCO_CNRCAP 0x00000002U 3070 #define LRFDRFE32_DIV_DCO_CNRCAP_M 0x00000002U 3071 #define LRFDRFE32_DIV_DCO_CNRCAP_S 1U 3072 #define LRFDRFE32_DIV_DCO_CNRCAP__50MHZ 0x00000002U 3073 #define LRFDRFE32_DIV_DCO_CNRCAP_DEFAULT 0x00000000U 3074 3075 // Field: [0] CRSCAPCM 3076 // 3077 // ENUMs: 3078 // REDUCED Reduced common mode for greater reliability 3079 // DEFAULT Default 3080 #define LRFDRFE32_DIV_DCO_CRSCAPCM 0x00000001U 3081 #define LRFDRFE32_DIV_DCO_CRSCAPCM_M 0x00000001U 3082 #define LRFDRFE32_DIV_DCO_CRSCAPCM_S 0U 3083 #define LRFDRFE32_DIV_DCO_CRSCAPCM_REDUCED 0x00000001U 3084 #define LRFDRFE32_DIV_DCO_CRSCAPCM_DEFAULT 0x00000000U 3085 3086 //***************************************************************************** 3087 // 3088 // Register: LRFDRFE32_O_TDCLDO_DIVLDO 3089 // 3090 //***************************************************************************** 3091 // Field: [31] TDCLDO_ITESTCTL 3092 // 3093 // ENUMs: 3094 // EN ITEST enabled 3095 // DIS ITEST Disabled 3096 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTCTL 0x80000000U 3097 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTCTL_M 0x80000000U 3098 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTCTL_S 31U 3099 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTCTL_EN 0x80000000U 3100 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTCTL_DIS 0x00000000U 3101 3102 // Field: [30:24] TDCLDO_VOUTTRIM 3103 // 3104 // ENUMs: 3105 // ONES All bits are one 3106 // ZEROS All bits are zero 3107 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_VOUTTRIM_W 7U 3108 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_VOUTTRIM_M 0x7F000000U 3109 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_VOUTTRIM_S 24U 3110 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_VOUTTRIM_ONES 0x7F000000U 3111 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_VOUTTRIM_ZEROS 0x00000000U 3112 3113 // Field: [23] TDCLDO_ITESTBUFCTL 3114 // 3115 // ENUMs: 3116 // EN ITEST mode in buffer is enabled 3117 // DIS ITEST mode in buffer is disabled 3118 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTBUFCTL 0x00800000U 3119 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTBUFCTL_M 0x00800000U 3120 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTBUFCTL_S 23U 3121 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTBUFCTL_EN 0x00800000U 3122 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_ITESTBUFCTL_DIS 0x00000000U 3123 3124 // Field: [22:20] TDCLDO_TMUX 3125 // 3126 // ENUMs: 3127 // VSSA ATEST output is VSSA 3128 // LDO_OUT ATEST output is LDO output 3129 // VDDA ATEST output is VDDA 3130 // OFF Normal mode 3131 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_W 3U 3132 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_M 0x00700000U 3133 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_S 20U 3134 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_VSSA 0x00400000U 3135 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_LDO_OUT 0x00200000U 3136 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_VDDA 0x00100000U 3137 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_TMUX_OFF 0x00000000U 3138 3139 // Field: [19] TDCLDO_PDSEL 3140 // 3141 // ENUMs: 3142 // DIODE Diode stack 3143 // R R (default) 3144 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_PDSEL 0x00080000U 3145 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_PDSEL_M 0x00080000U 3146 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_PDSEL_S 19U 3147 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_PDSEL_DIODE 0x00080000U 3148 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_PDSEL_R 0x00000000U 3149 3150 // Field: [18] TDCLDO_MODE 3151 // 3152 // ENUMs: 3153 // FAST Regulator in high bandwidth mode 3154 // NORM Regular low bandwidth of LDO 3155 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_MODE 0x00040000U 3156 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_MODE_M 0x00040000U 3157 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_MODE_S 18U 3158 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_MODE_FAST 0x00040000U 3159 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_MODE_NORM 0x00000000U 3160 3161 // Field: [17] TDCLDO_BYPASS 3162 // 3163 // ENUMs: 3164 // EN Regulator is bypassed 3165 // DIS No bypass 3166 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_BYPASS 0x00020000U 3167 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_BYPASS_M 0x00020000U 3168 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_BYPASS_S 17U 3169 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_BYPASS_EN 0x00020000U 3170 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_BYPASS_DIS 0x00000000U 3171 3172 // Field: [16] TDCLDO_CTL 3173 // 3174 // ENUMs: 3175 // EN Regulator is enabled 3176 // DIS Regulator is disabled 3177 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_CTL 0x00010000U 3178 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_CTL_M 0x00010000U 3179 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_CTL_S 16U 3180 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_CTL_EN 0x00010000U 3181 #define LRFDRFE32_TDCLDO_DIVLDO_TDCLDO_CTL_DIS 0x00000000U 3182 3183 // Field: [15] DIVLDO_SPARE15 3184 // 3185 // ENUMs: 3186 // ONES All bits are one 3187 // ZEROS All bits are zero 3188 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE15 0x00008000U 3189 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE15_M 0x00008000U 3190 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE15_S 15U 3191 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE15_ONES 0x00008000U 3192 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE15_ZEROS 0x00000000U 3193 3194 // Field: [14:8] DIVLDO_VOUTTRIM 3195 // 3196 // ENUMs: 3197 // ONES All bits are one 3198 // ZEROS All bits are zero 3199 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_VOUTTRIM_W 7U 3200 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_VOUTTRIM_M 0x00007F00U 3201 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_VOUTTRIM_S 8U 3202 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_VOUTTRIM_ONES 0x00007F00U 3203 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_VOUTTRIM_ZEROS 0x00000000U 3204 3205 // Field: [7] DIVLDO_ITST 3206 // 3207 // ENUMs: 3208 // EN Regulator is enabled 3209 // DIS Regulator is disabled 3210 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_ITST 0x00000080U 3211 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_ITST_M 0x00000080U 3212 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_ITST_S 7U 3213 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_ITST_EN 0x00000080U 3214 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_ITST_DIS 0x00000000U 3215 3216 // Field: [6:4] DIVLDO_TMUX 3217 // 3218 // ENUMs: 3219 // VDDR ATEST output is VDDR 3220 // LDO_OUT ATEST output is LDO output 3221 // GND ATEST output is grounded 3222 // OFF Normal mode 3223 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_W 3U 3224 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_M 0x00000070U 3225 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_S 4U 3226 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_VDDR 0x00000040U 3227 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_LDO_OUT 0x00000020U 3228 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_GND 0x00000010U 3229 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_TMUX_OFF 0x00000000U 3230 3231 // Field: [3] DIVLDO_SPARE3 3232 // 3233 // ENUMs: 3234 // ONE The bit is 1 3235 // ZERO The bit is 0 3236 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE3 0x00000008U 3237 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE3_M 0x00000008U 3238 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE3_S 3U 3239 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE3_ONE 0x00000008U 3240 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_SPARE3_ZERO 0x00000000U 3241 3242 // Field: [2] DIVLDO_MODE 3243 // 3244 // ENUMs: 3245 // FAST Regulator in high bandwidth mode 3246 // NORM Regular low bandwidth of LDO 3247 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_MODE 0x00000004U 3248 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_MODE_M 0x00000004U 3249 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_MODE_S 2U 3250 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_MODE_FAST 0x00000004U 3251 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_MODE_NORM 0x00000000U 3252 3253 // Field: [1] DIVLDO_BYPASS 3254 // 3255 // ENUMs: 3256 // EN Regulator is bypassed 3257 // DIS No bypass 3258 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_BYPASS 0x00000002U 3259 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_BYPASS_M 0x00000002U 3260 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_BYPASS_S 1U 3261 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_BYPASS_EN 0x00000002U 3262 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_BYPASS_DIS 0x00000000U 3263 3264 // Field: [0] DIVLDO_CTL 3265 // 3266 // ENUMs: 3267 // EN Regulator is enabled 3268 // DIS Regulator is disabled 3269 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_CTL 0x00000001U 3270 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_CTL_M 0x00000001U 3271 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_CTL_S 0U 3272 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_CTL_EN 0x00000001U 3273 #define LRFDRFE32_TDCLDO_DIVLDO_DIVLDO_CTL_DIS 0x00000000U 3274 3275 //***************************************************************************** 3276 // 3277 // Register: LRFDRFE32_O_DCOLDO1_DCOLDO0 3278 // 3279 //***************************************************************************** 3280 // Field: [26] REFSRC 3281 // 3282 // ENUMs: 3283 // BAW PLL clock source is BAW 3284 // XTAL PLL clock source is XTAL 3285 #define LRFDRFE32_DCOLDO1_DCOLDO0_REFSRC 0x04000000U 3286 #define LRFDRFE32_DCOLDO1_DCOLDO0_REFSRC_M 0x04000000U 3287 #define LRFDRFE32_DCOLDO1_DCOLDO0_REFSRC_S 26U 3288 #define LRFDRFE32_DCOLDO1_DCOLDO0_REFSRC_BAW 0x04000000U 3289 #define LRFDRFE32_DCOLDO1_DCOLDO0_REFSRC_XTAL 0x00000000U 3290 3291 // Field: [25:24] DIVATST 3292 // 3293 // ENUMs: 3294 // ONES All bits are one 3295 // ZEROS All bits are zero 3296 #define LRFDRFE32_DCOLDO1_DCOLDO0_DIVATST_W 2U 3297 #define LRFDRFE32_DCOLDO1_DCOLDO0_DIVATST_M 0x03000000U 3298 #define LRFDRFE32_DCOLDO1_DCOLDO0_DIVATST_S 24U 3299 #define LRFDRFE32_DCOLDO1_DCOLDO0_DIVATST_ONES 0x03000000U 3300 #define LRFDRFE32_DCOLDO1_DCOLDO0_DIVATST_ZEROS 0x00000000U 3301 3302 // Field: [23] PERFM 3303 // 3304 // ENUMs: 3305 // EN Enabled (performance) 3306 // DIS Disabled (normal) 3307 #define LRFDRFE32_DCOLDO1_DCOLDO0_PERFM 0x00800000U 3308 #define LRFDRFE32_DCOLDO1_DCOLDO0_PERFM_M 0x00800000U 3309 #define LRFDRFE32_DCOLDO1_DCOLDO0_PERFM_S 23U 3310 #define LRFDRFE32_DCOLDO1_DCOLDO0_PERFM_EN 0x00800000U 3311 #define LRFDRFE32_DCOLDO1_DCOLDO0_PERFM_DIS 0x00000000U 3312 3313 // Field: [22] CHRGFILT 3314 // 3315 // ENUMs: 3316 // EN Charging enabled 3317 // DIS Charging disabled, normal operation 3318 #define LRFDRFE32_DCOLDO1_DCOLDO0_CHRGFILT 0x00400000U 3319 #define LRFDRFE32_DCOLDO1_DCOLDO0_CHRGFILT_M 0x00400000U 3320 #define LRFDRFE32_DCOLDO1_DCOLDO0_CHRGFILT_S 22U 3321 #define LRFDRFE32_DCOLDO1_DCOLDO0_CHRGFILT_EN 0x00400000U 3322 #define LRFDRFE32_DCOLDO1_DCOLDO0_CHRGFILT_DIS 0x00000000U 3323 3324 // Field: [21:16] ATST 3325 // 3326 // ENUMs: 3327 // VSSANA VSSANA 3328 // FIRST_OUT First LDO output 3329 // LDO_OUT LDO output 3330 #define LRFDRFE32_DCOLDO1_DCOLDO0_ATST_W 6U 3331 #define LRFDRFE32_DCOLDO1_DCOLDO0_ATST_M 0x003F0000U 3332 #define LRFDRFE32_DCOLDO1_DCOLDO0_ATST_S 16U 3333 #define LRFDRFE32_DCOLDO1_DCOLDO0_ATST_VSSANA 0x00200000U 3334 #define LRFDRFE32_DCOLDO1_DCOLDO0_ATST_FIRST_OUT 0x00010000U 3335 #define LRFDRFE32_DCOLDO1_DCOLDO0_ATST_LDO_OUT 0x00000000U 3336 3337 // Field: [15:14] ITST 3338 // 3339 // ENUMs: 3340 // BOTH Enable both pass transistors 3341 // SECOND Enable second pass transistor 3342 // FIRST Enable first pass transistor 3343 // DIS Regulator is disabled 3344 #define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_W 2U 3345 #define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_M 0x0000C000U 3346 #define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_S 14U 3347 #define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_BOTH 0x0000C000U 3348 #define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_SECOND 0x00008000U 3349 #define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_FIRST 0x00004000U 3350 #define LRFDRFE32_DCOLDO1_DCOLDO0_ITST_DIS 0x00000000U 3351 3352 // Field: [13:8] SECONDTRIM 3353 // 3354 // ENUMs: 3355 // ONES All bits are one 3356 // ZEROS All bits are zero 3357 #define LRFDRFE32_DCOLDO1_DCOLDO0_SECONDTRIM_W 6U 3358 #define LRFDRFE32_DCOLDO1_DCOLDO0_SECONDTRIM_M 0x00003F00U 3359 #define LRFDRFE32_DCOLDO1_DCOLDO0_SECONDTRIM_S 8U 3360 #define LRFDRFE32_DCOLDO1_DCOLDO0_SECONDTRIM_ONES 0x00003F00U 3361 #define LRFDRFE32_DCOLDO1_DCOLDO0_SECONDTRIM_ZEROS 0x00000000U 3362 3363 // Field: [7:4] FIRSTTRIM 3364 // 3365 // ENUMs: 3366 // ONES All bits are one 3367 // ZEROS All bits are zero 3368 #define LRFDRFE32_DCOLDO1_DCOLDO0_FIRSTTRIM_W 4U 3369 #define LRFDRFE32_DCOLDO1_DCOLDO0_FIRSTTRIM_M 0x000000F0U 3370 #define LRFDRFE32_DCOLDO1_DCOLDO0_FIRSTTRIM_S 4U 3371 #define LRFDRFE32_DCOLDO1_DCOLDO0_FIRSTTRIM_ONES 0x000000F0U 3372 #define LRFDRFE32_DCOLDO1_DCOLDO0_FIRSTTRIM_ZEROS 0x00000000U 3373 3374 // Field: [3] PDN 3375 // 3376 // ENUMs: 3377 // EN Pulldown 3378 // DIS No Pulldown 3379 #define LRFDRFE32_DCOLDO1_DCOLDO0_PDN 0x00000008U 3380 #define LRFDRFE32_DCOLDO1_DCOLDO0_PDN_M 0x00000008U 3381 #define LRFDRFE32_DCOLDO1_DCOLDO0_PDN_S 3U 3382 #define LRFDRFE32_DCOLDO1_DCOLDO0_PDN_EN 0x00000008U 3383 #define LRFDRFE32_DCOLDO1_DCOLDO0_PDN_DIS 0x00000000U 3384 3385 // Field: [2] BYPFIRST 3386 // 3387 // ENUMs: 3388 // EN Regulator is bypassed 3389 // DIS No bypass 3390 #define LRFDRFE32_DCOLDO1_DCOLDO0_BYPFIRST 0x00000004U 3391 #define LRFDRFE32_DCOLDO1_DCOLDO0_BYPFIRST_M 0x00000004U 3392 #define LRFDRFE32_DCOLDO1_DCOLDO0_BYPFIRST_S 2U 3393 #define LRFDRFE32_DCOLDO1_DCOLDO0_BYPFIRST_EN 0x00000004U 3394 #define LRFDRFE32_DCOLDO1_DCOLDO0_BYPFIRST_DIS 0x00000000U 3395 3396 // Field: [1] BYPBOTH 3397 // 3398 // ENUMs: 3399 // EN Regulator is bypassed 3400 // DIS No bypass 3401 #define LRFDRFE32_DCOLDO1_DCOLDO0_BYPBOTH 0x00000002U 3402 #define LRFDRFE32_DCOLDO1_DCOLDO0_BYPBOTH_M 0x00000002U 3403 #define LRFDRFE32_DCOLDO1_DCOLDO0_BYPBOTH_S 1U 3404 #define LRFDRFE32_DCOLDO1_DCOLDO0_BYPBOTH_EN 0x00000002U 3405 #define LRFDRFE32_DCOLDO1_DCOLDO0_BYPBOTH_DIS 0x00000000U 3406 3407 // Field: [0] CTL 3408 // 3409 // ENUMs: 3410 // EN Regulator is enabled 3411 // DIS Regulator is disabled 3412 #define LRFDRFE32_DCOLDO1_DCOLDO0_CTL 0x00000001U 3413 #define LRFDRFE32_DCOLDO1_DCOLDO0_CTL_M 0x00000001U 3414 #define LRFDRFE32_DCOLDO1_DCOLDO0_CTL_S 0U 3415 #define LRFDRFE32_DCOLDO1_DCOLDO0_CTL_EN 0x00000001U 3416 #define LRFDRFE32_DCOLDO1_DCOLDO0_CTL_DIS 0x00000000U 3417 3418 //***************************************************************************** 3419 // 3420 // Register: LRFDRFE32_O_PRE1_PRE0 3421 // 3422 //***************************************************************************** 3423 // Field: [31:30] IIRBW 3424 // 3425 // ENUMs: 3426 // K16 K=16 3427 // K8 3428 // K4 3429 // K2 3430 #define LRFDRFE32_PRE1_PRE0_IIRBW_W 2U 3431 #define LRFDRFE32_PRE1_PRE0_IIRBW_M 0xC0000000U 3432 #define LRFDRFE32_PRE1_PRE0_IIRBW_S 30U 3433 #define LRFDRFE32_PRE1_PRE0_IIRBW_K16 0xC0000000U 3434 #define LRFDRFE32_PRE1_PRE0_IIRBW_K8 0x80000000U 3435 #define LRFDRFE32_PRE1_PRE0_IIRBW_K4 0x40000000U 3436 #define LRFDRFE32_PRE1_PRE0_IIRBW_K2 0x00000000U 3437 3438 // Field: [29] IIRORD 3439 // 3440 // ENUMs: 3441 // SECOND Select second order IIR filter 3442 // FIRST Select first order IIR filter 3443 #define LRFDRFE32_PRE1_PRE0_IIRORD 0x20000000U 3444 #define LRFDRFE32_PRE1_PRE0_IIRORD_M 0x20000000U 3445 #define LRFDRFE32_PRE1_PRE0_IIRORD_S 29U 3446 #define LRFDRFE32_PRE1_PRE0_IIRORD_SECOND 0x20000000U 3447 #define LRFDRFE32_PRE1_PRE0_IIRORD_FIRST 0x00000000U 3448 3449 // Field: [28:24] IIRDIV 3450 // 3451 // ENUMs: 3452 // ALLONES All the bits are 1 3453 // ALLZEROS All the bits are 0 3454 #define LRFDRFE32_PRE1_PRE0_IIRDIV_W 5U 3455 #define LRFDRFE32_PRE1_PRE0_IIRDIV_M 0x1F000000U 3456 #define LRFDRFE32_PRE1_PRE0_IIRDIV_S 24U 3457 #define LRFDRFE32_PRE1_PRE0_IIRDIV_ALLONES 0x1F000000U 3458 #define LRFDRFE32_PRE1_PRE0_IIRDIV_ALLZEROS 0x00000000U 3459 3460 // Field: [22] CALHSDDC 3461 // 3462 // ENUMs: 3463 // GATE Duty-cycling given by HSDDC 3464 // NOGATE No duty-cycling 3465 #define LRFDRFE32_PRE1_PRE0_CALHSDDC 0x00400000U 3466 #define LRFDRFE32_PRE1_PRE0_CALHSDDC_M 0x00400000U 3467 #define LRFDRFE32_PRE1_PRE0_CALHSDDC_S 22U 3468 #define LRFDRFE32_PRE1_PRE0_CALHSDDC_GATE 0x00400000U 3469 #define LRFDRFE32_PRE1_PRE0_CALHSDDC_NOGATE 0x00000000U 3470 3471 // Field: [21:16] HSDDC 3472 // 3473 // ENUMs: 3474 // ALLONES All the bits are 1 3475 // ALLZEROS All the bits are 0 3476 #define LRFDRFE32_PRE1_PRE0_HSDDC_W 6U 3477 #define LRFDRFE32_PRE1_PRE0_HSDDC_M 0x003F0000U 3478 #define LRFDRFE32_PRE1_PRE0_HSDDC_S 16U 3479 #define LRFDRFE32_PRE1_PRE0_HSDDC_ALLONES 0x003F0000U 3480 #define LRFDRFE32_PRE1_PRE0_HSDDC_ALLZEROS 0x00000000U 3481 3482 // Field: [15:14] SPARE14 3483 // 3484 // ENUMs: 3485 // ALLONES All the bits are 1 3486 // ALLZEROS All the bits are 0 3487 #define LRFDRFE32_PRE1_PRE0_SPARE14_W 2U 3488 #define LRFDRFE32_PRE1_PRE0_SPARE14_M 0x0000C000U 3489 #define LRFDRFE32_PRE1_PRE0_SPARE14_S 14U 3490 #define LRFDRFE32_PRE1_PRE0_SPARE14_ALLONES 0x0000C000U 3491 #define LRFDRFE32_PRE1_PRE0_SPARE14_ALLZEROS 0x00000000U 3492 3493 // Field: [13:8] PLLDIV1 3494 // 3495 // ENUMs: 3496 // ALLONES All the bits are 1 3497 // ALLZEROS All the bits are 0 3498 #define LRFDRFE32_PRE1_PRE0_PLLDIV1_W 6U 3499 #define LRFDRFE32_PRE1_PRE0_PLLDIV1_M 0x00003F00U 3500 #define LRFDRFE32_PRE1_PRE0_PLLDIV1_S 8U 3501 #define LRFDRFE32_PRE1_PRE0_PLLDIV1_ALLONES 0x00003F00U 3502 #define LRFDRFE32_PRE1_PRE0_PLLDIV1_ALLZEROS 0x00000000U 3503 3504 // Field: [7:6] SPARE6 3505 // 3506 // ENUMs: 3507 // ALLONES All the bits are 1 3508 // ALLZEROS All the bits are 0 3509 #define LRFDRFE32_PRE1_PRE0_SPARE6_W 2U 3510 #define LRFDRFE32_PRE1_PRE0_SPARE6_M 0x000000C0U 3511 #define LRFDRFE32_PRE1_PRE0_SPARE6_S 6U 3512 #define LRFDRFE32_PRE1_PRE0_SPARE6_ALLONES 0x000000C0U 3513 #define LRFDRFE32_PRE1_PRE0_SPARE6_ALLZEROS 0x00000000U 3514 3515 // Field: [5:0] PLLDIV0 3516 // 3517 // ENUMs: 3518 // ALLONES All the bits are 1 3519 // ALLZEROS All the bits are 0 3520 #define LRFDRFE32_PRE1_PRE0_PLLDIV0_W 6U 3521 #define LRFDRFE32_PRE1_PRE0_PLLDIV0_M 0x0000003FU 3522 #define LRFDRFE32_PRE1_PRE0_PLLDIV0_S 0U 3523 #define LRFDRFE32_PRE1_PRE0_PLLDIV0_ALLONES 0x0000003FU 3524 #define LRFDRFE32_PRE1_PRE0_PLLDIV0_ALLZEROS 0x00000000U 3525 3526 //***************************************************************************** 3527 // 3528 // Register: LRFDRFE32_O_PRE3_PRE2 3529 // 3530 //***************************************************************************** 3531 // Field: [31:21] FINECALDIV 3532 // 3533 // ENUMs: 3534 // ALLONES All the bits are 1 3535 // ALLZEROS All the bits are 0 3536 #define LRFDRFE32_PRE3_PRE2_FINECALDIV_W 11U 3537 #define LRFDRFE32_PRE3_PRE2_FINECALDIV_M 0xFFE00000U 3538 #define LRFDRFE32_PRE3_PRE2_FINECALDIV_S 21U 3539 #define LRFDRFE32_PRE3_PRE2_FINECALDIV_ALLONES 0xFFE00000U 3540 #define LRFDRFE32_PRE3_PRE2_FINECALDIV_ALLZEROS 0x00000000U 3541 3542 // Field: [20:16] MIDCALDIVMSB 3543 // 3544 // ENUMs: 3545 // ALLONES All the bits are 1 3546 // ALLZEROS All the bits are 0 3547 #define LRFDRFE32_PRE3_PRE2_MIDCALDIVMSB_W 5U 3548 #define LRFDRFE32_PRE3_PRE2_MIDCALDIVMSB_M 0x001F0000U 3549 #define LRFDRFE32_PRE3_PRE2_MIDCALDIVMSB_S 16U 3550 #define LRFDRFE32_PRE3_PRE2_MIDCALDIVMSB_ALLONES 0x001F0000U 3551 #define LRFDRFE32_PRE3_PRE2_MIDCALDIVMSB_ALLZEROS 0x00000000U 3552 3553 // Field: [15:12] MIDCALDIVLSB 3554 // 3555 // ENUMs: 3556 // ALLONES All the bits are 1 3557 // ALLZEROS All the bits are 0 3558 #define LRFDRFE32_PRE3_PRE2_MIDCALDIVLSB_W 4U 3559 #define LRFDRFE32_PRE3_PRE2_MIDCALDIVLSB_M 0x0000F000U 3560 #define LRFDRFE32_PRE3_PRE2_MIDCALDIVLSB_S 12U 3561 #define LRFDRFE32_PRE3_PRE2_MIDCALDIVLSB_ALLONES 0x0000F000U 3562 #define LRFDRFE32_PRE3_PRE2_MIDCALDIVLSB_ALLZEROS 0x00000000U 3563 3564 // Field: [11:6] CRSCALDIV 3565 // 3566 // ENUMs: 3567 // ALLONES All the bits are 1 3568 // ALLZEROS All the bits are 0 3569 #define LRFDRFE32_PRE3_PRE2_CRSCALDIV_W 6U 3570 #define LRFDRFE32_PRE3_PRE2_CRSCALDIV_M 0x00000FC0U 3571 #define LRFDRFE32_PRE3_PRE2_CRSCALDIV_S 6U 3572 #define LRFDRFE32_PRE3_PRE2_CRSCALDIV_ALLONES 0x00000FC0U 3573 #define LRFDRFE32_PRE3_PRE2_CRSCALDIV_ALLZEROS 0x00000000U 3574 3575 // Field: [5:0] FSMDIV 3576 // 3577 // ENUMs: 3578 // ALLONES All the bits are 1 3579 // ALLZEROS All the bits are 0 3580 #define LRFDRFE32_PRE3_PRE2_FSMDIV_W 6U 3581 #define LRFDRFE32_PRE3_PRE2_FSMDIV_M 0x0000003FU 3582 #define LRFDRFE32_PRE3_PRE2_FSMDIV_S 0U 3583 #define LRFDRFE32_PRE3_PRE2_FSMDIV_ALLONES 0x0000003FU 3584 #define LRFDRFE32_PRE3_PRE2_FSMDIV_ALLZEROS 0x00000000U 3585 3586 //***************************************************************************** 3587 // 3588 // Register: LRFDRFE32_O_CAL1_CAL0 3589 // 3590 //***************************************************************************** 3591 // Field: [31] CAL1_SPARE15 3592 // 3593 // ENUMs: 3594 // ONE The bit is 1 3595 // ZERO The bit is 0 3596 #define LRFDRFE32_CAL1_CAL0_CAL1_SPARE15 0x80000000U 3597 #define LRFDRFE32_CAL1_CAL0_CAL1_SPARE15_M 0x80000000U 3598 #define LRFDRFE32_CAL1_CAL0_CAL1_SPARE15_S 31U 3599 #define LRFDRFE32_CAL1_CAL0_CAL1_SPARE15_ONE 0x80000000U 3600 #define LRFDRFE32_CAL1_CAL0_CAL1_SPARE15_ZERO 0x00000000U 3601 3602 // Field: [30:24] CAL1_FCTOP 3603 // 3604 // ENUMs: 3605 // ALLONES All the bits are 1 3606 // ALLZEROS All the bits are 0 3607 #define LRFDRFE32_CAL1_CAL0_CAL1_FCTOP_W 7U 3608 #define LRFDRFE32_CAL1_CAL0_CAL1_FCTOP_M 0x7F000000U 3609 #define LRFDRFE32_CAL1_CAL0_CAL1_FCTOP_S 24U 3610 #define LRFDRFE32_CAL1_CAL0_CAL1_FCTOP_ALLONES 0x7F000000U 3611 #define LRFDRFE32_CAL1_CAL0_CAL1_FCTOP_ALLZEROS 0x00000000U 3612 3613 // Field: [23] CAL1_SPARE7 3614 // 3615 // ENUMs: 3616 // ONE The bit is 1 3617 // ZERO The bit is 0 3618 #define LRFDRFE32_CAL1_CAL0_CAL1_SPARE7 0x00800000U 3619 #define LRFDRFE32_CAL1_CAL0_CAL1_SPARE7_M 0x00800000U 3620 #define LRFDRFE32_CAL1_CAL0_CAL1_SPARE7_S 23U 3621 #define LRFDRFE32_CAL1_CAL0_CAL1_SPARE7_ONE 0x00800000U 3622 #define LRFDRFE32_CAL1_CAL0_CAL1_SPARE7_ZERO 0x00000000U 3623 3624 // Field: [22:16] CAL1_FCBOT 3625 // 3626 // ENUMs: 3627 // ALLONES All the bits are 1 3628 // ALLZEROS All the bits are 0 3629 #define LRFDRFE32_CAL1_CAL0_CAL1_FCBOT_W 7U 3630 #define LRFDRFE32_CAL1_CAL0_CAL1_FCBOT_M 0x007F0000U 3631 #define LRFDRFE32_CAL1_CAL0_CAL1_FCBOT_S 16U 3632 #define LRFDRFE32_CAL1_CAL0_CAL1_FCBOT_ALLONES 0x007F0000U 3633 #define LRFDRFE32_CAL1_CAL0_CAL1_FCBOT_ALLZEROS 0x00000000U 3634 3635 // Field: [15] CAL0_SPARE15 3636 // 3637 // ENUMs: 3638 // ONE The bit is 1 3639 // ZERO The bit is 0 3640 #define LRFDRFE32_CAL1_CAL0_CAL0_SPARE15 0x00008000U 3641 #define LRFDRFE32_CAL1_CAL0_CAL0_SPARE15_M 0x00008000U 3642 #define LRFDRFE32_CAL1_CAL0_CAL0_SPARE15_S 15U 3643 #define LRFDRFE32_CAL1_CAL0_CAL0_SPARE15_ONE 0x00008000U 3644 #define LRFDRFE32_CAL1_CAL0_CAL0_SPARE15_ZERO 0x00000000U 3645 3646 // Field: [14:8] CAL0_FCSTART 3647 // 3648 // ENUMs: 3649 // ALLONES All the bits are 1 3650 // ALLZEROS All the bits are 0 3651 #define LRFDRFE32_CAL1_CAL0_CAL0_FCSTART_W 7U 3652 #define LRFDRFE32_CAL1_CAL0_CAL0_FCSTART_M 0x00007F00U 3653 #define LRFDRFE32_CAL1_CAL0_CAL0_FCSTART_S 8U 3654 #define LRFDRFE32_CAL1_CAL0_CAL0_FCSTART_ALLONES 0x00007F00U 3655 #define LRFDRFE32_CAL1_CAL0_CAL0_FCSTART_ALLZEROS 0x00000000U 3656 3657 // Field: [7] CAL0_CRS 3658 // 3659 // ENUMs: 3660 // EN Enable coarse calibration 3661 // DIS Disable coarse calibration 3662 #define LRFDRFE32_CAL1_CAL0_CAL0_CRS 0x00000080U 3663 #define LRFDRFE32_CAL1_CAL0_CAL0_CRS_M 0x00000080U 3664 #define LRFDRFE32_CAL1_CAL0_CAL0_CRS_S 7U 3665 #define LRFDRFE32_CAL1_CAL0_CAL0_CRS_EN 0x00000080U 3666 #define LRFDRFE32_CAL1_CAL0_CAL0_CRS_DIS 0x00000000U 3667 3668 // Field: [6] CAL0_MID 3669 // 3670 // ENUMs: 3671 // EN Enable mid calibration 3672 // DIS Disable mid calibration 3673 #define LRFDRFE32_CAL1_CAL0_CAL0_MID 0x00000040U 3674 #define LRFDRFE32_CAL1_CAL0_CAL0_MID_M 0x00000040U 3675 #define LRFDRFE32_CAL1_CAL0_CAL0_MID_S 6U 3676 #define LRFDRFE32_CAL1_CAL0_CAL0_MID_EN 0x00000040U 3677 #define LRFDRFE32_CAL1_CAL0_CAL0_MID_DIS 0x00000000U 3678 3679 // Field: [5] CAL0_KTDC 3680 // 3681 // ENUMs: 3682 // EN Enable TDC estimation 3683 // DIS Disable TDC estimation 3684 #define LRFDRFE32_CAL1_CAL0_CAL0_KTDC 0x00000020U 3685 #define LRFDRFE32_CAL1_CAL0_CAL0_KTDC_M 0x00000020U 3686 #define LRFDRFE32_CAL1_CAL0_CAL0_KTDC_S 5U 3687 #define LRFDRFE32_CAL1_CAL0_CAL0_KTDC_EN 0x00000020U 3688 #define LRFDRFE32_CAL1_CAL0_CAL0_KTDC_DIS 0x00000000U 3689 3690 // Field: [4] CAL0_KDCO 3691 // 3692 // ENUMs: 3693 // EN Enable KDCO estimation 3694 // DIS Disable KDCO estimation 3695 #define LRFDRFE32_CAL1_CAL0_CAL0_KDCO 0x00000010U 3696 #define LRFDRFE32_CAL1_CAL0_CAL0_KDCO_M 0x00000010U 3697 #define LRFDRFE32_CAL1_CAL0_CAL0_KDCO_S 4U 3698 #define LRFDRFE32_CAL1_CAL0_CAL0_KDCO_EN 0x00000010U 3699 #define LRFDRFE32_CAL1_CAL0_CAL0_KDCO_DIS 0x00000000U 3700 3701 // Field: [3:2] CAL0_TDCAVG 3702 // 3703 // ENUMs: 3704 // REPEAT_8_TIMES Repeat measurement 8 times 3705 // REPEAT_4_TIMES Repeat measurement 4 times 3706 // REPEAT_2_TIMES Repeat measurement 2 times 3707 // REPEAT_1_TIME Repeat measurement 1 time 3708 #define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_W 2U 3709 #define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_M 0x0000000CU 3710 #define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_S 2U 3711 #define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_REPEAT_8_TIMES 0x0000000CU 3712 #define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_REPEAT_4_TIMES 0x00000008U 3713 #define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_REPEAT_2_TIMES 0x00000004U 3714 #define LRFDRFE32_CAL1_CAL0_CAL0_TDCAVG_REPEAT_1_TIME 0x00000000U 3715 3716 // Field: [1:0] CAL0_TDC_SPARE 3717 // 3718 // ENUMs: 3719 // ALLONES All the bits are 1 3720 // ALLZEROS All the bits are 0 3721 #define LRFDRFE32_CAL1_CAL0_CAL0_TDC_SPARE_W 2U 3722 #define LRFDRFE32_CAL1_CAL0_CAL0_TDC_SPARE_M 0x00000003U 3723 #define LRFDRFE32_CAL1_CAL0_CAL0_TDC_SPARE_S 0U 3724 #define LRFDRFE32_CAL1_CAL0_CAL0_TDC_SPARE_ALLONES 0x00000003U 3725 #define LRFDRFE32_CAL1_CAL0_CAL0_TDC_SPARE_ALLZEROS 0x00000000U 3726 3727 //***************************************************************************** 3728 // 3729 // Register: LRFDRFE32_O_CAL3_CAL2 3730 // 3731 //***************************************************************************** 3732 // Field: [31:16] DTXGAIN 3733 // 3734 // ENUMs: 3735 // ALLONES All the bits are 1 3736 // ALLZEROS All the bits are 0 3737 #define LRFDRFE32_CAL3_CAL2_DTXGAIN_W 16U 3738 #define LRFDRFE32_CAL3_CAL2_DTXGAIN_M 0xFFFF0000U 3739 #define LRFDRFE32_CAL3_CAL2_DTXGAIN_S 16U 3740 #define LRFDRFE32_CAL3_CAL2_DTXGAIN_ALLONES 0xFFFF0000U 3741 #define LRFDRFE32_CAL3_CAL2_DTXGAIN_ALLZEROS 0x00000000U 3742 3743 // Field: [15:0] KTDCINV 3744 // 3745 // ENUMs: 3746 // ALLONES All the bits are 1 3747 // ALLZEROS All the bits are 0 3748 #define LRFDRFE32_CAL3_CAL2_KTDCINV_W 16U 3749 #define LRFDRFE32_CAL3_CAL2_KTDCINV_M 0x0000FFFFU 3750 #define LRFDRFE32_CAL3_CAL2_KTDCINV_S 0U 3751 #define LRFDRFE32_CAL3_CAL2_KTDCINV_ALLONES 0x0000FFFFU 3752 #define LRFDRFE32_CAL3_CAL2_KTDCINV_ALLZEROS 0x00000000U 3753 3754 //***************************************************************************** 3755 // 3756 // Register: LRFDRFE32_O_MISC1_MISC0 3757 // 3758 //***************************************************************************** 3759 // Field: [30] FCDEMCLK 3760 // 3761 // ENUMs: 3762 // CKVD64 ckvd64 clock used for update upper and lower DWA 3763 // DEM 3764 // CKCD16 ckvd16 clock used for update upper and lower DWA 3765 // DEM 3766 #define LRFDRFE32_MISC1_MISC0_FCDEMCLK 0x40000000U 3767 #define LRFDRFE32_MISC1_MISC0_FCDEMCLK_M 0x40000000U 3768 #define LRFDRFE32_MISC1_MISC0_FCDEMCLK_S 30U 3769 #define LRFDRFE32_MISC1_MISC0_FCDEMCLK_CKVD64 0x40000000U 3770 #define LRFDRFE32_MISC1_MISC0_FCDEMCLK_CKCD16 0x00000000U 3771 3772 // Field: [29:28] FCDEMUPD 3773 // 3774 // ENUMs: 3775 // SDM_XOR_PH_ERR phase_error[0] xor SDM[1] 3776 // SDM SDM[1] (this value depends on DEM for SDM) 3777 // PH_ERR phase_error[0]. (Phase error is 6.11s ) 3778 // DEFAULT Default: Update both DWAs always at rising edge of 3779 // selected clock 3780 #define LRFDRFE32_MISC1_MISC0_FCDEMUPD_W 2U 3781 #define LRFDRFE32_MISC1_MISC0_FCDEMUPD_M 0x30000000U 3782 #define LRFDRFE32_MISC1_MISC0_FCDEMUPD_S 28U 3783 #define LRFDRFE32_MISC1_MISC0_FCDEMUPD_SDM_XOR_PH_ERR 0x30000000U 3784 #define LRFDRFE32_MISC1_MISC0_FCDEMUPD_SDM 0x20000000U 3785 #define LRFDRFE32_MISC1_MISC0_FCDEMUPD_PH_ERR 0x10000000U 3786 #define LRFDRFE32_MISC1_MISC0_FCDEMUPD_DEFAULT 0x00000000U 3787 3788 // Field: [27:22] TDCINL 3789 // 3790 // ENUMs: 3791 // ONES All bits are one 3792 // ZEROS All bits are zero 3793 #define LRFDRFE32_MISC1_MISC0_TDCINL_W 6U 3794 #define LRFDRFE32_MISC1_MISC0_TDCINL_M 0x0FC00000U 3795 #define LRFDRFE32_MISC1_MISC0_TDCINL_S 22U 3796 #define LRFDRFE32_MISC1_MISC0_TDCINL_ONES 0x0FC00000U 3797 #define LRFDRFE32_MISC1_MISC0_TDCINL_ZEROS 0x00000000U 3798 3799 // Field: [21] TDCINLCTL 3800 // 3801 // ENUMs: 3802 // EN Enables INL correction of TDC 3803 // DIS Disabled INL correction 3804 #define LRFDRFE32_MISC1_MISC0_TDCINLCTL 0x00200000U 3805 #define LRFDRFE32_MISC1_MISC0_TDCINLCTL_M 0x00200000U 3806 #define LRFDRFE32_MISC1_MISC0_TDCINLCTL_S 21U 3807 #define LRFDRFE32_MISC1_MISC0_TDCINLCTL_EN 0x00200000U 3808 #define LRFDRFE32_MISC1_MISC0_TDCINLCTL_DIS 0x00000000U 3809 3810 // Field: [20] PHINIT 3811 // 3812 // ENUMs: 3813 // UNKNOWN Unknown phase 3814 // KNOWN Known phase 3815 #define LRFDRFE32_MISC1_MISC0_PHINIT 0x00100000U 3816 #define LRFDRFE32_MISC1_MISC0_PHINIT_M 0x00100000U 3817 #define LRFDRFE32_MISC1_MISC0_PHINIT_S 20U 3818 #define LRFDRFE32_MISC1_MISC0_PHINIT_UNKNOWN 0x00100000U 3819 #define LRFDRFE32_MISC1_MISC0_PHINIT_KNOWN 0x00000000U 3820 3821 // Field: [19] SDMOOVRCTL 3822 // 3823 // ENUMs: 3824 // EN Enable SDM output override 3825 // DIS Disable SDM output override 3826 #define LRFDRFE32_MISC1_MISC0_SDMOOVRCTL 0x00080000U 3827 #define LRFDRFE32_MISC1_MISC0_SDMOOVRCTL_M 0x00080000U 3828 #define LRFDRFE32_MISC1_MISC0_SDMOOVRCTL_S 19U 3829 #define LRFDRFE32_MISC1_MISC0_SDMOOVRCTL_EN 0x00080000U 3830 #define LRFDRFE32_MISC1_MISC0_SDMOOVRCTL_DIS 0x00000000U 3831 3832 // Field: [18:16] SDMOOVR 3833 // 3834 // ENUMs: 3835 // ALLONES All the bits are 1 3836 // ALLZEROS All the bits are 0 3837 #define LRFDRFE32_MISC1_MISC0_SDMOOVR_W 3U 3838 #define LRFDRFE32_MISC1_MISC0_SDMOOVR_M 0x00070000U 3839 #define LRFDRFE32_MISC1_MISC0_SDMOOVR_S 16U 3840 #define LRFDRFE32_MISC1_MISC0_SDMOOVR_ALLONES 0x00070000U 3841 #define LRFDRFE32_MISC1_MISC0_SDMOOVR_ALLZEROS 0x00000000U 3842 3843 // Field: [13] PHCPT 3844 // 3845 // ENUMs: 3846 // ASYNC Phase capture mode is asyncrhonous 3847 // SYNC Phase capture mode is synchronous 3848 #define LRFDRFE32_MISC1_MISC0_PHCPT 0x00002000U 3849 #define LRFDRFE32_MISC1_MISC0_PHCPT_M 0x00002000U 3850 #define LRFDRFE32_MISC1_MISC0_PHCPT_S 13U 3851 #define LRFDRFE32_MISC1_MISC0_PHCPT_ASYNC 0x00002000U 3852 #define LRFDRFE32_MISC1_MISC0_PHCPT_SYNC 0x00000000U 3853 3854 // Field: [12] TDCCALCORR 3855 // 3856 // ENUMs: 3857 // EN Enable TDC error correction inside DLO. 3858 // DIS Disable TDC error correction inside DLO. 3859 #define LRFDRFE32_MISC1_MISC0_TDCCALCORR 0x00001000U 3860 #define LRFDRFE32_MISC1_MISC0_TDCCALCORR_M 0x00001000U 3861 #define LRFDRFE32_MISC1_MISC0_TDCCALCORR_S 12U 3862 #define LRFDRFE32_MISC1_MISC0_TDCCALCORR_EN 0x00001000U 3863 #define LRFDRFE32_MISC1_MISC0_TDCCALCORR_DIS 0x00000000U 3864 3865 // Field: [11] TDCMSBCORR 3866 // 3867 // ENUMs: 3868 // EN Enable TDC error correction inside DLO. 3869 // DIS Disable TDC error correction inside DLO. 3870 #define LRFDRFE32_MISC1_MISC0_TDCMSBCORR 0x00000800U 3871 #define LRFDRFE32_MISC1_MISC0_TDCMSBCORR_M 0x00000800U 3872 #define LRFDRFE32_MISC1_MISC0_TDCMSBCORR_S 11U 3873 #define LRFDRFE32_MISC1_MISC0_TDCMSBCORR_EN 0x00000800U 3874 #define LRFDRFE32_MISC1_MISC0_TDCMSBCORR_DIS 0x00000000U 3875 3876 // Field: [10] SDMDEM 3877 // 3878 // ENUMs: 3879 // EN Enable dynamic element matching (recommended) 3880 // DIS Disable dynamic element matching 3881 #define LRFDRFE32_MISC1_MISC0_SDMDEM 0x00000400U 3882 #define LRFDRFE32_MISC1_MISC0_SDMDEM_M 0x00000400U 3883 #define LRFDRFE32_MISC1_MISC0_SDMDEM_S 10U 3884 #define LRFDRFE32_MISC1_MISC0_SDMDEM_EN 0x00000400U 3885 #define LRFDRFE32_MISC1_MISC0_SDMDEM_DIS 0x00000000U 3886 3887 // Field: [9:8] DLYSDM 3888 // 3889 // ENUMs: 3890 // CKVD16_3_PER Delay integer fine code by 3 CKVD16 clock periods 3891 // CKVD16_2_PER Delay integer fine code by 2 CKVD16 clock periods 3892 // CKVD16_1_PER Delay integer fine code by 1 CKVD16 clock period 3893 // CKVD16_0_PER Delay integer fine code by 0 CKVD16 clock periods 3894 #define LRFDRFE32_MISC1_MISC0_DLYSDM_W 2U 3895 #define LRFDRFE32_MISC1_MISC0_DLYSDM_M 0x00000300U 3896 #define LRFDRFE32_MISC1_MISC0_DLYSDM_S 8U 3897 #define LRFDRFE32_MISC1_MISC0_DLYSDM_CKVD16_3_PER 0x00000300U 3898 #define LRFDRFE32_MISC1_MISC0_DLYSDM_CKVD16_2_PER 0x00000200U 3899 #define LRFDRFE32_MISC1_MISC0_DLYSDM_CKVD16_1_PER 0x00000100U 3900 #define LRFDRFE32_MISC1_MISC0_DLYSDM_CKVD16_0_PER 0x00000000U 3901 3902 // Field: [6] DLYPHVALID 3903 // 3904 // ENUMs: 3905 // CKVD16_1_PER Delays the variable phase capture and hence the 3906 // phase error calculation with 1 CKVD16 clock 3907 // period. 3908 // CKVD16_0_PER No additional delay on variable phase capture. 3909 #define LRFDRFE32_MISC1_MISC0_DLYPHVALID 0x00000040U 3910 #define LRFDRFE32_MISC1_MISC0_DLYPHVALID_M 0x00000040U 3911 #define LRFDRFE32_MISC1_MISC0_DLYPHVALID_S 6U 3912 #define LRFDRFE32_MISC1_MISC0_DLYPHVALID_CKVD16_1_PER 0x00000040U 3913 #define LRFDRFE32_MISC1_MISC0_DLYPHVALID_CKVD16_0_PER 0x00000000U 3914 3915 // Field: [5:4] DLYCANCRS 3916 // 3917 // ENUMs: 3918 // CKVD64_3_PER Delay by 3 CKVD64 clock periods 3919 // CKVD64_2_PER Delay by 2 CKVD64 clock periods 3920 // CKVD64_1_PER Delay by 1 CKVD64 clock period 3921 // CKVD64_0_PER Delay by 0 CKVD64 clock periods 3922 #define LRFDRFE32_MISC1_MISC0_DLYCANCRS_W 2U 3923 #define LRFDRFE32_MISC1_MISC0_DLYCANCRS_M 0x00000030U 3924 #define LRFDRFE32_MISC1_MISC0_DLYCANCRS_S 4U 3925 #define LRFDRFE32_MISC1_MISC0_DLYCANCRS_CKVD64_3_PER 0x00000030U 3926 #define LRFDRFE32_MISC1_MISC0_DLYCANCRS_CKVD64_2_PER 0x00000020U 3927 #define LRFDRFE32_MISC1_MISC0_DLYCANCRS_CKVD64_1_PER 0x00000010U 3928 #define LRFDRFE32_MISC1_MISC0_DLYCANCRS_CKVD64_0_PER 0x00000000U 3929 3930 // Field: [3:2] DLYCANFINE 3931 // 3932 // ENUMs: 3933 // CKVD16_4_PER Delay by 4 CKVD16 clock periods 3934 // CKVD16_3_PER Delay by 3 CKVD16 clock periods 3935 // CKVD16_2_PER Delay by 2 CKVD16 clock period 3936 // CKVD16_1_PER Delay by 1 CKVD16 clock periods 3937 #define LRFDRFE32_MISC1_MISC0_DLYCANFINE_W 2U 3938 #define LRFDRFE32_MISC1_MISC0_DLYCANFINE_M 0x0000000CU 3939 #define LRFDRFE32_MISC1_MISC0_DLYCANFINE_S 2U 3940 #define LRFDRFE32_MISC1_MISC0_DLYCANFINE_CKVD16_4_PER 0x0000000CU 3941 #define LRFDRFE32_MISC1_MISC0_DLYCANFINE_CKVD16_3_PER 0x00000008U 3942 #define LRFDRFE32_MISC1_MISC0_DLYCANFINE_CKVD16_2_PER 0x00000004U 3943 #define LRFDRFE32_MISC1_MISC0_DLYCANFINE_CKVD16_1_PER 0x00000000U 3944 3945 // Field: [1:0] DLYADD 3946 // 3947 // ENUMs: 3948 // CKVD64_3_PER Delay by 3 CKVD64 clock periods 3949 // CKVD64_2_PER Delay by 2 CKVD64 clock periods 3950 // CKVD64_1_PER Delay by 1 CKVD64 clock period 3951 // CKVD64_0_PER Delay by 0 CKVD64 clock periods 3952 #define LRFDRFE32_MISC1_MISC0_DLYADD_W 2U 3953 #define LRFDRFE32_MISC1_MISC0_DLYADD_M 0x00000003U 3954 #define LRFDRFE32_MISC1_MISC0_DLYADD_S 0U 3955 #define LRFDRFE32_MISC1_MISC0_DLYADD_CKVD64_3_PER 0x00000003U 3956 #define LRFDRFE32_MISC1_MISC0_DLYADD_CKVD64_2_PER 0x00000002U 3957 #define LRFDRFE32_MISC1_MISC0_DLYADD_CKVD64_1_PER 0x00000001U 3958 #define LRFDRFE32_MISC1_MISC0_DLYADD_CKVD64_0_PER 0x00000000U 3959 3960 //***************************************************************************** 3961 // 3962 // Register: LRFDRFE32_O_LF1_LF0 3963 // 3964 //***************************************************************************** 3965 // Field: [29:16] KP 3966 // 3967 // ENUMs: 3968 // ALLONES All the bits are 1 3969 // ALLZEROS All the bits are 0 3970 #define LRFDRFE32_LF1_LF0_KP_W 14U 3971 #define LRFDRFE32_LF1_LF0_KP_M 0x3FFF0000U 3972 #define LRFDRFE32_LF1_LF0_KP_S 16U 3973 #define LRFDRFE32_LF1_LF0_KP_ALLONES 0x3FFF0000U 3974 #define LRFDRFE32_LF1_LF0_KP_ALLZEROS 0x00000000U 3975 3976 // Field: [12] KIPREC 3977 // 3978 // ENUMs: 3979 // HIGH KI encoding is <4.08> 3980 // LOW KI encoding is <12.0u> 3981 #define LRFDRFE32_LF1_LF0_KIPREC 0x00001000U 3982 #define LRFDRFE32_LF1_LF0_KIPREC_M 0x00001000U 3983 #define LRFDRFE32_LF1_LF0_KIPREC_S 12U 3984 #define LRFDRFE32_LF1_LF0_KIPREC_HIGH 0x00001000U 3985 #define LRFDRFE32_LF1_LF0_KIPREC_LOW 0x00000000U 3986 3987 // Field: [11:0] KI 3988 // 3989 // ENUMs: 3990 // ALLONES All the bits are 1 3991 // ALLZEROS All the bits are 0 3992 #define LRFDRFE32_LF1_LF0_KI_W 12U 3993 #define LRFDRFE32_LF1_LF0_KI_M 0x00000FFFU 3994 #define LRFDRFE32_LF1_LF0_KI_S 0U 3995 #define LRFDRFE32_LF1_LF0_KI_ALLONES 0x00000FFFU 3996 #define LRFDRFE32_LF1_LF0_KI_ALLZEROS 0x00000000U 3997 3998 //***************************************************************************** 3999 // 4000 // Register: LRFDRFE32_O_PHINIT_PHEDISC 4001 // 4002 //***************************************************************************** 4003 // Field: [23:16] OFF 4004 // 4005 // ENUMs: 4006 // ALLONES All the bits are 1 4007 // ALLZEROS All the bits are 0 4008 #define LRFDRFE32_PHINIT_PHEDISC_OFF_W 8U 4009 #define LRFDRFE32_PHINIT_PHEDISC_OFF_M 0x00FF0000U 4010 #define LRFDRFE32_PHINIT_PHEDISC_OFF_S 16U 4011 #define LRFDRFE32_PHINIT_PHEDISC_OFF_ALLONES 0x00FF0000U 4012 #define LRFDRFE32_PHINIT_PHEDISC_OFF_ALLZEROS 0x00000000U 4013 4014 // Field: [13:10] CNT 4015 // 4016 // ENUMs: 4017 // ALLONES All the bits are 1 4018 // ALLZEROS All the bits are 0 4019 #define LRFDRFE32_PHINIT_PHEDISC_CNT_W 4U 4020 #define LRFDRFE32_PHINIT_PHEDISC_CNT_M 0x00003C00U 4021 #define LRFDRFE32_PHINIT_PHEDISC_CNT_S 10U 4022 #define LRFDRFE32_PHINIT_PHEDISC_CNT_ALLONES 0x00003C00U 4023 #define LRFDRFE32_PHINIT_PHEDISC_CNT_ALLZEROS 0x00000000U 4024 4025 // Field: [9:0] THR 4026 // 4027 // ENUMs: 4028 // ALLONES All the bits are 1 4029 // ALLZEROS All the bits are 0 4030 #define LRFDRFE32_PHINIT_PHEDISC_THR_W 10U 4031 #define LRFDRFE32_PHINIT_PHEDISC_THR_M 0x000003FFU 4032 #define LRFDRFE32_PHINIT_PHEDISC_THR_S 0U 4033 #define LRFDRFE32_PHINIT_PHEDISC_THR_ALLONES 0x000003FFU 4034 #define LRFDRFE32_PHINIT_PHEDISC_THR_ALLZEROS 0x00000000U 4035 4036 //***************************************************************************** 4037 // 4038 // Register: LRFDRFE32_O_PLLMON1_PLLMON0 4039 // 4040 //***************************************************************************** 4041 // Field: [28:24] PHELOCKCNT 4042 // 4043 // ENUMs: 4044 // ALLONES All the bits are 1 4045 // ALLZEROS All the bits are 0 4046 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKCNT_W 5U 4047 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKCNT_M 0x1F000000U 4048 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKCNT_S 24U 4049 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKCNT_ALLONES 0x1F000000U 4050 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKCNT_ALLZEROS 0x00000000U 4051 4052 // Field: [23:16] PHELOCKTHR 4053 // 4054 // ENUMs: 4055 // ALLONES All the bits are 1 4056 // ALLZEROS All the bits are 0 4057 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKTHR_W 8U 4058 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKTHR_M 0x00FF0000U 4059 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKTHR_S 16U 4060 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKTHR_ALLONES 0x00FF0000U 4061 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOCKTHR_ALLZEROS 0x00000000U 4062 4063 // Field: [15:14] PHELOLCNT 4064 // 4065 // ENUMs: 4066 // REFCLK_128_PER Threshold count is 128 REFCLK periods 4067 // REFCLK_64_PER Threshold count is 64 REFCLK periods 4068 // REFCLK_32_PER Threshold count is 32 REFCLK periods 4069 // REFCLK_16_PER Threshold count is 16 REFCLK periods 4070 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_W 2U 4071 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_M 0x0000C000U 4072 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_S 14U 4073 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_REFCLK_128_PER 0x0000C000U 4074 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_REFCLK_64_PER 0x00008000U 4075 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_REFCLK_32_PER 0x00004000U 4076 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOLCNT_REFCLK_16_PER 0x00000000U 4077 4078 // Field: [13:8] PHELOLTHR 4079 // 4080 // ENUMs: 4081 // ALLONES All the bits are 1 4082 // ALLZEROS All the bits are 0 4083 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOLTHR_W 6U 4084 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOLTHR_M 0x00003F00U 4085 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOLTHR_S 8U 4086 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOLTHR_ALLONES 0x00003F00U 4087 #define LRFDRFE32_PLLMON1_PLLMON0_PHELOLTHR_ALLZEROS 0x00000000U 4088 4089 // Field: [6:0] FCTHR 4090 // 4091 // ENUMs: 4092 // ALLONES All the bits are 1 4093 // ALLZEROS All the bits are 0 4094 #define LRFDRFE32_PLLMON1_PLLMON0_FCTHR_W 7U 4095 #define LRFDRFE32_PLLMON1_PLLMON0_FCTHR_M 0x0000007FU 4096 #define LRFDRFE32_PLLMON1_PLLMON0_FCTHR_S 0U 4097 #define LRFDRFE32_PLLMON1_PLLMON0_FCTHR_ALLONES 0x0000007FU 4098 #define LRFDRFE32_PLLMON1_PLLMON0_FCTHR_ALLZEROS 0x00000000U 4099 4100 //***************************************************************************** 4101 // 4102 // Register: LRFDRFE32_O_MOD1_MOD0 4103 // 4104 //***************************************************************************** 4105 // Field: [27:16] FOFF 4106 // 4107 // ENUMs: 4108 // ALLONES All the bits are 1 4109 // ALLZEROS All the bits are 0 4110 #define LRFDRFE32_MOD1_MOD0_FOFF_W 12U 4111 #define LRFDRFE32_MOD1_MOD0_FOFF_M 0x0FFF0000U 4112 #define LRFDRFE32_MOD1_MOD0_FOFF_S 16U 4113 #define LRFDRFE32_MOD1_MOD0_FOFF_ALLONES 0x0FFF0000U 4114 #define LRFDRFE32_MOD1_MOD0_FOFF_ALLZEROS 0x00000000U 4115 4116 // Field: [12:11] SCHEME 4117 // 4118 // ENUMs: 4119 // TWO_POINT_MOD_FRF 2-point modulation with FRF resolution MOD_RES = 4120 // FRF / 2^(21+CANPTHGAIN) Scheme supports both 4121 // open -and closed-loop operation. Scheme allows 4122 // wider modulation bandwiths than INLOOP_MOD_FRF. 4123 // INLOOP_MOD_FRF In-loop modulation with FRF resolution MOD_RES = 4124 // FRF / 2^(21+CANPTHGAIN) 4125 // INLOOP_MOD_FREF In-loop modulation with FREF resolution MOD_RES = 4126 // FREF / (DIVIDER/2) / 2^(15+CANPTHGAIN) 4127 // DIV.RATIO determines DIVIDER configuration. 4128 // Scheme only supports closed-loop operation. 4129 // NC No connect Modulator output does not add to 4130 // frequencey control word from PLL. 4131 #define LRFDRFE32_MOD1_MOD0_SCHEME_W 2U 4132 #define LRFDRFE32_MOD1_MOD0_SCHEME_M 0x00001800U 4133 #define LRFDRFE32_MOD1_MOD0_SCHEME_S 11U 4134 #define LRFDRFE32_MOD1_MOD0_SCHEME_TWO_POINT_MOD_FRF 0x00001800U 4135 #define LRFDRFE32_MOD1_MOD0_SCHEME_INLOOP_MOD_FRF 0x00001000U 4136 #define LRFDRFE32_MOD1_MOD0_SCHEME_INLOOP_MOD_FREF 0x00000800U 4137 #define LRFDRFE32_MOD1_MOD0_SCHEME_NC 0x00000000U 4138 4139 // Field: [10:8] SYMSHP 4140 // 4141 // ENUMs: 4142 // CHIRP Chirp modulation 4143 // SHAPEDZIGBEE Use Shaped 802.15.4 modulation 4144 // PCWSPSK Use piecewise linear PSK shaper defined by 4145 // SHAPECFG* registers. 4146 // ZIGBEE Use unshaped zigbee 4147 // SHAPEDFSK Use generic 3 symbol shaper defined by SHAPECFG* 4148 // registers. 4149 #define LRFDRFE32_MOD1_MOD0_SYMSHP_W 3U 4150 #define LRFDRFE32_MOD1_MOD0_SYMSHP_M 0x00000700U 4151 #define LRFDRFE32_MOD1_MOD0_SYMSHP_S 8U 4152 #define LRFDRFE32_MOD1_MOD0_SYMSHP_CHIRP 0x00000400U 4153 #define LRFDRFE32_MOD1_MOD0_SYMSHP_SHAPEDZIGBEE 0x00000300U 4154 #define LRFDRFE32_MOD1_MOD0_SYMSHP_PCWSPSK 0x00000200U 4155 #define LRFDRFE32_MOD1_MOD0_SYMSHP_ZIGBEE 0x00000100U 4156 #define LRFDRFE32_MOD1_MOD0_SYMSHP_SHAPEDFSK 0x00000000U 4157 4158 // Field: [7:6] CANPTHGAIN 4159 // 4160 // ENUMs: 4161 // TWO_POW_M_18 POW(2,-18) 4162 // TWO_POW_M_17 POW(2,-17) 4163 // TWO_POW_M_16 POW(2,-16) 4164 // TWO_POW_M_15 POW(2,-15) 4165 #define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_W 2U 4166 #define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_M 0x000000C0U 4167 #define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_S 6U 4168 #define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_TWO_POW_M_18 0x000000C0U 4169 #define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_TWO_POW_M_17 0x00000080U 4170 #define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_TWO_POW_M_16 0x00000040U 4171 #define LRFDRFE32_MOD1_MOD0_CANPTHGAIN_TWO_POW_M_15 0x00000000U 4172 4173 // Field: [5:4] SHPGAIN 4174 // 4175 // ENUMs: 4176 // X8 Shape gain = 8 4177 // X4 Shape gain = 4 4178 // X2 Shape gain = 2 4179 // X1 Shape gain = 1 4180 #define LRFDRFE32_MOD1_MOD0_SHPGAIN_W 2U 4181 #define LRFDRFE32_MOD1_MOD0_SHPGAIN_M 0x00000030U 4182 #define LRFDRFE32_MOD1_MOD0_SHPGAIN_S 4U 4183 #define LRFDRFE32_MOD1_MOD0_SHPGAIN_X8 0x00000030U 4184 #define LRFDRFE32_MOD1_MOD0_SHPGAIN_X4 0x00000020U 4185 #define LRFDRFE32_MOD1_MOD0_SHPGAIN_X2 0x00000010U 4186 #define LRFDRFE32_MOD1_MOD0_SHPGAIN_X1 0x00000000U 4187 4188 // Field: [3:2] INTPFACT 4189 // 4190 // ENUMs: 4191 // ILLEGAL1 Illegal, unsupported setting 4192 // INTP_BY_32 Interpolate by 32 4193 // INTP_BY_16 Interpolate by 16 4194 // ILLEGAL0 Illegal, unsupported setting 4195 #define LRFDRFE32_MOD1_MOD0_INTPFACT_W 2U 4196 #define LRFDRFE32_MOD1_MOD0_INTPFACT_M 0x0000000CU 4197 #define LRFDRFE32_MOD1_MOD0_INTPFACT_S 2U 4198 #define LRFDRFE32_MOD1_MOD0_INTPFACT_ILLEGAL1 0x0000000CU 4199 #define LRFDRFE32_MOD1_MOD0_INTPFACT_INTP_BY_32 0x00000008U 4200 #define LRFDRFE32_MOD1_MOD0_INTPFACT_INTP_BY_16 0x00000004U 4201 #define LRFDRFE32_MOD1_MOD0_INTPFACT_ILLEGAL0 0x00000000U 4202 4203 //***************************************************************************** 4204 // 4205 // Register: LRFDRFE32_O_DTX1_DTX0 4206 // 4207 //***************************************************************************** 4208 // Field: [31:24] SHP3 4209 // 4210 // ENUMs: 4211 // ALLONES All the bits are 1 4212 // ALLZEROS All the bits are 0 4213 #define LRFDRFE32_DTX1_DTX0_SHP3_W 8U 4214 #define LRFDRFE32_DTX1_DTX0_SHP3_M 0xFF000000U 4215 #define LRFDRFE32_DTX1_DTX0_SHP3_S 24U 4216 #define LRFDRFE32_DTX1_DTX0_SHP3_ALLONES 0xFF000000U 4217 #define LRFDRFE32_DTX1_DTX0_SHP3_ALLZEROS 0x00000000U 4218 4219 // Field: [23:16] SHP2 4220 // 4221 // ENUMs: 4222 // ALLONES All the bits are 1 4223 // ALLZEROS All the bits are 0 4224 #define LRFDRFE32_DTX1_DTX0_SHP2_W 8U 4225 #define LRFDRFE32_DTX1_DTX0_SHP2_M 0x00FF0000U 4226 #define LRFDRFE32_DTX1_DTX0_SHP2_S 16U 4227 #define LRFDRFE32_DTX1_DTX0_SHP2_ALLONES 0x00FF0000U 4228 #define LRFDRFE32_DTX1_DTX0_SHP2_ALLZEROS 0x00000000U 4229 4230 // Field: [15:8] SHP1 4231 // 4232 // ENUMs: 4233 // ALLONES All the bits are 1 4234 // ALLZEROS All the bits are 0 4235 #define LRFDRFE32_DTX1_DTX0_SHP1_W 8U 4236 #define LRFDRFE32_DTX1_DTX0_SHP1_M 0x0000FF00U 4237 #define LRFDRFE32_DTX1_DTX0_SHP1_S 8U 4238 #define LRFDRFE32_DTX1_DTX0_SHP1_ALLONES 0x0000FF00U 4239 #define LRFDRFE32_DTX1_DTX0_SHP1_ALLZEROS 0x00000000U 4240 4241 // Field: [7:0] SHP0 4242 // 4243 // ENUMs: 4244 // ALLONES All the bits are 1 4245 // ALLZEROS All the bits are 0 4246 #define LRFDRFE32_DTX1_DTX0_SHP0_W 8U 4247 #define LRFDRFE32_DTX1_DTX0_SHP0_M 0x000000FFU 4248 #define LRFDRFE32_DTX1_DTX0_SHP0_S 0U 4249 #define LRFDRFE32_DTX1_DTX0_SHP0_ALLONES 0x000000FFU 4250 #define LRFDRFE32_DTX1_DTX0_SHP0_ALLZEROS 0x00000000U 4251 4252 //***************************************************************************** 4253 // 4254 // Register: LRFDRFE32_O_DTX3_DTX2 4255 // 4256 //***************************************************************************** 4257 // Field: [31:24] SHP7 4258 // 4259 // ENUMs: 4260 // ALLONES All the bits are 1 4261 // ALLZEROS All the bits are 0 4262 #define LRFDRFE32_DTX3_DTX2_SHP7_W 8U 4263 #define LRFDRFE32_DTX3_DTX2_SHP7_M 0xFF000000U 4264 #define LRFDRFE32_DTX3_DTX2_SHP7_S 24U 4265 #define LRFDRFE32_DTX3_DTX2_SHP7_ALLONES 0xFF000000U 4266 #define LRFDRFE32_DTX3_DTX2_SHP7_ALLZEROS 0x00000000U 4267 4268 // Field: [23:16] SHP6 4269 // 4270 // ENUMs: 4271 // ALLONES All the bits are 1 4272 // ALLZEROS All the bits are 0 4273 #define LRFDRFE32_DTX3_DTX2_SHP6_W 8U 4274 #define LRFDRFE32_DTX3_DTX2_SHP6_M 0x00FF0000U 4275 #define LRFDRFE32_DTX3_DTX2_SHP6_S 16U 4276 #define LRFDRFE32_DTX3_DTX2_SHP6_ALLONES 0x00FF0000U 4277 #define LRFDRFE32_DTX3_DTX2_SHP6_ALLZEROS 0x00000000U 4278 4279 // Field: [15:8] SHP5 4280 // 4281 // ENUMs: 4282 // ALLONES All the bits are 1 4283 // ALLZEROS All the bits are 0 4284 #define LRFDRFE32_DTX3_DTX2_SHP5_W 8U 4285 #define LRFDRFE32_DTX3_DTX2_SHP5_M 0x0000FF00U 4286 #define LRFDRFE32_DTX3_DTX2_SHP5_S 8U 4287 #define LRFDRFE32_DTX3_DTX2_SHP5_ALLONES 0x0000FF00U 4288 #define LRFDRFE32_DTX3_DTX2_SHP5_ALLZEROS 0x00000000U 4289 4290 // Field: [7:0] SHP4 4291 // 4292 // ENUMs: 4293 // ALLONES All the bits are 1 4294 // ALLZEROS All the bits are 0 4295 #define LRFDRFE32_DTX3_DTX2_SHP4_W 8U 4296 #define LRFDRFE32_DTX3_DTX2_SHP4_M 0x000000FFU 4297 #define LRFDRFE32_DTX3_DTX2_SHP4_S 0U 4298 #define LRFDRFE32_DTX3_DTX2_SHP4_ALLONES 0x000000FFU 4299 #define LRFDRFE32_DTX3_DTX2_SHP4_ALLZEROS 0x00000000U 4300 4301 //***************************************************************************** 4302 // 4303 // Register: LRFDRFE32_O_DTX5_DTX4 4304 // 4305 //***************************************************************************** 4306 // Field: [31:24] SHP11 4307 // 4308 // ENUMs: 4309 // ALLONES All the bits are 1 4310 // ALLZEROS All the bits are 0 4311 #define LRFDRFE32_DTX5_DTX4_SHP11_W 8U 4312 #define LRFDRFE32_DTX5_DTX4_SHP11_M 0xFF000000U 4313 #define LRFDRFE32_DTX5_DTX4_SHP11_S 24U 4314 #define LRFDRFE32_DTX5_DTX4_SHP11_ALLONES 0xFF000000U 4315 #define LRFDRFE32_DTX5_DTX4_SHP11_ALLZEROS 0x00000000U 4316 4317 // Field: [23:16] SHP10 4318 // 4319 // ENUMs: 4320 // ALLONES All the bits are 1 4321 // ALLZEROS All the bits are 0 4322 #define LRFDRFE32_DTX5_DTX4_SHP10_W 8U 4323 #define LRFDRFE32_DTX5_DTX4_SHP10_M 0x00FF0000U 4324 #define LRFDRFE32_DTX5_DTX4_SHP10_S 16U 4325 #define LRFDRFE32_DTX5_DTX4_SHP10_ALLONES 0x00FF0000U 4326 #define LRFDRFE32_DTX5_DTX4_SHP10_ALLZEROS 0x00000000U 4327 4328 // Field: [15:8] SHP9 4329 // 4330 // ENUMs: 4331 // ALLONES All the bits are 1 4332 // ALLZEROS All the bits are 0 4333 #define LRFDRFE32_DTX5_DTX4_SHP9_W 8U 4334 #define LRFDRFE32_DTX5_DTX4_SHP9_M 0x0000FF00U 4335 #define LRFDRFE32_DTX5_DTX4_SHP9_S 8U 4336 #define LRFDRFE32_DTX5_DTX4_SHP9_ALLONES 0x0000FF00U 4337 #define LRFDRFE32_DTX5_DTX4_SHP9_ALLZEROS 0x00000000U 4338 4339 // Field: [7:0] SHP8 4340 // 4341 // ENUMs: 4342 // ALLONES All the bits are 1 4343 // ALLZEROS All the bits are 0 4344 #define LRFDRFE32_DTX5_DTX4_SHP8_W 8U 4345 #define LRFDRFE32_DTX5_DTX4_SHP8_M 0x000000FFU 4346 #define LRFDRFE32_DTX5_DTX4_SHP8_S 0U 4347 #define LRFDRFE32_DTX5_DTX4_SHP8_ALLONES 0x000000FFU 4348 #define LRFDRFE32_DTX5_DTX4_SHP8_ALLZEROS 0x00000000U 4349 4350 //***************************************************************************** 4351 // 4352 // Register: LRFDRFE32_O_DTX7_DTX6 4353 // 4354 //***************************************************************************** 4355 // Field: [31:24] SHP15 4356 // 4357 // ENUMs: 4358 // ALLONES All the bits are 1 4359 // ALLZEROS All the bits are 0 4360 #define LRFDRFE32_DTX7_DTX6_SHP15_W 8U 4361 #define LRFDRFE32_DTX7_DTX6_SHP15_M 0xFF000000U 4362 #define LRFDRFE32_DTX7_DTX6_SHP15_S 24U 4363 #define LRFDRFE32_DTX7_DTX6_SHP15_ALLONES 0xFF000000U 4364 #define LRFDRFE32_DTX7_DTX6_SHP15_ALLZEROS 0x00000000U 4365 4366 // Field: [23:16] SHP14 4367 // 4368 // ENUMs: 4369 // ALLONES All the bits are 1 4370 // ALLZEROS All the bits are 0 4371 #define LRFDRFE32_DTX7_DTX6_SHP14_W 8U 4372 #define LRFDRFE32_DTX7_DTX6_SHP14_M 0x00FF0000U 4373 #define LRFDRFE32_DTX7_DTX6_SHP14_S 16U 4374 #define LRFDRFE32_DTX7_DTX6_SHP14_ALLONES 0x00FF0000U 4375 #define LRFDRFE32_DTX7_DTX6_SHP14_ALLZEROS 0x00000000U 4376 4377 // Field: [15:8] SHP13 4378 // 4379 // ENUMs: 4380 // ALLONES All the bits are 1 4381 // ALLZEROS All the bits are 0 4382 #define LRFDRFE32_DTX7_DTX6_SHP13_W 8U 4383 #define LRFDRFE32_DTX7_DTX6_SHP13_M 0x0000FF00U 4384 #define LRFDRFE32_DTX7_DTX6_SHP13_S 8U 4385 #define LRFDRFE32_DTX7_DTX6_SHP13_ALLONES 0x0000FF00U 4386 #define LRFDRFE32_DTX7_DTX6_SHP13_ALLZEROS 0x00000000U 4387 4388 // Field: [7:0] SHP12 4389 // 4390 // ENUMs: 4391 // ALLONES All the bits are 1 4392 // ALLZEROS All the bits are 0 4393 #define LRFDRFE32_DTX7_DTX6_SHP12_W 8U 4394 #define LRFDRFE32_DTX7_DTX6_SHP12_M 0x000000FFU 4395 #define LRFDRFE32_DTX7_DTX6_SHP12_S 0U 4396 #define LRFDRFE32_DTX7_DTX6_SHP12_ALLONES 0x000000FFU 4397 #define LRFDRFE32_DTX7_DTX6_SHP12_ALLZEROS 0x00000000U 4398 4399 //***************************************************************************** 4400 // 4401 // Register: LRFDRFE32_O_DTX9_DTX8 4402 // 4403 //***************************************************************************** 4404 // Field: [31:24] SHP19 4405 // 4406 // ENUMs: 4407 // ALLONES All the bits are 1 4408 // ALLZEROS All the bits are 0 4409 #define LRFDRFE32_DTX9_DTX8_SHP19_W 8U 4410 #define LRFDRFE32_DTX9_DTX8_SHP19_M 0xFF000000U 4411 #define LRFDRFE32_DTX9_DTX8_SHP19_S 24U 4412 #define LRFDRFE32_DTX9_DTX8_SHP19_ALLONES 0xFF000000U 4413 #define LRFDRFE32_DTX9_DTX8_SHP19_ALLZEROS 0x00000000U 4414 4415 // Field: [23:16] SHP18 4416 // 4417 // ENUMs: 4418 // ALLONES All the bits are 1 4419 // ALLZEROS All the bits are 0 4420 #define LRFDRFE32_DTX9_DTX8_SHP18_W 8U 4421 #define LRFDRFE32_DTX9_DTX8_SHP18_M 0x00FF0000U 4422 #define LRFDRFE32_DTX9_DTX8_SHP18_S 16U 4423 #define LRFDRFE32_DTX9_DTX8_SHP18_ALLONES 0x00FF0000U 4424 #define LRFDRFE32_DTX9_DTX8_SHP18_ALLZEROS 0x00000000U 4425 4426 // Field: [15:8] SHP17 4427 // 4428 // ENUMs: 4429 // ALLONES All the bits are 1 4430 // ALLZEROS All the bits are 0 4431 #define LRFDRFE32_DTX9_DTX8_SHP17_W 8U 4432 #define LRFDRFE32_DTX9_DTX8_SHP17_M 0x0000FF00U 4433 #define LRFDRFE32_DTX9_DTX8_SHP17_S 8U 4434 #define LRFDRFE32_DTX9_DTX8_SHP17_ALLONES 0x0000FF00U 4435 #define LRFDRFE32_DTX9_DTX8_SHP17_ALLZEROS 0x00000000U 4436 4437 // Field: [7:0] SHP16 4438 // 4439 // ENUMs: 4440 // ALLONES All the bits are 1 4441 // ALLZEROS All the bits are 0 4442 #define LRFDRFE32_DTX9_DTX8_SHP16_W 8U 4443 #define LRFDRFE32_DTX9_DTX8_SHP16_M 0x000000FFU 4444 #define LRFDRFE32_DTX9_DTX8_SHP16_S 0U 4445 #define LRFDRFE32_DTX9_DTX8_SHP16_ALLONES 0x000000FFU 4446 #define LRFDRFE32_DTX9_DTX8_SHP16_ALLZEROS 0x00000000U 4447 4448 //***************************************************************************** 4449 // 4450 // Register: LRFDRFE32_O_DTX11_DTX10 4451 // 4452 //***************************************************************************** 4453 // Field: [31:24] SHP23 4454 // 4455 // ENUMs: 4456 // ALLONES All the bits are 1 4457 // ALLZEROS All the bits are 0 4458 #define LRFDRFE32_DTX11_DTX10_SHP23_W 8U 4459 #define LRFDRFE32_DTX11_DTX10_SHP23_M 0xFF000000U 4460 #define LRFDRFE32_DTX11_DTX10_SHP23_S 24U 4461 #define LRFDRFE32_DTX11_DTX10_SHP23_ALLONES 0xFF000000U 4462 #define LRFDRFE32_DTX11_DTX10_SHP23_ALLZEROS 0x00000000U 4463 4464 // Field: [23:16] SHP22 4465 // 4466 // ENUMs: 4467 // ALLONES All the bits are 1 4468 // ALLZEROS All the bits are 0 4469 #define LRFDRFE32_DTX11_DTX10_SHP22_W 8U 4470 #define LRFDRFE32_DTX11_DTX10_SHP22_M 0x00FF0000U 4471 #define LRFDRFE32_DTX11_DTX10_SHP22_S 16U 4472 #define LRFDRFE32_DTX11_DTX10_SHP22_ALLONES 0x00FF0000U 4473 #define LRFDRFE32_DTX11_DTX10_SHP22_ALLZEROS 0x00000000U 4474 4475 // Field: [15:8] SHP21 4476 // 4477 // ENUMs: 4478 // ALLONES All the bits are 1 4479 // ALLZEROS All the bits are 0 4480 #define LRFDRFE32_DTX11_DTX10_SHP21_W 8U 4481 #define LRFDRFE32_DTX11_DTX10_SHP21_M 0x0000FF00U 4482 #define LRFDRFE32_DTX11_DTX10_SHP21_S 8U 4483 #define LRFDRFE32_DTX11_DTX10_SHP21_ALLONES 0x0000FF00U 4484 #define LRFDRFE32_DTX11_DTX10_SHP21_ALLZEROS 0x00000000U 4485 4486 // Field: [7:0] SHP20 4487 // 4488 // ENUMs: 4489 // ALLONES All the bits are 1 4490 // ALLZEROS All the bits are 0 4491 #define LRFDRFE32_DTX11_DTX10_SHP20_W 8U 4492 #define LRFDRFE32_DTX11_DTX10_SHP20_M 0x000000FFU 4493 #define LRFDRFE32_DTX11_DTX10_SHP20_S 0U 4494 #define LRFDRFE32_DTX11_DTX10_SHP20_ALLONES 0x000000FFU 4495 #define LRFDRFE32_DTX11_DTX10_SHP20_ALLZEROS 0x00000000U 4496 4497 //***************************************************************************** 4498 // 4499 // Register: LRFDRFE32_O_PLLM0 4500 // 4501 //***************************************************************************** 4502 // Field: [31:2] VAL 4503 // 4504 // ENUMs: 4505 // ALLONES All the bits are 1 4506 // ALLZEROS All the bits are 0 4507 #define LRFDRFE32_PLLM0_VAL_W 30U 4508 #define LRFDRFE32_PLLM0_VAL_M 0xFFFFFFFCU 4509 #define LRFDRFE32_PLLM0_VAL_S 2U 4510 #define LRFDRFE32_PLLM0_VAL_ALLONES 0x0000FFFCU 4511 #define LRFDRFE32_PLLM0_VAL_ALLZEROS 0x00000000U 4512 4513 // Field: [1:0] SPARE0 4514 // 4515 // ENUMs: 4516 // ALLONES All the bits are 1 4517 // ALLZEROS All the bits are 0 4518 #define LRFDRFE32_PLLM0_SPARE0_W 2U 4519 #define LRFDRFE32_PLLM0_SPARE0_M 0x00000003U 4520 #define LRFDRFE32_PLLM0_SPARE0_S 0U 4521 #define LRFDRFE32_PLLM0_SPARE0_ALLONES 0x00000003U 4522 #define LRFDRFE32_PLLM0_SPARE0_ALLZEROS 0x00000000U 4523 4524 //***************************************************************************** 4525 // 4526 // Register: LRFDRFE32_O_PLLM1 4527 // 4528 //***************************************************************************** 4529 // Field: [31:2] VAL 4530 // 4531 // ENUMs: 4532 // ALLONES All the bits are 1 4533 // ALLZEROS All the bits are 0 4534 #define LRFDRFE32_PLLM1_VAL_W 30U 4535 #define LRFDRFE32_PLLM1_VAL_M 0xFFFFFFFCU 4536 #define LRFDRFE32_PLLM1_VAL_S 2U 4537 #define LRFDRFE32_PLLM1_VAL_ALLONES 0x0000FFFCU 4538 #define LRFDRFE32_PLLM1_VAL_ALLZEROS 0x00000000U 4539 4540 // Field: [1:0] SPARE0 4541 // 4542 // ENUMs: 4543 // ALLONES All the bits are 1 4544 // ALLZEROS All the bits are 0 4545 #define LRFDRFE32_PLLM1_SPARE0_W 2U 4546 #define LRFDRFE32_PLLM1_SPARE0_M 0x00000003U 4547 #define LRFDRFE32_PLLM1_SPARE0_S 0U 4548 #define LRFDRFE32_PLLM1_SPARE0_ALLONES 0x00000003U 4549 #define LRFDRFE32_PLLM1_SPARE0_ALLZEROS 0x00000000U 4550 4551 //***************************************************************************** 4552 // 4553 // Register: LRFDRFE32_O_CALMMID_CALMCRS 4554 // 4555 //***************************************************************************** 4556 // Field: [31:16] CALMMID_VAL 4557 // 4558 // ENUMs: 4559 // ALLONES All the bits are 1 4560 // ALLZEROS All the bits are 0 4561 #define LRFDRFE32_CALMMID_CALMCRS_CALMMID_VAL_W 16U 4562 #define LRFDRFE32_CALMMID_CALMCRS_CALMMID_VAL_M 0xFFFF0000U 4563 #define LRFDRFE32_CALMMID_CALMCRS_CALMMID_VAL_S 16U 4564 #define LRFDRFE32_CALMMID_CALMCRS_CALMMID_VAL_ALLONES 0xFFFF0000U 4565 #define LRFDRFE32_CALMMID_CALMCRS_CALMMID_VAL_ALLZEROS 0x00000000U 4566 4567 // Field: [15:0] CALMCRS_VAL 4568 // 4569 // ENUMs: 4570 // ALLONES All the bits are 1 4571 // ALLZEROS All the bits are 0 4572 #define LRFDRFE32_CALMMID_CALMCRS_CALMCRS_VAL_W 16U 4573 #define LRFDRFE32_CALMMID_CALMCRS_CALMCRS_VAL_M 0x0000FFFFU 4574 #define LRFDRFE32_CALMMID_CALMCRS_CALMCRS_VAL_S 0U 4575 #define LRFDRFE32_CALMMID_CALMCRS_CALMCRS_VAL_ALLONES 0x0000FFFFU 4576 #define LRFDRFE32_CALMMID_CALMCRS_CALMCRS_VAL_ALLZEROS 0x00000000U 4577 4578 //***************************************************************************** 4579 // 4580 // Register: LRFDRFE32_O_REFDIV 4581 // 4582 //***************************************************************************** 4583 // Field: [15:0] LOAD 4584 // 4585 // ENUMs: 4586 // ALLONES All the bits are 1 4587 // ALLZEROS All the bits are 0 4588 #define LRFDRFE32_REFDIV_LOAD_W 16U 4589 #define LRFDRFE32_REFDIV_LOAD_M 0x0000FFFFU 4590 #define LRFDRFE32_REFDIV_LOAD_S 0U 4591 #define LRFDRFE32_REFDIV_LOAD_ALLONES 0x0000FFFFU 4592 #define LRFDRFE32_REFDIV_LOAD_ALLZEROS 0x00000000U 4593 4594 //***************************************************************************** 4595 // 4596 // Register: LRFDRFE32_O_DLOCTL0 4597 // 4598 //***************************************************************************** 4599 // Field: [10:8] TDCSTOP 4600 // 4601 // ENUMs: 4602 // OPEN Open-loop operation 4603 // CLOSED Closed-loop operation 4604 #define LRFDRFE32_DLOCTL0_TDCSTOP_W 3U 4605 #define LRFDRFE32_DLOCTL0_TDCSTOP_M 0x00000700U 4606 #define LRFDRFE32_DLOCTL0_TDCSTOP_S 8U 4607 #define LRFDRFE32_DLOCTL0_TDCSTOP_OPEN 0x00000100U 4608 #define LRFDRFE32_DLOCTL0_TDCSTOP_CLOSED 0x00000000U 4609 4610 // Field: [7] DTSTXTAL 4611 // 4612 // ENUMs: 4613 // ONE Enable XTALBAW DTST interface 4614 // ZERO Disable XTALBAW DTST interface 4615 #define LRFDRFE32_DLOCTL0_DTSTXTAL 0x00000080U 4616 #define LRFDRFE32_DLOCTL0_DTSTXTAL_M 0x00000080U 4617 #define LRFDRFE32_DLOCTL0_DTSTXTAL_S 7U 4618 #define LRFDRFE32_DLOCTL0_DTSTXTAL_ONE 0x00000080U 4619 #define LRFDRFE32_DLOCTL0_DTSTXTAL_ZERO 0x00000000U 4620 4621 // Field: [6:4] LOOPUPD 4622 // 4623 // ENUMs: 4624 // ALT Use alternate REF (PLLM1) 4625 // DEF Use default FREF (PLLM0) 4626 #define LRFDRFE32_DLOCTL0_LOOPUPD_W 3U 4627 #define LRFDRFE32_DLOCTL0_LOOPUPD_M 0x00000070U 4628 #define LRFDRFE32_DLOCTL0_LOOPUPD_S 4U 4629 #define LRFDRFE32_DLOCTL0_LOOPUPD_ALT 0x00000010U 4630 #define LRFDRFE32_DLOCTL0_LOOPUPD_DEF 0x00000000U 4631 4632 // Field: [3] PH3 4633 // 4634 // ENUMs: 4635 // START Close the loop to aquire phase lock, i.e. phase 3 4636 // of calibration routine. 4637 // HALT Halt DLO FSM after DCO frequency span measurement 4638 // When DLO and RFE runs KDCO estimation, RFE must 4639 // compute KDCO from the frequency span, and 4640 // calculate loop filter settings to use before 4641 // lock aquisition. 4642 #define LRFDRFE32_DLOCTL0_PH3 0x00000008U 4643 #define LRFDRFE32_DLOCTL0_PH3_M 0x00000008U 4644 #define LRFDRFE32_DLOCTL0_PH3_S 3U 4645 #define LRFDRFE32_DLOCTL0_PH3_START 0x00000008U 4646 #define LRFDRFE32_DLOCTL0_PH3_HALT 0x00000000U 4647 4648 // Field: [2] PH2 4649 // 4650 // ENUMs: 4651 // START Start KDCO estimation, i.e. phase 2 of calibration 4652 // routine. 4653 // HALT Halt DLO FSM after TDC calibration measurement 4654 // When DLO and RFE runs TDC calibration, RFE must 4655 // use calibration measurement to calculcate 4656 // CAL2.KTDCINV. 4657 #define LRFDRFE32_DLOCTL0_PH2 0x00000004U 4658 #define LRFDRFE32_DLOCTL0_PH2_M 0x00000004U 4659 #define LRFDRFE32_DLOCTL0_PH2_S 2U 4660 #define LRFDRFE32_DLOCTL0_PH2_START 0x00000004U 4661 #define LRFDRFE32_DLOCTL0_PH2_HALT 0x00000000U 4662 4663 // Field: [1] LOOPMODE 4664 // 4665 // ENUMs: 4666 // OPEN Open-loop operation 4667 // CLOSED Closed-loop operation 4668 #define LRFDRFE32_DLOCTL0_LOOPMODE 0x00000002U 4669 #define LRFDRFE32_DLOCTL0_LOOPMODE_M 0x00000002U 4670 #define LRFDRFE32_DLOCTL0_LOOPMODE_S 1U 4671 #define LRFDRFE32_DLOCTL0_LOOPMODE_OPEN 0x00000002U 4672 #define LRFDRFE32_DLOCTL0_LOOPMODE_CLOSED 0x00000000U 4673 4674 // Field: [0] RSTN 4675 // 4676 // ENUMs: 4677 // ACTIVE DLO is not held in reset 4678 // RESET DLO is reset 4679 #define LRFDRFE32_DLOCTL0_RSTN 0x00000001U 4680 #define LRFDRFE32_DLOCTL0_RSTN_M 0x00000001U 4681 #define LRFDRFE32_DLOCTL0_RSTN_S 0U 4682 #define LRFDRFE32_DLOCTL0_RSTN_ACTIVE 0x00000001U 4683 #define LRFDRFE32_DLOCTL0_RSTN_RESET 0x00000000U 4684 4685 //***************************************************************************** 4686 // 4687 // Register: LRFDRFE32_O_DLOCTL1 4688 // 4689 //***************************************************************************** 4690 // Field: [15] DCO 4691 // 4692 // ENUMs: 4693 // EN Enable DCO 4694 // DIS Disable DCO 4695 #define LRFDRFE32_DLOCTL1_DCO 0x00008000U 4696 #define LRFDRFE32_DLOCTL1_DCO_M 0x00008000U 4697 #define LRFDRFE32_DLOCTL1_DCO_S 15U 4698 #define LRFDRFE32_DLOCTL1_DCO_EN 0x00008000U 4699 #define LRFDRFE32_DLOCTL1_DCO_DIS 0x00000000U 4700 4701 // Field: [7] FCDEM 4702 // 4703 // ENUMs: 4704 // EN Enable DEM 4705 // DIS Disable DEM 4706 #define LRFDRFE32_DLOCTL1_FCDEM 0x00000080U 4707 #define LRFDRFE32_DLOCTL1_FCDEM_M 0x00000080U 4708 #define LRFDRFE32_DLOCTL1_FCDEM_S 7U 4709 #define LRFDRFE32_DLOCTL1_FCDEM_EN 0x00000080U 4710 #define LRFDRFE32_DLOCTL1_FCDEM_DIS 0x00000000U 4711 4712 // Field: [6] DTSTCKVD 4713 // 4714 // ENUMs: 4715 // ONE Enable CKVD DTST interface 4716 // ZERO Disable CKVD DTST interface 4717 #define LRFDRFE32_DLOCTL1_DTSTCKVD 0x00000040U 4718 #define LRFDRFE32_DLOCTL1_DTSTCKVD_M 0x00000040U 4719 #define LRFDRFE32_DLOCTL1_DTSTCKVD_S 6U 4720 #define LRFDRFE32_DLOCTL1_DTSTCKVD_ONE 0x00000040U 4721 #define LRFDRFE32_DLOCTL1_DTSTCKVD_ZERO 0x00000000U 4722 4723 // Field: [5] PHEDISC 4724 // 4725 // ENUMs: 4726 // EN Enable phase error discard function 4727 // DIS Disable phase error discard function 4728 #define LRFDRFE32_DLOCTL1_PHEDISC 0x00000020U 4729 #define LRFDRFE32_DLOCTL1_PHEDISC_M 0x00000020U 4730 #define LRFDRFE32_DLOCTL1_PHEDISC_S 5U 4731 #define LRFDRFE32_DLOCTL1_PHEDISC_EN 0x00000020U 4732 #define LRFDRFE32_DLOCTL1_PHEDISC_DIS 0x00000000U 4733 4734 // Field: [4] PLLMON 4735 // 4736 // ENUMs: 4737 // EN Enable PLL monitor 4738 // DIS Disable and reset PLL monitor 4739 #define LRFDRFE32_DLOCTL1_PLLMON 0x00000010U 4740 #define LRFDRFE32_DLOCTL1_PLLMON_M 0x00000010U 4741 #define LRFDRFE32_DLOCTL1_PLLMON_S 4U 4742 #define LRFDRFE32_DLOCTL1_PLLMON_EN 0x00000010U 4743 #define LRFDRFE32_DLOCTL1_PLLMON_DIS 0x00000000U 4744 4745 // Field: [3] IIR 4746 // 4747 // ENUMs: 4748 // EN Enable IIR filter 4749 // DIS Disable IIR filter 4750 #define LRFDRFE32_DLOCTL1_IIR 0x00000008U 4751 #define LRFDRFE32_DLOCTL1_IIR_M 0x00000008U 4752 #define LRFDRFE32_DLOCTL1_IIR_S 3U 4753 #define LRFDRFE32_DLOCTL1_IIR_EN 0x00000008U 4754 #define LRFDRFE32_DLOCTL1_IIR_DIS 0x00000000U 4755 4756 // Field: [2] MOD 4757 // 4758 // ENUMs: 4759 // EN Enable MODISF 4760 // DIS Disable MODISF 4761 #define LRFDRFE32_DLOCTL1_MOD 0x00000004U 4762 #define LRFDRFE32_DLOCTL1_MOD_M 0x00000004U 4763 #define LRFDRFE32_DLOCTL1_MOD_S 2U 4764 #define LRFDRFE32_DLOCTL1_MOD_EN 0x00000004U 4765 #define LRFDRFE32_DLOCTL1_MOD_DIS 0x00000000U 4766 4767 // Field: [1] MODINIT 4768 // 4769 // ENUMs: 4770 // ACTIVATE Activate MODISF initialization 4771 // DEACTIVATE Deactivate MODISF initialization 4772 #define LRFDRFE32_DLOCTL1_MODINIT 0x00000002U 4773 #define LRFDRFE32_DLOCTL1_MODINIT_M 0x00000002U 4774 #define LRFDRFE32_DLOCTL1_MODINIT_S 1U 4775 #define LRFDRFE32_DLOCTL1_MODINIT_ACTIVATE 0x00000002U 4776 #define LRFDRFE32_DLOCTL1_MODINIT_DEACTIVATE 0x00000000U 4777 4778 // Field: [0] MTDCRSTN 4779 // 4780 // ENUMs: 4781 // ACTIVE Release MTDC reset 4782 // RESET Reset MTDC 4783 #define LRFDRFE32_DLOCTL1_MTDCRSTN 0x00000001U 4784 #define LRFDRFE32_DLOCTL1_MTDCRSTN_M 0x00000001U 4785 #define LRFDRFE32_DLOCTL1_MTDCRSTN_S 0U 4786 #define LRFDRFE32_DLOCTL1_MTDCRSTN_ACTIVE 0x00000001U 4787 #define LRFDRFE32_DLOCTL1_MTDCRSTN_RESET 0x00000000U 4788 4789 //***************************************************************************** 4790 // 4791 // Register: LRFDRFE32_O_DCOOVR1_DCOOVR0 4792 // 4793 //***************************************************************************** 4794 // Field: [30:24] FINECODE 4795 // 4796 // ENUMs: 4797 // ALLONES All the bits are 1 4798 // ALLZEROS All the bits are 0 4799 #define LRFDRFE32_DCOOVR1_DCOOVR0_FINECODE_W 7U 4800 #define LRFDRFE32_DCOOVR1_DCOOVR0_FINECODE_M 0x7F000000U 4801 #define LRFDRFE32_DCOOVR1_DCOOVR0_FINECODE_S 24U 4802 #define LRFDRFE32_DCOOVR1_DCOOVR0_FINECODE_ALLONES 0x7F000000U 4803 #define LRFDRFE32_DCOOVR1_DCOOVR0_FINECODE_ALLZEROS 0x00000000U 4804 4805 // Field: [23:16] SDMICODE 4806 // 4807 // ENUMs: 4808 // ALLONES All the bits are 1 4809 // ALLZEROS All the bits are 0 4810 #define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICODE_W 8U 4811 #define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICODE_M 0x00FF0000U 4812 #define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICODE_S 16U 4813 #define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICODE_ALLONES 0x00FF0000U 4814 #define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICODE_ALLZEROS 0x00000000U 4815 4816 // Field: [13:8] MIDCODE 4817 // 4818 // ENUMs: 4819 // ALLONES All the bits are 1 4820 // ALLZEROS All the bits are 0 4821 #define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCODE_W 6U 4822 #define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCODE_M 0x00003F00U 4823 #define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCODE_S 8U 4824 #define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCODE_ALLONES 0x00003F00U 4825 #define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCODE_ALLZEROS 0x00000000U 4826 4827 // Field: [7:4] CRSCODE 4828 // 4829 // ENUMs: 4830 // ALLONES All the bits are 1 4831 // ALLZEROS All the bits are 0 4832 #define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCODE_W 4U 4833 #define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCODE_M 0x000000F0U 4834 #define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCODE_S 4U 4835 #define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCODE_ALLONES 0x000000F0U 4836 #define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCODE_ALLZEROS 0x00000000U 4837 4838 // Field: [3] FINECTL 4839 // 4840 // ENUMs: 4841 // EN Enable fine code override 4842 // DIS Disable fine code override 4843 #define LRFDRFE32_DCOOVR1_DCOOVR0_FINECTL 0x00000008U 4844 #define LRFDRFE32_DCOOVR1_DCOOVR0_FINECTL_M 0x00000008U 4845 #define LRFDRFE32_DCOOVR1_DCOOVR0_FINECTL_S 3U 4846 #define LRFDRFE32_DCOOVR1_DCOOVR0_FINECTL_EN 0x00000008U 4847 #define LRFDRFE32_DCOOVR1_DCOOVR0_FINECTL_DIS 0x00000000U 4848 4849 // Field: [2] SDMICTL 4850 // 4851 // ENUMs: 4852 // EN Enable SDM input code override 4853 // DIS Disable SDM input code override 4854 #define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICTL 0x00000004U 4855 #define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICTL_M 0x00000004U 4856 #define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICTL_S 2U 4857 #define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICTL_EN 0x00000004U 4858 #define LRFDRFE32_DCOOVR1_DCOOVR0_SDMICTL_DIS 0x00000000U 4859 4860 // Field: [1] MIDCTL 4861 // 4862 // ENUMs: 4863 // EN Enable mid code override 4864 // DIS Disable mid code override 4865 #define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCTL 0x00000002U 4866 #define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCTL_M 0x00000002U 4867 #define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCTL_S 1U 4868 #define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCTL_EN 0x00000002U 4869 #define LRFDRFE32_DCOOVR1_DCOOVR0_MIDCTL_DIS 0x00000000U 4870 4871 // Field: [0] CRSCTL 4872 // 4873 // ENUMs: 4874 // EN Enable coarse code override 4875 // DIS Disable coarse code override 4876 #define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCTL 0x00000001U 4877 #define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCTL_M 0x00000001U 4878 #define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCTL_S 0U 4879 #define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCTL_EN 0x00000001U 4880 #define LRFDRFE32_DCOOVR1_DCOOVR0_CRSCTL_DIS 0x00000000U 4881 4882 //***************************************************************************** 4883 // 4884 // Register: LRFDRFE32_O_DLOEV_DTST 4885 // 4886 //***************************************************************************** 4887 // Field: [23] LOCK 4888 // 4889 // ENUMs: 4890 // ONE The bit is 1 4891 // ZERO The bit is 0 4892 #define LRFDRFE32_DLOEV_DTST_LOCK 0x00800000U 4893 #define LRFDRFE32_DLOEV_DTST_LOCK_M 0x00800000U 4894 #define LRFDRFE32_DLOEV_DTST_LOCK_S 23U 4895 #define LRFDRFE32_DLOEV_DTST_LOCK_ONE 0x00800000U 4896 #define LRFDRFE32_DLOEV_DTST_LOCK_ZERO 0x00000000U 4897 4898 // Field: [22] LOL 4899 // 4900 // ENUMs: 4901 // ONE The bit is 1 4902 // ZERO The bit is 0 4903 #define LRFDRFE32_DLOEV_DTST_LOL 0x00400000U 4904 #define LRFDRFE32_DLOEV_DTST_LOL_M 0x00400000U 4905 #define LRFDRFE32_DLOEV_DTST_LOL_S 22U 4906 #define LRFDRFE32_DLOEV_DTST_LOL_ONE 0x00400000U 4907 #define LRFDRFE32_DLOEV_DTST_LOL_ZERO 0x00000000U 4908 4909 // Field: [21] FCABVTHR 4910 // 4911 // ENUMs: 4912 // ONE The bit is 1 4913 // ZERO The bit is 0 4914 #define LRFDRFE32_DLOEV_DTST_FCABVTHR 0x00200000U 4915 #define LRFDRFE32_DLOEV_DTST_FCABVTHR_M 0x00200000U 4916 #define LRFDRFE32_DLOEV_DTST_FCABVTHR_S 21U 4917 #define LRFDRFE32_DLOEV_DTST_FCABVTHR_ONE 0x00200000U 4918 #define LRFDRFE32_DLOEV_DTST_FCABVTHR_ZERO 0x00000000U 4919 4920 // Field: [20] FCBLWTHR 4921 // 4922 // ENUMs: 4923 // ONE The bit is 1 4924 // ZERO The bit is 0 4925 #define LRFDRFE32_DLOEV_DTST_FCBLWTHR 0x00100000U 4926 #define LRFDRFE32_DLOEV_DTST_FCBLWTHR_M 0x00100000U 4927 #define LRFDRFE32_DLOEV_DTST_FCBLWTHR_S 20U 4928 #define LRFDRFE32_DLOEV_DTST_FCBLWTHR_ONE 0x00100000U 4929 #define LRFDRFE32_DLOEV_DTST_FCBLWTHR_ZERO 0x00000000U 4930 4931 // Field: [19:16] STATE 4932 // 4933 // ENUMs: 4934 // ALLONES All the bits are 1 4935 // ALLZEROS All the bits are 0 4936 #define LRFDRFE32_DLOEV_DTST_STATE_W 4U 4937 #define LRFDRFE32_DLOEV_DTST_STATE_M 0x000F0000U 4938 #define LRFDRFE32_DLOEV_DTST_STATE_S 16U 4939 #define LRFDRFE32_DLOEV_DTST_STATE_ALLONES 0x000F0000U 4940 #define LRFDRFE32_DLOEV_DTST_STATE_ALLZEROS 0x00000000U 4941 4942 // Field: [14:11] SPARE11 4943 // 4944 // ENUMs: 4945 // ALLONES All the bits are 1 4946 // ALLZEROS All the bits are 0 4947 #define LRFDRFE32_DLOEV_DTST_SPARE11_W 4U 4948 #define LRFDRFE32_DLOEV_DTST_SPARE11_M 0x00007800U 4949 #define LRFDRFE32_DLOEV_DTST_SPARE11_S 11U 4950 #define LRFDRFE32_DLOEV_DTST_SPARE11_ALLONES 0x00007800U 4951 #define LRFDRFE32_DLOEV_DTST_SPARE11_ALLZEROS 0x00000000U 4952 4953 // Field: [10:8] VARTGLDLY 4954 // 4955 // ENUMs: 4956 // CLK_7_PER Toggle lags data by 7 CKVD16 periods. 4957 // CLK_6_PER Toggle lags data by 6 CKVD16 periods. 4958 // CLK_5_PER Toggle lags data by 5 CKVD16 periods. 4959 // CLK_4_PER Toggle lags data by 4 CKVD16 periods. 4960 // CLK_3_PER Toggle lags data by 3 CKVD16 periods. 4961 // CLK_2_PER Toggle lags data by 2 CKVD16 periods. 4962 // CLK_1_PER Toggle lags data by 1 CKVD16 periods. 4963 // CLK_0_PER Toggle lags data by 0 CKVD16 periods. 4964 #define LRFDRFE32_DLOEV_DTST_VARTGLDLY_W 3U 4965 #define LRFDRFE32_DLOEV_DTST_VARTGLDLY_M 0x00000700U 4966 #define LRFDRFE32_DLOEV_DTST_VARTGLDLY_S 8U 4967 #define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_7_PER 0x00000700U 4968 #define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_6_PER 0x00000600U 4969 #define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_5_PER 0x00000500U 4970 #define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_4_PER 0x00000400U 4971 #define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_3_PER 0x00000300U 4972 #define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_2_PER 0x00000200U 4973 #define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_1_PER 0x00000100U 4974 #define LRFDRFE32_DLOEV_DTST_VARTGLDLY_CLK_0_PER 0x00000000U 4975 4976 // Field: [7] REFTGLDLY 4977 // 4978 // ENUMs: 4979 // CLK_1_PER Toggle lags data by 1 HFXT/BAW periods. 4980 // CLK_0_PER Toggle lags data by 0 HFXT/BAW periods. 4981 #define LRFDRFE32_DLOEV_DTST_REFTGLDLY 0x00000080U 4982 #define LRFDRFE32_DLOEV_DTST_REFTGLDLY_M 0x00000080U 4983 #define LRFDRFE32_DLOEV_DTST_REFTGLDLY_S 7U 4984 #define LRFDRFE32_DLOEV_DTST_REFTGLDLY_CLK_1_PER 0x00000080U 4985 #define LRFDRFE32_DLOEV_DTST_REFTGLDLY_CLK_0_PER 0x00000000U 4986 4987 // Field: [6] TRNSEQ 4988 // 4989 // ENUMs: 4990 // EN Enable trainer sequence 4991 // DIS Disable trainer sequence 4992 #define LRFDRFE32_DLOEV_DTST_TRNSEQ 0x00000040U 4993 #define LRFDRFE32_DLOEV_DTST_TRNSEQ_M 0x00000040U 4994 #define LRFDRFE32_DLOEV_DTST_TRNSEQ_S 6U 4995 #define LRFDRFE32_DLOEV_DTST_TRNSEQ_EN 0x00000040U 4996 #define LRFDRFE32_DLOEV_DTST_TRNSEQ_DIS 0x00000000U 4997 4998 // Field: [5] SPARE5 4999 // 5000 // ENUMs: 5001 // ONE The bit is 1 5002 // ZERO The bit is 0 5003 #define LRFDRFE32_DLOEV_DTST_SPARE5 0x00000020U 5004 #define LRFDRFE32_DLOEV_DTST_SPARE5_M 0x00000020U 5005 #define LRFDRFE32_DLOEV_DTST_SPARE5_S 5U 5006 #define LRFDRFE32_DLOEV_DTST_SPARE5_ONE 0x00000020U 5007 #define LRFDRFE32_DLOEV_DTST_SPARE5_ZERO 0x00000000U 5008 5009 // Field: [4:0] SIG 5010 // 5011 // ENUMs: 5012 // VAR_NC_15 dtst_data = 0x0000 5013 // VAR_NC_14 dtst_data = 0x0000 5014 // VAR_NC_13 dtst_data = 0x0000 5015 // VAR_NC_12 dtst_data = 0x0000 5016 // VAR_NC_11 dtst_data = 0x0000 5017 // VAR_LOOP_UPD_FINECODE dtst_data : [15] : (u_pll/pll_loop_update) [14:0] 5018 // : u_pll/po_ckvd16_finecode_pll 5019 // VAR_LOCK_FINECODE dtst_data : [15] : (u_pll/po_ckvd48_pllmon_lock 5020 // XOR u_pll/po_ckvd48_pllmon_lol) [14:0] : 5021 // u_pll/po_ckvd16_finecode_pll 5022 // VAR_MPX_CAN dtst_data : [15] : u_mpx/freq_can[16] [14:0] : 5023 // u_mpx/freq_can[14:0] Format is 1.15s. This 5024 // field holds how much phase DTX adds to DCO per 5025 // reference frequency. This is a slice of the 5026 // signals that goes to u_pll which is 3.18s. 5027 // Hence, wrapping can occur. 5028 // VAR_TDCSTOP_STATUS_TDC dtst_data : [15:14] : po_tdc_stop_dly_sel [13] : 5029 // u_pll/pi_tdc_msb_error [12] : 5030 // u_pll/pll_loop_update [11] : 5031 // (u_pll/po_ckvd48_pllmon_lock XOR 5032 // u_pll/po_ckvd48_pllmon_lol) [10:0]: 5033 // u_pll/pi_tdc_data Note that [12:11] are samples 5034 // from previous reference clock edge. 5035 // VAR_TDCSTOP_PHERR dtst_data : [15:14] : po_tdc_stop_dly_sel [13] 5036 // u_pll/phase_error[16] [12:0]: 5037 // u_pll/phase_error[12:0] [13:0] : phase_error. 5038 // Format is 3.11s. 5039 // VAR_PH_COMP_PHERR_TDCSTOPdtst_data : [15:14] : po_tdc_stop_dly_sel [13] : 5040 // u_pll/phase_error[16] [12:9]: 5041 // u_pll/phase_error[11:8] [8:0] : 5042 // u_pll/var_phase[14: 6] [13:9] : phase error. 5043 // Format is 2.3s. [8:0] : variable phase. Format 5044 // is 4.5u. 5045 // VAR_PH_TDCCORR dtst_data : [15] ; u_pll/pi_tdc_msb_error [14:11] 5046 // : u_pll/pi_pi_cnt_lsb [10:0] : 5047 // u_pll/tdc_data_corr 5048 // VAR_PH_RAW dtst_data : [15] ; u_pll/pi_tdc_msb_error [14:11] 5049 // : u_pll/pi_pi_cnt_lsb [10:0] : 5050 // u_pll/pi_tdc_data 5051 // VAR_PHERR_LOWER dtst_data : [15] : u_pll/phase_error[16] [14:0] : 5052 // u_pll/phase_error[14:0] Format is 5.11s. Phase 5053 // error wraps if if too large. 5054 // VAR_PHERR_UPPER dtst_data = u_pll/phase_error[16:1] Format is 5055 // 6.10s. 5056 // VAR_NC_0 dtst_data = 0x0000 5057 // REF_NC_15 dtst_data = 0x0000 5058 // REF_NC_14 dtst_data = 0x0000 5059 // REF_NC_13 dtst_data = 0x0000 5060 // REF_NC_12 dtst_data = 0x0000 5061 // REF_NC_11 dtst_data = 0x0000 5062 // REF_NC_10 dtst_data = 0x0000 5063 // REF_NC_9 dtst_data = 0x0000 5064 // REF_NC_8 dtst_data = 0x0000 5065 // REF_NC_7 dtst_data = 0x0000 5066 // REF_NC_6 dtst_data = 0x0000 5067 // REF_NC_5 dtst_data = 0x0000 5068 // REF_NC_4 dtst_data = 0x0000 5069 // REF_NC_3 dtst_data = 0x0000 5070 // REF_FERR_MAG dtst_data = u_fsm/po_dtst_fsm_ferr_mag Format 5071 // is14.2u. The signal is only updated for 5072 // frequency measurements that affect the 5073 // calibration result. 5074 // REF_FSMCAL dtst_data : [15] : '0' [14] : 5075 // u_fsm/pi_pll_lock_ind [13:10] : 5076 // u_fsm/po_dsts_fsm_state [9:6] : 5077 // u_fsm/po_dtst_fsm_coarse [5:0] : 5078 // u_fsm/po_dtst_fsm_mid 5079 // REF_NC_0 dtst_data = 0x0000 5080 #define LRFDRFE32_DLOEV_DTST_SIG_W 5U 5081 #define LRFDRFE32_DLOEV_DTST_SIG_M 0x0000001FU 5082 #define LRFDRFE32_DLOEV_DTST_SIG_S 0U 5083 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_NC_15 0x0000001FU 5084 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_NC_14 0x0000001EU 5085 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_NC_13 0x0000001DU 5086 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_NC_12 0x0000001CU 5087 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_NC_11 0x0000001BU 5088 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_LOOP_UPD_FINECODE 0x0000001AU 5089 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_LOCK_FINECODE 0x00000019U 5090 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_MPX_CAN 0x00000018U 5091 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_TDCSTOP_STATUS_TDC 0x00000017U 5092 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_TDCSTOP_PHERR 0x00000016U 5093 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_PH_COMP_PHERR_TDCSTOP 0x00000015U 5094 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_PH_TDCCORR 0x00000014U 5095 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_PH_RAW 0x00000013U 5096 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_PHERR_LOWER 0x00000012U 5097 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_PHERR_UPPER 0x00000011U 5098 #define LRFDRFE32_DLOEV_DTST_SIG_VAR_NC_0 0x00000010U 5099 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_15 0x0000000FU 5100 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_14 0x0000000EU 5101 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_13 0x0000000DU 5102 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_12 0x0000000CU 5103 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_11 0x0000000BU 5104 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_10 0x0000000AU 5105 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_9 0x00000009U 5106 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_8 0x00000008U 5107 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_7 0x00000007U 5108 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_6 0x00000006U 5109 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_5 0x00000005U 5110 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_4 0x00000004U 5111 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_3 0x00000003U 5112 #define LRFDRFE32_DLOEV_DTST_SIG_REF_FERR_MAG 0x00000002U 5113 #define LRFDRFE32_DLOEV_DTST_SIG_REF_FSMCAL 0x00000001U 5114 #define LRFDRFE32_DLOEV_DTST_SIG_REF_NC_0 0x00000000U 5115 5116 //***************************************************************************** 5117 // 5118 // Register: LRFDRFE32_O_FDCOSPANLSB_DTSTRD 5119 // 5120 //***************************************************************************** 5121 // Field: [31:16] VAL 5122 // 5123 // ENUMs: 5124 // ALLONES All the bits are 1 5125 // ALLZEROS All the bits are 0 5126 #define LRFDRFE32_FDCOSPANLSB_DTSTRD_VAL_W 16U 5127 #define LRFDRFE32_FDCOSPANLSB_DTSTRD_VAL_M 0xFFFF0000U 5128 #define LRFDRFE32_FDCOSPANLSB_DTSTRD_VAL_S 16U 5129 #define LRFDRFE32_FDCOSPANLSB_DTSTRD_VAL_ALLONES 0xFFFF0000U 5130 #define LRFDRFE32_FDCOSPANLSB_DTSTRD_VAL_ALLZEROS 0x00000000U 5131 5132 // Field: [15:0] DATA 5133 // 5134 // ENUMs: 5135 // ALLONES All the bits are 1 5136 // ALLZEROS All the bits are 0 5137 #define LRFDRFE32_FDCOSPANLSB_DTSTRD_DATA_W 16U 5138 #define LRFDRFE32_FDCOSPANLSB_DTSTRD_DATA_M 0x0000FFFFU 5139 #define LRFDRFE32_FDCOSPANLSB_DTSTRD_DATA_S 0U 5140 #define LRFDRFE32_FDCOSPANLSB_DTSTRD_DATA_ALLONES 0x0000FFFFU 5141 #define LRFDRFE32_FDCOSPANLSB_DTSTRD_DATA_ALLZEROS 0x00000000U 5142 5143 //***************************************************************************** 5144 // 5145 // Register: LRFDRFE32_O_TDCCAL_FDCOSPANMSB 5146 // 5147 //***************************************************************************** 5148 // Field: [31:16] TDCCAL_VAL 5149 // 5150 // ENUMs: 5151 // ALLONES All the bits are 1 5152 // ALLZEROS All the bits are 0 5153 #define LRFDRFE32_TDCCAL_FDCOSPANMSB_TDCCAL_VAL_W 16U 5154 #define LRFDRFE32_TDCCAL_FDCOSPANMSB_TDCCAL_VAL_M 0xFFFF0000U 5155 #define LRFDRFE32_TDCCAL_FDCOSPANMSB_TDCCAL_VAL_S 16U 5156 #define LRFDRFE32_TDCCAL_FDCOSPANMSB_TDCCAL_VAL_ALLONES 0xFFFF0000U 5157 #define LRFDRFE32_TDCCAL_FDCOSPANMSB_TDCCAL_VAL_ALLZEROS 0x00000000U 5158 5159 // Field: [2:0] FDCOSPANMSB_VAL 5160 // 5161 // ENUMs: 5162 // ALLONES All the bits are 1 5163 // ALLZEROS All the bits are 0 5164 #define LRFDRFE32_TDCCAL_FDCOSPANMSB_FDCOSPANMSB_VAL_W 3U 5165 #define LRFDRFE32_TDCCAL_FDCOSPANMSB_FDCOSPANMSB_VAL_M 0x00000007U 5166 #define LRFDRFE32_TDCCAL_FDCOSPANMSB_FDCOSPANMSB_VAL_S 0U 5167 #define LRFDRFE32_TDCCAL_FDCOSPANMSB_FDCOSPANMSB_VAL_ALLONES 0x00000007U 5168 #define LRFDRFE32_TDCCAL_FDCOSPANMSB_FDCOSPANMSB_VAL_ALLZEROS 0x00000000U 5169 5170 //***************************************************************************** 5171 // 5172 // Register: LRFDRFE32_O_GPI_CALRES 5173 // 5174 //***************************************************************************** 5175 // Field: [23] GPI7 5176 // 5177 // ENUMs: 5178 // ONE The bit is 1 5179 // ZERO The bit is 0 5180 #define LRFDRFE32_GPI_CALRES_GPI7 0x00800000U 5181 #define LRFDRFE32_GPI_CALRES_GPI7_M 0x00800000U 5182 #define LRFDRFE32_GPI_CALRES_GPI7_S 23U 5183 #define LRFDRFE32_GPI_CALRES_GPI7_ONE 0x00800000U 5184 #define LRFDRFE32_GPI_CALRES_GPI7_ZERO 0x00000000U 5185 5186 // Field: [22] GPI6 5187 // 5188 // ENUMs: 5189 // ONE The bit is 1 5190 // ZERO The bit is 0 5191 #define LRFDRFE32_GPI_CALRES_GPI6 0x00400000U 5192 #define LRFDRFE32_GPI_CALRES_GPI6_M 0x00400000U 5193 #define LRFDRFE32_GPI_CALRES_GPI6_S 22U 5194 #define LRFDRFE32_GPI_CALRES_GPI6_ONE 0x00400000U 5195 #define LRFDRFE32_GPI_CALRES_GPI6_ZERO 0x00000000U 5196 5197 // Field: [21] GPI5 5198 // 5199 // ENUMs: 5200 // ONE The bit is 1 5201 // ZERO The bit is 0 5202 #define LRFDRFE32_GPI_CALRES_GPI5 0x00200000U 5203 #define LRFDRFE32_GPI_CALRES_GPI5_M 0x00200000U 5204 #define LRFDRFE32_GPI_CALRES_GPI5_S 21U 5205 #define LRFDRFE32_GPI_CALRES_GPI5_ONE 0x00200000U 5206 #define LRFDRFE32_GPI_CALRES_GPI5_ZERO 0x00000000U 5207 5208 // Field: [20] GPI4 5209 // 5210 // ENUMs: 5211 // ONE The bit is 1 5212 // ZERO The bit is 0 5213 #define LRFDRFE32_GPI_CALRES_GPI4 0x00100000U 5214 #define LRFDRFE32_GPI_CALRES_GPI4_M 0x00100000U 5215 #define LRFDRFE32_GPI_CALRES_GPI4_S 20U 5216 #define LRFDRFE32_GPI_CALRES_GPI4_ONE 0x00100000U 5217 #define LRFDRFE32_GPI_CALRES_GPI4_ZERO 0x00000000U 5218 5219 // Field: [19] GPI3 5220 // 5221 // ENUMs: 5222 // ONE The bit is 1 5223 // ZERO The bit is 0 5224 #define LRFDRFE32_GPI_CALRES_GPI3 0x00080000U 5225 #define LRFDRFE32_GPI_CALRES_GPI3_M 0x00080000U 5226 #define LRFDRFE32_GPI_CALRES_GPI3_S 19U 5227 #define LRFDRFE32_GPI_CALRES_GPI3_ONE 0x00080000U 5228 #define LRFDRFE32_GPI_CALRES_GPI3_ZERO 0x00000000U 5229 5230 // Field: [18] GPI2 5231 // 5232 // ENUMs: 5233 // ONE The bit is 1 5234 // ZERO The bit is 0 5235 #define LRFDRFE32_GPI_CALRES_GPI2 0x00040000U 5236 #define LRFDRFE32_GPI_CALRES_GPI2_M 0x00040000U 5237 #define LRFDRFE32_GPI_CALRES_GPI2_S 18U 5238 #define LRFDRFE32_GPI_CALRES_GPI2_ONE 0x00040000U 5239 #define LRFDRFE32_GPI_CALRES_GPI2_ZERO 0x00000000U 5240 5241 // Field: [17] GPI1 5242 // 5243 // ENUMs: 5244 // ONE The bit is 1 5245 // ZERO The bit is 0 5246 #define LRFDRFE32_GPI_CALRES_GPI1 0x00020000U 5247 #define LRFDRFE32_GPI_CALRES_GPI1_M 0x00020000U 5248 #define LRFDRFE32_GPI_CALRES_GPI1_S 17U 5249 #define LRFDRFE32_GPI_CALRES_GPI1_ONE 0x00020000U 5250 #define LRFDRFE32_GPI_CALRES_GPI1_ZERO 0x00000000U 5251 5252 // Field: [16] GPI0 5253 // 5254 // ENUMs: 5255 // ONE The bit is 1 5256 // ZERO The bit is 0 5257 #define LRFDRFE32_GPI_CALRES_GPI0 0x00010000U 5258 #define LRFDRFE32_GPI_CALRES_GPI0_M 0x00010000U 5259 #define LRFDRFE32_GPI_CALRES_GPI0_S 16U 5260 #define LRFDRFE32_GPI_CALRES_GPI0_ONE 0x00010000U 5261 #define LRFDRFE32_GPI_CALRES_GPI0_ZERO 0x00000000U 5262 5263 // Field: [9:4] MIDCODE 5264 // 5265 // ENUMs: 5266 // ALLONES All the bits are 1 5267 // ALLZEROS All the bits are 0 5268 #define LRFDRFE32_GPI_CALRES_MIDCODE_W 6U 5269 #define LRFDRFE32_GPI_CALRES_MIDCODE_M 0x000003F0U 5270 #define LRFDRFE32_GPI_CALRES_MIDCODE_S 4U 5271 #define LRFDRFE32_GPI_CALRES_MIDCODE_ALLONES 0x000003F0U 5272 #define LRFDRFE32_GPI_CALRES_MIDCODE_ALLZEROS 0x00000000U 5273 5274 // Field: [3:0] CRSCODE 5275 // 5276 // ENUMs: 5277 // ALLONES All the bits are 1 5278 // ALLZEROS All the bits are 0 5279 #define LRFDRFE32_GPI_CALRES_CRSCODE_W 4U 5280 #define LRFDRFE32_GPI_CALRES_CRSCODE_M 0x0000000FU 5281 #define LRFDRFE32_GPI_CALRES_CRSCODE_S 0U 5282 #define LRFDRFE32_GPI_CALRES_CRSCODE_ALLONES 0x0000000FU 5283 #define LRFDRFE32_GPI_CALRES_CRSCODE_ALLZEROS 0x00000000U 5284 5285 //***************************************************************************** 5286 // 5287 // Register: LRFDRFE32_O_LIN2LOGOUT_MATHACCELIN 5288 // 5289 //***************************************************************************** 5290 // Field: [22:16] LOGVAL 5291 // 5292 // ENUMs: 5293 // ALLONES All the bits are 1 5294 // ALLZEROS All the bits are 0 5295 #define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_LOGVAL_W 7U 5296 #define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_LOGVAL_M 0x007F0000U 5297 #define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_LOGVAL_S 16U 5298 #define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_LOGVAL_ALLONES 0x007F0000U 5299 #define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_LOGVAL_ALLZEROS 0x00000000U 5300 5301 // Field: [15:0] VAL 5302 // 5303 // ENUMs: 5304 // ALLONES All the bits are 1 5305 // ALLZEROS All the bits are 0 5306 #define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_VAL_W 16U 5307 #define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_VAL_M 0x0000FFFFU 5308 #define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_VAL_S 0U 5309 #define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_VAL_ALLONES 0x0000FFFFU 5310 #define LRFDRFE32_LIN2LOGOUT_MATHACCELIN_VAL_ALLZEROS 0x00000000U 5311 5312 //***************************************************************************** 5313 // 5314 // Register: LRFDRFE32_O_TIMCTL_DIVBY3OUT 5315 // 5316 //***************************************************************************** 5317 // Field: [29:24] CPTSRC 5318 // 5319 // ENUMs: 5320 // ALLONES All the bits are 1 5321 // ALLZEROS All the bits are 0 5322 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTSRC_W 6U 5323 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTSRC_M 0x3F000000U 5324 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTSRC_S 24U 5325 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTSRC_ALLONES 0x3F000000U 5326 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTSRC_ALLZEROS 0x00000000U 5327 5328 // Field: [23] CPTCTL 5329 // 5330 // ENUMs: 5331 // EN Enable counter capture mode 5332 // DIS Disable counter capture mode 5333 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTCTL 0x00800000U 5334 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTCTL_M 0x00800000U 5335 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTCTL_S 23U 5336 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTCTL_EN 0x00800000U 5337 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CPTCTL_DIS 0x00000000U 5338 5339 // Field: [22:21] CNTRSRC 5340 // 5341 // ENUMs: 5342 // FREF Count FREF ticks 5343 // MAGN1 Use magnitude estimator 1 data enable 5344 // MAGN0 Use magnitude estimator 0 data enable 5345 // CLK Use clock 5346 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_W 2U 5347 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_M 0x00600000U 5348 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_S 21U 5349 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_FREF 0x00600000U 5350 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_MAGN1 0x00400000U 5351 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_MAGN0 0x00200000U 5352 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRSRC_CLK 0x00000000U 5353 5354 // Field: [20] CNTRCLR 5355 // 5356 // ENUMs: 5357 // ONE Clear counter value 5358 // ZERO No action 5359 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCLR 0x00100000U 5360 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCLR_M 0x00100000U 5361 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCLR_S 20U 5362 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCLR_ONE 0x00100000U 5363 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCLR_ZERO 0x00000000U 5364 5365 // Field: [19] CNTRCTL 5366 // 5367 // ENUMs: 5368 // EN Enable counter 5369 // DIS Disable counter 5370 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCTL 0x00080000U 5371 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCTL_M 0x00080000U 5372 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCTL_S 19U 5373 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCTL_EN 0x00080000U 5374 #define LRFDRFE32_TIMCTL_DIVBY3OUT_CNTRCTL_DIS 0x00000000U 5375 5376 // Field: [18:17] TIMSRC 5377 // 5378 // ENUMs: 5379 // FREF Count FREF ticks 5380 // MAGN1 Use magnitude estimator 1 data enable 5381 // MAGN0 Use magnitude estimator 0 data enable 5382 // CLK Use clock 5383 #define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_W 2U 5384 #define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_M 0x00060000U 5385 #define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_S 17U 5386 #define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_FREF 0x00060000U 5387 #define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_MAGN1 0x00040000U 5388 #define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_MAGN0 0x00020000U 5389 #define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMSRC_CLK 0x00000000U 5390 5391 // Field: [16] TIMCTL 5392 // 5393 // ENUMs: 5394 // EN Enable timer 5395 // DIS Disable timer and clear internal timer value 5396 #define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMCTL 0x00010000U 5397 #define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMCTL_M 0x00010000U 5398 #define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMCTL_S 16U 5399 #define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMCTL_EN 0x00010000U 5400 #define LRFDRFE32_TIMCTL_DIVBY3OUT_TIMCTL_DIS 0x00000000U 5401 5402 // Field: [3:0] DIV3 5403 // 5404 // ENUMs: 5405 // ALLONES All the bits are 1 5406 // ALLZEROS All the bits are 0 5407 #define LRFDRFE32_TIMCTL_DIVBY3OUT_DIV3_W 4U 5408 #define LRFDRFE32_TIMCTL_DIVBY3OUT_DIV3_M 0x0000000FU 5409 #define LRFDRFE32_TIMCTL_DIVBY3OUT_DIV3_S 0U 5410 #define LRFDRFE32_TIMCTL_DIVBY3OUT_DIV3_ALLONES 0x0000000FU 5411 #define LRFDRFE32_TIMCTL_DIVBY3OUT_DIV3_ALLZEROS 0x00000000U 5412 5413 //***************************************************************************** 5414 // 5415 // Register: LRFDRFE32_O_TIMPER_TIMINC 5416 // 5417 //***************************************************************************** 5418 // Field: [31:16] TIMPER_VAL 5419 // 5420 // ENUMs: 5421 // ALLONES All the bits are 1 5422 // ALLZEROS All the bits are 0 5423 #define LRFDRFE32_TIMPER_TIMINC_TIMPER_VAL_W 16U 5424 #define LRFDRFE32_TIMPER_TIMINC_TIMPER_VAL_M 0xFFFF0000U 5425 #define LRFDRFE32_TIMPER_TIMINC_TIMPER_VAL_S 16U 5426 #define LRFDRFE32_TIMPER_TIMINC_TIMPER_VAL_ALLONES 0xFFFF0000U 5427 #define LRFDRFE32_TIMPER_TIMINC_TIMPER_VAL_ALLZEROS 0x00000000U 5428 5429 // Field: [15:0] TIMINC_VAL 5430 // 5431 // ENUMs: 5432 // ALLONES All the bits are 1 5433 // ALLZEROS All the bits are 0 5434 #define LRFDRFE32_TIMPER_TIMINC_TIMINC_VAL_W 16U 5435 #define LRFDRFE32_TIMPER_TIMINC_TIMINC_VAL_M 0x0000FFFFU 5436 #define LRFDRFE32_TIMPER_TIMINC_TIMINC_VAL_S 0U 5437 #define LRFDRFE32_TIMPER_TIMINC_TIMINC_VAL_ALLONES 0x0000FFFFU 5438 #define LRFDRFE32_TIMPER_TIMINC_TIMINC_VAL_ALLZEROS 0x00000000U 5439 5440 //***************************************************************************** 5441 // 5442 // Register: LRFDRFE32_O_TIMCAPT_TIMCNT 5443 // 5444 //***************************************************************************** 5445 // Field: [31:16] VALUE 5446 // 5447 // ENUMs: 5448 // ALLONES All the bits are 1 5449 // ALLZEROS All the bits are 0 5450 #define LRFDRFE32_TIMCAPT_TIMCNT_VALUE_W 16U 5451 #define LRFDRFE32_TIMCAPT_TIMCNT_VALUE_M 0xFFFF0000U 5452 #define LRFDRFE32_TIMCAPT_TIMCNT_VALUE_S 16U 5453 #define LRFDRFE32_TIMCAPT_TIMCNT_VALUE_ALLONES 0xFFFF0000U 5454 #define LRFDRFE32_TIMCAPT_TIMCNT_VALUE_ALLZEROS 0x00000000U 5455 5456 // Field: [15:0] VAL 5457 // 5458 // ENUMs: 5459 // ALLONES All the bits are 1 5460 // ALLZEROS All the bits are 0 5461 #define LRFDRFE32_TIMCAPT_TIMCNT_VAL_W 16U 5462 #define LRFDRFE32_TIMCAPT_TIMCNT_VAL_M 0x0000FFFFU 5463 #define LRFDRFE32_TIMCAPT_TIMCNT_VAL_S 0U 5464 #define LRFDRFE32_TIMCAPT_TIMCNT_VAL_ALLONES 0x0000FFFFU 5465 #define LRFDRFE32_TIMCAPT_TIMCNT_VAL_ALLZEROS 0x00000000U 5466 5467 //***************************************************************************** 5468 // 5469 // Register: LRFDRFE32_O_TRCSTAT_TRCCTRL 5470 // 5471 //***************************************************************************** 5472 // Field: [16] BUSY 5473 // 5474 // ENUMs: 5475 // ONE The bit is 1 5476 // ZERO The bit is 0 5477 #define LRFDRFE32_TRCSTAT_TRCCTRL_BUSY 0x00010000U 5478 #define LRFDRFE32_TRCSTAT_TRCCTRL_BUSY_M 0x00010000U 5479 #define LRFDRFE32_TRCSTAT_TRCCTRL_BUSY_S 16U 5480 #define LRFDRFE32_TRCSTAT_TRCCTRL_BUSY_ONE 0x00010000U 5481 #define LRFDRFE32_TRCSTAT_TRCCTRL_BUSY_ZERO 0x00000000U 5482 5483 // Field: [0] SEND 5484 // 5485 // ENUMs: 5486 // ONE The bit is 1 5487 // ZERO The bit is 0 5488 #define LRFDRFE32_TRCSTAT_TRCCTRL_SEND 0x00000001U 5489 #define LRFDRFE32_TRCSTAT_TRCCTRL_SEND_M 0x00000001U 5490 #define LRFDRFE32_TRCSTAT_TRCCTRL_SEND_S 0U 5491 #define LRFDRFE32_TRCSTAT_TRCCTRL_SEND_ONE 0x00000001U 5492 #define LRFDRFE32_TRCSTAT_TRCCTRL_SEND_ZERO 0x00000000U 5493 5494 //***************************************************************************** 5495 // 5496 // Register: LRFDRFE32_O_TRCPAR0_TRCCMD 5497 // 5498 //***************************************************************************** 5499 // Field: [31:16] VAL 5500 // 5501 // ENUMs: 5502 // ALLONES All the bits are 1 5503 // ALLZEROS All the bits are 0 5504 #define LRFDRFE32_TRCPAR0_TRCCMD_VAL_W 16U 5505 #define LRFDRFE32_TRCPAR0_TRCCMD_VAL_M 0xFFFF0000U 5506 #define LRFDRFE32_TRCPAR0_TRCCMD_VAL_S 16U 5507 #define LRFDRFE32_TRCPAR0_TRCCMD_VAL_ALLONES 0xFFFF0000U 5508 #define LRFDRFE32_TRCPAR0_TRCCMD_VAL_ALLZEROS 0x00000000U 5509 5510 // Field: [9:8] PARCNT 5511 // 5512 // ENUMs: 5513 // ALLONES All the bits are 1 5514 // ALLZEROS All the bits are 0 5515 #define LRFDRFE32_TRCPAR0_TRCCMD_PARCNT_W 2U 5516 #define LRFDRFE32_TRCPAR0_TRCCMD_PARCNT_M 0x00000300U 5517 #define LRFDRFE32_TRCPAR0_TRCCMD_PARCNT_S 8U 5518 #define LRFDRFE32_TRCPAR0_TRCCMD_PARCNT_ALLONES 0x00000300U 5519 #define LRFDRFE32_TRCPAR0_TRCCMD_PARCNT_ALLZEROS 0x00000000U 5520 5521 // Field: [7:0] PKTHDR 5522 // 5523 // ENUMs: 5524 // ALLONES All the bits are 1 5525 // ALLZEROS All the bits are 0 5526 #define LRFDRFE32_TRCPAR0_TRCCMD_PKTHDR_W 8U 5527 #define LRFDRFE32_TRCPAR0_TRCCMD_PKTHDR_M 0x000000FFU 5528 #define LRFDRFE32_TRCPAR0_TRCCMD_PKTHDR_S 0U 5529 #define LRFDRFE32_TRCPAR0_TRCCMD_PKTHDR_ALLONES 0x000000FFU 5530 #define LRFDRFE32_TRCPAR0_TRCCMD_PKTHDR_ALLZEROS 0x00000000U 5531 5532 //***************************************************************************** 5533 // 5534 // Register: LRFDRFE32_O_GPOCTL_TRCPAR1 5535 // 5536 //***************************************************************************** 5537 // Field: [31] SEL7 5538 // 5539 // ENUMs: 5540 // HW The pin is controlled by its HW source 5541 // SW The pin is controlled by GPOCTRL.GPO7 5542 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL7 0x80000000U 5543 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL7_M 0x80000000U 5544 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL7_S 31U 5545 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL7_HW 0x80000000U 5546 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL7_SW 0x00000000U 5547 5548 // Field: [30] SEL6 5549 // 5550 // ENUMs: 5551 // HW The pin is controlled by its HW source 5552 // SW The pin is controlled by GPOCTRL.GPO6 5553 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL6 0x40000000U 5554 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL6_M 0x40000000U 5555 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL6_S 30U 5556 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL6_HW 0x40000000U 5557 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL6_SW 0x00000000U 5558 5559 // Field: [29] SEL5 5560 // 5561 // ENUMs: 5562 // HW The pin is controlled by its HW source 5563 // SW The pin is controlled by GPOCTRL.GPO5 5564 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL5 0x20000000U 5565 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL5_M 0x20000000U 5566 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL5_S 29U 5567 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL5_HW 0x20000000U 5568 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL5_SW 0x00000000U 5569 5570 // Field: [28] SEL4 5571 // 5572 // ENUMs: 5573 // HW The pin is controlled by its HW source 5574 // SW The pin is controlled by GPOCTRL.GPO4 5575 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL4 0x10000000U 5576 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL4_M 0x10000000U 5577 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL4_S 28U 5578 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL4_HW 0x10000000U 5579 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL4_SW 0x00000000U 5580 5581 // Field: [27] SEL3 5582 // 5583 // ENUMs: 5584 // HW The pin is controlled by its HW source 5585 // SW The pin is controlled by GPOCTRL.GPO3 5586 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL3 0x08000000U 5587 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL3_M 0x08000000U 5588 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL3_S 27U 5589 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL3_HW 0x08000000U 5590 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL3_SW 0x00000000U 5591 5592 // Field: [26] SEL2 5593 // 5594 // ENUMs: 5595 // HW The pin is controlled by its HW source 5596 // SW The pin is controlled by GPOCTRL.GPO2 5597 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL2 0x04000000U 5598 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL2_M 0x04000000U 5599 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL2_S 26U 5600 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL2_HW 0x04000000U 5601 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL2_SW 0x00000000U 5602 5603 // Field: [25] SEL1 5604 // 5605 // ENUMs: 5606 // HW The pin is controlled by its HW source 5607 // SW The pin is controlled by GPOCTRL.GPO1 5608 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL1 0x02000000U 5609 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL1_M 0x02000000U 5610 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL1_S 25U 5611 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL1_HW 0x02000000U 5612 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL1_SW 0x00000000U 5613 5614 // Field: [24] SEL0 5615 // 5616 // ENUMs: 5617 // HW The pin is controlled by its HW source 5618 // SW The pin is controlled by GPOCTRL.GPO0 5619 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL0 0x01000000U 5620 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL0_M 0x01000000U 5621 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL0_S 24U 5622 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL0_HW 0x01000000U 5623 #define LRFDRFE32_GPOCTL_TRCPAR1_SEL0_SW 0x00000000U 5624 5625 // Field: [23] GPO7 5626 // 5627 // ENUMs: 5628 // ONE The bit is 1 5629 // ZERO The bit is 0 5630 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO7 0x00800000U 5631 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO7_M 0x00800000U 5632 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO7_S 23U 5633 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO7_ONE 0x00800000U 5634 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO7_ZERO 0x00000000U 5635 5636 // Field: [22] GPO6 5637 // 5638 // ENUMs: 5639 // ONE The bit is 1 5640 // ZERO The bit is 0 5641 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO6 0x00400000U 5642 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO6_M 0x00400000U 5643 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO6_S 22U 5644 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO6_ONE 0x00400000U 5645 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO6_ZERO 0x00000000U 5646 5647 // Field: [21] GPO5 5648 // 5649 // ENUMs: 5650 // ONE The bit is 1 5651 // ZERO The bit is 0 5652 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO5 0x00200000U 5653 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO5_M 0x00200000U 5654 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO5_S 21U 5655 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO5_ONE 0x00200000U 5656 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO5_ZERO 0x00000000U 5657 5658 // Field: [20] GPO4 5659 // 5660 // ENUMs: 5661 // ONE The bit is 1 5662 // ZERO The bit is 0 5663 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO4 0x00100000U 5664 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO4_M 0x00100000U 5665 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO4_S 20U 5666 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO4_ONE 0x00100000U 5667 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO4_ZERO 0x00000000U 5668 5669 // Field: [19] GPO3 5670 // 5671 // ENUMs: 5672 // ONE The bit is 1 5673 // ZERO The bit is 0 5674 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO3 0x00080000U 5675 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO3_M 0x00080000U 5676 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO3_S 19U 5677 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO3_ONE 0x00080000U 5678 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO3_ZERO 0x00000000U 5679 5680 // Field: [18] GPO2 5681 // 5682 // ENUMs: 5683 // ONE The bit is 1 5684 // ZERO The bit is 0 5685 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO2 0x00040000U 5686 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO2_M 0x00040000U 5687 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO2_S 18U 5688 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO2_ONE 0x00040000U 5689 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO2_ZERO 0x00000000U 5690 5691 // Field: [17] GPO1 5692 // 5693 // ENUMs: 5694 // ONE The bit is 1 5695 // ZERO The bit is 0 5696 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO1 0x00020000U 5697 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO1_M 0x00020000U 5698 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO1_S 17U 5699 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO1_ONE 0x00020000U 5700 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO1_ZERO 0x00000000U 5701 5702 // Field: [16] GPO0 5703 // 5704 // ENUMs: 5705 // ONE The bit is 1 5706 // ZERO The bit is 0 5707 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO0 0x00010000U 5708 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO0_M 0x00010000U 5709 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO0_S 16U 5710 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO0_ONE 0x00010000U 5711 #define LRFDRFE32_GPOCTL_TRCPAR1_GPO0_ZERO 0x00000000U 5712 5713 // Field: [15:0] VAL 5714 // 5715 // ENUMs: 5716 // ALLONES All the bits are 1 5717 // ALLZEROS All the bits are 0 5718 #define LRFDRFE32_GPOCTL_TRCPAR1_VAL_W 16U 5719 #define LRFDRFE32_GPOCTL_TRCPAR1_VAL_M 0x0000FFFFU 5720 #define LRFDRFE32_GPOCTL_TRCPAR1_VAL_S 0U 5721 #define LRFDRFE32_GPOCTL_TRCPAR1_VAL_ALLONES 0x0000FFFFU 5722 #define LRFDRFE32_GPOCTL_TRCPAR1_VAL_ALLZEROS 0x00000000U 5723 5724 //***************************************************************************** 5725 // 5726 // Register: LRFDRFE32_O_DIVCTL_ANAISOCTL 5727 // 5728 //***************************************************************************** 5729 // Field: [31] DIV2PH180 5730 // 5731 // ENUMs: 5732 // EN Enable path 5733 // DIS Disable path 5734 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH180 0x80000000U 5735 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH180_M 0x80000000U 5736 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH180_S 31U 5737 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH180_EN 0x80000000U 5738 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH180_DIS 0x00000000U 5739 5740 // Field: [30] DIV2PH0 5741 // 5742 // ENUMs: 5743 // EN Enable path 5744 // DIS Disable path 5745 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH0 0x40000000U 5746 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH0_M 0x40000000U 5747 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH0_S 30U 5748 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH0_EN 0x40000000U 5749 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH0_DIS 0x00000000U 5750 5751 // Field: [29] DIV2PH270 5752 // 5753 // ENUMs: 5754 // EN Enable path 5755 // DIS Disable path 5756 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH270 0x20000000U 5757 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH270_M 0x20000000U 5758 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH270_S 29U 5759 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH270_EN 0x20000000U 5760 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH270_DIS 0x00000000U 5761 5762 // Field: [28] DIV2PH90 5763 // 5764 // ENUMs: 5765 // EN Enable path 5766 // DIS Disable path 5767 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH90 0x10000000U 5768 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH90_M 0x10000000U 5769 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH90_S 28U 5770 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH90_EN 0x10000000U 5771 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2PH90_DIS 0x00000000U 5772 5773 // Field: [27] SPARE11 5774 // 5775 // ENUMs: 5776 // ONE Bit is one 5777 // ZERO Bit is 0 5778 #define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE11 0x08000000U 5779 #define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE11_M 0x08000000U 5780 #define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE11_S 27U 5781 #define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE11_ONE 0x08000000U 5782 #define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE11_ZERO 0x00000000U 5783 5784 // Field: [26] S1G20DBMMUX 5785 // 5786 // ENUMs: 5787 // DISABLE Disable mux 5788 // ENABLEN Enable mux 5789 #define LRFDRFE32_DIVCTL_ANAISOCTL_S1G20DBMMUX 0x04000000U 5790 #define LRFDRFE32_DIVCTL_ANAISOCTL_S1G20DBMMUX_M 0x04000000U 5791 #define LRFDRFE32_DIVCTL_ANAISOCTL_S1G20DBMMUX_S 26U 5792 #define LRFDRFE32_DIVCTL_ANAISOCTL_S1G20DBMMUX_DISABLE 0x04000000U 5793 #define LRFDRFE32_DIVCTL_ANAISOCTL_S1G20DBMMUX_ENABLEN 0x00000000U 5794 5795 // Field: [25] ADCDIV 5796 // 5797 // ENUMs: 5798 // EN Enable divider 5799 // DIS Disable divider 5800 #define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIV 0x02000000U 5801 #define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIV_M 0x02000000U 5802 #define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIV_S 25U 5803 #define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIV_EN 0x02000000U 5804 #define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIV_DIS 0x00000000U 5805 5806 // Field: [24] ENSYNTH 5807 // 5808 // ENUMs: 5809 // EN Clock is enabled 5810 // DIS Clock is disabled 5811 #define LRFDRFE32_DIVCTL_ANAISOCTL_ENSYNTH 0x01000000U 5812 #define LRFDRFE32_DIVCTL_ANAISOCTL_ENSYNTH_M 0x01000000U 5813 #define LRFDRFE32_DIVCTL_ANAISOCTL_ENSYNTH_S 24U 5814 #define LRFDRFE32_DIVCTL_ANAISOCTL_ENSYNTH_EN 0x01000000U 5815 #define LRFDRFE32_DIVCTL_ANAISOCTL_ENSYNTH_DIS 0x00000000U 5816 5817 // Field: [23] TXPH18020DBMDIV 5818 // 5819 // ENUMs: 5820 // EN Enable divider 5821 // DIS Disable divider 5822 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH18020DBMDIV 0x00800000U 5823 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH18020DBMDIV_M 0x00800000U 5824 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH18020DBMDIV_S 23U 5825 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH18020DBMDIV_EN 0x00800000U 5826 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH18020DBMDIV_DIS 0x00000000U 5827 5828 // Field: [22] TXPH020DBMDIV 5829 // 5830 // ENUMs: 5831 // EN Enable divider 5832 // DIS Disable divider 5833 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH020DBMDIV 0x00400000U 5834 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH020DBMDIV_M 0x00400000U 5835 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH020DBMDIV_S 22U 5836 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH020DBMDIV_EN 0x00400000U 5837 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH020DBMDIV_DIS 0x00000000U 5838 5839 // Field: [21] TXPH180DIV 5840 // 5841 // ENUMs: 5842 // EN Enable divider 5843 // DIS Disable divider 5844 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH180DIV 0x00200000U 5845 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH180DIV_M 0x00200000U 5846 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH180DIV_S 21U 5847 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH180DIV_EN 0x00200000U 5848 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH180DIV_DIS 0x00000000U 5849 5850 // Field: [20] TXPH0DIV 5851 // 5852 // ENUMs: 5853 // EN Enable divider 5854 // DIS Disable divider 5855 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH0DIV 0x00100000U 5856 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH0DIV_M 0x00100000U 5857 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH0DIV_S 20U 5858 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH0DIV_EN 0x00100000U 5859 #define LRFDRFE32_DIVCTL_ANAISOCTL_TXPH0DIV_DIS 0x00000000U 5860 5861 // Field: [19] RXPH90DIV 5862 // 5863 // ENUMs: 5864 // EN Enable divider 5865 // DIS Disable divider 5866 #define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH90DIV 0x00080000U 5867 #define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH90DIV_M 0x00080000U 5868 #define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH90DIV_S 19U 5869 #define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH90DIV_EN 0x00080000U 5870 #define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH90DIV_DIS 0x00000000U 5871 5872 // Field: [18] RXPH0DIV 5873 // 5874 // ENUMs: 5875 // EN Enable divider 5876 // DIS Disable divider 5877 #define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH0DIV 0x00040000U 5878 #define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH0DIV_M 0x00040000U 5879 #define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH0DIV_S 18U 5880 #define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH0DIV_EN 0x00040000U 5881 #define LRFDRFE32_DIVCTL_ANAISOCTL_RXPH0DIV_DIS 0x00000000U 5882 5883 // Field: [17] Spare1 5884 // 5885 // ENUMs: 5886 // ONE The bit is 1 5887 // ZERO The bit is 0 5888 #define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE1 0x00020000U 5889 #define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE1_M 0x00020000U 5890 #define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE1_S 17U 5891 #define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE1_ONE 0x00020000U 5892 #define LRFDRFE32_DIVCTL_ANAISOCTL_SPARE1_ZERO 0x00000000U 5893 5894 // Field: [16] EN 5895 // 5896 // ENUMs: 5897 // ON Enable divider 5898 // OFF Disable divider 5899 #define LRFDRFE32_DIVCTL_ANAISOCTL_EN 0x00010000U 5900 #define LRFDRFE32_DIVCTL_ANAISOCTL_EN_M 0x00010000U 5901 #define LRFDRFE32_DIVCTL_ANAISOCTL_EN_S 16U 5902 #define LRFDRFE32_DIVCTL_ANAISOCTL_EN_ON 0x00010000U 5903 #define LRFDRFE32_DIVCTL_ANAISOCTL_EN_OFF 0x00000000U 5904 5905 // Field: [4] ADCDIGRSTN 5906 // 5907 // ENUMs: 5908 // ACTIVE Don't reset 5909 // RESET Reset 5910 #define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIGRSTN 0x00000010U 5911 #define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIGRSTN_M 0x00000010U 5912 #define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIGRSTN_S 4U 5913 #define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIGRSTN_ACTIVE 0x00000010U 5914 #define LRFDRFE32_DIVCTL_ANAISOCTL_ADCDIGRSTN_RESET 0x00000000U 5915 5916 // Field: [3] IFADC2SVTISO 5917 // 5918 // ENUMs: 5919 // ISOLATE Isolate 5920 // CONNECT Don't isolate 5921 #define LRFDRFE32_DIVCTL_ANAISOCTL_IFADC2SVTISO 0x00000008U 5922 #define LRFDRFE32_DIVCTL_ANAISOCTL_IFADC2SVTISO_M 0x00000008U 5923 #define LRFDRFE32_DIVCTL_ANAISOCTL_IFADC2SVTISO_S 3U 5924 #define LRFDRFE32_DIVCTL_ANAISOCTL_IFADC2SVTISO_ISOLATE 0x00000008U 5925 #define LRFDRFE32_DIVCTL_ANAISOCTL_IFADC2SVTISO_CONNECT 0x00000000U 5926 5927 // Field: [2] DIV2IFADCISO 5928 // 5929 // ENUMs: 5930 // ISOLATE Isolate 5931 // CONNECT Don't isolate 5932 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2IFADCISO 0x00000004U 5933 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2IFADCISO_M 0x00000004U 5934 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2IFADCISO_S 2U 5935 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2IFADCISO_ISOLATE 0x00000004U 5936 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2IFADCISO_CONNECT 0x00000000U 5937 5938 // Field: [1] MTDC2SVTISO 5939 // 5940 // ENUMs: 5941 // ISOLATE Isolate 5942 // CONNECT Don't isolate 5943 #define LRFDRFE32_DIVCTL_ANAISOCTL_MTDC2SVTISO 0x00000002U 5944 #define LRFDRFE32_DIVCTL_ANAISOCTL_MTDC2SVTISO_M 0x00000002U 5945 #define LRFDRFE32_DIVCTL_ANAISOCTL_MTDC2SVTISO_S 1U 5946 #define LRFDRFE32_DIVCTL_ANAISOCTL_MTDC2SVTISO_ISOLATE 0x00000002U 5947 #define LRFDRFE32_DIVCTL_ANAISOCTL_MTDC2SVTISO_CONNECT 0x00000000U 5948 5949 // Field: [0] DIV2MTDCISO 5950 // 5951 // ENUMs: 5952 // ISOLATE Isolate 5953 // CONNECT Don't isolate 5954 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2MTDCISO 0x00000001U 5955 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2MTDCISO_M 0x00000001U 5956 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2MTDCISO_S 0U 5957 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2MTDCISO_ISOLATE 0x00000001U 5958 #define LRFDRFE32_DIVCTL_ANAISOCTL_DIV2MTDCISO_CONNECT 0x00000000U 5959 5960 //***************************************************************************** 5961 // 5962 // Register: LRFDRFE32_O_MAGNACC0_RXCTRL 5963 // 5964 //***************************************************************************** 5965 // Field: [31:16] VAL 5966 // 5967 // ENUMs: 5968 // ALLONES All the bits are 1 5969 // ALLZEROS All the bits are 0 5970 #define LRFDRFE32_MAGNACC0_RXCTRL_VAL_W 16U 5971 #define LRFDRFE32_MAGNACC0_RXCTRL_VAL_M 0xFFFF0000U 5972 #define LRFDRFE32_MAGNACC0_RXCTRL_VAL_S 16U 5973 #define LRFDRFE32_MAGNACC0_RXCTRL_VAL_ALLONES 0xFFFF0000U 5974 #define LRFDRFE32_MAGNACC0_RXCTRL_VAL_ALLZEROS 0x00000000U 5975 5976 // Field: [12] SPARE 5977 // 5978 // ENUMs: 5979 // ONE The bit is 1 5980 // ZERO The bit is 0 5981 #define LRFDRFE32_MAGNACC0_RXCTRL_SPARE 0x00001000U 5982 #define LRFDRFE32_MAGNACC0_RXCTRL_SPARE_M 0x00001000U 5983 #define LRFDRFE32_MAGNACC0_RXCTRL_SPARE_S 12U 5984 #define LRFDRFE32_MAGNACC0_RXCTRL_SPARE_ONE 0x00001000U 5985 #define LRFDRFE32_MAGNACC0_RXCTRL_SPARE_ZERO 0x00000000U 5986 5987 // Field: [11:9] ATTN 5988 // 5989 // ENUMs: 5990 // _21DB 21dB attenuation 5991 // _18DB 18dB attenuation 5992 // _15DB 15dB attenuation 5993 // _12DB 12dB attenuation 5994 // _9DB 9dB attenuation 5995 // _6DB 6dB attenuation 5996 // _3DB 3dB attenuation 5997 // NOATT No attenuation 5998 #define LRFDRFE32_MAGNACC0_RXCTRL_ATTN_W 3U 5999 #define LRFDRFE32_MAGNACC0_RXCTRL_ATTN_M 0x00000E00U 6000 #define LRFDRFE32_MAGNACC0_RXCTRL_ATTN_S 9U 6001 #define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__21DB 0x00000E00U 6002 #define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__18DB 0x00000C00U 6003 #define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__15DB 0x00000A00U 6004 #define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__12DB 0x00000800U 6005 #define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__9DB 0x00000600U 6006 #define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__6DB 0x00000400U 6007 #define LRFDRFE32_MAGNACC0_RXCTRL_ATTN__3DB 0x00000200U 6008 #define LRFDRFE32_MAGNACC0_RXCTRL_ATTN_NOATT 0x00000000U 6009 6010 // Field: [8:4] IFAMPGC 6011 // 6012 // ENUMs: 6013 // MAX Set IFAMP gain to MAX 6014 // MIN3DB Set gain to MAX - 3 dB 6015 // MIN6DB Set gain to MAX - 6 dB 6016 // MIN9DB Set gain to MAX - 9 dB 6017 // MIN12DB Set gain to MAX - 12 dB 6018 // MIN15DB Set gain to MAX - 15 dB 6019 #define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_W 5U 6020 #define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_M 0x000001F0U 6021 #define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_S 4U 6022 #define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_MAX 0x000001F0U 6023 #define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_MIN3DB 0x000000F0U 6024 #define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_MIN6DB 0x00000070U 6025 #define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_MIN9DB 0x00000030U 6026 #define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_MIN12DB 0x00000010U 6027 #define LRFDRFE32_MAGNACC0_RXCTRL_IFAMPGC_MIN15DB 0x00000000U 6028 6029 // Field: [3:0] LNAGAIN 6030 // 6031 // ENUMs: 6032 // MAX Set gain to MAX 6033 // MIN3DB Set gain to MAX - 3 dB 6034 // MIN6DB Set gain to MAX - 6 dB 6035 // MIN9DB Set gain to MAX - 9 dB 6036 // MIN12DB Set gain to MAX - 12 dB 6037 #define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_W 4U 6038 #define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_M 0x0000000FU 6039 #define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_S 0U 6040 #define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_MAX 0x0000000FU 6041 #define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_MIN3DB 0x00000007U 6042 #define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_MIN6DB 0x00000003U 6043 #define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_MIN9DB 0x00000001U 6044 #define LRFDRFE32_MAGNACC0_RXCTRL_LNAGAIN_MIN12DB 0x00000000U 6045 6046 //***************************************************************************** 6047 // 6048 // Register: LRFDRFE32_O_RSSI_MAGNACC1 6049 // 6050 //***************************************************************************** 6051 // Field: [23:16] RSSI_VAL 6052 // 6053 // ENUMs: 6054 // ALLONES All the bits are 1 6055 // ALLZEROS All the bits are 0 6056 #define LRFDRFE32_RSSI_MAGNACC1_RSSI_VAL_W 8U 6057 #define LRFDRFE32_RSSI_MAGNACC1_RSSI_VAL_M 0x00FF0000U 6058 #define LRFDRFE32_RSSI_MAGNACC1_RSSI_VAL_S 16U 6059 #define LRFDRFE32_RSSI_MAGNACC1_RSSI_VAL_ALLONES 0x00FF0000U 6060 #define LRFDRFE32_RSSI_MAGNACC1_RSSI_VAL_ALLZEROS 0x00000000U 6061 6062 // Field: [15:0] MAGNACC1_VAL 6063 // 6064 // ENUMs: 6065 // ALLONES All the bits are 1 6066 // ALLZEROS All the bits are 0 6067 #define LRFDRFE32_RSSI_MAGNACC1_MAGNACC1_VAL_W 16U 6068 #define LRFDRFE32_RSSI_MAGNACC1_MAGNACC1_VAL_M 0x0000FFFFU 6069 #define LRFDRFE32_RSSI_MAGNACC1_MAGNACC1_VAL_S 0U 6070 #define LRFDRFE32_RSSI_MAGNACC1_MAGNACC1_VAL_ALLONES 0x0000FFFFU 6071 #define LRFDRFE32_RSSI_MAGNACC1_MAGNACC1_VAL_ALLZEROS 0x00000000U 6072 6073 //***************************************************************************** 6074 // 6075 // Register: LRFDRFE32_O_RFGAIN_RSSIMAX 6076 // 6077 //***************************************************************************** 6078 // Field: [23:16] DBGAIN 6079 // 6080 // ENUMs: 6081 // ALLONES All the bits are 1 6082 // ALLZEROS All the bits are 0 6083 #define LRFDRFE32_RFGAIN_RSSIMAX_DBGAIN_W 8U 6084 #define LRFDRFE32_RFGAIN_RSSIMAX_DBGAIN_M 0x00FF0000U 6085 #define LRFDRFE32_RFGAIN_RSSIMAX_DBGAIN_S 16U 6086 #define LRFDRFE32_RFGAIN_RSSIMAX_DBGAIN_ALLONES 0x00FF0000U 6087 #define LRFDRFE32_RFGAIN_RSSIMAX_DBGAIN_ALLZEROS 0x00000000U 6088 6089 // Field: [7:0] VAL 6090 // 6091 // ENUMs: 6092 // ALLONES All the bits are 1 6093 // ALLZEROS All the bits are 0 6094 #define LRFDRFE32_RFGAIN_RSSIMAX_VAL_W 8U 6095 #define LRFDRFE32_RFGAIN_RSSIMAX_VAL_M 0x000000FFU 6096 #define LRFDRFE32_RFGAIN_RSSIMAX_VAL_S 0U 6097 #define LRFDRFE32_RFGAIN_RSSIMAX_VAL_ALLONES 0x000000FFU 6098 #define LRFDRFE32_RFGAIN_RSSIMAX_VAL_ALLZEROS 0x00000000U 6099 6100 //***************************************************************************** 6101 // 6102 // Register: LRFDRFE32_O_DIVSTA_IFADCSTAT 6103 // 6104 //***************************************************************************** 6105 // Field: [16] STAT 6106 // 6107 // ENUMs: 6108 // BUSY Serial divider is busy and result is not available 6109 // yet 6110 // IDLE Serial divider is idle 6111 #define LRFDRFE32_DIVSTA_IFADCSTAT_STAT 0x00010000U 6112 #define LRFDRFE32_DIVSTA_IFADCSTAT_STAT_M 0x00010000U 6113 #define LRFDRFE32_DIVSTA_IFADCSTAT_STAT_S 16U 6114 #define LRFDRFE32_DIVSTA_IFADCSTAT_STAT_BUSY 0x00010000U 6115 #define LRFDRFE32_DIVSTA_IFADCSTAT_STAT_IDLE 0x00000000U 6116 6117 // Field: [6:2] QUANTCALVAL 6118 // 6119 // ENUMs: 6120 // COMP1 I comparator 6121 // COMP0 Q Comparator 6122 #define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALVAL_W 5U 6123 #define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALVAL_M 0x0000007CU 6124 #define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALVAL_S 2U 6125 #define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALVAL_COMP1 0x00000004U 6126 #define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALVAL_COMP0 0x00000000U 6127 6128 // Field: [1] QUANTCALDONE 6129 // 6130 // ENUMs: 6131 // READY Calibration is complete 6132 // NOT_READY Calibration is not finished 6133 #define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALDONE 0x00000002U 6134 #define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALDONE_M 0x00000002U 6135 #define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALDONE_S 1U 6136 #define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALDONE_READY 0x00000002U 6137 #define LRFDRFE32_DIVSTA_IFADCSTAT_QUANTCALDONE_NOT_READY 0x00000000U 6138 6139 //***************************************************************************** 6140 // 6141 // Register: LRFDRFE32_O_DIVIDEND 6142 // 6143 //***************************************************************************** 6144 // Field: [31:0] VAL 6145 // 6146 // ENUMs: 6147 // ALLONES All the bits are 1 6148 // ALLZEROS All the bits are 0 6149 #define LRFDRFE32_DIVIDEND_VAL_W 32U 6150 #define LRFDRFE32_DIVIDEND_VAL_M 0xFFFFFFFFU 6151 #define LRFDRFE32_DIVIDEND_VAL_S 0U 6152 #define LRFDRFE32_DIVIDEND_VAL_ALLONES 0x0000FFFFU 6153 #define LRFDRFE32_DIVIDEND_VAL_ALLZEROS 0x00000000U 6154 6155 //***************************************************************************** 6156 // 6157 // Register: LRFDRFE32_O_DIVISOR 6158 // 6159 //***************************************************************************** 6160 // Field: [31:0] VAL 6161 // 6162 // ENUMs: 6163 // ALLONES All the bits are 1 6164 // ALLZEROS All the bits are 0 6165 #define LRFDRFE32_DIVISOR_VAL_W 32U 6166 #define LRFDRFE32_DIVISOR_VAL_M 0xFFFFFFFFU 6167 #define LRFDRFE32_DIVISOR_VAL_S 0U 6168 #define LRFDRFE32_DIVISOR_VAL_ALLONES 0x0000FFFFU 6169 #define LRFDRFE32_DIVISOR_VAL_ALLZEROS 0x00000000U 6170 6171 //***************************************************************************** 6172 // 6173 // Register: LRFDRFE32_O_QUOTIENT 6174 // 6175 //***************************************************************************** 6176 // Field: [31:0] VAL 6177 // 6178 // ENUMs: 6179 // ALLONES All the bits are 1 6180 // ALLZEROS All the bits are 0 6181 #define LRFDRFE32_QUOTIENT_VAL_W 32U 6182 #define LRFDRFE32_QUOTIENT_VAL_M 0xFFFFFFFFU 6183 #define LRFDRFE32_QUOTIENT_VAL_S 0U 6184 #define LRFDRFE32_QUOTIENT_VAL_ALLONES 0x0000FFFFU 6185 #define LRFDRFE32_QUOTIENT_VAL_ALLZEROS 0x00000000U 6186 6187 //***************************************************************************** 6188 // 6189 // Register: LRFDRFE32_O_PRODUCT 6190 // 6191 //***************************************************************************** 6192 // Field: [31:0] VAL 6193 // 6194 // ENUMs: 6195 // ALLONES All the bits are 1 6196 // ALLZEROS All the bits are 0 6197 #define LRFDRFE32_PRODUCT_VAL_W 32U 6198 #define LRFDRFE32_PRODUCT_VAL_M 0xFFFFFFFFU 6199 #define LRFDRFE32_PRODUCT_VAL_S 0U 6200 #define LRFDRFE32_PRODUCT_VAL_ALLONES 0x0000FFFFU 6201 #define LRFDRFE32_PRODUCT_VAL_ALLZEROS 0x00000000U 6202 6203 //***************************************************************************** 6204 // 6205 // Register: LRFDRFE32_O_MULTSTA 6206 // 6207 //***************************************************************************** 6208 // Field: [0] STAT 6209 // 6210 // ENUMs: 6211 // BUSY Multiplier is busy, result is not ready yet 6212 // IDLE Multiplier is idle 6213 #define LRFDRFE32_MULTSTA_STAT 0x00000001U 6214 #define LRFDRFE32_MULTSTA_STAT_M 0x00000001U 6215 #define LRFDRFE32_MULTSTA_STAT_S 0U 6216 #define LRFDRFE32_MULTSTA_STAT_BUSY 0x00000001U 6217 #define LRFDRFE32_MULTSTA_STAT_IDLE 0x00000000U 6218 6219 //***************************************************************************** 6220 // 6221 // Register: LRFDRFE32_O_MULTCFG 6222 // 6223 //***************************************************************************** 6224 // Field: [0] MODE 6225 // 6226 // ENUMs: 6227 // SIGNED Multiplier assumes inputs are signed numbers 6228 // UNSIGNED Multiplier assumes inputs are unsigned numbers 6229 #define LRFDRFE32_MULTCFG_MODE 0x00000001U 6230 #define LRFDRFE32_MULTCFG_MODE_M 0x00000001U 6231 #define LRFDRFE32_MULTCFG_MODE_S 0U 6232 #define LRFDRFE32_MULTCFG_MODE_SIGNED 0x00000001U 6233 #define LRFDRFE32_MULTCFG_MODE_UNSIGNED 0x00000000U 6234 6235 6236 #endif // __LRFDRFE32__ 6237
