1 /****************************************************************************** 2 * Filename: hw_lrfdpbe_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_LRFDPBE_H__ 34 #define __HW_LRFDPBE_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // LRFDPBE component 40 // 41 //***************************************************************************** 42 // Packet Building Engine Enable Register 43 #define LRFDPBE_O_ENABLE 0x00000000U 44 45 // PBE program source select register 46 #define LRFDPBE_O_FWSRC 0x00000004U 47 48 // Packet Building Engine Initialization Register 49 #define LRFDPBE_O_INIT 0x00000008U 50 51 // Packet Building Engine (PBE) Strobe Register 0 52 #define LRFDPBE_O_STROBES0 0x0000000CU 53 54 // Interrupt generate register 55 #define LRFDPBE_O_IRQ 0x00000010U 56 57 // PBE Event Flag Register 0 58 #define LRFDPBE_O_EVT0 0x00000014U 59 60 // PBE Event Flag Register 1 61 #define LRFDPBE_O_EVT1 0x00000018U 62 63 // PBE Event Mask Register 0 64 #define LRFDPBE_O_EVTMSK0 0x0000001CU 65 66 // PBE Event Mask Register 1 67 #define LRFDPBE_O_EVTMSK1 0x00000020U 68 69 // PBE Event Clear Register 0 70 #define LRFDPBE_O_EVTCLR0 0x00000024U 71 72 // PBE Event Mask Register 1 73 #define LRFDPBE_O_EVTCLR1 0x00000028U 74 75 // Packet Building Engine Power-down Register 76 #define LRFDPBE_O_PDREQ 0x0000002CU 77 78 // PBE API Command Register 79 #define LRFDPBE_O_API 0x00000030U 80 81 // PBE-to-MCE Send Data Register 82 #define LRFDPBE_O_MCEDATOUT0 0x00000034U 83 84 // MCE-to-PBE Receive Data Register 85 #define LRFDPBE_O_MCEDATIN0 0x00000038U 86 87 // PBE-to-MCE Send Command Register 88 #define LRFDPBE_O_MCECMDOUT 0x0000003CU 89 90 // MCE-to-PBE Receive Command Register 91 #define LRFDPBE_O_MCECMDIN 0x00000040U 92 93 // Modem API Command Register 94 #define LRFDPBE_O_MDMAPI 0x00000044U 95 96 // Modem Command Status Register 97 #define LRFDPBE_O_MDMMSGBOX 0x00000048U 98 99 // Frequency Offset 100 #define LRFDPBE_O_FREQ 0x0000004CU 101 102 // Link quality indicator 103 #define LRFDPBE_O_MDMLQI 0x00000050U 104 105 // PBE-to-RFE Send Data Register 106 #define LRFDPBE_O_RFEDATOUT0 0x00000054U 107 108 // RFE-to-PBE Receive Data Register 109 #define LRFDPBE_O_RFEDATIN0 0x00000058U 110 111 // PBE-to-RFE Send Command Register 112 #define LRFDPBE_O_RFECMDOUT 0x0000005CU 113 114 // RFE-to-PBE Receive Command Register 115 #define LRFDPBE_O_RFECMDIN 0x00000060U 116 117 // RFE API Command Register 118 #define LRFDPBE_O_RFEAPI 0x00000064U 119 120 // RFE Command Parameter 0 121 #define LRFDPBE_O_RFECMDPAR0 0x00000068U 122 123 // RFE Command Parameter 1 124 #define LRFDPBE_O_RFECMDPAR1 0x0000006CU 125 126 // RFE Command Status and Message Box Register 127 #define LRFDPBE_O_RFEMSGBOX 0x00000070U 128 129 // RSSI Value Register 130 #define LRFDPBE_O_RFERSSI 0x00000074U 131 132 // RSSI Maximum Value Register 133 #define LRFDPBE_O_RFERSSIMAX 0x00000078U 134 135 // RF front-end gain value 136 #define LRFDPBE_O_RFERFGAIN 0x0000007CU 137 138 // Modem Sync Word Register 0 139 #define LRFDPBE_O_MDMSYNCAL 0x00000080U 140 141 // Modem Sync Word Register 1 142 #define LRFDPBE_O_MDMSYNCAH 0x00000084U 143 144 // Modem Sync Word Register 2 145 #define LRFDPBE_O_MDMSYNCBL 0x00000088U 146 147 // Modem Sync Word Register 3 148 #define LRFDPBE_O_MDMSYNCBH 0x0000008CU 149 150 // Modem API Command Parameter 0 151 #define LRFDPBE_O_MDMCMDPAR0 0x00000090U 152 153 // Modem API Command Parameter 1 154 #define LRFDPBE_O_MDMCMDPAR1 0x00000094U 155 156 // Modem API Command Parameter 2 157 #define LRFDPBE_O_MDMCMDPAR2 0x00000098U 158 159 // LFSR 0 Polynomial Definition 160 #define LRFDPBE_O_POLY0L 0x000000A0U 161 162 // LFSR 0 Polynomial Definition 163 #define LRFDPBE_O_POLY0H 0x000000A4U 164 165 // LFSR 1 Polynomial Definition 166 #define LRFDPBE_O_POLY1L 0x000000A8U 167 168 // LFSR 1 Polynomial Definition 169 #define LRFDPBE_O_POLY1H 0x000000ACU 170 171 // Packet Handler Accelerator Config Register 172 #define LRFDPBE_O_PHACFG 0x000000B0U 173 174 // FIFO configuration register 175 #define LRFDPBE_O_FCFG0 0x000000B4U 176 177 // FIFO configuration register 178 #define LRFDPBE_O_FCFG1 0x000000B8U 179 180 // FIFO configuration register 181 #define LRFDPBE_O_FCFG2 0x000000BCU 182 183 // FIFO configuration register 184 #define LRFDPBE_O_FCFG3 0x000000C0U 185 186 // FIFO configuration register 187 #define LRFDPBE_O_FCFG4 0x000000C4U 188 189 // FIFO configuration register 190 #define LRFDPBE_O_FCFG5 0x000000C8U 191 192 // FIFO write pointer 193 #define LRFDPBE_O_RXFWBTHRS 0x000000CCU 194 195 // FIFO read pointer 196 #define LRFDPBE_O_RXFRBTHRS 0x000000D0U 197 198 // FIFO write pointer 199 #define LRFDPBE_O_TXFWBTHRS 0x000000D4U 200 201 // FIFO read pointer 202 #define LRFDPBE_O_TXFRBTHRS 0x000000D8U 203 204 // PBE Timer Control Register 205 #define LRFDPBE_O_TIMCTL 0x000000DCU 206 207 // Prescaler setting for timer 0 and timer 1 208 #define LRFDPBE_O_TIMPRE 0x000000E0U 209 210 // PBE Timer Period Configuration 211 #define LRFDPBE_O_TIMPER0 0x000000E4U 212 213 // PBE Timer Period Configuration 214 #define LRFDPBE_O_TIMPER1 0x000000E8U 215 216 // PBE Counter Capture Value 217 #define LRFDPBE_O_TIMCAPT0 0x000000ECU 218 219 // PBE Counter Capture Value 220 #define LRFDPBE_O_TIMCAPT1 0x000000F0U 221 222 // PBE Tracer Send Trigger Register 223 #define LRFDPBE_O_TRCCTL 0x00000100U 224 225 // PBE Tracer Status Register 226 #define LRFDPBE_O_TRCSTAT 0x00000104U 227 228 // PBE Tracer Commmand Register 229 #define LRFDPBE_O_TRCCMD 0x00000108U 230 231 // PBE Tracer Command Parameter Register 0 232 #define LRFDPBE_O_TRCPAR0 0x0000010CU 233 234 // PBE Tracer Command Parameter Register 1 235 #define LRFDPBE_O_TRCPAR1 0x00000110U 236 237 // PBE Direct GPO control register 238 #define LRFDPBE_O_GPOCTRL 0x00000114U 239 240 // Modem FIFO Write Register 241 #define LRFDPBE_O_MDMFWR 0x00000118U 242 243 // Modem FIFO Read Register 244 #define LRFDPBE_O_MDMFRD 0x0000011CU 245 246 // Modem FIFO Write Configuration 247 #define LRFDPBE_O_MDMFWRCTL 0x00000120U 248 249 // Modem FIFO Read Configuration 250 #define LRFDPBE_O_MDMFRDCTL 0x00000124U 251 252 // Modem FIFO Configuration for watermark thresholds 253 #define LRFDPBE_O_MDMFCFG 0x00000128U 254 255 // Modem FIFO Status Flags 256 #define LRFDPBE_O_MDMFSTA 0x0000012CU 257 258 // Packet Handler Accelerator Status 259 #define LRFDPBE_O_PHASTA 0x00000134U 260 261 // LFSR 0 Current Value 262 #define LRFDPBE_O_LFSR0L 0x00000138U 263 264 // LFSR 0 Current Value 265 #define LRFDPBE_O_LFSR0H 0x0000013CU 266 267 // LFSR 0 Current Value, Bit-reversed 268 #define LRFDPBE_O_LFSR0BRL 0x00000140U 269 270 // LFSR 0 Current Value, Bit-reversed 271 #define LRFDPBE_O_LFSR0BRH 0x00000144U 272 273 // LFSR 1 Current Value 274 #define LRFDPBE_O_LFSR1L 0x00000148U 275 276 // LFSR 1 Current Value 277 #define LRFDPBE_O_LFSR1H 0x0000014CU 278 279 // LFSR 1 Current Value, Bit-reversed 280 #define LRFDPBE_O_LFSR1BRL 0x00000150U 281 282 // LFSR 1 Current Value, Bit-reversed 283 #define LRFDPBE_O_LFSR1BRH 0x00000154U 284 285 // LFSR 0 Input, LSB First 286 #define LRFDPBE_O_LFSR0INL 0x00000158U 287 288 // Control input size of LSFR 0 289 #define LRFDPBE_O_LFSR0N 0x0000015CU 290 291 // LFSR 0 Input, MSB First 292 #define LRFDPBE_O_LFSR0INM 0x00000160U 293 294 // LFSR 0 Output 295 #define LRFDPBE_O_PHAOUT0 0x00000164U 296 297 // LFSR 1 Input, LSB First 298 #define LRFDPBE_O_LFSR1INL 0x00000168U 299 300 // Controls input size of LFSR 1 301 #define LRFDPBE_O_LFSR1N 0x0000016CU 302 303 // LFSR 1 Input, MSB First 304 #define LRFDPBE_O_LFSR1INM 0x00000170U 305 306 // LFSR 0 Output, Bit-reversed 307 #define LRFDPBE_O_PHAOUT0BR 0x00000174U 308 309 // Systimer capture value 310 #define LRFDPBE_O_SYSTIM0L 0x00000180U 311 312 // Systimer capture value 313 #define LRFDPBE_O_SYSTIM0H 0x00000184U 314 315 // Systimer capture value 316 #define LRFDPBE_O_SYSTIM1L 0x00000188U 317 318 // Systimer capture value 319 #define LRFDPBE_O_SYSTIM1H 0x0000018CU 320 321 // Systimer capture value 322 #define LRFDPBE_O_SYSTIM2L 0x00000190U 323 324 // Systimer capture value 325 #define LRFDPBE_O_SYSTIM2H 0x00000194U 326 327 // PBE Direct GPI Status 328 #define LRFDPBE_O_GPI 0x00000198U 329 330 // The FIFO command register 331 #define LRFDPBE_O_FCMD 0x000001A0U 332 333 // FIFO status register 334 #define LRFDPBE_O_FSTAT 0x000001A4U 335 336 // FIFO write pointer 337 #define LRFDPBE_O_RXFWP 0x000001A8U 338 339 // FIFO read pointer 340 #define LRFDPBE_O_RXFRP 0x000001ACU 341 342 // Rx FIFO start of written package 343 #define LRFDPBE_O_RXFSWP 0x000001B0U 344 345 // Rxfifo start of read package. 346 #define LRFDPBE_O_RXFSRP 0x000001B4U 347 348 // TXFIFO write pointer 349 #define LRFDPBE_O_TXFWP 0x000001B8U 350 351 // TXFIFO read pointer 352 #define LRFDPBE_O_TXFRP 0x000001BCU 353 354 // TXFIFO start of written package 355 #define LRFDPBE_O_TXFSWP 0x000001C0U 356 357 // TXFIFO start of read package. 358 #define LRFDPBE_O_TXFSRP 0x000001C4U 359 360 // The amount of bytes which are deallocated and not yet written. 361 #define LRFDPBE_O_RXFWRITABLE 0x000001C8U 362 363 // The amount of bytes which are comitted and not yet read. 364 #define LRFDPBE_O_RXFREADABLE 0x000001CCU 365 366 // The amount of bytes which are deallocated and not yet written. 367 #define LRFDPBE_O_TXFWRITABLE 0x000001D0U 368 369 // The amount of bytes which are comitted and not yet read. 370 #define LRFDPBE_O_TXFREADABLE 0x000001D4U 371 372 // FIFO read access register 373 #define LRFDPBE_O_RXFBRD 0x000001D8U 374 375 // FIFO access register 376 #define LRFDPBE_O_RXFBWR 0x000001DCU 377 378 // FIFO read access register 379 #define LRFDPBE_O_TXFBRD 0x000001E0U 380 381 // FIFO access register 382 #define LRFDPBE_O_TXFBWR 0x000001E4U 383 384 // FIFO read access register 385 #define LRFDPBE_O_RXFHRD 0x000001E8U 386 387 // FIFO access register 388 #define LRFDPBE_O_RXFHWR 0x000001ECU 389 390 // FIFO read access register 391 #define LRFDPBE_O_TXFHRD 0x000001F0U 392 393 // FIFO access register 394 #define LRFDPBE_O_TXFHWR 0x000001F4U 395 396 //***************************************************************************** 397 // 398 // Register: LRFDPBE_O_ENABLE 399 // 400 //***************************************************************************** 401 // Field: [2] MDMF 402 // 403 // Modem fifo, OR'ed with equivalent siganl in modem 404 // ENUMs: 405 // EN The bit is 1 406 // DIS The bit is 0 407 #define LRFDPBE_ENABLE_MDMF 0x00000004U 408 #define LRFDPBE_ENABLE_MDMF_M 0x00000004U 409 #define LRFDPBE_ENABLE_MDMF_S 2U 410 #define LRFDPBE_ENABLE_MDMF_EN 0x00000004U 411 #define LRFDPBE_ENABLE_MDMF_DIS 0x00000000U 412 413 // Field: [1] LOCTIM 414 // 415 // Enables the Local timer 416 // ENUMs: 417 // EN The bit is 1 418 // DIS The bit is 0 419 #define LRFDPBE_ENABLE_LOCTIM 0x00000002U 420 #define LRFDPBE_ENABLE_LOCTIM_M 0x00000002U 421 #define LRFDPBE_ENABLE_LOCTIM_S 1U 422 #define LRFDPBE_ENABLE_LOCTIM_EN 0x00000002U 423 #define LRFDPBE_ENABLE_LOCTIM_DIS 0x00000000U 424 425 // Field: [0] TOPSM 426 // 427 // Enables the TOPsm (PBE) 428 // ENUMs: 429 // EN The bit is 1 430 // DIS The bit is 0 431 #define LRFDPBE_ENABLE_TOPSM 0x00000001U 432 #define LRFDPBE_ENABLE_TOPSM_M 0x00000001U 433 #define LRFDPBE_ENABLE_TOPSM_S 0U 434 #define LRFDPBE_ENABLE_TOPSM_EN 0x00000001U 435 #define LRFDPBE_ENABLE_TOPSM_DIS 0x00000000U 436 437 //***************************************************************************** 438 // 439 // Register: LRFDPBE_O_FWSRC 440 // 441 //***************************************************************************** 442 // Field: [2] DATARAM 443 // 444 // Selects which RAM will be used for data storage 445 // ENUMs: 446 // S2RRAM Use S2RRAM for data 447 // PBERAM Use PBERAM for data 448 #define LRFDPBE_FWSRC_DATARAM 0x00000004U 449 #define LRFDPBE_FWSRC_DATARAM_M 0x00000004U 450 #define LRFDPBE_FWSRC_DATARAM_S 2U 451 #define LRFDPBE_FWSRC_DATARAM_S2RRAM 0x00000004U 452 #define LRFDPBE_FWSRC_DATARAM_PBERAM 0x00000000U 453 454 // Field: [1] FWRAM 455 // 456 // Select which RAM we run FW from 457 // ENUMs: 458 // S2RRAM Run code from S2RRAM 459 // PBERAM Run code from PBERAM 460 #define LRFDPBE_FWSRC_FWRAM 0x00000002U 461 #define LRFDPBE_FWSRC_FWRAM_M 0x00000002U 462 #define LRFDPBE_FWSRC_FWRAM_S 1U 463 #define LRFDPBE_FWSRC_FWRAM_S2RRAM 0x00000002U 464 #define LRFDPBE_FWSRC_FWRAM_PBERAM 0x00000000U 465 466 // Field: [0] BANK 467 // 468 // Sets the MSB of the address to the memory holding the program. 469 // ENUMs: 470 // ONE Run code from bank 1 471 // ZERO Run code from bank 0 472 #define LRFDPBE_FWSRC_BANK 0x00000001U 473 #define LRFDPBE_FWSRC_BANK_M 0x00000001U 474 #define LRFDPBE_FWSRC_BANK_S 0U 475 #define LRFDPBE_FWSRC_BANK_ONE 0x00000001U 476 #define LRFDPBE_FWSRC_BANK_ZERO 0x00000000U 477 478 //***************************************************************************** 479 // 480 // Register: LRFDPBE_O_INIT 481 // 482 //***************************************************************************** 483 // Field: [4] RFE 484 // 485 // Do an INIT of the TOPSM in RFE, OR'ed with equivalent signal in RFE 486 // ENUMs: 487 // RESET The bit is 1 488 // NO_EFFECT The bit is 0 489 #define LRFDPBE_INIT_RFE 0x00000010U 490 #define LRFDPBE_INIT_RFE_M 0x00000010U 491 #define LRFDPBE_INIT_RFE_S 4U 492 #define LRFDPBE_INIT_RFE_RESET 0x00000010U 493 #define LRFDPBE_INIT_RFE_NO_EFFECT 0x00000000U 494 495 // Field: [3] MDM 496 // 497 // Do an INIT of the TOPSM in MDM, OR'ed with equivalent signal in MDM 498 // ENUMs: 499 // RESET The bit is 1 500 // NO_EFFECT The bit is 0 501 #define LRFDPBE_INIT_MDM 0x00000008U 502 #define LRFDPBE_INIT_MDM_M 0x00000008U 503 #define LRFDPBE_INIT_MDM_S 3U 504 #define LRFDPBE_INIT_MDM_RESET 0x00000008U 505 #define LRFDPBE_INIT_MDM_NO_EFFECT 0x00000000U 506 507 // Field: [2] MDMF 508 // 509 // Modem FIFO, OR'ed with equivalent signal in MDM 510 // ENUMs: 511 // RESET The bit is 1 512 // NO_EFFECT The bit is 0 513 #define LRFDPBE_INIT_MDMF 0x00000004U 514 #define LRFDPBE_INIT_MDMF_M 0x00000004U 515 #define LRFDPBE_INIT_MDMF_S 2U 516 #define LRFDPBE_INIT_MDMF_RESET 0x00000004U 517 #define LRFDPBE_INIT_MDMF_NO_EFFECT 0x00000000U 518 519 // Field: [1] LOCTIM 520 // 521 // Synch reset Local timer 522 // ENUMs: 523 // RESET The bit is 1 524 // NO_EFFECT The bit is 0 525 #define LRFDPBE_INIT_LOCTIM 0x00000002U 526 #define LRFDPBE_INIT_LOCTIM_M 0x00000002U 527 #define LRFDPBE_INIT_LOCTIM_S 1U 528 #define LRFDPBE_INIT_LOCTIM_RESET 0x00000002U 529 #define LRFDPBE_INIT_LOCTIM_NO_EFFECT 0x00000000U 530 531 // Field: [0] TOPSM 532 // 533 // Synch reset TOPsm (PBE) 534 // ENUMs: 535 // RESET The bit is 1 536 // NO_EFFECT The bit is 0 537 #define LRFDPBE_INIT_TOPSM 0x00000001U 538 #define LRFDPBE_INIT_TOPSM_M 0x00000001U 539 #define LRFDPBE_INIT_TOPSM_S 0U 540 #define LRFDPBE_INIT_TOPSM_RESET 0x00000001U 541 #define LRFDPBE_INIT_TOPSM_NO_EFFECT 0x00000000U 542 543 //***************************************************************************** 544 // 545 // Register: LRFDPBE_O_STROBES0 546 // 547 //***************************************************************************** 548 // Field: [6] TIMCAPT1 549 // 550 // PBE timer 1 capture strobe 551 // ENUMs: 552 // ONE The bit is 1 553 // ZERO The bit is 0 554 #define LRFDPBE_STROBES0_TIMCAPT1 0x00000040U 555 #define LRFDPBE_STROBES0_TIMCAPT1_M 0x00000040U 556 #define LRFDPBE_STROBES0_TIMCAPT1_S 6U 557 #define LRFDPBE_STROBES0_TIMCAPT1_ONE 0x00000040U 558 #define LRFDPBE_STROBES0_TIMCAPT1_ZERO 0x00000000U 559 560 // Field: [5] TIMCAPT0 561 // 562 // PBE timer 0 capture strobe 563 // ENUMs: 564 // ONE The bit is 1 565 // ZERO The bit is 0 566 #define LRFDPBE_STROBES0_TIMCAPT0 0x00000020U 567 #define LRFDPBE_STROBES0_TIMCAPT0_M 0x00000020U 568 #define LRFDPBE_STROBES0_TIMCAPT0_S 5U 569 #define LRFDPBE_STROBES0_TIMCAPT0_ONE 0x00000020U 570 #define LRFDPBE_STROBES0_TIMCAPT0_ZERO 0x00000000U 571 572 // Field: [4] S2RTRIG 573 // 574 // Arm/Trigger the S2R module 575 // ENUMs: 576 // ARM The bit is 1 577 // NO_EFFECT The bit is 0 578 #define LRFDPBE_STROBES0_S2RTRIG 0x00000010U 579 #define LRFDPBE_STROBES0_S2RTRIG_M 0x00000010U 580 #define LRFDPBE_STROBES0_S2RTRIG_S 4U 581 #define LRFDPBE_STROBES0_S2RTRIG_ARM 0x00000010U 582 #define LRFDPBE_STROBES0_S2RTRIG_NO_EFFECT 0x00000000U 583 584 // Field: [3] DMATRIG 585 // 586 // FW triggered DMA transfer 587 // ENUMs: 588 // ARM The bit is 1 589 // NO_EFFECT The bit is 0 590 #define LRFDPBE_STROBES0_DMATRIG 0x00000008U 591 #define LRFDPBE_STROBES0_DMATRIG_M 0x00000008U 592 #define LRFDPBE_STROBES0_DMATRIG_S 3U 593 #define LRFDPBE_STROBES0_DMATRIG_ARM 0x00000008U 594 #define LRFDPBE_STROBES0_DMATRIG_NO_EFFECT 0x00000000U 595 596 // Field: [2] SYSTCAPT2 597 // 598 // Systimer capture 2 strobe 0 599 // ENUMs: 600 // ONE The bit is 1 601 // ZERO The bit is 0 602 #define LRFDPBE_STROBES0_SYSTCAPT2 0x00000004U 603 #define LRFDPBE_STROBES0_SYSTCAPT2_M 0x00000004U 604 #define LRFDPBE_STROBES0_SYSTCAPT2_S 2U 605 #define LRFDPBE_STROBES0_SYSTCAPT2_ONE 0x00000004U 606 #define LRFDPBE_STROBES0_SYSTCAPT2_ZERO 0x00000000U 607 608 // Field: [1] SYSTCAPT1 609 // 610 // Systimer capture1 strobe 0 611 // ENUMs: 612 // ONE The bit is 1 613 // ZERO The bit is 0 614 #define LRFDPBE_STROBES0_SYSTCAPT1 0x00000002U 615 #define LRFDPBE_STROBES0_SYSTCAPT1_M 0x00000002U 616 #define LRFDPBE_STROBES0_SYSTCAPT1_S 1U 617 #define LRFDPBE_STROBES0_SYSTCAPT1_ONE 0x00000002U 618 #define LRFDPBE_STROBES0_SYSTCAPT1_ZERO 0x00000000U 619 620 // Field: [0] SYSTCAPT0 621 // 622 // Systimer capture 0 strobe 0 623 // ENUMs: 624 // ONE The bit is 1 625 // ZERO The bit is 0 626 #define LRFDPBE_STROBES0_SYSTCAPT0 0x00000001U 627 #define LRFDPBE_STROBES0_SYSTCAPT0_M 0x00000001U 628 #define LRFDPBE_STROBES0_SYSTCAPT0_S 0U 629 #define LRFDPBE_STROBES0_SYSTCAPT0_ONE 0x00000001U 630 #define LRFDPBE_STROBES0_SYSTCAPT0_ZERO 0x00000000U 631 632 //***************************************************************************** 633 // 634 // Register: LRFDPBE_O_IRQ 635 // 636 //***************************************************************************** 637 // Field: [15] SOFT15 638 // 639 // Software defined interrupt 640 // ENUMs: 641 // ON The bit is 1 642 // OFF The bit is 0 643 #define LRFDPBE_IRQ_SOFT15 0x00008000U 644 #define LRFDPBE_IRQ_SOFT15_M 0x00008000U 645 #define LRFDPBE_IRQ_SOFT15_S 15U 646 #define LRFDPBE_IRQ_SOFT15_ON 0x00008000U 647 #define LRFDPBE_IRQ_SOFT15_OFF 0x00000000U 648 649 // Field: [14] SOFT14 650 // 651 // Software defined interrupt 652 // ENUMs: 653 // ON The bit is 1 654 // OFF The bit is 0 655 #define LRFDPBE_IRQ_SOFT14 0x00004000U 656 #define LRFDPBE_IRQ_SOFT14_M 0x00004000U 657 #define LRFDPBE_IRQ_SOFT14_S 14U 658 #define LRFDPBE_IRQ_SOFT14_ON 0x00004000U 659 #define LRFDPBE_IRQ_SOFT14_OFF 0x00000000U 660 661 // Field: [13] SOFT13 662 // 663 // Software defined interrupt 664 // ENUMs: 665 // ON The bit is 1 666 // OFF The bit is 0 667 #define LRFDPBE_IRQ_SOFT13 0x00002000U 668 #define LRFDPBE_IRQ_SOFT13_M 0x00002000U 669 #define LRFDPBE_IRQ_SOFT13_S 13U 670 #define LRFDPBE_IRQ_SOFT13_ON 0x00002000U 671 #define LRFDPBE_IRQ_SOFT13_OFF 0x00000000U 672 673 // Field: [12] SOFT12 674 // 675 // Software defined interrupt 676 // ENUMs: 677 // ON The bit is 1 678 // OFF The bit is 0 679 #define LRFDPBE_IRQ_SOFT12 0x00001000U 680 #define LRFDPBE_IRQ_SOFT12_M 0x00001000U 681 #define LRFDPBE_IRQ_SOFT12_S 12U 682 #define LRFDPBE_IRQ_SOFT12_ON 0x00001000U 683 #define LRFDPBE_IRQ_SOFT12_OFF 0x00000000U 684 685 // Field: [11] SOFT11 686 // 687 // Software defined interrupt 688 // ENUMs: 689 // ON The bit is 1 690 // OFF The bit is 0 691 #define LRFDPBE_IRQ_SOFT11 0x00000800U 692 #define LRFDPBE_IRQ_SOFT11_M 0x00000800U 693 #define LRFDPBE_IRQ_SOFT11_S 11U 694 #define LRFDPBE_IRQ_SOFT11_ON 0x00000800U 695 #define LRFDPBE_IRQ_SOFT11_OFF 0x00000000U 696 697 // Field: [10] SOFT10 698 // 699 // Software defined interrupt 700 // ENUMs: 701 // ON The bit is 1 702 // OFF The bit is 0 703 #define LRFDPBE_IRQ_SOFT10 0x00000400U 704 #define LRFDPBE_IRQ_SOFT10_M 0x00000400U 705 #define LRFDPBE_IRQ_SOFT10_S 10U 706 #define LRFDPBE_IRQ_SOFT10_ON 0x00000400U 707 #define LRFDPBE_IRQ_SOFT10_OFF 0x00000000U 708 709 // Field: [9] SOFT9 710 // 711 // Software defined interrupt 712 // ENUMs: 713 // ON The bit is 1 714 // OFF The bit is 0 715 #define LRFDPBE_IRQ_SOFT9 0x00000200U 716 #define LRFDPBE_IRQ_SOFT9_M 0x00000200U 717 #define LRFDPBE_IRQ_SOFT9_S 9U 718 #define LRFDPBE_IRQ_SOFT9_ON 0x00000200U 719 #define LRFDPBE_IRQ_SOFT9_OFF 0x00000000U 720 721 // Field: [8] SOFT8 722 // 723 // Software defined interrupt 724 // ENUMs: 725 // ON The bit is 1 726 // OFF The bit is 0 727 #define LRFDPBE_IRQ_SOFT8 0x00000100U 728 #define LRFDPBE_IRQ_SOFT8_M 0x00000100U 729 #define LRFDPBE_IRQ_SOFT8_S 8U 730 #define LRFDPBE_IRQ_SOFT8_ON 0x00000100U 731 #define LRFDPBE_IRQ_SOFT8_OFF 0x00000000U 732 733 // Field: [7] SOFT7 734 // 735 // Software defined interrupt 736 // ENUMs: 737 // ON The bit is 1 738 // OFF The bit is 0 739 #define LRFDPBE_IRQ_SOFT7 0x00000080U 740 #define LRFDPBE_IRQ_SOFT7_M 0x00000080U 741 #define LRFDPBE_IRQ_SOFT7_S 7U 742 #define LRFDPBE_IRQ_SOFT7_ON 0x00000080U 743 #define LRFDPBE_IRQ_SOFT7_OFF 0x00000000U 744 745 // Field: [6] SOFT6 746 // 747 // Software defined interrupt 748 // ENUMs: 749 // ON The bit is 1 750 // OFF The bit is 0 751 #define LRFDPBE_IRQ_SOFT6 0x00000040U 752 #define LRFDPBE_IRQ_SOFT6_M 0x00000040U 753 #define LRFDPBE_IRQ_SOFT6_S 6U 754 #define LRFDPBE_IRQ_SOFT6_ON 0x00000040U 755 #define LRFDPBE_IRQ_SOFT6_OFF 0x00000000U 756 757 // Field: [5] SOFT5 758 // 759 // Software defined interrupt 760 // ENUMs: 761 // ON The bit is 1 762 // OFF The bit is 0 763 #define LRFDPBE_IRQ_SOFT5 0x00000020U 764 #define LRFDPBE_IRQ_SOFT5_M 0x00000020U 765 #define LRFDPBE_IRQ_SOFT5_S 5U 766 #define LRFDPBE_IRQ_SOFT5_ON 0x00000020U 767 #define LRFDPBE_IRQ_SOFT5_OFF 0x00000000U 768 769 // Field: [4] SOFT4 770 // 771 // Software defined interrupt 772 // ENUMs: 773 // ON The bit is 1 774 // OFF The bit is 0 775 #define LRFDPBE_IRQ_SOFT4 0x00000010U 776 #define LRFDPBE_IRQ_SOFT4_M 0x00000010U 777 #define LRFDPBE_IRQ_SOFT4_S 4U 778 #define LRFDPBE_IRQ_SOFT4_ON 0x00000010U 779 #define LRFDPBE_IRQ_SOFT4_OFF 0x00000000U 780 781 // Field: [3] SOFT3 782 // 783 // Software defined interrupt 784 // ENUMs: 785 // ON The bit is 1 786 // OFF The bit is 0 787 #define LRFDPBE_IRQ_SOFT3 0x00000008U 788 #define LRFDPBE_IRQ_SOFT3_M 0x00000008U 789 #define LRFDPBE_IRQ_SOFT3_S 3U 790 #define LRFDPBE_IRQ_SOFT3_ON 0x00000008U 791 #define LRFDPBE_IRQ_SOFT3_OFF 0x00000000U 792 793 // Field: [2] SOFT2 794 // 795 // Software defined interrupt 796 // ENUMs: 797 // ON The bit is 1 798 // OFF The bit is 0 799 #define LRFDPBE_IRQ_SOFT2 0x00000004U 800 #define LRFDPBE_IRQ_SOFT2_M 0x00000004U 801 #define LRFDPBE_IRQ_SOFT2_S 2U 802 #define LRFDPBE_IRQ_SOFT2_ON 0x00000004U 803 #define LRFDPBE_IRQ_SOFT2_OFF 0x00000000U 804 805 // Field: [1] SOFT1 806 // 807 // Software defined interrupt 808 // ENUMs: 809 // ON The bit is 1 810 // OFF The bit is 0 811 #define LRFDPBE_IRQ_SOFT1 0x00000002U 812 #define LRFDPBE_IRQ_SOFT1_M 0x00000002U 813 #define LRFDPBE_IRQ_SOFT1_S 1U 814 #define LRFDPBE_IRQ_SOFT1_ON 0x00000002U 815 #define LRFDPBE_IRQ_SOFT1_OFF 0x00000000U 816 817 // Field: [0] SOFT0 818 // 819 // Software defined interrupt 820 // ENUMs: 821 // ON The bit is 1 822 // OFF The bit is 0 823 #define LRFDPBE_IRQ_SOFT0 0x00000001U 824 #define LRFDPBE_IRQ_SOFT0_M 0x00000001U 825 #define LRFDPBE_IRQ_SOFT0_S 0U 826 #define LRFDPBE_IRQ_SOFT0_ON 0x00000001U 827 #define LRFDPBE_IRQ_SOFT0_OFF 0x00000000U 828 829 //***************************************************************************** 830 // 831 // Register: LRFDPBE_O_EVT0 832 // 833 //***************************************************************************** 834 // Field: [15] MDMFAEMPTY 835 // 836 // Modem fifo is emptied below the empty threshold 837 // ENUMs: 838 // ONE The bit is 1 839 // ZERO The bit is 0 840 #define LRFDPBE_EVT0_MDMFAEMPTY 0x00008000U 841 #define LRFDPBE_EVT0_MDMFAEMPTY_M 0x00008000U 842 #define LRFDPBE_EVT0_MDMFAEMPTY_S 15U 843 #define LRFDPBE_EVT0_MDMFAEMPTY_ONE 0x00008000U 844 #define LRFDPBE_EVT0_MDMFAEMPTY_ZERO 0x00000000U 845 846 // Field: [14] S2RSTOP 847 // 848 // S2R has written to the STOP_ADDRESS location 849 // ENUMs: 850 // ONE The bit is 1 851 // ZERO The bit is 0 852 #define LRFDPBE_EVT0_S2RSTOP 0x00004000U 853 #define LRFDPBE_EVT0_S2RSTOP_M 0x00004000U 854 #define LRFDPBE_EVT0_S2RSTOP_S 14U 855 #define LRFDPBE_EVT0_S2RSTOP_ONE 0x00004000U 856 #define LRFDPBE_EVT0_S2RSTOP_ZERO 0x00000000U 857 858 // Field: [13] FIFOERR 859 // 860 // Error event from fifo 861 // ENUMs: 862 // ONE The bit is 1 863 // ZERO The bit is 0 864 #define LRFDPBE_EVT0_FIFOERR 0x00002000U 865 #define LRFDPBE_EVT0_FIFOERR_M 0x00002000U 866 #define LRFDPBE_EVT0_FIFOERR_S 13U 867 #define LRFDPBE_EVT0_FIFOERR_ONE 0x00002000U 868 #define LRFDPBE_EVT0_FIFOERR_ZERO 0x00000000U 869 870 // Field: [12] MDMFAFULL 871 // 872 // Modem fifo is filled above the threshold 873 // ENUMs: 874 // ONE The bit is 1 875 // ZERO The bit is 0 876 #define LRFDPBE_EVT0_MDMFAFULL 0x00001000U 877 #define LRFDPBE_EVT0_MDMFAFULL_M 0x00001000U 878 #define LRFDPBE_EVT0_MDMFAFULL_S 12U 879 #define LRFDPBE_EVT0_MDMFAFULL_ONE 0x00001000U 880 #define LRFDPBE_EVT0_MDMFAFULL_ZERO 0x00000000U 881 882 // Field: [11] SYSTCMP2 883 // 884 // Systimer compare event 885 // ENUMs: 886 // ONE The bit is 1 887 // ZERO The bit is 0 888 #define LRFDPBE_EVT0_SYSTCMP2 0x00000800U 889 #define LRFDPBE_EVT0_SYSTCMP2_M 0x00000800U 890 #define LRFDPBE_EVT0_SYSTCMP2_S 11U 891 #define LRFDPBE_EVT0_SYSTCMP2_ONE 0x00000800U 892 #define LRFDPBE_EVT0_SYSTCMP2_ZERO 0x00000000U 893 894 // Field: [10] SYSTCMP1 895 // 896 // Systimer compare event 897 // ENUMs: 898 // ONE The bit is 1 899 // ZERO The bit is 0 900 #define LRFDPBE_EVT0_SYSTCMP1 0x00000400U 901 #define LRFDPBE_EVT0_SYSTCMP1_M 0x00000400U 902 #define LRFDPBE_EVT0_SYSTCMP1_S 10U 903 #define LRFDPBE_EVT0_SYSTCMP1_ONE 0x00000400U 904 #define LRFDPBE_EVT0_SYSTCMP1_ZERO 0x00000000U 905 906 // Field: [9] SYSTCMP0 907 // 908 // Systimer compare event 909 // ENUMs: 910 // ONE The bit is 1 911 // ZERO The bit is 0 912 #define LRFDPBE_EVT0_SYSTCMP0 0x00000200U 913 #define LRFDPBE_EVT0_SYSTCMP0_M 0x00000200U 914 #define LRFDPBE_EVT0_SYSTCMP0_S 9U 915 #define LRFDPBE_EVT0_SYSTCMP0_ONE 0x00000200U 916 #define LRFDPBE_EVT0_SYSTCMP0_ZERO 0x00000000U 917 918 // Field: [8] MDMMSGBOX 919 // 920 // New command status from MCE received in MDMMSGBOX register. 921 // ENUMs: 922 // ONE The bit is 1 923 // ZERO The bit is 0 924 #define LRFDPBE_EVT0_MDMMSGBOX 0x00000100U 925 #define LRFDPBE_EVT0_MDMMSGBOX_M 0x00000100U 926 #define LRFDPBE_EVT0_MDMMSGBOX_S 8U 927 #define LRFDPBE_EVT0_MDMMSGBOX_ONE 0x00000100U 928 #define LRFDPBE_EVT0_MDMMSGBOX_ZERO 0x00000000U 929 930 // Field: [7] RFEMSGBOX 931 // 932 // New command status from RFE received in RFEMSGBOX register. 933 // ENUMs: 934 // ONE The bit is 1 935 // ZERO The bit is 0 936 #define LRFDPBE_EVT0_RFEMSGBOX 0x00000080U 937 #define LRFDPBE_EVT0_RFEMSGBOX_M 0x00000080U 938 #define LRFDPBE_EVT0_RFEMSGBOX_S 7U 939 #define LRFDPBE_EVT0_RFEMSGBOX_ONE 0x00000080U 940 #define LRFDPBE_EVT0_RFEMSGBOX_ZERO 0x00000000U 941 942 // Field: [6] RFEDAT 943 // 944 // New data from RFE received in RFEDATIN0 register. 945 // ENUMs: 946 // ONE The bit is 1 947 // ZERO The bit is 0 948 #define LRFDPBE_EVT0_RFEDAT 0x00000040U 949 #define LRFDPBE_EVT0_RFEDAT_M 0x00000040U 950 #define LRFDPBE_EVT0_RFEDAT_S 6U 951 #define LRFDPBE_EVT0_RFEDAT_ONE 0x00000040U 952 #define LRFDPBE_EVT0_RFEDAT_ZERO 0x00000000U 953 954 // Field: [5] RFECMD 955 // 956 // New command from RFE received in RFECMDIN register. 957 // ENUMs: 958 // ONE The bit is 1 959 // ZERO The bit is 0 960 #define LRFDPBE_EVT0_RFECMD 0x00000020U 961 #define LRFDPBE_EVT0_RFECMD_M 0x00000020U 962 #define LRFDPBE_EVT0_RFECMD_S 5U 963 #define LRFDPBE_EVT0_RFECMD_ONE 0x00000020U 964 #define LRFDPBE_EVT0_RFECMD_ZERO 0x00000000U 965 966 // Field: [4] MDMDAT 967 // 968 // New data from MCE received in MCEDATIN0 register. 969 // ENUMs: 970 // ONE The bit is 1 971 // ZERO The bit is 0 972 #define LRFDPBE_EVT0_MDMDAT 0x00000010U 973 #define LRFDPBE_EVT0_MDMDAT_M 0x00000010U 974 #define LRFDPBE_EVT0_MDMDAT_S 4U 975 #define LRFDPBE_EVT0_MDMDAT_ONE 0x00000010U 976 #define LRFDPBE_EVT0_MDMDAT_ZERO 0x00000000U 977 978 // Field: [3] MDMCMD 979 // 980 // New command from MCE received in MCECMDIN register. 981 // ENUMs: 982 // ONE The bit is 1 983 // ZERO The bit is 0 984 #define LRFDPBE_EVT0_MDMCMD 0x00000008U 985 #define LRFDPBE_EVT0_MDMCMD_M 0x00000008U 986 #define LRFDPBE_EVT0_MDMCMD_S 3U 987 #define LRFDPBE_EVT0_MDMCMD_ONE 0x00000008U 988 #define LRFDPBE_EVT0_MDMCMD_ZERO 0x00000000U 989 990 // Field: [2] TIMER1 991 // 992 // Counter value reached in local timer. 993 // ENUMs: 994 // ONE The bit is 1 995 // ZERO The bit is 0 996 #define LRFDPBE_EVT0_TIMER1 0x00000004U 997 #define LRFDPBE_EVT0_TIMER1_M 0x00000004U 998 #define LRFDPBE_EVT0_TIMER1_S 2U 999 #define LRFDPBE_EVT0_TIMER1_ONE 0x00000004U 1000 #define LRFDPBE_EVT0_TIMER1_ZERO 0x00000000U 1001 1002 // Field: [1] TIMER0 1003 // 1004 // Timer period expired in local timer. 1005 // ENUMs: 1006 // ONE The bit is 1 1007 // ZERO The bit is 0 1008 #define LRFDPBE_EVT0_TIMER0 0x00000002U 1009 #define LRFDPBE_EVT0_TIMER0_M 0x00000002U 1010 #define LRFDPBE_EVT0_TIMER0_S 1U 1011 #define LRFDPBE_EVT0_TIMER0_ONE 0x00000002U 1012 #define LRFDPBE_EVT0_TIMER0_ZERO 0x00000000U 1013 1014 // Field: [0] PBEAPI 1015 // 1016 // New command from CPE has been written in API register. 1017 // ENUMs: 1018 // ONE The bit is 1 1019 // ZERO The bit is 0 1020 #define LRFDPBE_EVT0_PBEAPI 0x00000001U 1021 #define LRFDPBE_EVT0_PBEAPI_M 0x00000001U 1022 #define LRFDPBE_EVT0_PBEAPI_S 0U 1023 #define LRFDPBE_EVT0_PBEAPI_ONE 0x00000001U 1024 #define LRFDPBE_EVT0_PBEAPI_ZERO 0x00000000U 1025 1026 //***************************************************************************** 1027 // 1028 // Register: LRFDPBE_O_EVT1 1029 // 1030 //***************************************************************************** 1031 // Field: [12] TXRDBTHR 1032 // 1033 // The TX FIFO contains TXFRBTHRS or more readable bytes. 1034 // ENUMs: 1035 // MET The TX FIFO contains TXFRBTHRS or more readable 1036 // bytes. 1037 // BELOW The TX FIFO contains less than the threshold 1038 // TXFRBTHRS readable bytes. 1039 #define LRFDPBE_EVT1_TXRDBTHR 0x00001000U 1040 #define LRFDPBE_EVT1_TXRDBTHR_M 0x00001000U 1041 #define LRFDPBE_EVT1_TXRDBTHR_S 12U 1042 #define LRFDPBE_EVT1_TXRDBTHR_MET 0x00001000U 1043 #define LRFDPBE_EVT1_TXRDBTHR_BELOW 0x00000000U 1044 1045 // Field: [11] TXWRBTHR 1046 // 1047 // The TX FIFO contains TXFWBTHRS or more writable bytes. 1048 // ENUMs: 1049 // MET The TX FIFO contains TXFWBTHRS or more writable 1050 // bytes. 1051 // BELOW The TX FIFO contains less than the threshold 1052 // TXFWBTHRS writable bytes. 1053 #define LRFDPBE_EVT1_TXWRBTHR 0x00000800U 1054 #define LRFDPBE_EVT1_TXWRBTHR_M 0x00000800U 1055 #define LRFDPBE_EVT1_TXWRBTHR_S 11U 1056 #define LRFDPBE_EVT1_TXWRBTHR_MET 0x00000800U 1057 #define LRFDPBE_EVT1_TXWRBTHR_BELOW 0x00000000U 1058 1059 // Field: [10] RXRDBTHR 1060 // 1061 // The RX FIFO contains RXFRBTHRS or more readable bytes. 1062 // ENUMs: 1063 // MET The TX FIFO contains TXFRBTHRS or more readable 1064 // bytes. 1065 // BELOW The TX FIFO contains less than the threshold 1066 // TXFRBTHRS readable bytes. 1067 #define LRFDPBE_EVT1_RXRDBTHR 0x00000400U 1068 #define LRFDPBE_EVT1_RXRDBTHR_M 0x00000400U 1069 #define LRFDPBE_EVT1_RXRDBTHR_S 10U 1070 #define LRFDPBE_EVT1_RXRDBTHR_MET 0x00000400U 1071 #define LRFDPBE_EVT1_RXRDBTHR_BELOW 0x00000000U 1072 1073 // Field: [9] RXWRBTHR 1074 // 1075 // The RX FIFO contains RXFWBTHRS or more writable bytes. 1076 // ENUMs: 1077 // MET The RX FIFO contains RXFWBTHRS or more writable 1078 // bytes. 1079 // BELOW The RX FIFO contains less than the threshold 1080 // RXFWBTHRS writable bytes. 1081 #define LRFDPBE_EVT1_RXWRBTHR 0x00000200U 1082 #define LRFDPBE_EVT1_RXWRBTHR_M 0x00000200U 1083 #define LRFDPBE_EVT1_RXWRBTHR_S 9U 1084 #define LRFDPBE_EVT1_RXWRBTHR_MET 0x00000200U 1085 #define LRFDPBE_EVT1_RXWRBTHR_BELOW 0x00000000U 1086 1087 // Field: [8] MDMPROG 1088 // 1089 // Programmable event from modem 1090 // ENUMs: 1091 // ONE The bit is 1 1092 // ZERO The bit is 0 1093 #define LRFDPBE_EVT1_MDMPROG 0x00000100U 1094 #define LRFDPBE_EVT1_MDMPROG_M 0x00000100U 1095 #define LRFDPBE_EVT1_MDMPROG_S 8U 1096 #define LRFDPBE_EVT1_MDMPROG_ONE 0x00000100U 1097 #define LRFDPBE_EVT1_MDMPROG_ZERO 0x00000000U 1098 1099 // Field: [7] PBEGPI7 1100 // 1101 // External input event line GPI7 from IOC. 1102 // ENUMs: 1103 // ONE The bit is 1 1104 // ZERO The bit is 0 1105 #define LRFDPBE_EVT1_PBEGPI7 0x00000080U 1106 #define LRFDPBE_EVT1_PBEGPI7_M 0x00000080U 1107 #define LRFDPBE_EVT1_PBEGPI7_S 7U 1108 #define LRFDPBE_EVT1_PBEGPI7_ONE 0x00000080U 1109 #define LRFDPBE_EVT1_PBEGPI7_ZERO 0x00000000U 1110 1111 // Field: [6] PBEGPI6 1112 // 1113 // External input event line GPI6 from IOC. 1114 // ENUMs: 1115 // ONE The bit is 1 1116 // ZERO The bit is 0 1117 #define LRFDPBE_EVT1_PBEGPI6 0x00000040U 1118 #define LRFDPBE_EVT1_PBEGPI6_M 0x00000040U 1119 #define LRFDPBE_EVT1_PBEGPI6_S 6U 1120 #define LRFDPBE_EVT1_PBEGPI6_ONE 0x00000040U 1121 #define LRFDPBE_EVT1_PBEGPI6_ZERO 0x00000000U 1122 1123 // Field: [5] PBEGPI5 1124 // 1125 // External input event line GPI5 from IOC. 1126 // ENUMs: 1127 // ONE The bit is 1 1128 // ZERO The bit is 0 1129 #define LRFDPBE_EVT1_PBEGPI5 0x00000020U 1130 #define LRFDPBE_EVT1_PBEGPI5_M 0x00000020U 1131 #define LRFDPBE_EVT1_PBEGPI5_S 5U 1132 #define LRFDPBE_EVT1_PBEGPI5_ONE 0x00000020U 1133 #define LRFDPBE_EVT1_PBEGPI5_ZERO 0x00000000U 1134 1135 // Field: [4] PBEGPI4 1136 // 1137 // External input event line GPI4 from IOC. 1138 // ENUMs: 1139 // ONE The bit is 1 1140 // ZERO The bit is 0 1141 #define LRFDPBE_EVT1_PBEGPI4 0x00000010U 1142 #define LRFDPBE_EVT1_PBEGPI4_M 0x00000010U 1143 #define LRFDPBE_EVT1_PBEGPI4_S 4U 1144 #define LRFDPBE_EVT1_PBEGPI4_ONE 0x00000010U 1145 #define LRFDPBE_EVT1_PBEGPI4_ZERO 0x00000000U 1146 1147 // Field: [3] PBEGPI3 1148 // 1149 // External input event line GPI3 from IOC. 1150 // ENUMs: 1151 // ONE The bit is 1 1152 // ZERO The bit is 0 1153 #define LRFDPBE_EVT1_PBEGPI3 0x00000008U 1154 #define LRFDPBE_EVT1_PBEGPI3_M 0x00000008U 1155 #define LRFDPBE_EVT1_PBEGPI3_S 3U 1156 #define LRFDPBE_EVT1_PBEGPI3_ONE 0x00000008U 1157 #define LRFDPBE_EVT1_PBEGPI3_ZERO 0x00000000U 1158 1159 // Field: [2] PBEGPI2 1160 // 1161 // External input event line GPI2 from IOC. 1162 // ENUMs: 1163 // ONE The bit is 1 1164 // ZERO The bit is 0 1165 #define LRFDPBE_EVT1_PBEGPI2 0x00000004U 1166 #define LRFDPBE_EVT1_PBEGPI2_M 0x00000004U 1167 #define LRFDPBE_EVT1_PBEGPI2_S 2U 1168 #define LRFDPBE_EVT1_PBEGPI2_ONE 0x00000004U 1169 #define LRFDPBE_EVT1_PBEGPI2_ZERO 0x00000000U 1170 1171 // Field: [1] PBEGPI1 1172 // 1173 // External input event line GPI1 from IOC. 1174 // ENUMs: 1175 // ONE The bit is 1 1176 // ZERO The bit is 0 1177 #define LRFDPBE_EVT1_PBEGPI1 0x00000002U 1178 #define LRFDPBE_EVT1_PBEGPI1_M 0x00000002U 1179 #define LRFDPBE_EVT1_PBEGPI1_S 1U 1180 #define LRFDPBE_EVT1_PBEGPI1_ONE 0x00000002U 1181 #define LRFDPBE_EVT1_PBEGPI1_ZERO 0x00000000U 1182 1183 // Field: [0] PBEGPI0 1184 // 1185 // External input event line GPI0 from IOC. 1186 // ENUMs: 1187 // ONE The bit is 1 1188 // ZERO The bit is 0 1189 #define LRFDPBE_EVT1_PBEGPI0 0x00000001U 1190 #define LRFDPBE_EVT1_PBEGPI0_M 0x00000001U 1191 #define LRFDPBE_EVT1_PBEGPI0_S 0U 1192 #define LRFDPBE_EVT1_PBEGPI0_ONE 0x00000001U 1193 #define LRFDPBE_EVT1_PBEGPI0_ZERO 0x00000000U 1194 1195 //***************************************************************************** 1196 // 1197 // Register: LRFDPBE_O_EVTMSK0 1198 // 1199 //***************************************************************************** 1200 // Field: [15] MDMFAEMPTY 1201 // 1202 // Enable mask for event EVT0.MDMFAEMPTY 1203 // ENUMs: 1204 // EN The bit is 1 1205 // DIS The bit is 0 1206 #define LRFDPBE_EVTMSK0_MDMFAEMPTY 0x00008000U 1207 #define LRFDPBE_EVTMSK0_MDMFAEMPTY_M 0x00008000U 1208 #define LRFDPBE_EVTMSK0_MDMFAEMPTY_S 15U 1209 #define LRFDPBE_EVTMSK0_MDMFAEMPTY_EN 0x00008000U 1210 #define LRFDPBE_EVTMSK0_MDMFAEMPTY_DIS 0x00000000U 1211 1212 // Field: [14] S2RSTOP 1213 // 1214 // Enable mask for event EVT0.S2RSTOP 1215 // ENUMs: 1216 // EN The bit is 1 1217 // DIS The bit is 0 1218 #define LRFDPBE_EVTMSK0_S2RSTOP 0x00004000U 1219 #define LRFDPBE_EVTMSK0_S2RSTOP_M 0x00004000U 1220 #define LRFDPBE_EVTMSK0_S2RSTOP_S 14U 1221 #define LRFDPBE_EVTMSK0_S2RSTOP_EN 0x00004000U 1222 #define LRFDPBE_EVTMSK0_S2RSTOP_DIS 0x00000000U 1223 1224 // Field: [13] FIFOERR 1225 // 1226 // Enable mask for event EVT0.FIFOERR 1227 // ENUMs: 1228 // EN The bit is 1 1229 // DIS The bit is 0 1230 #define LRFDPBE_EVTMSK0_FIFOERR 0x00002000U 1231 #define LRFDPBE_EVTMSK0_FIFOERR_M 0x00002000U 1232 #define LRFDPBE_EVTMSK0_FIFOERR_S 13U 1233 #define LRFDPBE_EVTMSK0_FIFOERR_EN 0x00002000U 1234 #define LRFDPBE_EVTMSK0_FIFOERR_DIS 0x00000000U 1235 1236 // Field: [12] MDMFAFULL 1237 // 1238 // Enable mask for event EVT0.MDMFAFULL 1239 // ENUMs: 1240 // EN The bit is 1 1241 // DIS The bit is 0 1242 #define LRFDPBE_EVTMSK0_MDMFAFULL 0x00001000U 1243 #define LRFDPBE_EVTMSK0_MDMFAFULL_M 0x00001000U 1244 #define LRFDPBE_EVTMSK0_MDMFAFULL_S 12U 1245 #define LRFDPBE_EVTMSK0_MDMFAFULL_EN 0x00001000U 1246 #define LRFDPBE_EVTMSK0_MDMFAFULL_DIS 0x00000000U 1247 1248 // Field: [11] SYSTCMP2 1249 // 1250 // Enable mask for event EVT0.SYSTCMP2 1251 // ENUMs: 1252 // EN The bit is 1 1253 // DIS The bit is 0 1254 #define LRFDPBE_EVTMSK0_SYSTCMP2 0x00000800U 1255 #define LRFDPBE_EVTMSK0_SYSTCMP2_M 0x00000800U 1256 #define LRFDPBE_EVTMSK0_SYSTCMP2_S 11U 1257 #define LRFDPBE_EVTMSK0_SYSTCMP2_EN 0x00000800U 1258 #define LRFDPBE_EVTMSK0_SYSTCMP2_DIS 0x00000000U 1259 1260 // Field: [10] SYSTCMP1 1261 // 1262 // Enable mask for event EVT0.SYSTCMP1 1263 // ENUMs: 1264 // EN The bit is 1 1265 // DIS The bit is 0 1266 #define LRFDPBE_EVTMSK0_SYSTCMP1 0x00000400U 1267 #define LRFDPBE_EVTMSK0_SYSTCMP1_M 0x00000400U 1268 #define LRFDPBE_EVTMSK0_SYSTCMP1_S 10U 1269 #define LRFDPBE_EVTMSK0_SYSTCMP1_EN 0x00000400U 1270 #define LRFDPBE_EVTMSK0_SYSTCMP1_DIS 0x00000000U 1271 1272 // Field: [9] SYSTCMP0 1273 // 1274 // Enable mask for event EVT0.SYSTCMP0 1275 // ENUMs: 1276 // EN The bit is 1 1277 // DIS The bit is 0 1278 #define LRFDPBE_EVTMSK0_SYSTCMP0 0x00000200U 1279 #define LRFDPBE_EVTMSK0_SYSTCMP0_M 0x00000200U 1280 #define LRFDPBE_EVTMSK0_SYSTCMP0_S 9U 1281 #define LRFDPBE_EVTMSK0_SYSTCMP0_EN 0x00000200U 1282 #define LRFDPBE_EVTMSK0_SYSTCMP0_DIS 0x00000000U 1283 1284 // Field: [8] MDMMSGBOX 1285 // 1286 // Enable mask for event EVT0.MDMMSGBOX 1287 // ENUMs: 1288 // EN The bit is 1 1289 // DIS The bit is 0 1290 #define LRFDPBE_EVTMSK0_MDMMSGBOX 0x00000100U 1291 #define LRFDPBE_EVTMSK0_MDMMSGBOX_M 0x00000100U 1292 #define LRFDPBE_EVTMSK0_MDMMSGBOX_S 8U 1293 #define LRFDPBE_EVTMSK0_MDMMSGBOX_EN 0x00000100U 1294 #define LRFDPBE_EVTMSK0_MDMMSGBOX_DIS 0x00000000U 1295 1296 // Field: [7] RFEMSGBOX 1297 // 1298 // Enable mask for event EVT0.RFEMSGBOX 1299 // ENUMs: 1300 // EN The bit is 1 1301 // DIS The bit is 0 1302 #define LRFDPBE_EVTMSK0_RFEMSGBOX 0x00000080U 1303 #define LRFDPBE_EVTMSK0_RFEMSGBOX_M 0x00000080U 1304 #define LRFDPBE_EVTMSK0_RFEMSGBOX_S 7U 1305 #define LRFDPBE_EVTMSK0_RFEMSGBOX_EN 0x00000080U 1306 #define LRFDPBE_EVTMSK0_RFEMSGBOX_DIS 0x00000000U 1307 1308 // Field: [6] RFEDAT 1309 // 1310 // Enable mask for event EVT0.RFEDAT 1311 // ENUMs: 1312 // EN The bit is 1 1313 // DIS The bit is 0 1314 #define LRFDPBE_EVTMSK0_RFEDAT 0x00000040U 1315 #define LRFDPBE_EVTMSK0_RFEDAT_M 0x00000040U 1316 #define LRFDPBE_EVTMSK0_RFEDAT_S 6U 1317 #define LRFDPBE_EVTMSK0_RFEDAT_EN 0x00000040U 1318 #define LRFDPBE_EVTMSK0_RFEDAT_DIS 0x00000000U 1319 1320 // Field: [5] RFECMD 1321 // 1322 // Enable mask for event EVT0.RFECMD 1323 // ENUMs: 1324 // EN The bit is 1 1325 // DIS The bit is 0 1326 #define LRFDPBE_EVTMSK0_RFECMD 0x00000020U 1327 #define LRFDPBE_EVTMSK0_RFECMD_M 0x00000020U 1328 #define LRFDPBE_EVTMSK0_RFECMD_S 5U 1329 #define LRFDPBE_EVTMSK0_RFECMD_EN 0x00000020U 1330 #define LRFDPBE_EVTMSK0_RFECMD_DIS 0x00000000U 1331 1332 // Field: [4] MDMDAT 1333 // 1334 // Enable mask for event EVT0.MDMDAT 1335 // ENUMs: 1336 // EN The bit is 1 1337 // DIS The bit is 0 1338 #define LRFDPBE_EVTMSK0_MDMDAT 0x00000010U 1339 #define LRFDPBE_EVTMSK0_MDMDAT_M 0x00000010U 1340 #define LRFDPBE_EVTMSK0_MDMDAT_S 4U 1341 #define LRFDPBE_EVTMSK0_MDMDAT_EN 0x00000010U 1342 #define LRFDPBE_EVTMSK0_MDMDAT_DIS 0x00000000U 1343 1344 // Field: [3] MDMCMD 1345 // 1346 // Enable mask for event EVT0.MDMCMD 1347 // ENUMs: 1348 // EN The bit is 1 1349 // DIS The bit is 0 1350 #define LRFDPBE_EVTMSK0_MDMCMD 0x00000008U 1351 #define LRFDPBE_EVTMSK0_MDMCMD_M 0x00000008U 1352 #define LRFDPBE_EVTMSK0_MDMCMD_S 3U 1353 #define LRFDPBE_EVTMSK0_MDMCMD_EN 0x00000008U 1354 #define LRFDPBE_EVTMSK0_MDMCMD_DIS 0x00000000U 1355 1356 // Field: [2] TIMER1 1357 // 1358 // Enable mask for event EVT0.TIMER1 1359 // ENUMs: 1360 // EN The bit is 1 1361 // DIS The bit is 0 1362 #define LRFDPBE_EVTMSK0_TIMER1 0x00000004U 1363 #define LRFDPBE_EVTMSK0_TIMER1_M 0x00000004U 1364 #define LRFDPBE_EVTMSK0_TIMER1_S 2U 1365 #define LRFDPBE_EVTMSK0_TIMER1_EN 0x00000004U 1366 #define LRFDPBE_EVTMSK0_TIMER1_DIS 0x00000000U 1367 1368 // Field: [1] TIMER0 1369 // 1370 // Enable mask for event EVT0.TIMER0 1371 // ENUMs: 1372 // EN The bit is 1 1373 // DIS The bit is 0 1374 #define LRFDPBE_EVTMSK0_TIMER0 0x00000002U 1375 #define LRFDPBE_EVTMSK0_TIMER0_M 0x00000002U 1376 #define LRFDPBE_EVTMSK0_TIMER0_S 1U 1377 #define LRFDPBE_EVTMSK0_TIMER0_EN 0x00000002U 1378 #define LRFDPBE_EVTMSK0_TIMER0_DIS 0x00000000U 1379 1380 // Field: [0] PBEAPI 1381 // 1382 // Enable mask for event EVT0.PBEAPI 1383 // ENUMs: 1384 // EN The bit is 1 1385 // DIS The bit is 0 1386 #define LRFDPBE_EVTMSK0_PBEAPI 0x00000001U 1387 #define LRFDPBE_EVTMSK0_PBEAPI_M 0x00000001U 1388 #define LRFDPBE_EVTMSK0_PBEAPI_S 0U 1389 #define LRFDPBE_EVTMSK0_PBEAPI_EN 0x00000001U 1390 #define LRFDPBE_EVTMSK0_PBEAPI_DIS 0x00000000U 1391 1392 //***************************************************************************** 1393 // 1394 // Register: LRFDPBE_O_EVTMSK1 1395 // 1396 //***************************************************************************** 1397 // Field: [12] TXRDBTHR 1398 // 1399 // Enable mask for event EVT0.TXRDBTHR 1400 // ENUMs: 1401 // EN The TX FIFO contains TXFRBTHRS or more readable 1402 // bytes. 1403 // DIS The TX FIFO contains less than the threshold 1404 // TXFRBTHRS readable bytes. 1405 #define LRFDPBE_EVTMSK1_TXRDBTHR 0x00001000U 1406 #define LRFDPBE_EVTMSK1_TXRDBTHR_M 0x00001000U 1407 #define LRFDPBE_EVTMSK1_TXRDBTHR_S 12U 1408 #define LRFDPBE_EVTMSK1_TXRDBTHR_EN 0x00001000U 1409 #define LRFDPBE_EVTMSK1_TXRDBTHR_DIS 0x00000000U 1410 1411 // Field: [11] TXWRBTHR 1412 // 1413 // Enable mask for event EVT0.TXWRBTHR 1414 // ENUMs: 1415 // EN The TX FIFO contains TXFWBTHRS or more writable 1416 // bytes. 1417 // DIS The TX FIFO contains less than the threshold 1418 // TXFWBTHRS writable bytes. 1419 #define LRFDPBE_EVTMSK1_TXWRBTHR 0x00000800U 1420 #define LRFDPBE_EVTMSK1_TXWRBTHR_M 0x00000800U 1421 #define LRFDPBE_EVTMSK1_TXWRBTHR_S 11U 1422 #define LRFDPBE_EVTMSK1_TXWRBTHR_EN 0x00000800U 1423 #define LRFDPBE_EVTMSK1_TXWRBTHR_DIS 0x00000000U 1424 1425 // Field: [10] RXRDBTHR 1426 // 1427 // Enable mask for event EVT0.RXRDBTHR 1428 // ENUMs: 1429 // EN The TX FIFO contains TXFWBTHRS or more writable 1430 // bytes. 1431 // DIS The TX FIFO contains less than the threshold 1432 // TXFWBTHRS writable bytes. 1433 #define LRFDPBE_EVTMSK1_RXRDBTHR 0x00000400U 1434 #define LRFDPBE_EVTMSK1_RXRDBTHR_M 0x00000400U 1435 #define LRFDPBE_EVTMSK1_RXRDBTHR_S 10U 1436 #define LRFDPBE_EVTMSK1_RXRDBTHR_EN 0x00000400U 1437 #define LRFDPBE_EVTMSK1_RXRDBTHR_DIS 0x00000000U 1438 1439 // Field: [9] RXWRBTHR 1440 // 1441 // Enable mask for event EVT0.RXWRBTHR 1442 // ENUMs: 1443 // EN The TX FIFO contains TXFWBTHRS or more writable 1444 // bytes. 1445 // DIS The TX FIFO contains less than the threshold 1446 // TXFWBTHRS writable bytes. 1447 #define LRFDPBE_EVTMSK1_RXWRBTHR 0x00000200U 1448 #define LRFDPBE_EVTMSK1_RXWRBTHR_M 0x00000200U 1449 #define LRFDPBE_EVTMSK1_RXWRBTHR_S 9U 1450 #define LRFDPBE_EVTMSK1_RXWRBTHR_EN 0x00000200U 1451 #define LRFDPBE_EVTMSK1_RXWRBTHR_DIS 0x00000000U 1452 1453 // Field: [8] MDMPROG 1454 // 1455 // Enable mask for event EVT0.MDMPROG 1456 // ENUMs: 1457 // EN The bit is 1 1458 // DIS The bit is 0 1459 #define LRFDPBE_EVTMSK1_MDMPROG 0x00000100U 1460 #define LRFDPBE_EVTMSK1_MDMPROG_M 0x00000100U 1461 #define LRFDPBE_EVTMSK1_MDMPROG_S 8U 1462 #define LRFDPBE_EVTMSK1_MDMPROG_EN 0x00000100U 1463 #define LRFDPBE_EVTMSK1_MDMPROG_DIS 0x00000000U 1464 1465 // Field: [7] PBEGPI7 1466 // 1467 // Enable mask for event EVT0.PBEGPI7 1468 // ENUMs: 1469 // EN The bit is 1 1470 // DIS The bit is 0 1471 #define LRFDPBE_EVTMSK1_PBEGPI7 0x00000080U 1472 #define LRFDPBE_EVTMSK1_PBEGPI7_M 0x00000080U 1473 #define LRFDPBE_EVTMSK1_PBEGPI7_S 7U 1474 #define LRFDPBE_EVTMSK1_PBEGPI7_EN 0x00000080U 1475 #define LRFDPBE_EVTMSK1_PBEGPI7_DIS 0x00000000U 1476 1477 // Field: [6] PBEGPI6 1478 // 1479 // Enable mask for event EVT0.PBEGPI6 1480 // ENUMs: 1481 // EN The bit is 1 1482 // DIS The bit is 0 1483 #define LRFDPBE_EVTMSK1_PBEGPI6 0x00000040U 1484 #define LRFDPBE_EVTMSK1_PBEGPI6_M 0x00000040U 1485 #define LRFDPBE_EVTMSK1_PBEGPI6_S 6U 1486 #define LRFDPBE_EVTMSK1_PBEGPI6_EN 0x00000040U 1487 #define LRFDPBE_EVTMSK1_PBEGPI6_DIS 0x00000000U 1488 1489 // Field: [5] PBEGPI5 1490 // 1491 // Enable mask for event EVT0.PBEGPI5 1492 // ENUMs: 1493 // EN The bit is 1 1494 // DIS The bit is 0 1495 #define LRFDPBE_EVTMSK1_PBEGPI5 0x00000020U 1496 #define LRFDPBE_EVTMSK1_PBEGPI5_M 0x00000020U 1497 #define LRFDPBE_EVTMSK1_PBEGPI5_S 5U 1498 #define LRFDPBE_EVTMSK1_PBEGPI5_EN 0x00000020U 1499 #define LRFDPBE_EVTMSK1_PBEGPI5_DIS 0x00000000U 1500 1501 // Field: [4] PBEGPI4 1502 // 1503 // Enable mask for event EVT0.PBEGPI4 1504 // ENUMs: 1505 // EN The bit is 1 1506 // DIS The bit is 0 1507 #define LRFDPBE_EVTMSK1_PBEGPI4 0x00000010U 1508 #define LRFDPBE_EVTMSK1_PBEGPI4_M 0x00000010U 1509 #define LRFDPBE_EVTMSK1_PBEGPI4_S 4U 1510 #define LRFDPBE_EVTMSK1_PBEGPI4_EN 0x00000010U 1511 #define LRFDPBE_EVTMSK1_PBEGPI4_DIS 0x00000000U 1512 1513 // Field: [3] PBEGPI3 1514 // 1515 // Enable mask for event EVT0.PBEGPI3 1516 // ENUMs: 1517 // EN The bit is 1 1518 // DIS The bit is 0 1519 #define LRFDPBE_EVTMSK1_PBEGPI3 0x00000008U 1520 #define LRFDPBE_EVTMSK1_PBEGPI3_M 0x00000008U 1521 #define LRFDPBE_EVTMSK1_PBEGPI3_S 3U 1522 #define LRFDPBE_EVTMSK1_PBEGPI3_EN 0x00000008U 1523 #define LRFDPBE_EVTMSK1_PBEGPI3_DIS 0x00000000U 1524 1525 // Field: [2] PBEGPI2 1526 // 1527 // Enable mask for event EVT0.PBEGPI2 1528 // ENUMs: 1529 // EN The bit is 1 1530 // DIS The bit is 0 1531 #define LRFDPBE_EVTMSK1_PBEGPI2 0x00000004U 1532 #define LRFDPBE_EVTMSK1_PBEGPI2_M 0x00000004U 1533 #define LRFDPBE_EVTMSK1_PBEGPI2_S 2U 1534 #define LRFDPBE_EVTMSK1_PBEGPI2_EN 0x00000004U 1535 #define LRFDPBE_EVTMSK1_PBEGPI2_DIS 0x00000000U 1536 1537 // Field: [1] PBEGPI1 1538 // 1539 // Enable mask for event EVT0.PBEGPI1 1540 // ENUMs: 1541 // EN The bit is 1 1542 // DIS The bit is 0 1543 #define LRFDPBE_EVTMSK1_PBEGPI1 0x00000002U 1544 #define LRFDPBE_EVTMSK1_PBEGPI1_M 0x00000002U 1545 #define LRFDPBE_EVTMSK1_PBEGPI1_S 1U 1546 #define LRFDPBE_EVTMSK1_PBEGPI1_EN 0x00000002U 1547 #define LRFDPBE_EVTMSK1_PBEGPI1_DIS 0x00000000U 1548 1549 // Field: [0] PBEGPI0 1550 // 1551 // Enable mask for event EVT0.PBEGPI0 1552 // ENUMs: 1553 // EN The bit is 1 1554 // DIS The bit is 0 1555 #define LRFDPBE_EVTMSK1_PBEGPI0 0x00000001U 1556 #define LRFDPBE_EVTMSK1_PBEGPI0_M 0x00000001U 1557 #define LRFDPBE_EVTMSK1_PBEGPI0_S 0U 1558 #define LRFDPBE_EVTMSK1_PBEGPI0_EN 0x00000001U 1559 #define LRFDPBE_EVTMSK1_PBEGPI0_DIS 0x00000000U 1560 1561 //***************************************************************************** 1562 // 1563 // Register: LRFDPBE_O_EVTCLR0 1564 // 1565 //***************************************************************************** 1566 // Field: [15] MDMFAEMPTY 1567 // 1568 // Clear event EVT0.MDMFAEMPTY 1569 // ENUMs: 1570 // CLEAR The bit is 1 1571 // RETAIN The bit is 0 1572 #define LRFDPBE_EVTCLR0_MDMFAEMPTY 0x00008000U 1573 #define LRFDPBE_EVTCLR0_MDMFAEMPTY_M 0x00008000U 1574 #define LRFDPBE_EVTCLR0_MDMFAEMPTY_S 15U 1575 #define LRFDPBE_EVTCLR0_MDMFAEMPTY_CLEAR 0x00008000U 1576 #define LRFDPBE_EVTCLR0_MDMFAEMPTY_RETAIN 0x00000000U 1577 1578 // Field: [14] S2RSTOP 1579 // 1580 // Clear event EVT0.S2RSTOP 1581 // ENUMs: 1582 // CLEAR The bit is 1 1583 // RETAIN The bit is 0 1584 #define LRFDPBE_EVTCLR0_S2RSTOP 0x00004000U 1585 #define LRFDPBE_EVTCLR0_S2RSTOP_M 0x00004000U 1586 #define LRFDPBE_EVTCLR0_S2RSTOP_S 14U 1587 #define LRFDPBE_EVTCLR0_S2RSTOP_CLEAR 0x00004000U 1588 #define LRFDPBE_EVTCLR0_S2RSTOP_RETAIN 0x00000000U 1589 1590 // Field: [13] FIFOERR 1591 // 1592 // Clear event EVT0.FIFOERR 1593 // ENUMs: 1594 // CLEAR The bit is 1 1595 // RETAIN The bit is 0 1596 #define LRFDPBE_EVTCLR0_FIFOERR 0x00002000U 1597 #define LRFDPBE_EVTCLR0_FIFOERR_M 0x00002000U 1598 #define LRFDPBE_EVTCLR0_FIFOERR_S 13U 1599 #define LRFDPBE_EVTCLR0_FIFOERR_CLEAR 0x00002000U 1600 #define LRFDPBE_EVTCLR0_FIFOERR_RETAIN 0x00000000U 1601 1602 // Field: [12] MDMFAFULL 1603 // 1604 // Clear event EVT0.MDMFAFULL 1605 // ENUMs: 1606 // CLEAR The bit is 1 1607 // RETAIN The bit is 0 1608 #define LRFDPBE_EVTCLR0_MDMFAFULL 0x00001000U 1609 #define LRFDPBE_EVTCLR0_MDMFAFULL_M 0x00001000U 1610 #define LRFDPBE_EVTCLR0_MDMFAFULL_S 12U 1611 #define LRFDPBE_EVTCLR0_MDMFAFULL_CLEAR 0x00001000U 1612 #define LRFDPBE_EVTCLR0_MDMFAFULL_RETAIN 0x00000000U 1613 1614 // Field: [11] SYSTCMP2 1615 // 1616 // Clear event EVT0.SYSTCMP2 1617 // ENUMs: 1618 // CLEAR The bit is 1 1619 // RETAIN The bit is 0 1620 #define LRFDPBE_EVTCLR0_SYSTCMP2 0x00000800U 1621 #define LRFDPBE_EVTCLR0_SYSTCMP2_M 0x00000800U 1622 #define LRFDPBE_EVTCLR0_SYSTCMP2_S 11U 1623 #define LRFDPBE_EVTCLR0_SYSTCMP2_CLEAR 0x00000800U 1624 #define LRFDPBE_EVTCLR0_SYSTCMP2_RETAIN 0x00000000U 1625 1626 // Field: [10] SYSTCMP1 1627 // 1628 // Clear event EVT0.SYSTCMP1 1629 // ENUMs: 1630 // CLEAR The bit is 1 1631 // RETAIN The bit is 0 1632 #define LRFDPBE_EVTCLR0_SYSTCMP1 0x00000400U 1633 #define LRFDPBE_EVTCLR0_SYSTCMP1_M 0x00000400U 1634 #define LRFDPBE_EVTCLR0_SYSTCMP1_S 10U 1635 #define LRFDPBE_EVTCLR0_SYSTCMP1_CLEAR 0x00000400U 1636 #define LRFDPBE_EVTCLR0_SYSTCMP1_RETAIN 0x00000000U 1637 1638 // Field: [9] SYSTCMP0 1639 // 1640 // Clear event EVT0.SYSTCMP0 1641 // ENUMs: 1642 // CLEAR The bit is 1 1643 // RETAIN The bit is 0 1644 #define LRFDPBE_EVTCLR0_SYSTCMP0 0x00000200U 1645 #define LRFDPBE_EVTCLR0_SYSTCMP0_M 0x00000200U 1646 #define LRFDPBE_EVTCLR0_SYSTCMP0_S 9U 1647 #define LRFDPBE_EVTCLR0_SYSTCMP0_CLEAR 0x00000200U 1648 #define LRFDPBE_EVTCLR0_SYSTCMP0_RETAIN 0x00000000U 1649 1650 // Field: [8] MDMMSGBOX 1651 // 1652 // Clear event EVT0.MDMMSGBOX 1653 // ENUMs: 1654 // CLEAR The bit is 1 1655 // RETAIN The bit is 0 1656 #define LRFDPBE_EVTCLR0_MDMMSGBOX 0x00000100U 1657 #define LRFDPBE_EVTCLR0_MDMMSGBOX_M 0x00000100U 1658 #define LRFDPBE_EVTCLR0_MDMMSGBOX_S 8U 1659 #define LRFDPBE_EVTCLR0_MDMMSGBOX_CLEAR 0x00000100U 1660 #define LRFDPBE_EVTCLR0_MDMMSGBOX_RETAIN 0x00000000U 1661 1662 // Field: [7] RFEMSGBOX 1663 // 1664 // Clear event EVT0.RFEMSGBOX 1665 // ENUMs: 1666 // CLEAR The bit is 1 1667 // RETAIN The bit is 0 1668 #define LRFDPBE_EVTCLR0_RFEMSGBOX 0x00000080U 1669 #define LRFDPBE_EVTCLR0_RFEMSGBOX_M 0x00000080U 1670 #define LRFDPBE_EVTCLR0_RFEMSGBOX_S 7U 1671 #define LRFDPBE_EVTCLR0_RFEMSGBOX_CLEAR 0x00000080U 1672 #define LRFDPBE_EVTCLR0_RFEMSGBOX_RETAIN 0x00000000U 1673 1674 // Field: [6] RFEDAT 1675 // 1676 // Clear event EVT0.RFEDAT 1677 // ENUMs: 1678 // CLEAR The bit is 1 1679 // RETAIN The bit is 0 1680 #define LRFDPBE_EVTCLR0_RFEDAT 0x00000040U 1681 #define LRFDPBE_EVTCLR0_RFEDAT_M 0x00000040U 1682 #define LRFDPBE_EVTCLR0_RFEDAT_S 6U 1683 #define LRFDPBE_EVTCLR0_RFEDAT_CLEAR 0x00000040U 1684 #define LRFDPBE_EVTCLR0_RFEDAT_RETAIN 0x00000000U 1685 1686 // Field: [5] RFECMD 1687 // 1688 // Clear event EVT0.RFECMD 1689 // ENUMs: 1690 // CLEAR The bit is 1 1691 // RETAIN The bit is 0 1692 #define LRFDPBE_EVTCLR0_RFECMD 0x00000020U 1693 #define LRFDPBE_EVTCLR0_RFECMD_M 0x00000020U 1694 #define LRFDPBE_EVTCLR0_RFECMD_S 5U 1695 #define LRFDPBE_EVTCLR0_RFECMD_CLEAR 0x00000020U 1696 #define LRFDPBE_EVTCLR0_RFECMD_RETAIN 0x00000000U 1697 1698 // Field: [4] MDMDAT 1699 // 1700 // Clear event EVT0.MDMDAT 1701 // ENUMs: 1702 // CLEAR The bit is 1 1703 // RETAIN The bit is 0 1704 #define LRFDPBE_EVTCLR0_MDMDAT 0x00000010U 1705 #define LRFDPBE_EVTCLR0_MDMDAT_M 0x00000010U 1706 #define LRFDPBE_EVTCLR0_MDMDAT_S 4U 1707 #define LRFDPBE_EVTCLR0_MDMDAT_CLEAR 0x00000010U 1708 #define LRFDPBE_EVTCLR0_MDMDAT_RETAIN 0x00000000U 1709 1710 // Field: [3] MDMCMD 1711 // 1712 // Clear event EVT0.MDMCMD 1713 // ENUMs: 1714 // CLEAR The bit is 1 1715 // RETAIN The bit is 0 1716 #define LRFDPBE_EVTCLR0_MDMCMD 0x00000008U 1717 #define LRFDPBE_EVTCLR0_MDMCMD_M 0x00000008U 1718 #define LRFDPBE_EVTCLR0_MDMCMD_S 3U 1719 #define LRFDPBE_EVTCLR0_MDMCMD_CLEAR 0x00000008U 1720 #define LRFDPBE_EVTCLR0_MDMCMD_RETAIN 0x00000000U 1721 1722 // Field: [2] TIMER1 1723 // 1724 // Clear event EVT0.TIMER1 1725 // ENUMs: 1726 // CLEAR The bit is 1 1727 // RETAIN The bit is 0 1728 #define LRFDPBE_EVTCLR0_TIMER1 0x00000004U 1729 #define LRFDPBE_EVTCLR0_TIMER1_M 0x00000004U 1730 #define LRFDPBE_EVTCLR0_TIMER1_S 2U 1731 #define LRFDPBE_EVTCLR0_TIMER1_CLEAR 0x00000004U 1732 #define LRFDPBE_EVTCLR0_TIMER1_RETAIN 0x00000000U 1733 1734 // Field: [1] TIMER0 1735 // 1736 // Clear event EVT0.TIMER0 1737 // ENUMs: 1738 // CLEAR The bit is 1 1739 // RETAIN The bit is 0 1740 #define LRFDPBE_EVTCLR0_TIMER0 0x00000002U 1741 #define LRFDPBE_EVTCLR0_TIMER0_M 0x00000002U 1742 #define LRFDPBE_EVTCLR0_TIMER0_S 1U 1743 #define LRFDPBE_EVTCLR0_TIMER0_CLEAR 0x00000002U 1744 #define LRFDPBE_EVTCLR0_TIMER0_RETAIN 0x00000000U 1745 1746 // Field: [0] PBEAPI 1747 // 1748 // Clear event EVT0.PBEAPI 1749 // ENUMs: 1750 // CLEAR The bit is 1 1751 // RETAIN The bit is 0 1752 #define LRFDPBE_EVTCLR0_PBEAPI 0x00000001U 1753 #define LRFDPBE_EVTCLR0_PBEAPI_M 0x00000001U 1754 #define LRFDPBE_EVTCLR0_PBEAPI_S 0U 1755 #define LRFDPBE_EVTCLR0_PBEAPI_CLEAR 0x00000001U 1756 #define LRFDPBE_EVTCLR0_PBEAPI_RETAIN 0x00000000U 1757 1758 //***************************************************************************** 1759 // 1760 // Register: LRFDPBE_O_EVTCLR1 1761 // 1762 //***************************************************************************** 1763 // Field: [12] TXRDBTHR 1764 // 1765 // Clear event EVT0.TXRDBTHR 1766 // ENUMs: 1767 // CLEAR The bit is 1 1768 // RETAIN The bit is 0 1769 #define LRFDPBE_EVTCLR1_TXRDBTHR 0x00001000U 1770 #define LRFDPBE_EVTCLR1_TXRDBTHR_M 0x00001000U 1771 #define LRFDPBE_EVTCLR1_TXRDBTHR_S 12U 1772 #define LRFDPBE_EVTCLR1_TXRDBTHR_CLEAR 0x00001000U 1773 #define LRFDPBE_EVTCLR1_TXRDBTHR_RETAIN 0x00000000U 1774 1775 // Field: [11] TXWRBTHR 1776 // 1777 // Clear event EVT0.TXWRBTHR 1778 // ENUMs: 1779 // CLEAR The bit is 1 1780 // RETAIN The bit is 0 1781 #define LRFDPBE_EVTCLR1_TXWRBTHR 0x00000800U 1782 #define LRFDPBE_EVTCLR1_TXWRBTHR_M 0x00000800U 1783 #define LRFDPBE_EVTCLR1_TXWRBTHR_S 11U 1784 #define LRFDPBE_EVTCLR1_TXWRBTHR_CLEAR 0x00000800U 1785 #define LRFDPBE_EVTCLR1_TXWRBTHR_RETAIN 0x00000000U 1786 1787 // Field: [10] RXRDBTHR 1788 // 1789 // Clear event EVT0.RXRDBTHR 1790 // ENUMs: 1791 // CLEAR The bit is 1 1792 // RETAIN The bit is 0 1793 #define LRFDPBE_EVTCLR1_RXRDBTHR 0x00000400U 1794 #define LRFDPBE_EVTCLR1_RXRDBTHR_M 0x00000400U 1795 #define LRFDPBE_EVTCLR1_RXRDBTHR_S 10U 1796 #define LRFDPBE_EVTCLR1_RXRDBTHR_CLEAR 0x00000400U 1797 #define LRFDPBE_EVTCLR1_RXRDBTHR_RETAIN 0x00000000U 1798 1799 // Field: [9] RXWRBTHR 1800 // 1801 // Clear event EVT0.RXWRBTHR 1802 // ENUMs: 1803 // CLEAR The bit is 1 1804 // RETAIN The bit is 0 1805 #define LRFDPBE_EVTCLR1_RXWRBTHR 0x00000200U 1806 #define LRFDPBE_EVTCLR1_RXWRBTHR_M 0x00000200U 1807 #define LRFDPBE_EVTCLR1_RXWRBTHR_S 9U 1808 #define LRFDPBE_EVTCLR1_RXWRBTHR_CLEAR 0x00000200U 1809 #define LRFDPBE_EVTCLR1_RXWRBTHR_RETAIN 0x00000000U 1810 1811 // Field: [8] MDMPROG 1812 // 1813 // Clear event EVT0.MDMPROG 1814 // ENUMs: 1815 // CLEAR The bit is 1 1816 // RETAIN The bit is 0 1817 #define LRFDPBE_EVTCLR1_MDMPROG 0x00000100U 1818 #define LRFDPBE_EVTCLR1_MDMPROG_M 0x00000100U 1819 #define LRFDPBE_EVTCLR1_MDMPROG_S 8U 1820 #define LRFDPBE_EVTCLR1_MDMPROG_CLEAR 0x00000100U 1821 #define LRFDPBE_EVTCLR1_MDMPROG_RETAIN 0x00000000U 1822 1823 // Field: [7] PBEGPI7 1824 // 1825 // Clear event EVT0.PBEGPI7 1826 // ENUMs: 1827 // CLEAR The bit is 1 1828 // RETAIN The bit is 0 1829 #define LRFDPBE_EVTCLR1_PBEGPI7 0x00000080U 1830 #define LRFDPBE_EVTCLR1_PBEGPI7_M 0x00000080U 1831 #define LRFDPBE_EVTCLR1_PBEGPI7_S 7U 1832 #define LRFDPBE_EVTCLR1_PBEGPI7_CLEAR 0x00000080U 1833 #define LRFDPBE_EVTCLR1_PBEGPI7_RETAIN 0x00000000U 1834 1835 // Field: [6] PBEGPI6 1836 // 1837 // Clear event EVT0.PBEGPI6 1838 // ENUMs: 1839 // CLEAR The bit is 1 1840 // RETAIN The bit is 0 1841 #define LRFDPBE_EVTCLR1_PBEGPI6 0x00000040U 1842 #define LRFDPBE_EVTCLR1_PBEGPI6_M 0x00000040U 1843 #define LRFDPBE_EVTCLR1_PBEGPI6_S 6U 1844 #define LRFDPBE_EVTCLR1_PBEGPI6_CLEAR 0x00000040U 1845 #define LRFDPBE_EVTCLR1_PBEGPI6_RETAIN 0x00000000U 1846 1847 // Field: [5] PBEGPI5 1848 // 1849 // Clear event EVT0.PBEGPI5 1850 // ENUMs: 1851 // CLEAR The bit is 1 1852 // RETAIN The bit is 0 1853 #define LRFDPBE_EVTCLR1_PBEGPI5 0x00000020U 1854 #define LRFDPBE_EVTCLR1_PBEGPI5_M 0x00000020U 1855 #define LRFDPBE_EVTCLR1_PBEGPI5_S 5U 1856 #define LRFDPBE_EVTCLR1_PBEGPI5_CLEAR 0x00000020U 1857 #define LRFDPBE_EVTCLR1_PBEGPI5_RETAIN 0x00000000U 1858 1859 // Field: [4] PBEGPI4 1860 // 1861 // Clear event EVT0.PBEGPI4 1862 // ENUMs: 1863 // CLEAR The bit is 1 1864 // RETAIN The bit is 0 1865 #define LRFDPBE_EVTCLR1_PBEGPI4 0x00000010U 1866 #define LRFDPBE_EVTCLR1_PBEGPI4_M 0x00000010U 1867 #define LRFDPBE_EVTCLR1_PBEGPI4_S 4U 1868 #define LRFDPBE_EVTCLR1_PBEGPI4_CLEAR 0x00000010U 1869 #define LRFDPBE_EVTCLR1_PBEGPI4_RETAIN 0x00000000U 1870 1871 // Field: [3] PBEGPI3 1872 // 1873 // Clear event EVT0.PBEGPI3 1874 // ENUMs: 1875 // CLEAR The bit is 1 1876 // RETAIN The bit is 0 1877 #define LRFDPBE_EVTCLR1_PBEGPI3 0x00000008U 1878 #define LRFDPBE_EVTCLR1_PBEGPI3_M 0x00000008U 1879 #define LRFDPBE_EVTCLR1_PBEGPI3_S 3U 1880 #define LRFDPBE_EVTCLR1_PBEGPI3_CLEAR 0x00000008U 1881 #define LRFDPBE_EVTCLR1_PBEGPI3_RETAIN 0x00000000U 1882 1883 // Field: [2] PBEGPI2 1884 // 1885 // Clear event EVT0.PBEGPI2 1886 // ENUMs: 1887 // CLEAR The bit is 1 1888 // RETAIN The bit is 0 1889 #define LRFDPBE_EVTCLR1_PBEGPI2 0x00000004U 1890 #define LRFDPBE_EVTCLR1_PBEGPI2_M 0x00000004U 1891 #define LRFDPBE_EVTCLR1_PBEGPI2_S 2U 1892 #define LRFDPBE_EVTCLR1_PBEGPI2_CLEAR 0x00000004U 1893 #define LRFDPBE_EVTCLR1_PBEGPI2_RETAIN 0x00000000U 1894 1895 // Field: [1] PBEGPI1 1896 // 1897 // Clear event EVT0.PBEGPI1 1898 // ENUMs: 1899 // CLEAR The bit is 1 1900 // RETAIN The bit is 0 1901 #define LRFDPBE_EVTCLR1_PBEGPI1 0x00000002U 1902 #define LRFDPBE_EVTCLR1_PBEGPI1_M 0x00000002U 1903 #define LRFDPBE_EVTCLR1_PBEGPI1_S 1U 1904 #define LRFDPBE_EVTCLR1_PBEGPI1_CLEAR 0x00000002U 1905 #define LRFDPBE_EVTCLR1_PBEGPI1_RETAIN 0x00000000U 1906 1907 // Field: [0] PBEGPI0 1908 // 1909 // Clear event EVT0.PBEGPI0 1910 // ENUMs: 1911 // CLEAR The bit is 1 1912 // RETAIN The bit is 0 1913 #define LRFDPBE_EVTCLR1_PBEGPI0 0x00000001U 1914 #define LRFDPBE_EVTCLR1_PBEGPI0_M 0x00000001U 1915 #define LRFDPBE_EVTCLR1_PBEGPI0_S 0U 1916 #define LRFDPBE_EVTCLR1_PBEGPI0_CLEAR 0x00000001U 1917 #define LRFDPBE_EVTCLR1_PBEGPI0_RETAIN 0x00000000U 1918 1919 //***************************************************************************** 1920 // 1921 // Register: LRFDPBE_O_PDREQ 1922 // 1923 //***************************************************************************** 1924 // Field: [0] TOPSMPDREQ 1925 // 1926 // Requests power down for TOPsm core. If the TOPsm has an ongoing memory 1927 // access, the hardware will safely gate the clock after the transaction has 1928 // completed. 1929 // ENUMs: 1930 // ON The bit is 1 1931 // OFF The bit is 0 1932 #define LRFDPBE_PDREQ_TOPSMPDREQ 0x00000001U 1933 #define LRFDPBE_PDREQ_TOPSMPDREQ_M 0x00000001U 1934 #define LRFDPBE_PDREQ_TOPSMPDREQ_S 0U 1935 #define LRFDPBE_PDREQ_TOPSMPDREQ_ON 0x00000001U 1936 #define LRFDPBE_PDREQ_TOPSMPDREQ_OFF 0x00000000U 1937 1938 //***************************************************************************** 1939 // 1940 // Register: LRFDPBE_O_API 1941 // 1942 //***************************************************************************** 1943 // Field: [4:0] PBECMD 1944 // 1945 // PBE Command 1946 // ENUMs: 1947 // ALLONES All the bits are 1 1948 // ALLZEROS All the bits are 0 1949 #define LRFDPBE_API_PBECMD_W 5U 1950 #define LRFDPBE_API_PBECMD_M 0x0000001FU 1951 #define LRFDPBE_API_PBECMD_S 0U 1952 #define LRFDPBE_API_PBECMD_ALLONES 0x0000001FU 1953 #define LRFDPBE_API_PBECMD_ALLZEROS 0x00000000U 1954 1955 //***************************************************************************** 1956 // 1957 // Register: LRFDPBE_O_MCEDATOUT0 1958 // 1959 //***************************************************************************** 1960 // Field: [15:0] VAL 1961 // 1962 // Data to send to the MCE. Writing to this register will trigger an event in 1963 // the MCE, and the data value written here will be readable in 1964 // LRFDMDM:PBEDATIN0 register. 1965 // ENUMs: 1966 // ALLONES All the bits are 1 1967 // ALLZEROS All the bits are 0 1968 #define LRFDPBE_MCEDATOUT0_VAL_W 16U 1969 #define LRFDPBE_MCEDATOUT0_VAL_M 0x0000FFFFU 1970 #define LRFDPBE_MCEDATOUT0_VAL_S 0U 1971 #define LRFDPBE_MCEDATOUT0_VAL_ALLONES 0x0000FFFFU 1972 #define LRFDPBE_MCEDATOUT0_VAL_ALLZEROS 0x00000000U 1973 1974 //***************************************************************************** 1975 // 1976 // Register: LRFDPBE_O_MCEDATIN0 1977 // 1978 //***************************************************************************** 1979 // Field: [15:0] VAL 1980 // 1981 // Data received from MCE 1982 // ENUMs: 1983 // ALLONES All the bits are 1 1984 // ALLZEROS All the bits are 0 1985 #define LRFDPBE_MCEDATIN0_VAL_W 16U 1986 #define LRFDPBE_MCEDATIN0_VAL_M 0x0000FFFFU 1987 #define LRFDPBE_MCEDATIN0_VAL_S 0U 1988 #define LRFDPBE_MCEDATIN0_VAL_ALLONES 0x0000FFFFU 1989 #define LRFDPBE_MCEDATIN0_VAL_ALLZEROS 0x00000000U 1990 1991 //***************************************************************************** 1992 // 1993 // Register: LRFDPBE_O_MCECMDOUT 1994 // 1995 //***************************************************************************** 1996 // Field: [3:0] VAL 1997 // 1998 // Command to send to the MCE. Writing to this register will trigger an event 1999 // in the MCE, and the command value written here will be readable in 2000 // LRFDMDM:PBECMDIN register. 2001 // ENUMs: 2002 // ALLONES All the bits are 1 2003 // ALLZEROS All the bits are 0 2004 #define LRFDPBE_MCECMDOUT_VAL_W 4U 2005 #define LRFDPBE_MCECMDOUT_VAL_M 0x0000000FU 2006 #define LRFDPBE_MCECMDOUT_VAL_S 0U 2007 #define LRFDPBE_MCECMDOUT_VAL_ALLONES 0x0000000FU 2008 #define LRFDPBE_MCECMDOUT_VAL_ALLZEROS 0x00000000U 2009 2010 //***************************************************************************** 2011 // 2012 // Register: LRFDPBE_O_MCECMDIN 2013 // 2014 //***************************************************************************** 2015 // Field: [3:0] VAL 2016 // 2017 // Command received from MCE 2018 // ENUMs: 2019 // ALLONES All the bits are 1 2020 // ALLZEROS All the bits are 0 2021 #define LRFDPBE_MCECMDIN_VAL_W 4U 2022 #define LRFDPBE_MCECMDIN_VAL_M 0x0000000FU 2023 #define LRFDPBE_MCECMDIN_VAL_S 0U 2024 #define LRFDPBE_MCECMDIN_VAL_ALLONES 0x0000000FU 2025 #define LRFDPBE_MCECMDIN_VAL_ALLZEROS 0x00000000U 2026 2027 //***************************************************************************** 2028 // 2029 // Register: LRFDPBE_O_MDMAPI 2030 // 2031 //***************************************************************************** 2032 // Field: [7:4] PROTOCOLID 2033 // 2034 // Protocol ID 2035 // ENUMs: 2036 // ALLONES All the bits are 1 2037 // ALLZEROS All the bits are 0 2038 #define LRFDPBE_MDMAPI_PROTOCOLID_W 4U 2039 #define LRFDPBE_MDMAPI_PROTOCOLID_M 0x000000F0U 2040 #define LRFDPBE_MDMAPI_PROTOCOLID_S 4U 2041 #define LRFDPBE_MDMAPI_PROTOCOLID_ALLONES 0x000000F0U 2042 #define LRFDPBE_MDMAPI_PROTOCOLID_ALLZEROS 0x00000000U 2043 2044 // Field: [3:0] MDMCMD 2045 // 2046 // Modem command 2047 // ENUMs: 2048 // ALLONES All the bits are 1 2049 // ALLZEROS All the bits are 0 2050 #define LRFDPBE_MDMAPI_MDMCMD_W 4U 2051 #define LRFDPBE_MDMAPI_MDMCMD_M 0x0000000FU 2052 #define LRFDPBE_MDMAPI_MDMCMD_S 0U 2053 #define LRFDPBE_MDMAPI_MDMCMD_ALLONES 0x0000000FU 2054 #define LRFDPBE_MDMAPI_MDMCMD_ALLZEROS 0x00000000U 2055 2056 //***************************************************************************** 2057 // 2058 // Register: LRFDPBE_O_MDMMSGBOX 2059 // 2060 //***************************************************************************** 2061 // Field: [7:0] VALUE 2062 // 2063 // Diverse status, error, report bits from MCE. Controlled by software. 2064 // ENUMs: 2065 // ALLONES All the bits are 1 2066 // ALLZEROS All the bits are 0 2067 #define LRFDPBE_MDMMSGBOX_VALUE_W 8U 2068 #define LRFDPBE_MDMMSGBOX_VALUE_M 0x000000FFU 2069 #define LRFDPBE_MDMMSGBOX_VALUE_S 0U 2070 #define LRFDPBE_MDMMSGBOX_VALUE_ALLONES 0x000000FFU 2071 #define LRFDPBE_MDMMSGBOX_VALUE_ALLZEROS 0x00000000U 2072 2073 //***************************************************************************** 2074 // 2075 // Register: LRFDPBE_O_FREQ 2076 // 2077 //***************************************************************************** 2078 // Field: [15:0] OFFSET 2079 // 2080 // Frequency Offset from MCE. Controlled by software. 2081 // ENUMs: 2082 // ALLONES All the bits are 1 2083 // ALLZEROS All the bits are 0 2084 #define LRFDPBE_FREQ_OFFSET_W 16U 2085 #define LRFDPBE_FREQ_OFFSET_M 0x0000FFFFU 2086 #define LRFDPBE_FREQ_OFFSET_S 0U 2087 #define LRFDPBE_FREQ_OFFSET_ALLONES 0x0000FFFFU 2088 #define LRFDPBE_FREQ_OFFSET_ALLZEROS 0x00000000U 2089 2090 //***************************************************************************** 2091 // 2092 // Register: LRFDPBE_O_MDMLQI 2093 // 2094 //***************************************************************************** 2095 // Field: [7:0] VAL 2096 // 2097 // LQI status from MCE. Controlled by software. 2098 // ENUMs: 2099 // ALLONES All the bits are 1 2100 // ALLZEROS All the bits are 0 2101 #define LRFDPBE_MDMLQI_VAL_W 8U 2102 #define LRFDPBE_MDMLQI_VAL_M 0x000000FFU 2103 #define LRFDPBE_MDMLQI_VAL_S 0U 2104 #define LRFDPBE_MDMLQI_VAL_ALLONES 0x000000FFU 2105 #define LRFDPBE_MDMLQI_VAL_ALLZEROS 0x00000000U 2106 2107 //***************************************************************************** 2108 // 2109 // Register: LRFDPBE_O_RFEDATOUT0 2110 // 2111 //***************************************************************************** 2112 // Field: [15:0] VAL 2113 // 2114 // Data to send to the RFE. Writing to this register will trigger an event in 2115 // the RFE, and the data value written here will be readable in 2116 // LRFDRFE:PBEDATIN0 register. 2117 // ENUMs: 2118 // ALLONES All the bits are 1 2119 // ALLZEROS All the bits are 0 2120 #define LRFDPBE_RFEDATOUT0_VAL_W 16U 2121 #define LRFDPBE_RFEDATOUT0_VAL_M 0x0000FFFFU 2122 #define LRFDPBE_RFEDATOUT0_VAL_S 0U 2123 #define LRFDPBE_RFEDATOUT0_VAL_ALLONES 0x0000FFFFU 2124 #define LRFDPBE_RFEDATOUT0_VAL_ALLZEROS 0x00000000U 2125 2126 //***************************************************************************** 2127 // 2128 // Register: LRFDPBE_O_RFEDATIN0 2129 // 2130 //***************************************************************************** 2131 // Field: [15:0] VAL 2132 // 2133 // Data received from RFE 2134 // ENUMs: 2135 // ALLONES All the bits are 1 2136 // ALLZEROS All the bits are 0 2137 #define LRFDPBE_RFEDATIN0_VAL_W 16U 2138 #define LRFDPBE_RFEDATIN0_VAL_M 0x0000FFFFU 2139 #define LRFDPBE_RFEDATIN0_VAL_S 0U 2140 #define LRFDPBE_RFEDATIN0_VAL_ALLONES 0x0000FFFFU 2141 #define LRFDPBE_RFEDATIN0_VAL_ALLZEROS 0x00000000U 2142 2143 //***************************************************************************** 2144 // 2145 // Register: LRFDPBE_O_RFECMDOUT 2146 // 2147 //***************************************************************************** 2148 // Field: [3:0] VAL 2149 // 2150 // Command to send to the RFE. Writing to this register will trigger an event 2151 // in the RFE, and the command value written here will be readable in 2152 // LRFDRFE:PBECMDIN register. 2153 // ENUMs: 2154 // ALLONES All the bits are 1 2155 // ALLZEROS All the bits are 0 2156 #define LRFDPBE_RFECMDOUT_VAL_W 4U 2157 #define LRFDPBE_RFECMDOUT_VAL_M 0x0000000FU 2158 #define LRFDPBE_RFECMDOUT_VAL_S 0U 2159 #define LRFDPBE_RFECMDOUT_VAL_ALLONES 0x0000000FU 2160 #define LRFDPBE_RFECMDOUT_VAL_ALLZEROS 0x00000000U 2161 2162 //***************************************************************************** 2163 // 2164 // Register: LRFDPBE_O_RFECMDIN 2165 // 2166 //***************************************************************************** 2167 // Field: [3:0] VAL 2168 // 2169 // Command received from RFE 2170 // ENUMs: 2171 // ALLONES All the bits are 1 2172 // ALLZEROS All the bits are 0 2173 #define LRFDPBE_RFECMDIN_VAL_W 4U 2174 #define LRFDPBE_RFECMDIN_VAL_M 0x0000000FU 2175 #define LRFDPBE_RFECMDIN_VAL_S 0U 2176 #define LRFDPBE_RFECMDIN_VAL_ALLONES 0x0000000FU 2177 #define LRFDPBE_RFECMDIN_VAL_ALLZEROS 0x00000000U 2178 2179 //***************************************************************************** 2180 // 2181 // Register: LRFDPBE_O_RFEAPI 2182 // 2183 //***************************************************************************** 2184 // Field: [7:4] PROTOCOLID 2185 // 2186 // Protocol ID 2187 // ENUMs: 2188 // ALLONES All the bits are 1 2189 // ALLZEROS All the bits are 0 2190 #define LRFDPBE_RFEAPI_PROTOCOLID_W 4U 2191 #define LRFDPBE_RFEAPI_PROTOCOLID_M 0x000000F0U 2192 #define LRFDPBE_RFEAPI_PROTOCOLID_S 4U 2193 #define LRFDPBE_RFEAPI_PROTOCOLID_ALLONES 0x000000F0U 2194 #define LRFDPBE_RFEAPI_PROTOCOLID_ALLZEROS 0x00000000U 2195 2196 // Field: [3:0] RFECMD 2197 // 2198 // RFE Command 2199 // ENUMs: 2200 // ALLONES All the bits are 1 2201 // ALLZEROS All the bits are 0 2202 #define LRFDPBE_RFEAPI_RFECMD_W 4U 2203 #define LRFDPBE_RFEAPI_RFECMD_M 0x0000000FU 2204 #define LRFDPBE_RFEAPI_RFECMD_S 0U 2205 #define LRFDPBE_RFEAPI_RFECMD_ALLONES 0x0000000FU 2206 #define LRFDPBE_RFEAPI_RFECMD_ALLZEROS 0x00000000U 2207 2208 //***************************************************************************** 2209 // 2210 // Register: LRFDPBE_O_RFECMDPAR0 2211 // 2212 //***************************************************************************** 2213 // Field: [15:0] VAL 2214 // 2215 // Parameter 0 2216 // ENUMs: 2217 // ALLONES All the bits are 1 2218 // ALLZEROS All the bits are 0 2219 #define LRFDPBE_RFECMDPAR0_VAL_W 16U 2220 #define LRFDPBE_RFECMDPAR0_VAL_M 0x0000FFFFU 2221 #define LRFDPBE_RFECMDPAR0_VAL_S 0U 2222 #define LRFDPBE_RFECMDPAR0_VAL_ALLONES 0x0000FFFFU 2223 #define LRFDPBE_RFECMDPAR0_VAL_ALLZEROS 0x00000000U 2224 2225 //***************************************************************************** 2226 // 2227 // Register: LRFDPBE_O_RFECMDPAR1 2228 // 2229 //***************************************************************************** 2230 // Field: [15:0] VAL 2231 // 2232 // Parameter 1 2233 // ENUMs: 2234 // ALLONES All the bits are 1 2235 // ALLZEROS All the bits are 0 2236 #define LRFDPBE_RFECMDPAR1_VAL_W 16U 2237 #define LRFDPBE_RFECMDPAR1_VAL_M 0x0000FFFFU 2238 #define LRFDPBE_RFECMDPAR1_VAL_S 0U 2239 #define LRFDPBE_RFECMDPAR1_VAL_ALLONES 0x0000FFFFU 2240 #define LRFDPBE_RFECMDPAR1_VAL_ALLZEROS 0x00000000U 2241 2242 //***************************************************************************** 2243 // 2244 // Register: LRFDPBE_O_RFEMSGBOX 2245 // 2246 //***************************************************************************** 2247 // Field: [7:0] VAL 2248 // 2249 // Diverse status, error, report bits from RFE 2250 // ENUMs: 2251 // ALLONES All the bits are 1 2252 // ALLZEROS All the bits are 0 2253 #define LRFDPBE_RFEMSGBOX_VAL_W 8U 2254 #define LRFDPBE_RFEMSGBOX_VAL_M 0x000000FFU 2255 #define LRFDPBE_RFEMSGBOX_VAL_S 0U 2256 #define LRFDPBE_RFEMSGBOX_VAL_ALLONES 0x000000FFU 2257 #define LRFDPBE_RFEMSGBOX_VAL_ALLZEROS 0x00000000U 2258 2259 //***************************************************************************** 2260 // 2261 // Register: LRFDPBE_O_RFERSSI 2262 // 2263 //***************************************************************************** 2264 // Field: [7:0] VAL 2265 // 2266 // Current RSSI value (signed). If this register reads as -128 (0x80) it means 2267 // that the value is not yet valid. 2268 // ENUMs: 2269 // ALLONES All the bits are 1 2270 // ALLZEROS All the bits are 0 2271 #define LRFDPBE_RFERSSI_VAL_W 8U 2272 #define LRFDPBE_RFERSSI_VAL_M 0x000000FFU 2273 #define LRFDPBE_RFERSSI_VAL_S 0U 2274 #define LRFDPBE_RFERSSI_VAL_ALLONES 0x000000FFU 2275 #define LRFDPBE_RFERSSI_VAL_ALLZEROS 0x00000000U 2276 2277 //***************************************************************************** 2278 // 2279 // Register: LRFDPBE_O_RFERSSIMAX 2280 // 2281 //***************************************************************************** 2282 // Field: [7:0] VAL 2283 // 2284 // Maximum RSSI value since start of measurements cycle. If this field reads as 2285 // -128 (0x80) it means that the value is not yet valid. 2286 // ENUMs: 2287 // ALLONES All the bits are 1 2288 // ALLZEROS All the bits are 0 2289 #define LRFDPBE_RFERSSIMAX_VAL_W 8U 2290 #define LRFDPBE_RFERSSIMAX_VAL_M 0x000000FFU 2291 #define LRFDPBE_RFERSSIMAX_VAL_S 0U 2292 #define LRFDPBE_RFERSSIMAX_VAL_ALLONES 0x000000FFU 2293 #define LRFDPBE_RFERSSIMAX_VAL_ALLZEROS 0x00000000U 2294 2295 //***************************************************************************** 2296 // 2297 // Register: LRFDPBE_O_RFERFGAIN 2298 // 2299 //***************************************************************************** 2300 // Field: [7:0] DBGAIN 2301 // 2302 // Current RF front-end gain, in dB 2303 // ENUMs: 2304 // ALLONES All the bits are 1 2305 // ALLZEROS All the bits are 0 2306 #define LRFDPBE_RFERFGAIN_DBGAIN_W 8U 2307 #define LRFDPBE_RFERFGAIN_DBGAIN_M 0x000000FFU 2308 #define LRFDPBE_RFERFGAIN_DBGAIN_S 0U 2309 #define LRFDPBE_RFERFGAIN_DBGAIN_ALLONES 0x000000FFU 2310 #define LRFDPBE_RFERFGAIN_DBGAIN_ALLZEROS 0x00000000U 2311 2312 //***************************************************************************** 2313 // 2314 // Register: LRFDPBE_O_MDMSYNCAL 2315 // 2316 //***************************************************************************** 2317 // Field: [15:0] SWALSB 2318 // 2319 // Sync word A bits 15:0. Sync words shorter than 32 bits must be stored as 2320 // most signicant bits of sync word A. The sync word is expected to be 2321 // transmitted/received in lsb to msb order. 2322 // ENUMs: 2323 // ALLONES All the bits are 1 2324 // ALLZEROS All the bits are 0 2325 #define LRFDPBE_MDMSYNCAL_SWALSB_W 16U 2326 #define LRFDPBE_MDMSYNCAL_SWALSB_M 0x0000FFFFU 2327 #define LRFDPBE_MDMSYNCAL_SWALSB_S 0U 2328 #define LRFDPBE_MDMSYNCAL_SWALSB_ALLONES 0x0000FFFFU 2329 #define LRFDPBE_MDMSYNCAL_SWALSB_ALLZEROS 0x00000000U 2330 2331 //***************************************************************************** 2332 // 2333 // Register: LRFDPBE_O_MDMSYNCAH 2334 // 2335 //***************************************************************************** 2336 // Field: [15:0] SWAMSB 2337 // 2338 // Sync word A bits 31:16. Sync words shorter than 32 bits must be stored as 2339 // most significant bits of sync word A. The sync word is expected to be 2340 // transmitted/received in lsb to msb order. 2341 // ENUMs: 2342 // ALLONES All the bits are 1 2343 // ALLZEROS All the bits are 0 2344 #define LRFDPBE_MDMSYNCAH_SWAMSB_W 16U 2345 #define LRFDPBE_MDMSYNCAH_SWAMSB_M 0x0000FFFFU 2346 #define LRFDPBE_MDMSYNCAH_SWAMSB_S 0U 2347 #define LRFDPBE_MDMSYNCAH_SWAMSB_ALLONES 0x0000FFFFU 2348 #define LRFDPBE_MDMSYNCAH_SWAMSB_ALLZEROS 0x00000000U 2349 2350 //***************************************************************************** 2351 // 2352 // Register: LRFDPBE_O_MDMSYNCBL 2353 // 2354 //***************************************************************************** 2355 // Field: [15:0] SWBLSB 2356 // 2357 // Sync word B bits 15:0. Sync words shorter than 32 bits must be stored as 2358 // most significant bits of sync word B. The sync word is expected to be 2359 // transmitted/received in lsb to msb order. 2360 // ENUMs: 2361 // ALLONES All the bits are 1 2362 // ALLZEROS All the bits are 0 2363 #define LRFDPBE_MDMSYNCBL_SWBLSB_W 16U 2364 #define LRFDPBE_MDMSYNCBL_SWBLSB_M 0x0000FFFFU 2365 #define LRFDPBE_MDMSYNCBL_SWBLSB_S 0U 2366 #define LRFDPBE_MDMSYNCBL_SWBLSB_ALLONES 0x0000FFFFU 2367 #define LRFDPBE_MDMSYNCBL_SWBLSB_ALLZEROS 0x00000000U 2368 2369 //***************************************************************************** 2370 // 2371 // Register: LRFDPBE_O_MDMSYNCBH 2372 // 2373 //***************************************************************************** 2374 // Field: [15:0] SWBMSB 2375 // 2376 // Sync word B bits 31:16. Sync words shorter than 32 bits must be stored as 2377 // most significant bits of sync word B. The sync word is expected to be 2378 // transmitted/received in lsb to msb order. 2379 // ENUMs: 2380 // ALLONES All the bits are 1 2381 // ALLZEROS All the bits are 0 2382 #define LRFDPBE_MDMSYNCBH_SWBMSB_W 16U 2383 #define LRFDPBE_MDMSYNCBH_SWBMSB_M 0x0000FFFFU 2384 #define LRFDPBE_MDMSYNCBH_SWBMSB_S 0U 2385 #define LRFDPBE_MDMSYNCBH_SWBMSB_ALLONES 0x0000FFFFU 2386 #define LRFDPBE_MDMSYNCBH_SWBMSB_ALLZEROS 0x00000000U 2387 2388 //***************************************************************************** 2389 // 2390 // Register: LRFDPBE_O_MDMCMDPAR0 2391 // 2392 //***************************************************************************** 2393 // Field: [15:0] VAL 2394 // 2395 // Parameter 0. Software defined function. 2396 // ENUMs: 2397 // ALLONES All the bits are 1 2398 // ALLZEROS All the bits are 0 2399 #define LRFDPBE_MDMCMDPAR0_VAL_W 16U 2400 #define LRFDPBE_MDMCMDPAR0_VAL_M 0x0000FFFFU 2401 #define LRFDPBE_MDMCMDPAR0_VAL_S 0U 2402 #define LRFDPBE_MDMCMDPAR0_VAL_ALLONES 0x0000FFFFU 2403 #define LRFDPBE_MDMCMDPAR0_VAL_ALLZEROS 0x00000000U 2404 2405 //***************************************************************************** 2406 // 2407 // Register: LRFDPBE_O_MDMCMDPAR1 2408 // 2409 //***************************************************************************** 2410 // Field: [15:0] VAL 2411 // 2412 // Parameter 1. Software defined function. 2413 // ENUMs: 2414 // ALLONES All the bits are 1 2415 // ALLZEROS All the bits are 0 2416 #define LRFDPBE_MDMCMDPAR1_VAL_W 16U 2417 #define LRFDPBE_MDMCMDPAR1_VAL_M 0x0000FFFFU 2418 #define LRFDPBE_MDMCMDPAR1_VAL_S 0U 2419 #define LRFDPBE_MDMCMDPAR1_VAL_ALLONES 0x0000FFFFU 2420 #define LRFDPBE_MDMCMDPAR1_VAL_ALLZEROS 0x00000000U 2421 2422 //***************************************************************************** 2423 // 2424 // Register: LRFDPBE_O_MDMCMDPAR2 2425 // 2426 //***************************************************************************** 2427 // Field: [15:0] VAL 2428 // 2429 // Parameter 2. Software defined function. 2430 // ENUMs: 2431 // ALLONES All the bits are 1 2432 // ALLZEROS All the bits are 0 2433 #define LRFDPBE_MDMCMDPAR2_VAL_W 16U 2434 #define LRFDPBE_MDMCMDPAR2_VAL_M 0x0000FFFFU 2435 #define LRFDPBE_MDMCMDPAR2_VAL_S 0U 2436 #define LRFDPBE_MDMCMDPAR2_VAL_ALLONES 0x0000FFFFU 2437 #define LRFDPBE_MDMCMDPAR2_VAL_ALLZEROS 0x00000000U 2438 2439 //***************************************************************************** 2440 // 2441 // Register: LRFDPBE_O_POLY0L 2442 // 2443 //***************************************************************************** 2444 // Field: [15:0] VALLSB 2445 // 2446 // LFSR 0 polynomial taps, lower half 2447 // ENUMs: 2448 // ALLONES All the bits are 1 2449 // ALLZEROS All the bits are 0 2450 #define LRFDPBE_POLY0L_VALLSB_W 16U 2451 #define LRFDPBE_POLY0L_VALLSB_M 0x0000FFFFU 2452 #define LRFDPBE_POLY0L_VALLSB_S 0U 2453 #define LRFDPBE_POLY0L_VALLSB_ALLONES 0x0000FFFFU 2454 #define LRFDPBE_POLY0L_VALLSB_ALLZEROS 0x00000000U 2455 2456 //***************************************************************************** 2457 // 2458 // Register: LRFDPBE_O_POLY0H 2459 // 2460 //***************************************************************************** 2461 // Field: [15:0] VALMSB 2462 // 2463 // LFSR 0 polynomial taps, upper half 2464 // ENUMs: 2465 // ALLONES All the bits are 1 2466 // ALLZEROS All the bits are 0 2467 #define LRFDPBE_POLY0H_VALMSB_W 16U 2468 #define LRFDPBE_POLY0H_VALMSB_M 0x0000FFFFU 2469 #define LRFDPBE_POLY0H_VALMSB_S 0U 2470 #define LRFDPBE_POLY0H_VALMSB_ALLONES 0x0000FFFFU 2471 #define LRFDPBE_POLY0H_VALMSB_ALLZEROS 0x00000000U 2472 2473 //***************************************************************************** 2474 // 2475 // Register: LRFDPBE_O_POLY1L 2476 // 2477 //***************************************************************************** 2478 // Field: [15:0] VALLSB 2479 // 2480 // LFSR 1 polynomial taps, low part 2481 // ENUMs: 2482 // ALLONES All the bits are 1 2483 // ALLZEROS All the bits are 0 2484 #define LRFDPBE_POLY1L_VALLSB_W 16U 2485 #define LRFDPBE_POLY1L_VALLSB_M 0x0000FFFFU 2486 #define LRFDPBE_POLY1L_VALLSB_S 0U 2487 #define LRFDPBE_POLY1L_VALLSB_ALLONES 0x0000FFFFU 2488 #define LRFDPBE_POLY1L_VALLSB_ALLZEROS 0x00000000U 2489 2490 //***************************************************************************** 2491 // 2492 // Register: LRFDPBE_O_POLY1H 2493 // 2494 //***************************************************************************** 2495 // Field: [15:0] VALMSB 2496 // 2497 // LFSR 1 polynomial taps, high part 2498 // ENUMs: 2499 // ALLONES All the bits are 1 2500 // ALLZEROS All the bits are 0 2501 #define LRFDPBE_POLY1H_VALMSB_W 16U 2502 #define LRFDPBE_POLY1H_VALMSB_M 0x0000FFFFU 2503 #define LRFDPBE_POLY1H_VALMSB_S 0U 2504 #define LRFDPBE_POLY1H_VALMSB_ALLONES 0x0000FFFFU 2505 #define LRFDPBE_POLY1H_VALMSB_ALLZEROS 0x00000000U 2506 2507 //***************************************************************************** 2508 // 2509 // Register: LRFDPBE_O_PHACFG 2510 // 2511 //***************************************************************************** 2512 // Field: [2:1] MODE1 2513 // 2514 // Dual LFSR operating mode 2515 // ENUMs: 2516 // PARAL LFSR0 and LFSR1 are operated in parallel 2517 // CASC LFSR0 whitener is followed by LFSR1 CRC 2518 // INDEP LFSR0 and LFSR1 are operated independently 2519 #define LRFDPBE_PHACFG_MODE1_W 2U 2520 #define LRFDPBE_PHACFG_MODE1_M 0x00000006U 2521 #define LRFDPBE_PHACFG_MODE1_S 1U 2522 #define LRFDPBE_PHACFG_MODE1_PARAL 0x00000004U 2523 #define LRFDPBE_PHACFG_MODE1_CASC 0x00000002U 2524 #define LRFDPBE_PHACFG_MODE1_INDEP 0x00000000U 2525 2526 // Field: [0] MODE0 2527 // 2528 // LFSR 0 operating mode 2529 // ENUMs: 2530 // WHITE LFSR 0 is in whitening mode 2531 // CRC LFSR 0 is in CRC mode 2532 #define LRFDPBE_PHACFG_MODE0 0x00000001U 2533 #define LRFDPBE_PHACFG_MODE0_M 0x00000001U 2534 #define LRFDPBE_PHACFG_MODE0_S 0U 2535 #define LRFDPBE_PHACFG_MODE0_WHITE 0x00000001U 2536 #define LRFDPBE_PHACFG_MODE0_CRC 0x00000000U 2537 2538 //***************************************************************************** 2539 // 2540 // Register: LRFDPBE_O_FCFG0 2541 // 2542 //***************************************************************************** 2543 // Field: [7] TXIRQMET 2544 // 2545 // Select source for pbe_irq(17) 2546 // ENUMs: 2547 // TXRDBTHR The TX FIFO contains TXFRBTHRS or more readable 2548 // bytes. 2549 // TXWRBTHR The TX FIFO contains TXFWBTHRS or more writable 2550 // bytes. 2551 #define LRFDPBE_FCFG0_TXIRQMET 0x00000080U 2552 #define LRFDPBE_FCFG0_TXIRQMET_M 0x00000080U 2553 #define LRFDPBE_FCFG0_TXIRQMET_S 7U 2554 #define LRFDPBE_FCFG0_TXIRQMET_TXRDBTHR 0x00000080U 2555 #define LRFDPBE_FCFG0_TXIRQMET_TXWRBTHR 0x00000000U 2556 2557 // Field: [6] RXIRQMET 2558 // 2559 // Select source for pbe_irq(16) 2560 // ENUMs: 2561 // RXWRBTHR The RX FIFO contains RXFWBTHRS or more writable 2562 // bytes. 2563 // RXRDBTHR The RX FIFO contains RXFRBTHRS or more readable 2564 // bytes. 2565 #define LRFDPBE_FCFG0_RXIRQMET 0x00000040U 2566 #define LRFDPBE_FCFG0_RXIRQMET_M 0x00000040U 2567 #define LRFDPBE_FCFG0_RXIRQMET_S 6U 2568 #define LRFDPBE_FCFG0_RXIRQMET_RXWRBTHR 0x00000040U 2569 #define LRFDPBE_FCFG0_RXIRQMET_RXRDBTHR 0x00000000U 2570 2571 // Field: [5] TXACOM 2572 // 2573 // Automatic FIFO commit configuration 2574 // ENUMs: 2575 // EN Always set TXSWP := TXWP 2576 // DIS commit TXFIFO only on command 0x95 2577 #define LRFDPBE_FCFG0_TXACOM 0x00000020U 2578 #define LRFDPBE_FCFG0_TXACOM_M 0x00000020U 2579 #define LRFDPBE_FCFG0_TXACOM_S 5U 2580 #define LRFDPBE_FCFG0_TXACOM_EN 0x00000020U 2581 #define LRFDPBE_FCFG0_TXACOM_DIS 0x00000000U 2582 2583 // Field: [4] TXADEAL 2584 // 2585 // Automatic deallocation setting 2586 // ENUMs: 2587 // EN Always set TXFSRP := TXFRP. 2588 // DIS Deallocate TXFIFO only on command 0x92 2589 #define LRFDPBE_FCFG0_TXADEAL 0x00000010U 2590 #define LRFDPBE_FCFG0_TXADEAL_M 0x00000010U 2591 #define LRFDPBE_FCFG0_TXADEAL_S 4U 2592 #define LRFDPBE_FCFG0_TXADEAL_EN 0x00000010U 2593 #define LRFDPBE_FCFG0_TXADEAL_DIS 0x00000000U 2594 2595 // Field: [1] RXACOM 2596 // 2597 // Automatic FIFO commit configuration 2598 // ENUMs: 2599 // EN Always set RXFSWP := RXFWP 2600 // DIS commit rxfifo only on command 0x85 2601 #define LRFDPBE_FCFG0_RXACOM 0x00000002U 2602 #define LRFDPBE_FCFG0_RXACOM_M 0x00000002U 2603 #define LRFDPBE_FCFG0_RXACOM_S 1U 2604 #define LRFDPBE_FCFG0_RXACOM_EN 0x00000002U 2605 #define LRFDPBE_FCFG0_RXACOM_DIS 0x00000000U 2606 2607 // Field: [0] RXADEAL 2608 // 2609 // Automatic deallocation setting 2610 // ENUMs: 2611 // EN Always set RXFSRP := RXFRP. 2612 // DIS Deallocate RXFIFO only on command 0x82 2613 #define LRFDPBE_FCFG0_RXADEAL 0x00000001U 2614 #define LRFDPBE_FCFG0_RXADEAL_M 0x00000001U 2615 #define LRFDPBE_FCFG0_RXADEAL_S 0U 2616 #define LRFDPBE_FCFG0_RXADEAL_EN 0x00000001U 2617 #define LRFDPBE_FCFG0_RXADEAL_DIS 0x00000000U 2618 2619 //***************************************************************************** 2620 // 2621 // Register: LRFDPBE_O_FCFG1 2622 // 2623 //***************************************************************************** 2624 // Field: [8:0] TXSTRT 2625 // 2626 // FIFO start address, offset from start of BUFRAM. Address is 32-bit word 2627 // address (not byte address) 2628 // ENUMs: 2629 // ONES All bits are 1s 2630 // ZEROS All bits are zero 2631 #define LRFDPBE_FCFG1_TXSTRT_W 9U 2632 #define LRFDPBE_FCFG1_TXSTRT_M 0x000001FFU 2633 #define LRFDPBE_FCFG1_TXSTRT_S 0U 2634 #define LRFDPBE_FCFG1_TXSTRT_ONES 0x000001FFU 2635 #define LRFDPBE_FCFG1_TXSTRT_ZEROS 0x00000000U 2636 2637 //***************************************************************************** 2638 // 2639 // Register: LRFDPBE_O_FCFG2 2640 // 2641 //***************************************************************************** 2642 // Field: [10:8] TXHSIZE 2643 // 2644 // Select transfer size to calculate DMA_SREQ_TRIGGER MD(more data) and FREE, 2645 // for both RX FIFO and TX FIFO. 2646 // ENUMs: 2647 // WORD MCU receives IRQ when the TX FIFO contains more or 2648 // equal amount of data than the configured 2649 // threshold. 2650 // HALFW MCU receives IRQ when the TX FIFO contains less 2651 // amount of data than the configured threshold. 2652 // BYTE MCU receives IRQ when the TX FIFO contains less 2653 // amount of data than the configured threshold. 2654 #define LRFDPBE_FCFG2_TXHSIZE_W 3U 2655 #define LRFDPBE_FCFG2_TXHSIZE_M 0x00000700U 2656 #define LRFDPBE_FCFG2_TXHSIZE_S 8U 2657 #define LRFDPBE_FCFG2_TXHSIZE_WORD 0x00000200U 2658 #define LRFDPBE_FCFG2_TXHSIZE_HALFW 0x00000100U 2659 #define LRFDPBE_FCFG2_TXHSIZE_BYTE 0x00000000U 2660 2661 // Field: [7:0] TXSIZE 2662 // 2663 // TXFIFO size in number of 32-bit words 2664 // ENUMs: 2665 // ONES All bits are 1s 2666 // ZEROS All bits are zero 2667 #define LRFDPBE_FCFG2_TXSIZE_W 8U 2668 #define LRFDPBE_FCFG2_TXSIZE_M 0x000000FFU 2669 #define LRFDPBE_FCFG2_TXSIZE_S 0U 2670 #define LRFDPBE_FCFG2_TXSIZE_ONES 0x000000FFU 2671 #define LRFDPBE_FCFG2_TXSIZE_ZEROS 0x00000000U 2672 2673 //***************************************************************************** 2674 // 2675 // Register: LRFDPBE_O_FCFG3 2676 // 2677 //***************************************************************************** 2678 // Field: [8:0] RXSTRT 2679 // 2680 // FIFO start address, offset from start of BUFRAM. Address is 32-bit word 2681 // adress (not byte address) 2682 // ENUMs: 2683 // ONES All bits are 1s 2684 // ZEROS All bits are zero 2685 #define LRFDPBE_FCFG3_RXSTRT_W 9U 2686 #define LRFDPBE_FCFG3_RXSTRT_M 0x000001FFU 2687 #define LRFDPBE_FCFG3_RXSTRT_S 0U 2688 #define LRFDPBE_FCFG3_RXSTRT_ONES 0x000001FFU 2689 #define LRFDPBE_FCFG3_RXSTRT_ZEROS 0x00000000U 2690 2691 //***************************************************************************** 2692 // 2693 // Register: LRFDPBE_O_FCFG4 2694 // 2695 //***************************************************************************** 2696 // Field: [10:8] RXHSIZE 2697 // 2698 // Select transfer size to calculate DMA_SREQ_TRIGGER MD(more data) and FREE, 2699 // for both RX FIFO and TX FIFO. 2700 // ENUMs: 2701 // WORD MCU receives IRQ when the TX FIFO contains more or 2702 // equal amount of data than the configured 2703 // threshold. 2704 // HALFW MCU receives IRQ when the TX FIFO contains less 2705 // amount of data than the configured threshold. 2706 // BYTE MCU receives IRQ when the TX FIFO contains less 2707 // amount of data than the configured threshold. 2708 #define LRFDPBE_FCFG4_RXHSIZE_W 3U 2709 #define LRFDPBE_FCFG4_RXHSIZE_M 0x00000700U 2710 #define LRFDPBE_FCFG4_RXHSIZE_S 8U 2711 #define LRFDPBE_FCFG4_RXHSIZE_WORD 0x00000200U 2712 #define LRFDPBE_FCFG4_RXHSIZE_HALFW 0x00000100U 2713 #define LRFDPBE_FCFG4_RXHSIZE_BYTE 0x00000000U 2714 2715 // Field: [7:0] RXSIZE 2716 // 2717 // RXFIFO size in number of 32-bit words 2718 // ENUMs: 2719 // ONES Always set RXFSWP := RXFWP 2720 // ZEROS commit rxfifo only on command 0x85 2721 #define LRFDPBE_FCFG4_RXSIZE_W 8U 2722 #define LRFDPBE_FCFG4_RXSIZE_M 0x000000FFU 2723 #define LRFDPBE_FCFG4_RXSIZE_S 0U 2724 #define LRFDPBE_FCFG4_RXSIZE_ONES 0x000000FFU 2725 #define LRFDPBE_FCFG4_RXSIZE_ZEROS 0x00000000U 2726 2727 //***************************************************************************** 2728 // 2729 // Register: LRFDPBE_O_FCFG5 2730 // 2731 //***************************************************************************** 2732 // Field: [8:6] DMASREQ 2733 // 2734 // DMA trigger select. Triggers DMA when selected trigger occurs. Note that it 2735 // is a mix of pulse type and level type triggers 2736 // ENUMs: 2737 // TXFIFOFREE The TX FIFO contains FCFG2_TXHSIZE or more 2738 // writable bytes. 2739 // TXFIFOMD The TX FIFO contains FCFG2_TXHSIZE or more 2740 // readable bytes. 2741 // RXFIFOFREE The RX FIFO contains FCFG4_RXHSIZE or more 2742 // writable bytes. 2743 // RXFIFOMD The RX FIFO contains FCFG4_RXHSIZE or more 2744 // readable bytes. 2745 // NONE No triggers generated 2746 #define LRFDPBE_FCFG5_DMASREQ_W 3U 2747 #define LRFDPBE_FCFG5_DMASREQ_M 0x000001C0U 2748 #define LRFDPBE_FCFG5_DMASREQ_S 6U 2749 #define LRFDPBE_FCFG5_DMASREQ_TXFIFOFREE 0x00000100U 2750 #define LRFDPBE_FCFG5_DMASREQ_TXFIFOMD 0x000000C0U 2751 #define LRFDPBE_FCFG5_DMASREQ_RXFIFOFREE 0x00000080U 2752 #define LRFDPBE_FCFG5_DMASREQ_RXFIFOMD 0x00000040U 2753 #define LRFDPBE_FCFG5_DMASREQ_NONE 0x00000000U 2754 2755 // Field: [4:0] DMAREQ 2756 // 2757 // DMA trigger select. Triggers DMA when selected trigger occurs. Note that it 2758 // is a mix of pulse type and level type triggers 2759 // ENUMs: 2760 // TXFIFO_COMMIT TXFIFO is committed 2761 // TXFIFO_DISCARD TXFIFO is discarded 2762 // TXFIFO_RETRY TXFIFO is retried 2763 // TXFIFO_DEALLOC TXFIFO is deallocated 2764 // TXFIFO_RESET TXFIFO is reset 2765 // TXWRBTHR_MET The TX FIFO contains TXFWBTHRS or more writable 2766 // bytes. 2767 // TXRDBTHR_MET The TX FIFO contains TXFRBTHRS or more readable 2768 // bytes. 2769 // RXFIFO_COMMIT RXFIFO is committed 2770 // RXFIFO_DISCARD RXFIFO is discarded 2771 // RXFIFO_RETRY RXFIFO is retried 2772 // RXFIFO_DEALLOC RXFIFO is deallocated 2773 // RXFIFO_RESET RXFIFO is reset 2774 // RXWRBTHR_MET The RX FIFO contains RXFWBTHRS or more writable 2775 // bytes. 2776 // RXRDBTHR_MET The RX FIFO contains RXFRBTHRS or more readable 2777 // bytes. 2778 // NONE No triggers generated 2779 #define LRFDPBE_FCFG5_DMAREQ_W 5U 2780 #define LRFDPBE_FCFG5_DMAREQ_M 0x0000001FU 2781 #define LRFDPBE_FCFG5_DMAREQ_S 0U 2782 #define LRFDPBE_FCFG5_DMAREQ_TXFIFO_COMMIT 0x0000000FU 2783 #define LRFDPBE_FCFG5_DMAREQ_TXFIFO_DISCARD 0x0000000EU 2784 #define LRFDPBE_FCFG5_DMAREQ_TXFIFO_RETRY 0x0000000DU 2785 #define LRFDPBE_FCFG5_DMAREQ_TXFIFO_DEALLOC 0x0000000CU 2786 #define LRFDPBE_FCFG5_DMAREQ_TXFIFO_RESET 0x0000000BU 2787 #define LRFDPBE_FCFG5_DMAREQ_TXWRBTHR_MET 0x0000000AU 2788 #define LRFDPBE_FCFG5_DMAREQ_TXRDBTHR_MET 0x00000009U 2789 #define LRFDPBE_FCFG5_DMAREQ_RXFIFO_COMMIT 0x00000007U 2790 #define LRFDPBE_FCFG5_DMAREQ_RXFIFO_DISCARD 0x00000006U 2791 #define LRFDPBE_FCFG5_DMAREQ_RXFIFO_RETRY 0x00000005U 2792 #define LRFDPBE_FCFG5_DMAREQ_RXFIFO_DEALLOC 0x00000004U 2793 #define LRFDPBE_FCFG5_DMAREQ_RXFIFO_RESET 0x00000003U 2794 #define LRFDPBE_FCFG5_DMAREQ_RXWRBTHR_MET 0x00000002U 2795 #define LRFDPBE_FCFG5_DMAREQ_RXRDBTHR_MET 0x00000001U 2796 #define LRFDPBE_FCFG5_DMAREQ_NONE 0x00000000U 2797 2798 //***************************************************************************** 2799 // 2800 // Register: LRFDPBE_O_RXFWBTHRS 2801 // 2802 //***************************************************************************** 2803 // Field: [9:0] BYTES 2804 // 2805 // ENUMs: 2806 // ALLONES All the bits are 1 2807 // ALLZEROS All the bits are 0 2808 #define LRFDPBE_RXFWBTHRS_BYTES_W 10U 2809 #define LRFDPBE_RXFWBTHRS_BYTES_M 0x000003FFU 2810 #define LRFDPBE_RXFWBTHRS_BYTES_S 0U 2811 #define LRFDPBE_RXFWBTHRS_BYTES_ALLONES 0x000003FFU 2812 #define LRFDPBE_RXFWBTHRS_BYTES_ALLZEROS 0x00000000U 2813 2814 //***************************************************************************** 2815 // 2816 // Register: LRFDPBE_O_RXFRBTHRS 2817 // 2818 //***************************************************************************** 2819 // Field: [9:0] BYTES 2820 // 2821 // ENUMs: 2822 // ALLONES All the bits are 1 2823 // ALLZEROS All the bits are 0 2824 #define LRFDPBE_RXFRBTHRS_BYTES_W 10U 2825 #define LRFDPBE_RXFRBTHRS_BYTES_M 0x000003FFU 2826 #define LRFDPBE_RXFRBTHRS_BYTES_S 0U 2827 #define LRFDPBE_RXFRBTHRS_BYTES_ALLONES 0x000003FFU 2828 #define LRFDPBE_RXFRBTHRS_BYTES_ALLZEROS 0x00000000U 2829 2830 //***************************************************************************** 2831 // 2832 // Register: LRFDPBE_O_TXFWBTHRS 2833 // 2834 //***************************************************************************** 2835 // Field: [9:0] BYTES 2836 // 2837 // ENUMs: 2838 // ALLONES All the bits are 1 2839 // ALLZEROS All the bits are 0 2840 #define LRFDPBE_TXFWBTHRS_BYTES_W 10U 2841 #define LRFDPBE_TXFWBTHRS_BYTES_M 0x000003FFU 2842 #define LRFDPBE_TXFWBTHRS_BYTES_S 0U 2843 #define LRFDPBE_TXFWBTHRS_BYTES_ALLONES 0x000003FFU 2844 #define LRFDPBE_TXFWBTHRS_BYTES_ALLZEROS 0x00000000U 2845 2846 //***************************************************************************** 2847 // 2848 // Register: LRFDPBE_O_TXFRBTHRS 2849 // 2850 //***************************************************************************** 2851 // Field: [9:0] BYTES 2852 // 2853 // ENUMs: 2854 // ALLONES All the bits are 1 2855 // ALLZEROS All the bits are 0 2856 #define LRFDPBE_TXFRBTHRS_BYTES_W 10U 2857 #define LRFDPBE_TXFRBTHRS_BYTES_M 0x000003FFU 2858 #define LRFDPBE_TXFRBTHRS_BYTES_S 0U 2859 #define LRFDPBE_TXFRBTHRS_BYTES_ALLONES 0x000003FFU 2860 #define LRFDPBE_TXFRBTHRS_BYTES_ALLZEROS 0x00000000U 2861 2862 //***************************************************************************** 2863 // 2864 // Register: LRFDPBE_O_TIMCTL 2865 // 2866 //***************************************************************************** 2867 // Field: [15:11] CPTSRC1 2868 // 2869 // Selects bit number from event bus to use for a counter capture. Event number 2870 // in range 0 to 31 2871 // ENUMs: 2872 // ALLONES All the bits are 1 2873 // ALLZEROS All the bits are 0 2874 #define LRFDPBE_TIMCTL_CPTSRC1_W 5U 2875 #define LRFDPBE_TIMCTL_CPTSRC1_M 0x0000F800U 2876 #define LRFDPBE_TIMCTL_CPTSRC1_S 11U 2877 #define LRFDPBE_TIMCTL_CPTSRC1_ALLONES 0x0000F800U 2878 #define LRFDPBE_TIMCTL_CPTSRC1_ALLZEROS 0x00000000U 2879 2880 // Field: [10] ENCPT1 2881 // 2882 // Enable timer capture on event. Upon a capture event, the timer value will be 2883 // captured in TIMCAPT register. The timer value can always be captured using 2884 // the STROBES0.TIMCAPT1 2885 // ENUMs: 2886 // ON Enable capture mode for counter 2887 // OFF Disable capture mode for counter 2888 #define LRFDPBE_TIMCTL_ENCPT1 0x00000400U 2889 #define LRFDPBE_TIMCTL_ENCPT1_M 0x00000400U 2890 #define LRFDPBE_TIMCTL_ENCPT1_S 10U 2891 #define LRFDPBE_TIMCTL_ENCPT1_ON 0x00000400U 2892 #define LRFDPBE_TIMCTL_ENCPT1_OFF 0x00000000U 2893 2894 // Field: [9] SRC1 2895 // 2896 // Select timer tick source for timer 2897 // ENUMs: 2898 // PRE1 Use magnitude estimator 0 data enable 2899 // CLK Use clock 2900 #define LRFDPBE_TIMCTL_SRC1 0x00000200U 2901 #define LRFDPBE_TIMCTL_SRC1_M 0x00000200U 2902 #define LRFDPBE_TIMCTL_SRC1_S 9U 2903 #define LRFDPBE_TIMCTL_SRC1_PRE1 0x00000200U 2904 #define LRFDPBE_TIMCTL_SRC1_CLK 0x00000000U 2905 2906 // Field: [8] EN1 2907 // 2908 // Enable 16-bit timer1. It will generate a timer interrupt after TIMPER1 timer 2909 // ticks. 2910 // ENUMs: 2911 // ON Will enable timer 2912 // OFF Will disable timer and clear internal timer value 2913 #define LRFDPBE_TIMCTL_EN1 0x00000100U 2914 #define LRFDPBE_TIMCTL_EN1_M 0x00000100U 2915 #define LRFDPBE_TIMCTL_EN1_S 8U 2916 #define LRFDPBE_TIMCTL_EN1_ON 0x00000100U 2917 #define LRFDPBE_TIMCTL_EN1_OFF 0x00000000U 2918 2919 // Field: [7:3] CPTSRC0 2920 // 2921 // Selects bit number from event bus to use for a counter capture. Event number 2922 // in range 0 to 31 2923 // ENUMs: 2924 // ALLONES All the bits are 1 2925 // ALLZEROS All the bits are 0 2926 #define LRFDPBE_TIMCTL_CPTSRC0_W 5U 2927 #define LRFDPBE_TIMCTL_CPTSRC0_M 0x000000F8U 2928 #define LRFDPBE_TIMCTL_CPTSRC0_S 3U 2929 #define LRFDPBE_TIMCTL_CPTSRC0_ALLONES 0x000000F8U 2930 #define LRFDPBE_TIMCTL_CPTSRC0_ALLZEROS 0x00000000U 2931 2932 // Field: [2] ENCPT0 2933 // 2934 // Enable timer capture on event. Upon a capture event, the timer value will be 2935 // captured in TIMCAPT register. The timer value can always be captured using 2936 // the STROBES0.TIMCAPT0 2937 // ENUMs: 2938 // ON Enable capture mode for counter 2939 // OFF Disable capture mode for counter 2940 #define LRFDPBE_TIMCTL_ENCPT0 0x00000004U 2941 #define LRFDPBE_TIMCTL_ENCPT0_M 0x00000004U 2942 #define LRFDPBE_TIMCTL_ENCPT0_S 2U 2943 #define LRFDPBE_TIMCTL_ENCPT0_ON 0x00000004U 2944 #define LRFDPBE_TIMCTL_ENCPT0_OFF 0x00000000U 2945 2946 // Field: [1] SRC0 2947 // 2948 // Select timer tick source for timer 2949 // ENUMs: 2950 // PRE0 Use magnitude estimator 0 data enable 2951 // CLK Use clock 2952 #define LRFDPBE_TIMCTL_SRC0 0x00000002U 2953 #define LRFDPBE_TIMCTL_SRC0_M 0x00000002U 2954 #define LRFDPBE_TIMCTL_SRC0_S 1U 2955 #define LRFDPBE_TIMCTL_SRC0_PRE0 0x00000002U 2956 #define LRFDPBE_TIMCTL_SRC0_CLK 0x00000000U 2957 2958 // Field: [0] EN0 2959 // 2960 // Enable 16-bit timer0. It will generate a timer interrupt after TIMPER0 timer 2961 // ticks. Note that the internal timer value is not readable from the PBE. 2962 // ENUMs: 2963 // ON Will enable timer 2964 // OFF Will disable timer and clear internal timer value 2965 #define LRFDPBE_TIMCTL_EN0 0x00000001U 2966 #define LRFDPBE_TIMCTL_EN0_M 0x00000001U 2967 #define LRFDPBE_TIMCTL_EN0_S 0U 2968 #define LRFDPBE_TIMCTL_EN0_ON 0x00000001U 2969 #define LRFDPBE_TIMCTL_EN0_OFF 0x00000000U 2970 2971 //***************************************************************************** 2972 // 2973 // Register: LRFDPBE_O_TIMPRE 2974 // 2975 //***************************************************************************** 2976 // Field: [13:8] PRE1 2977 // 2978 // Prescaler setting for timer 1, timer speed will be reduced to clk/(PRE1+1) 2979 // ENUMs: 2980 // DIV64 DIV64 mode 2981 // NO_DIV No prescaling 2982 #define LRFDPBE_TIMPRE_PRE1_W 6U 2983 #define LRFDPBE_TIMPRE_PRE1_M 0x00003F00U 2984 #define LRFDPBE_TIMPRE_PRE1_S 8U 2985 #define LRFDPBE_TIMPRE_PRE1_DIV64 0x00003F00U 2986 #define LRFDPBE_TIMPRE_PRE1_NO_DIV 0x00000000U 2987 2988 // Field: [5:0] PRE0 2989 // 2990 // Prescaler setting for timer 0, timer speed will be reduced to clk/(PRE0+1) 2991 // ENUMs: 2992 // DIV64 DIV64 mode 2993 // NO_DIV No prescaling 2994 #define LRFDPBE_TIMPRE_PRE0_W 6U 2995 #define LRFDPBE_TIMPRE_PRE0_M 0x0000003FU 2996 #define LRFDPBE_TIMPRE_PRE0_S 0U 2997 #define LRFDPBE_TIMPRE_PRE0_DIV64 0x0000003FU 2998 #define LRFDPBE_TIMPRE_PRE0_NO_DIV 0x00000000U 2999 3000 //***************************************************************************** 3001 // 3002 // Register: LRFDPBE_O_TIMPER0 3003 // 3004 //***************************************************************************** 3005 // Field: [15:0] VAL 3006 // 3007 // Configurable 16 bit period that can be used for either the timer or the 3008 // counter. In timer context, when timer value reach the timer period (i.e. it 3009 // expires) a TIMER_IRQ event will occur, and the timer will restart from zero 3010 // (until the timer is manually disabled). In counter context, a COUNTER_IRQ 3011 // event will occur when the counter is equal to or higher than the period 3012 // value. 3013 // ENUMs: 3014 // ALLONES All the bits are 1 3015 // ALLZEROS All the bits are 0 3016 #define LRFDPBE_TIMPER0_VAL_W 16U 3017 #define LRFDPBE_TIMPER0_VAL_M 0x0000FFFFU 3018 #define LRFDPBE_TIMPER0_VAL_S 0U 3019 #define LRFDPBE_TIMPER0_VAL_ALLONES 0x0000FFFFU 3020 #define LRFDPBE_TIMPER0_VAL_ALLZEROS 0x00000000U 3021 3022 //***************************************************************************** 3023 // 3024 // Register: LRFDPBE_O_TIMPER1 3025 // 3026 //***************************************************************************** 3027 // Field: [15:0] VAL 3028 // 3029 // Configurable 16 bit period that can be used for either the timer or the 3030 // counter. In timer context, when timer value reach the timer period (i.e. it 3031 // expires) a TIMER_IRQ event will occur, and the timer will restart from zero 3032 // (until the timer is manually disabled). In counter context, a COUNTER_IRQ 3033 // event will occur when the counter is equal to or higher than the period 3034 // value. 3035 // ENUMs: 3036 // ALLONES All the bits are 1 3037 // ALLZEROS All the bits are 0 3038 #define LRFDPBE_TIMPER1_VAL_W 16U 3039 #define LRFDPBE_TIMPER1_VAL_M 0x0000FFFFU 3040 #define LRFDPBE_TIMPER1_VAL_S 0U 3041 #define LRFDPBE_TIMPER1_VAL_ALLONES 0x0000FFFFU 3042 #define LRFDPBE_TIMPER1_VAL_ALLZEROS 0x00000000U 3043 3044 //***************************************************************************** 3045 // 3046 // Register: LRFDPBE_O_TIMCAPT0 3047 // 3048 //***************************************************************************** 3049 // Field: [15:0] VALUE 3050 // 3051 // Captured value of counter 3052 // ENUMs: 3053 // ALLONES All the bits are 1 3054 // ALLZEROS All the bits are 0 3055 #define LRFDPBE_TIMCAPT0_VALUE_W 16U 3056 #define LRFDPBE_TIMCAPT0_VALUE_M 0x0000FFFFU 3057 #define LRFDPBE_TIMCAPT0_VALUE_S 0U 3058 #define LRFDPBE_TIMCAPT0_VALUE_ALLONES 0x0000FFFFU 3059 #define LRFDPBE_TIMCAPT0_VALUE_ALLZEROS 0x00000000U 3060 3061 //***************************************************************************** 3062 // 3063 // Register: LRFDPBE_O_TIMCAPT1 3064 // 3065 //***************************************************************************** 3066 // Field: [15:0] VALUE 3067 // 3068 // Captured value of counter 3069 // ENUMs: 3070 // ALLONES All the bits are 1 3071 // ALLZEROS All the bits are 0 3072 #define LRFDPBE_TIMCAPT1_VALUE_W 16U 3073 #define LRFDPBE_TIMCAPT1_VALUE_M 0x0000FFFFU 3074 #define LRFDPBE_TIMCAPT1_VALUE_S 0U 3075 #define LRFDPBE_TIMCAPT1_VALUE_ALLONES 0x0000FFFFU 3076 #define LRFDPBE_TIMCAPT1_VALUE_ALLZEROS 0x00000000U 3077 3078 //***************************************************************************** 3079 // 3080 // Register: LRFDPBE_O_TRCCTL 3081 // 3082 //***************************************************************************** 3083 // Field: [0] SEND 3084 // 3085 // Sends a command to the tracer 3086 // ENUMs: 3087 // ONE The bit is 1 3088 // ZERO The bit is 0 3089 #define LRFDPBE_TRCCTL_SEND 0x00000001U 3090 #define LRFDPBE_TRCCTL_SEND_M 0x00000001U 3091 #define LRFDPBE_TRCCTL_SEND_S 0U 3092 #define LRFDPBE_TRCCTL_SEND_ONE 0x00000001U 3093 #define LRFDPBE_TRCCTL_SEND_ZERO 0x00000000U 3094 3095 //***************************************************************************** 3096 // 3097 // Register: LRFDPBE_O_TRCSTAT 3098 // 3099 //***************************************************************************** 3100 // Field: [0] BUSY 3101 // 3102 // Checks if the tracer is busy 3103 // ENUMs: 3104 // ONE The bit is 1 3105 // ZERO The bit is 0 3106 #define LRFDPBE_TRCSTAT_BUSY 0x00000001U 3107 #define LRFDPBE_TRCSTAT_BUSY_M 0x00000001U 3108 #define LRFDPBE_TRCSTAT_BUSY_S 0U 3109 #define LRFDPBE_TRCSTAT_BUSY_ONE 0x00000001U 3110 #define LRFDPBE_TRCSTAT_BUSY_ZERO 0x00000000U 3111 3112 //***************************************************************************** 3113 // 3114 // Register: LRFDPBE_O_TRCCMD 3115 // 3116 //***************************************************************************** 3117 // Field: [9:8] PARCNT 3118 // 3119 // Number of parameters 3120 // ENUMs: 3121 // ALLONES All the bits are 1 3122 // ALLZEROS All the bits are 0 3123 #define LRFDPBE_TRCCMD_PARCNT_W 2U 3124 #define LRFDPBE_TRCCMD_PARCNT_M 0x00000300U 3125 #define LRFDPBE_TRCCMD_PARCNT_S 8U 3126 #define LRFDPBE_TRCCMD_PARCNT_ALLONES 0x00000300U 3127 #define LRFDPBE_TRCCMD_PARCNT_ALLZEROS 0x00000000U 3128 3129 // Field: [7:0] PKTHDR 3130 // 3131 // Packet header 3132 // ENUMs: 3133 // ALLONES All the bits are 1 3134 // ALLZEROS All the bits are 0 3135 #define LRFDPBE_TRCCMD_PKTHDR_W 8U 3136 #define LRFDPBE_TRCCMD_PKTHDR_M 0x000000FFU 3137 #define LRFDPBE_TRCCMD_PKTHDR_S 0U 3138 #define LRFDPBE_TRCCMD_PKTHDR_ALLONES 0x000000FFU 3139 #define LRFDPBE_TRCCMD_PKTHDR_ALLZEROS 0x00000000U 3140 3141 //***************************************************************************** 3142 // 3143 // Register: LRFDPBE_O_TRCPAR0 3144 // 3145 //***************************************************************************** 3146 // Field: [15:0] VAL 3147 // 3148 // Parameter 0 3149 // ENUMs: 3150 // ALLONES All the bits are 1 3151 // ALLZEROS All the bits are 0 3152 #define LRFDPBE_TRCPAR0_VAL_W 16U 3153 #define LRFDPBE_TRCPAR0_VAL_M 0x0000FFFFU 3154 #define LRFDPBE_TRCPAR0_VAL_S 0U 3155 #define LRFDPBE_TRCPAR0_VAL_ALLONES 0x0000FFFFU 3156 #define LRFDPBE_TRCPAR0_VAL_ALLZEROS 0x00000000U 3157 3158 //***************************************************************************** 3159 // 3160 // Register: LRFDPBE_O_TRCPAR1 3161 // 3162 //***************************************************************************** 3163 // Field: [15:0] VAL 3164 // 3165 // Parameter 1 3166 // ENUMs: 3167 // ALLONES All the bits are 1 3168 // ALLZEROS All the bits are 0 3169 #define LRFDPBE_TRCPAR1_VAL_W 16U 3170 #define LRFDPBE_TRCPAR1_VAL_M 0x0000FFFFU 3171 #define LRFDPBE_TRCPAR1_VAL_S 0U 3172 #define LRFDPBE_TRCPAR1_VAL_ALLONES 0x0000FFFFU 3173 #define LRFDPBE_TRCPAR1_VAL_ALLZEROS 0x00000000U 3174 3175 //***************************************************************************** 3176 // 3177 // Register: LRFDPBE_O_GPOCTRL 3178 // 3179 //***************************************************************************** 3180 // Field: [7] GPO7 3181 // 3182 // Control GPO7 3183 // ENUMs: 3184 // ONE The bit is 1 3185 // ZERO The bit is 0 3186 #define LRFDPBE_GPOCTRL_GPO7 0x00000080U 3187 #define LRFDPBE_GPOCTRL_GPO7_M 0x00000080U 3188 #define LRFDPBE_GPOCTRL_GPO7_S 7U 3189 #define LRFDPBE_GPOCTRL_GPO7_ONE 0x00000080U 3190 #define LRFDPBE_GPOCTRL_GPO7_ZERO 0x00000000U 3191 3192 // Field: [6] GPO6 3193 // 3194 // Control GPO6 3195 // ENUMs: 3196 // ONE The bit is 1 3197 // ZERO The bit is 0 3198 #define LRFDPBE_GPOCTRL_GPO6 0x00000040U 3199 #define LRFDPBE_GPOCTRL_GPO6_M 0x00000040U 3200 #define LRFDPBE_GPOCTRL_GPO6_S 6U 3201 #define LRFDPBE_GPOCTRL_GPO6_ONE 0x00000040U 3202 #define LRFDPBE_GPOCTRL_GPO6_ZERO 0x00000000U 3203 3204 // Field: [5] GPO5 3205 // 3206 // Control GPO5 3207 // ENUMs: 3208 // ONE The bit is 1 3209 // ZERO The bit is 0 3210 #define LRFDPBE_GPOCTRL_GPO5 0x00000020U 3211 #define LRFDPBE_GPOCTRL_GPO5_M 0x00000020U 3212 #define LRFDPBE_GPOCTRL_GPO5_S 5U 3213 #define LRFDPBE_GPOCTRL_GPO5_ONE 0x00000020U 3214 #define LRFDPBE_GPOCTRL_GPO5_ZERO 0x00000000U 3215 3216 // Field: [4] GPO4 3217 // 3218 // Control GPO4 3219 // ENUMs: 3220 // ONE The bit is 1 3221 // ZERO The bit is 0 3222 #define LRFDPBE_GPOCTRL_GPO4 0x00000010U 3223 #define LRFDPBE_GPOCTRL_GPO4_M 0x00000010U 3224 #define LRFDPBE_GPOCTRL_GPO4_S 4U 3225 #define LRFDPBE_GPOCTRL_GPO4_ONE 0x00000010U 3226 #define LRFDPBE_GPOCTRL_GPO4_ZERO 0x00000000U 3227 3228 // Field: [3] GPO3 3229 // 3230 // Control GPO3 3231 // ENUMs: 3232 // ONE The bit is 1 3233 // ZERO The bit is 0 3234 #define LRFDPBE_GPOCTRL_GPO3 0x00000008U 3235 #define LRFDPBE_GPOCTRL_GPO3_M 0x00000008U 3236 #define LRFDPBE_GPOCTRL_GPO3_S 3U 3237 #define LRFDPBE_GPOCTRL_GPO3_ONE 0x00000008U 3238 #define LRFDPBE_GPOCTRL_GPO3_ZERO 0x00000000U 3239 3240 // Field: [2] GPO2 3241 // 3242 // Control GPO2 3243 // ENUMs: 3244 // ONE The bit is 1 3245 // ZERO The bit is 0 3246 #define LRFDPBE_GPOCTRL_GPO2 0x00000004U 3247 #define LRFDPBE_GPOCTRL_GPO2_M 0x00000004U 3248 #define LRFDPBE_GPOCTRL_GPO2_S 2U 3249 #define LRFDPBE_GPOCTRL_GPO2_ONE 0x00000004U 3250 #define LRFDPBE_GPOCTRL_GPO2_ZERO 0x00000000U 3251 3252 // Field: [1] GPO1 3253 // 3254 // Control GPO1 3255 // ENUMs: 3256 // ONE The bit is 1 3257 // ZERO The bit is 0 3258 #define LRFDPBE_GPOCTRL_GPO1 0x00000002U 3259 #define LRFDPBE_GPOCTRL_GPO1_M 0x00000002U 3260 #define LRFDPBE_GPOCTRL_GPO1_S 1U 3261 #define LRFDPBE_GPOCTRL_GPO1_ONE 0x00000002U 3262 #define LRFDPBE_GPOCTRL_GPO1_ZERO 0x00000000U 3263 3264 // Field: [0] GPO0 3265 // 3266 // Control GPO0 3267 // ENUMs: 3268 // ONE The bit is 1 3269 // ZERO The bit is 0 3270 #define LRFDPBE_GPOCTRL_GPO0 0x00000001U 3271 #define LRFDPBE_GPOCTRL_GPO0_M 0x00000001U 3272 #define LRFDPBE_GPOCTRL_GPO0_S 0U 3273 #define LRFDPBE_GPOCTRL_GPO0_ONE 0x00000001U 3274 #define LRFDPBE_GPOCTRL_GPO0_ZERO 0x00000000U 3275 3276 //***************************************************************************** 3277 // 3278 // Register: LRFDPBE_O_MDMFWR 3279 // 3280 //***************************************************************************** 3281 // Field: [15:0] PAYLOADIN 3282 // 3283 // FIFO write port. The actual port size is configurable in LRFDMDM:FIFOWRCTRL. 3284 // ENUMs: 3285 // ALLONES All the bits are 1 3286 // ALLZEROS All the bits are 0 3287 #define LRFDPBE_MDMFWR_PAYLOADIN_W 16U 3288 #define LRFDPBE_MDMFWR_PAYLOADIN_M 0x0000FFFFU 3289 #define LRFDPBE_MDMFWR_PAYLOADIN_S 0U 3290 #define LRFDPBE_MDMFWR_PAYLOADIN_ALLONES 0x0000FFFFU 3291 #define LRFDPBE_MDMFWR_PAYLOADIN_ALLZEROS 0x00000000U 3292 3293 //***************************************************************************** 3294 // 3295 // Register: LRFDPBE_O_MDMFRD 3296 // 3297 //***************************************************************************** 3298 // Field: [15:0] PAYLOADOUT 3299 // 3300 // FIFO read port. The actual port size is configurable in LRFDMDM:FIFORDCTRL. 3301 // A new value is read by writing LRFDMDM:FIFOWR.PAYLOADIN. 3302 // ENUMs: 3303 // ALLONES All the bits are 1 3304 // ALLZEROS All the bits are 0 3305 #define LRFDPBE_MDMFRD_PAYLOADOUT_W 16U 3306 #define LRFDPBE_MDMFRD_PAYLOADOUT_M 0x0000FFFFU 3307 #define LRFDPBE_MDMFRD_PAYLOADOUT_S 0U 3308 #define LRFDPBE_MDMFRD_PAYLOADOUT_ALLONES 0x0000FFFFU 3309 #define LRFDPBE_MDMFRD_PAYLOADOUT_ALLZEROS 0x00000000U 3310 3311 //***************************************************************************** 3312 // 3313 // Register: LRFDPBE_O_MDMFWRCTL 3314 // 3315 //***************************************************************************** 3316 // Field: [3:0] WORDSZWR 3317 // 3318 // Actual bits in every word write access 3319 // ENUMs: 3320 // BITS16 16 bits 3321 // BITS15 15 bits 3322 // BITS14 14 bits 3323 // BITS13 13 bits 3324 // BITS12 12 bits 3325 // BITS11 11 bits 3326 // BITS10 10 bits 3327 // BITS9 9 bits 3328 // BITS8 8 bits 3329 // BITS7 7 bits 3330 // BITS6 6 bits 3331 // BITS5 5 bits 3332 // BITS4 4 bits 3333 // BITS3 3 bits 3334 // BITS2 2 bits 3335 // BITS1 1 bit 3336 #define LRFDPBE_MDMFWRCTL_WORDSZWR_W 4U 3337 #define LRFDPBE_MDMFWRCTL_WORDSZWR_M 0x0000000FU 3338 #define LRFDPBE_MDMFWRCTL_WORDSZWR_S 0U 3339 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS16 0x0000000FU 3340 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS15 0x0000000EU 3341 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS14 0x0000000DU 3342 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS13 0x0000000CU 3343 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS12 0x0000000BU 3344 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS11 0x0000000AU 3345 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS10 0x00000009U 3346 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS9 0x00000008U 3347 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS8 0x00000007U 3348 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS7 0x00000006U 3349 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS6 0x00000005U 3350 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS5 0x00000004U 3351 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS4 0x00000003U 3352 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS3 0x00000002U 3353 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS2 0x00000001U 3354 #define LRFDPBE_MDMFWRCTL_WORDSZWR_BITS1 0x00000000U 3355 3356 //***************************************************************************** 3357 // 3358 // Register: LRFDPBE_O_MDMFRDCTL 3359 // 3360 //***************************************************************************** 3361 // Field: [3:0] WORDSZRD 3362 // 3363 // Actual bits in every word read access 3364 // ENUMs: 3365 // BITS16 16 bits 3366 // BITS15 15 bits 3367 // BITS14 14 bits 3368 // BITS13 13 bits 3369 // BITS12 12 bits 3370 // BITS11 11 bits 3371 // BITS10 10 bits 3372 // BITS9 9 bits 3373 // BITS8 8 bits 3374 // BITS7 7 bits 3375 // BITS6 6 bits 3376 // BITS5 5 bits 3377 // BITS4 4 bits 3378 // BITS3 3 bits 3379 // BITS2 2 bits 3380 // BITS1 1 bit 3381 #define LRFDPBE_MDMFRDCTL_WORDSZRD_W 4U 3382 #define LRFDPBE_MDMFRDCTL_WORDSZRD_M 0x0000000FU 3383 #define LRFDPBE_MDMFRDCTL_WORDSZRD_S 0U 3384 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS16 0x0000000FU 3385 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS15 0x0000000EU 3386 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS14 0x0000000DU 3387 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS13 0x0000000CU 3388 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS12 0x0000000BU 3389 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS11 0x0000000AU 3390 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS10 0x00000009U 3391 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS9 0x00000008U 3392 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS8 0x00000007U 3393 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS7 0x00000006U 3394 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS6 0x00000005U 3395 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS5 0x00000004U 3396 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS4 0x00000003U 3397 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS3 0x00000002U 3398 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS2 0x00000001U 3399 #define LRFDPBE_MDMFRDCTL_WORDSZRD_BITS1 0x00000000U 3400 3401 //***************************************************************************** 3402 // 3403 // Register: LRFDPBE_O_MDMFCFG 3404 // 3405 //***************************************************************************** 3406 // Field: [15:8] AFULLTHR 3407 // 3408 // Almost full threshold value in bits. This threshold affects the 3409 // LRFDMDM:FIFOSTA.ALMOSTFULL and LRFDMDM:FIFOSTA.TXREADY status bits. The FIFO 3410 // can hold up to 64 bits. 3411 // ENUMs: 3412 // ALLONES All the bits are 1 3413 // ALLZEROS All the bits are 0 3414 #define LRFDPBE_MDMFCFG_AFULLTHR_W 8U 3415 #define LRFDPBE_MDMFCFG_AFULLTHR_M 0x0000FF00U 3416 #define LRFDPBE_MDMFCFG_AFULLTHR_S 8U 3417 #define LRFDPBE_MDMFCFG_AFULLTHR_ALLONES 0x0000FF00U 3418 #define LRFDPBE_MDMFCFG_AFULLTHR_ALLZEROS 0x00000000U 3419 3420 // Field: [7:0] AEMPTYTHR 3421 // 3422 // Almost empty threshold in bits. This threshold affects the 3423 // LRFDMDM:FIFOSTA.ALMOSTEMPTY and LRFDMDM:FIFOSTA.RXVALID status bits. The 3424 // FIFO can hold up to 64 bits. 3425 // ENUMs: 3426 // ALLONES All the bits are 1 3427 // ALLZEROS All the bits are 0 3428 #define LRFDPBE_MDMFCFG_AEMPTYTHR_W 8U 3429 #define LRFDPBE_MDMFCFG_AEMPTYTHR_M 0x000000FFU 3430 #define LRFDPBE_MDMFCFG_AEMPTYTHR_S 0U 3431 #define LRFDPBE_MDMFCFG_AEMPTYTHR_ALLONES 0x000000FFU 3432 #define LRFDPBE_MDMFCFG_AEMPTYTHR_ALLZEROS 0x00000000U 3433 3434 //***************************************************************************** 3435 // 3436 // Register: LRFDPBE_O_MDMFSTA 3437 // 3438 //***************************************************************************** 3439 // Field: [5] OVFL 3440 // 3441 // FIFO overflow error. If this flag is asserted the modem FIFO must be 3442 // re-initialized with LRFDMDM:INIT.TXRXFIFO to clear it. Note that 3443 // re-initializing will flush the FIFO. 3444 // ENUMs: 3445 // ONE The bit is 1 3446 // ZERO The bit is 0 3447 #define LRFDPBE_MDMFSTA_OVFL 0x00000020U 3448 #define LRFDPBE_MDMFSTA_OVFL_M 0x00000020U 3449 #define LRFDPBE_MDMFSTA_OVFL_S 5U 3450 #define LRFDPBE_MDMFSTA_OVFL_ONE 0x00000020U 3451 #define LRFDPBE_MDMFSTA_OVFL_ZERO 0x00000000U 3452 3453 // Field: [4] ALMOSTFULL 3454 // 3455 // FIFO is almost full. Asserts when the FIFO fill level is above the almost 3456 // full threshold. 3457 // ENUMs: 3458 // ONE The bit is 1 3459 // ZERO The bit is 0 3460 #define LRFDPBE_MDMFSTA_ALMOSTFULL 0x00000010U 3461 #define LRFDPBE_MDMFSTA_ALMOSTFULL_M 0x00000010U 3462 #define LRFDPBE_MDMFSTA_ALMOSTFULL_S 4U 3463 #define LRFDPBE_MDMFSTA_ALMOSTFULL_ONE 0x00000010U 3464 #define LRFDPBE_MDMFSTA_ALMOSTFULL_ZERO 0x00000000U 3465 3466 // Field: [3] ALMOSTEMPTY 3467 // 3468 // FIFO is almost empty. Asserts when the FIFO fill level is below the almost 3469 // empty threshold. 3470 // ENUMs: 3471 // ONE The bit is 1 3472 // ZERO The bit is 0 3473 #define LRFDPBE_MDMFSTA_ALMOSTEMPTY 0x00000008U 3474 #define LRFDPBE_MDMFSTA_ALMOSTEMPTY_M 0x00000008U 3475 #define LRFDPBE_MDMFSTA_ALMOSTEMPTY_S 3U 3476 #define LRFDPBE_MDMFSTA_ALMOSTEMPTY_ONE 0x00000008U 3477 #define LRFDPBE_MDMFSTA_ALMOSTEMPTY_ZERO 0x00000000U 3478 3479 // Field: [2] UNFL 3480 // 3481 // FIFO underflow error. If this flag is asserted the modem FIFO must be 3482 // re-initialized with LRFDMDM:INIT.TXRXFIFO to clear it. 3483 // ENUMs: 3484 // ONE The bit is 1 3485 // ZERO The bit is 0 3486 #define LRFDPBE_MDMFSTA_UNFL 0x00000004U 3487 #define LRFDPBE_MDMFSTA_UNFL_M 0x00000004U 3488 #define LRFDPBE_MDMFSTA_UNFL_S 2U 3489 #define LRFDPBE_MDMFSTA_UNFL_ONE 0x00000004U 3490 #define LRFDPBE_MDMFSTA_UNFL_ZERO 0x00000000U 3491 3492 // Field: [1] RXVALID 3493 // 3494 // A full data word is valid and can be read in LRFDMDM:FIFORD register read 3495 // port. 3496 // ENUMs: 3497 // ONE The bit is 1 3498 // ZERO The bit is 0 3499 #define LRFDPBE_MDMFSTA_RXVALID 0x00000002U 3500 #define LRFDPBE_MDMFSTA_RXVALID_M 0x00000002U 3501 #define LRFDPBE_MDMFSTA_RXVALID_S 1U 3502 #define LRFDPBE_MDMFSTA_RXVALID_ONE 0x00000002U 3503 #define LRFDPBE_MDMFSTA_RXVALID_ZERO 0x00000000U 3504 3505 // Field: [0] TXREADY 3506 // 3507 // The LRFDMDM:FIFOWR register write port is ready to receive a data word. 3508 // ENUMs: 3509 // ONE The bit is 1 3510 // ZERO The bit is 0 3511 #define LRFDPBE_MDMFSTA_TXREADY 0x00000001U 3512 #define LRFDPBE_MDMFSTA_TXREADY_M 0x00000001U 3513 #define LRFDPBE_MDMFSTA_TXREADY_S 0U 3514 #define LRFDPBE_MDMFSTA_TXREADY_ONE 0x00000001U 3515 #define LRFDPBE_MDMFSTA_TXREADY_ZERO 0x00000000U 3516 3517 //***************************************************************************** 3518 // 3519 // Register: LRFDPBE_O_PHASTA 3520 // 3521 //***************************************************************************** 3522 // Field: [1:0] BUSY 3523 // 3524 // Status busy flags. 3525 // ENUMs: 3526 // BUSY LFSR n sub-engine busy 3527 // IDLE LFSR n sub-engine idle 3528 #define LRFDPBE_PHASTA_BUSY_W 2U 3529 #define LRFDPBE_PHASTA_BUSY_M 0x00000003U 3530 #define LRFDPBE_PHASTA_BUSY_S 0U 3531 #define LRFDPBE_PHASTA_BUSY_BUSY 0x00000001U 3532 #define LRFDPBE_PHASTA_BUSY_IDLE 0x00000000U 3533 3534 //***************************************************************************** 3535 // 3536 // Register: LRFDPBE_O_LFSR0L 3537 // 3538 //***************************************************************************** 3539 // Field: [15:0] VALLSB 3540 // 3541 // LFSR 0 low part value, bits 15:0 3542 // ENUMs: 3543 // ALLONES All the bits are 1 3544 // ALLZEROS All the bits are 0 3545 #define LRFDPBE_LFSR0L_VALLSB_W 16U 3546 #define LRFDPBE_LFSR0L_VALLSB_M 0x0000FFFFU 3547 #define LRFDPBE_LFSR0L_VALLSB_S 0U 3548 #define LRFDPBE_LFSR0L_VALLSB_ALLONES 0x0000FFFFU 3549 #define LRFDPBE_LFSR0L_VALLSB_ALLZEROS 0x00000000U 3550 3551 //***************************************************************************** 3552 // 3553 // Register: LRFDPBE_O_LFSR0H 3554 // 3555 //***************************************************************************** 3556 // Field: [15:0] VALMSB 3557 // 3558 // LFSR 0 high part value, bits 31:16 3559 // ENUMs: 3560 // ALLONES All the bits are 1 3561 // ALLZEROS All the bits are 0 3562 #define LRFDPBE_LFSR0H_VALMSB_W 16U 3563 #define LRFDPBE_LFSR0H_VALMSB_M 0x0000FFFFU 3564 #define LRFDPBE_LFSR0H_VALMSB_S 0U 3565 #define LRFDPBE_LFSR0H_VALMSB_ALLONES 0x0000FFFFU 3566 #define LRFDPBE_LFSR0H_VALMSB_ALLZEROS 0x00000000U 3567 3568 //***************************************************************************** 3569 // 3570 // Register: LRFDPBE_O_LFSR0BRL 3571 // 3572 //***************************************************************************** 3573 // Field: [15:0] VALLSB 3574 // 3575 // LFSR 0 value, bit reversed order bits 15:0 3576 // ENUMs: 3577 // ALLONES All the bits are 1 3578 // ALLZEROS All the bits are 0 3579 #define LRFDPBE_LFSR0BRL_VALLSB_W 16U 3580 #define LRFDPBE_LFSR0BRL_VALLSB_M 0x0000FFFFU 3581 #define LRFDPBE_LFSR0BRL_VALLSB_S 0U 3582 #define LRFDPBE_LFSR0BRL_VALLSB_ALLONES 0x0000FFFFU 3583 #define LRFDPBE_LFSR0BRL_VALLSB_ALLZEROS 0x00000000U 3584 3585 //***************************************************************************** 3586 // 3587 // Register: LRFDPBE_O_LFSR0BRH 3588 // 3589 //***************************************************************************** 3590 // Field: [15:0] VALMSB 3591 // 3592 // LFSR 0 value, bit reversed order bits 31:16 3593 // ENUMs: 3594 // ALLONES All the bits are 1 3595 // ALLZEROS All the bits are 0 3596 #define LRFDPBE_LFSR0BRH_VALMSB_W 16U 3597 #define LRFDPBE_LFSR0BRH_VALMSB_M 0x0000FFFFU 3598 #define LRFDPBE_LFSR0BRH_VALMSB_S 0U 3599 #define LRFDPBE_LFSR0BRH_VALMSB_ALLONES 0x0000FFFFU 3600 #define LRFDPBE_LFSR0BRH_VALMSB_ALLZEROS 0x00000000U 3601 3602 //***************************************************************************** 3603 // 3604 // Register: LRFDPBE_O_LFSR1L 3605 // 3606 //***************************************************************************** 3607 // Field: [15:0] VALLSB 3608 // 3609 // LFSR 1 low part value, bits 15:0 3610 // ENUMs: 3611 // ALLONES All the bits are 1 3612 // ALLZEROS All the bits are 0 3613 #define LRFDPBE_LFSR1L_VALLSB_W 16U 3614 #define LRFDPBE_LFSR1L_VALLSB_M 0x0000FFFFU 3615 #define LRFDPBE_LFSR1L_VALLSB_S 0U 3616 #define LRFDPBE_LFSR1L_VALLSB_ALLONES 0x0000FFFFU 3617 #define LRFDPBE_LFSR1L_VALLSB_ALLZEROS 0x00000000U 3618 3619 //***************************************************************************** 3620 // 3621 // Register: LRFDPBE_O_LFSR1H 3622 // 3623 //***************************************************************************** 3624 // Field: [15:0] VALMSB 3625 // 3626 // LFSR 1 high part value, bits 31:16 3627 // ENUMs: 3628 // ALLONES All the bits are 1 3629 // ALLZEROS All the bits are 0 3630 #define LRFDPBE_LFSR1H_VALMSB_W 16U 3631 #define LRFDPBE_LFSR1H_VALMSB_M 0x0000FFFFU 3632 #define LRFDPBE_LFSR1H_VALMSB_S 0U 3633 #define LRFDPBE_LFSR1H_VALMSB_ALLONES 0x0000FFFFU 3634 #define LRFDPBE_LFSR1H_VALMSB_ALLZEROS 0x00000000U 3635 3636 //***************************************************************************** 3637 // 3638 // Register: LRFDPBE_O_LFSR1BRL 3639 // 3640 //***************************************************************************** 3641 // Field: [15:0] VALLSB 3642 // 3643 // LFSR 1 value, bit reversed order bits 15:0 3644 // ENUMs: 3645 // ALLONES All the bits are 1 3646 // ALLZEROS All the bits are 0 3647 #define LRFDPBE_LFSR1BRL_VALLSB_W 16U 3648 #define LRFDPBE_LFSR1BRL_VALLSB_M 0x0000FFFFU 3649 #define LRFDPBE_LFSR1BRL_VALLSB_S 0U 3650 #define LRFDPBE_LFSR1BRL_VALLSB_ALLONES 0x0000FFFFU 3651 #define LRFDPBE_LFSR1BRL_VALLSB_ALLZEROS 0x00000000U 3652 3653 //***************************************************************************** 3654 // 3655 // Register: LRFDPBE_O_LFSR1BRH 3656 // 3657 //***************************************************************************** 3658 // Field: [15:0] VALMSB 3659 // 3660 // LFSR 1 value, bit reversed order bits 31:16 3661 // ENUMs: 3662 // ALLONES All the bits are 1 3663 // ALLZEROS All the bits are 0 3664 #define LRFDPBE_LFSR1BRH_VALMSB_W 16U 3665 #define LRFDPBE_LFSR1BRH_VALMSB_M 0x0000FFFFU 3666 #define LRFDPBE_LFSR1BRH_VALMSB_S 0U 3667 #define LRFDPBE_LFSR1BRH_VALMSB_ALLONES 0x0000FFFFU 3668 #define LRFDPBE_LFSR1BRH_VALMSB_ALLZEROS 0x00000000U 3669 3670 //***************************************************************************** 3671 // 3672 // Register: LRFDPBE_O_LFSR0INL 3673 // 3674 //***************************************************************************** 3675 // Field: [15:0] VAL 3676 // 3677 // LFSR 0 input value LSB first 3678 // ENUMs: 3679 // ALLONES All the bits are 1 3680 // ALLZEROS All the bits are 0 3681 #define LRFDPBE_LFSR0INL_VAL_W 16U 3682 #define LRFDPBE_LFSR0INL_VAL_M 0x0000FFFFU 3683 #define LRFDPBE_LFSR0INL_VAL_S 0U 3684 #define LRFDPBE_LFSR0INL_VAL_ALLONES 0x00000003U 3685 #define LRFDPBE_LFSR0INL_VAL_ALLZEROS 0x00000000U 3686 3687 //***************************************************************************** 3688 // 3689 // Register: LRFDPBE_O_LFSR0N 3690 // 3691 //***************************************************************************** 3692 // Field: [3:0] SIZE 3693 // 3694 // Number of bits to clock into LSFR0 upon next write to LFSR0INL or LFSR0INM 3695 // ENUMs: 3696 // ALLONES All the bits are 1 3697 // ALLZEROS All the bits are 0 3698 #define LRFDPBE_LFSR0N_SIZE_W 4U 3699 #define LRFDPBE_LFSR0N_SIZE_M 0x0000000FU 3700 #define LRFDPBE_LFSR0N_SIZE_S 0U 3701 #define LRFDPBE_LFSR0N_SIZE_ALLONES 0x0000000FU 3702 #define LRFDPBE_LFSR0N_SIZE_ALLZEROS 0x00000000U 3703 3704 //***************************************************************************** 3705 // 3706 // Register: LRFDPBE_O_LFSR0INM 3707 // 3708 //***************************************************************************** 3709 // Field: [15:0] VAL 3710 // 3711 // LFSR 0 input value MSB first 3712 // ENUMs: 3713 // ONE The bit is 1 3714 // ZERO The bit is 0 3715 #define LRFDPBE_LFSR0INM_VAL_W 16U 3716 #define LRFDPBE_LFSR0INM_VAL_M 0x0000FFFFU 3717 #define LRFDPBE_LFSR0INM_VAL_S 0U 3718 #define LRFDPBE_LFSR0INM_VAL_ONE 0x00000001U 3719 #define LRFDPBE_LFSR0INM_VAL_ZERO 0x00000000U 3720 3721 //***************************************************************************** 3722 // 3723 // Register: LRFDPBE_O_PHAOUT0 3724 // 3725 //***************************************************************************** 3726 // Field: [15:0] VAL 3727 // 3728 // Output value of LFSR0 3729 // ENUMs: 3730 // ALLONES All the bits are 1 3731 // ALLZEROS All the bits are 0 3732 #define LRFDPBE_PHAOUT0_VAL_W 16U 3733 #define LRFDPBE_PHAOUT0_VAL_M 0x0000FFFFU 3734 #define LRFDPBE_PHAOUT0_VAL_S 0U 3735 #define LRFDPBE_PHAOUT0_VAL_ALLONES 0x0000DCD7U 3736 #define LRFDPBE_PHAOUT0_VAL_ALLZEROS 0x00000000U 3737 3738 //***************************************************************************** 3739 // 3740 // Register: LRFDPBE_O_LFSR1INL 3741 // 3742 //***************************************************************************** 3743 // Field: [15:0] VAL 3744 // 3745 // LFSR 1 input value LSB first 3746 // ENUMs: 3747 // ALLONES All the bits are 1 3748 // ALLZEROS All the bits are 0 3749 #define LRFDPBE_LFSR1INL_VAL_W 16U 3750 #define LRFDPBE_LFSR1INL_VAL_M 0x0000FFFFU 3751 #define LRFDPBE_LFSR1INL_VAL_S 0U 3752 #define LRFDPBE_LFSR1INL_VAL_ALLONES 0x00000003U 3753 #define LRFDPBE_LFSR1INL_VAL_ALLZEROS 0x00000000U 3754 3755 //***************************************************************************** 3756 // 3757 // Register: LRFDPBE_O_LFSR1N 3758 // 3759 //***************************************************************************** 3760 // Field: [3:0] SIZE 3761 // 3762 // Number of bits to clock into LSFR1 upon next write to LFSR1INL or LFSR1INM 3763 // ENUMs: 3764 // ALLONES All the bits are 1 3765 // ALLZEROS All the bits are 0 3766 #define LRFDPBE_LFSR1N_SIZE_W 4U 3767 #define LRFDPBE_LFSR1N_SIZE_M 0x0000000FU 3768 #define LRFDPBE_LFSR1N_SIZE_S 0U 3769 #define LRFDPBE_LFSR1N_SIZE_ALLONES 0x0000000FU 3770 #define LRFDPBE_LFSR1N_SIZE_ALLZEROS 0x00000000U 3771 3772 //***************************************************************************** 3773 // 3774 // Register: LRFDPBE_O_LFSR1INM 3775 // 3776 //***************************************************************************** 3777 // Field: [15:0] VAL 3778 // 3779 // LFSR 1 input value MSB first 3780 // ENUMs: 3781 // ONE The bit is 1 3782 // ZERO The bit is 0 3783 #define LRFDPBE_LFSR1INM_VAL_W 16U 3784 #define LRFDPBE_LFSR1INM_VAL_M 0x0000FFFFU 3785 #define LRFDPBE_LFSR1INM_VAL_S 0U 3786 #define LRFDPBE_LFSR1INM_VAL_ONE 0x00000001U 3787 #define LRFDPBE_LFSR1INM_VAL_ZERO 0x00000000U 3788 3789 //***************************************************************************** 3790 // 3791 // Register: LRFDPBE_O_PHAOUT0BR 3792 // 3793 //***************************************************************************** 3794 // Field: [15:0] VAL 3795 // 3796 // Output value of LFSR0 in bit reversed order 3797 // ENUMs: 3798 // ALLONES All the bits are 1 3799 // ALLZEROS All the bits are 0 3800 #define LRFDPBE_PHAOUT0BR_VAL_W 16U 3801 #define LRFDPBE_PHAOUT0BR_VAL_M 0x0000FFFFU 3802 #define LRFDPBE_PHAOUT0BR_VAL_S 0U 3803 #define LRFDPBE_PHAOUT0BR_VAL_ALLONES 0x0000FFFFU 3804 #define LRFDPBE_PHAOUT0BR_VAL_ALLZEROS 0x00000000U 3805 3806 //***************************************************************************** 3807 // 3808 // Register: LRFDPBE_O_SYSTIM0L 3809 // 3810 //***************************************************************************** 3811 // Field: [15:0] VALLSB 3812 // 3813 // SYSTIM0 capture low part value, bits 15:0 3814 // ENUMs: 3815 // ONE The bit is 1 3816 // ZERO The bit is 0 3817 #define LRFDPBE_SYSTIM0L_VALLSB_W 16U 3818 #define LRFDPBE_SYSTIM0L_VALLSB_M 0x0000FFFFU 3819 #define LRFDPBE_SYSTIM0L_VALLSB_S 0U 3820 #define LRFDPBE_SYSTIM0L_VALLSB_ONE 0x00000001U 3821 #define LRFDPBE_SYSTIM0L_VALLSB_ZERO 0x00000000U 3822 3823 //***************************************************************************** 3824 // 3825 // Register: LRFDPBE_O_SYSTIM0H 3826 // 3827 //***************************************************************************** 3828 // Field: [15:0] VALMSB 3829 // 3830 // SYSTIM0 capture high part value, bits 31:16 3831 // ENUMs: 3832 // ONE The bit is 1 3833 // ZERO The bit is 0 3834 #define LRFDPBE_SYSTIM0H_VALMSB_W 16U 3835 #define LRFDPBE_SYSTIM0H_VALMSB_M 0x0000FFFFU 3836 #define LRFDPBE_SYSTIM0H_VALMSB_S 0U 3837 #define LRFDPBE_SYSTIM0H_VALMSB_ONE 0x00000001U 3838 #define LRFDPBE_SYSTIM0H_VALMSB_ZERO 0x00000000U 3839 3840 //***************************************************************************** 3841 // 3842 // Register: LRFDPBE_O_SYSTIM1L 3843 // 3844 //***************************************************************************** 3845 // Field: [15:0] VALLSB 3846 // 3847 // SYSTIM1 capture low part value, bits 15:0 3848 // ENUMs: 3849 // ONE The bit is 1 3850 // ZERO The bit is 0 3851 #define LRFDPBE_SYSTIM1L_VALLSB_W 16U 3852 #define LRFDPBE_SYSTIM1L_VALLSB_M 0x0000FFFFU 3853 #define LRFDPBE_SYSTIM1L_VALLSB_S 0U 3854 #define LRFDPBE_SYSTIM1L_VALLSB_ONE 0x00000001U 3855 #define LRFDPBE_SYSTIM1L_VALLSB_ZERO 0x00000000U 3856 3857 //***************************************************************************** 3858 // 3859 // Register: LRFDPBE_O_SYSTIM1H 3860 // 3861 //***************************************************************************** 3862 // Field: [15:0] VALMSB 3863 // 3864 // SYSTIM1 capture high part value, bits 31:16 3865 // ENUMs: 3866 // ONE The bit is 1 3867 // ZERO The bit is 0 3868 #define LRFDPBE_SYSTIM1H_VALMSB_W 16U 3869 #define LRFDPBE_SYSTIM1H_VALMSB_M 0x0000FFFFU 3870 #define LRFDPBE_SYSTIM1H_VALMSB_S 0U 3871 #define LRFDPBE_SYSTIM1H_VALMSB_ONE 0x00000001U 3872 #define LRFDPBE_SYSTIM1H_VALMSB_ZERO 0x00000000U 3873 3874 //***************************************************************************** 3875 // 3876 // Register: LRFDPBE_O_SYSTIM2L 3877 // 3878 //***************************************************************************** 3879 // Field: [15:0] VALLSB 3880 // 3881 // SYSTIM2 capture low part value, bits 15:0 3882 // ENUMs: 3883 // ONE The bit is 1 3884 // ZERO The bit is 0 3885 #define LRFDPBE_SYSTIM2L_VALLSB_W 16U 3886 #define LRFDPBE_SYSTIM2L_VALLSB_M 0x0000FFFFU 3887 #define LRFDPBE_SYSTIM2L_VALLSB_S 0U 3888 #define LRFDPBE_SYSTIM2L_VALLSB_ONE 0x00000001U 3889 #define LRFDPBE_SYSTIM2L_VALLSB_ZERO 0x00000000U 3890 3891 //***************************************************************************** 3892 // 3893 // Register: LRFDPBE_O_SYSTIM2H 3894 // 3895 //***************************************************************************** 3896 // Field: [15:0] VALMSB 3897 // 3898 // SYSTIM2 capture high part value, bits 31:16 3899 // ENUMs: 3900 // ONE The bit is 1 3901 // ZERO The bit is 0 3902 #define LRFDPBE_SYSTIM2H_VALMSB_W 16U 3903 #define LRFDPBE_SYSTIM2H_VALMSB_M 0x0000FFFFU 3904 #define LRFDPBE_SYSTIM2H_VALMSB_S 0U 3905 #define LRFDPBE_SYSTIM2H_VALMSB_ONE 0x00000001U 3906 #define LRFDPBE_SYSTIM2H_VALMSB_ZERO 0x00000000U 3907 3908 //***************************************************************************** 3909 // 3910 // Register: LRFDPBE_O_GPI 3911 // 3912 //***************************************************************************** 3913 // Field: [7] GPI7 3914 // 3915 // Control GPI7 3916 // ENUMs: 3917 // ONE The bit is 1 3918 // ZERO The bit is 0 3919 #define LRFDPBE_GPI_GPI7 0x00000080U 3920 #define LRFDPBE_GPI_GPI7_M 0x00000080U 3921 #define LRFDPBE_GPI_GPI7_S 7U 3922 #define LRFDPBE_GPI_GPI7_ONE 0x00000080U 3923 #define LRFDPBE_GPI_GPI7_ZERO 0x00000000U 3924 3925 // Field: [6] GPI6 3926 // 3927 // Control GPI6 3928 // ENUMs: 3929 // ONE The bit is 1 3930 // ZERO The bit is 0 3931 #define LRFDPBE_GPI_GPI6 0x00000040U 3932 #define LRFDPBE_GPI_GPI6_M 0x00000040U 3933 #define LRFDPBE_GPI_GPI6_S 6U 3934 #define LRFDPBE_GPI_GPI6_ONE 0x00000040U 3935 #define LRFDPBE_GPI_GPI6_ZERO 0x00000000U 3936 3937 // Field: [5] GPI5 3938 // 3939 // Control GPI5 3940 // ENUMs: 3941 // ONE The bit is 1 3942 // ZERO The bit is 0 3943 #define LRFDPBE_GPI_GPI5 0x00000020U 3944 #define LRFDPBE_GPI_GPI5_M 0x00000020U 3945 #define LRFDPBE_GPI_GPI5_S 5U 3946 #define LRFDPBE_GPI_GPI5_ONE 0x00000020U 3947 #define LRFDPBE_GPI_GPI5_ZERO 0x00000000U 3948 3949 // Field: [4] GPI4 3950 // 3951 // Control GPI4 3952 // ENUMs: 3953 // ONE The bit is 1 3954 // ZERO The bit is 0 3955 #define LRFDPBE_GPI_GPI4 0x00000010U 3956 #define LRFDPBE_GPI_GPI4_M 0x00000010U 3957 #define LRFDPBE_GPI_GPI4_S 4U 3958 #define LRFDPBE_GPI_GPI4_ONE 0x00000010U 3959 #define LRFDPBE_GPI_GPI4_ZERO 0x00000000U 3960 3961 // Field: [3] GPI3 3962 // 3963 // Control GPI3 3964 // ENUMs: 3965 // ONE The bit is 1 3966 // ZERO The bit is 0 3967 #define LRFDPBE_GPI_GPI3 0x00000008U 3968 #define LRFDPBE_GPI_GPI3_M 0x00000008U 3969 #define LRFDPBE_GPI_GPI3_S 3U 3970 #define LRFDPBE_GPI_GPI3_ONE 0x00000008U 3971 #define LRFDPBE_GPI_GPI3_ZERO 0x00000000U 3972 3973 // Field: [2] GPI2 3974 // 3975 // Control GPI2 3976 // ENUMs: 3977 // ONE The bit is 1 3978 // ZERO The bit is 0 3979 #define LRFDPBE_GPI_GPI2 0x00000004U 3980 #define LRFDPBE_GPI_GPI2_M 0x00000004U 3981 #define LRFDPBE_GPI_GPI2_S 2U 3982 #define LRFDPBE_GPI_GPI2_ONE 0x00000004U 3983 #define LRFDPBE_GPI_GPI2_ZERO 0x00000000U 3984 3985 // Field: [1] GPI1 3986 // 3987 // Control GPI1 3988 // ENUMs: 3989 // ONE The bit is 1 3990 // ZERO The bit is 0 3991 #define LRFDPBE_GPI_GPI1 0x00000002U 3992 #define LRFDPBE_GPI_GPI1_M 0x00000002U 3993 #define LRFDPBE_GPI_GPI1_S 1U 3994 #define LRFDPBE_GPI_GPI1_ONE 0x00000002U 3995 #define LRFDPBE_GPI_GPI1_ZERO 0x00000000U 3996 3997 // Field: [0] GPI0 3998 // 3999 // Control GPI0 4000 // ENUMs: 4001 // ONE The bit is 1 4002 // ZERO The bit is 0 4003 #define LRFDPBE_GPI_GPI0 0x00000001U 4004 #define LRFDPBE_GPI_GPI0_M 0x00000001U 4005 #define LRFDPBE_GPI_GPI0_S 0U 4006 #define LRFDPBE_GPI_GPI0_ONE 0x00000001U 4007 #define LRFDPBE_GPI_GPI0_ZERO 0x00000000U 4008 4009 //***************************************************************************** 4010 // 4011 // Register: LRFDPBE_O_FCMD 4012 // 4013 //***************************************************************************** 4014 // Field: [7:0] DATA 4015 // 4016 // Command either RX or TX FIFO or both. Strobe signals which clear after 4017 // write. 4018 // ENUMs: 4019 // FIFO_COMMIT Commit both FIFOs 4020 // FIFO_DISCARD Discard both FIFOs 4021 // FIFO_RETRY Retry both FIFOs 4022 // FIFO_DEALLOC Deallocate both FIFOS 4023 // FIFO_RESET Reset (empty) both FIFOs 4024 // RXFIFO_RETRY Retry rxfifo. This sets RXFRP := RXFSRP 4025 // RXFIFO_DISCARD Discard rxfifo. This sets RXFWP := RXFSWP 4026 // RXFIFO_COMMIT Commit rxfifo. This sets RXFSWP := RXFWP 4027 // TXFIFO_RESET Reset (empty) txfifo. Set TXF* := 0 4028 // TXFIFO_DEALLOC Deallocate txfifo. This sets TXFSRP := TXFRP. 4029 // TXFIFO_RETRY Retry txfifo. This sets TXFRP := TXFSRP 4030 // TXFIFO_DISCARD Discard txfifo. This sets TXFWP := TXFSWP 4031 // TXFIFO_COMMIT Commit txfifo. This sets TXFSWP := TXFWP 4032 // RXFIFO_DEALLOC Deallocate rxfifo. This sets RXFSRP := RXFRP. 4033 // RXFIFO_RESET Reset (empty) rxfifo. Set RXF* := 0 4034 #define LRFDPBE_FCMD_DATA_W 8U 4035 #define LRFDPBE_FCMD_DATA_M 0x000000FFU 4036 #define LRFDPBE_FCMD_DATA_S 0U 4037 #define LRFDPBE_FCMD_DATA_FIFO_COMMIT 0x0000000FU 4038 #define LRFDPBE_FCMD_DATA_FIFO_DISCARD 0x0000000EU 4039 #define LRFDPBE_FCMD_DATA_FIFO_RETRY 0x0000000DU 4040 #define LRFDPBE_FCMD_DATA_FIFO_DEALLOC 0x0000000CU 4041 #define LRFDPBE_FCMD_DATA_FIFO_RESET 0x0000000BU 4042 #define LRFDPBE_FCMD_DATA_RXFIFO_RETRY 0x0000000AU 4043 #define LRFDPBE_FCMD_DATA_RXFIFO_DISCARD 0x00000009U 4044 #define LRFDPBE_FCMD_DATA_RXFIFO_COMMIT 0x00000008U 4045 #define LRFDPBE_FCMD_DATA_TXFIFO_RESET 0x00000007U 4046 #define LRFDPBE_FCMD_DATA_TXFIFO_DEALLOC 0x00000006U 4047 #define LRFDPBE_FCMD_DATA_TXFIFO_RETRY 0x00000005U 4048 #define LRFDPBE_FCMD_DATA_TXFIFO_DISCARD 0x00000004U 4049 #define LRFDPBE_FCMD_DATA_TXFIFO_COMMIT 0x00000003U 4050 #define LRFDPBE_FCMD_DATA_RXFIFO_DEALLOC 0x00000002U 4051 #define LRFDPBE_FCMD_DATA_RXFIFO_RESET 0x00000001U 4052 4053 //***************************************************************************** 4054 // 4055 // Register: LRFDPBE_O_FSTAT 4056 // 4057 //***************************************************************************** 4058 // Field: [11] TXUNFL 4059 // 4060 // Underflow occurred in the TX FIFO. 4061 // ENUMs: 4062 // TRUE Underflow has occurred 4063 // FALSE Normal operation ensues 4064 #define LRFDPBE_FSTAT_TXUNFL 0x00000800U 4065 #define LRFDPBE_FSTAT_TXUNFL_M 0x00000800U 4066 #define LRFDPBE_FSTAT_TXUNFL_S 11U 4067 #define LRFDPBE_FSTAT_TXUNFL_TRUE 0x00000800U 4068 #define LRFDPBE_FSTAT_TXUNFL_FALSE 0x00000000U 4069 4070 // Field: [10] TXOVFL 4071 // 4072 // Overflow occurred in the TX FIFO. 4073 // ENUMs: 4074 // TRUE Overflow has occurred 4075 // FALSE Normal operation ensues 4076 #define LRFDPBE_FSTAT_TXOVFL 0x00000400U 4077 #define LRFDPBE_FSTAT_TXOVFL_M 0x00000400U 4078 #define LRFDPBE_FSTAT_TXOVFL_S 10U 4079 #define LRFDPBE_FSTAT_TXOVFL_TRUE 0x00000400U 4080 #define LRFDPBE_FSTAT_TXOVFL_FALSE 0x00000000U 4081 4082 // Field: [9] TXEMPTY 4083 // 4084 // TXFIFO empty flag 4085 // ENUMs: 4086 // TRUE TXFIFO is empty 4087 // FALSE TXFIFO is not empty 4088 #define LRFDPBE_FSTAT_TXEMPTY 0x00000200U 4089 #define LRFDPBE_FSTAT_TXEMPTY_M 0x00000200U 4090 #define LRFDPBE_FSTAT_TXEMPTY_S 9U 4091 #define LRFDPBE_FSTAT_TXEMPTY_TRUE 0x00000200U 4092 #define LRFDPBE_FSTAT_TXEMPTY_FALSE 0x00000000U 4093 4094 // Field: [8] TXFULL 4095 // 4096 // TXFIFO full flag 4097 // ENUMs: 4098 // TRUE TXFIFO is full 4099 // FALSE TXFIFO is not full 4100 #define LRFDPBE_FSTAT_TXFULL 0x00000100U 4101 #define LRFDPBE_FSTAT_TXFULL_M 0x00000100U 4102 #define LRFDPBE_FSTAT_TXFULL_S 8U 4103 #define LRFDPBE_FSTAT_TXFULL_TRUE 0x00000100U 4104 #define LRFDPBE_FSTAT_TXFULL_FALSE 0x00000000U 4105 4106 // Field: [3] RXUNFL 4107 // 4108 // Underflow occurred in the RX FIFO. 4109 // ENUMs: 4110 // TRUE Underflow has occurred 4111 // FALSE Normal operation ensues 4112 #define LRFDPBE_FSTAT_RXUNFL 0x00000008U 4113 #define LRFDPBE_FSTAT_RXUNFL_M 0x00000008U 4114 #define LRFDPBE_FSTAT_RXUNFL_S 3U 4115 #define LRFDPBE_FSTAT_RXUNFL_TRUE 0x00000008U 4116 #define LRFDPBE_FSTAT_RXUNFL_FALSE 0x00000000U 4117 4118 // Field: [2] RXOVFL 4119 // 4120 // Overflow occurred in the RX FIFO. 4121 // ENUMs: 4122 // TRUE Overflow has occurred 4123 // FALSE Normal operation ensues 4124 #define LRFDPBE_FSTAT_RXOVFL 0x00000004U 4125 #define LRFDPBE_FSTAT_RXOVFL_M 0x00000004U 4126 #define LRFDPBE_FSTAT_RXOVFL_S 2U 4127 #define LRFDPBE_FSTAT_RXOVFL_TRUE 0x00000004U 4128 #define LRFDPBE_FSTAT_RXOVFL_FALSE 0x00000000U 4129 4130 // Field: [1] RXEMPTY 4131 // 4132 // RXFIFO empty flag 4133 // ENUMs: 4134 // TRUE RXFIFO is empty 4135 // FALSE RXFIFO is not empty 4136 #define LRFDPBE_FSTAT_RXEMPTY 0x00000002U 4137 #define LRFDPBE_FSTAT_RXEMPTY_M 0x00000002U 4138 #define LRFDPBE_FSTAT_RXEMPTY_S 1U 4139 #define LRFDPBE_FSTAT_RXEMPTY_TRUE 0x00000002U 4140 #define LRFDPBE_FSTAT_RXEMPTY_FALSE 0x00000000U 4141 4142 // Field: [0] RXFULL 4143 // 4144 // RXFIFO full flag 4145 // ENUMs: 4146 // TRUE RXFIFO is full 4147 // FALSE RXFIFO is not full 4148 #define LRFDPBE_FSTAT_RXFULL 0x00000001U 4149 #define LRFDPBE_FSTAT_RXFULL_M 0x00000001U 4150 #define LRFDPBE_FSTAT_RXFULL_S 0U 4151 #define LRFDPBE_FSTAT_RXFULL_TRUE 0x00000001U 4152 #define LRFDPBE_FSTAT_RXFULL_FALSE 0x00000000U 4153 4154 //***************************************************************************** 4155 // 4156 // Register: LRFDPBE_O_RXFWP 4157 // 4158 //***************************************************************************** 4159 // Field: [9:0] PTR 4160 // 4161 // Write pointer 4162 // ENUMs: 4163 // ALLONES All the bits are 1 4164 // ALLZEROS All the bits are 0 4165 #define LRFDPBE_RXFWP_PTR_W 10U 4166 #define LRFDPBE_RXFWP_PTR_M 0x000003FFU 4167 #define LRFDPBE_RXFWP_PTR_S 0U 4168 #define LRFDPBE_RXFWP_PTR_ALLONES 0x000003FFU 4169 #define LRFDPBE_RXFWP_PTR_ALLZEROS 0x00000000U 4170 4171 //***************************************************************************** 4172 // 4173 // Register: LRFDPBE_O_RXFRP 4174 // 4175 //***************************************************************************** 4176 // Field: [9:0] PTR 4177 // 4178 // Read pointer 4179 // ENUMs: 4180 // ALLONES All the bits are 1 4181 // ALLZEROS All the bits are 0 4182 #define LRFDPBE_RXFRP_PTR_W 10U 4183 #define LRFDPBE_RXFRP_PTR_M 0x000003FFU 4184 #define LRFDPBE_RXFRP_PTR_S 0U 4185 #define LRFDPBE_RXFRP_PTR_ALLONES 0x000003FFU 4186 #define LRFDPBE_RXFRP_PTR_ALLZEROS 0x00000000U 4187 4188 //***************************************************************************** 4189 // 4190 // Register: LRFDPBE_O_RXFSWP 4191 // 4192 //***************************************************************************** 4193 // Field: [9:0] PTR 4194 // 4195 // Pointer to start of written package 4196 // ENUMs: 4197 // ALLONES All the bits are 1 4198 // ALLZEROS All the bits are 0 4199 #define LRFDPBE_RXFSWP_PTR_W 10U 4200 #define LRFDPBE_RXFSWP_PTR_M 0x000003FFU 4201 #define LRFDPBE_RXFSWP_PTR_S 0U 4202 #define LRFDPBE_RXFSWP_PTR_ALLONES 0x000003FFU 4203 #define LRFDPBE_RXFSWP_PTR_ALLZEROS 0x00000000U 4204 4205 //***************************************************************************** 4206 // 4207 // Register: LRFDPBE_O_RXFSRP 4208 // 4209 //***************************************************************************** 4210 // Field: [9:0] PTR 4211 // 4212 // Pointer to start of read package 4213 // ENUMs: 4214 // ALLONES All the bits are 1 4215 // ALLZEROS All the bits are 0 4216 #define LRFDPBE_RXFSRP_PTR_W 10U 4217 #define LRFDPBE_RXFSRP_PTR_M 0x000003FFU 4218 #define LRFDPBE_RXFSRP_PTR_S 0U 4219 #define LRFDPBE_RXFSRP_PTR_ALLONES 0x000003FFU 4220 #define LRFDPBE_RXFSRP_PTR_ALLZEROS 0x00000000U 4221 4222 //***************************************************************************** 4223 // 4224 // Register: LRFDPBE_O_TXFWP 4225 // 4226 //***************************************************************************** 4227 // Field: [9:0] PTR 4228 // 4229 // Write pointer 4230 // ENUMs: 4231 // ALLONES All the bits are 1 4232 // ALLZEROS All the bits are 0 4233 #define LRFDPBE_TXFWP_PTR_W 10U 4234 #define LRFDPBE_TXFWP_PTR_M 0x000003FFU 4235 #define LRFDPBE_TXFWP_PTR_S 0U 4236 #define LRFDPBE_TXFWP_PTR_ALLONES 0x000003FFU 4237 #define LRFDPBE_TXFWP_PTR_ALLZEROS 0x00000000U 4238 4239 //***************************************************************************** 4240 // 4241 // Register: LRFDPBE_O_TXFRP 4242 // 4243 //***************************************************************************** 4244 // Field: [9:0] PTR 4245 // 4246 // Read pointer 4247 // ENUMs: 4248 // ALLONES All the bits are 1 4249 // ALLZEROS All the bits are 0 4250 #define LRFDPBE_TXFRP_PTR_W 10U 4251 #define LRFDPBE_TXFRP_PTR_M 0x000003FFU 4252 #define LRFDPBE_TXFRP_PTR_S 0U 4253 #define LRFDPBE_TXFRP_PTR_ALLONES 0x000003FFU 4254 #define LRFDPBE_TXFRP_PTR_ALLZEROS 0x00000000U 4255 4256 //***************************************************************************** 4257 // 4258 // Register: LRFDPBE_O_TXFSWP 4259 // 4260 //***************************************************************************** 4261 // Field: [9:0] PTR 4262 // 4263 // Pointer to start of written package 4264 // ENUMs: 4265 // ALLONES All the bits are 1 4266 // ALLZEROS All the bits are 0 4267 #define LRFDPBE_TXFSWP_PTR_W 10U 4268 #define LRFDPBE_TXFSWP_PTR_M 0x000003FFU 4269 #define LRFDPBE_TXFSWP_PTR_S 0U 4270 #define LRFDPBE_TXFSWP_PTR_ALLONES 0x000003FFU 4271 #define LRFDPBE_TXFSWP_PTR_ALLZEROS 0x00000000U 4272 4273 //***************************************************************************** 4274 // 4275 // Register: LRFDPBE_O_TXFSRP 4276 // 4277 //***************************************************************************** 4278 // Field: [9:0] PTR 4279 // 4280 // Pointer to start of read package 4281 // ENUMs: 4282 // ALLONES_2 All the bits are 1 4283 // ALLZEROS All the bits are 0 4284 #define LRFDPBE_TXFSRP_PTR_W 10U 4285 #define LRFDPBE_TXFSRP_PTR_M 0x000003FFU 4286 #define LRFDPBE_TXFSRP_PTR_S 0U 4287 #define LRFDPBE_TXFSRP_PTR_ALLONES_2 0x000003FFU 4288 #define LRFDPBE_TXFSRP_PTR_ALLZEROS 0x00000000U 4289 4290 //***************************************************************************** 4291 // 4292 // Register: LRFDPBE_O_RXFWRITABLE 4293 // 4294 //***************************************************************************** 4295 // Field: [9:0] BYTES 4296 // 4297 // The amount of writable bytes for the RX FIFO may be directly read here 4298 // ENUMs: 4299 // ALLONES All the bits are 1 4300 // ALLZEROS All the bits are 0 4301 #define LRFDPBE_RXFWRITABLE_BYTES_W 10U 4302 #define LRFDPBE_RXFWRITABLE_BYTES_M 0x000003FFU 4303 #define LRFDPBE_RXFWRITABLE_BYTES_S 0U 4304 #define LRFDPBE_RXFWRITABLE_BYTES_ALLONES 0x000003FFU 4305 #define LRFDPBE_RXFWRITABLE_BYTES_ALLZEROS 0x00000000U 4306 4307 //***************************************************************************** 4308 // 4309 // Register: LRFDPBE_O_RXFREADABLE 4310 // 4311 //***************************************************************************** 4312 // Field: [9:0] BYTES 4313 // 4314 // The amount of readable bytes for the RX FIFO may be directly read here 4315 // ENUMs: 4316 // ALLONES All the bits are 1 4317 // ALLZEROS All the bits are 0 4318 #define LRFDPBE_RXFREADABLE_BYTES_W 10U 4319 #define LRFDPBE_RXFREADABLE_BYTES_M 0x000003FFU 4320 #define LRFDPBE_RXFREADABLE_BYTES_S 0U 4321 #define LRFDPBE_RXFREADABLE_BYTES_ALLONES 0x000003FFU 4322 #define LRFDPBE_RXFREADABLE_BYTES_ALLZEROS 0x00000000U 4323 4324 //***************************************************************************** 4325 // 4326 // Register: LRFDPBE_O_TXFWRITABLE 4327 // 4328 //***************************************************************************** 4329 // Field: [9:0] BYTES 4330 // 4331 // The amount of writable bytes for the TX FIFO may be directly read here 4332 // ENUMs: 4333 // ALLONES All the bits are 1 4334 // ALLZEROS All the bits are 0 4335 #define LRFDPBE_TXFWRITABLE_BYTES_W 10U 4336 #define LRFDPBE_TXFWRITABLE_BYTES_M 0x000003FFU 4337 #define LRFDPBE_TXFWRITABLE_BYTES_S 0U 4338 #define LRFDPBE_TXFWRITABLE_BYTES_ALLONES 0x000003FFU 4339 #define LRFDPBE_TXFWRITABLE_BYTES_ALLZEROS 0x00000000U 4340 4341 //***************************************************************************** 4342 // 4343 // Register: LRFDPBE_O_TXFREADABLE 4344 // 4345 //***************************************************************************** 4346 // Field: [9:0] BYTES 4347 // 4348 // The amount of readable bytes for the TX FIFO may be directly read here 4349 // ENUMs: 4350 // ALLONES All the bits are 1 4351 // ALLZEROS All the bits are 0 4352 #define LRFDPBE_TXFREADABLE_BYTES_W 10U 4353 #define LRFDPBE_TXFREADABLE_BYTES_M 0x000003FFU 4354 #define LRFDPBE_TXFREADABLE_BYTES_S 0U 4355 #define LRFDPBE_TXFREADABLE_BYTES_ALLONES 0x000003FFU 4356 #define LRFDPBE_TXFREADABLE_BYTES_ALLZEROS 0x00000000U 4357 4358 //***************************************************************************** 4359 // 4360 // Register: LRFDPBE_O_RXFBRD 4361 // 4362 //***************************************************************************** 4363 // Field: [7:0] DATA 4364 // 4365 // Data to be read 4366 // ENUMs: 4367 // ALLONES All the bits are 1 4368 // ALLZEROS All the bits are 0 4369 #define LRFDPBE_RXFBRD_DATA_W 8U 4370 #define LRFDPBE_RXFBRD_DATA_M 0x000000FFU 4371 #define LRFDPBE_RXFBRD_DATA_S 0U 4372 #define LRFDPBE_RXFBRD_DATA_ALLONES 0x000000FFU 4373 #define LRFDPBE_RXFBRD_DATA_ALLZEROS 0x00000000U 4374 4375 //***************************************************************************** 4376 // 4377 // Register: LRFDPBE_O_RXFBWR 4378 // 4379 //***************************************************************************** 4380 // Field: [7:0] DATA 4381 // 4382 // Data to be written 4383 // ENUMs: 4384 // ALLONES All the bits are 1 4385 // ALLZEROS All the bits are 0 4386 #define LRFDPBE_RXFBWR_DATA_W 8U 4387 #define LRFDPBE_RXFBWR_DATA_M 0x000000FFU 4388 #define LRFDPBE_RXFBWR_DATA_S 0U 4389 #define LRFDPBE_RXFBWR_DATA_ALLONES 0x000000FFU 4390 #define LRFDPBE_RXFBWR_DATA_ALLZEROS 0x00000000U 4391 4392 //***************************************************************************** 4393 // 4394 // Register: LRFDPBE_O_TXFBRD 4395 // 4396 //***************************************************************************** 4397 // Field: [7:0] DATA 4398 // 4399 // Data to be read 4400 // ENUMs: 4401 // ALLONES All the bits are 1 4402 // ALLZEROS All the bits are 0 4403 #define LRFDPBE_TXFBRD_DATA_W 8U 4404 #define LRFDPBE_TXFBRD_DATA_M 0x000000FFU 4405 #define LRFDPBE_TXFBRD_DATA_S 0U 4406 #define LRFDPBE_TXFBRD_DATA_ALLONES 0x000000FFU 4407 #define LRFDPBE_TXFBRD_DATA_ALLZEROS 0x00000000U 4408 4409 //***************************************************************************** 4410 // 4411 // Register: LRFDPBE_O_TXFBWR 4412 // 4413 //***************************************************************************** 4414 // Field: [7:0] DATA 4415 // 4416 // Data to be written 4417 // ENUMs: 4418 // ALLONES All the bits are 1 4419 // ALLZEROS All the bits are 0 4420 #define LRFDPBE_TXFBWR_DATA_W 8U 4421 #define LRFDPBE_TXFBWR_DATA_M 0x000000FFU 4422 #define LRFDPBE_TXFBWR_DATA_S 0U 4423 #define LRFDPBE_TXFBWR_DATA_ALLONES 0x000000FFU 4424 #define LRFDPBE_TXFBWR_DATA_ALLZEROS 0x00000000U 4425 4426 //***************************************************************************** 4427 // 4428 // Register: LRFDPBE_O_RXFHRD 4429 // 4430 //***************************************************************************** 4431 // Field: [15:0] DATA 4432 // 4433 // Data to be read 4434 // ENUMs: 4435 // ALLONES All the bits are 1 4436 // ALLZEROS All the bits are 0 4437 #define LRFDPBE_RXFHRD_DATA_W 16U 4438 #define LRFDPBE_RXFHRD_DATA_M 0x0000FFFFU 4439 #define LRFDPBE_RXFHRD_DATA_S 0U 4440 #define LRFDPBE_RXFHRD_DATA_ALLONES 0x0000FFFFU 4441 #define LRFDPBE_RXFHRD_DATA_ALLZEROS 0x00000000U 4442 4443 //***************************************************************************** 4444 // 4445 // Register: LRFDPBE_O_RXFHWR 4446 // 4447 //***************************************************************************** 4448 // Field: [15:0] DATA 4449 // 4450 // Data to be written 4451 // ENUMs: 4452 // ALLONES All the bits are 1 4453 // ALLZEROS All the bits are 0 4454 #define LRFDPBE_RXFHWR_DATA_W 16U 4455 #define LRFDPBE_RXFHWR_DATA_M 0x0000FFFFU 4456 #define LRFDPBE_RXFHWR_DATA_S 0U 4457 #define LRFDPBE_RXFHWR_DATA_ALLONES 0x0000FFFFU 4458 #define LRFDPBE_RXFHWR_DATA_ALLZEROS 0x00000000U 4459 4460 //***************************************************************************** 4461 // 4462 // Register: LRFDPBE_O_TXFHRD 4463 // 4464 //***************************************************************************** 4465 // Field: [15:0] DATA 4466 // 4467 // Data to be read 4468 // ENUMs: 4469 // ALLONES All the bits are 1 4470 // ALLZEROS All the bits are 0 4471 #define LRFDPBE_TXFHRD_DATA_W 16U 4472 #define LRFDPBE_TXFHRD_DATA_M 0x0000FFFFU 4473 #define LRFDPBE_TXFHRD_DATA_S 0U 4474 #define LRFDPBE_TXFHRD_DATA_ALLONES 0x0000FFFFU 4475 #define LRFDPBE_TXFHRD_DATA_ALLZEROS 0x00000000U 4476 4477 //***************************************************************************** 4478 // 4479 // Register: LRFDPBE_O_TXFHWR 4480 // 4481 //***************************************************************************** 4482 // Field: [15:0] DATA 4483 // 4484 // Data to be written 4485 // ENUMs: 4486 // ALLONES All the bits are 1 4487 // ALLZEROS All the bits are 0 4488 #define LRFDPBE_TXFHWR_DATA_W 16U 4489 #define LRFDPBE_TXFHWR_DATA_M 0x0000FFFFU 4490 #define LRFDPBE_TXFHWR_DATA_S 0U 4491 #define LRFDPBE_TXFHWR_DATA_ALLONES 0x0000FFFFU 4492 #define LRFDPBE_TXFHWR_DATA_ALLZEROS 0x00000000U 4493 4494 4495 #endif // __LRFDPBE__ 4496
