1 /****************************************************************************** 2 * Filename: hw_lrfdpbe32_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_LRFDPBE32_H__ 34 #define __HW_LRFDPBE32_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // LRFDPBE32 component 40 // 41 //***************************************************************************** 42 // Packet Building Engine Enable Register 43 #define LRFDPBE32_O_FWSRC_ENABLE 0x00000000U 44 45 // Packet Building Engine Initialization Register 46 #define LRFDPBE32_O_STROBES0_INIT 0x00000004U 47 48 // Interrupt generate register 49 #define LRFDPBE32_O_EVT0_IRQ 0x00000008U 50 51 // PBE Event Flag Register 1 52 #define LRFDPBE32_O_EVTMSK0_EVT1 0x0000000CU 53 54 // PBE Event Mask Register 1 55 #define LRFDPBE32_O_EVTCLR0_EVTMSK1 0x00000010U 56 57 // PBE Event Mask Register 1 58 #define LRFDPBE32_O_PDREQ_EVTCLR1 0x00000014U 59 60 // PBE API Command Register 61 #define LRFDPBE32_O_MCEDATOUT0_API 0x00000018U 62 63 // MCE-to-PBE Receive Data Register 64 #define LRFDPBE32_O_MCECMDOUT_MCEDATIN0 0x0000001CU 65 66 // MCE-to-PBE Receive Command Register 67 #define LRFDPBE32_O_MDMAPI_MCECMDIN 0x00000020U 68 69 // Modem Command Status Register 70 #define LRFDPBE32_O_FREQ_MDMMSGBOX 0x00000024U 71 72 // Link quality indicator 73 #define LRFDPBE32_O_RFEDATOUT0_MDMLQI 0x00000028U 74 75 // RFE-to-PBE Receive Data Register 76 #define LRFDPBE32_O_RFECMDOUT_RFEDATIN0 0x0000002CU 77 78 // RFE-to-PBE Receive Command Register 79 #define LRFDPBE32_O_RFEAPI_RFECMDIN 0x00000030U 80 81 // RFE Command Parameter 0 82 #define LRFDPBE32_O_RFECMDPAR1_RFECMDPAR0 0x00000034U 83 84 // RFE Command Status and Message Box Register 85 #define LRFDPBE32_O_RFERSSI_RFEMSGBOX 0x00000038U 86 87 // RSSI Maximum Value Register 88 #define LRFDPBE32_O_RFERFGAIN_RFERSSIMAX 0x0000003CU 89 90 // Modem Sync Word Register 0 91 #define LRFDPBE32_O_MDMSYNCA 0x00000040U 92 93 // Modem Sync Word Register 2 94 #define LRFDPBE32_O_MDMSYNCB 0x00000044U 95 96 // Modem API Command Parameter 0 97 #define LRFDPBE32_O_MDMCMDPAR1_MDMCMDPAR0 0x00000048U 98 99 // Modem API Command Parameter 2 100 #define LRFDPBE32_O_MDMCMDPAR2 0x0000004CU 101 102 // LFSR 0 Polynomial Definition 103 #define LRFDPBE32_O_POLY0 0x00000050U 104 105 // LFSR 1 Polynomial Definition 106 #define LRFDPBE32_O_POLY1 0x00000054U 107 108 // Packet Handler Accelerator Config Register 109 #define LRFDPBE32_O_FCFG0_PHACFG 0x00000058U 110 111 // FIFO configuration register 112 #define LRFDPBE32_O_FCFG2_FCFG1 0x0000005CU 113 114 // FIFO configuration register 115 #define LRFDPBE32_O_FCFG4_FCFG3 0x00000060U 116 117 // FIFO configuration register 118 #define LRFDPBE32_O_RXFWBTHRS_FCFG5 0x00000064U 119 120 // FIFO read pointer 121 #define LRFDPBE32_O_TXFWBTHRS_RXFRBTHRS 0x00000068U 122 123 // FIFO read pointer 124 #define LRFDPBE32_O_TIMCTL_TXFRBTHRS 0x0000006CU 125 126 // Prescaler setting for timer 0 and timer 1 127 #define LRFDPBE32_O_TIMPER0_TIMPRE 0x00000070U 128 129 // PBE Timer Period Configuration 130 #define LRFDPBE32_O_TIMCAPT0_TIMPER1 0x00000074U 131 132 // PBE Counter Capture Value 133 #define LRFDPBE32_O_TIMCAPT1 0x00000078U 134 135 // PBE Tracer Send Trigger Register 136 #define LRFDPBE32_O_TRCSTAT_TRCCTL 0x00000080U 137 138 // PBE Tracer Commmand Register 139 #define LRFDPBE32_O_TRCPAR0_TRCCMD 0x00000084U 140 141 // PBE Tracer Command Parameter Register 1 142 #define LRFDPBE32_O_GPOCTRL_TRCPAR1 0x00000088U 143 144 // Modem FIFO Write Register 145 #define LRFDPBE32_O_MDMFRD_MDMFWR 0x0000008CU 146 147 // Modem FIFO Write Configuration 148 #define LRFDPBE32_O_MDMFRDCTL_MDMFWRCTL 0x00000090U 149 150 // Modem FIFO Configuration for watermark thresholds 151 #define LRFDPBE32_O_MDMFSTA_MDMFCFG 0x00000094U 152 153 // Packet Handler Accelerator Status 154 #define LRFDPBE32_O_PHASTA 0x00000098U 155 156 // LFSR 0 Current Value 157 #define LRFDPBE32_O_LFSR0 0x0000009CU 158 159 // LFSR 0 Current Value, Bit-reversed 160 #define LRFDPBE32_O_LFSR0BR 0x000000A0U 161 162 // LFSR 1 Current Value 163 #define LRFDPBE32_O_LFSR1 0x000000A4U 164 165 // LFSR 1 Current Value, Bit-reversed 166 #define LRFDPBE32_O_LFSR1BR 0x000000A8U 167 168 // LFSR 0 Input, LSB First 169 #define LRFDPBE32_O_LFSR0N_LFSR0INL 0x000000ACU 170 171 // LFSR 0 Input, MSB First 172 #define LRFDPBE32_O_PHAOUT0_LFSR0INM 0x000000B0U 173 174 // LFSR 1 Input, LSB First 175 #define LRFDPBE32_O_LFSR1N_LFSR1INL 0x000000B4U 176 177 // LFSR 1 Input, MSB First 178 #define LRFDPBE32_O_PHAOUT0BR_LFSR1INM 0x000000B8U 179 180 // Systimer capture value 181 #define LRFDPBE32_O_SYSTIM0 0x000000C0U 182 183 // Systimer capture value 184 #define LRFDPBE32_O_SYSTIM1 0x000000C4U 185 186 // Systimer capture value 187 #define LRFDPBE32_O_SYSTIM2 0x000000C8U 188 189 // PBE Direct GPI Status 190 #define LRFDPBE32_O_GPI 0x000000CCU 191 192 // The FIFO command register 193 #define LRFDPBE32_O_FSTAT_FCMD 0x000000D0U 194 195 // FIFO write pointer 196 #define LRFDPBE32_O_RXFRP_RXFWP 0x000000D4U 197 198 // Rx FIFO start of written package 199 #define LRFDPBE32_O_RXFSRP_RXFSWP 0x000000D8U 200 201 // TXFIFO write pointer 202 #define LRFDPBE32_O_TXFRP_TXFWP 0x000000DCU 203 204 // TXFIFO start of written package 205 #define LRFDPBE32_O_TXFSRP_TXFSWP 0x000000E0U 206 207 // The amount of bytes which are deallocated and not yet written. 208 #define LRFDPBE32_O_RXFREADABLE_RXFWRITABLE 0x000000E4U 209 210 // The amount of bytes which are deallocated and not yet written. 211 #define LRFDPBE32_O_TXFREADABLE_TXFWRITABLE 0x000000E8U 212 213 // FIFO read access register 214 #define LRFDPBE32_O_RXFBWR_RXFBRD 0x000000ECU 215 216 // FIFO read access register 217 #define LRFDPBE32_O_TXFBWR_TXFBRD 0x000000F0U 218 219 // FIFO read access register 220 #define LRFDPBE32_O_RXFHWR_RXFHRD 0x000000F4U 221 222 // FIFO read access register 223 #define LRFDPBE32_O_TXFHWR_TXFHRD 0x000000F8U 224 225 //***************************************************************************** 226 // 227 // Register: LRFDPBE32_O_FWSRC_ENABLE 228 // 229 //***************************************************************************** 230 // Field: [18] DATARAM 231 // 232 // ENUMs: 233 // S2RRAM Use S2RRAM for data 234 // PBERAM Use PBERAM for data 235 #define LRFDPBE32_FWSRC_ENABLE_DATARAM 0x00040000U 236 #define LRFDPBE32_FWSRC_ENABLE_DATARAM_M 0x00040000U 237 #define LRFDPBE32_FWSRC_ENABLE_DATARAM_S 18U 238 #define LRFDPBE32_FWSRC_ENABLE_DATARAM_S2RRAM 0x00040000U 239 #define LRFDPBE32_FWSRC_ENABLE_DATARAM_PBERAM 0x00000000U 240 241 // Field: [17] FWRAM 242 // 243 // ENUMs: 244 // S2RRAM Run code from S2RRAM 245 // PBERAM Run code from PBERAM 246 #define LRFDPBE32_FWSRC_ENABLE_FWRAM 0x00020000U 247 #define LRFDPBE32_FWSRC_ENABLE_FWRAM_M 0x00020000U 248 #define LRFDPBE32_FWSRC_ENABLE_FWRAM_S 17U 249 #define LRFDPBE32_FWSRC_ENABLE_FWRAM_S2RRAM 0x00020000U 250 #define LRFDPBE32_FWSRC_ENABLE_FWRAM_PBERAM 0x00000000U 251 252 // Field: [16] BANK 253 // 254 // ENUMs: 255 // ONE Run code from bank 1 256 // ZERO Run code from bank 0 257 #define LRFDPBE32_FWSRC_ENABLE_BANK 0x00010000U 258 #define LRFDPBE32_FWSRC_ENABLE_BANK_M 0x00010000U 259 #define LRFDPBE32_FWSRC_ENABLE_BANK_S 16U 260 #define LRFDPBE32_FWSRC_ENABLE_BANK_ONE 0x00010000U 261 #define LRFDPBE32_FWSRC_ENABLE_BANK_ZERO 0x00000000U 262 263 // Field: [2] MDMF 264 // 265 // ENUMs: 266 // EN The bit is 1 267 // DIS The bit is 0 268 #define LRFDPBE32_FWSRC_ENABLE_MDMF 0x00000004U 269 #define LRFDPBE32_FWSRC_ENABLE_MDMF_M 0x00000004U 270 #define LRFDPBE32_FWSRC_ENABLE_MDMF_S 2U 271 #define LRFDPBE32_FWSRC_ENABLE_MDMF_EN 0x00000004U 272 #define LRFDPBE32_FWSRC_ENABLE_MDMF_DIS 0x00000000U 273 274 // Field: [1] LOCTIM 275 // 276 // ENUMs: 277 // EN The bit is 1 278 // DIS The bit is 0 279 #define LRFDPBE32_FWSRC_ENABLE_LOCTIM 0x00000002U 280 #define LRFDPBE32_FWSRC_ENABLE_LOCTIM_M 0x00000002U 281 #define LRFDPBE32_FWSRC_ENABLE_LOCTIM_S 1U 282 #define LRFDPBE32_FWSRC_ENABLE_LOCTIM_EN 0x00000002U 283 #define LRFDPBE32_FWSRC_ENABLE_LOCTIM_DIS 0x00000000U 284 285 // Field: [0] TOPSM 286 // 287 // ENUMs: 288 // EN The bit is 1 289 // DIS The bit is 0 290 #define LRFDPBE32_FWSRC_ENABLE_TOPSM 0x00000001U 291 #define LRFDPBE32_FWSRC_ENABLE_TOPSM_M 0x00000001U 292 #define LRFDPBE32_FWSRC_ENABLE_TOPSM_S 0U 293 #define LRFDPBE32_FWSRC_ENABLE_TOPSM_EN 0x00000001U 294 #define LRFDPBE32_FWSRC_ENABLE_TOPSM_DIS 0x00000000U 295 296 //***************************************************************************** 297 // 298 // Register: LRFDPBE32_O_STROBES0_INIT 299 // 300 //***************************************************************************** 301 // Field: [22] TIMCAPT1 302 // 303 // ENUMs: 304 // ONE The bit is 1 305 // ZERO The bit is 0 306 #define LRFDPBE32_STROBES0_INIT_TIMCAPT1 0x00400000U 307 #define LRFDPBE32_STROBES0_INIT_TIMCAPT1_M 0x00400000U 308 #define LRFDPBE32_STROBES0_INIT_TIMCAPT1_S 22U 309 #define LRFDPBE32_STROBES0_INIT_TIMCAPT1_ONE 0x00400000U 310 #define LRFDPBE32_STROBES0_INIT_TIMCAPT1_ZERO 0x00000000U 311 312 // Field: [21] TIMCAPT0 313 // 314 // ENUMs: 315 // ONE The bit is 1 316 // ZERO The bit is 0 317 #define LRFDPBE32_STROBES0_INIT_TIMCAPT0 0x00200000U 318 #define LRFDPBE32_STROBES0_INIT_TIMCAPT0_M 0x00200000U 319 #define LRFDPBE32_STROBES0_INIT_TIMCAPT0_S 21U 320 #define LRFDPBE32_STROBES0_INIT_TIMCAPT0_ONE 0x00200000U 321 #define LRFDPBE32_STROBES0_INIT_TIMCAPT0_ZERO 0x00000000U 322 323 // Field: [20] S2RTRIG 324 // 325 // ENUMs: 326 // ARM The bit is 1 327 // NO_EFFECT The bit is 0 328 #define LRFDPBE32_STROBES0_INIT_S2RTRIG 0x00100000U 329 #define LRFDPBE32_STROBES0_INIT_S2RTRIG_M 0x00100000U 330 #define LRFDPBE32_STROBES0_INIT_S2RTRIG_S 20U 331 #define LRFDPBE32_STROBES0_INIT_S2RTRIG_ARM 0x00100000U 332 #define LRFDPBE32_STROBES0_INIT_S2RTRIG_NO_EFFECT 0x00000000U 333 334 // Field: [19] DMATRIG 335 // 336 // ENUMs: 337 // ARM The bit is 1 338 // NO_EFFECT The bit is 0 339 #define LRFDPBE32_STROBES0_INIT_DMATRIG 0x00080000U 340 #define LRFDPBE32_STROBES0_INIT_DMATRIG_M 0x00080000U 341 #define LRFDPBE32_STROBES0_INIT_DMATRIG_S 19U 342 #define LRFDPBE32_STROBES0_INIT_DMATRIG_ARM 0x00080000U 343 #define LRFDPBE32_STROBES0_INIT_DMATRIG_NO_EFFECT 0x00000000U 344 345 // Field: [18] SYSTCAPT2 346 // 347 // ENUMs: 348 // ONE The bit is 1 349 // ZERO The bit is 0 350 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT2 0x00040000U 351 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT2_M 0x00040000U 352 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT2_S 18U 353 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT2_ONE 0x00040000U 354 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT2_ZERO 0x00000000U 355 356 // Field: [17] SYSTCAPT1 357 // 358 // ENUMs: 359 // ONE The bit is 1 360 // ZERO The bit is 0 361 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT1 0x00020000U 362 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT1_M 0x00020000U 363 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT1_S 17U 364 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT1_ONE 0x00020000U 365 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT1_ZERO 0x00000000U 366 367 // Field: [16] SYSTCAPT0 368 // 369 // ENUMs: 370 // ONE The bit is 1 371 // ZERO The bit is 0 372 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT0 0x00010000U 373 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT0_M 0x00010000U 374 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT0_S 16U 375 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT0_ONE 0x00010000U 376 #define LRFDPBE32_STROBES0_INIT_SYSTCAPT0_ZERO 0x00000000U 377 378 // Field: [4] RFE 379 // 380 // ENUMs: 381 // RESET The bit is 1 382 // NO_EFFECT The bit is 0 383 #define LRFDPBE32_STROBES0_INIT_RFE 0x00000010U 384 #define LRFDPBE32_STROBES0_INIT_RFE_M 0x00000010U 385 #define LRFDPBE32_STROBES0_INIT_RFE_S 4U 386 #define LRFDPBE32_STROBES0_INIT_RFE_RESET 0x00000010U 387 #define LRFDPBE32_STROBES0_INIT_RFE_NO_EFFECT 0x00000000U 388 389 // Field: [3] MDM 390 // 391 // ENUMs: 392 // RESET The bit is 1 393 // NO_EFFECT The bit is 0 394 #define LRFDPBE32_STROBES0_INIT_MDM 0x00000008U 395 #define LRFDPBE32_STROBES0_INIT_MDM_M 0x00000008U 396 #define LRFDPBE32_STROBES0_INIT_MDM_S 3U 397 #define LRFDPBE32_STROBES0_INIT_MDM_RESET 0x00000008U 398 #define LRFDPBE32_STROBES0_INIT_MDM_NO_EFFECT 0x00000000U 399 400 // Field: [2] MDMF 401 // 402 // ENUMs: 403 // RESET The bit is 1 404 // NO_EFFECT The bit is 0 405 #define LRFDPBE32_STROBES0_INIT_MDMF 0x00000004U 406 #define LRFDPBE32_STROBES0_INIT_MDMF_M 0x00000004U 407 #define LRFDPBE32_STROBES0_INIT_MDMF_S 2U 408 #define LRFDPBE32_STROBES0_INIT_MDMF_RESET 0x00000004U 409 #define LRFDPBE32_STROBES0_INIT_MDMF_NO_EFFECT 0x00000000U 410 411 // Field: [1] LOCTIM 412 // 413 // ENUMs: 414 // RESET The bit is 1 415 // NO_EFFECT The bit is 0 416 #define LRFDPBE32_STROBES0_INIT_LOCTIM 0x00000002U 417 #define LRFDPBE32_STROBES0_INIT_LOCTIM_M 0x00000002U 418 #define LRFDPBE32_STROBES0_INIT_LOCTIM_S 1U 419 #define LRFDPBE32_STROBES0_INIT_LOCTIM_RESET 0x00000002U 420 #define LRFDPBE32_STROBES0_INIT_LOCTIM_NO_EFFECT 0x00000000U 421 422 // Field: [0] TOPSM 423 // 424 // ENUMs: 425 // RESET The bit is 1 426 // NO_EFFECT The bit is 0 427 #define LRFDPBE32_STROBES0_INIT_TOPSM 0x00000001U 428 #define LRFDPBE32_STROBES0_INIT_TOPSM_M 0x00000001U 429 #define LRFDPBE32_STROBES0_INIT_TOPSM_S 0U 430 #define LRFDPBE32_STROBES0_INIT_TOPSM_RESET 0x00000001U 431 #define LRFDPBE32_STROBES0_INIT_TOPSM_NO_EFFECT 0x00000000U 432 433 //***************************************************************************** 434 // 435 // Register: LRFDPBE32_O_EVT0_IRQ 436 // 437 //***************************************************************************** 438 // Field: [31] MDMFAEMPTY 439 // 440 // ENUMs: 441 // ONE The bit is 1 442 // ZERO The bit is 0 443 #define LRFDPBE32_EVT0_IRQ_MDMFAEMPTY 0x80000000U 444 #define LRFDPBE32_EVT0_IRQ_MDMFAEMPTY_M 0x80000000U 445 #define LRFDPBE32_EVT0_IRQ_MDMFAEMPTY_S 31U 446 #define LRFDPBE32_EVT0_IRQ_MDMFAEMPTY_ONE 0x80000000U 447 #define LRFDPBE32_EVT0_IRQ_MDMFAEMPTY_ZERO 0x00000000U 448 449 // Field: [30] S2RSTOP 450 // 451 // ENUMs: 452 // ONE The bit is 1 453 // ZERO The bit is 0 454 #define LRFDPBE32_EVT0_IRQ_S2RSTOP 0x40000000U 455 #define LRFDPBE32_EVT0_IRQ_S2RSTOP_M 0x40000000U 456 #define LRFDPBE32_EVT0_IRQ_S2RSTOP_S 30U 457 #define LRFDPBE32_EVT0_IRQ_S2RSTOP_ONE 0x40000000U 458 #define LRFDPBE32_EVT0_IRQ_S2RSTOP_ZERO 0x00000000U 459 460 // Field: [29] FIFOERR 461 // 462 // ENUMs: 463 // ONE The bit is 1 464 // ZERO The bit is 0 465 #define LRFDPBE32_EVT0_IRQ_FIFOERR 0x20000000U 466 #define LRFDPBE32_EVT0_IRQ_FIFOERR_M 0x20000000U 467 #define LRFDPBE32_EVT0_IRQ_FIFOERR_S 29U 468 #define LRFDPBE32_EVT0_IRQ_FIFOERR_ONE 0x20000000U 469 #define LRFDPBE32_EVT0_IRQ_FIFOERR_ZERO 0x00000000U 470 471 // Field: [28] MDMFAFULL 472 // 473 // ENUMs: 474 // ONE The bit is 1 475 // ZERO The bit is 0 476 #define LRFDPBE32_EVT0_IRQ_MDMFAFULL 0x10000000U 477 #define LRFDPBE32_EVT0_IRQ_MDMFAFULL_M 0x10000000U 478 #define LRFDPBE32_EVT0_IRQ_MDMFAFULL_S 28U 479 #define LRFDPBE32_EVT0_IRQ_MDMFAFULL_ONE 0x10000000U 480 #define LRFDPBE32_EVT0_IRQ_MDMFAFULL_ZERO 0x00000000U 481 482 // Field: [27] SYSTCMP2 483 // 484 // ENUMs: 485 // ONE The bit is 1 486 // ZERO The bit is 0 487 #define LRFDPBE32_EVT0_IRQ_SYSTCMP2 0x08000000U 488 #define LRFDPBE32_EVT0_IRQ_SYSTCMP2_M 0x08000000U 489 #define LRFDPBE32_EVT0_IRQ_SYSTCMP2_S 27U 490 #define LRFDPBE32_EVT0_IRQ_SYSTCMP2_ONE 0x08000000U 491 #define LRFDPBE32_EVT0_IRQ_SYSTCMP2_ZERO 0x00000000U 492 493 // Field: [26] SYSTCMP1 494 // 495 // ENUMs: 496 // ONE The bit is 1 497 // ZERO The bit is 0 498 #define LRFDPBE32_EVT0_IRQ_SYSTCMP1 0x04000000U 499 #define LRFDPBE32_EVT0_IRQ_SYSTCMP1_M 0x04000000U 500 #define LRFDPBE32_EVT0_IRQ_SYSTCMP1_S 26U 501 #define LRFDPBE32_EVT0_IRQ_SYSTCMP1_ONE 0x04000000U 502 #define LRFDPBE32_EVT0_IRQ_SYSTCMP1_ZERO 0x00000000U 503 504 // Field: [25] SYSTCMP0 505 // 506 // ENUMs: 507 // ONE The bit is 1 508 // ZERO The bit is 0 509 #define LRFDPBE32_EVT0_IRQ_SYSTCMP0 0x02000000U 510 #define LRFDPBE32_EVT0_IRQ_SYSTCMP0_M 0x02000000U 511 #define LRFDPBE32_EVT0_IRQ_SYSTCMP0_S 25U 512 #define LRFDPBE32_EVT0_IRQ_SYSTCMP0_ONE 0x02000000U 513 #define LRFDPBE32_EVT0_IRQ_SYSTCMP0_ZERO 0x00000000U 514 515 // Field: [24] MDMMSGBOX 516 // 517 // ENUMs: 518 // ONE The bit is 1 519 // ZERO The bit is 0 520 #define LRFDPBE32_EVT0_IRQ_MDMMSGBOX 0x01000000U 521 #define LRFDPBE32_EVT0_IRQ_MDMMSGBOX_M 0x01000000U 522 #define LRFDPBE32_EVT0_IRQ_MDMMSGBOX_S 24U 523 #define LRFDPBE32_EVT0_IRQ_MDMMSGBOX_ONE 0x01000000U 524 #define LRFDPBE32_EVT0_IRQ_MDMMSGBOX_ZERO 0x00000000U 525 526 // Field: [23] RFEMSGBOX 527 // 528 // ENUMs: 529 // ONE The bit is 1 530 // ZERO The bit is 0 531 #define LRFDPBE32_EVT0_IRQ_RFEMSGBOX 0x00800000U 532 #define LRFDPBE32_EVT0_IRQ_RFEMSGBOX_M 0x00800000U 533 #define LRFDPBE32_EVT0_IRQ_RFEMSGBOX_S 23U 534 #define LRFDPBE32_EVT0_IRQ_RFEMSGBOX_ONE 0x00800000U 535 #define LRFDPBE32_EVT0_IRQ_RFEMSGBOX_ZERO 0x00000000U 536 537 // Field: [22] RFEDAT 538 // 539 // ENUMs: 540 // ONE The bit is 1 541 // ZERO The bit is 0 542 #define LRFDPBE32_EVT0_IRQ_RFEDAT 0x00400000U 543 #define LRFDPBE32_EVT0_IRQ_RFEDAT_M 0x00400000U 544 #define LRFDPBE32_EVT0_IRQ_RFEDAT_S 22U 545 #define LRFDPBE32_EVT0_IRQ_RFEDAT_ONE 0x00400000U 546 #define LRFDPBE32_EVT0_IRQ_RFEDAT_ZERO 0x00000000U 547 548 // Field: [21] RFECMD 549 // 550 // ENUMs: 551 // ONE The bit is 1 552 // ZERO The bit is 0 553 #define LRFDPBE32_EVT0_IRQ_RFECMD 0x00200000U 554 #define LRFDPBE32_EVT0_IRQ_RFECMD_M 0x00200000U 555 #define LRFDPBE32_EVT0_IRQ_RFECMD_S 21U 556 #define LRFDPBE32_EVT0_IRQ_RFECMD_ONE 0x00200000U 557 #define LRFDPBE32_EVT0_IRQ_RFECMD_ZERO 0x00000000U 558 559 // Field: [20] MDMDAT 560 // 561 // ENUMs: 562 // ONE The bit is 1 563 // ZERO The bit is 0 564 #define LRFDPBE32_EVT0_IRQ_MDMDAT 0x00100000U 565 #define LRFDPBE32_EVT0_IRQ_MDMDAT_M 0x00100000U 566 #define LRFDPBE32_EVT0_IRQ_MDMDAT_S 20U 567 #define LRFDPBE32_EVT0_IRQ_MDMDAT_ONE 0x00100000U 568 #define LRFDPBE32_EVT0_IRQ_MDMDAT_ZERO 0x00000000U 569 570 // Field: [19] MDMCMD 571 // 572 // ENUMs: 573 // ONE The bit is 1 574 // ZERO The bit is 0 575 #define LRFDPBE32_EVT0_IRQ_MDMCMD 0x00080000U 576 #define LRFDPBE32_EVT0_IRQ_MDMCMD_M 0x00080000U 577 #define LRFDPBE32_EVT0_IRQ_MDMCMD_S 19U 578 #define LRFDPBE32_EVT0_IRQ_MDMCMD_ONE 0x00080000U 579 #define LRFDPBE32_EVT0_IRQ_MDMCMD_ZERO 0x00000000U 580 581 // Field: [18] TIMER1 582 // 583 // ENUMs: 584 // ONE The bit is 1 585 // ZERO The bit is 0 586 #define LRFDPBE32_EVT0_IRQ_TIMER1 0x00040000U 587 #define LRFDPBE32_EVT0_IRQ_TIMER1_M 0x00040000U 588 #define LRFDPBE32_EVT0_IRQ_TIMER1_S 18U 589 #define LRFDPBE32_EVT0_IRQ_TIMER1_ONE 0x00040000U 590 #define LRFDPBE32_EVT0_IRQ_TIMER1_ZERO 0x00000000U 591 592 // Field: [17] TIMER0 593 // 594 // ENUMs: 595 // ONE The bit is 1 596 // ZERO The bit is 0 597 #define LRFDPBE32_EVT0_IRQ_TIMER0 0x00020000U 598 #define LRFDPBE32_EVT0_IRQ_TIMER0_M 0x00020000U 599 #define LRFDPBE32_EVT0_IRQ_TIMER0_S 17U 600 #define LRFDPBE32_EVT0_IRQ_TIMER0_ONE 0x00020000U 601 #define LRFDPBE32_EVT0_IRQ_TIMER0_ZERO 0x00000000U 602 603 // Field: [16] PBEAPI 604 // 605 // ENUMs: 606 // ONE The bit is 1 607 // ZERO The bit is 0 608 #define LRFDPBE32_EVT0_IRQ_PBEAPI 0x00010000U 609 #define LRFDPBE32_EVT0_IRQ_PBEAPI_M 0x00010000U 610 #define LRFDPBE32_EVT0_IRQ_PBEAPI_S 16U 611 #define LRFDPBE32_EVT0_IRQ_PBEAPI_ONE 0x00010000U 612 #define LRFDPBE32_EVT0_IRQ_PBEAPI_ZERO 0x00000000U 613 614 // Field: [15] SOFT15 615 // 616 // ENUMs: 617 // ON The bit is 1 618 // OFF The bit is 0 619 #define LRFDPBE32_EVT0_IRQ_SOFT15 0x00008000U 620 #define LRFDPBE32_EVT0_IRQ_SOFT15_M 0x00008000U 621 #define LRFDPBE32_EVT0_IRQ_SOFT15_S 15U 622 #define LRFDPBE32_EVT0_IRQ_SOFT15_ON 0x00008000U 623 #define LRFDPBE32_EVT0_IRQ_SOFT15_OFF 0x00000000U 624 625 // Field: [14] SOFT14 626 // 627 // ENUMs: 628 // ON The bit is 1 629 // OFF The bit is 0 630 #define LRFDPBE32_EVT0_IRQ_SOFT14 0x00004000U 631 #define LRFDPBE32_EVT0_IRQ_SOFT14_M 0x00004000U 632 #define LRFDPBE32_EVT0_IRQ_SOFT14_S 14U 633 #define LRFDPBE32_EVT0_IRQ_SOFT14_ON 0x00004000U 634 #define LRFDPBE32_EVT0_IRQ_SOFT14_OFF 0x00000000U 635 636 // Field: [13] SOFT13 637 // 638 // ENUMs: 639 // ON The bit is 1 640 // OFF The bit is 0 641 #define LRFDPBE32_EVT0_IRQ_SOFT13 0x00002000U 642 #define LRFDPBE32_EVT0_IRQ_SOFT13_M 0x00002000U 643 #define LRFDPBE32_EVT0_IRQ_SOFT13_S 13U 644 #define LRFDPBE32_EVT0_IRQ_SOFT13_ON 0x00002000U 645 #define LRFDPBE32_EVT0_IRQ_SOFT13_OFF 0x00000000U 646 647 // Field: [12] SOFT12 648 // 649 // ENUMs: 650 // ON The bit is 1 651 // OFF The bit is 0 652 #define LRFDPBE32_EVT0_IRQ_SOFT12 0x00001000U 653 #define LRFDPBE32_EVT0_IRQ_SOFT12_M 0x00001000U 654 #define LRFDPBE32_EVT0_IRQ_SOFT12_S 12U 655 #define LRFDPBE32_EVT0_IRQ_SOFT12_ON 0x00001000U 656 #define LRFDPBE32_EVT0_IRQ_SOFT12_OFF 0x00000000U 657 658 // Field: [11] SOFT11 659 // 660 // ENUMs: 661 // ON The bit is 1 662 // OFF The bit is 0 663 #define LRFDPBE32_EVT0_IRQ_SOFT11 0x00000800U 664 #define LRFDPBE32_EVT0_IRQ_SOFT11_M 0x00000800U 665 #define LRFDPBE32_EVT0_IRQ_SOFT11_S 11U 666 #define LRFDPBE32_EVT0_IRQ_SOFT11_ON 0x00000800U 667 #define LRFDPBE32_EVT0_IRQ_SOFT11_OFF 0x00000000U 668 669 // Field: [10] SOFT10 670 // 671 // ENUMs: 672 // ON The bit is 1 673 // OFF The bit is 0 674 #define LRFDPBE32_EVT0_IRQ_SOFT10 0x00000400U 675 #define LRFDPBE32_EVT0_IRQ_SOFT10_M 0x00000400U 676 #define LRFDPBE32_EVT0_IRQ_SOFT10_S 10U 677 #define LRFDPBE32_EVT0_IRQ_SOFT10_ON 0x00000400U 678 #define LRFDPBE32_EVT0_IRQ_SOFT10_OFF 0x00000000U 679 680 // Field: [9] SOFT9 681 // 682 // ENUMs: 683 // ON The bit is 1 684 // OFF The bit is 0 685 #define LRFDPBE32_EVT0_IRQ_SOFT9 0x00000200U 686 #define LRFDPBE32_EVT0_IRQ_SOFT9_M 0x00000200U 687 #define LRFDPBE32_EVT0_IRQ_SOFT9_S 9U 688 #define LRFDPBE32_EVT0_IRQ_SOFT9_ON 0x00000200U 689 #define LRFDPBE32_EVT0_IRQ_SOFT9_OFF 0x00000000U 690 691 // Field: [8] SOFT8 692 // 693 // ENUMs: 694 // ON The bit is 1 695 // OFF The bit is 0 696 #define LRFDPBE32_EVT0_IRQ_SOFT8 0x00000100U 697 #define LRFDPBE32_EVT0_IRQ_SOFT8_M 0x00000100U 698 #define LRFDPBE32_EVT0_IRQ_SOFT8_S 8U 699 #define LRFDPBE32_EVT0_IRQ_SOFT8_ON 0x00000100U 700 #define LRFDPBE32_EVT0_IRQ_SOFT8_OFF 0x00000000U 701 702 // Field: [7] SOFT7 703 // 704 // ENUMs: 705 // ON The bit is 1 706 // OFF The bit is 0 707 #define LRFDPBE32_EVT0_IRQ_SOFT7 0x00000080U 708 #define LRFDPBE32_EVT0_IRQ_SOFT7_M 0x00000080U 709 #define LRFDPBE32_EVT0_IRQ_SOFT7_S 7U 710 #define LRFDPBE32_EVT0_IRQ_SOFT7_ON 0x00000080U 711 #define LRFDPBE32_EVT0_IRQ_SOFT7_OFF 0x00000000U 712 713 // Field: [6] SOFT6 714 // 715 // ENUMs: 716 // ON The bit is 1 717 // OFF The bit is 0 718 #define LRFDPBE32_EVT0_IRQ_SOFT6 0x00000040U 719 #define LRFDPBE32_EVT0_IRQ_SOFT6_M 0x00000040U 720 #define LRFDPBE32_EVT0_IRQ_SOFT6_S 6U 721 #define LRFDPBE32_EVT0_IRQ_SOFT6_ON 0x00000040U 722 #define LRFDPBE32_EVT0_IRQ_SOFT6_OFF 0x00000000U 723 724 // Field: [5] SOFT5 725 // 726 // ENUMs: 727 // ON The bit is 1 728 // OFF The bit is 0 729 #define LRFDPBE32_EVT0_IRQ_SOFT5 0x00000020U 730 #define LRFDPBE32_EVT0_IRQ_SOFT5_M 0x00000020U 731 #define LRFDPBE32_EVT0_IRQ_SOFT5_S 5U 732 #define LRFDPBE32_EVT0_IRQ_SOFT5_ON 0x00000020U 733 #define LRFDPBE32_EVT0_IRQ_SOFT5_OFF 0x00000000U 734 735 // Field: [4] SOFT4 736 // 737 // ENUMs: 738 // ON The bit is 1 739 // OFF The bit is 0 740 #define LRFDPBE32_EVT0_IRQ_SOFT4 0x00000010U 741 #define LRFDPBE32_EVT0_IRQ_SOFT4_M 0x00000010U 742 #define LRFDPBE32_EVT0_IRQ_SOFT4_S 4U 743 #define LRFDPBE32_EVT0_IRQ_SOFT4_ON 0x00000010U 744 #define LRFDPBE32_EVT0_IRQ_SOFT4_OFF 0x00000000U 745 746 // Field: [3] SOFT3 747 // 748 // ENUMs: 749 // ON The bit is 1 750 // OFF The bit is 0 751 #define LRFDPBE32_EVT0_IRQ_SOFT3 0x00000008U 752 #define LRFDPBE32_EVT0_IRQ_SOFT3_M 0x00000008U 753 #define LRFDPBE32_EVT0_IRQ_SOFT3_S 3U 754 #define LRFDPBE32_EVT0_IRQ_SOFT3_ON 0x00000008U 755 #define LRFDPBE32_EVT0_IRQ_SOFT3_OFF 0x00000000U 756 757 // Field: [2] SOFT2 758 // 759 // ENUMs: 760 // ON The bit is 1 761 // OFF The bit is 0 762 #define LRFDPBE32_EVT0_IRQ_SOFT2 0x00000004U 763 #define LRFDPBE32_EVT0_IRQ_SOFT2_M 0x00000004U 764 #define LRFDPBE32_EVT0_IRQ_SOFT2_S 2U 765 #define LRFDPBE32_EVT0_IRQ_SOFT2_ON 0x00000004U 766 #define LRFDPBE32_EVT0_IRQ_SOFT2_OFF 0x00000000U 767 768 // Field: [1] SOFT1 769 // 770 // ENUMs: 771 // ON The bit is 1 772 // OFF The bit is 0 773 #define LRFDPBE32_EVT0_IRQ_SOFT1 0x00000002U 774 #define LRFDPBE32_EVT0_IRQ_SOFT1_M 0x00000002U 775 #define LRFDPBE32_EVT0_IRQ_SOFT1_S 1U 776 #define LRFDPBE32_EVT0_IRQ_SOFT1_ON 0x00000002U 777 #define LRFDPBE32_EVT0_IRQ_SOFT1_OFF 0x00000000U 778 779 // Field: [0] SOFT0 780 // 781 // ENUMs: 782 // ON The bit is 1 783 // OFF The bit is 0 784 #define LRFDPBE32_EVT0_IRQ_SOFT0 0x00000001U 785 #define LRFDPBE32_EVT0_IRQ_SOFT0_M 0x00000001U 786 #define LRFDPBE32_EVT0_IRQ_SOFT0_S 0U 787 #define LRFDPBE32_EVT0_IRQ_SOFT0_ON 0x00000001U 788 #define LRFDPBE32_EVT0_IRQ_SOFT0_OFF 0x00000000U 789 790 //***************************************************************************** 791 // 792 // Register: LRFDPBE32_O_EVTMSK0_EVT1 793 // 794 //***************************************************************************** 795 // Field: [31] MDMFAEMPTY 796 // 797 // ENUMs: 798 // EN The bit is 1 799 // DIS The bit is 0 800 #define LRFDPBE32_EVTMSK0_EVT1_MDMFAEMPTY 0x80000000U 801 #define LRFDPBE32_EVTMSK0_EVT1_MDMFAEMPTY_M 0x80000000U 802 #define LRFDPBE32_EVTMSK0_EVT1_MDMFAEMPTY_S 31U 803 #define LRFDPBE32_EVTMSK0_EVT1_MDMFAEMPTY_EN 0x80000000U 804 #define LRFDPBE32_EVTMSK0_EVT1_MDMFAEMPTY_DIS 0x00000000U 805 806 // Field: [30] S2RSTOP 807 // 808 // ENUMs: 809 // EN The bit is 1 810 // DIS The bit is 0 811 #define LRFDPBE32_EVTMSK0_EVT1_S2RSTOP 0x40000000U 812 #define LRFDPBE32_EVTMSK0_EVT1_S2RSTOP_M 0x40000000U 813 #define LRFDPBE32_EVTMSK0_EVT1_S2RSTOP_S 30U 814 #define LRFDPBE32_EVTMSK0_EVT1_S2RSTOP_EN 0x40000000U 815 #define LRFDPBE32_EVTMSK0_EVT1_S2RSTOP_DIS 0x00000000U 816 817 // Field: [29] FIFOERR 818 // 819 // ENUMs: 820 // EN The bit is 1 821 // DIS The bit is 0 822 #define LRFDPBE32_EVTMSK0_EVT1_FIFOERR 0x20000000U 823 #define LRFDPBE32_EVTMSK0_EVT1_FIFOERR_M 0x20000000U 824 #define LRFDPBE32_EVTMSK0_EVT1_FIFOERR_S 29U 825 #define LRFDPBE32_EVTMSK0_EVT1_FIFOERR_EN 0x20000000U 826 #define LRFDPBE32_EVTMSK0_EVT1_FIFOERR_DIS 0x00000000U 827 828 // Field: [28] MDMFAFULL 829 // 830 // ENUMs: 831 // EN The bit is 1 832 // DIS The bit is 0 833 #define LRFDPBE32_EVTMSK0_EVT1_MDMFAFULL 0x10000000U 834 #define LRFDPBE32_EVTMSK0_EVT1_MDMFAFULL_M 0x10000000U 835 #define LRFDPBE32_EVTMSK0_EVT1_MDMFAFULL_S 28U 836 #define LRFDPBE32_EVTMSK0_EVT1_MDMFAFULL_EN 0x10000000U 837 #define LRFDPBE32_EVTMSK0_EVT1_MDMFAFULL_DIS 0x00000000U 838 839 // Field: [27] SYSTCMP2 840 // 841 // ENUMs: 842 // EN The bit is 1 843 // DIS The bit is 0 844 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP2 0x08000000U 845 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP2_M 0x08000000U 846 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP2_S 27U 847 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP2_EN 0x08000000U 848 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP2_DIS 0x00000000U 849 850 // Field: [26] SYSTCMP1 851 // 852 // ENUMs: 853 // EN The bit is 1 854 // DIS The bit is 0 855 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP1 0x04000000U 856 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP1_M 0x04000000U 857 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP1_S 26U 858 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP1_EN 0x04000000U 859 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP1_DIS 0x00000000U 860 861 // Field: [25] SYSTCMP0 862 // 863 // ENUMs: 864 // EN The bit is 1 865 // DIS The bit is 0 866 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP0 0x02000000U 867 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP0_M 0x02000000U 868 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP0_S 25U 869 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP0_EN 0x02000000U 870 #define LRFDPBE32_EVTMSK0_EVT1_SYSTCMP0_DIS 0x00000000U 871 872 // Field: [24] MDMMSGBOX 873 // 874 // ENUMs: 875 // EN The bit is 1 876 // DIS The bit is 0 877 #define LRFDPBE32_EVTMSK0_EVT1_MDMMSGBOX 0x01000000U 878 #define LRFDPBE32_EVTMSK0_EVT1_MDMMSGBOX_M 0x01000000U 879 #define LRFDPBE32_EVTMSK0_EVT1_MDMMSGBOX_S 24U 880 #define LRFDPBE32_EVTMSK0_EVT1_MDMMSGBOX_EN 0x01000000U 881 #define LRFDPBE32_EVTMSK0_EVT1_MDMMSGBOX_DIS 0x00000000U 882 883 // Field: [23] RFEMSGBOX 884 // 885 // ENUMs: 886 // EN The bit is 1 887 // DIS The bit is 0 888 #define LRFDPBE32_EVTMSK0_EVT1_RFEMSGBOX 0x00800000U 889 #define LRFDPBE32_EVTMSK0_EVT1_RFEMSGBOX_M 0x00800000U 890 #define LRFDPBE32_EVTMSK0_EVT1_RFEMSGBOX_S 23U 891 #define LRFDPBE32_EVTMSK0_EVT1_RFEMSGBOX_EN 0x00800000U 892 #define LRFDPBE32_EVTMSK0_EVT1_RFEMSGBOX_DIS 0x00000000U 893 894 // Field: [22] RFEDAT 895 // 896 // ENUMs: 897 // EN The bit is 1 898 // DIS The bit is 0 899 #define LRFDPBE32_EVTMSK0_EVT1_RFEDAT 0x00400000U 900 #define LRFDPBE32_EVTMSK0_EVT1_RFEDAT_M 0x00400000U 901 #define LRFDPBE32_EVTMSK0_EVT1_RFEDAT_S 22U 902 #define LRFDPBE32_EVTMSK0_EVT1_RFEDAT_EN 0x00400000U 903 #define LRFDPBE32_EVTMSK0_EVT1_RFEDAT_DIS 0x00000000U 904 905 // Field: [21] RFECMD 906 // 907 // ENUMs: 908 // EN The bit is 1 909 // DIS The bit is 0 910 #define LRFDPBE32_EVTMSK0_EVT1_RFECMD 0x00200000U 911 #define LRFDPBE32_EVTMSK0_EVT1_RFECMD_M 0x00200000U 912 #define LRFDPBE32_EVTMSK0_EVT1_RFECMD_S 21U 913 #define LRFDPBE32_EVTMSK0_EVT1_RFECMD_EN 0x00200000U 914 #define LRFDPBE32_EVTMSK0_EVT1_RFECMD_DIS 0x00000000U 915 916 // Field: [20] MDMDAT 917 // 918 // ENUMs: 919 // EN The bit is 1 920 // DIS The bit is 0 921 #define LRFDPBE32_EVTMSK0_EVT1_MDMDAT 0x00100000U 922 #define LRFDPBE32_EVTMSK0_EVT1_MDMDAT_M 0x00100000U 923 #define LRFDPBE32_EVTMSK0_EVT1_MDMDAT_S 20U 924 #define LRFDPBE32_EVTMSK0_EVT1_MDMDAT_EN 0x00100000U 925 #define LRFDPBE32_EVTMSK0_EVT1_MDMDAT_DIS 0x00000000U 926 927 // Field: [19] MDMCMD 928 // 929 // ENUMs: 930 // EN The bit is 1 931 // DIS The bit is 0 932 #define LRFDPBE32_EVTMSK0_EVT1_MDMCMD 0x00080000U 933 #define LRFDPBE32_EVTMSK0_EVT1_MDMCMD_M 0x00080000U 934 #define LRFDPBE32_EVTMSK0_EVT1_MDMCMD_S 19U 935 #define LRFDPBE32_EVTMSK0_EVT1_MDMCMD_EN 0x00080000U 936 #define LRFDPBE32_EVTMSK0_EVT1_MDMCMD_DIS 0x00000000U 937 938 // Field: [18] TIMER1 939 // 940 // ENUMs: 941 // EN The bit is 1 942 // DIS The bit is 0 943 #define LRFDPBE32_EVTMSK0_EVT1_TIMER1 0x00040000U 944 #define LRFDPBE32_EVTMSK0_EVT1_TIMER1_M 0x00040000U 945 #define LRFDPBE32_EVTMSK0_EVT1_TIMER1_S 18U 946 #define LRFDPBE32_EVTMSK0_EVT1_TIMER1_EN 0x00040000U 947 #define LRFDPBE32_EVTMSK0_EVT1_TIMER1_DIS 0x00000000U 948 949 // Field: [17] TIMER0 950 // 951 // ENUMs: 952 // EN The bit is 1 953 // DIS The bit is 0 954 #define LRFDPBE32_EVTMSK0_EVT1_TIMER0 0x00020000U 955 #define LRFDPBE32_EVTMSK0_EVT1_TIMER0_M 0x00020000U 956 #define LRFDPBE32_EVTMSK0_EVT1_TIMER0_S 17U 957 #define LRFDPBE32_EVTMSK0_EVT1_TIMER0_EN 0x00020000U 958 #define LRFDPBE32_EVTMSK0_EVT1_TIMER0_DIS 0x00000000U 959 960 // Field: [16] PBEAPI 961 // 962 // ENUMs: 963 // EN The bit is 1 964 // DIS The bit is 0 965 #define LRFDPBE32_EVTMSK0_EVT1_PBEAPI 0x00010000U 966 #define LRFDPBE32_EVTMSK0_EVT1_PBEAPI_M 0x00010000U 967 #define LRFDPBE32_EVTMSK0_EVT1_PBEAPI_S 16U 968 #define LRFDPBE32_EVTMSK0_EVT1_PBEAPI_EN 0x00010000U 969 #define LRFDPBE32_EVTMSK0_EVT1_PBEAPI_DIS 0x00000000U 970 971 // Field: [12] TXRDBTHR 972 // 973 // ENUMs: 974 // MET The TX FIFO contains TXFRBTHRS or more readable 975 // bytes. 976 // BELOW The TX FIFO contains less than the threshold 977 // TXFRBTHRS readable bytes. 978 #define LRFDPBE32_EVTMSK0_EVT1_TXRDBTHR 0x00001000U 979 #define LRFDPBE32_EVTMSK0_EVT1_TXRDBTHR_M 0x00001000U 980 #define LRFDPBE32_EVTMSK0_EVT1_TXRDBTHR_S 12U 981 #define LRFDPBE32_EVTMSK0_EVT1_TXRDBTHR_MET 0x00001000U 982 #define LRFDPBE32_EVTMSK0_EVT1_TXRDBTHR_BELOW 0x00000000U 983 984 // Field: [11] TXWRBTHR 985 // 986 // ENUMs: 987 // MET The TX FIFO contains TXFWBTHRS or more writable 988 // bytes. 989 // BELOW The TX FIFO contains less than the threshold 990 // TXFWBTHRS writable bytes. 991 #define LRFDPBE32_EVTMSK0_EVT1_TXWRBTHR 0x00000800U 992 #define LRFDPBE32_EVTMSK0_EVT1_TXWRBTHR_M 0x00000800U 993 #define LRFDPBE32_EVTMSK0_EVT1_TXWRBTHR_S 11U 994 #define LRFDPBE32_EVTMSK0_EVT1_TXWRBTHR_MET 0x00000800U 995 #define LRFDPBE32_EVTMSK0_EVT1_TXWRBTHR_BELOW 0x00000000U 996 997 // Field: [10] RXRDBTHR 998 // 999 // ENUMs: 1000 // MET The TX FIFO contains TXFRBTHRS or more readable 1001 // bytes. 1002 // BELOW The TX FIFO contains less than the threshold 1003 // TXFRBTHRS readable bytes. 1004 #define LRFDPBE32_EVTMSK0_EVT1_RXRDBTHR 0x00000400U 1005 #define LRFDPBE32_EVTMSK0_EVT1_RXRDBTHR_M 0x00000400U 1006 #define LRFDPBE32_EVTMSK0_EVT1_RXRDBTHR_S 10U 1007 #define LRFDPBE32_EVTMSK0_EVT1_RXRDBTHR_MET 0x00000400U 1008 #define LRFDPBE32_EVTMSK0_EVT1_RXRDBTHR_BELOW 0x00000000U 1009 1010 // Field: [9] RXWRBTHR 1011 // 1012 // ENUMs: 1013 // MET The RX FIFO contains RXFWBTHRS or more writable 1014 // bytes. 1015 // BELOW The RX FIFO contains less than the threshold 1016 // RXFWBTHRS writable bytes. 1017 #define LRFDPBE32_EVTMSK0_EVT1_RXWRBTHR 0x00000200U 1018 #define LRFDPBE32_EVTMSK0_EVT1_RXWRBTHR_M 0x00000200U 1019 #define LRFDPBE32_EVTMSK0_EVT1_RXWRBTHR_S 9U 1020 #define LRFDPBE32_EVTMSK0_EVT1_RXWRBTHR_MET 0x00000200U 1021 #define LRFDPBE32_EVTMSK0_EVT1_RXWRBTHR_BELOW 0x00000000U 1022 1023 // Field: [8] MDMPROG 1024 // 1025 // ENUMs: 1026 // ONE The bit is 1 1027 // ZERO The bit is 0 1028 #define LRFDPBE32_EVTMSK0_EVT1_MDMPROG 0x00000100U 1029 #define LRFDPBE32_EVTMSK0_EVT1_MDMPROG_M 0x00000100U 1030 #define LRFDPBE32_EVTMSK0_EVT1_MDMPROG_S 8U 1031 #define LRFDPBE32_EVTMSK0_EVT1_MDMPROG_ONE 0x00000100U 1032 #define LRFDPBE32_EVTMSK0_EVT1_MDMPROG_ZERO 0x00000000U 1033 1034 // Field: [7] PBEGPI7 1035 // 1036 // ENUMs: 1037 // ONE The bit is 1 1038 // ZERO The bit is 0 1039 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI7 0x00000080U 1040 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI7_M 0x00000080U 1041 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI7_S 7U 1042 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI7_ONE 0x00000080U 1043 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI7_ZERO 0x00000000U 1044 1045 // Field: [6] PBEGPI6 1046 // 1047 // ENUMs: 1048 // ONE The bit is 1 1049 // ZERO The bit is 0 1050 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI6 0x00000040U 1051 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI6_M 0x00000040U 1052 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI6_S 6U 1053 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI6_ONE 0x00000040U 1054 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI6_ZERO 0x00000000U 1055 1056 // Field: [5] PBEGPI5 1057 // 1058 // ENUMs: 1059 // ONE The bit is 1 1060 // ZERO The bit is 0 1061 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI5 0x00000020U 1062 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI5_M 0x00000020U 1063 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI5_S 5U 1064 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI5_ONE 0x00000020U 1065 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI5_ZERO 0x00000000U 1066 1067 // Field: [4] PBEGPI4 1068 // 1069 // ENUMs: 1070 // ONE The bit is 1 1071 // ZERO The bit is 0 1072 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI4 0x00000010U 1073 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI4_M 0x00000010U 1074 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI4_S 4U 1075 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI4_ONE 0x00000010U 1076 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI4_ZERO 0x00000000U 1077 1078 // Field: [3] PBEGPI3 1079 // 1080 // ENUMs: 1081 // ONE The bit is 1 1082 // ZERO The bit is 0 1083 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI3 0x00000008U 1084 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI3_M 0x00000008U 1085 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI3_S 3U 1086 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI3_ONE 0x00000008U 1087 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI3_ZERO 0x00000000U 1088 1089 // Field: [2] PBEGPI2 1090 // 1091 // ENUMs: 1092 // ONE The bit is 1 1093 // ZERO The bit is 0 1094 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI2 0x00000004U 1095 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI2_M 0x00000004U 1096 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI2_S 2U 1097 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI2_ONE 0x00000004U 1098 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI2_ZERO 0x00000000U 1099 1100 // Field: [1] PBEGPI1 1101 // 1102 // ENUMs: 1103 // ONE The bit is 1 1104 // ZERO The bit is 0 1105 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI1 0x00000002U 1106 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI1_M 0x00000002U 1107 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI1_S 1U 1108 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI1_ONE 0x00000002U 1109 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI1_ZERO 0x00000000U 1110 1111 // Field: [0] PBEGPI0 1112 // 1113 // ENUMs: 1114 // ONE The bit is 1 1115 // ZERO The bit is 0 1116 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI0 0x00000001U 1117 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI0_M 0x00000001U 1118 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI0_S 0U 1119 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI0_ONE 0x00000001U 1120 #define LRFDPBE32_EVTMSK0_EVT1_PBEGPI0_ZERO 0x00000000U 1121 1122 //***************************************************************************** 1123 // 1124 // Register: LRFDPBE32_O_EVTCLR0_EVTMSK1 1125 // 1126 //***************************************************************************** 1127 // Field: [31] MDMFAEMPTY 1128 // 1129 // ENUMs: 1130 // CLEAR The bit is 1 1131 // RETAIN The bit is 0 1132 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAEMPTY 0x80000000U 1133 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAEMPTY_M 0x80000000U 1134 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAEMPTY_S 31U 1135 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAEMPTY_CLEAR 0x80000000U 1136 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAEMPTY_RETAIN 0x00000000U 1137 1138 // Field: [30] S2RSTOP 1139 // 1140 // ENUMs: 1141 // CLEAR The bit is 1 1142 // RETAIN The bit is 0 1143 #define LRFDPBE32_EVTCLR0_EVTMSK1_S2RSTOP 0x40000000U 1144 #define LRFDPBE32_EVTCLR0_EVTMSK1_S2RSTOP_M 0x40000000U 1145 #define LRFDPBE32_EVTCLR0_EVTMSK1_S2RSTOP_S 30U 1146 #define LRFDPBE32_EVTCLR0_EVTMSK1_S2RSTOP_CLEAR 0x40000000U 1147 #define LRFDPBE32_EVTCLR0_EVTMSK1_S2RSTOP_RETAIN 0x00000000U 1148 1149 // Field: [29] FIFOERR 1150 // 1151 // ENUMs: 1152 // CLEAR The bit is 1 1153 // RETAIN The bit is 0 1154 #define LRFDPBE32_EVTCLR0_EVTMSK1_FIFOERR 0x20000000U 1155 #define LRFDPBE32_EVTCLR0_EVTMSK1_FIFOERR_M 0x20000000U 1156 #define LRFDPBE32_EVTCLR0_EVTMSK1_FIFOERR_S 29U 1157 #define LRFDPBE32_EVTCLR0_EVTMSK1_FIFOERR_CLEAR 0x20000000U 1158 #define LRFDPBE32_EVTCLR0_EVTMSK1_FIFOERR_RETAIN 0x00000000U 1159 1160 // Field: [28] MDMFAFULL 1161 // 1162 // ENUMs: 1163 // CLEAR The bit is 1 1164 // RETAIN The bit is 0 1165 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAFULL 0x10000000U 1166 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAFULL_M 0x10000000U 1167 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAFULL_S 28U 1168 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAFULL_CLEAR 0x10000000U 1169 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMFAFULL_RETAIN 0x00000000U 1170 1171 // Field: [27] SYSTCMP2 1172 // 1173 // ENUMs: 1174 // CLEAR The bit is 1 1175 // RETAIN The bit is 0 1176 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP2 0x08000000U 1177 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP2_M 0x08000000U 1178 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP2_S 27U 1179 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP2_CLEAR 0x08000000U 1180 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP2_RETAIN 0x00000000U 1181 1182 // Field: [26] SYSTCMP1 1183 // 1184 // ENUMs: 1185 // CLEAR The bit is 1 1186 // RETAIN The bit is 0 1187 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP1 0x04000000U 1188 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP1_M 0x04000000U 1189 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP1_S 26U 1190 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP1_CLEAR 0x04000000U 1191 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP1_RETAIN 0x00000000U 1192 1193 // Field: [25] SYSTCMP0 1194 // 1195 // ENUMs: 1196 // CLEAR The bit is 1 1197 // RETAIN The bit is 0 1198 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP0 0x02000000U 1199 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP0_M 0x02000000U 1200 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP0_S 25U 1201 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP0_CLEAR 0x02000000U 1202 #define LRFDPBE32_EVTCLR0_EVTMSK1_SYSTCMP0_RETAIN 0x00000000U 1203 1204 // Field: [24] MDMMSGBOX 1205 // 1206 // ENUMs: 1207 // CLEAR The bit is 1 1208 // RETAIN The bit is 0 1209 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMMSGBOX 0x01000000U 1210 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMMSGBOX_M 0x01000000U 1211 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMMSGBOX_S 24U 1212 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMMSGBOX_CLEAR 0x01000000U 1213 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMMSGBOX_RETAIN 0x00000000U 1214 1215 // Field: [23] RFEMSGBOX 1216 // 1217 // ENUMs: 1218 // CLEAR The bit is 1 1219 // RETAIN The bit is 0 1220 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFEMSGBOX 0x00800000U 1221 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFEMSGBOX_M 0x00800000U 1222 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFEMSGBOX_S 23U 1223 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFEMSGBOX_CLEAR 0x00800000U 1224 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFEMSGBOX_RETAIN 0x00000000U 1225 1226 // Field: [22] RFEDAT 1227 // 1228 // ENUMs: 1229 // CLEAR The bit is 1 1230 // RETAIN The bit is 0 1231 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFEDAT 0x00400000U 1232 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFEDAT_M 0x00400000U 1233 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFEDAT_S 22U 1234 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFEDAT_CLEAR 0x00400000U 1235 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFEDAT_RETAIN 0x00000000U 1236 1237 // Field: [21] RFECMD 1238 // 1239 // ENUMs: 1240 // CLEAR The bit is 1 1241 // RETAIN The bit is 0 1242 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFECMD 0x00200000U 1243 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFECMD_M 0x00200000U 1244 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFECMD_S 21U 1245 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFECMD_CLEAR 0x00200000U 1246 #define LRFDPBE32_EVTCLR0_EVTMSK1_RFECMD_RETAIN 0x00000000U 1247 1248 // Field: [20] MDMDAT 1249 // 1250 // ENUMs: 1251 // CLEAR The bit is 1 1252 // RETAIN The bit is 0 1253 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMDAT 0x00100000U 1254 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMDAT_M 0x00100000U 1255 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMDAT_S 20U 1256 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMDAT_CLEAR 0x00100000U 1257 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMDAT_RETAIN 0x00000000U 1258 1259 // Field: [19] MDMCMD 1260 // 1261 // ENUMs: 1262 // CLEAR The bit is 1 1263 // RETAIN The bit is 0 1264 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMCMD 0x00080000U 1265 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMCMD_M 0x00080000U 1266 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMCMD_S 19U 1267 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMCMD_CLEAR 0x00080000U 1268 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMCMD_RETAIN 0x00000000U 1269 1270 // Field: [18] TIMER1 1271 // 1272 // ENUMs: 1273 // CLEAR The bit is 1 1274 // RETAIN The bit is 0 1275 #define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER1 0x00040000U 1276 #define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER1_M 0x00040000U 1277 #define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER1_S 18U 1278 #define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER1_CLEAR 0x00040000U 1279 #define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER1_RETAIN 0x00000000U 1280 1281 // Field: [17] TIMER0 1282 // 1283 // ENUMs: 1284 // CLEAR The bit is 1 1285 // RETAIN The bit is 0 1286 #define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER0 0x00020000U 1287 #define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER0_M 0x00020000U 1288 #define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER0_S 17U 1289 #define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER0_CLEAR 0x00020000U 1290 #define LRFDPBE32_EVTCLR0_EVTMSK1_TIMER0_RETAIN 0x00000000U 1291 1292 // Field: [16] PBEAPI 1293 // 1294 // ENUMs: 1295 // CLEAR The bit is 1 1296 // RETAIN The bit is 0 1297 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEAPI 0x00010000U 1298 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEAPI_M 0x00010000U 1299 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEAPI_S 16U 1300 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEAPI_CLEAR 0x00010000U 1301 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEAPI_RETAIN 0x00000000U 1302 1303 // Field: [12] TXRDBTHR 1304 // 1305 // ENUMs: 1306 // EN The TX FIFO contains TXFRBTHRS or more readable 1307 // bytes. 1308 // DIS The TX FIFO contains less than the threshold 1309 // TXFRBTHRS readable bytes. 1310 #define LRFDPBE32_EVTCLR0_EVTMSK1_TXRDBTHR 0x00001000U 1311 #define LRFDPBE32_EVTCLR0_EVTMSK1_TXRDBTHR_M 0x00001000U 1312 #define LRFDPBE32_EVTCLR0_EVTMSK1_TXRDBTHR_S 12U 1313 #define LRFDPBE32_EVTCLR0_EVTMSK1_TXRDBTHR_EN 0x00001000U 1314 #define LRFDPBE32_EVTCLR0_EVTMSK1_TXRDBTHR_DIS 0x00000000U 1315 1316 // Field: [11] TXWRBTHR 1317 // 1318 // ENUMs: 1319 // EN The TX FIFO contains TXFWBTHRS or more writable 1320 // bytes. 1321 // DIS The TX FIFO contains less than the threshold 1322 // TXFWBTHRS writable bytes. 1323 #define LRFDPBE32_EVTCLR0_EVTMSK1_TXWRBTHR 0x00000800U 1324 #define LRFDPBE32_EVTCLR0_EVTMSK1_TXWRBTHR_M 0x00000800U 1325 #define LRFDPBE32_EVTCLR0_EVTMSK1_TXWRBTHR_S 11U 1326 #define LRFDPBE32_EVTCLR0_EVTMSK1_TXWRBTHR_EN 0x00000800U 1327 #define LRFDPBE32_EVTCLR0_EVTMSK1_TXWRBTHR_DIS 0x00000000U 1328 1329 // Field: [10] RXRDBTHR 1330 // 1331 // ENUMs: 1332 // EN The TX FIFO contains TXFWBTHRS or more writable 1333 // bytes. 1334 // DIS The TX FIFO contains less than the threshold 1335 // TXFWBTHRS writable bytes. 1336 #define LRFDPBE32_EVTCLR0_EVTMSK1_RXRDBTHR 0x00000400U 1337 #define LRFDPBE32_EVTCLR0_EVTMSK1_RXRDBTHR_M 0x00000400U 1338 #define LRFDPBE32_EVTCLR0_EVTMSK1_RXRDBTHR_S 10U 1339 #define LRFDPBE32_EVTCLR0_EVTMSK1_RXRDBTHR_EN 0x00000400U 1340 #define LRFDPBE32_EVTCLR0_EVTMSK1_RXRDBTHR_DIS 0x00000000U 1341 1342 // Field: [9] RXWRBTHR 1343 // 1344 // ENUMs: 1345 // EN The TX FIFO contains TXFWBTHRS or more writable 1346 // bytes. 1347 // DIS The TX FIFO contains less than the threshold 1348 // TXFWBTHRS writable bytes. 1349 #define LRFDPBE32_EVTCLR0_EVTMSK1_RXWRBTHR 0x00000200U 1350 #define LRFDPBE32_EVTCLR0_EVTMSK1_RXWRBTHR_M 0x00000200U 1351 #define LRFDPBE32_EVTCLR0_EVTMSK1_RXWRBTHR_S 9U 1352 #define LRFDPBE32_EVTCLR0_EVTMSK1_RXWRBTHR_EN 0x00000200U 1353 #define LRFDPBE32_EVTCLR0_EVTMSK1_RXWRBTHR_DIS 0x00000000U 1354 1355 // Field: [8] MDMPROG 1356 // 1357 // ENUMs: 1358 // EN The bit is 1 1359 // DIS The bit is 0 1360 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMPROG 0x00000100U 1361 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMPROG_M 0x00000100U 1362 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMPROG_S 8U 1363 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMPROG_EN 0x00000100U 1364 #define LRFDPBE32_EVTCLR0_EVTMSK1_MDMPROG_DIS 0x00000000U 1365 1366 // Field: [7] PBEGPI7 1367 // 1368 // ENUMs: 1369 // EN The bit is 1 1370 // DIS The bit is 0 1371 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI7 0x00000080U 1372 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI7_M 0x00000080U 1373 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI7_S 7U 1374 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI7_EN 0x00000080U 1375 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI7_DIS 0x00000000U 1376 1377 // Field: [6] PBEGPI6 1378 // 1379 // ENUMs: 1380 // EN The bit is 1 1381 // DIS The bit is 0 1382 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI6 0x00000040U 1383 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI6_M 0x00000040U 1384 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI6_S 6U 1385 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI6_EN 0x00000040U 1386 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI6_DIS 0x00000000U 1387 1388 // Field: [5] PBEGPI5 1389 // 1390 // ENUMs: 1391 // EN The bit is 1 1392 // DIS The bit is 0 1393 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI5 0x00000020U 1394 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI5_M 0x00000020U 1395 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI5_S 5U 1396 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI5_EN 0x00000020U 1397 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI5_DIS 0x00000000U 1398 1399 // Field: [4] PBEGPI4 1400 // 1401 // ENUMs: 1402 // EN The bit is 1 1403 // DIS The bit is 0 1404 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI4 0x00000010U 1405 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI4_M 0x00000010U 1406 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI4_S 4U 1407 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI4_EN 0x00000010U 1408 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI4_DIS 0x00000000U 1409 1410 // Field: [3] PBEGPI3 1411 // 1412 // ENUMs: 1413 // EN The bit is 1 1414 // DIS The bit is 0 1415 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI3 0x00000008U 1416 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI3_M 0x00000008U 1417 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI3_S 3U 1418 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI3_EN 0x00000008U 1419 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI3_DIS 0x00000000U 1420 1421 // Field: [2] PBEGPI2 1422 // 1423 // ENUMs: 1424 // EN The bit is 1 1425 // DIS The bit is 0 1426 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI2 0x00000004U 1427 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI2_M 0x00000004U 1428 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI2_S 2U 1429 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI2_EN 0x00000004U 1430 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI2_DIS 0x00000000U 1431 1432 // Field: [1] PBEGPI1 1433 // 1434 // ENUMs: 1435 // EN The bit is 1 1436 // DIS The bit is 0 1437 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI1 0x00000002U 1438 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI1_M 0x00000002U 1439 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI1_S 1U 1440 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI1_EN 0x00000002U 1441 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI1_DIS 0x00000000U 1442 1443 // Field: [0] PBEGPI0 1444 // 1445 // ENUMs: 1446 // EN The bit is 1 1447 // DIS The bit is 0 1448 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI0 0x00000001U 1449 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI0_M 0x00000001U 1450 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI0_S 0U 1451 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI0_EN 0x00000001U 1452 #define LRFDPBE32_EVTCLR0_EVTMSK1_PBEGPI0_DIS 0x00000000U 1453 1454 //***************************************************************************** 1455 // 1456 // Register: LRFDPBE32_O_PDREQ_EVTCLR1 1457 // 1458 //***************************************************************************** 1459 // Field: [16] TOPSMPDREQ 1460 // 1461 // ENUMs: 1462 // ON The bit is 1 1463 // OFF The bit is 0 1464 #define LRFDPBE32_PDREQ_EVTCLR1_TOPSMPDREQ 0x00010000U 1465 #define LRFDPBE32_PDREQ_EVTCLR1_TOPSMPDREQ_M 0x00010000U 1466 #define LRFDPBE32_PDREQ_EVTCLR1_TOPSMPDREQ_S 16U 1467 #define LRFDPBE32_PDREQ_EVTCLR1_TOPSMPDREQ_ON 0x00010000U 1468 #define LRFDPBE32_PDREQ_EVTCLR1_TOPSMPDREQ_OFF 0x00000000U 1469 1470 // Field: [12] TXRDBTHR 1471 // 1472 // ENUMs: 1473 // CLEAR The bit is 1 1474 // RETAIN The bit is 0 1475 #define LRFDPBE32_PDREQ_EVTCLR1_TXRDBTHR 0x00001000U 1476 #define LRFDPBE32_PDREQ_EVTCLR1_TXRDBTHR_M 0x00001000U 1477 #define LRFDPBE32_PDREQ_EVTCLR1_TXRDBTHR_S 12U 1478 #define LRFDPBE32_PDREQ_EVTCLR1_TXRDBTHR_CLEAR 0x00001000U 1479 #define LRFDPBE32_PDREQ_EVTCLR1_TXRDBTHR_RETAIN 0x00000000U 1480 1481 // Field: [11] TXWRBTHR 1482 // 1483 // ENUMs: 1484 // CLEAR The bit is 1 1485 // RETAIN The bit is 0 1486 #define LRFDPBE32_PDREQ_EVTCLR1_TXWRBTHR 0x00000800U 1487 #define LRFDPBE32_PDREQ_EVTCLR1_TXWRBTHR_M 0x00000800U 1488 #define LRFDPBE32_PDREQ_EVTCLR1_TXWRBTHR_S 11U 1489 #define LRFDPBE32_PDREQ_EVTCLR1_TXWRBTHR_CLEAR 0x00000800U 1490 #define LRFDPBE32_PDREQ_EVTCLR1_TXWRBTHR_RETAIN 0x00000000U 1491 1492 // Field: [10] RXRDBTHR 1493 // 1494 // ENUMs: 1495 // CLEAR The bit is 1 1496 // RETAIN The bit is 0 1497 #define LRFDPBE32_PDREQ_EVTCLR1_RXRDBTHR 0x00000400U 1498 #define LRFDPBE32_PDREQ_EVTCLR1_RXRDBTHR_M 0x00000400U 1499 #define LRFDPBE32_PDREQ_EVTCLR1_RXRDBTHR_S 10U 1500 #define LRFDPBE32_PDREQ_EVTCLR1_RXRDBTHR_CLEAR 0x00000400U 1501 #define LRFDPBE32_PDREQ_EVTCLR1_RXRDBTHR_RETAIN 0x00000000U 1502 1503 // Field: [9] RXWRBTHR 1504 // 1505 // ENUMs: 1506 // CLEAR The bit is 1 1507 // RETAIN The bit is 0 1508 #define LRFDPBE32_PDREQ_EVTCLR1_RXWRBTHR 0x00000200U 1509 #define LRFDPBE32_PDREQ_EVTCLR1_RXWRBTHR_M 0x00000200U 1510 #define LRFDPBE32_PDREQ_EVTCLR1_RXWRBTHR_S 9U 1511 #define LRFDPBE32_PDREQ_EVTCLR1_RXWRBTHR_CLEAR 0x00000200U 1512 #define LRFDPBE32_PDREQ_EVTCLR1_RXWRBTHR_RETAIN 0x00000000U 1513 1514 // Field: [8] MDMPROG 1515 // 1516 // ENUMs: 1517 // CLEAR The bit is 1 1518 // RETAIN The bit is 0 1519 #define LRFDPBE32_PDREQ_EVTCLR1_MDMPROG 0x00000100U 1520 #define LRFDPBE32_PDREQ_EVTCLR1_MDMPROG_M 0x00000100U 1521 #define LRFDPBE32_PDREQ_EVTCLR1_MDMPROG_S 8U 1522 #define LRFDPBE32_PDREQ_EVTCLR1_MDMPROG_CLEAR 0x00000100U 1523 #define LRFDPBE32_PDREQ_EVTCLR1_MDMPROG_RETAIN 0x00000000U 1524 1525 // Field: [7] PBEGPI7 1526 // 1527 // ENUMs: 1528 // CLEAR The bit is 1 1529 // RETAIN The bit is 0 1530 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI7 0x00000080U 1531 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI7_M 0x00000080U 1532 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI7_S 7U 1533 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI7_CLEAR 0x00000080U 1534 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI7_RETAIN 0x00000000U 1535 1536 // Field: [6] PBEGPI6 1537 // 1538 // ENUMs: 1539 // CLEAR The bit is 1 1540 // RETAIN The bit is 0 1541 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI6 0x00000040U 1542 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI6_M 0x00000040U 1543 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI6_S 6U 1544 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI6_CLEAR 0x00000040U 1545 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI6_RETAIN 0x00000000U 1546 1547 // Field: [5] PBEGPI5 1548 // 1549 // ENUMs: 1550 // CLEAR The bit is 1 1551 // RETAIN The bit is 0 1552 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI5 0x00000020U 1553 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI5_M 0x00000020U 1554 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI5_S 5U 1555 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI5_CLEAR 0x00000020U 1556 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI5_RETAIN 0x00000000U 1557 1558 // Field: [4] PBEGPI4 1559 // 1560 // ENUMs: 1561 // CLEAR The bit is 1 1562 // RETAIN The bit is 0 1563 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI4 0x00000010U 1564 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI4_M 0x00000010U 1565 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI4_S 4U 1566 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI4_CLEAR 0x00000010U 1567 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI4_RETAIN 0x00000000U 1568 1569 // Field: [3] PBEGPI3 1570 // 1571 // ENUMs: 1572 // CLEAR The bit is 1 1573 // RETAIN The bit is 0 1574 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI3 0x00000008U 1575 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI3_M 0x00000008U 1576 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI3_S 3U 1577 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI3_CLEAR 0x00000008U 1578 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI3_RETAIN 0x00000000U 1579 1580 // Field: [2] PBEGPI2 1581 // 1582 // ENUMs: 1583 // CLEAR The bit is 1 1584 // RETAIN The bit is 0 1585 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI2 0x00000004U 1586 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI2_M 0x00000004U 1587 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI2_S 2U 1588 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI2_CLEAR 0x00000004U 1589 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI2_RETAIN 0x00000000U 1590 1591 // Field: [1] PBEGPI1 1592 // 1593 // ENUMs: 1594 // CLEAR The bit is 1 1595 // RETAIN The bit is 0 1596 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI1 0x00000002U 1597 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI1_M 0x00000002U 1598 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI1_S 1U 1599 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI1_CLEAR 0x00000002U 1600 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI1_RETAIN 0x00000000U 1601 1602 // Field: [0] PBEGPI0 1603 // 1604 // ENUMs: 1605 // CLEAR The bit is 1 1606 // RETAIN The bit is 0 1607 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI0 0x00000001U 1608 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI0_M 0x00000001U 1609 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI0_S 0U 1610 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI0_CLEAR 0x00000001U 1611 #define LRFDPBE32_PDREQ_EVTCLR1_PBEGPI0_RETAIN 0x00000000U 1612 1613 //***************************************************************************** 1614 // 1615 // Register: LRFDPBE32_O_MCEDATOUT0_API 1616 // 1617 //***************************************************************************** 1618 // Field: [31:16] VAL 1619 // 1620 // ENUMs: 1621 // ALLONES All the bits are 1 1622 // ALLZEROS All the bits are 0 1623 #define LRFDPBE32_MCEDATOUT0_API_VAL_W 16U 1624 #define LRFDPBE32_MCEDATOUT0_API_VAL_M 0xFFFF0000U 1625 #define LRFDPBE32_MCEDATOUT0_API_VAL_S 16U 1626 #define LRFDPBE32_MCEDATOUT0_API_VAL_ALLONES 0xFFFF0000U 1627 #define LRFDPBE32_MCEDATOUT0_API_VAL_ALLZEROS 0x00000000U 1628 1629 // Field: [4:0] PBECMD 1630 // 1631 // ENUMs: 1632 // ALLONES All the bits are 1 1633 // ALLZEROS All the bits are 0 1634 #define LRFDPBE32_MCEDATOUT0_API_PBECMD_W 5U 1635 #define LRFDPBE32_MCEDATOUT0_API_PBECMD_M 0x0000001FU 1636 #define LRFDPBE32_MCEDATOUT0_API_PBECMD_S 0U 1637 #define LRFDPBE32_MCEDATOUT0_API_PBECMD_ALLONES 0x0000001FU 1638 #define LRFDPBE32_MCEDATOUT0_API_PBECMD_ALLZEROS 0x00000000U 1639 1640 //***************************************************************************** 1641 // 1642 // Register: LRFDPBE32_O_MCECMDOUT_MCEDATIN0 1643 // 1644 //***************************************************************************** 1645 // Field: [19:16] MCECMDOUT_VAL 1646 // 1647 // ENUMs: 1648 // ALLONES All the bits are 1 1649 // ALLZEROS All the bits are 0 1650 #define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCECMDOUT_VAL_W 4U 1651 #define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCECMDOUT_VAL_M 0x000F0000U 1652 #define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCECMDOUT_VAL_S 16U 1653 #define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCECMDOUT_VAL_ALLONES 0x000F0000U 1654 #define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCECMDOUT_VAL_ALLZEROS 0x00000000U 1655 1656 // Field: [15:0] MCEDATIN0_VAL 1657 // 1658 // ENUMs: 1659 // ALLONES All the bits are 1 1660 // ALLZEROS All the bits are 0 1661 #define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCEDATIN0_VAL_W 16U 1662 #define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCEDATIN0_VAL_M 0x0000FFFFU 1663 #define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCEDATIN0_VAL_S 0U 1664 #define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCEDATIN0_VAL_ALLONES 0x0000FFFFU 1665 #define LRFDPBE32_MCECMDOUT_MCEDATIN0_MCEDATIN0_VAL_ALLZEROS 0x00000000U 1666 1667 //***************************************************************************** 1668 // 1669 // Register: LRFDPBE32_O_MDMAPI_MCECMDIN 1670 // 1671 //***************************************************************************** 1672 // Field: [23:20] PROTOCOLID 1673 // 1674 // ENUMs: 1675 // ALLONES All the bits are 1 1676 // ALLZEROS All the bits are 0 1677 #define LRFDPBE32_MDMAPI_MCECMDIN_PROTOCOLID_W 4U 1678 #define LRFDPBE32_MDMAPI_MCECMDIN_PROTOCOLID_M 0x00F00000U 1679 #define LRFDPBE32_MDMAPI_MCECMDIN_PROTOCOLID_S 20U 1680 #define LRFDPBE32_MDMAPI_MCECMDIN_PROTOCOLID_ALLONES 0x00F00000U 1681 #define LRFDPBE32_MDMAPI_MCECMDIN_PROTOCOLID_ALLZEROS 0x00000000U 1682 1683 // Field: [19:16] MDMCMD 1684 // 1685 // ENUMs: 1686 // ALLONES All the bits are 1 1687 // ALLZEROS All the bits are 0 1688 #define LRFDPBE32_MDMAPI_MCECMDIN_MDMCMD_W 4U 1689 #define LRFDPBE32_MDMAPI_MCECMDIN_MDMCMD_M 0x000F0000U 1690 #define LRFDPBE32_MDMAPI_MCECMDIN_MDMCMD_S 16U 1691 #define LRFDPBE32_MDMAPI_MCECMDIN_MDMCMD_ALLONES 0x000F0000U 1692 #define LRFDPBE32_MDMAPI_MCECMDIN_MDMCMD_ALLZEROS 0x00000000U 1693 1694 // Field: [3:0] VAL 1695 // 1696 // ENUMs: 1697 // ALLONES All the bits are 1 1698 // ALLZEROS All the bits are 0 1699 #define LRFDPBE32_MDMAPI_MCECMDIN_VAL_W 4U 1700 #define LRFDPBE32_MDMAPI_MCECMDIN_VAL_M 0x0000000FU 1701 #define LRFDPBE32_MDMAPI_MCECMDIN_VAL_S 0U 1702 #define LRFDPBE32_MDMAPI_MCECMDIN_VAL_ALLONES 0x0000000FU 1703 #define LRFDPBE32_MDMAPI_MCECMDIN_VAL_ALLZEROS 0x00000000U 1704 1705 //***************************************************************************** 1706 // 1707 // Register: LRFDPBE32_O_FREQ_MDMMSGBOX 1708 // 1709 //***************************************************************************** 1710 // Field: [31:16] OFFSET 1711 // 1712 // ENUMs: 1713 // ALLONES All the bits are 1 1714 // ALLZEROS All the bits are 0 1715 #define LRFDPBE32_FREQ_MDMMSGBOX_OFFSET_W 16U 1716 #define LRFDPBE32_FREQ_MDMMSGBOX_OFFSET_M 0xFFFF0000U 1717 #define LRFDPBE32_FREQ_MDMMSGBOX_OFFSET_S 16U 1718 #define LRFDPBE32_FREQ_MDMMSGBOX_OFFSET_ALLONES 0xFFFF0000U 1719 #define LRFDPBE32_FREQ_MDMMSGBOX_OFFSET_ALLZEROS 0x00000000U 1720 1721 // Field: [7:0] VALUE 1722 // 1723 // ENUMs: 1724 // ALLONES All the bits are 1 1725 // ALLZEROS All the bits are 0 1726 #define LRFDPBE32_FREQ_MDMMSGBOX_VALUE_W 8U 1727 #define LRFDPBE32_FREQ_MDMMSGBOX_VALUE_M 0x000000FFU 1728 #define LRFDPBE32_FREQ_MDMMSGBOX_VALUE_S 0U 1729 #define LRFDPBE32_FREQ_MDMMSGBOX_VALUE_ALLONES 0x000000FFU 1730 #define LRFDPBE32_FREQ_MDMMSGBOX_VALUE_ALLZEROS 0x00000000U 1731 1732 //***************************************************************************** 1733 // 1734 // Register: LRFDPBE32_O_RFEDATOUT0_MDMLQI 1735 // 1736 //***************************************************************************** 1737 // Field: [31:16] RFEDATOUT0_VAL 1738 // 1739 // ENUMs: 1740 // ALLONES All the bits are 1 1741 // ALLZEROS All the bits are 0 1742 #define LRFDPBE32_RFEDATOUT0_MDMLQI_RFEDATOUT0_VAL_W 16U 1743 #define LRFDPBE32_RFEDATOUT0_MDMLQI_RFEDATOUT0_VAL_M 0xFFFF0000U 1744 #define LRFDPBE32_RFEDATOUT0_MDMLQI_RFEDATOUT0_VAL_S 16U 1745 #define LRFDPBE32_RFEDATOUT0_MDMLQI_RFEDATOUT0_VAL_ALLONES 0xFFFF0000U 1746 #define LRFDPBE32_RFEDATOUT0_MDMLQI_RFEDATOUT0_VAL_ALLZEROS 0x00000000U 1747 1748 // Field: [7:0] MDMLQI_VAL 1749 // 1750 // ENUMs: 1751 // ALLONES All the bits are 1 1752 // ALLZEROS All the bits are 0 1753 #define LRFDPBE32_RFEDATOUT0_MDMLQI_MDMLQI_VAL_W 8U 1754 #define LRFDPBE32_RFEDATOUT0_MDMLQI_MDMLQI_VAL_M 0x000000FFU 1755 #define LRFDPBE32_RFEDATOUT0_MDMLQI_MDMLQI_VAL_S 0U 1756 #define LRFDPBE32_RFEDATOUT0_MDMLQI_MDMLQI_VAL_ALLONES 0x000000FFU 1757 #define LRFDPBE32_RFEDATOUT0_MDMLQI_MDMLQI_VAL_ALLZEROS 0x00000000U 1758 1759 //***************************************************************************** 1760 // 1761 // Register: LRFDPBE32_O_RFECMDOUT_RFEDATIN0 1762 // 1763 //***************************************************************************** 1764 // Field: [19:16] RFECMDOUT_VAL 1765 // 1766 // ENUMs: 1767 // ALLONES All the bits are 1 1768 // ALLZEROS All the bits are 0 1769 #define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFECMDOUT_VAL_W 4U 1770 #define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFECMDOUT_VAL_M 0x000F0000U 1771 #define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFECMDOUT_VAL_S 16U 1772 #define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFECMDOUT_VAL_ALLONES 0x000F0000U 1773 #define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFECMDOUT_VAL_ALLZEROS 0x00000000U 1774 1775 // Field: [15:0] RFEDATIN0_VAL 1776 // 1777 // ENUMs: 1778 // ALLONES All the bits are 1 1779 // ALLZEROS All the bits are 0 1780 #define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFEDATIN0_VAL_W 16U 1781 #define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFEDATIN0_VAL_M 0x0000FFFFU 1782 #define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFEDATIN0_VAL_S 0U 1783 #define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFEDATIN0_VAL_ALLONES 0x0000FFFFU 1784 #define LRFDPBE32_RFECMDOUT_RFEDATIN0_RFEDATIN0_VAL_ALLZEROS 0x00000000U 1785 1786 //***************************************************************************** 1787 // 1788 // Register: LRFDPBE32_O_RFEAPI_RFECMDIN 1789 // 1790 //***************************************************************************** 1791 // Field: [23:20] PROTOCOLID 1792 // 1793 // ENUMs: 1794 // ALLONES All the bits are 1 1795 // ALLZEROS All the bits are 0 1796 #define LRFDPBE32_RFEAPI_RFECMDIN_PROTOCOLID_W 4U 1797 #define LRFDPBE32_RFEAPI_RFECMDIN_PROTOCOLID_M 0x00F00000U 1798 #define LRFDPBE32_RFEAPI_RFECMDIN_PROTOCOLID_S 20U 1799 #define LRFDPBE32_RFEAPI_RFECMDIN_PROTOCOLID_ALLONES 0x00F00000U 1800 #define LRFDPBE32_RFEAPI_RFECMDIN_PROTOCOLID_ALLZEROS 0x00000000U 1801 1802 // Field: [19:16] RFECMD 1803 // 1804 // ENUMs: 1805 // ALLONES All the bits are 1 1806 // ALLZEROS All the bits are 0 1807 #define LRFDPBE32_RFEAPI_RFECMDIN_RFECMD_W 4U 1808 #define LRFDPBE32_RFEAPI_RFECMDIN_RFECMD_M 0x000F0000U 1809 #define LRFDPBE32_RFEAPI_RFECMDIN_RFECMD_S 16U 1810 #define LRFDPBE32_RFEAPI_RFECMDIN_RFECMD_ALLONES 0x000F0000U 1811 #define LRFDPBE32_RFEAPI_RFECMDIN_RFECMD_ALLZEROS 0x00000000U 1812 1813 // Field: [3:0] VAL 1814 // 1815 // ENUMs: 1816 // ALLONES All the bits are 1 1817 // ALLZEROS All the bits are 0 1818 #define LRFDPBE32_RFEAPI_RFECMDIN_VAL_W 4U 1819 #define LRFDPBE32_RFEAPI_RFECMDIN_VAL_M 0x0000000FU 1820 #define LRFDPBE32_RFEAPI_RFECMDIN_VAL_S 0U 1821 #define LRFDPBE32_RFEAPI_RFECMDIN_VAL_ALLONES 0x0000000FU 1822 #define LRFDPBE32_RFEAPI_RFECMDIN_VAL_ALLZEROS 0x00000000U 1823 1824 //***************************************************************************** 1825 // 1826 // Register: LRFDPBE32_O_RFECMDPAR1_RFECMDPAR0 1827 // 1828 //***************************************************************************** 1829 // Field: [31:16] RFECMDPAR1_VAL 1830 // 1831 // ENUMs: 1832 // ALLONES All the bits are 1 1833 // ALLZEROS All the bits are 0 1834 #define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR1_VAL_W 16U 1835 #define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR1_VAL_M 0xFFFF0000U 1836 #define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR1_VAL_S 16U 1837 #define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR1_VAL_ALLONES 0xFFFF0000U 1838 #define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR1_VAL_ALLZEROS 0x00000000U 1839 1840 // Field: [15:0] RFECMDPAR0_VAL 1841 // 1842 // ENUMs: 1843 // ALLONES All the bits are 1 1844 // ALLZEROS All the bits are 0 1845 #define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR0_VAL_W 16U 1846 #define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR0_VAL_M 0x0000FFFFU 1847 #define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR0_VAL_S 0U 1848 #define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR0_VAL_ALLONES 0x0000FFFFU 1849 #define LRFDPBE32_RFECMDPAR1_RFECMDPAR0_RFECMDPAR0_VAL_ALLZEROS 0x00000000U 1850 1851 //***************************************************************************** 1852 // 1853 // Register: LRFDPBE32_O_RFERSSI_RFEMSGBOX 1854 // 1855 //***************************************************************************** 1856 // Field: [23:16] RFERSSI_VAL 1857 // 1858 // ENUMs: 1859 // ALLONES All the bits are 1 1860 // ALLZEROS All the bits are 0 1861 #define LRFDPBE32_RFERSSI_RFEMSGBOX_RFERSSI_VAL_W 8U 1862 #define LRFDPBE32_RFERSSI_RFEMSGBOX_RFERSSI_VAL_M 0x00FF0000U 1863 #define LRFDPBE32_RFERSSI_RFEMSGBOX_RFERSSI_VAL_S 16U 1864 #define LRFDPBE32_RFERSSI_RFEMSGBOX_RFERSSI_VAL_ALLONES 0x00FF0000U 1865 #define LRFDPBE32_RFERSSI_RFEMSGBOX_RFERSSI_VAL_ALLZEROS 0x00000000U 1866 1867 // Field: [7:0] RFEMSGBOX_VAL 1868 // 1869 // ENUMs: 1870 // ALLONES All the bits are 1 1871 // ALLZEROS All the bits are 0 1872 #define LRFDPBE32_RFERSSI_RFEMSGBOX_RFEMSGBOX_VAL_W 8U 1873 #define LRFDPBE32_RFERSSI_RFEMSGBOX_RFEMSGBOX_VAL_M 0x000000FFU 1874 #define LRFDPBE32_RFERSSI_RFEMSGBOX_RFEMSGBOX_VAL_S 0U 1875 #define LRFDPBE32_RFERSSI_RFEMSGBOX_RFEMSGBOX_VAL_ALLONES 0x000000FFU 1876 #define LRFDPBE32_RFERSSI_RFEMSGBOX_RFEMSGBOX_VAL_ALLZEROS 0x00000000U 1877 1878 //***************************************************************************** 1879 // 1880 // Register: LRFDPBE32_O_RFERFGAIN_RFERSSIMAX 1881 // 1882 //***************************************************************************** 1883 // Field: [23:16] DBGAIN 1884 // 1885 // ENUMs: 1886 // ALLONES All the bits are 1 1887 // ALLZEROS All the bits are 0 1888 #define LRFDPBE32_RFERFGAIN_RFERSSIMAX_DBGAIN_W 8U 1889 #define LRFDPBE32_RFERFGAIN_RFERSSIMAX_DBGAIN_M 0x00FF0000U 1890 #define LRFDPBE32_RFERFGAIN_RFERSSIMAX_DBGAIN_S 16U 1891 #define LRFDPBE32_RFERFGAIN_RFERSSIMAX_DBGAIN_ALLONES 0x00FF0000U 1892 #define LRFDPBE32_RFERFGAIN_RFERSSIMAX_DBGAIN_ALLZEROS 0x00000000U 1893 1894 // Field: [7:0] VAL 1895 // 1896 // ENUMs: 1897 // ALLONES All the bits are 1 1898 // ALLZEROS All the bits are 0 1899 #define LRFDPBE32_RFERFGAIN_RFERSSIMAX_VAL_W 8U 1900 #define LRFDPBE32_RFERFGAIN_RFERSSIMAX_VAL_M 0x000000FFU 1901 #define LRFDPBE32_RFERFGAIN_RFERSSIMAX_VAL_S 0U 1902 #define LRFDPBE32_RFERFGAIN_RFERSSIMAX_VAL_ALLONES 0x000000FFU 1903 #define LRFDPBE32_RFERFGAIN_RFERSSIMAX_VAL_ALLZEROS 0x00000000U 1904 1905 //***************************************************************************** 1906 // 1907 // Register: LRFDPBE32_O_MDMSYNCA 1908 // 1909 //***************************************************************************** 1910 // Field: [31:0] SWA 1911 // 1912 // ENUMs: 1913 // ALLONES All the bits are 1 1914 // ALLZEROS All the bits are 0 1915 #define LRFDPBE32_MDMSYNCA_SWA_W 32U 1916 #define LRFDPBE32_MDMSYNCA_SWA_M 0xFFFFFFFFU 1917 #define LRFDPBE32_MDMSYNCA_SWA_S 0U 1918 #define LRFDPBE32_MDMSYNCA_SWA_ALLONES 0x0000FFFFU 1919 #define LRFDPBE32_MDMSYNCA_SWA_ALLZEROS 0x00000000U 1920 1921 //***************************************************************************** 1922 // 1923 // Register: LRFDPBE32_O_MDMSYNCB 1924 // 1925 //***************************************************************************** 1926 // Field: [31:0] SWB 1927 // 1928 // ENUMs: 1929 // ALLONES All the bits are 1 1930 // ALLZEROS All the bits are 0 1931 #define LRFDPBE32_MDMSYNCB_SWB_W 32U 1932 #define LRFDPBE32_MDMSYNCB_SWB_M 0xFFFFFFFFU 1933 #define LRFDPBE32_MDMSYNCB_SWB_S 0U 1934 #define LRFDPBE32_MDMSYNCB_SWB_ALLONES 0x0000FFFFU 1935 #define LRFDPBE32_MDMSYNCB_SWB_ALLZEROS 0x00000000U 1936 1937 //***************************************************************************** 1938 // 1939 // Register: LRFDPBE32_O_MDMCMDPAR1_MDMCMDPAR0 1940 // 1941 //***************************************************************************** 1942 // Field: [31:16] MDMCMDPAR1_VAL 1943 // 1944 // ENUMs: 1945 // ALLONES All the bits are 1 1946 // ALLZEROS All the bits are 0 1947 #define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR1_VAL_W 16U 1948 #define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR1_VAL_M 0xFFFF0000U 1949 #define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR1_VAL_S 16U 1950 #define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR1_VAL_ALLONES 0xFFFF0000U 1951 #define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR1_VAL_ALLZEROS 0x00000000U 1952 1953 // Field: [15:0] MDMCMDPAR0_VAL 1954 // 1955 // ENUMs: 1956 // ALLONES All the bits are 1 1957 // ALLZEROS All the bits are 0 1958 #define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR0_VAL_W 16U 1959 #define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR0_VAL_M 0x0000FFFFU 1960 #define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR0_VAL_S 0U 1961 #define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR0_VAL_ALLONES 0x0000FFFFU 1962 #define LRFDPBE32_MDMCMDPAR1_MDMCMDPAR0_MDMCMDPAR0_VAL_ALLZEROS 0x00000000U 1963 1964 //***************************************************************************** 1965 // 1966 // Register: LRFDPBE32_O_MDMCMDPAR2 1967 // 1968 //***************************************************************************** 1969 // Field: [15:0] VAL 1970 // 1971 // ENUMs: 1972 // ALLONES All the bits are 1 1973 // ALLZEROS All the bits are 0 1974 #define LRFDPBE32_MDMCMDPAR2_VAL_W 16U 1975 #define LRFDPBE32_MDMCMDPAR2_VAL_M 0x0000FFFFU 1976 #define LRFDPBE32_MDMCMDPAR2_VAL_S 0U 1977 #define LRFDPBE32_MDMCMDPAR2_VAL_ALLONES 0x0000FFFFU 1978 #define LRFDPBE32_MDMCMDPAR2_VAL_ALLZEROS 0x00000000U 1979 1980 //***************************************************************************** 1981 // 1982 // Register: LRFDPBE32_O_POLY0 1983 // 1984 //***************************************************************************** 1985 // Field: [31:0] VAL 1986 // 1987 // ENUMs: 1988 // ALLONES All the bits are 1 1989 // ALLZEROS All the bits are 0 1990 #define LRFDPBE32_POLY0_VAL_W 32U 1991 #define LRFDPBE32_POLY0_VAL_M 0xFFFFFFFFU 1992 #define LRFDPBE32_POLY0_VAL_S 0U 1993 #define LRFDPBE32_POLY0_VAL_ALLONES 0x0000FFFFU 1994 #define LRFDPBE32_POLY0_VAL_ALLZEROS 0x00000000U 1995 1996 //***************************************************************************** 1997 // 1998 // Register: LRFDPBE32_O_POLY1 1999 // 2000 //***************************************************************************** 2001 // Field: [31:0] VAL 2002 // 2003 // ENUMs: 2004 // ALLONES All the bits are 1 2005 // ALLZEROS All the bits are 0 2006 #define LRFDPBE32_POLY1_VAL_W 32U 2007 #define LRFDPBE32_POLY1_VAL_M 0xFFFFFFFFU 2008 #define LRFDPBE32_POLY1_VAL_S 0U 2009 #define LRFDPBE32_POLY1_VAL_ALLONES 0x0000FFFFU 2010 #define LRFDPBE32_POLY1_VAL_ALLZEROS 0x00000000U 2011 2012 //***************************************************************************** 2013 // 2014 // Register: LRFDPBE32_O_FCFG0_PHACFG 2015 // 2016 //***************************************************************************** 2017 // Field: [23] TXIRQMET 2018 // 2019 // ENUMs: 2020 // TXRDBTHR The TX FIFO contains TXFRBTHRS or more readable 2021 // bytes. 2022 // TXWRBTHR The TX FIFO contains TXFWBTHRS or more writable 2023 // bytes. 2024 #define LRFDPBE32_FCFG0_PHACFG_TXIRQMET 0x00800000U 2025 #define LRFDPBE32_FCFG0_PHACFG_TXIRQMET_M 0x00800000U 2026 #define LRFDPBE32_FCFG0_PHACFG_TXIRQMET_S 23U 2027 #define LRFDPBE32_FCFG0_PHACFG_TXIRQMET_TXRDBTHR 0x00800000U 2028 #define LRFDPBE32_FCFG0_PHACFG_TXIRQMET_TXWRBTHR 0x00000000U 2029 2030 // Field: [22] RXIRQMET 2031 // 2032 // ENUMs: 2033 // RXWRBTHR The RX FIFO contains RXFWBTHRS or more writable 2034 // bytes. 2035 // RXRDBTHR The RX FIFO contains RXFRBTHRS or more readable 2036 // bytes. 2037 #define LRFDPBE32_FCFG0_PHACFG_RXIRQMET 0x00400000U 2038 #define LRFDPBE32_FCFG0_PHACFG_RXIRQMET_M 0x00400000U 2039 #define LRFDPBE32_FCFG0_PHACFG_RXIRQMET_S 22U 2040 #define LRFDPBE32_FCFG0_PHACFG_RXIRQMET_RXWRBTHR 0x00400000U 2041 #define LRFDPBE32_FCFG0_PHACFG_RXIRQMET_RXRDBTHR 0x00000000U 2042 2043 // Field: [21] TXACOM 2044 // 2045 // ENUMs: 2046 // EN Always set TXSWP := TXWP 2047 // DIS commit TXFIFO only on command 0x95 2048 #define LRFDPBE32_FCFG0_PHACFG_TXACOM 0x00200000U 2049 #define LRFDPBE32_FCFG0_PHACFG_TXACOM_M 0x00200000U 2050 #define LRFDPBE32_FCFG0_PHACFG_TXACOM_S 21U 2051 #define LRFDPBE32_FCFG0_PHACFG_TXACOM_EN 0x00200000U 2052 #define LRFDPBE32_FCFG0_PHACFG_TXACOM_DIS 0x00000000U 2053 2054 // Field: [20] TXADEAL 2055 // 2056 // ENUMs: 2057 // EN Always set TXFSRP := TXFRP. 2058 // DIS Deallocate TXFIFO only on command 0x92 2059 #define LRFDPBE32_FCFG0_PHACFG_TXADEAL 0x00100000U 2060 #define LRFDPBE32_FCFG0_PHACFG_TXADEAL_M 0x00100000U 2061 #define LRFDPBE32_FCFG0_PHACFG_TXADEAL_S 20U 2062 #define LRFDPBE32_FCFG0_PHACFG_TXADEAL_EN 0x00100000U 2063 #define LRFDPBE32_FCFG0_PHACFG_TXADEAL_DIS 0x00000000U 2064 2065 // Field: [17] RXACOM 2066 // 2067 // ENUMs: 2068 // EN Always set RXFSWP := RXFWP 2069 // DIS commit rxfifo only on command 0x85 2070 #define LRFDPBE32_FCFG0_PHACFG_RXACOM 0x00020000U 2071 #define LRFDPBE32_FCFG0_PHACFG_RXACOM_M 0x00020000U 2072 #define LRFDPBE32_FCFG0_PHACFG_RXACOM_S 17U 2073 #define LRFDPBE32_FCFG0_PHACFG_RXACOM_EN 0x00020000U 2074 #define LRFDPBE32_FCFG0_PHACFG_RXACOM_DIS 0x00000000U 2075 2076 // Field: [16] RXADEAL 2077 // 2078 // ENUMs: 2079 // EN Always set RXFSRP := RXFRP. 2080 // DIS Deallocate RXFIFO only on command 0x82 2081 #define LRFDPBE32_FCFG0_PHACFG_RXADEAL 0x00010000U 2082 #define LRFDPBE32_FCFG0_PHACFG_RXADEAL_M 0x00010000U 2083 #define LRFDPBE32_FCFG0_PHACFG_RXADEAL_S 16U 2084 #define LRFDPBE32_FCFG0_PHACFG_RXADEAL_EN 0x00010000U 2085 #define LRFDPBE32_FCFG0_PHACFG_RXADEAL_DIS 0x00000000U 2086 2087 // Field: [2:1] MODE1 2088 // 2089 // ENUMs: 2090 // PARAL LFSR0 and LFSR1 are operated in parallel 2091 // CASC LFSR0 whitener is followed by LFSR1 CRC 2092 // INDEP LFSR0 and LFSR1 are operated independently 2093 #define LRFDPBE32_FCFG0_PHACFG_MODE1_W 2U 2094 #define LRFDPBE32_FCFG0_PHACFG_MODE1_M 0x00000006U 2095 #define LRFDPBE32_FCFG0_PHACFG_MODE1_S 1U 2096 #define LRFDPBE32_FCFG0_PHACFG_MODE1_PARAL 0x00000004U 2097 #define LRFDPBE32_FCFG0_PHACFG_MODE1_CASC 0x00000002U 2098 #define LRFDPBE32_FCFG0_PHACFG_MODE1_INDEP 0x00000000U 2099 2100 // Field: [0] MODE0 2101 // 2102 // ENUMs: 2103 // WHITE LFSR 0 is in whitening mode 2104 // CRC LFSR 0 is in CRC mode 2105 #define LRFDPBE32_FCFG0_PHACFG_MODE0 0x00000001U 2106 #define LRFDPBE32_FCFG0_PHACFG_MODE0_M 0x00000001U 2107 #define LRFDPBE32_FCFG0_PHACFG_MODE0_S 0U 2108 #define LRFDPBE32_FCFG0_PHACFG_MODE0_WHITE 0x00000001U 2109 #define LRFDPBE32_FCFG0_PHACFG_MODE0_CRC 0x00000000U 2110 2111 //***************************************************************************** 2112 // 2113 // Register: LRFDPBE32_O_FCFG2_FCFG1 2114 // 2115 //***************************************************************************** 2116 // Field: [26:24] TXHSIZE 2117 // 2118 // ENUMs: 2119 // WORD MCU receives IRQ when the TX FIFO contains more or 2120 // equal amount of data than the configured 2121 // threshold. 2122 // HALFW MCU receives IRQ when the TX FIFO contains less 2123 // amount of data than the configured threshold. 2124 // BYTE MCU receives IRQ when the TX FIFO contains less 2125 // amount of data than the configured threshold. 2126 #define LRFDPBE32_FCFG2_FCFG1_TXHSIZE_W 3U 2127 #define LRFDPBE32_FCFG2_FCFG1_TXHSIZE_M 0x07000000U 2128 #define LRFDPBE32_FCFG2_FCFG1_TXHSIZE_S 24U 2129 #define LRFDPBE32_FCFG2_FCFG1_TXHSIZE_WORD 0x02000000U 2130 #define LRFDPBE32_FCFG2_FCFG1_TXHSIZE_HALFW 0x01000000U 2131 #define LRFDPBE32_FCFG2_FCFG1_TXHSIZE_BYTE 0x00000000U 2132 2133 // Field: [23:16] TXSIZE 2134 // 2135 // ENUMs: 2136 // ONES All bits are 1s 2137 // ZEROS All bits are zero 2138 #define LRFDPBE32_FCFG2_FCFG1_TXSIZE_W 8U 2139 #define LRFDPBE32_FCFG2_FCFG1_TXSIZE_M 0x00FF0000U 2140 #define LRFDPBE32_FCFG2_FCFG1_TXSIZE_S 16U 2141 #define LRFDPBE32_FCFG2_FCFG1_TXSIZE_ONES 0x00FF0000U 2142 #define LRFDPBE32_FCFG2_FCFG1_TXSIZE_ZEROS 0x00000000U 2143 2144 // Field: [8:0] TXSTRT 2145 // 2146 // ENUMs: 2147 // ONES All bits are 1s 2148 // ZEROS All bits are zero 2149 #define LRFDPBE32_FCFG2_FCFG1_TXSTRT_W 9U 2150 #define LRFDPBE32_FCFG2_FCFG1_TXSTRT_M 0x000001FFU 2151 #define LRFDPBE32_FCFG2_FCFG1_TXSTRT_S 0U 2152 #define LRFDPBE32_FCFG2_FCFG1_TXSTRT_ONES 0x000001FFU 2153 #define LRFDPBE32_FCFG2_FCFG1_TXSTRT_ZEROS 0x00000000U 2154 2155 //***************************************************************************** 2156 // 2157 // Register: LRFDPBE32_O_FCFG4_FCFG3 2158 // 2159 //***************************************************************************** 2160 // Field: [26:24] RXHSIZE 2161 // 2162 // ENUMs: 2163 // WORD MCU receives IRQ when the TX FIFO contains more or 2164 // equal amount of data than the configured 2165 // threshold. 2166 // HALFW MCU receives IRQ when the TX FIFO contains less 2167 // amount of data than the configured threshold. 2168 // BYTE MCU receives IRQ when the TX FIFO contains less 2169 // amount of data than the configured threshold. 2170 #define LRFDPBE32_FCFG4_FCFG3_RXHSIZE_W 3U 2171 #define LRFDPBE32_FCFG4_FCFG3_RXHSIZE_M 0x07000000U 2172 #define LRFDPBE32_FCFG4_FCFG3_RXHSIZE_S 24U 2173 #define LRFDPBE32_FCFG4_FCFG3_RXHSIZE_WORD 0x02000000U 2174 #define LRFDPBE32_FCFG4_FCFG3_RXHSIZE_HALFW 0x01000000U 2175 #define LRFDPBE32_FCFG4_FCFG3_RXHSIZE_BYTE 0x00000000U 2176 2177 // Field: [23:16] RXSIZE 2178 // 2179 // ENUMs: 2180 // ONES Always set RXFSWP := RXFWP 2181 // ZEROS commit rxfifo only on command 0x85 2182 #define LRFDPBE32_FCFG4_FCFG3_RXSIZE_W 8U 2183 #define LRFDPBE32_FCFG4_FCFG3_RXSIZE_M 0x00FF0000U 2184 #define LRFDPBE32_FCFG4_FCFG3_RXSIZE_S 16U 2185 #define LRFDPBE32_FCFG4_FCFG3_RXSIZE_ONES 0x00FF0000U 2186 #define LRFDPBE32_FCFG4_FCFG3_RXSIZE_ZEROS 0x00000000U 2187 2188 // Field: [8:0] RXSTRT 2189 // 2190 // ENUMs: 2191 // ONES All bits are 1s 2192 // ZEROS All bits are zero 2193 #define LRFDPBE32_FCFG4_FCFG3_RXSTRT_W 9U 2194 #define LRFDPBE32_FCFG4_FCFG3_RXSTRT_M 0x000001FFU 2195 #define LRFDPBE32_FCFG4_FCFG3_RXSTRT_S 0U 2196 #define LRFDPBE32_FCFG4_FCFG3_RXSTRT_ONES 0x000001FFU 2197 #define LRFDPBE32_FCFG4_FCFG3_RXSTRT_ZEROS 0x00000000U 2198 2199 //***************************************************************************** 2200 // 2201 // Register: LRFDPBE32_O_RXFWBTHRS_FCFG5 2202 // 2203 //***************************************************************************** 2204 // Field: [25:16] BYTES 2205 // 2206 // ENUMs: 2207 // ALLONES All the bits are 1 2208 // ALLZEROS All the bits are 0 2209 #define LRFDPBE32_RXFWBTHRS_FCFG5_BYTES_W 10U 2210 #define LRFDPBE32_RXFWBTHRS_FCFG5_BYTES_M 0x03FF0000U 2211 #define LRFDPBE32_RXFWBTHRS_FCFG5_BYTES_S 16U 2212 #define LRFDPBE32_RXFWBTHRS_FCFG5_BYTES_ALLONES 0x03FF0000U 2213 #define LRFDPBE32_RXFWBTHRS_FCFG5_BYTES_ALLZEROS 0x00000000U 2214 2215 // Field: [8:6] DMASREQ 2216 // 2217 // ENUMs: 2218 // TXFIFOFREE The TX FIFO contains FCFG2_TXHSIZE or more 2219 // writable bytes. 2220 // TXFIFOMD The TX FIFO contains FCFG2_TXHSIZE or more 2221 // readable bytes. 2222 // RXFIFOFREE The RX FIFO contains FCFG4_RXHSIZE or more 2223 // writable bytes. 2224 // RXFIFOMD The RX FIFO contains FCFG4_RXHSIZE or more 2225 // readable bytes. 2226 // NONE No triggers generated 2227 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_W 3U 2228 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_M 0x000001C0U 2229 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_S 6U 2230 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_TXFIFOFREE 0x00000100U 2231 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_TXFIFOMD 0x000000C0U 2232 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_RXFIFOFREE 0x00000080U 2233 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_RXFIFOMD 0x00000040U 2234 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMASREQ_NONE 0x00000000U 2235 2236 // Field: [4:0] DMAREQ 2237 // 2238 // ENUMs: 2239 // TXFIFO_COMMIT TXFIFO is committed 2240 // TXFIFO_DISCARD TXFIFO is discarded 2241 // TXFIFO_RETRY TXFIFO is retried 2242 // TXFIFO_DEALLOC TXFIFO is deallocated 2243 // TXFIFO_RESET TXFIFO is reset 2244 // TXWRBTHR_MET The TX FIFO contains TXFWBTHRS or more writable 2245 // bytes. 2246 // TXRDBTHR_MET The TX FIFO contains TXFRBTHRS or more readable 2247 // bytes. 2248 // RXFIFO_COMMIT RXFIFO is committed 2249 // RXFIFO_DISCARD RXFIFO is discarded 2250 // RXFIFO_RETRY RXFIFO is retried 2251 // RXFIFO_DEALLOC RXFIFO is deallocated 2252 // RXFIFO_RESET RXFIFO is reset 2253 // RXWRBTHR_MET The RX FIFO contains RXFWBTHRS or more writable 2254 // bytes. 2255 // RXRDBTHR_MET The RX FIFO contains RXFRBTHRS or more readable 2256 // bytes. 2257 // NONE No triggers generated 2258 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_W 5U 2259 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_M 0x0000001FU 2260 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_S 0U 2261 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXFIFO_COMMIT 0x0000000FU 2262 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXFIFO_DISCARD 0x0000000EU 2263 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXFIFO_RETRY 0x0000000DU 2264 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXFIFO_DEALLOC 0x0000000CU 2265 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXFIFO_RESET 0x0000000BU 2266 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXWRBTHR_MET 0x0000000AU 2267 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_TXRDBTHR_MET 0x00000009U 2268 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXFIFO_COMMIT 0x00000007U 2269 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXFIFO_DISCARD 0x00000006U 2270 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXFIFO_RETRY 0x00000005U 2271 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXFIFO_DEALLOC 0x00000004U 2272 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXFIFO_RESET 0x00000003U 2273 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXWRBTHR_MET 0x00000002U 2274 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_RXRDBTHR_MET 0x00000001U 2275 #define LRFDPBE32_RXFWBTHRS_FCFG5_DMAREQ_NONE 0x00000000U 2276 2277 //***************************************************************************** 2278 // 2279 // Register: LRFDPBE32_O_TXFWBTHRS_RXFRBTHRS 2280 // 2281 //***************************************************************************** 2282 // Field: [25:16] TXFWBTHRS_BYTES 2283 // 2284 // ENUMs: 2285 // ALLONES All the bits are 1 2286 // ALLZEROS All the bits are 0 2287 #define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_TXFWBTHRS_BYTES_W 10U 2288 #define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_TXFWBTHRS_BYTES_M 0x03FF0000U 2289 #define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_TXFWBTHRS_BYTES_S 16U 2290 #define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_TXFWBTHRS_BYTES_ALLONES 0x03FF0000U 2291 #define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_TXFWBTHRS_BYTES_ALLZEROS 0x00000000U 2292 2293 // Field: [9:0] RXFRBTHRS_BYTES 2294 // 2295 // ENUMs: 2296 // ALLONES All the bits are 1 2297 // ALLZEROS All the bits are 0 2298 #define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_RXFRBTHRS_BYTES_W 10U 2299 #define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_RXFRBTHRS_BYTES_M 0x000003FFU 2300 #define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_RXFRBTHRS_BYTES_S 0U 2301 #define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_RXFRBTHRS_BYTES_ALLONES 0x000003FFU 2302 #define LRFDPBE32_TXFWBTHRS_RXFRBTHRS_RXFRBTHRS_BYTES_ALLZEROS 0x00000000U 2303 2304 //***************************************************************************** 2305 // 2306 // Register: LRFDPBE32_O_TIMCTL_TXFRBTHRS 2307 // 2308 //***************************************************************************** 2309 // Field: [31:27] CPTSRC1 2310 // 2311 // ENUMs: 2312 // ALLONES All the bits are 1 2313 // ALLZEROS All the bits are 0 2314 #define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC1_W 5U 2315 #define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC1_M 0xF8000000U 2316 #define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC1_S 27U 2317 #define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC1_ALLONES 0xF8000000U 2318 #define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC1_ALLZEROS 0x00000000U 2319 2320 // Field: [26] ENCPT1 2321 // 2322 // ENUMs: 2323 // ON Enable capture mode for counter 2324 // OFF Disable capture mode for counter 2325 #define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT1 0x04000000U 2326 #define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT1_M 0x04000000U 2327 #define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT1_S 26U 2328 #define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT1_ON 0x04000000U 2329 #define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT1_OFF 0x00000000U 2330 2331 // Field: [25] SRC1 2332 // 2333 // ENUMs: 2334 // PRE1 Use magnitude estimator 0 data enable 2335 // CLK Use clock 2336 #define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC1 0x02000000U 2337 #define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC1_M 0x02000000U 2338 #define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC1_S 25U 2339 #define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC1_PRE1 0x02000000U 2340 #define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC1_CLK 0x00000000U 2341 2342 // Field: [24] EN1 2343 // 2344 // ENUMs: 2345 // ON Will enable timer 2346 // OFF Will disable timer and clear internal timer value 2347 #define LRFDPBE32_TIMCTL_TXFRBTHRS_EN1 0x01000000U 2348 #define LRFDPBE32_TIMCTL_TXFRBTHRS_EN1_M 0x01000000U 2349 #define LRFDPBE32_TIMCTL_TXFRBTHRS_EN1_S 24U 2350 #define LRFDPBE32_TIMCTL_TXFRBTHRS_EN1_ON 0x01000000U 2351 #define LRFDPBE32_TIMCTL_TXFRBTHRS_EN1_OFF 0x00000000U 2352 2353 // Field: [23:19] CPTSRC0 2354 // 2355 // ENUMs: 2356 // ALLONES All the bits are 1 2357 // ALLZEROS All the bits are 0 2358 #define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC0_W 5U 2359 #define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC0_M 0x00F80000U 2360 #define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC0_S 19U 2361 #define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC0_ALLONES 0x00F80000U 2362 #define LRFDPBE32_TIMCTL_TXFRBTHRS_CPTSRC0_ALLZEROS 0x00000000U 2363 2364 // Field: [18] ENCPT0 2365 // 2366 // ENUMs: 2367 // ON Enable capture mode for counter 2368 // OFF Disable capture mode for counter 2369 #define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT0 0x00040000U 2370 #define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT0_M 0x00040000U 2371 #define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT0_S 18U 2372 #define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT0_ON 0x00040000U 2373 #define LRFDPBE32_TIMCTL_TXFRBTHRS_ENCPT0_OFF 0x00000000U 2374 2375 // Field: [17] SRC0 2376 // 2377 // ENUMs: 2378 // PRE0 Use magnitude estimator 0 data enable 2379 // CLK Use clock 2380 #define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC0 0x00020000U 2381 #define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC0_M 0x00020000U 2382 #define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC0_S 17U 2383 #define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC0_PRE0 0x00020000U 2384 #define LRFDPBE32_TIMCTL_TXFRBTHRS_SRC0_CLK 0x00000000U 2385 2386 // Field: [16] EN0 2387 // 2388 // ENUMs: 2389 // ON Will enable timer 2390 // OFF Will disable timer and clear internal timer value 2391 #define LRFDPBE32_TIMCTL_TXFRBTHRS_EN0 0x00010000U 2392 #define LRFDPBE32_TIMCTL_TXFRBTHRS_EN0_M 0x00010000U 2393 #define LRFDPBE32_TIMCTL_TXFRBTHRS_EN0_S 16U 2394 #define LRFDPBE32_TIMCTL_TXFRBTHRS_EN0_ON 0x00010000U 2395 #define LRFDPBE32_TIMCTL_TXFRBTHRS_EN0_OFF 0x00000000U 2396 2397 // Field: [9:0] BYTES 2398 // 2399 // ENUMs: 2400 // ALLONES All the bits are 1 2401 // ALLZEROS All the bits are 0 2402 #define LRFDPBE32_TIMCTL_TXFRBTHRS_BYTES_W 10U 2403 #define LRFDPBE32_TIMCTL_TXFRBTHRS_BYTES_M 0x000003FFU 2404 #define LRFDPBE32_TIMCTL_TXFRBTHRS_BYTES_S 0U 2405 #define LRFDPBE32_TIMCTL_TXFRBTHRS_BYTES_ALLONES 0x000003FFU 2406 #define LRFDPBE32_TIMCTL_TXFRBTHRS_BYTES_ALLZEROS 0x00000000U 2407 2408 //***************************************************************************** 2409 // 2410 // Register: LRFDPBE32_O_TIMPER0_TIMPRE 2411 // 2412 //***************************************************************************** 2413 // Field: [31:16] VAL 2414 // 2415 // ENUMs: 2416 // ALLONES All the bits are 1 2417 // ALLZEROS All the bits are 0 2418 #define LRFDPBE32_TIMPER0_TIMPRE_VAL_W 16U 2419 #define LRFDPBE32_TIMPER0_TIMPRE_VAL_M 0xFFFF0000U 2420 #define LRFDPBE32_TIMPER0_TIMPRE_VAL_S 16U 2421 #define LRFDPBE32_TIMPER0_TIMPRE_VAL_ALLONES 0xFFFF0000U 2422 #define LRFDPBE32_TIMPER0_TIMPRE_VAL_ALLZEROS 0x00000000U 2423 2424 // Field: [13:8] PRE1 2425 // 2426 // ENUMs: 2427 // DIV64 DIV64 mode 2428 // NO_DIV No prescaling 2429 #define LRFDPBE32_TIMPER0_TIMPRE_PRE1_W 6U 2430 #define LRFDPBE32_TIMPER0_TIMPRE_PRE1_M 0x00003F00U 2431 #define LRFDPBE32_TIMPER0_TIMPRE_PRE1_S 8U 2432 #define LRFDPBE32_TIMPER0_TIMPRE_PRE1_DIV64 0x00003F00U 2433 #define LRFDPBE32_TIMPER0_TIMPRE_PRE1_NO_DIV 0x00000000U 2434 2435 // Field: [5:0] PRE0 2436 // 2437 // ENUMs: 2438 // DIV64 DIV64 mode 2439 // NO_DIV No prescaling 2440 #define LRFDPBE32_TIMPER0_TIMPRE_PRE0_W 6U 2441 #define LRFDPBE32_TIMPER0_TIMPRE_PRE0_M 0x0000003FU 2442 #define LRFDPBE32_TIMPER0_TIMPRE_PRE0_S 0U 2443 #define LRFDPBE32_TIMPER0_TIMPRE_PRE0_DIV64 0x0000003FU 2444 #define LRFDPBE32_TIMPER0_TIMPRE_PRE0_NO_DIV 0x00000000U 2445 2446 //***************************************************************************** 2447 // 2448 // Register: LRFDPBE32_O_TIMCAPT0_TIMPER1 2449 // 2450 //***************************************************************************** 2451 // Field: [31:16] VALUE 2452 // 2453 // ENUMs: 2454 // ALLONES All the bits are 1 2455 // ALLZEROS All the bits are 0 2456 #define LRFDPBE32_TIMCAPT0_TIMPER1_VALUE_W 16U 2457 #define LRFDPBE32_TIMCAPT0_TIMPER1_VALUE_M 0xFFFF0000U 2458 #define LRFDPBE32_TIMCAPT0_TIMPER1_VALUE_S 16U 2459 #define LRFDPBE32_TIMCAPT0_TIMPER1_VALUE_ALLONES 0xFFFF0000U 2460 #define LRFDPBE32_TIMCAPT0_TIMPER1_VALUE_ALLZEROS 0x00000000U 2461 2462 // Field: [15:0] VAL 2463 // 2464 // ENUMs: 2465 // ALLONES All the bits are 1 2466 // ALLZEROS All the bits are 0 2467 #define LRFDPBE32_TIMCAPT0_TIMPER1_VAL_W 16U 2468 #define LRFDPBE32_TIMCAPT0_TIMPER1_VAL_M 0x0000FFFFU 2469 #define LRFDPBE32_TIMCAPT0_TIMPER1_VAL_S 0U 2470 #define LRFDPBE32_TIMCAPT0_TIMPER1_VAL_ALLONES 0x0000FFFFU 2471 #define LRFDPBE32_TIMCAPT0_TIMPER1_VAL_ALLZEROS 0x00000000U 2472 2473 //***************************************************************************** 2474 // 2475 // Register: LRFDPBE32_O_TIMCAPT1 2476 // 2477 //***************************************************************************** 2478 // Field: [15:0] VALUE 2479 // 2480 // ENUMs: 2481 // ALLONES All the bits are 1 2482 // ALLZEROS All the bits are 0 2483 #define LRFDPBE32_TIMCAPT1_VALUE_W 16U 2484 #define LRFDPBE32_TIMCAPT1_VALUE_M 0x0000FFFFU 2485 #define LRFDPBE32_TIMCAPT1_VALUE_S 0U 2486 #define LRFDPBE32_TIMCAPT1_VALUE_ALLONES 0x0000FFFFU 2487 #define LRFDPBE32_TIMCAPT1_VALUE_ALLZEROS 0x00000000U 2488 2489 //***************************************************************************** 2490 // 2491 // Register: LRFDPBE32_O_TRCSTAT_TRCCTL 2492 // 2493 //***************************************************************************** 2494 // Field: [16] BUSY 2495 // 2496 // ENUMs: 2497 // ONE The bit is 1 2498 // ZERO The bit is 0 2499 #define LRFDPBE32_TRCSTAT_TRCCTL_BUSY 0x00010000U 2500 #define LRFDPBE32_TRCSTAT_TRCCTL_BUSY_M 0x00010000U 2501 #define LRFDPBE32_TRCSTAT_TRCCTL_BUSY_S 16U 2502 #define LRFDPBE32_TRCSTAT_TRCCTL_BUSY_ONE 0x00010000U 2503 #define LRFDPBE32_TRCSTAT_TRCCTL_BUSY_ZERO 0x00000000U 2504 2505 // Field: [0] SEND 2506 // 2507 // ENUMs: 2508 // ONE The bit is 1 2509 // ZERO The bit is 0 2510 #define LRFDPBE32_TRCSTAT_TRCCTL_SEND 0x00000001U 2511 #define LRFDPBE32_TRCSTAT_TRCCTL_SEND_M 0x00000001U 2512 #define LRFDPBE32_TRCSTAT_TRCCTL_SEND_S 0U 2513 #define LRFDPBE32_TRCSTAT_TRCCTL_SEND_ONE 0x00000001U 2514 #define LRFDPBE32_TRCSTAT_TRCCTL_SEND_ZERO 0x00000000U 2515 2516 //***************************************************************************** 2517 // 2518 // Register: LRFDPBE32_O_TRCPAR0_TRCCMD 2519 // 2520 //***************************************************************************** 2521 // Field: [31:16] VAL 2522 // 2523 // ENUMs: 2524 // ALLONES All the bits are 1 2525 // ALLZEROS All the bits are 0 2526 #define LRFDPBE32_TRCPAR0_TRCCMD_VAL_W 16U 2527 #define LRFDPBE32_TRCPAR0_TRCCMD_VAL_M 0xFFFF0000U 2528 #define LRFDPBE32_TRCPAR0_TRCCMD_VAL_S 16U 2529 #define LRFDPBE32_TRCPAR0_TRCCMD_VAL_ALLONES 0xFFFF0000U 2530 #define LRFDPBE32_TRCPAR0_TRCCMD_VAL_ALLZEROS 0x00000000U 2531 2532 // Field: [9:8] PARCNT 2533 // 2534 // ENUMs: 2535 // ALLONES All the bits are 1 2536 // ALLZEROS All the bits are 0 2537 #define LRFDPBE32_TRCPAR0_TRCCMD_PARCNT_W 2U 2538 #define LRFDPBE32_TRCPAR0_TRCCMD_PARCNT_M 0x00000300U 2539 #define LRFDPBE32_TRCPAR0_TRCCMD_PARCNT_S 8U 2540 #define LRFDPBE32_TRCPAR0_TRCCMD_PARCNT_ALLONES 0x00000300U 2541 #define LRFDPBE32_TRCPAR0_TRCCMD_PARCNT_ALLZEROS 0x00000000U 2542 2543 // Field: [7:0] PKTHDR 2544 // 2545 // ENUMs: 2546 // ALLONES All the bits are 1 2547 // ALLZEROS All the bits are 0 2548 #define LRFDPBE32_TRCPAR0_TRCCMD_PKTHDR_W 8U 2549 #define LRFDPBE32_TRCPAR0_TRCCMD_PKTHDR_M 0x000000FFU 2550 #define LRFDPBE32_TRCPAR0_TRCCMD_PKTHDR_S 0U 2551 #define LRFDPBE32_TRCPAR0_TRCCMD_PKTHDR_ALLONES 0x000000FFU 2552 #define LRFDPBE32_TRCPAR0_TRCCMD_PKTHDR_ALLZEROS 0x00000000U 2553 2554 //***************************************************************************** 2555 // 2556 // Register: LRFDPBE32_O_GPOCTRL_TRCPAR1 2557 // 2558 //***************************************************************************** 2559 // Field: [23] GPO7 2560 // 2561 // ENUMs: 2562 // ONE The bit is 1 2563 // ZERO The bit is 0 2564 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO7 0x00800000U 2565 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO7_M 0x00800000U 2566 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO7_S 23U 2567 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO7_ONE 0x00800000U 2568 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO7_ZERO 0x00000000U 2569 2570 // Field: [22] GPO6 2571 // 2572 // ENUMs: 2573 // ONE The bit is 1 2574 // ZERO The bit is 0 2575 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO6 0x00400000U 2576 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO6_M 0x00400000U 2577 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO6_S 22U 2578 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO6_ONE 0x00400000U 2579 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO6_ZERO 0x00000000U 2580 2581 // Field: [21] GPO5 2582 // 2583 // ENUMs: 2584 // ONE The bit is 1 2585 // ZERO The bit is 0 2586 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO5 0x00200000U 2587 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO5_M 0x00200000U 2588 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO5_S 21U 2589 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO5_ONE 0x00200000U 2590 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO5_ZERO 0x00000000U 2591 2592 // Field: [20] GPO4 2593 // 2594 // ENUMs: 2595 // ONE The bit is 1 2596 // ZERO The bit is 0 2597 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO4 0x00100000U 2598 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO4_M 0x00100000U 2599 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO4_S 20U 2600 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO4_ONE 0x00100000U 2601 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO4_ZERO 0x00000000U 2602 2603 // Field: [19] GPO3 2604 // 2605 // ENUMs: 2606 // ONE The bit is 1 2607 // ZERO The bit is 0 2608 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO3 0x00080000U 2609 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO3_M 0x00080000U 2610 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO3_S 19U 2611 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO3_ONE 0x00080000U 2612 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO3_ZERO 0x00000000U 2613 2614 // Field: [18] GPO2 2615 // 2616 // ENUMs: 2617 // ONE The bit is 1 2618 // ZERO The bit is 0 2619 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO2 0x00040000U 2620 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO2_M 0x00040000U 2621 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO2_S 18U 2622 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO2_ONE 0x00040000U 2623 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO2_ZERO 0x00000000U 2624 2625 // Field: [17] GPO1 2626 // 2627 // ENUMs: 2628 // ONE The bit is 1 2629 // ZERO The bit is 0 2630 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO1 0x00020000U 2631 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO1_M 0x00020000U 2632 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO1_S 17U 2633 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO1_ONE 0x00020000U 2634 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO1_ZERO 0x00000000U 2635 2636 // Field: [16] GPO0 2637 // 2638 // ENUMs: 2639 // ONE The bit is 1 2640 // ZERO The bit is 0 2641 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO0 0x00010000U 2642 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO0_M 0x00010000U 2643 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO0_S 16U 2644 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO0_ONE 0x00010000U 2645 #define LRFDPBE32_GPOCTRL_TRCPAR1_GPO0_ZERO 0x00000000U 2646 2647 // Field: [15:0] VAL 2648 // 2649 // ENUMs: 2650 // ALLONES All the bits are 1 2651 // ALLZEROS All the bits are 0 2652 #define LRFDPBE32_GPOCTRL_TRCPAR1_VAL_W 16U 2653 #define LRFDPBE32_GPOCTRL_TRCPAR1_VAL_M 0x0000FFFFU 2654 #define LRFDPBE32_GPOCTRL_TRCPAR1_VAL_S 0U 2655 #define LRFDPBE32_GPOCTRL_TRCPAR1_VAL_ALLONES 0x0000FFFFU 2656 #define LRFDPBE32_GPOCTRL_TRCPAR1_VAL_ALLZEROS 0x00000000U 2657 2658 //***************************************************************************** 2659 // 2660 // Register: LRFDPBE32_O_MDMFRD_MDMFWR 2661 // 2662 //***************************************************************************** 2663 // Field: [31:16] PAYLOADOUT 2664 // 2665 // ENUMs: 2666 // ALLONES All the bits are 1 2667 // ALLZEROS All the bits are 0 2668 #define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADOUT_W 16U 2669 #define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADOUT_M 0xFFFF0000U 2670 #define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADOUT_S 16U 2671 #define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADOUT_ALLONES 0xFFFF0000U 2672 #define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADOUT_ALLZEROS 0x00000000U 2673 2674 // Field: [15:0] PAYLOADIN 2675 // 2676 // ENUMs: 2677 // ALLONES All the bits are 1 2678 // ALLZEROS All the bits are 0 2679 #define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADIN_W 16U 2680 #define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADIN_M 0x0000FFFFU 2681 #define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADIN_S 0U 2682 #define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADIN_ALLONES 0x0000FFFFU 2683 #define LRFDPBE32_MDMFRD_MDMFWR_PAYLOADIN_ALLZEROS 0x00000000U 2684 2685 //***************************************************************************** 2686 // 2687 // Register: LRFDPBE32_O_MDMFRDCTL_MDMFWRCTL 2688 // 2689 //***************************************************************************** 2690 // Field: [19:16] WORDSZRD 2691 // 2692 // ENUMs: 2693 // BITS16 16 bits 2694 // BITS15 15 bits 2695 // BITS14 14 bits 2696 // BITS13 13 bits 2697 // BITS12 12 bits 2698 // BITS11 11 bits 2699 // BITS10 10 bits 2700 // BITS9 9 bits 2701 // BITS8 8 bits 2702 // BITS7 7 bits 2703 // BITS6 6 bits 2704 // BITS5 5 bits 2705 // BITS4 4 bits 2706 // BITS3 3 bits 2707 // BITS2 2 bits 2708 // BITS1 1 bit 2709 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_W 4U 2710 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_M 0x000F0000U 2711 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_S 16U 2712 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS16 0x000F0000U 2713 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS15 0x000E0000U 2714 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS14 0x000D0000U 2715 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS13 0x000C0000U 2716 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS12 0x000B0000U 2717 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS11 0x000A0000U 2718 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS10 0x00090000U 2719 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS9 0x00080000U 2720 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS8 0x00070000U 2721 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS7 0x00060000U 2722 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS6 0x00050000U 2723 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS5 0x00040000U 2724 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS4 0x00030000U 2725 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS3 0x00020000U 2726 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS2 0x00010000U 2727 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZRD_BITS1 0x00000000U 2728 2729 // Field: [3:0] WORDSZWR 2730 // 2731 // ENUMs: 2732 // BITS16 16 bits 2733 // BITS15 15 bits 2734 // BITS14 14 bits 2735 // BITS13 13 bits 2736 // BITS12 12 bits 2737 // BITS11 11 bits 2738 // BITS10 10 bits 2739 // BITS9 9 bits 2740 // BITS8 8 bits 2741 // BITS7 7 bits 2742 // BITS6 6 bits 2743 // BITS5 5 bits 2744 // BITS4 4 bits 2745 // BITS3 3 bits 2746 // BITS2 2 bits 2747 // BITS1 1 bit 2748 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_W 4U 2749 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_M 0x0000000FU 2750 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_S 0U 2751 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS16 0x0000000FU 2752 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS15 0x0000000EU 2753 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS14 0x0000000DU 2754 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS13 0x0000000CU 2755 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS12 0x0000000BU 2756 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS11 0x0000000AU 2757 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS10 0x00000009U 2758 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS9 0x00000008U 2759 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS8 0x00000007U 2760 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS7 0x00000006U 2761 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS6 0x00000005U 2762 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS5 0x00000004U 2763 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS4 0x00000003U 2764 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS3 0x00000002U 2765 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS2 0x00000001U 2766 #define LRFDPBE32_MDMFRDCTL_MDMFWRCTL_WORDSZWR_BITS1 0x00000000U 2767 2768 //***************************************************************************** 2769 // 2770 // Register: LRFDPBE32_O_MDMFSTA_MDMFCFG 2771 // 2772 //***************************************************************************** 2773 // Field: [21] OVFL 2774 // 2775 // ENUMs: 2776 // ONE The bit is 1 2777 // ZERO The bit is 0 2778 #define LRFDPBE32_MDMFSTA_MDMFCFG_OVFL 0x00200000U 2779 #define LRFDPBE32_MDMFSTA_MDMFCFG_OVFL_M 0x00200000U 2780 #define LRFDPBE32_MDMFSTA_MDMFCFG_OVFL_S 21U 2781 #define LRFDPBE32_MDMFSTA_MDMFCFG_OVFL_ONE 0x00200000U 2782 #define LRFDPBE32_MDMFSTA_MDMFCFG_OVFL_ZERO 0x00000000U 2783 2784 // Field: [20] ALMOSTFULL 2785 // 2786 // ENUMs: 2787 // ONE The bit is 1 2788 // ZERO The bit is 0 2789 #define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTFULL 0x00100000U 2790 #define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTFULL_M 0x00100000U 2791 #define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTFULL_S 20U 2792 #define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTFULL_ONE 0x00100000U 2793 #define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTFULL_ZERO 0x00000000U 2794 2795 // Field: [19] ALMOSTEMPTY 2796 // 2797 // ENUMs: 2798 // ONE The bit is 1 2799 // ZERO The bit is 0 2800 #define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTEMPTY 0x00080000U 2801 #define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTEMPTY_M 0x00080000U 2802 #define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTEMPTY_S 19U 2803 #define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTEMPTY_ONE 0x00080000U 2804 #define LRFDPBE32_MDMFSTA_MDMFCFG_ALMOSTEMPTY_ZERO 0x00000000U 2805 2806 // Field: [18] UNFL 2807 // 2808 // ENUMs: 2809 // ONE The bit is 1 2810 // ZERO The bit is 0 2811 #define LRFDPBE32_MDMFSTA_MDMFCFG_UNFL 0x00040000U 2812 #define LRFDPBE32_MDMFSTA_MDMFCFG_UNFL_M 0x00040000U 2813 #define LRFDPBE32_MDMFSTA_MDMFCFG_UNFL_S 18U 2814 #define LRFDPBE32_MDMFSTA_MDMFCFG_UNFL_ONE 0x00040000U 2815 #define LRFDPBE32_MDMFSTA_MDMFCFG_UNFL_ZERO 0x00000000U 2816 2817 // Field: [17] RXVALID 2818 // 2819 // ENUMs: 2820 // ONE The bit is 1 2821 // ZERO The bit is 0 2822 #define LRFDPBE32_MDMFSTA_MDMFCFG_RXVALID 0x00020000U 2823 #define LRFDPBE32_MDMFSTA_MDMFCFG_RXVALID_M 0x00020000U 2824 #define LRFDPBE32_MDMFSTA_MDMFCFG_RXVALID_S 17U 2825 #define LRFDPBE32_MDMFSTA_MDMFCFG_RXVALID_ONE 0x00020000U 2826 #define LRFDPBE32_MDMFSTA_MDMFCFG_RXVALID_ZERO 0x00000000U 2827 2828 // Field: [16] TXREADY 2829 // 2830 // ENUMs: 2831 // ONE The bit is 1 2832 // ZERO The bit is 0 2833 #define LRFDPBE32_MDMFSTA_MDMFCFG_TXREADY 0x00010000U 2834 #define LRFDPBE32_MDMFSTA_MDMFCFG_TXREADY_M 0x00010000U 2835 #define LRFDPBE32_MDMFSTA_MDMFCFG_TXREADY_S 16U 2836 #define LRFDPBE32_MDMFSTA_MDMFCFG_TXREADY_ONE 0x00010000U 2837 #define LRFDPBE32_MDMFSTA_MDMFCFG_TXREADY_ZERO 0x00000000U 2838 2839 // Field: [15:8] AFULLTHR 2840 // 2841 // ENUMs: 2842 // ALLONES All the bits are 1 2843 // ALLZEROS All the bits are 0 2844 #define LRFDPBE32_MDMFSTA_MDMFCFG_AFULLTHR_W 8U 2845 #define LRFDPBE32_MDMFSTA_MDMFCFG_AFULLTHR_M 0x0000FF00U 2846 #define LRFDPBE32_MDMFSTA_MDMFCFG_AFULLTHR_S 8U 2847 #define LRFDPBE32_MDMFSTA_MDMFCFG_AFULLTHR_ALLONES 0x0000FF00U 2848 #define LRFDPBE32_MDMFSTA_MDMFCFG_AFULLTHR_ALLZEROS 0x00000000U 2849 2850 // Field: [7:0] AEMPTYTHR 2851 // 2852 // ENUMs: 2853 // ALLONES All the bits are 1 2854 // ALLZEROS All the bits are 0 2855 #define LRFDPBE32_MDMFSTA_MDMFCFG_AEMPTYTHR_W 8U 2856 #define LRFDPBE32_MDMFSTA_MDMFCFG_AEMPTYTHR_M 0x000000FFU 2857 #define LRFDPBE32_MDMFSTA_MDMFCFG_AEMPTYTHR_S 0U 2858 #define LRFDPBE32_MDMFSTA_MDMFCFG_AEMPTYTHR_ALLONES 0x000000FFU 2859 #define LRFDPBE32_MDMFSTA_MDMFCFG_AEMPTYTHR_ALLZEROS 0x00000000U 2860 2861 //***************************************************************************** 2862 // 2863 // Register: LRFDPBE32_O_PHASTA 2864 // 2865 //***************************************************************************** 2866 // Field: [17:16] BUSY 2867 // 2868 // ENUMs: 2869 // BUSY LFSR n sub-engine busy 2870 // IDLE LFSR n sub-engine idle 2871 #define LRFDPBE32_PHASTA_BUSY_W 2U 2872 #define LRFDPBE32_PHASTA_BUSY_M 0x00030000U 2873 #define LRFDPBE32_PHASTA_BUSY_S 16U 2874 #define LRFDPBE32_PHASTA_BUSY_BUSY 0x00010000U 2875 #define LRFDPBE32_PHASTA_BUSY_IDLE 0x00000000U 2876 2877 //***************************************************************************** 2878 // 2879 // Register: LRFDPBE32_O_LFSR0 2880 // 2881 //***************************************************************************** 2882 // Field: [31:0] VAL 2883 // 2884 // ENUMs: 2885 // ALLONES All the bits are 1 2886 // ALLZEROS All the bits are 0 2887 #define LRFDPBE32_LFSR0_VAL_W 32U 2888 #define LRFDPBE32_LFSR0_VAL_M 0xFFFFFFFFU 2889 #define LRFDPBE32_LFSR0_VAL_S 0U 2890 #define LRFDPBE32_LFSR0_VAL_ALLONES 0x0000FFFFU 2891 #define LRFDPBE32_LFSR0_VAL_ALLZEROS 0x00000000U 2892 2893 //***************************************************************************** 2894 // 2895 // Register: LRFDPBE32_O_LFSR0BR 2896 // 2897 //***************************************************************************** 2898 // Field: [31:0] VAL 2899 // 2900 // ENUMs: 2901 // ALLONES All the bits are 1 2902 // ALLZEROS All the bits are 0 2903 #define LRFDPBE32_LFSR0BR_VAL_W 32U 2904 #define LRFDPBE32_LFSR0BR_VAL_M 0xFFFFFFFFU 2905 #define LRFDPBE32_LFSR0BR_VAL_S 0U 2906 #define LRFDPBE32_LFSR0BR_VAL_ALLONES 0x0000FFFFU 2907 #define LRFDPBE32_LFSR0BR_VAL_ALLZEROS 0x00000000U 2908 2909 //***************************************************************************** 2910 // 2911 // Register: LRFDPBE32_O_LFSR1 2912 // 2913 //***************************************************************************** 2914 // Field: [31:0] VAL 2915 // 2916 // ENUMs: 2917 // ALLONES All the bits are 1 2918 // ALLZEROS All the bits are 0 2919 #define LRFDPBE32_LFSR1_VAL_W 32U 2920 #define LRFDPBE32_LFSR1_VAL_M 0xFFFFFFFFU 2921 #define LRFDPBE32_LFSR1_VAL_S 0U 2922 #define LRFDPBE32_LFSR1_VAL_ALLONES 0x0000FFFFU 2923 #define LRFDPBE32_LFSR1_VAL_ALLZEROS 0x00000000U 2924 2925 //***************************************************************************** 2926 // 2927 // Register: LRFDPBE32_O_LFSR1BR 2928 // 2929 //***************************************************************************** 2930 // Field: [31:0] VAL 2931 // 2932 // ENUMs: 2933 // ALLONES All the bits are 1 2934 // ALLZEROS All the bits are 0 2935 #define LRFDPBE32_LFSR1BR_VAL_W 32U 2936 #define LRFDPBE32_LFSR1BR_VAL_M 0xFFFFFFFFU 2937 #define LRFDPBE32_LFSR1BR_VAL_S 0U 2938 #define LRFDPBE32_LFSR1BR_VAL_ALLONES 0x0000FFFFU 2939 #define LRFDPBE32_LFSR1BR_VAL_ALLZEROS 0x00000000U 2940 2941 //***************************************************************************** 2942 // 2943 // Register: LRFDPBE32_O_LFSR0N_LFSR0INL 2944 // 2945 //***************************************************************************** 2946 // Field: [19:16] SIZE 2947 // 2948 // ENUMs: 2949 // ALLONES All the bits are 1 2950 // ALLZEROS All the bits are 0 2951 #define LRFDPBE32_LFSR0N_LFSR0INL_SIZE_W 4U 2952 #define LRFDPBE32_LFSR0N_LFSR0INL_SIZE_M 0x000F0000U 2953 #define LRFDPBE32_LFSR0N_LFSR0INL_SIZE_S 16U 2954 #define LRFDPBE32_LFSR0N_LFSR0INL_SIZE_ALLONES 0x000F0000U 2955 #define LRFDPBE32_LFSR0N_LFSR0INL_SIZE_ALLZEROS 0x00000000U 2956 2957 // Field: [15:0] VAL 2958 // 2959 // ENUMs: 2960 // ALLONES All the bits are 1 2961 // ALLZEROS All the bits are 0 2962 #define LRFDPBE32_LFSR0N_LFSR0INL_VAL_W 16U 2963 #define LRFDPBE32_LFSR0N_LFSR0INL_VAL_M 0x0000FFFFU 2964 #define LRFDPBE32_LFSR0N_LFSR0INL_VAL_S 0U 2965 #define LRFDPBE32_LFSR0N_LFSR0INL_VAL_ALLONES 0x00000003U 2966 #define LRFDPBE32_LFSR0N_LFSR0INL_VAL_ALLZEROS 0x00000000U 2967 2968 //***************************************************************************** 2969 // 2970 // Register: LRFDPBE32_O_PHAOUT0_LFSR0INM 2971 // 2972 //***************************************************************************** 2973 // Field: [31:16] PHAOUT0_VAL 2974 // 2975 // ENUMs: 2976 // ALLONES All the bits are 1 2977 // ALLZEROS All the bits are 0 2978 #define LRFDPBE32_PHAOUT0_LFSR0INM_PHAOUT0_VAL_W 16U 2979 #define LRFDPBE32_PHAOUT0_LFSR0INM_PHAOUT0_VAL_M 0xFFFF0000U 2980 #define LRFDPBE32_PHAOUT0_LFSR0INM_PHAOUT0_VAL_S 16U 2981 #define LRFDPBE32_PHAOUT0_LFSR0INM_PHAOUT0_VAL_ALLONES 0xDCD70000U 2982 #define LRFDPBE32_PHAOUT0_LFSR0INM_PHAOUT0_VAL_ALLZEROS 0x00000000U 2983 2984 // Field: [15:0] LFSR0INM_VAL 2985 // 2986 // ENUMs: 2987 // ONE The bit is 1 2988 // ZERO The bit is 0 2989 #define LRFDPBE32_PHAOUT0_LFSR0INM_LFSR0INM_VAL_W 16U 2990 #define LRFDPBE32_PHAOUT0_LFSR0INM_LFSR0INM_VAL_M 0x0000FFFFU 2991 #define LRFDPBE32_PHAOUT0_LFSR0INM_LFSR0INM_VAL_S 0U 2992 #define LRFDPBE32_PHAOUT0_LFSR0INM_LFSR0INM_VAL_ONE 0x00000001U 2993 #define LRFDPBE32_PHAOUT0_LFSR0INM_LFSR0INM_VAL_ZERO 0x00000000U 2994 2995 //***************************************************************************** 2996 // 2997 // Register: LRFDPBE32_O_LFSR1N_LFSR1INL 2998 // 2999 //***************************************************************************** 3000 // Field: [19:16] SIZE 3001 // 3002 // ENUMs: 3003 // ALLONES All the bits are 1 3004 // ALLZEROS All the bits are 0 3005 #define LRFDPBE32_LFSR1N_LFSR1INL_SIZE_W 4U 3006 #define LRFDPBE32_LFSR1N_LFSR1INL_SIZE_M 0x000F0000U 3007 #define LRFDPBE32_LFSR1N_LFSR1INL_SIZE_S 16U 3008 #define LRFDPBE32_LFSR1N_LFSR1INL_SIZE_ALLONES 0x000F0000U 3009 #define LRFDPBE32_LFSR1N_LFSR1INL_SIZE_ALLZEROS 0x00000000U 3010 3011 // Field: [15:0] VAL 3012 // 3013 // ENUMs: 3014 // ALLONES All the bits are 1 3015 // ALLZEROS All the bits are 0 3016 #define LRFDPBE32_LFSR1N_LFSR1INL_VAL_W 16U 3017 #define LRFDPBE32_LFSR1N_LFSR1INL_VAL_M 0x0000FFFFU 3018 #define LRFDPBE32_LFSR1N_LFSR1INL_VAL_S 0U 3019 #define LRFDPBE32_LFSR1N_LFSR1INL_VAL_ALLONES 0x00000003U 3020 #define LRFDPBE32_LFSR1N_LFSR1INL_VAL_ALLZEROS 0x00000000U 3021 3022 //***************************************************************************** 3023 // 3024 // Register: LRFDPBE32_O_PHAOUT0BR_LFSR1INM 3025 // 3026 //***************************************************************************** 3027 // Field: [31:16] PHAOUT0BR_VAL 3028 // 3029 // ENUMs: 3030 // ALLONES All the bits are 1 3031 // ALLZEROS All the bits are 0 3032 #define LRFDPBE32_PHAOUT0BR_LFSR1INM_PHAOUT0BR_VAL_W 16U 3033 #define LRFDPBE32_PHAOUT0BR_LFSR1INM_PHAOUT0BR_VAL_M 0xFFFF0000U 3034 #define LRFDPBE32_PHAOUT0BR_LFSR1INM_PHAOUT0BR_VAL_S 16U 3035 #define LRFDPBE32_PHAOUT0BR_LFSR1INM_PHAOUT0BR_VAL_ALLONES 0xFFFF0000U 3036 #define LRFDPBE32_PHAOUT0BR_LFSR1INM_PHAOUT0BR_VAL_ALLZEROS 0x00000000U 3037 3038 // Field: [15:0] LFSR1INM_VAL 3039 // 3040 // ENUMs: 3041 // ONE The bit is 1 3042 // ZERO The bit is 0 3043 #define LRFDPBE32_PHAOUT0BR_LFSR1INM_LFSR1INM_VAL_W 16U 3044 #define LRFDPBE32_PHAOUT0BR_LFSR1INM_LFSR1INM_VAL_M 0x0000FFFFU 3045 #define LRFDPBE32_PHAOUT0BR_LFSR1INM_LFSR1INM_VAL_S 0U 3046 #define LRFDPBE32_PHAOUT0BR_LFSR1INM_LFSR1INM_VAL_ONE 0x00000001U 3047 #define LRFDPBE32_PHAOUT0BR_LFSR1INM_LFSR1INM_VAL_ZERO 0x00000000U 3048 3049 //***************************************************************************** 3050 // 3051 // Register: LRFDPBE32_O_SYSTIM0 3052 // 3053 //***************************************************************************** 3054 // Field: [31:0] VAL 3055 // 3056 // ENUMs: 3057 // ONE The bit is 1 3058 // ZERO The bit is 0 3059 #define LRFDPBE32_SYSTIM0_VAL_W 32U 3060 #define LRFDPBE32_SYSTIM0_VAL_M 0xFFFFFFFFU 3061 #define LRFDPBE32_SYSTIM0_VAL_S 0U 3062 #define LRFDPBE32_SYSTIM0_VAL_ONE 0x00000001U 3063 #define LRFDPBE32_SYSTIM0_VAL_ZERO 0x00000000U 3064 3065 //***************************************************************************** 3066 // 3067 // Register: LRFDPBE32_O_SYSTIM1 3068 // 3069 //***************************************************************************** 3070 // Field: [31:0] VAL 3071 // 3072 // ENUMs: 3073 // ONE The bit is 1 3074 // ZERO The bit is 0 3075 #define LRFDPBE32_SYSTIM1_VAL_W 32U 3076 #define LRFDPBE32_SYSTIM1_VAL_M 0xFFFFFFFFU 3077 #define LRFDPBE32_SYSTIM1_VAL_S 0U 3078 #define LRFDPBE32_SYSTIM1_VAL_ONE 0x00000001U 3079 #define LRFDPBE32_SYSTIM1_VAL_ZERO 0x00000000U 3080 3081 //***************************************************************************** 3082 // 3083 // Register: LRFDPBE32_O_SYSTIM2 3084 // 3085 //***************************************************************************** 3086 // Field: [31:0] VAL 3087 // 3088 // ENUMs: 3089 // ONE The bit is 1 3090 // ZERO The bit is 0 3091 #define LRFDPBE32_SYSTIM2_VAL_W 32U 3092 #define LRFDPBE32_SYSTIM2_VAL_M 0xFFFFFFFFU 3093 #define LRFDPBE32_SYSTIM2_VAL_S 0U 3094 #define LRFDPBE32_SYSTIM2_VAL_ONE 0x00000001U 3095 #define LRFDPBE32_SYSTIM2_VAL_ZERO 0x00000000U 3096 3097 //***************************************************************************** 3098 // 3099 // Register: LRFDPBE32_O_GPI 3100 // 3101 //***************************************************************************** 3102 // Field: [7] GPI7 3103 // 3104 // ENUMs: 3105 // ONE The bit is 1 3106 // ZERO The bit is 0 3107 #define LRFDPBE32_GPI_GPI7 0x00000080U 3108 #define LRFDPBE32_GPI_GPI7_M 0x00000080U 3109 #define LRFDPBE32_GPI_GPI7_S 7U 3110 #define LRFDPBE32_GPI_GPI7_ONE 0x00000080U 3111 #define LRFDPBE32_GPI_GPI7_ZERO 0x00000000U 3112 3113 // Field: [6] GPI6 3114 // 3115 // ENUMs: 3116 // ONE The bit is 1 3117 // ZERO The bit is 0 3118 #define LRFDPBE32_GPI_GPI6 0x00000040U 3119 #define LRFDPBE32_GPI_GPI6_M 0x00000040U 3120 #define LRFDPBE32_GPI_GPI6_S 6U 3121 #define LRFDPBE32_GPI_GPI6_ONE 0x00000040U 3122 #define LRFDPBE32_GPI_GPI6_ZERO 0x00000000U 3123 3124 // Field: [5] GPI5 3125 // 3126 // ENUMs: 3127 // ONE The bit is 1 3128 // ZERO The bit is 0 3129 #define LRFDPBE32_GPI_GPI5 0x00000020U 3130 #define LRFDPBE32_GPI_GPI5_M 0x00000020U 3131 #define LRFDPBE32_GPI_GPI5_S 5U 3132 #define LRFDPBE32_GPI_GPI5_ONE 0x00000020U 3133 #define LRFDPBE32_GPI_GPI5_ZERO 0x00000000U 3134 3135 // Field: [4] GPI4 3136 // 3137 // ENUMs: 3138 // ONE The bit is 1 3139 // ZERO The bit is 0 3140 #define LRFDPBE32_GPI_GPI4 0x00000010U 3141 #define LRFDPBE32_GPI_GPI4_M 0x00000010U 3142 #define LRFDPBE32_GPI_GPI4_S 4U 3143 #define LRFDPBE32_GPI_GPI4_ONE 0x00000010U 3144 #define LRFDPBE32_GPI_GPI4_ZERO 0x00000000U 3145 3146 // Field: [3] GPI3 3147 // 3148 // ENUMs: 3149 // ONE The bit is 1 3150 // ZERO The bit is 0 3151 #define LRFDPBE32_GPI_GPI3 0x00000008U 3152 #define LRFDPBE32_GPI_GPI3_M 0x00000008U 3153 #define LRFDPBE32_GPI_GPI3_S 3U 3154 #define LRFDPBE32_GPI_GPI3_ONE 0x00000008U 3155 #define LRFDPBE32_GPI_GPI3_ZERO 0x00000000U 3156 3157 // Field: [2] GPI2 3158 // 3159 // ENUMs: 3160 // ONE The bit is 1 3161 // ZERO The bit is 0 3162 #define LRFDPBE32_GPI_GPI2 0x00000004U 3163 #define LRFDPBE32_GPI_GPI2_M 0x00000004U 3164 #define LRFDPBE32_GPI_GPI2_S 2U 3165 #define LRFDPBE32_GPI_GPI2_ONE 0x00000004U 3166 #define LRFDPBE32_GPI_GPI2_ZERO 0x00000000U 3167 3168 // Field: [1] GPI1 3169 // 3170 // ENUMs: 3171 // ONE The bit is 1 3172 // ZERO The bit is 0 3173 #define LRFDPBE32_GPI_GPI1 0x00000002U 3174 #define LRFDPBE32_GPI_GPI1_M 0x00000002U 3175 #define LRFDPBE32_GPI_GPI1_S 1U 3176 #define LRFDPBE32_GPI_GPI1_ONE 0x00000002U 3177 #define LRFDPBE32_GPI_GPI1_ZERO 0x00000000U 3178 3179 // Field: [0] GPI0 3180 // 3181 // ENUMs: 3182 // ONE The bit is 1 3183 // ZERO The bit is 0 3184 #define LRFDPBE32_GPI_GPI0 0x00000001U 3185 #define LRFDPBE32_GPI_GPI0_M 0x00000001U 3186 #define LRFDPBE32_GPI_GPI0_S 0U 3187 #define LRFDPBE32_GPI_GPI0_ONE 0x00000001U 3188 #define LRFDPBE32_GPI_GPI0_ZERO 0x00000000U 3189 3190 //***************************************************************************** 3191 // 3192 // Register: LRFDPBE32_O_FSTAT_FCMD 3193 // 3194 //***************************************************************************** 3195 // Field: [27] TXUNFL 3196 // 3197 // ENUMs: 3198 // TRUE Underflow has occurred 3199 // FALSE Normal operation ensues 3200 #define LRFDPBE32_FSTAT_FCMD_TXUNFL 0x08000000U 3201 #define LRFDPBE32_FSTAT_FCMD_TXUNFL_M 0x08000000U 3202 #define LRFDPBE32_FSTAT_FCMD_TXUNFL_S 27U 3203 #define LRFDPBE32_FSTAT_FCMD_TXUNFL_TRUE 0x08000000U 3204 #define LRFDPBE32_FSTAT_FCMD_TXUNFL_FALSE 0x00000000U 3205 3206 // Field: [26] TXOVFL 3207 // 3208 // ENUMs: 3209 // TRUE Overflow has occurred 3210 // FALSE Normal operation ensues 3211 #define LRFDPBE32_FSTAT_FCMD_TXOVFL 0x04000000U 3212 #define LRFDPBE32_FSTAT_FCMD_TXOVFL_M 0x04000000U 3213 #define LRFDPBE32_FSTAT_FCMD_TXOVFL_S 26U 3214 #define LRFDPBE32_FSTAT_FCMD_TXOVFL_TRUE 0x04000000U 3215 #define LRFDPBE32_FSTAT_FCMD_TXOVFL_FALSE 0x00000000U 3216 3217 // Field: [25] TXEMPTY 3218 // 3219 // ENUMs: 3220 // TRUE TXFIFO is empty 3221 // FALSE TXFIFO is not empty 3222 #define LRFDPBE32_FSTAT_FCMD_TXEMPTY 0x02000000U 3223 #define LRFDPBE32_FSTAT_FCMD_TXEMPTY_M 0x02000000U 3224 #define LRFDPBE32_FSTAT_FCMD_TXEMPTY_S 25U 3225 #define LRFDPBE32_FSTAT_FCMD_TXEMPTY_TRUE 0x02000000U 3226 #define LRFDPBE32_FSTAT_FCMD_TXEMPTY_FALSE 0x00000000U 3227 3228 // Field: [24] TXFULL 3229 // 3230 // ENUMs: 3231 // TRUE TXFIFO is full 3232 // FALSE TXFIFO is not full 3233 #define LRFDPBE32_FSTAT_FCMD_TXFULL 0x01000000U 3234 #define LRFDPBE32_FSTAT_FCMD_TXFULL_M 0x01000000U 3235 #define LRFDPBE32_FSTAT_FCMD_TXFULL_S 24U 3236 #define LRFDPBE32_FSTAT_FCMD_TXFULL_TRUE 0x01000000U 3237 #define LRFDPBE32_FSTAT_FCMD_TXFULL_FALSE 0x00000000U 3238 3239 // Field: [19] RXUNFL 3240 // 3241 // ENUMs: 3242 // TRUE Underflow has occurred 3243 // FALSE Normal operation ensues 3244 #define LRFDPBE32_FSTAT_FCMD_RXUNFL 0x00080000U 3245 #define LRFDPBE32_FSTAT_FCMD_RXUNFL_M 0x00080000U 3246 #define LRFDPBE32_FSTAT_FCMD_RXUNFL_S 19U 3247 #define LRFDPBE32_FSTAT_FCMD_RXUNFL_TRUE 0x00080000U 3248 #define LRFDPBE32_FSTAT_FCMD_RXUNFL_FALSE 0x00000000U 3249 3250 // Field: [18] RXOVFL 3251 // 3252 // ENUMs: 3253 // TRUE Overflow has occurred 3254 // FALSE Normal operation ensues 3255 #define LRFDPBE32_FSTAT_FCMD_RXOVFL 0x00040000U 3256 #define LRFDPBE32_FSTAT_FCMD_RXOVFL_M 0x00040000U 3257 #define LRFDPBE32_FSTAT_FCMD_RXOVFL_S 18U 3258 #define LRFDPBE32_FSTAT_FCMD_RXOVFL_TRUE 0x00040000U 3259 #define LRFDPBE32_FSTAT_FCMD_RXOVFL_FALSE 0x00000000U 3260 3261 // Field: [17] RXEMPTY 3262 // 3263 // ENUMs: 3264 // TRUE RXFIFO is empty 3265 // FALSE RXFIFO is not empty 3266 #define LRFDPBE32_FSTAT_FCMD_RXEMPTY 0x00020000U 3267 #define LRFDPBE32_FSTAT_FCMD_RXEMPTY_M 0x00020000U 3268 #define LRFDPBE32_FSTAT_FCMD_RXEMPTY_S 17U 3269 #define LRFDPBE32_FSTAT_FCMD_RXEMPTY_TRUE 0x00020000U 3270 #define LRFDPBE32_FSTAT_FCMD_RXEMPTY_FALSE 0x00000000U 3271 3272 // Field: [16] RXFULL 3273 // 3274 // ENUMs: 3275 // TRUE RXFIFO is full 3276 // FALSE RXFIFO is not full 3277 #define LRFDPBE32_FSTAT_FCMD_RXFULL 0x00010000U 3278 #define LRFDPBE32_FSTAT_FCMD_RXFULL_M 0x00010000U 3279 #define LRFDPBE32_FSTAT_FCMD_RXFULL_S 16U 3280 #define LRFDPBE32_FSTAT_FCMD_RXFULL_TRUE 0x00010000U 3281 #define LRFDPBE32_FSTAT_FCMD_RXFULL_FALSE 0x00000000U 3282 3283 // Field: [7:0] DATA 3284 // 3285 // ENUMs: 3286 // FIFO_COMMIT Commit both FIFOs 3287 // FIFO_DISCARD Discard both FIFOs 3288 // FIFO_RETRY Retry both FIFOs 3289 // FIFO_DEALLOC Deallocate both FIFOS 3290 // FIFO_RESET Reset (empty) both FIFOs 3291 // RXFIFO_RETRY Retry rxfifo. This sets RXFRP := RXFSRP 3292 // RXFIFO_DISCARD Discard rxfifo. This sets RXFWP := RXFSWP 3293 // RXFIFO_COMMIT Commit rxfifo. This sets RXFSWP := RXFWP 3294 // TXFIFO_RESET Reset (empty) txfifo. Set TXF* := 0 3295 // TXFIFO_DEALLOC Deallocate txfifo. This sets TXFSRP := TXFRP. 3296 // TXFIFO_RETRY Retry txfifo. This sets TXFRP := TXFSRP 3297 // TXFIFO_DISCARD Discard txfifo. This sets TXFWP := TXFSWP 3298 // TXFIFO_COMMIT Commit txfifo. This sets TXFSWP := TXFWP 3299 // RXFIFO_DEALLOC Deallocate rxfifo. This sets RXFSRP := RXFRP. 3300 // RXFIFO_RESET Reset (empty) rxfifo. Set RXF* := 0 3301 #define LRFDPBE32_FSTAT_FCMD_DATA_W 8U 3302 #define LRFDPBE32_FSTAT_FCMD_DATA_M 0x000000FFU 3303 #define LRFDPBE32_FSTAT_FCMD_DATA_S 0U 3304 #define LRFDPBE32_FSTAT_FCMD_DATA_FIFO_COMMIT 0x0000000FU 3305 #define LRFDPBE32_FSTAT_FCMD_DATA_FIFO_DISCARD 0x0000000EU 3306 #define LRFDPBE32_FSTAT_FCMD_DATA_FIFO_RETRY 0x0000000DU 3307 #define LRFDPBE32_FSTAT_FCMD_DATA_FIFO_DEALLOC 0x0000000CU 3308 #define LRFDPBE32_FSTAT_FCMD_DATA_FIFO_RESET 0x0000000BU 3309 #define LRFDPBE32_FSTAT_FCMD_DATA_RXFIFO_RETRY 0x0000000AU 3310 #define LRFDPBE32_FSTAT_FCMD_DATA_RXFIFO_DISCARD 0x00000009U 3311 #define LRFDPBE32_FSTAT_FCMD_DATA_RXFIFO_COMMIT 0x00000008U 3312 #define LRFDPBE32_FSTAT_FCMD_DATA_TXFIFO_RESET 0x00000007U 3313 #define LRFDPBE32_FSTAT_FCMD_DATA_TXFIFO_DEALLOC 0x00000006U 3314 #define LRFDPBE32_FSTAT_FCMD_DATA_TXFIFO_RETRY 0x00000005U 3315 #define LRFDPBE32_FSTAT_FCMD_DATA_TXFIFO_DISCARD 0x00000004U 3316 #define LRFDPBE32_FSTAT_FCMD_DATA_TXFIFO_COMMIT 0x00000003U 3317 #define LRFDPBE32_FSTAT_FCMD_DATA_RXFIFO_DEALLOC 0x00000002U 3318 #define LRFDPBE32_FSTAT_FCMD_DATA_RXFIFO_RESET 0x00000001U 3319 3320 //***************************************************************************** 3321 // 3322 // Register: LRFDPBE32_O_RXFRP_RXFWP 3323 // 3324 //***************************************************************************** 3325 // Field: [25:16] RXFRP_PTR 3326 // 3327 // ENUMs: 3328 // ALLONES All the bits are 1 3329 // ALLZEROS All the bits are 0 3330 #define LRFDPBE32_RXFRP_RXFWP_RXFRP_PTR_W 10U 3331 #define LRFDPBE32_RXFRP_RXFWP_RXFRP_PTR_M 0x03FF0000U 3332 #define LRFDPBE32_RXFRP_RXFWP_RXFRP_PTR_S 16U 3333 #define LRFDPBE32_RXFRP_RXFWP_RXFRP_PTR_ALLONES 0x03FF0000U 3334 #define LRFDPBE32_RXFRP_RXFWP_RXFRP_PTR_ALLZEROS 0x00000000U 3335 3336 // Field: [9:0] RXFWP_PTR 3337 // 3338 // ENUMs: 3339 // ALLONES All the bits are 1 3340 // ALLZEROS All the bits are 0 3341 #define LRFDPBE32_RXFRP_RXFWP_RXFWP_PTR_W 10U 3342 #define LRFDPBE32_RXFRP_RXFWP_RXFWP_PTR_M 0x000003FFU 3343 #define LRFDPBE32_RXFRP_RXFWP_RXFWP_PTR_S 0U 3344 #define LRFDPBE32_RXFRP_RXFWP_RXFWP_PTR_ALLONES 0x000003FFU 3345 #define LRFDPBE32_RXFRP_RXFWP_RXFWP_PTR_ALLZEROS 0x00000000U 3346 3347 //***************************************************************************** 3348 // 3349 // Register: LRFDPBE32_O_RXFSRP_RXFSWP 3350 // 3351 //***************************************************************************** 3352 // Field: [25:16] RXFSRP_PTR 3353 // 3354 // ENUMs: 3355 // ALLONES All the bits are 1 3356 // ALLZEROS All the bits are 0 3357 #define LRFDPBE32_RXFSRP_RXFSWP_RXFSRP_PTR_W 10U 3358 #define LRFDPBE32_RXFSRP_RXFSWP_RXFSRP_PTR_M 0x03FF0000U 3359 #define LRFDPBE32_RXFSRP_RXFSWP_RXFSRP_PTR_S 16U 3360 #define LRFDPBE32_RXFSRP_RXFSWP_RXFSRP_PTR_ALLONES 0x03FF0000U 3361 #define LRFDPBE32_RXFSRP_RXFSWP_RXFSRP_PTR_ALLZEROS 0x00000000U 3362 3363 // Field: [9:0] RXFSWP_PTR 3364 // 3365 // ENUMs: 3366 // ALLONES All the bits are 1 3367 // ALLZEROS All the bits are 0 3368 #define LRFDPBE32_RXFSRP_RXFSWP_RXFSWP_PTR_W 10U 3369 #define LRFDPBE32_RXFSRP_RXFSWP_RXFSWP_PTR_M 0x000003FFU 3370 #define LRFDPBE32_RXFSRP_RXFSWP_RXFSWP_PTR_S 0U 3371 #define LRFDPBE32_RXFSRP_RXFSWP_RXFSWP_PTR_ALLONES 0x000003FFU 3372 #define LRFDPBE32_RXFSRP_RXFSWP_RXFSWP_PTR_ALLZEROS 0x00000000U 3373 3374 //***************************************************************************** 3375 // 3376 // Register: LRFDPBE32_O_TXFRP_TXFWP 3377 // 3378 //***************************************************************************** 3379 // Field: [25:16] TXFRP_PTR 3380 // 3381 // ENUMs: 3382 // ALLONES All the bits are 1 3383 // ALLZEROS All the bits are 0 3384 #define LRFDPBE32_TXFRP_TXFWP_TXFRP_PTR_W 10U 3385 #define LRFDPBE32_TXFRP_TXFWP_TXFRP_PTR_M 0x03FF0000U 3386 #define LRFDPBE32_TXFRP_TXFWP_TXFRP_PTR_S 16U 3387 #define LRFDPBE32_TXFRP_TXFWP_TXFRP_PTR_ALLONES 0x03FF0000U 3388 #define LRFDPBE32_TXFRP_TXFWP_TXFRP_PTR_ALLZEROS 0x00000000U 3389 3390 // Field: [9:0] TXFWP_PTR 3391 // 3392 // ENUMs: 3393 // ALLONES All the bits are 1 3394 // ALLZEROS All the bits are 0 3395 #define LRFDPBE32_TXFRP_TXFWP_TXFWP_PTR_W 10U 3396 #define LRFDPBE32_TXFRP_TXFWP_TXFWP_PTR_M 0x000003FFU 3397 #define LRFDPBE32_TXFRP_TXFWP_TXFWP_PTR_S 0U 3398 #define LRFDPBE32_TXFRP_TXFWP_TXFWP_PTR_ALLONES 0x000003FFU 3399 #define LRFDPBE32_TXFRP_TXFWP_TXFWP_PTR_ALLZEROS 0x00000000U 3400 3401 //***************************************************************************** 3402 // 3403 // Register: LRFDPBE32_O_TXFSRP_TXFSWP 3404 // 3405 //***************************************************************************** 3406 // Field: [25:16] TXFSRP_PTR 3407 // 3408 // ENUMs: 3409 // ALLONES_2 All the bits are 1 3410 // ALLZEROS All the bits are 0 3411 #define LRFDPBE32_TXFSRP_TXFSWP_TXFSRP_PTR_W 10U 3412 #define LRFDPBE32_TXFSRP_TXFSWP_TXFSRP_PTR_M 0x03FF0000U 3413 #define LRFDPBE32_TXFSRP_TXFSWP_TXFSRP_PTR_S 16U 3414 #define LRFDPBE32_TXFSRP_TXFSWP_TXFSRP_PTR_ALLONES_2 0x03FF0000U 3415 #define LRFDPBE32_TXFSRP_TXFSWP_TXFSRP_PTR_ALLZEROS 0x00000000U 3416 3417 // Field: [9:0] TXFSWP_PTR 3418 // 3419 // ENUMs: 3420 // ALLONES All the bits are 1 3421 // ALLZEROS All the bits are 0 3422 #define LRFDPBE32_TXFSRP_TXFSWP_TXFSWP_PTR_W 10U 3423 #define LRFDPBE32_TXFSRP_TXFSWP_TXFSWP_PTR_M 0x000003FFU 3424 #define LRFDPBE32_TXFSRP_TXFSWP_TXFSWP_PTR_S 0U 3425 #define LRFDPBE32_TXFSRP_TXFSWP_TXFSWP_PTR_ALLONES 0x000003FFU 3426 #define LRFDPBE32_TXFSRP_TXFSWP_TXFSWP_PTR_ALLZEROS 0x00000000U 3427 3428 //***************************************************************************** 3429 // 3430 // Register: LRFDPBE32_O_RXFREADABLE_RXFWRITABLE 3431 // 3432 //***************************************************************************** 3433 // Field: [25:16] RXFREADABLE_BYTES 3434 // 3435 // ENUMs: 3436 // ALLONES All the bits are 1 3437 // ALLZEROS All the bits are 0 3438 #define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFREADABLE_BYTES_W 10U 3439 #define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFREADABLE_BYTES_M 0x03FF0000U 3440 #define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFREADABLE_BYTES_S 16U 3441 #define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFREADABLE_BYTES_ALLONES \ 3442 0x03FF0000U 3443 #define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFREADABLE_BYTES_ALLZEROS \ 3444 0x00000000U 3445 3446 // Field: [9:0] RXFWRITABLE_BYTES 3447 // 3448 // ENUMs: 3449 // ALLONES All the bits are 1 3450 // ALLZEROS All the bits are 0 3451 #define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFWRITABLE_BYTES_W 10U 3452 #define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFWRITABLE_BYTES_M 0x000003FFU 3453 #define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFWRITABLE_BYTES_S 0U 3454 #define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFWRITABLE_BYTES_ALLONES \ 3455 0x000003FFU 3456 #define LRFDPBE32_RXFREADABLE_RXFWRITABLE_RXFWRITABLE_BYTES_ALLZEROS \ 3457 0x00000000U 3458 3459 //***************************************************************************** 3460 // 3461 // Register: LRFDPBE32_O_TXFREADABLE_TXFWRITABLE 3462 // 3463 //***************************************************************************** 3464 // Field: [25:16] TXFREADABLE_BYTES 3465 // 3466 // ENUMs: 3467 // ALLONES All the bits are 1 3468 // ALLZEROS All the bits are 0 3469 #define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFREADABLE_BYTES_W 10U 3470 #define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFREADABLE_BYTES_M 0x03FF0000U 3471 #define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFREADABLE_BYTES_S 16U 3472 #define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFREADABLE_BYTES_ALLONES \ 3473 0x03FF0000U 3474 #define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFREADABLE_BYTES_ALLZEROS \ 3475 0x00000000U 3476 3477 // Field: [9:0] TXFWRITABLE_BYTES 3478 // 3479 // ENUMs: 3480 // ALLONES All the bits are 1 3481 // ALLZEROS All the bits are 0 3482 #define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFWRITABLE_BYTES_W 10U 3483 #define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFWRITABLE_BYTES_M 0x000003FFU 3484 #define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFWRITABLE_BYTES_S 0U 3485 #define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFWRITABLE_BYTES_ALLONES \ 3486 0x000003FFU 3487 #define LRFDPBE32_TXFREADABLE_TXFWRITABLE_TXFWRITABLE_BYTES_ALLZEROS \ 3488 0x00000000U 3489 3490 //***************************************************************************** 3491 // 3492 // Register: LRFDPBE32_O_RXFBWR_RXFBRD 3493 // 3494 //***************************************************************************** 3495 // Field: [23:16] RXFBWR_DATA 3496 // 3497 // ENUMs: 3498 // ALLONES All the bits are 1 3499 // ALLZEROS All the bits are 0 3500 #define LRFDPBE32_RXFBWR_RXFBRD_RXFBWR_DATA_W 8U 3501 #define LRFDPBE32_RXFBWR_RXFBRD_RXFBWR_DATA_M 0x00FF0000U 3502 #define LRFDPBE32_RXFBWR_RXFBRD_RXFBWR_DATA_S 16U 3503 #define LRFDPBE32_RXFBWR_RXFBRD_RXFBWR_DATA_ALLONES 0x00FF0000U 3504 #define LRFDPBE32_RXFBWR_RXFBRD_RXFBWR_DATA_ALLZEROS 0x00000000U 3505 3506 // Field: [7:0] RXFBRD_DATA 3507 // 3508 // ENUMs: 3509 // ALLONES All the bits are 1 3510 // ALLZEROS All the bits are 0 3511 #define LRFDPBE32_RXFBWR_RXFBRD_RXFBRD_DATA_W 8U 3512 #define LRFDPBE32_RXFBWR_RXFBRD_RXFBRD_DATA_M 0x000000FFU 3513 #define LRFDPBE32_RXFBWR_RXFBRD_RXFBRD_DATA_S 0U 3514 #define LRFDPBE32_RXFBWR_RXFBRD_RXFBRD_DATA_ALLONES 0x000000FFU 3515 #define LRFDPBE32_RXFBWR_RXFBRD_RXFBRD_DATA_ALLZEROS 0x00000000U 3516 3517 //***************************************************************************** 3518 // 3519 // Register: LRFDPBE32_O_TXFBWR_TXFBRD 3520 // 3521 //***************************************************************************** 3522 // Field: [23:16] TXFBWR_DATA 3523 // 3524 // ENUMs: 3525 // ALLONES All the bits are 1 3526 // ALLZEROS All the bits are 0 3527 #define LRFDPBE32_TXFBWR_TXFBRD_TXFBWR_DATA_W 8U 3528 #define LRFDPBE32_TXFBWR_TXFBRD_TXFBWR_DATA_M 0x00FF0000U 3529 #define LRFDPBE32_TXFBWR_TXFBRD_TXFBWR_DATA_S 16U 3530 #define LRFDPBE32_TXFBWR_TXFBRD_TXFBWR_DATA_ALLONES 0x00FF0000U 3531 #define LRFDPBE32_TXFBWR_TXFBRD_TXFBWR_DATA_ALLZEROS 0x00000000U 3532 3533 // Field: [7:0] TXFBRD_DATA 3534 // 3535 // ENUMs: 3536 // ALLONES All the bits are 1 3537 // ALLZEROS All the bits are 0 3538 #define LRFDPBE32_TXFBWR_TXFBRD_TXFBRD_DATA_W 8U 3539 #define LRFDPBE32_TXFBWR_TXFBRD_TXFBRD_DATA_M 0x000000FFU 3540 #define LRFDPBE32_TXFBWR_TXFBRD_TXFBRD_DATA_S 0U 3541 #define LRFDPBE32_TXFBWR_TXFBRD_TXFBRD_DATA_ALLONES 0x000000FFU 3542 #define LRFDPBE32_TXFBWR_TXFBRD_TXFBRD_DATA_ALLZEROS 0x00000000U 3543 3544 //***************************************************************************** 3545 // 3546 // Register: LRFDPBE32_O_RXFHWR_RXFHRD 3547 // 3548 //***************************************************************************** 3549 // Field: [31:16] RXFHWR_DATA 3550 // 3551 // ENUMs: 3552 // ALLONES All the bits are 1 3553 // ALLZEROS All the bits are 0 3554 #define LRFDPBE32_RXFHWR_RXFHRD_RXFHWR_DATA_W 16U 3555 #define LRFDPBE32_RXFHWR_RXFHRD_RXFHWR_DATA_M 0xFFFF0000U 3556 #define LRFDPBE32_RXFHWR_RXFHRD_RXFHWR_DATA_S 16U 3557 #define LRFDPBE32_RXFHWR_RXFHRD_RXFHWR_DATA_ALLONES 0xFFFF0000U 3558 #define LRFDPBE32_RXFHWR_RXFHRD_RXFHWR_DATA_ALLZEROS 0x00000000U 3559 3560 // Field: [15:0] RXFHRD_DATA 3561 // 3562 // ENUMs: 3563 // ALLONES All the bits are 1 3564 // ALLZEROS All the bits are 0 3565 #define LRFDPBE32_RXFHWR_RXFHRD_RXFHRD_DATA_W 16U 3566 #define LRFDPBE32_RXFHWR_RXFHRD_RXFHRD_DATA_M 0x0000FFFFU 3567 #define LRFDPBE32_RXFHWR_RXFHRD_RXFHRD_DATA_S 0U 3568 #define LRFDPBE32_RXFHWR_RXFHRD_RXFHRD_DATA_ALLONES 0x0000FFFFU 3569 #define LRFDPBE32_RXFHWR_RXFHRD_RXFHRD_DATA_ALLZEROS 0x00000000U 3570 3571 //***************************************************************************** 3572 // 3573 // Register: LRFDPBE32_O_TXFHWR_TXFHRD 3574 // 3575 //***************************************************************************** 3576 // Field: [31:16] TXFHWR_DATA 3577 // 3578 // ENUMs: 3579 // ALLONES All the bits are 1 3580 // ALLZEROS All the bits are 0 3581 #define LRFDPBE32_TXFHWR_TXFHRD_TXFHWR_DATA_W 16U 3582 #define LRFDPBE32_TXFHWR_TXFHRD_TXFHWR_DATA_M 0xFFFF0000U 3583 #define LRFDPBE32_TXFHWR_TXFHRD_TXFHWR_DATA_S 16U 3584 #define LRFDPBE32_TXFHWR_TXFHRD_TXFHWR_DATA_ALLONES 0xFFFF0000U 3585 #define LRFDPBE32_TXFHWR_TXFHRD_TXFHWR_DATA_ALLZEROS 0x00000000U 3586 3587 // Field: [15:0] TXFHRD_DATA 3588 // 3589 // ENUMs: 3590 // ALLONES All the bits are 1 3591 // ALLZEROS All the bits are 0 3592 #define LRFDPBE32_TXFHWR_TXFHRD_TXFHRD_DATA_W 16U 3593 #define LRFDPBE32_TXFHWR_TXFHRD_TXFHRD_DATA_M 0x0000FFFFU 3594 #define LRFDPBE32_TXFHWR_TXFHRD_TXFHRD_DATA_S 0U 3595 #define LRFDPBE32_TXFHWR_TXFHRD_TXFHRD_DATA_ALLONES 0x0000FFFFU 3596 #define LRFDPBE32_TXFHWR_TXFHRD_TXFHRD_DATA_ALLZEROS 0x00000000U 3597 3598 3599 #endif // __LRFDPBE32__ 3600
