1 /****************************************************************************** 2 * Filename: hw_lrfdmdm_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_LRFDMDM_H__ 34 #define __HW_LRFDMDM_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // LRFDMDM component 40 // 41 //***************************************************************************** 42 // Modem Enable Register 43 #define LRFDMDM_O_ENABLE 0x00000000U 44 45 // MCE program source select register 46 #define LRFDMDM_O_FWSRC 0x00000004U 47 48 // Modem Initialize Register 49 #define LRFDMDM_O_INIT 0x00000008U 50 51 // Demodulator Enable Register 0 52 #define LRFDMDM_O_DEMENABLE0 0x00000010U 53 54 // Demodulator Enable Register 1 55 #define LRFDMDM_O_DEMENABLE1 0x00000014U 56 57 // Demodulator Initialize Register 0 58 #define LRFDMDM_O_DEMINIT0 0x00000018U 59 60 // Demodulator Initialize Register 1 61 #define LRFDMDM_O_DEMINIT1 0x0000001CU 62 63 // Modem Command Engine (MCE) Strobe Register 0 64 #define LRFDMDM_O_STRB0 0x00000020U 65 66 // Modem Command Engine (MCE) Strobe Register 1 67 #define LRFDMDM_O_STRB1 0x00000024U 68 69 // MCE Event Flag Register 0 70 #define LRFDMDM_O_EVT0 0x00000028U 71 72 // MCE Event Flag Register 1 73 #define LRFDMDM_O_EVT1 0x0000002CU 74 75 // MCE Event Flag Register 2 76 #define LRFDMDM_O_EVT2 0x00000030U 77 78 // MCE Event Mask Register 0 79 #define LRFDMDM_O_EVTMSK0 0x00000038U 80 81 // MCE Event Mask Register 1 82 #define LRFDMDM_O_EVTMSK1 0x0000003CU 83 84 // MCE Event Mask Register 2 85 #define LRFDMDM_O_EVTMSK2 0x00000040U 86 87 // MCE Event Clear Register 0 88 #define LRFDMDM_O_EVTCLR0 0x00000048U 89 90 // MCE Event Clear Register 1 91 #define LRFDMDM_O_EVTCLR1 0x0000004CU 92 93 // MCE Event Clear Register 2 94 #define LRFDMDM_O_EVTCLR2 0x00000050U 95 96 // Modem Power Down Request Register 97 #define LRFDMDM_O_PDREQ 0x00000058U 98 99 // Modem API Command Register 100 #define LRFDMDM_O_API 0x0000005CU 101 102 // Modem API Command Parameter 0 103 #define LRFDMDM_O_CMDPAR0 0x00000060U 104 105 // Modem API Command Parameter 1 106 #define LRFDMDM_O_CMDPAR1 0x00000064U 107 108 // Modem API Command Parameter 2 109 #define LRFDMDM_O_CMDPAR2 0x00000068U 110 111 // Modem Command Status Register 112 #define LRFDMDM_O_MSGBOX 0x0000006CU 113 114 // Frequency Offset 115 #define LRFDMDM_O_FREQ 0x00000070U 116 117 // Modem FIFO Write Register 118 #define LRFDMDM_O_FIFOWR 0x00000074U 119 120 // Modem FIFO Read Register 121 #define LRFDMDM_O_FIFORD 0x00000078U 122 123 // Modem FIFO Write Configuration 124 #define LRFDMDM_O_FIFOWRCTRL 0x00000080U 125 126 // Modem FIFO Read Configuration 127 #define LRFDMDM_O_FIFORDCTRL 0x00000084U 128 129 // Modem FIFO Status Flags 130 #define LRFDMDM_O_FIFOSTA 0x0000008CU 131 132 // MCE-to-RFE Send Data Register 133 #define LRFDMDM_O_RFEDATOUT0 0x00000090U 134 135 // RFE-to-MCE Receive Data Register 136 #define LRFDMDM_O_RFEDATIN0 0x00000094U 137 138 // MCE-to-RFE Send Command Register 139 #define LRFDMDM_O_RFECMDOUT 0x00000098U 140 141 // RFE-to-MCE Receive Command Register 142 #define LRFDMDM_O_RFECMDIN 0x0000009CU 143 144 // MCE-to-PBE Send Data Register 145 #define LRFDMDM_O_PBEDATOUT0 0x000000A0U 146 147 // RFE-to-MCE Receive Data Register 148 #define LRFDMDM_O_PBEDATIN0 0x000000A4U 149 150 // MCE-to-PBE Send Command Register 151 #define LRFDMDM_O_PBECMDOUT 0x000000A8U 152 153 // PBE-to-MCE Receive Command Register 154 #define LRFDMDM_O_PBECMDIN 0x000000ACU 155 156 // Link quality indicator 157 #define LRFDMDM_O_LQIEST 0x000000B0U 158 159 // PBE event mux 160 #define LRFDMDM_O_PBEEVTMUX 0x000000B4U 161 162 // SYSTIME event mux 0 163 #define LRFDMDM_O_SYSTIMEVTMUX0 0x000000B8U 164 165 // SYSTIME event mux 1 166 #define LRFDMDM_O_SYSTIMEVTMUX1 0x000000BCU 167 168 // ADC Digital Interface Configuration 169 #define LRFDMDM_O_ADCDIGCONF 0x000000C0U 170 171 // Modulator Preamble Control 172 #define LRFDMDM_O_MODPRECTRL 0x000000C4U 173 174 // Modulator Symbol Mapping Register 0 175 #define LRFDMDM_O_MODSYMMAP0 0x000000C8U 176 177 // Modulator Symbol Mapping Register 1 178 #define LRFDMDM_O_MODSYMMAP1 0x000000CCU 179 180 // Modulator Soft Symbol Transmit 181 #define LRFDMDM_O_MODSOFTTX 0x000000D0U 182 183 // Modem Baud Rate Control 184 #define LRFDMDM_O_BAUD 0x000000D4U 185 186 // Modem Baud Rate Prescaler Control 187 #define LRFDMDM_O_BAUDPRE 0x000000D8U 188 189 // Modulator Main Config Register 190 #define LRFDMDM_O_MODMAIN 0x000000DCU 191 192 // Demodulator Config Register 0 193 #define LRFDMDM_O_DEMMISC0 0x000000E0U 194 195 // Demodulator Config Register 1 196 #define LRFDMDM_O_DEMMISC1 0x000000E4U 197 198 // Demodulator Config Register 2 199 #define LRFDMDM_O_DEMMISC2 0x000000E8U 200 201 // Demodulator Config Register 3 202 #define LRFDMDM_O_DEMMISC3 0x000000ECU 203 204 // Demodulator I/Q Mismatch Compensation Register 205 #define LRFDMDM_O_DEMIQMC0 0x000000F0U 206 207 // Dynamic Sample Buffer Config Register 208 #define LRFDMDM_O_DEMDSBU 0x000000F4U 209 210 // Demodulator Coarse DC Offset Estimator Register 0 211 #define LRFDMDM_O_DEMCODC0 0x000000F8U 212 213 // Demodulator Fine DC Offset Estimator Register 0 214 #define LRFDMDM_O_DEMFIDC0 0x000000FCU 215 216 // Demodulator Front-End Crossbar Register 0 217 #define LRFDMDM_O_DEMFEXB0 0x00000100U 218 219 // Demodulator Decode Stage Crossbar Register 0 220 #define LRFDMDM_O_DEMDSXB0 0x00000104U 221 222 // Demodulator Fine Frequency Offset Estimator Register 0 223 #define LRFDMDM_O_DEMFIFE0 0x00000108U 224 225 // Demodulator Matched Filter Register 0 226 #define LRFDMDM_O_DEMMAFI0 0x0000010CU 227 228 // Demodulator Matched Filter Register 1 229 #define LRFDMDM_O_DEMMAFI1 0x00000110U 230 231 // Demodulator Matched Filter Register 2 232 #define LRFDMDM_O_DEMMAFI2 0x00000114U 233 234 // Demodulator Correlator 1-bit Engine Register 0 235 #define LRFDMDM_O_DEMC1BE0 0x00000118U 236 237 // Demodulator Correlator 1-bit Engine Register 1 238 #define LRFDMDM_O_DEMC1BE1 0x0000011CU 239 240 // Demodulator Correlator 1-bit Engine Register 2 241 #define LRFDMDM_O_DEMC1BE2 0x00000120U 242 243 // Modem Spare 0 244 #define LRFDMDM_O_SPARE0 0x00000124U 245 246 // Modem Spare 1 247 #define LRFDMDM_O_SPARE1 0x00000128U 248 249 // Modem Spare 2 250 #define LRFDMDM_O_SPARE2 0x0000012CU 251 252 // Modem Spare 3 253 #define LRFDMDM_O_SPARE3 0x00000130U 254 255 // Demodulator Sync Word Qualifier Register 0 256 #define LRFDMDM_O_DEMSWQU0 0x00000134U 257 258 // Correlator reference register 0 259 #define LRFDMDM_O_DEMC1BEREF0 0x00000138U 260 261 // Correlator reference register 1 262 #define LRFDMDM_O_DEMC1BEREF1 0x0000013CU 263 264 // Correlator reference register 2 265 #define LRFDMDM_O_DEMC1BEREF2 0x00000140U 266 267 // Correlator reference register 3 268 #define LRFDMDM_O_DEMC1BEREF3 0x00000144U 269 270 // Dynamic Modem Control Signals from MCE 271 #define LRFDMDM_O_MODCTRL 0x00000148U 272 273 // Dynamic Modulator Preamble Register 274 #define LRFDMDM_O_MODPREAMBLE 0x0000014CU 275 276 // Demodulator Fractional Resampler Register 0 277 #define LRFDMDM_O_DEMFRAC0 0x00000150U 278 279 // Demodulator Fractional Resampler Register 1 280 #define LRFDMDM_O_DEMFRAC1 0x00000154U 281 282 // Demodulator Fractional Resampler Register 2 283 #define LRFDMDM_O_DEMFRAC2 0x00000158U 284 285 // Demodulator Fractional Resampler Register 3 286 #define LRFDMDM_O_DEMFRAC3 0x0000015CU 287 288 // Demodulator Coarse DC Offset Estimator Register 1 289 #define LRFDMDM_O_DEMCODC1 0x00000160U 290 291 // Demodulator Coarse DC Offset Estimator Register 2 292 #define LRFDMDM_O_DEMCODC2 0x00000164U 293 294 // Demodulator Fine DC Offset Estimator Register 1 295 #define LRFDMDM_O_DEMFIDC1 0x00000168U 296 297 // Demodulator Fine DC Offset Estimator Register 2 298 #define LRFDMDM_O_DEMFIDC2 0x0000016CU 299 300 // Demodulator Fine Frequency Offset Estimator Register 1 301 #define LRFDMDM_O_DEMFIFE1 0x00000170U 302 303 // Demodulator Manual Frequency Compensation Register 0 304 #define LRFDMDM_O_DEMMAFC0 0x00000174U 305 306 // Demodulator Matched Filter Register 4 307 #define LRFDMDM_O_DEMMAFI4 0x00000178U 308 309 // Demodulator Sync Word DC Imbalance Register 310 #define LRFDMDM_O_DEMSWIMBAL 0x0000017CU 311 312 // Demodulator Soft PDIFF Value Register 313 #define LRFDMDM_O_DEMSOFTPDIFF 0x00000180U 314 315 // Demodulator Debug Register 316 #define LRFDMDM_O_DEMDEBUG 0x00000184U 317 318 // Viterbi Control Register 319 #define LRFDMDM_O_VITCTRL 0x00000188U 320 321 // Viterbi Compute Register 322 #define LRFDMDM_O_VITCOMPUTE 0x0000018CU 323 324 // Viterbi APM Readback Register 325 #define LRFDMDM_O_VITAPMRDBACK 0x00000190U 326 327 // Viterbi State Register 328 #define LRFDMDM_O_VITSTATE 0x00000194U 329 330 // Viterbi Branch Metric 1 and 0 Register 331 #define LRFDMDM_O_VITBRMETRIC10 0x00000198U 332 333 // Viterbi Branch Metric 3 and 2 Register 334 #define LRFDMDM_O_VITBRMETRIC32 0x0000019CU 335 336 // Viterbi Branch Metric 5 and 4 Register 337 #define LRFDMDM_O_VITBRMETRIC54 0x000001A0U 338 339 // Viterbi Branch Metric 7 and 6 Register 340 #define LRFDMDM_O_VITBRMETRIC76 0x000001A4U 341 342 // Modem Timer and Counter Control Register 343 #define LRFDMDM_O_TIMCTL 0x000001E4U 344 345 // Modem Counter Increment Configuration 346 #define LRFDMDM_O_TIMINC 0x000001E8U 347 348 // Modem Timer/Counter Period Configuration 349 #define LRFDMDM_O_TIMPER 0x000001ECU 350 351 // Modem Counter Value 352 #define LRFDMDM_O_TIMCNT 0x000001F0U 353 354 // Modem Counter Capture Value 355 #define LRFDMDM_O_TIMCAPT 0x000001F4U 356 357 // Modem Timebase Control Register 358 #define LRFDMDM_O_TIMEBASE 0x000001F8U 359 360 // Local Count Ones Input Register 361 #define LRFDMDM_O_COUNT1IN 0x000001FCU 362 363 // Local Count Ones Result Register 364 #define LRFDMDM_O_COUNT1RES 0x00000200U 365 366 // Local Branch Metric Accelerator Module Register 1 367 #define LRFDMDM_O_BRMACC1 0x00000208U 368 369 // Local Branch Metric Accelerator Module Register 2 370 #define LRFDMDM_O_BRMACC2 0x0000020CU 371 372 // MCE Tracer Send Trigger Register 373 #define LRFDMDM_O_MCETRCCTRL 0x00000210U 374 375 // MCE Tracer Status Register 376 #define LRFDMDM_O_MCETRCSTAT 0x00000214U 377 378 // MCE Tracer Command Register 379 #define LRFDMDM_O_MCETRCCMD 0x00000218U 380 381 // MCE Tracer Command Parameter Register 0 382 #define LRFDMDM_O_MCETRCPAR0 0x0000021CU 383 384 // MCE Tracer Command Parameter Register 1 385 #define LRFDMDM_O_MCETRCPAR1 0x00000220U 386 387 // Modem Readback Capture Register 0 388 #define LRFDMDM_O_RDCAPT0 0x00000224U 389 390 // Modem Readback Capture Register 1 391 #define LRFDMDM_O_RDCAPT1 0x00000228U 392 393 // Frontend capture readback register 0 394 #define LRFDMDM_O_FECAPT0 0x0000022CU 395 396 // Frontend capture readback register 1 397 #define LRFDMDM_O_FECAPT1 0x00000230U 398 399 // Decoding stage capture register 0 400 #define LRFDMDM_O_DSCAPT0 0x00000234U 401 402 // Decoding stage capture register 1 403 #define LRFDMDM_O_DSCAPT1 0x00000238U 404 405 // Decoding stage capture register 2 406 #define LRFDMDM_O_DSCAPT2 0x0000023CU 407 408 // Decoding stage capture register 3 409 #define LRFDMDM_O_DSCAPT3 0x00000240U 410 411 // Demodulator sync word qualifier register 1 412 #define LRFDMDM_O_DEMSWQU1 0x00000244U 413 414 // Control of the MCE GPO signals 415 #define LRFDMDM_O_GPOCTRL0 0x00000248U 416 417 // Control of the MCE GPO signals 418 #define LRFDMDM_O_GPOCTRL1 0x0000024CU 419 420 // RFE received signal strength indicator 421 #define LRFDMDM_O_RFERSSI 0x00000250U 422 423 // RFE received signal strength indicator 424 #define LRFDMDM_O_RFEMAXRSSI 0x00000254U 425 426 // RFE front end gain setting 427 #define LRFDMDM_O_RFEDBGAIN 0x00000258U 428 429 // Modem Sync Word Register 0 430 #define LRFDMDM_O_SYNC0 0x0000025CU 431 432 // Modem Sync Word Register 1 433 #define LRFDMDM_O_SYNC1 0x00000260U 434 435 // Modem Sync Word Register 2 436 #define LRFDMDM_O_SYNC2 0x00000264U 437 438 // Modem Sync Word Register 3 439 #define LRFDMDM_O_SYNC3 0x00000268U 440 441 //***************************************************************************** 442 // 443 // Register: LRFDMDM_O_ENABLE 444 // 445 //***************************************************************************** 446 // Field: [5] ADCDIG 447 // 448 // Enables the ADC Digital interface 449 // ENUMs: 450 // EN Enable 451 // DIS Disable 452 #define LRFDMDM_ENABLE_ADCDIG 0x00000020U 453 #define LRFDMDM_ENABLE_ADCDIG_M 0x00000020U 454 #define LRFDMDM_ENABLE_ADCDIG_S 5U 455 #define LRFDMDM_ENABLE_ADCDIG_EN 0x00000020U 456 #define LRFDMDM_ENABLE_ADCDIG_DIS 0x00000000U 457 458 // Field: [4] DEMODULATOR 459 // 460 // Enables the Demodulator 461 // ENUMs: 462 // EN Enable 463 // DIS Disable 464 #define LRFDMDM_ENABLE_DEMODULATOR 0x00000010U 465 #define LRFDMDM_ENABLE_DEMODULATOR_M 0x00000010U 466 #define LRFDMDM_ENABLE_DEMODULATOR_S 4U 467 #define LRFDMDM_ENABLE_DEMODULATOR_EN 0x00000010U 468 #define LRFDMDM_ENABLE_DEMODULATOR_DIS 0x00000000U 469 470 // Field: [3] MODULATOR 471 // 472 // Enables the Modulator 473 // ENUMs: 474 // EN Enable 475 // DIS Disable 476 #define LRFDMDM_ENABLE_MODULATOR 0x00000008U 477 #define LRFDMDM_ENABLE_MODULATOR_M 0x00000008U 478 #define LRFDMDM_ENABLE_MODULATOR_S 3U 479 #define LRFDMDM_ENABLE_MODULATOR_EN 0x00000008U 480 #define LRFDMDM_ENABLE_MODULATOR_DIS 0x00000000U 481 482 // Field: [2] TIMEBASE 483 // 484 // Enables the Modem Timebase 485 // ENUMs: 486 // EN Enable 487 // DIS Disable 488 #define LRFDMDM_ENABLE_TIMEBASE 0x00000004U 489 #define LRFDMDM_ENABLE_TIMEBASE_M 0x00000004U 490 #define LRFDMDM_ENABLE_TIMEBASE_S 2U 491 #define LRFDMDM_ENABLE_TIMEBASE_EN 0x00000004U 492 #define LRFDMDM_ENABLE_TIMEBASE_DIS 0x00000000U 493 494 // Field: [1] TXRXFIFO 495 // 496 // Enables the TX/RX FIFO 497 // ENUMs: 498 // EN Enable 499 // DIS Disable 500 #define LRFDMDM_ENABLE_TXRXFIFO 0x00000002U 501 #define LRFDMDM_ENABLE_TXRXFIFO_M 0x00000002U 502 #define LRFDMDM_ENABLE_TXRXFIFO_S 1U 503 #define LRFDMDM_ENABLE_TXRXFIFO_EN 0x00000002U 504 #define LRFDMDM_ENABLE_TXRXFIFO_DIS 0x00000000U 505 506 // Field: [0] TOPSM 507 // 508 // Enables the TOPsm (MCE) 509 // ENUMs: 510 // EN Enable 511 // DIS Disable 512 #define LRFDMDM_ENABLE_TOPSM 0x00000001U 513 #define LRFDMDM_ENABLE_TOPSM_M 0x00000001U 514 #define LRFDMDM_ENABLE_TOPSM_S 0U 515 #define LRFDMDM_ENABLE_TOPSM_EN 0x00000001U 516 #define LRFDMDM_ENABLE_TOPSM_DIS 0x00000000U 517 518 //***************************************************************************** 519 // 520 // Register: LRFDMDM_O_FWSRC 521 // 522 //***************************************************************************** 523 // Field: [2] DATARAM 524 // 525 // Selects which RAM will be used for data storage 526 // ENUMs: 527 // S2RRAM Use S2RRAM for data 528 // MDMRAM Use MDMRAM for data 529 #define LRFDMDM_FWSRC_DATARAM 0x00000004U 530 #define LRFDMDM_FWSRC_DATARAM_M 0x00000004U 531 #define LRFDMDM_FWSRC_DATARAM_S 2U 532 #define LRFDMDM_FWSRC_DATARAM_S2RRAM 0x00000004U 533 #define LRFDMDM_FWSRC_DATARAM_MDMRAM 0x00000000U 534 535 // Field: [1] FWRAM 536 // 537 // Select which RAM we run FW from 538 // ENUMs: 539 // S2RRAM Run code from S2RRAM 540 // MDMRAM Run code from MDMRAM 541 #define LRFDMDM_FWSRC_FWRAM 0x00000002U 542 #define LRFDMDM_FWSRC_FWRAM_M 0x00000002U 543 #define LRFDMDM_FWSRC_FWRAM_S 1U 544 #define LRFDMDM_FWSRC_FWRAM_S2RRAM 0x00000002U 545 #define LRFDMDM_FWSRC_FWRAM_MDMRAM 0x00000000U 546 547 // Field: [0] BANK 548 // 549 // Sets the MSB of the address to the memory holding the program 550 // ENUMs: 551 // ONE Run code from bank 1 552 // ZERO Run code from bank 0 553 #define LRFDMDM_FWSRC_BANK 0x00000001U 554 #define LRFDMDM_FWSRC_BANK_M 0x00000001U 555 #define LRFDMDM_FWSRC_BANK_S 0U 556 #define LRFDMDM_FWSRC_BANK_ONE 0x00000001U 557 #define LRFDMDM_FWSRC_BANK_ZERO 0x00000000U 558 559 //***************************************************************************** 560 // 561 // Register: LRFDMDM_O_INIT 562 // 563 //***************************************************************************** 564 // Field: [5] ADCDIG 565 // 566 // Synch reset ADC Digital interface 567 // ENUMs: 568 // RESET Reset module 569 // NO_EFFECT No effect 570 #define LRFDMDM_INIT_ADCDIG 0x00000020U 571 #define LRFDMDM_INIT_ADCDIG_M 0x00000020U 572 #define LRFDMDM_INIT_ADCDIG_S 5U 573 #define LRFDMDM_INIT_ADCDIG_RESET 0x00000020U 574 #define LRFDMDM_INIT_ADCDIG_NO_EFFECT 0x00000000U 575 576 // Field: [4] DEMODULATOR 577 // 578 // Synch reset Demodulator 579 // ENUMs: 580 // RESET Reset module 581 // NO_EFFECT No effect 582 #define LRFDMDM_INIT_DEMODULATOR 0x00000010U 583 #define LRFDMDM_INIT_DEMODULATOR_M 0x00000010U 584 #define LRFDMDM_INIT_DEMODULATOR_S 4U 585 #define LRFDMDM_INIT_DEMODULATOR_RESET 0x00000010U 586 #define LRFDMDM_INIT_DEMODULATOR_NO_EFFECT 0x00000000U 587 588 // Field: [3] MODULATOR 589 // 590 // Synch reset Modulator 591 // ENUMs: 592 // RESET Reset module 593 // NO_EFFECT No effect 594 #define LRFDMDM_INIT_MODULATOR 0x00000008U 595 #define LRFDMDM_INIT_MODULATOR_M 0x00000008U 596 #define LRFDMDM_INIT_MODULATOR_S 3U 597 #define LRFDMDM_INIT_MODULATOR_RESET 0x00000008U 598 #define LRFDMDM_INIT_MODULATOR_NO_EFFECT 0x00000000U 599 600 // Field: [2] TIMEBASE 601 // 602 // Synch reset Modem Timebase 603 // ENUMs: 604 // RESET Reset module 605 // NO_EFFECT No effect 606 #define LRFDMDM_INIT_TIMEBASE 0x00000004U 607 #define LRFDMDM_INIT_TIMEBASE_M 0x00000004U 608 #define LRFDMDM_INIT_TIMEBASE_S 2U 609 #define LRFDMDM_INIT_TIMEBASE_RESET 0x00000004U 610 #define LRFDMDM_INIT_TIMEBASE_NO_EFFECT 0x00000000U 611 612 // Field: [1] TXRXFIFO 613 // 614 // Synch reset TX/RX FIFO 615 // ENUMs: 616 // RESET Reset module 617 // NO_EFFECT No effect 618 #define LRFDMDM_INIT_TXRXFIFO 0x00000002U 619 #define LRFDMDM_INIT_TXRXFIFO_M 0x00000002U 620 #define LRFDMDM_INIT_TXRXFIFO_S 1U 621 #define LRFDMDM_INIT_TXRXFIFO_RESET 0x00000002U 622 #define LRFDMDM_INIT_TXRXFIFO_NO_EFFECT 0x00000000U 623 624 // Field: [0] TOPSM 625 // 626 // Synch reset TOPsm (MCE) 627 // ENUMs: 628 // RESET Reset module 629 // NO_EFFECT No effect 630 #define LRFDMDM_INIT_TOPSM 0x00000001U 631 #define LRFDMDM_INIT_TOPSM_M 0x00000001U 632 #define LRFDMDM_INIT_TOPSM_S 0U 633 #define LRFDMDM_INIT_TOPSM_RESET 0x00000001U 634 #define LRFDMDM_INIT_TOPSM_NO_EFFECT 0x00000000U 635 636 //***************************************************************************** 637 // 638 // Register: LRFDMDM_O_DEMENABLE0 639 // 640 //***************************************************************************** 641 // Field: [8] FRAC 642 // 643 // Enables the fractional resampler 644 // ENUMs: 645 // EN Enable module 646 // DIS Disable 647 #define LRFDMDM_DEMENABLE0_FRAC 0x00000100U 648 #define LRFDMDM_DEMENABLE0_FRAC_M 0x00000100U 649 #define LRFDMDM_DEMENABLE0_FRAC_S 8U 650 #define LRFDMDM_DEMENABLE0_FRAC_EN 0x00000100U 651 #define LRFDMDM_DEMENABLE0_FRAC_DIS 0x00000000U 652 653 // Field: [7] FIDC 654 // 655 // Enables the fine DC estimator 656 // ENUMs: 657 // EN Enable module 658 // DIS Disable 659 #define LRFDMDM_DEMENABLE0_FIDC 0x00000080U 660 #define LRFDMDM_DEMENABLE0_FIDC_M 0x00000080U 661 #define LRFDMDM_DEMENABLE0_FIDC_S 7U 662 #define LRFDMDM_DEMENABLE0_FIDC_EN 0x00000080U 663 #define LRFDMDM_DEMENABLE0_FIDC_DIS 0x00000000U 664 665 // Field: [6] CHFI 666 // 667 // Enables the channel filter 668 // ENUMs: 669 // EN Enable module 670 // DIS Disable 671 #define LRFDMDM_DEMENABLE0_CHFI 0x00000040U 672 #define LRFDMDM_DEMENABLE0_CHFI_M 0x00000040U 673 #define LRFDMDM_DEMENABLE0_CHFI_S 6U 674 #define LRFDMDM_DEMENABLE0_CHFI_EN 0x00000040U 675 #define LRFDMDM_DEMENABLE0_CHFI_DIS 0x00000000U 676 677 // Field: [5] BDEC 678 // 679 // Enables the cascaded dec-by-2 stages (bde1 and bde2) 680 // ENUMs: 681 // EN Enable module 682 // DIS Disable 683 #define LRFDMDM_DEMENABLE0_BDEC 0x00000020U 684 #define LRFDMDM_DEMENABLE0_BDEC_M 0x00000020U 685 #define LRFDMDM_DEMENABLE0_BDEC_S 5U 686 #define LRFDMDM_DEMENABLE0_BDEC_EN 0x00000020U 687 #define LRFDMDM_DEMENABLE0_BDEC_DIS 0x00000000U 688 689 // Field: [4] IQMC 690 // 691 // Enables the IQ mismatch compensation 692 // ENUMs: 693 // EN Enable module 694 // DIS Disable 695 #define LRFDMDM_DEMENABLE0_IQMC 0x00000010U 696 #define LRFDMDM_DEMENABLE0_IQMC_M 0x00000010U 697 #define LRFDMDM_DEMENABLE0_IQMC_S 4U 698 #define LRFDMDM_DEMENABLE0_IQMC_EN 0x00000010U 699 #define LRFDMDM_DEMENABLE0_IQMC_DIS 0x00000000U 700 701 // Field: [3] MGE1 702 // 703 // Enables the magnitude estimator engine #1 704 // ENUMs: 705 // EN Enable module 706 // DIS Disable 707 #define LRFDMDM_DEMENABLE0_MGE1 0x00000008U 708 #define LRFDMDM_DEMENABLE0_MGE1_M 0x00000008U 709 #define LRFDMDM_DEMENABLE0_MGE1_S 3U 710 #define LRFDMDM_DEMENABLE0_MGE1_EN 0x00000008U 711 #define LRFDMDM_DEMENABLE0_MGE1_DIS 0x00000000U 712 713 // Field: [2] MGE0 714 // 715 // Enables the magnitude estimator engine #0 716 // ENUMs: 717 // EN Enable module 718 // DIS Disable 719 #define LRFDMDM_DEMENABLE0_MGE0 0x00000004U 720 #define LRFDMDM_DEMENABLE0_MGE0_M 0x00000004U 721 #define LRFDMDM_DEMENABLE0_MGE0_S 2U 722 #define LRFDMDM_DEMENABLE0_MGE0_EN 0x00000004U 723 #define LRFDMDM_DEMENABLE0_MGE0_DIS 0x00000000U 724 725 // Field: [1] CODC 726 // 727 // Enables the coarse DC estimator 728 // ENUMs: 729 // EN Enable module 730 // DIS Disable 731 #define LRFDMDM_DEMENABLE0_CODC 0x00000002U 732 #define LRFDMDM_DEMENABLE0_CODC_M 0x00000002U 733 #define LRFDMDM_DEMENABLE0_CODC_S 1U 734 #define LRFDMDM_DEMENABLE0_CODC_EN 0x00000002U 735 #define LRFDMDM_DEMENABLE0_CODC_DIS 0x00000000U 736 737 // Field: [0] CMIX 738 // 739 // Enables the N/1024 complex mixer 740 // ENUMs: 741 // EN Enable module 742 // DIS Disable 743 #define LRFDMDM_DEMENABLE0_CMIX 0x00000001U 744 #define LRFDMDM_DEMENABLE0_CMIX_M 0x00000001U 745 #define LRFDMDM_DEMENABLE0_CMIX_S 0U 746 #define LRFDMDM_DEMENABLE0_CMIX_EN 0x00000001U 747 #define LRFDMDM_DEMENABLE0_CMIX_DIS 0x00000000U 748 749 //***************************************************************************** 750 // 751 // Register: LRFDMDM_O_DEMENABLE1 752 // 753 //***************************************************************************** 754 // Field: [13] VITE 755 // 756 // Enables the Viterbi module 757 // ENUMs: 758 // EN Enable module 759 // DIS Disable 760 #define LRFDMDM_DEMENABLE1_VITE 0x00002000U 761 #define LRFDMDM_DEMENABLE1_VITE_M 0x00002000U 762 #define LRFDMDM_DEMENABLE1_VITE_S 13U 763 #define LRFDMDM_DEMENABLE1_VITE_EN 0x00002000U 764 #define LRFDMDM_DEMENABLE1_VITE_DIS 0x00000000U 765 766 // Field: [12] MLSE 767 // 768 // Enables the MLSE module 769 // ENUMs: 770 // EN Enable module 771 // DIS Disable 772 #define LRFDMDM_DEMENABLE1_MLSE 0x00001000U 773 #define LRFDMDM_DEMENABLE1_MLSE_M 0x00001000U 774 #define LRFDMDM_DEMENABLE1_MLSE_S 12U 775 #define LRFDMDM_DEMENABLE1_MLSE_EN 0x00001000U 776 #define LRFDMDM_DEMENABLE1_MLSE_DIS 0x00000000U 777 778 // Field: [11] SOFD 779 // 780 // Enables the soft decision module 781 // ENUMs: 782 // EN Enable module 783 // DIS Disable 784 #define LRFDMDM_DEMENABLE1_SOFD 0x00000800U 785 #define LRFDMDM_DEMENABLE1_SOFD_M 0x00000800U 786 #define LRFDMDM_DEMENABLE1_SOFD_S 11U 787 #define LRFDMDM_DEMENABLE1_SOFD_EN 0x00000800U 788 #define LRFDMDM_DEMENABLE1_SOFD_DIS 0x00000000U 789 790 // Field: [10] SWQU 791 // 792 // Enables the sync word qualifier 793 // ENUMs: 794 // EN Enable module 795 // DIS Disable 796 #define LRFDMDM_DEMENABLE1_SWQU 0x00000400U 797 #define LRFDMDM_DEMENABLE1_SWQU_M 0x00000400U 798 #define LRFDMDM_DEMENABLE1_SWQU_S 10U 799 #define LRFDMDM_DEMENABLE1_SWQU_EN 0x00000400U 800 #define LRFDMDM_DEMENABLE1_SWQU_DIS 0x00000000U 801 802 // Field: [9] MAFC 803 // 804 // Enables the manual frequency compensation module 805 // ENUMs: 806 // EN Enable module 807 // DIS Disable 808 #define LRFDMDM_DEMENABLE1_MAFC 0x00000200U 809 #define LRFDMDM_DEMENABLE1_MAFC_M 0x00000200U 810 #define LRFDMDM_DEMENABLE1_MAFC_S 9U 811 #define LRFDMDM_DEMENABLE1_MAFC_EN 0x00000200U 812 #define LRFDMDM_DEMENABLE1_MAFC_DIS 0x00000000U 813 814 // Field: [8] MAFI 815 // 816 // Enables the matched filter 817 // ENUMs: 818 // EN Enable module 819 // DIS Disable 820 #define LRFDMDM_DEMENABLE1_MAFI 0x00000100U 821 #define LRFDMDM_DEMENABLE1_MAFI_M 0x00000100U 822 #define LRFDMDM_DEMENABLE1_MAFI_S 8U 823 #define LRFDMDM_DEMENABLE1_MAFI_EN 0x00000100U 824 #define LRFDMDM_DEMENABLE1_MAFI_DIS 0x00000000U 825 826 // Field: [7] FIFE 827 // 828 // Enables the fine frequency offset estimator 829 // ENUMs: 830 // EN Enable module 831 // DIS Disable 832 #define LRFDMDM_DEMENABLE1_FIFE 0x00000080U 833 #define LRFDMDM_DEMENABLE1_FIFE_M 0x00000080U 834 #define LRFDMDM_DEMENABLE1_FIFE_S 7U 835 #define LRFDMDM_DEMENABLE1_FIFE_EN 0x00000080U 836 #define LRFDMDM_DEMENABLE1_FIFE_DIS 0x00000000U 837 838 // Field: [6] PDIF 839 // 840 // Enables the phase differentiation 841 // ENUMs: 842 // EN Enable module 843 // DIS Disable 844 #define LRFDMDM_DEMENABLE1_PDIF 0x00000040U 845 #define LRFDMDM_DEMENABLE1_PDIF_M 0x00000040U 846 #define LRFDMDM_DEMENABLE1_PDIF_S 6U 847 #define LRFDMDM_DEMENABLE1_PDIF_EN 0x00000040U 848 #define LRFDMDM_DEMENABLE1_PDIF_DIS 0x00000000U 849 850 // Field: [5] CA2P 851 // 852 // Enables the cart 2 polar conversion 853 // ENUMs: 854 // EN Enable module 855 // DIS Disable 856 #define LRFDMDM_DEMENABLE1_CA2P 0x00000020U 857 #define LRFDMDM_DEMENABLE1_CA2P_M 0x00000020U 858 #define LRFDMDM_DEMENABLE1_CA2P_S 5U 859 #define LRFDMDM_DEMENABLE1_CA2P_EN 0x00000020U 860 #define LRFDMDM_DEMENABLE1_CA2P_DIS 0x00000000U 861 862 // Field: [4] C1BE 863 // 864 // Enables the correlation 1-bit engine 865 // ENUMs: 866 // EN Enable module 867 // DIS Disable 868 #define LRFDMDM_DEMENABLE1_C1BE 0x00000010U 869 #define LRFDMDM_DEMENABLE1_C1BE_M 0x00000010U 870 #define LRFDMDM_DEMENABLE1_C1BE_S 4U 871 #define LRFDMDM_DEMENABLE1_C1BE_EN 0x00000010U 872 #define LRFDMDM_DEMENABLE1_C1BE_DIS 0x00000000U 873 874 // Field: [3] LQIE 875 // 876 // Enables the LQI engine 877 // ENUMs: 878 // EN Enable module 879 // DIS Disable 880 #define LRFDMDM_DEMENABLE1_LQIE 0x00000008U 881 #define LRFDMDM_DEMENABLE1_LQIE_M 0x00000008U 882 #define LRFDMDM_DEMENABLE1_LQIE_S 3U 883 #define LRFDMDM_DEMENABLE1_LQIE_EN 0x00000008U 884 #define LRFDMDM_DEMENABLE1_LQIE_DIS 0x00000000U 885 886 // Field: [2] F4BA 887 // 888 // Enables the clock-domain crossing fifo 889 // ENUMs: 890 // EN Enable module 891 // DIS Disable 892 #define LRFDMDM_DEMENABLE1_F4BA 0x00000004U 893 #define LRFDMDM_DEMENABLE1_F4BA_M 0x00000004U 894 #define LRFDMDM_DEMENABLE1_F4BA_S 2U 895 #define LRFDMDM_DEMENABLE1_F4BA_EN 0x00000004U 896 #define LRFDMDM_DEMENABLE1_F4BA_DIS 0x00000000U 897 898 // Field: [1] STIM 899 // 900 // Enables the symbol timing tracker 901 // ENUMs: 902 // EN Enable module 903 // DIS Disable 904 #define LRFDMDM_DEMENABLE1_STIM 0x00000002U 905 #define LRFDMDM_DEMENABLE1_STIM_M 0x00000002U 906 #define LRFDMDM_DEMENABLE1_STIM_S 1U 907 #define LRFDMDM_DEMENABLE1_STIM_EN 0x00000002U 908 #define LRFDMDM_DEMENABLE1_STIM_DIS 0x00000000U 909 910 // Field: [0] DSBU 911 // 912 // Enables the dynamic sample buffer 913 // ENUMs: 914 // EN Enable module 915 // DIS Disable 916 #define LRFDMDM_DEMENABLE1_DSBU 0x00000001U 917 #define LRFDMDM_DEMENABLE1_DSBU_M 0x00000001U 918 #define LRFDMDM_DEMENABLE1_DSBU_S 0U 919 #define LRFDMDM_DEMENABLE1_DSBU_EN 0x00000001U 920 #define LRFDMDM_DEMENABLE1_DSBU_DIS 0x00000000U 921 922 //***************************************************************************** 923 // 924 // Register: LRFDMDM_O_DEMINIT0 925 // 926 //***************************************************************************** 927 // Field: [8] FRAC 928 // 929 // Synch reset fractional resampler 930 // ENUMs: 931 // RESET Reset module 932 // NO_EFFECT No effect 933 #define LRFDMDM_DEMINIT0_FRAC 0x00000100U 934 #define LRFDMDM_DEMINIT0_FRAC_M 0x00000100U 935 #define LRFDMDM_DEMINIT0_FRAC_S 8U 936 #define LRFDMDM_DEMINIT0_FRAC_RESET 0x00000100U 937 #define LRFDMDM_DEMINIT0_FRAC_NO_EFFECT 0x00000000U 938 939 // Field: [7] FIDC 940 // 941 // Synch reset fine DC estimator 942 // ENUMs: 943 // RESET Reset module 944 // NO_EFFECT No effect 945 #define LRFDMDM_DEMINIT0_FIDC 0x00000080U 946 #define LRFDMDM_DEMINIT0_FIDC_M 0x00000080U 947 #define LRFDMDM_DEMINIT0_FIDC_S 7U 948 #define LRFDMDM_DEMINIT0_FIDC_RESET 0x00000080U 949 #define LRFDMDM_DEMINIT0_FIDC_NO_EFFECT 0x00000000U 950 951 // Field: [6] CHFI 952 // 953 // Synch reset channel filter 954 // ENUMs: 955 // RESET Reset module 956 // NO_EFFECT No effect 957 #define LRFDMDM_DEMINIT0_CHFI 0x00000040U 958 #define LRFDMDM_DEMINIT0_CHFI_M 0x00000040U 959 #define LRFDMDM_DEMINIT0_CHFI_S 6U 960 #define LRFDMDM_DEMINIT0_CHFI_RESET 0x00000040U 961 #define LRFDMDM_DEMINIT0_CHFI_NO_EFFECT 0x00000000U 962 963 // Field: [5] BDEC 964 // 965 // Synch reset cascaded dec-by-2 stages (bde1 and bde2) 966 // ENUMs: 967 // RESET Reset module 968 // NO_EFFECT No effect 969 #define LRFDMDM_DEMINIT0_BDEC 0x00000020U 970 #define LRFDMDM_DEMINIT0_BDEC_M 0x00000020U 971 #define LRFDMDM_DEMINIT0_BDEC_S 5U 972 #define LRFDMDM_DEMINIT0_BDEC_RESET 0x00000020U 973 #define LRFDMDM_DEMINIT0_BDEC_NO_EFFECT 0x00000000U 974 975 // Field: [4] IQMC 976 // 977 // Synch reset IQ mismatch compensation 978 // ENUMs: 979 // RESET Reset module 980 // NO_EFFECT No effect 981 #define LRFDMDM_DEMINIT0_IQMC 0x00000010U 982 #define LRFDMDM_DEMINIT0_IQMC_M 0x00000010U 983 #define LRFDMDM_DEMINIT0_IQMC_S 4U 984 #define LRFDMDM_DEMINIT0_IQMC_RESET 0x00000010U 985 #define LRFDMDM_DEMINIT0_IQMC_NO_EFFECT 0x00000000U 986 987 // Field: [3] MGE1 988 // 989 // Synch reset magnitude estimator engine #1 990 // ENUMs: 991 // RESET Reset module 992 // NO_EFFECT No effect 993 #define LRFDMDM_DEMINIT0_MGE1 0x00000008U 994 #define LRFDMDM_DEMINIT0_MGE1_M 0x00000008U 995 #define LRFDMDM_DEMINIT0_MGE1_S 3U 996 #define LRFDMDM_DEMINIT0_MGE1_RESET 0x00000008U 997 #define LRFDMDM_DEMINIT0_MGE1_NO_EFFECT 0x00000000U 998 999 // Field: [2] MGE0 1000 // 1001 // Synch reset magnitude estimator engine #0 1002 // ENUMs: 1003 // RESET Reset module 1004 // NO_EFFECT No effect 1005 #define LRFDMDM_DEMINIT0_MGE0 0x00000004U 1006 #define LRFDMDM_DEMINIT0_MGE0_M 0x00000004U 1007 #define LRFDMDM_DEMINIT0_MGE0_S 2U 1008 #define LRFDMDM_DEMINIT0_MGE0_RESET 0x00000004U 1009 #define LRFDMDM_DEMINIT0_MGE0_NO_EFFECT 0x00000000U 1010 1011 // Field: [1] CODC 1012 // 1013 // Synch reset coarse DC estimator 1014 // ENUMs: 1015 // RESET Reset module 1016 // NO_EFFECT No effect 1017 #define LRFDMDM_DEMINIT0_CODC 0x00000002U 1018 #define LRFDMDM_DEMINIT0_CODC_M 0x00000002U 1019 #define LRFDMDM_DEMINIT0_CODC_S 1U 1020 #define LRFDMDM_DEMINIT0_CODC_RESET 0x00000002U 1021 #define LRFDMDM_DEMINIT0_CODC_NO_EFFECT 0x00000000U 1022 1023 // Field: [0] CMIX 1024 // 1025 // Synch reset N/1024 complex mixer 1026 // ENUMs: 1027 // RESET Reset module 1028 // NO_EFFECT No effect 1029 #define LRFDMDM_DEMINIT0_CMIX 0x00000001U 1030 #define LRFDMDM_DEMINIT0_CMIX_M 0x00000001U 1031 #define LRFDMDM_DEMINIT0_CMIX_S 0U 1032 #define LRFDMDM_DEMINIT0_CMIX_RESET 0x00000001U 1033 #define LRFDMDM_DEMINIT0_CMIX_NO_EFFECT 0x00000000U 1034 1035 //***************************************************************************** 1036 // 1037 // Register: LRFDMDM_O_DEMINIT1 1038 // 1039 //***************************************************************************** 1040 // Field: [13] VITE 1041 // 1042 // Synch reset Viterbi Module 1043 // ENUMs: 1044 // RESET Reset module 1045 // NO_EFFECT No effect 1046 #define LRFDMDM_DEMINIT1_VITE 0x00002000U 1047 #define LRFDMDM_DEMINIT1_VITE_M 0x00002000U 1048 #define LRFDMDM_DEMINIT1_VITE_S 13U 1049 #define LRFDMDM_DEMINIT1_VITE_RESET 0x00002000U 1050 #define LRFDMDM_DEMINIT1_VITE_NO_EFFECT 0x00000000U 1051 1052 // Field: [12] MLSE 1053 // 1054 // Synch reset MLSE module 1055 // ENUMs: 1056 // RESET Reset module 1057 // NO_EFFECT No effect 1058 #define LRFDMDM_DEMINIT1_MLSE 0x00001000U 1059 #define LRFDMDM_DEMINIT1_MLSE_M 0x00001000U 1060 #define LRFDMDM_DEMINIT1_MLSE_S 12U 1061 #define LRFDMDM_DEMINIT1_MLSE_RESET 0x00001000U 1062 #define LRFDMDM_DEMINIT1_MLSE_NO_EFFECT 0x00000000U 1063 1064 // Field: [11] SOFD 1065 // 1066 // Synch reset soft decision module 1067 // ENUMs: 1068 // RESET Reset module 1069 // NO_EFFECT No effect 1070 #define LRFDMDM_DEMINIT1_SOFD 0x00000800U 1071 #define LRFDMDM_DEMINIT1_SOFD_M 0x00000800U 1072 #define LRFDMDM_DEMINIT1_SOFD_S 11U 1073 #define LRFDMDM_DEMINIT1_SOFD_RESET 0x00000800U 1074 #define LRFDMDM_DEMINIT1_SOFD_NO_EFFECT 0x00000000U 1075 1076 // Field: [10] SWQU 1077 // 1078 // Synch reset sync word qualifyer 1079 // ENUMs: 1080 // RESET Reset module 1081 // NO_EFFECT No effect 1082 #define LRFDMDM_DEMINIT1_SWQU 0x00000400U 1083 #define LRFDMDM_DEMINIT1_SWQU_M 0x00000400U 1084 #define LRFDMDM_DEMINIT1_SWQU_S 10U 1085 #define LRFDMDM_DEMINIT1_SWQU_RESET 0x00000400U 1086 #define LRFDMDM_DEMINIT1_SWQU_NO_EFFECT 0x00000000U 1087 1088 // Field: [9] MAFC 1089 // 1090 // Synch reset manual frequency compensation module 1091 // ENUMs: 1092 // RESET Reset module 1093 // NO_EFFECT No effect 1094 #define LRFDMDM_DEMINIT1_MAFC 0x00000200U 1095 #define LRFDMDM_DEMINIT1_MAFC_M 0x00000200U 1096 #define LRFDMDM_DEMINIT1_MAFC_S 9U 1097 #define LRFDMDM_DEMINIT1_MAFC_RESET 0x00000200U 1098 #define LRFDMDM_DEMINIT1_MAFC_NO_EFFECT 0x00000000U 1099 1100 // Field: [8] MAFI 1101 // 1102 // Synch reset matched filter 1103 // ENUMs: 1104 // RESET Reset module 1105 // NO_EFFECT No effect 1106 #define LRFDMDM_DEMINIT1_MAFI 0x00000100U 1107 #define LRFDMDM_DEMINIT1_MAFI_M 0x00000100U 1108 #define LRFDMDM_DEMINIT1_MAFI_S 8U 1109 #define LRFDMDM_DEMINIT1_MAFI_RESET 0x00000100U 1110 #define LRFDMDM_DEMINIT1_MAFI_NO_EFFECT 0x00000000U 1111 1112 // Field: [7] FIFE 1113 // 1114 // Synch reset fine frequency offset estimator 1115 // ENUMs: 1116 // RESET Reset module 1117 // NO_EFFECT No effect 1118 #define LRFDMDM_DEMINIT1_FIFE 0x00000080U 1119 #define LRFDMDM_DEMINIT1_FIFE_M 0x00000080U 1120 #define LRFDMDM_DEMINIT1_FIFE_S 7U 1121 #define LRFDMDM_DEMINIT1_FIFE_RESET 0x00000080U 1122 #define LRFDMDM_DEMINIT1_FIFE_NO_EFFECT 0x00000000U 1123 1124 // Field: [6] PDIF 1125 // 1126 // Synch reset phase differentiation 1127 // ENUMs: 1128 // RESET Reset module 1129 // NO_EFFECT No effect 1130 #define LRFDMDM_DEMINIT1_PDIF 0x00000040U 1131 #define LRFDMDM_DEMINIT1_PDIF_M 0x00000040U 1132 #define LRFDMDM_DEMINIT1_PDIF_S 6U 1133 #define LRFDMDM_DEMINIT1_PDIF_RESET 0x00000040U 1134 #define LRFDMDM_DEMINIT1_PDIF_NO_EFFECT 0x00000000U 1135 1136 // Field: [5] CA2P 1137 // 1138 // Synch reset cart 2 polar conversion 1139 // ENUMs: 1140 // RESET Reset module 1141 // NO_EFFECT No effect 1142 #define LRFDMDM_DEMINIT1_CA2P 0x00000020U 1143 #define LRFDMDM_DEMINIT1_CA2P_M 0x00000020U 1144 #define LRFDMDM_DEMINIT1_CA2P_S 5U 1145 #define LRFDMDM_DEMINIT1_CA2P_RESET 0x00000020U 1146 #define LRFDMDM_DEMINIT1_CA2P_NO_EFFECT 0x00000000U 1147 1148 // Field: [4] C1BE 1149 // 1150 // Synch reset correlation 1-bit engine 1151 // ENUMs: 1152 // RESET Reset module 1153 // NO_EFFECT No effect 1154 #define LRFDMDM_DEMINIT1_C1BE 0x00000010U 1155 #define LRFDMDM_DEMINIT1_C1BE_M 0x00000010U 1156 #define LRFDMDM_DEMINIT1_C1BE_S 4U 1157 #define LRFDMDM_DEMINIT1_C1BE_RESET 0x00000010U 1158 #define LRFDMDM_DEMINIT1_C1BE_NO_EFFECT 0x00000000U 1159 1160 // Field: [3] LQIE 1161 // 1162 // Synch reset LQI engine 1163 // ENUMs: 1164 // RESET Reset module 1165 // NO_EFFECT No effect 1166 #define LRFDMDM_DEMINIT1_LQIE 0x00000008U 1167 #define LRFDMDM_DEMINIT1_LQIE_M 0x00000008U 1168 #define LRFDMDM_DEMINIT1_LQIE_S 3U 1169 #define LRFDMDM_DEMINIT1_LQIE_RESET 0x00000008U 1170 #define LRFDMDM_DEMINIT1_LQIE_NO_EFFECT 0x00000000U 1171 1172 // Field: [2] F4BA 1173 // 1174 // Synch reset clock-domain crossing fifo 1175 // ENUMs: 1176 // RESET Reset module 1177 // NO_EFFECT No effect 1178 #define LRFDMDM_DEMINIT1_F4BA 0x00000004U 1179 #define LRFDMDM_DEMINIT1_F4BA_M 0x00000004U 1180 #define LRFDMDM_DEMINIT1_F4BA_S 2U 1181 #define LRFDMDM_DEMINIT1_F4BA_RESET 0x00000004U 1182 #define LRFDMDM_DEMINIT1_F4BA_NO_EFFECT 0x00000000U 1183 1184 // Field: [1] STIM 1185 // 1186 // Synch reset symbol timing tracker 1187 // ENUMs: 1188 // RESET Reset module 1189 // NO_EFFECT No effect 1190 #define LRFDMDM_DEMINIT1_STIM 0x00000002U 1191 #define LRFDMDM_DEMINIT1_STIM_M 0x00000002U 1192 #define LRFDMDM_DEMINIT1_STIM_S 1U 1193 #define LRFDMDM_DEMINIT1_STIM_RESET 0x00000002U 1194 #define LRFDMDM_DEMINIT1_STIM_NO_EFFECT 0x00000000U 1195 1196 // Field: [0] DSBU 1197 // 1198 // Synch reset dynamic sample buffer 1199 // ENUMs: 1200 // RESET Reset module 1201 // NO_EFFECT No effect 1202 #define LRFDMDM_DEMINIT1_DSBU 0x00000001U 1203 #define LRFDMDM_DEMINIT1_DSBU_M 0x00000001U 1204 #define LRFDMDM_DEMINIT1_DSBU_S 0U 1205 #define LRFDMDM_DEMINIT1_DSBU_RESET 0x00000001U 1206 #define LRFDMDM_DEMINIT1_DSBU_NO_EFFECT 0x00000000U 1207 1208 //***************************************************************************** 1209 // 1210 // Register: LRFDMDM_O_STRB0 1211 // 1212 //***************************************************************************** 1213 // Field: [11] TIMBADVANCE 1214 // 1215 // Advance the timebase one 4baud sample, so the current symbol will have three 1216 // 4baud samples. 1217 // ENUMs: 1218 // ON The bit is 1 1219 // NO_EFFECT The bit is 0 1220 #define LRFDMDM_STRB0_TIMBADVANCE 0x00000800U 1221 #define LRFDMDM_STRB0_TIMBADVANCE_M 0x00000800U 1222 #define LRFDMDM_STRB0_TIMBADVANCE_S 11U 1223 #define LRFDMDM_STRB0_TIMBADVANCE_ON 0x00000800U 1224 #define LRFDMDM_STRB0_TIMBADVANCE_NO_EFFECT 0x00000000U 1225 1226 // Field: [10] TIMBSTALL 1227 // 1228 // Stall the timebase one 4baud sample, so the current symbol will have five 1229 // 4baud samples. 1230 // ENUMs: 1231 // ON The bit is 1 1232 // NO_EFFECT The bit is 0 1233 #define LRFDMDM_STRB0_TIMBSTALL 0x00000400U 1234 #define LRFDMDM_STRB0_TIMBSTALL_M 0x00000400U 1235 #define LRFDMDM_STRB0_TIMBSTALL_S 10U 1236 #define LRFDMDM_STRB0_TIMBSTALL_ON 0x00000400U 1237 #define LRFDMDM_STRB0_TIMBSTALL_NO_EFFECT 0x00000000U 1238 1239 // Field: [9] EVT5 1240 // 1241 // Firmware defined 1242 // ENUMs: 1243 // ONE The bit is 1 1244 // ZERO The bit is 0 1245 #define LRFDMDM_STRB0_EVT5 0x00000200U 1246 #define LRFDMDM_STRB0_EVT5_M 0x00000200U 1247 #define LRFDMDM_STRB0_EVT5_S 9U 1248 #define LRFDMDM_STRB0_EVT5_ONE 0x00000200U 1249 #define LRFDMDM_STRB0_EVT5_ZERO 0x00000000U 1250 1251 // Field: [8] EVT4 1252 // 1253 // Firmware defined 1254 // ENUMs: 1255 // ONE The bit is 1 1256 // ZERO The bit is 0 1257 #define LRFDMDM_STRB0_EVT4 0x00000100U 1258 #define LRFDMDM_STRB0_EVT4_M 0x00000100U 1259 #define LRFDMDM_STRB0_EVT4_S 8U 1260 #define LRFDMDM_STRB0_EVT4_ONE 0x00000100U 1261 #define LRFDMDM_STRB0_EVT4_ZERO 0x00000000U 1262 1263 // Field: [7] MLSETERM 1264 // 1265 // Terminate MLSE unit 1266 // ENUMs: 1267 // ON The bit is 1 1268 // OFF The bit is 0 1269 #define LRFDMDM_STRB0_MLSETERM 0x00000080U 1270 #define LRFDMDM_STRB0_MLSETERM_M 0x00000080U 1271 #define LRFDMDM_STRB0_MLSETERM_S 7U 1272 #define LRFDMDM_STRB0_MLSETERM_ON 0x00000080U 1273 #define LRFDMDM_STRB0_MLSETERM_OFF 0x00000000U 1274 1275 // Field: [6] EVT3 1276 // 1277 // Firmware defined 1278 // ENUMs: 1279 // ONE The bit is 1 1280 // ZERO The bit is 0 1281 #define LRFDMDM_STRB0_EVT3 0x00000040U 1282 #define LRFDMDM_STRB0_EVT3_M 0x00000040U 1283 #define LRFDMDM_STRB0_EVT3_S 6U 1284 #define LRFDMDM_STRB0_EVT3_ONE 0x00000040U 1285 #define LRFDMDM_STRB0_EVT3_ZERO 0x00000000U 1286 1287 // Field: [5] EVT2 1288 // 1289 // Firmware defined SYSTIMER event 2 1290 // ENUMs: 1291 // ONE The bit is 1 1292 // ZERO The bit is 0 1293 #define LRFDMDM_STRB0_EVT2 0x00000020U 1294 #define LRFDMDM_STRB0_EVT2_M 0x00000020U 1295 #define LRFDMDM_STRB0_EVT2_S 5U 1296 #define LRFDMDM_STRB0_EVT2_ONE 0x00000020U 1297 #define LRFDMDM_STRB0_EVT2_ZERO 0x00000000U 1298 1299 // Field: [4] EVT1 1300 // 1301 // Firmware defined SYSTIMER event 1 1302 // ENUMs: 1303 // ONE The bit is 1 1304 // ZERO The bit is 0 1305 #define LRFDMDM_STRB0_EVT1 0x00000010U 1306 #define LRFDMDM_STRB0_EVT1_M 0x00000010U 1307 #define LRFDMDM_STRB0_EVT1_S 4U 1308 #define LRFDMDM_STRB0_EVT1_ONE 0x00000010U 1309 #define LRFDMDM_STRB0_EVT1_ZERO 0x00000000U 1310 1311 // Field: [3] EVT0 1312 // 1313 // Firmware defined SYSTIMER event 0 1314 // ENUMs: 1315 // ONE The bit is 1 1316 // ZERO The bit is 0 1317 #define LRFDMDM_STRB0_EVT0 0x00000008U 1318 #define LRFDMDM_STRB0_EVT0_M 0x00000008U 1319 #define LRFDMDM_STRB0_EVT0_S 3U 1320 #define LRFDMDM_STRB0_EVT0_ONE 0x00000008U 1321 #define LRFDMDM_STRB0_EVT0_ZERO 0x00000000U 1322 1323 // Field: [2] TIMBALIGN 1324 // 1325 // Align the 1baud to the next 4baud event 1326 // ENUMs: 1327 // ON The bit is 1 1328 // NO_EFFECT The bit is 0 1329 #define LRFDMDM_STRB0_TIMBALIGN 0x00000004U 1330 #define LRFDMDM_STRB0_TIMBALIGN_M 0x00000004U 1331 #define LRFDMDM_STRB0_TIMBALIGN_S 2U 1332 #define LRFDMDM_STRB0_TIMBALIGN_ON 0x00000004U 1333 #define LRFDMDM_STRB0_TIMBALIGN_NO_EFFECT 0x00000000U 1334 1335 // Field: [1] DSBURST 1336 // 1337 // Restart DSBU 1338 // ENUMs: 1339 // RESTART Restart module 1340 // NO_EFFECT No effect 1341 #define LRFDMDM_STRB0_DSBURST 0x00000002U 1342 #define LRFDMDM_STRB0_DSBURST_M 0x00000002U 1343 #define LRFDMDM_STRB0_DSBURST_S 1U 1344 #define LRFDMDM_STRB0_DSBURST_RESTART 0x00000002U 1345 #define LRFDMDM_STRB0_DSBURST_NO_EFFECT 0x00000000U 1346 1347 // Field: [0] CMDDONE 1348 // 1349 // Signal command done to CPE 1350 // ENUMs: 1351 // YES The bit is 1 1352 // NO The bit is 0 1353 #define LRFDMDM_STRB0_CMDDONE 0x00000001U 1354 #define LRFDMDM_STRB0_CMDDONE_M 0x00000001U 1355 #define LRFDMDM_STRB0_CMDDONE_S 0U 1356 #define LRFDMDM_STRB0_CMDDONE_YES 0x00000001U 1357 #define LRFDMDM_STRB0_CMDDONE_NO 0x00000000U 1358 1359 //***************************************************************************** 1360 // 1361 // Register: LRFDMDM_O_STRB1 1362 // 1363 //***************************************************************************** 1364 // Field: [13] S2RTRG 1365 // 1366 // Arm/Trigger the S2R module 1367 // ENUMs: 1368 // ONE The bit is 1 1369 // ZERO The bit is 0 1370 #define LRFDMDM_STRB1_S2RTRG 0x00002000U 1371 #define LRFDMDM_STRB1_S2RTRG_M 0x00002000U 1372 #define LRFDMDM_STRB1_S2RTRG_S 13U 1373 #define LRFDMDM_STRB1_S2RTRG_ONE 0x00002000U 1374 #define LRFDMDM_STRB1_S2RTRG_ZERO 0x00000000U 1375 1376 // Field: [12] DMATRG 1377 // 1378 // FW triggered DMA transfer 1379 // ENUMs: 1380 // ONE The bit is 1 1381 // ZERO The bit is 0 1382 #define LRFDMDM_STRB1_DMATRG 0x00001000U 1383 #define LRFDMDM_STRB1_DMATRG_M 0x00001000U 1384 #define LRFDMDM_STRB1_DMATRG_S 12U 1385 #define LRFDMDM_STRB1_DMATRG_ONE 0x00001000U 1386 #define LRFDMDM_STRB1_DMATRG_ZERO 0x00000000U 1387 1388 // Field: [11] SYSTCAPT2 1389 // 1390 // Systimer capture event 2 1391 // ENUMs: 1392 // ONE The bit is 1 1393 // ZERO The bit is 0 1394 #define LRFDMDM_STRB1_SYSTCAPT2 0x00000800U 1395 #define LRFDMDM_STRB1_SYSTCAPT2_M 0x00000800U 1396 #define LRFDMDM_STRB1_SYSTCAPT2_S 11U 1397 #define LRFDMDM_STRB1_SYSTCAPT2_ONE 0x00000800U 1398 #define LRFDMDM_STRB1_SYSTCAPT2_ZERO 0x00000000U 1399 1400 // Field: [10] SYSTCAPT1 1401 // 1402 // Systimer capture event 1 1403 // ENUMs: 1404 // ONE The bit is 1 1405 // ZERO The bit is 0 1406 #define LRFDMDM_STRB1_SYSTCAPT1 0x00000400U 1407 #define LRFDMDM_STRB1_SYSTCAPT1_M 0x00000400U 1408 #define LRFDMDM_STRB1_SYSTCAPT1_S 10U 1409 #define LRFDMDM_STRB1_SYSTCAPT1_ONE 0x00000400U 1410 #define LRFDMDM_STRB1_SYSTCAPT1_ZERO 0x00000000U 1411 1412 // Field: [9] SYSTCAPT0 1413 // 1414 // Systimer capture event 0 1415 // ENUMs: 1416 // ONE The bit is 1 1417 // ZERO The bit is 0 1418 #define LRFDMDM_STRB1_SYSTCAPT0 0x00000200U 1419 #define LRFDMDM_STRB1_SYSTCAPT0_M 0x00000200U 1420 #define LRFDMDM_STRB1_SYSTCAPT0_S 9U 1421 #define LRFDMDM_STRB1_SYSTCAPT0_ONE 0x00000200U 1422 #define LRFDMDM_STRB1_SYSTCAPT0_ZERO 0x00000000U 1423 1424 // Field: [8] C1BEPEAKAB 1425 // 1426 // Restart C1BE peak A and B search 1427 // ENUMs: 1428 // ONE The bit is 1 1429 // ZERO The bit is 0 1430 #define LRFDMDM_STRB1_C1BEPEAKAB 0x00000100U 1431 #define LRFDMDM_STRB1_C1BEPEAKAB_M 0x00000100U 1432 #define LRFDMDM_STRB1_C1BEPEAKAB_S 8U 1433 #define LRFDMDM_STRB1_C1BEPEAKAB_ONE 0x00000100U 1434 #define LRFDMDM_STRB1_C1BEPEAKAB_ZERO 0x00000000U 1435 1436 // Field: [7] C1BEPEAKC 1437 // 1438 // Restart C1BE peak C search (corr C is corr A+B combined = 64 symbols = 256 1439 // samples) 1440 // ENUMs: 1441 // ONE The bit is 1 1442 // ZERO The bit is 0 1443 #define LRFDMDM_STRB1_C1BEPEAKC 0x00000080U 1444 #define LRFDMDM_STRB1_C1BEPEAKC_M 0x00000080U 1445 #define LRFDMDM_STRB1_C1BEPEAKC_S 7U 1446 #define LRFDMDM_STRB1_C1BEPEAKC_ONE 0x00000080U 1447 #define LRFDMDM_STRB1_C1BEPEAKC_ZERO 0x00000000U 1448 1449 // Field: [6] C1BEPEAKB 1450 // 1451 // Restart C1BE peak B search (32 symbols = 128 samples) 1452 // ENUMs: 1453 // ONE The bit is 1 1454 // ZERO The bit is 0 1455 #define LRFDMDM_STRB1_C1BEPEAKB 0x00000040U 1456 #define LRFDMDM_STRB1_C1BEPEAKB_M 0x00000040U 1457 #define LRFDMDM_STRB1_C1BEPEAKB_S 6U 1458 #define LRFDMDM_STRB1_C1BEPEAKB_ONE 0x00000040U 1459 #define LRFDMDM_STRB1_C1BEPEAKB_ZERO 0x00000000U 1460 1461 // Field: [5] C1BEPEAKA 1462 // 1463 // Restart C1BE peak A search (32 symbols = 128 samples) 1464 // ENUMs: 1465 // ONE The bit is 1 1466 // ZERO The bit is 0 1467 #define LRFDMDM_STRB1_C1BEPEAKA 0x00000020U 1468 #define LRFDMDM_STRB1_C1BEPEAKA_M 0x00000020U 1469 #define LRFDMDM_STRB1_C1BEPEAKA_S 5U 1470 #define LRFDMDM_STRB1_C1BEPEAKA_ONE 0x00000020U 1471 #define LRFDMDM_STRB1_C1BEPEAKA_ZERO 0x00000000U 1472 1473 // Field: [4] C1BEADVANCE 1474 // 1475 // Speed up correlator autocopy with one sample 1476 // ENUMs: 1477 // ONE The bit is 1 1478 // ZERO The bit is 0 1479 #define LRFDMDM_STRB1_C1BEADVANCE 0x00000010U 1480 #define LRFDMDM_STRB1_C1BEADVANCE_M 0x00000010U 1481 #define LRFDMDM_STRB1_C1BEADVANCE_S 4U 1482 #define LRFDMDM_STRB1_C1BEADVANCE_ONE 0x00000010U 1483 #define LRFDMDM_STRB1_C1BEADVANCE_ZERO 0x00000000U 1484 1485 // Field: [3] C1BESTALL 1486 // 1487 // Slow down correlator autocopy with one sample 1488 // ENUMs: 1489 // ONE The bit is 1 1490 // ZERO The bit is 0 1491 #define LRFDMDM_STRB1_C1BESTALL 0x00000008U 1492 #define LRFDMDM_STRB1_C1BESTALL_M 0x00000008U 1493 #define LRFDMDM_STRB1_C1BESTALL_S 3U 1494 #define LRFDMDM_STRB1_C1BESTALL_ONE 0x00000008U 1495 #define LRFDMDM_STRB1_C1BESTALL_ZERO 0x00000000U 1496 1497 // Field: [2:1] C1BEROT 1498 // 1499 // Correlator rotate command to shift reg B 1500 // ENUMs: 1501 // ROT16R Rotate 16 samples to the right 1502 // ROT1L Rotate 1 sample to the left 1503 // ROT1R Rotate 1 sample to the right 1504 // ROT0 No additional rotation (normal shift-right mode) 1505 #define LRFDMDM_STRB1_C1BEROT_W 2U 1506 #define LRFDMDM_STRB1_C1BEROT_M 0x00000006U 1507 #define LRFDMDM_STRB1_C1BEROT_S 1U 1508 #define LRFDMDM_STRB1_C1BEROT_ROT16R 0x00000006U 1509 #define LRFDMDM_STRB1_C1BEROT_ROT1L 0x00000004U 1510 #define LRFDMDM_STRB1_C1BEROT_ROT1R 0x00000002U 1511 #define LRFDMDM_STRB1_C1BEROT_ROT0 0x00000000U 1512 1513 // Field: [0] C1BECOPY 1514 // 1515 // Copy contents of shift reg A into shift reg B 1516 // ENUMs: 1517 // ONE The bit is 1 1518 // ZERO The bit is 0 1519 #define LRFDMDM_STRB1_C1BECOPY 0x00000001U 1520 #define LRFDMDM_STRB1_C1BECOPY_M 0x00000001U 1521 #define LRFDMDM_STRB1_C1BECOPY_S 0U 1522 #define LRFDMDM_STRB1_C1BECOPY_ONE 0x00000001U 1523 #define LRFDMDM_STRB1_C1BECOPY_ZERO 0x00000000U 1524 1525 //***************************************************************************** 1526 // 1527 // Register: LRFDMDM_O_EVT0 1528 // 1529 //***************************************************************************** 1530 // Field: [15] PBEDAT 1531 // 1532 // New data from PBE received in PBEDATIN0 register. 1533 // ENUMs: 1534 // ONE The bit is 1 1535 // ZERO The bit is 0 1536 #define LRFDMDM_EVT0_PBEDAT 0x00008000U 1537 #define LRFDMDM_EVT0_PBEDAT_M 0x00008000U 1538 #define LRFDMDM_EVT0_PBEDAT_S 15U 1539 #define LRFDMDM_EVT0_PBEDAT_ONE 0x00008000U 1540 #define LRFDMDM_EVT0_PBEDAT_ZERO 0x00000000U 1541 1542 // Field: [14] PBECMD 1543 // 1544 // New command from PBE received in PBECMDIN register. 1545 // ENUMs: 1546 // ONE The bit is 1 1547 // ZERO The bit is 0 1548 #define LRFDMDM_EVT0_PBECMD 0x00004000U 1549 #define LRFDMDM_EVT0_PBECMD_M 0x00004000U 1550 #define LRFDMDM_EVT0_PBECMD_S 14U 1551 #define LRFDMDM_EVT0_PBECMD_ONE 0x00004000U 1552 #define LRFDMDM_EVT0_PBECMD_ZERO 0x00000000U 1553 1554 // Field: [13] RFEDAT 1555 // 1556 // New data from RFE received in RFEDATIN0 register. 1557 // ENUMs: 1558 // ONE The bit is 1 1559 // ZERO The bit is 0 1560 #define LRFDMDM_EVT0_RFEDAT 0x00002000U 1561 #define LRFDMDM_EVT0_RFEDAT_M 0x00002000U 1562 #define LRFDMDM_EVT0_RFEDAT_S 13U 1563 #define LRFDMDM_EVT0_RFEDAT_ONE 0x00002000U 1564 #define LRFDMDM_EVT0_RFEDAT_ZERO 0x00000000U 1565 1566 // Field: [12] BDEC 1567 // 1568 // BDEC output enable event 1569 // ENUMs: 1570 // ONE The bit is 1 1571 // ZERO The bit is 0 1572 #define LRFDMDM_EVT0_BDEC 0x00001000U 1573 #define LRFDMDM_EVT0_BDEC_M 0x00001000U 1574 #define LRFDMDM_EVT0_BDEC_S 12U 1575 #define LRFDMDM_EVT0_BDEC_ONE 0x00001000U 1576 #define LRFDMDM_EVT0_BDEC_ZERO 0x00000000U 1577 1578 // Field: [11] FRAC 1579 // 1580 // FRAC output enable event 1581 // ENUMs: 1582 // ONE The bit is 1 1583 // ZERO The bit is 0 1584 #define LRFDMDM_EVT0_FRAC 0x00000800U 1585 #define LRFDMDM_EVT0_FRAC_M 0x00000800U 1586 #define LRFDMDM_EVT0_FRAC_S 11U 1587 #define LRFDMDM_EVT0_FRAC_ONE 0x00000800U 1588 #define LRFDMDM_EVT0_FRAC_ZERO 0x00000000U 1589 1590 // Field: [10] SYSTIMEVT2 1591 // 1592 // Event 2 from SYSTIMER 1593 // ENUMs: 1594 // ONE The bit is 1 1595 // ZERO The bit is 0 1596 #define LRFDMDM_EVT0_SYSTIMEVT2 0x00000400U 1597 #define LRFDMDM_EVT0_SYSTIMEVT2_M 0x00000400U 1598 #define LRFDMDM_EVT0_SYSTIMEVT2_S 10U 1599 #define LRFDMDM_EVT0_SYSTIMEVT2_ONE 0x00000400U 1600 #define LRFDMDM_EVT0_SYSTIMEVT2_ZERO 0x00000000U 1601 1602 // Field: [9] SYSTIMEVT1 1603 // 1604 // Event 1 from SYSTIMER 1605 // ENUMs: 1606 // ONE The bit is 1 1607 // ZERO The bit is 0 1608 #define LRFDMDM_EVT0_SYSTIMEVT1 0x00000200U 1609 #define LRFDMDM_EVT0_SYSTIMEVT1_M 0x00000200U 1610 #define LRFDMDM_EVT0_SYSTIMEVT1_S 9U 1611 #define LRFDMDM_EVT0_SYSTIMEVT1_ONE 0x00000200U 1612 #define LRFDMDM_EVT0_SYSTIMEVT1_ZERO 0x00000000U 1613 1614 // Field: [8] SYSTIMEVT0 1615 // 1616 // Event 0 from SYSTIMER 1617 // ENUMs: 1618 // ONE The bit is 1 1619 // ZERO The bit is 0 1620 #define LRFDMDM_EVT0_SYSTIMEVT0 0x00000100U 1621 #define LRFDMDM_EVT0_SYSTIMEVT0_M 0x00000100U 1622 #define LRFDMDM_EVT0_SYSTIMEVT0_S 8U 1623 #define LRFDMDM_EVT0_SYSTIMEVT0_ONE 0x00000100U 1624 #define LRFDMDM_EVT0_SYSTIMEVT0_ZERO 0x00000000U 1625 1626 // Field: [7] FIFOWR 1627 // 1628 // A write to the modem FIFO (via FIFOWR register), probably by CPE. 1629 // ENUMs: 1630 // ONE The bit is 1 1631 // ZERO The bit is 0 1632 #define LRFDMDM_EVT0_FIFOWR 0x00000080U 1633 #define LRFDMDM_EVT0_FIFOWR_M 0x00000080U 1634 #define LRFDMDM_EVT0_FIFOWR_S 7U 1635 #define LRFDMDM_EVT0_FIFOWR_ONE 0x00000080U 1636 #define LRFDMDM_EVT0_FIFOWR_ZERO 0x00000000U 1637 1638 // Field: [6] COUNTER 1639 // 1640 // Counter value reached in local timer 1641 // ENUMs: 1642 // ONE The bit is 1 1643 // ZERO The bit is 0 1644 #define LRFDMDM_EVT0_COUNTER 0x00000040U 1645 #define LRFDMDM_EVT0_COUNTER_M 0x00000040U 1646 #define LRFDMDM_EVT0_COUNTER_S 6U 1647 #define LRFDMDM_EVT0_COUNTER_ONE 0x00000040U 1648 #define LRFDMDM_EVT0_COUNTER_ZERO 0x00000000U 1649 1650 // Field: [5] RFECMD 1651 // 1652 // New command from RFE received in RFECMDIN register. 1653 // ENUMs: 1654 // ONE The bit is 1 1655 // ZERO The bit is 0 1656 #define LRFDMDM_EVT0_RFECMD 0x00000020U 1657 #define LRFDMDM_EVT0_RFECMD_M 0x00000020U 1658 #define LRFDMDM_EVT0_RFECMD_S 5U 1659 #define LRFDMDM_EVT0_RFECMD_ONE 0x00000020U 1660 #define LRFDMDM_EVT0_RFECMD_ZERO 0x00000000U 1661 1662 // Field: [4] FIFOOVFL 1663 // 1664 // Modem FIFO overflow error event 1665 // ENUMs: 1666 // ONE The bit is 1 1667 // ZERO The bit is 0 1668 #define LRFDMDM_EVT0_FIFOOVFL 0x00000010U 1669 #define LRFDMDM_EVT0_FIFOOVFL_M 0x00000010U 1670 #define LRFDMDM_EVT0_FIFOOVFL_S 4U 1671 #define LRFDMDM_EVT0_FIFOOVFL_ONE 0x00000010U 1672 #define LRFDMDM_EVT0_FIFOOVFL_ZERO 0x00000000U 1673 1674 // Field: [3] FIFOUNFL 1675 // 1676 // Modem FIFO underflow error event 1677 // ENUMs: 1678 // ONE The bit is 1 1679 // ZERO The bit is 0 1680 #define LRFDMDM_EVT0_FIFOUNFL 0x00000008U 1681 #define LRFDMDM_EVT0_FIFOUNFL_M 0x00000008U 1682 #define LRFDMDM_EVT0_FIFOUNFL_S 3U 1683 #define LRFDMDM_EVT0_FIFOUNFL_ONE 0x00000008U 1684 #define LRFDMDM_EVT0_FIFOUNFL_ZERO 0x00000000U 1685 1686 // Field: [2] CLKEN4BAUD 1687 // 1688 // Clock enable event at 4 times baud rate 1689 // ENUMs: 1690 // ONE The bit is 1 1691 // ZERO The bit is 0 1692 #define LRFDMDM_EVT0_CLKEN4BAUD 0x00000004U 1693 #define LRFDMDM_EVT0_CLKEN4BAUD_M 0x00000004U 1694 #define LRFDMDM_EVT0_CLKEN4BAUD_S 2U 1695 #define LRFDMDM_EVT0_CLKEN4BAUD_ONE 0x00000004U 1696 #define LRFDMDM_EVT0_CLKEN4BAUD_ZERO 0x00000000U 1697 1698 // Field: [1] TIMER 1699 // 1700 // Timer period expired in local timer 1701 // ENUMs: 1702 // ONE The bit is 1 1703 // ZERO The bit is 0 1704 #define LRFDMDM_EVT0_TIMER 0x00000002U 1705 #define LRFDMDM_EVT0_TIMER_M 0x00000002U 1706 #define LRFDMDM_EVT0_TIMER_S 1U 1707 #define LRFDMDM_EVT0_TIMER_ONE 0x00000002U 1708 #define LRFDMDM_EVT0_TIMER_ZERO 0x00000000U 1709 1710 // Field: [0] MDMAPI 1711 // 1712 // New command from PBE has been written in API register. 1713 // ENUMs: 1714 // ONE The bit is 1 1715 // ZERO The bit is 0 1716 #define LRFDMDM_EVT0_MDMAPI 0x00000001U 1717 #define LRFDMDM_EVT0_MDMAPI_M 0x00000001U 1718 #define LRFDMDM_EVT0_MDMAPI_S 0U 1719 #define LRFDMDM_EVT0_MDMAPI_ONE 0x00000001U 1720 #define LRFDMDM_EVT0_MDMAPI_ZERO 0x00000000U 1721 1722 //***************************************************************************** 1723 // 1724 // Register: LRFDMDM_O_EVT1 1725 // 1726 //***************************************************************************** 1727 // Field: [8] REFCLK 1728 // 1729 // PLL REFCLK tick 1730 // ENUMs: 1731 // ONE The bit is 1 1732 // ZERO The bit is 0 1733 #define LRFDMDM_EVT1_REFCLK 0x00000100U 1734 #define LRFDMDM_EVT1_REFCLK_M 0x00000100U 1735 #define LRFDMDM_EVT1_REFCLK_S 8U 1736 #define LRFDMDM_EVT1_REFCLK_ONE 0x00000100U 1737 #define LRFDMDM_EVT1_REFCLK_ZERO 0x00000000U 1738 1739 // Field: [7] S2RSTOP 1740 // 1741 // S2R module has written to the STOP_ADDRESS register 1742 // ENUMs: 1743 // ONE The bit is 1 1744 // ZERO The bit is 0 1745 #define LRFDMDM_EVT1_S2RSTOP 0x00000080U 1746 #define LRFDMDM_EVT1_S2RSTOP_M 0x00000080U 1747 #define LRFDMDM_EVT1_S2RSTOP_S 7U 1748 #define LRFDMDM_EVT1_S2RSTOP_ONE 0x00000080U 1749 #define LRFDMDM_EVT1_S2RSTOP_ZERO 0x00000000U 1750 1751 // Field: [6] SWQUFALSESYNC 1752 // 1753 // Sync word qualifier rejected sync due to bit errors (happens if a correlator 1754 // event was incorrect due to noise). 1755 // ENUMs: 1756 // ONE The bit is 1 1757 // ZERO The bit is 0 1758 #define LRFDMDM_EVT1_SWQUFALSESYNC 0x00000040U 1759 #define LRFDMDM_EVT1_SWQUFALSESYNC_M 0x00000040U 1760 #define LRFDMDM_EVT1_SWQUFALSESYNC_S 6U 1761 #define LRFDMDM_EVT1_SWQUFALSESYNC_ONE 0x00000040U 1762 #define LRFDMDM_EVT1_SWQUFALSESYNC_ZERO 0x00000000U 1763 1764 // Field: [5] SWQUSYNCED 1765 // 1766 // Sync word qualifier detected sync word 1767 // ENUMs: 1768 // ONE The bit is 1 1769 // ZERO The bit is 0 1770 #define LRFDMDM_EVT1_SWQUSYNCED 0x00000020U 1771 #define LRFDMDM_EVT1_SWQUSYNCED_M 0x00000020U 1772 #define LRFDMDM_EVT1_SWQUSYNCED_S 5U 1773 #define LRFDMDM_EVT1_SWQUSYNCED_ONE 0x00000020U 1774 #define LRFDMDM_EVT1_SWQUSYNCED_ZERO 0x00000000U 1775 1776 // Field: [4] CLKENBAUDF 1777 // 1778 // Clock enable event at flushed baud rate 1779 // ENUMs: 1780 // ONE The bit is 1 1781 // ZERO The bit is 0 1782 #define LRFDMDM_EVT1_CLKENBAUDF 0x00000010U 1783 #define LRFDMDM_EVT1_CLKENBAUDF_M 0x00000010U 1784 #define LRFDMDM_EVT1_CLKENBAUDF_S 4U 1785 #define LRFDMDM_EVT1_CLKENBAUDF_ONE 0x00000010U 1786 #define LRFDMDM_EVT1_CLKENBAUDF_ZERO 0x00000000U 1787 1788 // Field: [3] FIFORVALID 1789 // 1790 // Modem FIFO has valid data so a new word can be read from it, via FIFORD. 1791 // ENUMs: 1792 // ONE The bit is 1 1793 // ZERO The bit is 0 1794 #define LRFDMDM_EVT1_FIFORVALID 0x00000008U 1795 #define LRFDMDM_EVT1_FIFORVALID_M 0x00000008U 1796 #define LRFDMDM_EVT1_FIFORVALID_S 3U 1797 #define LRFDMDM_EVT1_FIFORVALID_ONE 0x00000008U 1798 #define LRFDMDM_EVT1_FIFORVALID_ZERO 0x00000000U 1799 1800 // Field: [2] FIFOWREADY 1801 // 1802 // Modem FIFO is ready for more data so a new word can be written to it, via 1803 // FIFOWR register. 1804 // ENUMs: 1805 // ONE The bit is 1 1806 // ZERO The bit is 0 1807 #define LRFDMDM_EVT1_FIFOWREADY 0x00000004U 1808 #define LRFDMDM_EVT1_FIFOWREADY_M 0x00000004U 1809 #define LRFDMDM_EVT1_FIFOWREADY_S 2U 1810 #define LRFDMDM_EVT1_FIFOWREADY_ONE 0x00000004U 1811 #define LRFDMDM_EVT1_FIFOWREADY_ZERO 0x00000000U 1812 1813 // Field: [1] CLKENBAUD 1814 // 1815 // Clock enable event at baud rate 1816 // ENUMs: 1817 // ONE The bit is 1 1818 // ZERO The bit is 0 1819 #define LRFDMDM_EVT1_CLKENBAUD 0x00000002U 1820 #define LRFDMDM_EVT1_CLKENBAUD_M 0x00000002U 1821 #define LRFDMDM_EVT1_CLKENBAUD_S 1U 1822 #define LRFDMDM_EVT1_CLKENBAUD_ONE 0x00000002U 1823 #define LRFDMDM_EVT1_CLKENBAUD_ZERO 0x00000000U 1824 1825 // Field: [0] PREAMBLEDONE 1826 // 1827 // Preamble done interrupt from modulator 1828 // ENUMs: 1829 // ONE The bit is 1 1830 // ZERO The bit is 0 1831 #define LRFDMDM_EVT1_PREAMBLEDONE 0x00000001U 1832 #define LRFDMDM_EVT1_PREAMBLEDONE_M 0x00000001U 1833 #define LRFDMDM_EVT1_PREAMBLEDONE_S 0U 1834 #define LRFDMDM_EVT1_PREAMBLEDONE_ONE 0x00000001U 1835 #define LRFDMDM_EVT1_PREAMBLEDONE_ZERO 0x00000000U 1836 1837 //***************************************************************************** 1838 // 1839 // Register: LRFDMDM_O_EVT2 1840 // 1841 //***************************************************************************** 1842 // Field: [15] GPI1 1843 // 1844 // External input event line GPI1 from IOC 1845 // ENUMs: 1846 // ONE The bit is 1 1847 // ZERO The bit is 0 1848 #define LRFDMDM_EVT2_GPI1 0x00008000U 1849 #define LRFDMDM_EVT2_GPI1_M 0x00008000U 1850 #define LRFDMDM_EVT2_GPI1_S 15U 1851 #define LRFDMDM_EVT2_GPI1_ONE 0x00008000U 1852 #define LRFDMDM_EVT2_GPI1_ZERO 0x00000000U 1853 1854 // Field: [14] GPI0 1855 // 1856 // External input event line GPI0 from IOC. (Also, when loopback mode is 1857 // enabled in DEMDEBUG.LOOPBACKMODE, this input line represents the symbols fed 1858 // to the demodulator's decode stage). 1859 // ENUMs: 1860 // ONE The bit is 1 1861 // ZERO The bit is 0 1862 #define LRFDMDM_EVT2_GPI0 0x00004000U 1863 #define LRFDMDM_EVT2_GPI0_M 0x00004000U 1864 #define LRFDMDM_EVT2_GPI0_S 14U 1865 #define LRFDMDM_EVT2_GPI0_ONE 0x00004000U 1866 #define LRFDMDM_EVT2_GPI0_ZERO 0x00000000U 1867 1868 // Field: [12] C1BEBLOADED 1869 // 1870 // C1BE correlator B loaded (by auto-copy function) 1871 // ENUMs: 1872 // ONE The bit is 1 1873 // ZERO The bit is 0 1874 #define LRFDMDM_EVT2_C1BEBLOADED 0x00001000U 1875 #define LRFDMDM_EVT2_C1BEBLOADED_M 0x00001000U 1876 #define LRFDMDM_EVT2_C1BEBLOADED_S 12U 1877 #define LRFDMDM_EVT2_C1BEBLOADED_ONE 0x00001000U 1878 #define LRFDMDM_EVT2_C1BEBLOADED_ZERO 0x00000000U 1879 1880 // Field: [11] C1BECMBANY 1881 // 1882 // C1BE correlator AB combined, any peak detect: (abs(corr A) > thr A) and 1883 // (abs(corr B) > thr B). Event occurs one sample after actual peak. 1884 // ENUMs: 1885 // ONE The bit is 1 1886 // ZERO The bit is 0 1887 #define LRFDMDM_EVT2_C1BECMBANY 0x00000800U 1888 #define LRFDMDM_EVT2_C1BECMBANY_M 0x00000800U 1889 #define LRFDMDM_EVT2_C1BECMBANY_S 11U 1890 #define LRFDMDM_EVT2_C1BECMBANY_ONE 0x00000800U 1891 #define LRFDMDM_EVT2_C1BECMBANY_ZERO 0x00000000U 1892 1893 // Field: [10] C1BECMBNEG 1894 // 1895 // C1BE correlator AB combined, negative peak detect: (corr A < -thr A) and 1896 // (corr B < -thr B). Event occurs one sample after actual peak. 1897 // ENUMs: 1898 // ONE The bit is 1 1899 // ZERO The bit is 0 1900 #define LRFDMDM_EVT2_C1BECMBNEG 0x00000400U 1901 #define LRFDMDM_EVT2_C1BECMBNEG_M 0x00000400U 1902 #define LRFDMDM_EVT2_C1BECMBNEG_S 10U 1903 #define LRFDMDM_EVT2_C1BECMBNEG_ONE 0x00000400U 1904 #define LRFDMDM_EVT2_C1BECMBNEG_ZERO 0x00000000U 1905 1906 // Field: [9] C1BECMBPOS 1907 // 1908 // C1BE correlator AB combined, positive peak detect: (corr A > thr A) and 1909 // (corr B > thr B). Event occurs one sample after actual peak. 1910 // ENUMs: 1911 // ONE The bit is 1 1912 // ZERO The bit is 0 1913 #define LRFDMDM_EVT2_C1BECMBPOS 0x00000200U 1914 #define LRFDMDM_EVT2_C1BECMBPOS_M 0x00000200U 1915 #define LRFDMDM_EVT2_C1BECMBPOS_S 9U 1916 #define LRFDMDM_EVT2_C1BECMBPOS_ONE 0x00000200U 1917 #define LRFDMDM_EVT2_C1BECMBPOS_ZERO 0x00000000U 1918 1919 // Field: [8] C1BECANY 1920 // 1921 // C1BE correlator C, any peak detect: abs(corr C) > thr C. Event occurs one 1922 // sample after actual peak. 1923 // ENUMs: 1924 // ONE The bit is 1 1925 // ZERO The bit is 0 1926 #define LRFDMDM_EVT2_C1BECANY 0x00000100U 1927 #define LRFDMDM_EVT2_C1BECANY_M 0x00000100U 1928 #define LRFDMDM_EVT2_C1BECANY_S 8U 1929 #define LRFDMDM_EVT2_C1BECANY_ONE 0x00000100U 1930 #define LRFDMDM_EVT2_C1BECANY_ZERO 0x00000000U 1931 1932 // Field: [7] C1BECNEG 1933 // 1934 // C1BE correlator C, negative peak detect: corr C < -thr C. Event occurs one 1935 // sample after actual peak. 1936 // ENUMs: 1937 // ONE The bit is 1 1938 // ZERO The bit is 0 1939 #define LRFDMDM_EVT2_C1BECNEG 0x00000080U 1940 #define LRFDMDM_EVT2_C1BECNEG_M 0x00000080U 1941 #define LRFDMDM_EVT2_C1BECNEG_S 7U 1942 #define LRFDMDM_EVT2_C1BECNEG_ONE 0x00000080U 1943 #define LRFDMDM_EVT2_C1BECNEG_ZERO 0x00000000U 1944 1945 // Field: [6] C1BECPOS 1946 // 1947 // C1BE correlator C, positive peak detect: corr C > thr C. Event occurs one 1948 // sample after actual peak. 1949 // ENUMs: 1950 // ONE The bit is 1 1951 // ZERO The bit is 0 1952 #define LRFDMDM_EVT2_C1BECPOS 0x00000040U 1953 #define LRFDMDM_EVT2_C1BECPOS_M 0x00000040U 1954 #define LRFDMDM_EVT2_C1BECPOS_S 6U 1955 #define LRFDMDM_EVT2_C1BECPOS_ONE 0x00000040U 1956 #define LRFDMDM_EVT2_C1BECPOS_ZERO 0x00000000U 1957 1958 // Field: [5] C1BEBANY 1959 // 1960 // C1BE correlator B, any peak detect: abs(corr B) > thr B. Event occurs one 1961 // sample after actual peak. 1962 // ENUMs: 1963 // ONE The bit is 1 1964 // ZERO The bit is 0 1965 #define LRFDMDM_EVT2_C1BEBANY 0x00000020U 1966 #define LRFDMDM_EVT2_C1BEBANY_M 0x00000020U 1967 #define LRFDMDM_EVT2_C1BEBANY_S 5U 1968 #define LRFDMDM_EVT2_C1BEBANY_ONE 0x00000020U 1969 #define LRFDMDM_EVT2_C1BEBANY_ZERO 0x00000000U 1970 1971 // Field: [4] C1BEBNEG 1972 // 1973 // C1BE correlator B, negative peak detect: corr B < -threshold B. Event occurs 1974 // one sample after actual peak. 1975 // ENUMs: 1976 // ONE The bit is 1 1977 // ZERO The bit is 0 1978 #define LRFDMDM_EVT2_C1BEBNEG 0x00000010U 1979 #define LRFDMDM_EVT2_C1BEBNEG_M 0x00000010U 1980 #define LRFDMDM_EVT2_C1BEBNEG_S 4U 1981 #define LRFDMDM_EVT2_C1BEBNEG_ONE 0x00000010U 1982 #define LRFDMDM_EVT2_C1BEBNEG_ZERO 0x00000000U 1983 1984 // Field: [3] C1BEBPOS 1985 // 1986 // C1BE correlator B, positive peak detect: corr B > threshold B. Event occurs 1987 // one sample after actual peak. 1988 // ENUMs: 1989 // ONE The bit is 1 1990 // ZERO The bit is 0 1991 #define LRFDMDM_EVT2_C1BEBPOS 0x00000008U 1992 #define LRFDMDM_EVT2_C1BEBPOS_M 0x00000008U 1993 #define LRFDMDM_EVT2_C1BEBPOS_S 3U 1994 #define LRFDMDM_EVT2_C1BEBPOS_ONE 0x00000008U 1995 #define LRFDMDM_EVT2_C1BEBPOS_ZERO 0x00000000U 1996 1997 // Field: [2] C1BEAANY 1998 // 1999 // C1BE correlator A, any peak detect: abs(corr A) > thr A. Event occurs one 2000 // sample after actual peak. 2001 // ENUMs: 2002 // ONE The bit is 1 2003 // ZERO The bit is 0 2004 #define LRFDMDM_EVT2_C1BEAANY 0x00000004U 2005 #define LRFDMDM_EVT2_C1BEAANY_M 0x00000004U 2006 #define LRFDMDM_EVT2_C1BEAANY_S 2U 2007 #define LRFDMDM_EVT2_C1BEAANY_ONE 0x00000004U 2008 #define LRFDMDM_EVT2_C1BEAANY_ZERO 0x00000000U 2009 2010 // Field: [1] C1BEANEG 2011 // 2012 // C1BE correlator A, negative peak detect: corr A < -thr A. Event occurs one 2013 // sample after actual peak. 2014 // ENUMs: 2015 // ONE The bit is 1 2016 // ZERO The bit is 0 2017 #define LRFDMDM_EVT2_C1BEANEG 0x00000002U 2018 #define LRFDMDM_EVT2_C1BEANEG_M 0x00000002U 2019 #define LRFDMDM_EVT2_C1BEANEG_S 1U 2020 #define LRFDMDM_EVT2_C1BEANEG_ONE 0x00000002U 2021 #define LRFDMDM_EVT2_C1BEANEG_ZERO 0x00000000U 2022 2023 // Field: [0] C1BEAPOS 2024 // 2025 // C1BE correlator A, positive peak detect: corr A > thr A. Event occurs one 2026 // sample after actual peak. 2027 // ENUMs: 2028 // ONE The bit is 1 2029 // ZERO The bit is 0 2030 #define LRFDMDM_EVT2_C1BEAPOS 0x00000001U 2031 #define LRFDMDM_EVT2_C1BEAPOS_M 0x00000001U 2032 #define LRFDMDM_EVT2_C1BEAPOS_S 0U 2033 #define LRFDMDM_EVT2_C1BEAPOS_ONE 0x00000001U 2034 #define LRFDMDM_EVT2_C1BEAPOS_ZERO 0x00000000U 2035 2036 //***************************************************************************** 2037 // 2038 // Register: LRFDMDM_O_EVTMSK0 2039 // 2040 //***************************************************************************** 2041 // Field: [15] PBEDAT 2042 // 2043 // Enable mask for event EVT0.PBEDAT 2044 // ENUMs: 2045 // EN The bit is 1 2046 // DIS The bit is 0 2047 #define LRFDMDM_EVTMSK0_PBEDAT 0x00008000U 2048 #define LRFDMDM_EVTMSK0_PBEDAT_M 0x00008000U 2049 #define LRFDMDM_EVTMSK0_PBEDAT_S 15U 2050 #define LRFDMDM_EVTMSK0_PBEDAT_EN 0x00008000U 2051 #define LRFDMDM_EVTMSK0_PBEDAT_DIS 0x00000000U 2052 2053 // Field: [14] PBECMD 2054 // 2055 // Enable mask for event EVT0.PBECMD 2056 // ENUMs: 2057 // EN The bit is 1 2058 // DIS The bit is 0 2059 #define LRFDMDM_EVTMSK0_PBECMD 0x00004000U 2060 #define LRFDMDM_EVTMSK0_PBECMD_M 0x00004000U 2061 #define LRFDMDM_EVTMSK0_PBECMD_S 14U 2062 #define LRFDMDM_EVTMSK0_PBECMD_EN 0x00004000U 2063 #define LRFDMDM_EVTMSK0_PBECMD_DIS 0x00000000U 2064 2065 // Field: [13] RFEDAT 2066 // 2067 // Enable mask for event EVT0.RFEDAT 2068 // ENUMs: 2069 // EN The bit is 1 2070 // DIS The bit is 0 2071 #define LRFDMDM_EVTMSK0_RFEDAT 0x00002000U 2072 #define LRFDMDM_EVTMSK0_RFEDAT_M 0x00002000U 2073 #define LRFDMDM_EVTMSK0_RFEDAT_S 13U 2074 #define LRFDMDM_EVTMSK0_RFEDAT_EN 0x00002000U 2075 #define LRFDMDM_EVTMSK0_RFEDAT_DIS 0x00000000U 2076 2077 // Field: [12] BDEC 2078 // 2079 // Enable mask for event EVT0.BDEC 2080 // ENUMs: 2081 // EN The bit is 1 2082 // DIS The bit is 0 2083 #define LRFDMDM_EVTMSK0_BDEC 0x00001000U 2084 #define LRFDMDM_EVTMSK0_BDEC_M 0x00001000U 2085 #define LRFDMDM_EVTMSK0_BDEC_S 12U 2086 #define LRFDMDM_EVTMSK0_BDEC_EN 0x00001000U 2087 #define LRFDMDM_EVTMSK0_BDEC_DIS 0x00000000U 2088 2089 // Field: [11] FRAC 2090 // 2091 // Enable mask for event EVT0.FRAC 2092 // ENUMs: 2093 // EN The bit is 1 2094 // DIS The bit is 0 2095 #define LRFDMDM_EVTMSK0_FRAC 0x00000800U 2096 #define LRFDMDM_EVTMSK0_FRAC_M 0x00000800U 2097 #define LRFDMDM_EVTMSK0_FRAC_S 11U 2098 #define LRFDMDM_EVTMSK0_FRAC_EN 0x00000800U 2099 #define LRFDMDM_EVTMSK0_FRAC_DIS 0x00000000U 2100 2101 // Field: [10] SYSTIMEVT2 2102 // 2103 // Enable mask for event EVT0.SYSTIMEVT2 2104 // ENUMs: 2105 // EN The bit is 1 2106 // DIS The bit is 0 2107 #define LRFDMDM_EVTMSK0_SYSTIMEVT2 0x00000400U 2108 #define LRFDMDM_EVTMSK0_SYSTIMEVT2_M 0x00000400U 2109 #define LRFDMDM_EVTMSK0_SYSTIMEVT2_S 10U 2110 #define LRFDMDM_EVTMSK0_SYSTIMEVT2_EN 0x00000400U 2111 #define LRFDMDM_EVTMSK0_SYSTIMEVT2_DIS 0x00000000U 2112 2113 // Field: [9] SYSTIMEVT1 2114 // 2115 // Enable mask for event EVT0.SYSTIMEVT1 2116 // ENUMs: 2117 // EN The bit is 1 2118 // DIS The bit is 0 2119 #define LRFDMDM_EVTMSK0_SYSTIMEVT1 0x00000200U 2120 #define LRFDMDM_EVTMSK0_SYSTIMEVT1_M 0x00000200U 2121 #define LRFDMDM_EVTMSK0_SYSTIMEVT1_S 9U 2122 #define LRFDMDM_EVTMSK0_SYSTIMEVT1_EN 0x00000200U 2123 #define LRFDMDM_EVTMSK0_SYSTIMEVT1_DIS 0x00000000U 2124 2125 // Field: [8] SYSTIMEVT0 2126 // 2127 // Enable mask for event EVT0.SYSTIMEVT0 2128 // ENUMs: 2129 // EN The bit is 1 2130 // DIS The bit is 0 2131 #define LRFDMDM_EVTMSK0_SYSTIMEVT0 0x00000100U 2132 #define LRFDMDM_EVTMSK0_SYSTIMEVT0_M 0x00000100U 2133 #define LRFDMDM_EVTMSK0_SYSTIMEVT0_S 8U 2134 #define LRFDMDM_EVTMSK0_SYSTIMEVT0_EN 0x00000100U 2135 #define LRFDMDM_EVTMSK0_SYSTIMEVT0_DIS 0x00000000U 2136 2137 // Field: [7] FIFOWR 2138 // 2139 // Enable mask for event EVT0.FIFOWR 2140 // ENUMs: 2141 // EN The bit is 1 2142 // DIS The bit is 0 2143 #define LRFDMDM_EVTMSK0_FIFOWR 0x00000080U 2144 #define LRFDMDM_EVTMSK0_FIFOWR_M 0x00000080U 2145 #define LRFDMDM_EVTMSK0_FIFOWR_S 7U 2146 #define LRFDMDM_EVTMSK0_FIFOWR_EN 0x00000080U 2147 #define LRFDMDM_EVTMSK0_FIFOWR_DIS 0x00000000U 2148 2149 // Field: [6] COUNTER 2150 // 2151 // Enable mask for event EVT0.COUNTER 2152 // ENUMs: 2153 // EN The bit is 1 2154 // DIS The bit is 0 2155 #define LRFDMDM_EVTMSK0_COUNTER 0x00000040U 2156 #define LRFDMDM_EVTMSK0_COUNTER_M 0x00000040U 2157 #define LRFDMDM_EVTMSK0_COUNTER_S 6U 2158 #define LRFDMDM_EVTMSK0_COUNTER_EN 0x00000040U 2159 #define LRFDMDM_EVTMSK0_COUNTER_DIS 0x00000000U 2160 2161 // Field: [5] RFECMD 2162 // 2163 // Enable mask for event EVT0.RFECMD 2164 // ENUMs: 2165 // EN The bit is 1 2166 // DIS The bit is 0 2167 #define LRFDMDM_EVTMSK0_RFECMD 0x00000020U 2168 #define LRFDMDM_EVTMSK0_RFECMD_M 0x00000020U 2169 #define LRFDMDM_EVTMSK0_RFECMD_S 5U 2170 #define LRFDMDM_EVTMSK0_RFECMD_EN 0x00000020U 2171 #define LRFDMDM_EVTMSK0_RFECMD_DIS 0x00000000U 2172 2173 // Field: [4] FIFOOVFL 2174 // 2175 // Enable mask for event EVT0.FIFOOVFL 2176 // ENUMs: 2177 // EN The bit is 1 2178 // DIS The bit is 0 2179 #define LRFDMDM_EVTMSK0_FIFOOVFL 0x00000010U 2180 #define LRFDMDM_EVTMSK0_FIFOOVFL_M 0x00000010U 2181 #define LRFDMDM_EVTMSK0_FIFOOVFL_S 4U 2182 #define LRFDMDM_EVTMSK0_FIFOOVFL_EN 0x00000010U 2183 #define LRFDMDM_EVTMSK0_FIFOOVFL_DIS 0x00000000U 2184 2185 // Field: [3] FIFOUNFL 2186 // 2187 // Enable mask for event EVT0.FIFOUNFL 2188 // ENUMs: 2189 // EN The bit is 1 2190 // DIS The bit is 0 2191 #define LRFDMDM_EVTMSK0_FIFOUNFL 0x00000008U 2192 #define LRFDMDM_EVTMSK0_FIFOUNFL_M 0x00000008U 2193 #define LRFDMDM_EVTMSK0_FIFOUNFL_S 3U 2194 #define LRFDMDM_EVTMSK0_FIFOUNFL_EN 0x00000008U 2195 #define LRFDMDM_EVTMSK0_FIFOUNFL_DIS 0x00000000U 2196 2197 // Field: [2] CLKEN4BAUD 2198 // 2199 // Enable mask for event EVT0.CLKEN4BAUD 2200 // ENUMs: 2201 // EN The bit is 1 2202 // DIS The bit is 0 2203 #define LRFDMDM_EVTMSK0_CLKEN4BAUD 0x00000004U 2204 #define LRFDMDM_EVTMSK0_CLKEN4BAUD_M 0x00000004U 2205 #define LRFDMDM_EVTMSK0_CLKEN4BAUD_S 2U 2206 #define LRFDMDM_EVTMSK0_CLKEN4BAUD_EN 0x00000004U 2207 #define LRFDMDM_EVTMSK0_CLKEN4BAUD_DIS 0x00000000U 2208 2209 // Field: [1] TIMER 2210 // 2211 // Enable mask for event EVT0.TIMER 2212 // ENUMs: 2213 // EN The bit is 1 2214 // DIS The bit is 0 2215 #define LRFDMDM_EVTMSK0_TIMER 0x00000002U 2216 #define LRFDMDM_EVTMSK0_TIMER_M 0x00000002U 2217 #define LRFDMDM_EVTMSK0_TIMER_S 1U 2218 #define LRFDMDM_EVTMSK0_TIMER_EN 0x00000002U 2219 #define LRFDMDM_EVTMSK0_TIMER_DIS 0x00000000U 2220 2221 // Field: [0] MDMAPI 2222 // 2223 // Enable mask for event EVT0.MDMAPI 2224 // ENUMs: 2225 // EN The bit is 1 2226 // DIS The bit is 0 2227 #define LRFDMDM_EVTMSK0_MDMAPI 0x00000001U 2228 #define LRFDMDM_EVTMSK0_MDMAPI_M 0x00000001U 2229 #define LRFDMDM_EVTMSK0_MDMAPI_S 0U 2230 #define LRFDMDM_EVTMSK0_MDMAPI_EN 0x00000001U 2231 #define LRFDMDM_EVTMSK0_MDMAPI_DIS 0x00000000U 2232 2233 //***************************************************************************** 2234 // 2235 // Register: LRFDMDM_O_EVTMSK1 2236 // 2237 //***************************************************************************** 2238 // Field: [8] REFCLK 2239 // 2240 // Enable mask for EVT1.REFCLK 2241 // ENUMs: 2242 // EN The bit is 1 2243 // DIS The bit is 0 2244 #define LRFDMDM_EVTMSK1_REFCLK 0x00000100U 2245 #define LRFDMDM_EVTMSK1_REFCLK_M 0x00000100U 2246 #define LRFDMDM_EVTMSK1_REFCLK_S 8U 2247 #define LRFDMDM_EVTMSK1_REFCLK_EN 0x00000100U 2248 #define LRFDMDM_EVTMSK1_REFCLK_DIS 0x00000000U 2249 2250 // Field: [7] S2RSTOP 2251 // 2252 // Enable mask for EVT1.S2RSTOP 2253 // ENUMs: 2254 // EN The bit is 1 2255 // DIS The bit is 0 2256 #define LRFDMDM_EVTMSK1_S2RSTOP 0x00000080U 2257 #define LRFDMDM_EVTMSK1_S2RSTOP_M 0x00000080U 2258 #define LRFDMDM_EVTMSK1_S2RSTOP_S 7U 2259 #define LRFDMDM_EVTMSK1_S2RSTOP_EN 0x00000080U 2260 #define LRFDMDM_EVTMSK1_S2RSTOP_DIS 0x00000000U 2261 2262 // Field: [6] SWQUFALSESYNC 2263 // 2264 // Enable mask for event EVT1.SWQUFALSESYNC 2265 // ENUMs: 2266 // EN The bit is 1 2267 // DIS The bit is 0 2268 #define LRFDMDM_EVTMSK1_SWQUFALSESYNC 0x00000040U 2269 #define LRFDMDM_EVTMSK1_SWQUFALSESYNC_M 0x00000040U 2270 #define LRFDMDM_EVTMSK1_SWQUFALSESYNC_S 6U 2271 #define LRFDMDM_EVTMSK1_SWQUFALSESYNC_EN 0x00000040U 2272 #define LRFDMDM_EVTMSK1_SWQUFALSESYNC_DIS 0x00000000U 2273 2274 // Field: [5] SWQUSYNCED 2275 // 2276 // Enable mask for event EVT1.SWQUSYNCED 2277 // ENUMs: 2278 // EN The bit is 1 2279 // DIS The bit is 0 2280 #define LRFDMDM_EVTMSK1_SWQUSYNCED 0x00000020U 2281 #define LRFDMDM_EVTMSK1_SWQUSYNCED_M 0x00000020U 2282 #define LRFDMDM_EVTMSK1_SWQUSYNCED_S 5U 2283 #define LRFDMDM_EVTMSK1_SWQUSYNCED_EN 0x00000020U 2284 #define LRFDMDM_EVTMSK1_SWQUSYNCED_DIS 0x00000000U 2285 2286 // Field: [4] CLKENBAUDF 2287 // 2288 // Enable mask for event EVT1.CLKENBAUDF 2289 // ENUMs: 2290 // EN The bit is 1 2291 // DIS The bit is 0 2292 #define LRFDMDM_EVTMSK1_CLKENBAUDF 0x00000010U 2293 #define LRFDMDM_EVTMSK1_CLKENBAUDF_M 0x00000010U 2294 #define LRFDMDM_EVTMSK1_CLKENBAUDF_S 4U 2295 #define LRFDMDM_EVTMSK1_CLKENBAUDF_EN 0x00000010U 2296 #define LRFDMDM_EVTMSK1_CLKENBAUDF_DIS 0x00000000U 2297 2298 // Field: [3] FIFORVALID 2299 // 2300 // Enable mask for event EVT1.FIFORVALID 2301 // ENUMs: 2302 // EN The bit is 1 2303 // DIS The bit is 0 2304 #define LRFDMDM_EVTMSK1_FIFORVALID 0x00000008U 2305 #define LRFDMDM_EVTMSK1_FIFORVALID_M 0x00000008U 2306 #define LRFDMDM_EVTMSK1_FIFORVALID_S 3U 2307 #define LRFDMDM_EVTMSK1_FIFORVALID_EN 0x00000008U 2308 #define LRFDMDM_EVTMSK1_FIFORVALID_DIS 0x00000000U 2309 2310 // Field: [2] FIFOWREADY 2311 // 2312 // Enable mask for event EVT1.FIFOWREADY 2313 // ENUMs: 2314 // EN The bit is 1 2315 // DIS The bit is 0 2316 #define LRFDMDM_EVTMSK1_FIFOWREADY 0x00000004U 2317 #define LRFDMDM_EVTMSK1_FIFOWREADY_M 0x00000004U 2318 #define LRFDMDM_EVTMSK1_FIFOWREADY_S 2U 2319 #define LRFDMDM_EVTMSK1_FIFOWREADY_EN 0x00000004U 2320 #define LRFDMDM_EVTMSK1_FIFOWREADY_DIS 0x00000000U 2321 2322 // Field: [1] CLKENBAUD 2323 // 2324 // Enable mask for event EVT1.CLKENBAUD 2325 // ENUMs: 2326 // EN The bit is 1 2327 // DIS The bit is 0 2328 #define LRFDMDM_EVTMSK1_CLKENBAUD 0x00000002U 2329 #define LRFDMDM_EVTMSK1_CLKENBAUD_M 0x00000002U 2330 #define LRFDMDM_EVTMSK1_CLKENBAUD_S 1U 2331 #define LRFDMDM_EVTMSK1_CLKENBAUD_EN 0x00000002U 2332 #define LRFDMDM_EVTMSK1_CLKENBAUD_DIS 0x00000000U 2333 2334 // Field: [0] PREAMBLEDONE 2335 // 2336 // Enable mask for event EVT1.PREAMBLEDONE 2337 // ENUMs: 2338 // EN The bit is 1 2339 // DIS The bit is 0 2340 #define LRFDMDM_EVTMSK1_PREAMBLEDONE 0x00000001U 2341 #define LRFDMDM_EVTMSK1_PREAMBLEDONE_M 0x00000001U 2342 #define LRFDMDM_EVTMSK1_PREAMBLEDONE_S 0U 2343 #define LRFDMDM_EVTMSK1_PREAMBLEDONE_EN 0x00000001U 2344 #define LRFDMDM_EVTMSK1_PREAMBLEDONE_DIS 0x00000000U 2345 2346 //***************************************************************************** 2347 // 2348 // Register: LRFDMDM_O_EVTMSK2 2349 // 2350 //***************************************************************************** 2351 // Field: [15] GPI1 2352 // 2353 // Enable mask for event EVT2.GPI1 2354 // ENUMs: 2355 // EN The bit is 1 2356 // DIS The bit is 0 2357 #define LRFDMDM_EVTMSK2_GPI1 0x00008000U 2358 #define LRFDMDM_EVTMSK2_GPI1_M 0x00008000U 2359 #define LRFDMDM_EVTMSK2_GPI1_S 15U 2360 #define LRFDMDM_EVTMSK2_GPI1_EN 0x00008000U 2361 #define LRFDMDM_EVTMSK2_GPI1_DIS 0x00000000U 2362 2363 // Field: [14] GPI0 2364 // 2365 // Enable mask for event EVT2.GPI0 2366 // ENUMs: 2367 // EN The bit is 1 2368 // DIS The bit is 0 2369 #define LRFDMDM_EVTMSK2_GPI0 0x00004000U 2370 #define LRFDMDM_EVTMSK2_GPI0_M 0x00004000U 2371 #define LRFDMDM_EVTMSK2_GPI0_S 14U 2372 #define LRFDMDM_EVTMSK2_GPI0_EN 0x00004000U 2373 #define LRFDMDM_EVTMSK2_GPI0_DIS 0x00000000U 2374 2375 // Field: [12] C1BEBLOADED 2376 // 2377 // Enable mask for event EVT2.C1BEBLOADED 2378 // ENUMs: 2379 // EN The bit is 1 2380 // DIS The bit is 0 2381 #define LRFDMDM_EVTMSK2_C1BEBLOADED 0x00001000U 2382 #define LRFDMDM_EVTMSK2_C1BEBLOADED_M 0x00001000U 2383 #define LRFDMDM_EVTMSK2_C1BEBLOADED_S 12U 2384 #define LRFDMDM_EVTMSK2_C1BEBLOADED_EN 0x00001000U 2385 #define LRFDMDM_EVTMSK2_C1BEBLOADED_DIS 0x00000000U 2386 2387 // Field: [11] C1BECMBANY 2388 // 2389 // Enable mask for event EVT2.C1BECMBANY 2390 // ENUMs: 2391 // EN The bit is 1 2392 // DIS The bit is 0 2393 #define LRFDMDM_EVTMSK2_C1BECMBANY 0x00000800U 2394 #define LRFDMDM_EVTMSK2_C1BECMBANY_M 0x00000800U 2395 #define LRFDMDM_EVTMSK2_C1BECMBANY_S 11U 2396 #define LRFDMDM_EVTMSK2_C1BECMBANY_EN 0x00000800U 2397 #define LRFDMDM_EVTMSK2_C1BECMBANY_DIS 0x00000000U 2398 2399 // Field: [10] C1BECMBNEG 2400 // 2401 // Enable mask for event EVT2.C1BECMBNEG 2402 // ENUMs: 2403 // EN The bit is 1 2404 // DIS The bit is 0 2405 #define LRFDMDM_EVTMSK2_C1BECMBNEG 0x00000400U 2406 #define LRFDMDM_EVTMSK2_C1BECMBNEG_M 0x00000400U 2407 #define LRFDMDM_EVTMSK2_C1BECMBNEG_S 10U 2408 #define LRFDMDM_EVTMSK2_C1BECMBNEG_EN 0x00000400U 2409 #define LRFDMDM_EVTMSK2_C1BECMBNEG_DIS 0x00000000U 2410 2411 // Field: [9] C1BECMBPOS 2412 // 2413 // Enable mask for event EVT2.C1BECMBPOS 2414 // ENUMs: 2415 // EN The bit is 1 2416 // DIS The bit is 0 2417 #define LRFDMDM_EVTMSK2_C1BECMBPOS 0x00000200U 2418 #define LRFDMDM_EVTMSK2_C1BECMBPOS_M 0x00000200U 2419 #define LRFDMDM_EVTMSK2_C1BECMBPOS_S 9U 2420 #define LRFDMDM_EVTMSK2_C1BECMBPOS_EN 0x00000200U 2421 #define LRFDMDM_EVTMSK2_C1BECMBPOS_DIS 0x00000000U 2422 2423 // Field: [8] C1BECANY 2424 // 2425 // Enable mask for event EVT2.C1BECANY 2426 // ENUMs: 2427 // EN The bit is 1 2428 // DIS The bit is 0 2429 #define LRFDMDM_EVTMSK2_C1BECANY 0x00000100U 2430 #define LRFDMDM_EVTMSK2_C1BECANY_M 0x00000100U 2431 #define LRFDMDM_EVTMSK2_C1BECANY_S 8U 2432 #define LRFDMDM_EVTMSK2_C1BECANY_EN 0x00000100U 2433 #define LRFDMDM_EVTMSK2_C1BECANY_DIS 0x00000000U 2434 2435 // Field: [7] C1BECNEG 2436 // 2437 // Enable mask for event EVT2.C1BECNEG 2438 // ENUMs: 2439 // EN The bit is 1 2440 // DIS The bit is 0 2441 #define LRFDMDM_EVTMSK2_C1BECNEG 0x00000080U 2442 #define LRFDMDM_EVTMSK2_C1BECNEG_M 0x00000080U 2443 #define LRFDMDM_EVTMSK2_C1BECNEG_S 7U 2444 #define LRFDMDM_EVTMSK2_C1BECNEG_EN 0x00000080U 2445 #define LRFDMDM_EVTMSK2_C1BECNEG_DIS 0x00000000U 2446 2447 // Field: [6] C1BECPOS 2448 // 2449 // Enable mask for event EVT2.C1BECPOS 2450 // ENUMs: 2451 // EN The bit is 1 2452 // DIS The bit is 0 2453 #define LRFDMDM_EVTMSK2_C1BECPOS 0x00000040U 2454 #define LRFDMDM_EVTMSK2_C1BECPOS_M 0x00000040U 2455 #define LRFDMDM_EVTMSK2_C1BECPOS_S 6U 2456 #define LRFDMDM_EVTMSK2_C1BECPOS_EN 0x00000040U 2457 #define LRFDMDM_EVTMSK2_C1BECPOS_DIS 0x00000000U 2458 2459 // Field: [5] C1BEBANY 2460 // 2461 // Enable mask for event EVT2.C1BEBANY 2462 // ENUMs: 2463 // EN The bit is 1 2464 // DIS The bit is 0 2465 #define LRFDMDM_EVTMSK2_C1BEBANY 0x00000020U 2466 #define LRFDMDM_EVTMSK2_C1BEBANY_M 0x00000020U 2467 #define LRFDMDM_EVTMSK2_C1BEBANY_S 5U 2468 #define LRFDMDM_EVTMSK2_C1BEBANY_EN 0x00000020U 2469 #define LRFDMDM_EVTMSK2_C1BEBANY_DIS 0x00000000U 2470 2471 // Field: [4] C1BEBNEG 2472 // 2473 // Enable mask for event EVT2.C1BEBNEG 2474 // ENUMs: 2475 // EN The bit is 1 2476 // DIS The bit is 0 2477 #define LRFDMDM_EVTMSK2_C1BEBNEG 0x00000010U 2478 #define LRFDMDM_EVTMSK2_C1BEBNEG_M 0x00000010U 2479 #define LRFDMDM_EVTMSK2_C1BEBNEG_S 4U 2480 #define LRFDMDM_EVTMSK2_C1BEBNEG_EN 0x00000010U 2481 #define LRFDMDM_EVTMSK2_C1BEBNEG_DIS 0x00000000U 2482 2483 // Field: [3] C1BEBPOS 2484 // 2485 // Enable mask for event EVT2.C1BEBPOS 2486 // ENUMs: 2487 // EN The bit is 1 2488 // DIS The bit is 0 2489 #define LRFDMDM_EVTMSK2_C1BEBPOS 0x00000008U 2490 #define LRFDMDM_EVTMSK2_C1BEBPOS_M 0x00000008U 2491 #define LRFDMDM_EVTMSK2_C1BEBPOS_S 3U 2492 #define LRFDMDM_EVTMSK2_C1BEBPOS_EN 0x00000008U 2493 #define LRFDMDM_EVTMSK2_C1BEBPOS_DIS 0x00000000U 2494 2495 // Field: [2] C1BEAANY 2496 // 2497 // Enable mask for event EVT2.C1BEAANY 2498 // ENUMs: 2499 // EN The bit is 1 2500 // DIS The bit is 0 2501 #define LRFDMDM_EVTMSK2_C1BEAANY 0x00000004U 2502 #define LRFDMDM_EVTMSK2_C1BEAANY_M 0x00000004U 2503 #define LRFDMDM_EVTMSK2_C1BEAANY_S 2U 2504 #define LRFDMDM_EVTMSK2_C1BEAANY_EN 0x00000004U 2505 #define LRFDMDM_EVTMSK2_C1BEAANY_DIS 0x00000000U 2506 2507 // Field: [1] C1BEANEG 2508 // 2509 // Enable mask for event EVT2.C1BEANEG 2510 // ENUMs: 2511 // EN The bit is 1 2512 // DIS The bit is 0 2513 #define LRFDMDM_EVTMSK2_C1BEANEG 0x00000002U 2514 #define LRFDMDM_EVTMSK2_C1BEANEG_M 0x00000002U 2515 #define LRFDMDM_EVTMSK2_C1BEANEG_S 1U 2516 #define LRFDMDM_EVTMSK2_C1BEANEG_EN 0x00000002U 2517 #define LRFDMDM_EVTMSK2_C1BEANEG_DIS 0x00000000U 2518 2519 // Field: [0] C1BEAPOS 2520 // 2521 // Enable mask for event EVT2.C1BEAPOS 2522 // ENUMs: 2523 // EN The bit is 1 2524 // DIS The bit is 0 2525 #define LRFDMDM_EVTMSK2_C1BEAPOS 0x00000001U 2526 #define LRFDMDM_EVTMSK2_C1BEAPOS_M 0x00000001U 2527 #define LRFDMDM_EVTMSK2_C1BEAPOS_S 0U 2528 #define LRFDMDM_EVTMSK2_C1BEAPOS_EN 0x00000001U 2529 #define LRFDMDM_EVTMSK2_C1BEAPOS_DIS 0x00000000U 2530 2531 //***************************************************************************** 2532 // 2533 // Register: LRFDMDM_O_EVTCLR0 2534 // 2535 //***************************************************************************** 2536 // Field: [15] PBEDAT 2537 // 2538 // Clear event EVT0.PBEDAT 2539 // ENUMs: 2540 // CLEAR The bit is 1 2541 // RETAIN The bit is 0 2542 #define LRFDMDM_EVTCLR0_PBEDAT 0x00008000U 2543 #define LRFDMDM_EVTCLR0_PBEDAT_M 0x00008000U 2544 #define LRFDMDM_EVTCLR0_PBEDAT_S 15U 2545 #define LRFDMDM_EVTCLR0_PBEDAT_CLEAR 0x00008000U 2546 #define LRFDMDM_EVTCLR0_PBEDAT_RETAIN 0x00000000U 2547 2548 // Field: [14] PBECMD 2549 // 2550 // Clear event EVT0.PBECMD 2551 // ENUMs: 2552 // CLEAR The bit is 1 2553 // RETAIN The bit is 0 2554 #define LRFDMDM_EVTCLR0_PBECMD 0x00004000U 2555 #define LRFDMDM_EVTCLR0_PBECMD_M 0x00004000U 2556 #define LRFDMDM_EVTCLR0_PBECMD_S 14U 2557 #define LRFDMDM_EVTCLR0_PBECMD_CLEAR 0x00004000U 2558 #define LRFDMDM_EVTCLR0_PBECMD_RETAIN 0x00000000U 2559 2560 // Field: [13] RFEDAT 2561 // 2562 // Clear event EVT0.RFEDAT 2563 // ENUMs: 2564 // CLEAR The bit is 1 2565 // RETAIN The bit is 0 2566 #define LRFDMDM_EVTCLR0_RFEDAT 0x00002000U 2567 #define LRFDMDM_EVTCLR0_RFEDAT_M 0x00002000U 2568 #define LRFDMDM_EVTCLR0_RFEDAT_S 13U 2569 #define LRFDMDM_EVTCLR0_RFEDAT_CLEAR 0x00002000U 2570 #define LRFDMDM_EVTCLR0_RFEDAT_RETAIN 0x00000000U 2571 2572 // Field: [12] BDEC 2573 // 2574 // Clear event EVT0.BDEC 2575 // ENUMs: 2576 // CLEAR The bit is 1 2577 // RETAIN The bit is 0 2578 #define LRFDMDM_EVTCLR0_BDEC 0x00001000U 2579 #define LRFDMDM_EVTCLR0_BDEC_M 0x00001000U 2580 #define LRFDMDM_EVTCLR0_BDEC_S 12U 2581 #define LRFDMDM_EVTCLR0_BDEC_CLEAR 0x00001000U 2582 #define LRFDMDM_EVTCLR0_BDEC_RETAIN 0x00000000U 2583 2584 // Field: [11] FRAC 2585 // 2586 // Clear event EVT0.FRAC 2587 // ENUMs: 2588 // CLEAR The bit is 1 2589 // RETAIN The bit is 0 2590 #define LRFDMDM_EVTCLR0_FRAC 0x00000800U 2591 #define LRFDMDM_EVTCLR0_FRAC_M 0x00000800U 2592 #define LRFDMDM_EVTCLR0_FRAC_S 11U 2593 #define LRFDMDM_EVTCLR0_FRAC_CLEAR 0x00000800U 2594 #define LRFDMDM_EVTCLR0_FRAC_RETAIN 0x00000000U 2595 2596 // Field: [10] SYSTIMEVT2 2597 // 2598 // Clear event EVT0.SYSTIMEVT2 2599 // ENUMs: 2600 // CLEAR The bit is 1 2601 // RETAIN The bit is 0 2602 #define LRFDMDM_EVTCLR0_SYSTIMEVT2 0x00000400U 2603 #define LRFDMDM_EVTCLR0_SYSTIMEVT2_M 0x00000400U 2604 #define LRFDMDM_EVTCLR0_SYSTIMEVT2_S 10U 2605 #define LRFDMDM_EVTCLR0_SYSTIMEVT2_CLEAR 0x00000400U 2606 #define LRFDMDM_EVTCLR0_SYSTIMEVT2_RETAIN 0x00000000U 2607 2608 // Field: [9] SYSTIMEVT1 2609 // 2610 // Clear event EVT0.SYSTIMEVT1 2611 // ENUMs: 2612 // CLEAR The bit is 1 2613 // RETAIN The bit is 0 2614 #define LRFDMDM_EVTCLR0_SYSTIMEVT1 0x00000200U 2615 #define LRFDMDM_EVTCLR0_SYSTIMEVT1_M 0x00000200U 2616 #define LRFDMDM_EVTCLR0_SYSTIMEVT1_S 9U 2617 #define LRFDMDM_EVTCLR0_SYSTIMEVT1_CLEAR 0x00000200U 2618 #define LRFDMDM_EVTCLR0_SYSTIMEVT1_RETAIN 0x00000000U 2619 2620 // Field: [8] SYSTIMEVT0 2621 // 2622 // Clear event EVT0.SYSTIMEVT0 2623 // ENUMs: 2624 // CLEAR The bit is 1 2625 // RETAIN The bit is 0 2626 #define LRFDMDM_EVTCLR0_SYSTIMEVT0 0x00000100U 2627 #define LRFDMDM_EVTCLR0_SYSTIMEVT0_M 0x00000100U 2628 #define LRFDMDM_EVTCLR0_SYSTIMEVT0_S 8U 2629 #define LRFDMDM_EVTCLR0_SYSTIMEVT0_CLEAR 0x00000100U 2630 #define LRFDMDM_EVTCLR0_SYSTIMEVT0_RETAIN 0x00000000U 2631 2632 // Field: [7] FIFOWR 2633 // 2634 // Clear event EVT0.FIFOWR 2635 // ENUMs: 2636 // CLEAR The bit is 1 2637 // RETAIN The bit is 0 2638 #define LRFDMDM_EVTCLR0_FIFOWR 0x00000080U 2639 #define LRFDMDM_EVTCLR0_FIFOWR_M 0x00000080U 2640 #define LRFDMDM_EVTCLR0_FIFOWR_S 7U 2641 #define LRFDMDM_EVTCLR0_FIFOWR_CLEAR 0x00000080U 2642 #define LRFDMDM_EVTCLR0_FIFOWR_RETAIN 0x00000000U 2643 2644 // Field: [6] COUNTER 2645 // 2646 // Clear event EVT0.COUNTER 2647 // ENUMs: 2648 // CLEAR The bit is 1 2649 // RETAIN The bit is 0 2650 #define LRFDMDM_EVTCLR0_COUNTER 0x00000040U 2651 #define LRFDMDM_EVTCLR0_COUNTER_M 0x00000040U 2652 #define LRFDMDM_EVTCLR0_COUNTER_S 6U 2653 #define LRFDMDM_EVTCLR0_COUNTER_CLEAR 0x00000040U 2654 #define LRFDMDM_EVTCLR0_COUNTER_RETAIN 0x00000000U 2655 2656 // Field: [5] RFECMD 2657 // 2658 // Clear event EVT0.RFECMD 2659 // ENUMs: 2660 // CLEAR The bit is 1 2661 // RETAIN The bit is 0 2662 #define LRFDMDM_EVTCLR0_RFECMD 0x00000020U 2663 #define LRFDMDM_EVTCLR0_RFECMD_M 0x00000020U 2664 #define LRFDMDM_EVTCLR0_RFECMD_S 5U 2665 #define LRFDMDM_EVTCLR0_RFECMD_CLEAR 0x00000020U 2666 #define LRFDMDM_EVTCLR0_RFECMD_RETAIN 0x00000000U 2667 2668 // Field: [4] FIFOOVFL 2669 // 2670 // Clear event EVT0.FIFOOVFL 2671 // ENUMs: 2672 // CLEAR The bit is 1 2673 // RETAIN The bit is 0 2674 #define LRFDMDM_EVTCLR0_FIFOOVFL 0x00000010U 2675 #define LRFDMDM_EVTCLR0_FIFOOVFL_M 0x00000010U 2676 #define LRFDMDM_EVTCLR0_FIFOOVFL_S 4U 2677 #define LRFDMDM_EVTCLR0_FIFOOVFL_CLEAR 0x00000010U 2678 #define LRFDMDM_EVTCLR0_FIFOOVFL_RETAIN 0x00000000U 2679 2680 // Field: [3] FIFOUNFL 2681 // 2682 // Clear event EVT0.FIFOUNFL 2683 // ENUMs: 2684 // CLEAR The bit is 1 2685 // RETAIN The bit is 0 2686 #define LRFDMDM_EVTCLR0_FIFOUNFL 0x00000008U 2687 #define LRFDMDM_EVTCLR0_FIFOUNFL_M 0x00000008U 2688 #define LRFDMDM_EVTCLR0_FIFOUNFL_S 3U 2689 #define LRFDMDM_EVTCLR0_FIFOUNFL_CLEAR 0x00000008U 2690 #define LRFDMDM_EVTCLR0_FIFOUNFL_RETAIN 0x00000000U 2691 2692 // Field: [2] CLKEN4BAUD 2693 // 2694 // Clear event EVT0.CLKEN4BAUD 2695 // ENUMs: 2696 // CLEAR The bit is 1 2697 // RETAIN The bit is 0 2698 #define LRFDMDM_EVTCLR0_CLKEN4BAUD 0x00000004U 2699 #define LRFDMDM_EVTCLR0_CLKEN4BAUD_M 0x00000004U 2700 #define LRFDMDM_EVTCLR0_CLKEN4BAUD_S 2U 2701 #define LRFDMDM_EVTCLR0_CLKEN4BAUD_CLEAR 0x00000004U 2702 #define LRFDMDM_EVTCLR0_CLKEN4BAUD_RETAIN 0x00000000U 2703 2704 // Field: [1] TIMER 2705 // 2706 // Clear event EVT0.TIMER 2707 // ENUMs: 2708 // CLEAR The bit is 1 2709 // RETAIN The bit is 0 2710 #define LRFDMDM_EVTCLR0_TIMER 0x00000002U 2711 #define LRFDMDM_EVTCLR0_TIMER_M 0x00000002U 2712 #define LRFDMDM_EVTCLR0_TIMER_S 1U 2713 #define LRFDMDM_EVTCLR0_TIMER_CLEAR 0x00000002U 2714 #define LRFDMDM_EVTCLR0_TIMER_RETAIN 0x00000000U 2715 2716 // Field: [0] MDMAPI 2717 // 2718 // Clear event EVT0.MDMAPI 2719 // ENUMs: 2720 // CLEAR The bit is 1 2721 // RETAIN The bit is 0 2722 #define LRFDMDM_EVTCLR0_MDMAPI 0x00000001U 2723 #define LRFDMDM_EVTCLR0_MDMAPI_M 0x00000001U 2724 #define LRFDMDM_EVTCLR0_MDMAPI_S 0U 2725 #define LRFDMDM_EVTCLR0_MDMAPI_CLEAR 0x00000001U 2726 #define LRFDMDM_EVTCLR0_MDMAPI_RETAIN 0x00000000U 2727 2728 //***************************************************************************** 2729 // 2730 // Register: LRFDMDM_O_EVTCLR1 2731 // 2732 //***************************************************************************** 2733 // Field: [8] REFCLK 2734 // 2735 // Clear event EVT1.REFCLK 2736 // ENUMs: 2737 // CLEAR The bit is 1 2738 // RETAIN The bit is 0 2739 #define LRFDMDM_EVTCLR1_REFCLK 0x00000100U 2740 #define LRFDMDM_EVTCLR1_REFCLK_M 0x00000100U 2741 #define LRFDMDM_EVTCLR1_REFCLK_S 8U 2742 #define LRFDMDM_EVTCLR1_REFCLK_CLEAR 0x00000100U 2743 #define LRFDMDM_EVTCLR1_REFCLK_RETAIN 0x00000000U 2744 2745 // Field: [7] S2RSTOP 2746 // 2747 // Clear event EVT1.S2RSTOP 2748 // ENUMs: 2749 // CLEAR The bit is 1 2750 // RETAIN The bit is 0 2751 #define LRFDMDM_EVTCLR1_S2RSTOP 0x00000080U 2752 #define LRFDMDM_EVTCLR1_S2RSTOP_M 0x00000080U 2753 #define LRFDMDM_EVTCLR1_S2RSTOP_S 7U 2754 #define LRFDMDM_EVTCLR1_S2RSTOP_CLEAR 0x00000080U 2755 #define LRFDMDM_EVTCLR1_S2RSTOP_RETAIN 0x00000000U 2756 2757 // Field: [6] SWQUFALSESYNC 2758 // 2759 // Clear event EVT1.SWQUFALSESYNC 2760 // ENUMs: 2761 // CLEAR The bit is 1 2762 // RETAIN The bit is 0 2763 #define LRFDMDM_EVTCLR1_SWQUFALSESYNC 0x00000040U 2764 #define LRFDMDM_EVTCLR1_SWQUFALSESYNC_M 0x00000040U 2765 #define LRFDMDM_EVTCLR1_SWQUFALSESYNC_S 6U 2766 #define LRFDMDM_EVTCLR1_SWQUFALSESYNC_CLEAR 0x00000040U 2767 #define LRFDMDM_EVTCLR1_SWQUFALSESYNC_RETAIN 0x00000000U 2768 2769 // Field: [5] SWQUSYNCED 2770 // 2771 // Clear event EVT1.SWQUSYNCED 2772 // ENUMs: 2773 // CLEAR The bit is 1 2774 // RETAIN The bit is 0 2775 #define LRFDMDM_EVTCLR1_SWQUSYNCED 0x00000020U 2776 #define LRFDMDM_EVTCLR1_SWQUSYNCED_M 0x00000020U 2777 #define LRFDMDM_EVTCLR1_SWQUSYNCED_S 5U 2778 #define LRFDMDM_EVTCLR1_SWQUSYNCED_CLEAR 0x00000020U 2779 #define LRFDMDM_EVTCLR1_SWQUSYNCED_RETAIN 0x00000000U 2780 2781 // Field: [4] CLKENBAUDF 2782 // 2783 // Clear event EVT1.CLKENBAUDF 2784 // ENUMs: 2785 // CLEAR The bit is 1 2786 // RETAIN The bit is 0 2787 #define LRFDMDM_EVTCLR1_CLKENBAUDF 0x00000010U 2788 #define LRFDMDM_EVTCLR1_CLKENBAUDF_M 0x00000010U 2789 #define LRFDMDM_EVTCLR1_CLKENBAUDF_S 4U 2790 #define LRFDMDM_EVTCLR1_CLKENBAUDF_CLEAR 0x00000010U 2791 #define LRFDMDM_EVTCLR1_CLKENBAUDF_RETAIN 0x00000000U 2792 2793 // Field: [3] FIFORVALID 2794 // 2795 // Clear event EVT1.FIFORVALID 2796 // ENUMs: 2797 // CLEAR The bit is 1 2798 // RETAIN The bit is 0 2799 #define LRFDMDM_EVTCLR1_FIFORVALID 0x00000008U 2800 #define LRFDMDM_EVTCLR1_FIFORVALID_M 0x00000008U 2801 #define LRFDMDM_EVTCLR1_FIFORVALID_S 3U 2802 #define LRFDMDM_EVTCLR1_FIFORVALID_CLEAR 0x00000008U 2803 #define LRFDMDM_EVTCLR1_FIFORVALID_RETAIN 0x00000000U 2804 2805 // Field: [2] FIFOWREADY 2806 // 2807 // Clear event EVT1.FIFOWREADY 2808 // ENUMs: 2809 // CLEAR The bit is 1 2810 // RETAIN The bit is 0 2811 #define LRFDMDM_EVTCLR1_FIFOWREADY 0x00000004U 2812 #define LRFDMDM_EVTCLR1_FIFOWREADY_M 0x00000004U 2813 #define LRFDMDM_EVTCLR1_FIFOWREADY_S 2U 2814 #define LRFDMDM_EVTCLR1_FIFOWREADY_CLEAR 0x00000004U 2815 #define LRFDMDM_EVTCLR1_FIFOWREADY_RETAIN 0x00000000U 2816 2817 // Field: [1] CLKENBAUD 2818 // 2819 // Clear event EVT1.CLKENBAUD 2820 // ENUMs: 2821 // CLEAR The bit is 1 2822 // RETAIN The bit is 0 2823 #define LRFDMDM_EVTCLR1_CLKENBAUD 0x00000002U 2824 #define LRFDMDM_EVTCLR1_CLKENBAUD_M 0x00000002U 2825 #define LRFDMDM_EVTCLR1_CLKENBAUD_S 1U 2826 #define LRFDMDM_EVTCLR1_CLKENBAUD_CLEAR 0x00000002U 2827 #define LRFDMDM_EVTCLR1_CLKENBAUD_RETAIN 0x00000000U 2828 2829 // Field: [0] PREAMBLEDONE 2830 // 2831 // Clear event EVT1.PREAMBLEDONE 2832 // ENUMs: 2833 // CLEAR The bit is 1 2834 // RETAIN The bit is 0 2835 #define LRFDMDM_EVTCLR1_PREAMBLEDONE 0x00000001U 2836 #define LRFDMDM_EVTCLR1_PREAMBLEDONE_M 0x00000001U 2837 #define LRFDMDM_EVTCLR1_PREAMBLEDONE_S 0U 2838 #define LRFDMDM_EVTCLR1_PREAMBLEDONE_CLEAR 0x00000001U 2839 #define LRFDMDM_EVTCLR1_PREAMBLEDONE_RETAIN 0x00000000U 2840 2841 //***************************************************************************** 2842 // 2843 // Register: LRFDMDM_O_EVTCLR2 2844 // 2845 //***************************************************************************** 2846 // Field: [15] GPI1 2847 // 2848 // Clear event EVT2.GPI1 2849 // ENUMs: 2850 // CLEAR The bit is 1 2851 // RETAIN The bit is 0 2852 #define LRFDMDM_EVTCLR2_GPI1 0x00008000U 2853 #define LRFDMDM_EVTCLR2_GPI1_M 0x00008000U 2854 #define LRFDMDM_EVTCLR2_GPI1_S 15U 2855 #define LRFDMDM_EVTCLR2_GPI1_CLEAR 0x00008000U 2856 #define LRFDMDM_EVTCLR2_GPI1_RETAIN 0x00000000U 2857 2858 // Field: [14] GPI0 2859 // 2860 // Clear event EVT2.GPI0 2861 // ENUMs: 2862 // CLEAR The bit is 1 2863 // RETAIN The bit is 0 2864 #define LRFDMDM_EVTCLR2_GPI0 0x00004000U 2865 #define LRFDMDM_EVTCLR2_GPI0_M 0x00004000U 2866 #define LRFDMDM_EVTCLR2_GPI0_S 14U 2867 #define LRFDMDM_EVTCLR2_GPI0_CLEAR 0x00004000U 2868 #define LRFDMDM_EVTCLR2_GPI0_RETAIN 0x00000000U 2869 2870 // Field: [12] C1BEBLOADED 2871 // 2872 // Clear event EVT2.C1BEBLOADED 2873 // ENUMs: 2874 // CLEAR The bit is 1 2875 // RETAIN The bit is 0 2876 #define LRFDMDM_EVTCLR2_C1BEBLOADED 0x00001000U 2877 #define LRFDMDM_EVTCLR2_C1BEBLOADED_M 0x00001000U 2878 #define LRFDMDM_EVTCLR2_C1BEBLOADED_S 12U 2879 #define LRFDMDM_EVTCLR2_C1BEBLOADED_CLEAR 0x00001000U 2880 #define LRFDMDM_EVTCLR2_C1BEBLOADED_RETAIN 0x00000000U 2881 2882 // Field: [11] C1BECMBANY 2883 // 2884 // Clear event EVT2.C1BECMBANY 2885 // ENUMs: 2886 // CLEAR The bit is 1 2887 // RETAIN The bit is 0 2888 #define LRFDMDM_EVTCLR2_C1BECMBANY 0x00000800U 2889 #define LRFDMDM_EVTCLR2_C1BECMBANY_M 0x00000800U 2890 #define LRFDMDM_EVTCLR2_C1BECMBANY_S 11U 2891 #define LRFDMDM_EVTCLR2_C1BECMBANY_CLEAR 0x00000800U 2892 #define LRFDMDM_EVTCLR2_C1BECMBANY_RETAIN 0x00000000U 2893 2894 // Field: [10] C1BECMBNEG 2895 // 2896 // Clear event EVT2.C1BECMBNEG 2897 // ENUMs: 2898 // CLEAR The bit is 1 2899 // RETAIN The bit is 0 2900 #define LRFDMDM_EVTCLR2_C1BECMBNEG 0x00000400U 2901 #define LRFDMDM_EVTCLR2_C1BECMBNEG_M 0x00000400U 2902 #define LRFDMDM_EVTCLR2_C1BECMBNEG_S 10U 2903 #define LRFDMDM_EVTCLR2_C1BECMBNEG_CLEAR 0x00000400U 2904 #define LRFDMDM_EVTCLR2_C1BECMBNEG_RETAIN 0x00000000U 2905 2906 // Field: [9] C1BECMBPOS 2907 // 2908 // Clear event EVT2.C1BECMBPOS 2909 // ENUMs: 2910 // CLEAR The bit is 1 2911 // RETAIN The bit is 0 2912 #define LRFDMDM_EVTCLR2_C1BECMBPOS 0x00000200U 2913 #define LRFDMDM_EVTCLR2_C1BECMBPOS_M 0x00000200U 2914 #define LRFDMDM_EVTCLR2_C1BECMBPOS_S 9U 2915 #define LRFDMDM_EVTCLR2_C1BECMBPOS_CLEAR 0x00000200U 2916 #define LRFDMDM_EVTCLR2_C1BECMBPOS_RETAIN 0x00000000U 2917 2918 // Field: [8] C1BECANY 2919 // 2920 // Clear event EVT2.C1BECANY 2921 // ENUMs: 2922 // CLEAR The bit is 1 2923 // RETAIN The bit is 0 2924 #define LRFDMDM_EVTCLR2_C1BECANY 0x00000100U 2925 #define LRFDMDM_EVTCLR2_C1BECANY_M 0x00000100U 2926 #define LRFDMDM_EVTCLR2_C1BECANY_S 8U 2927 #define LRFDMDM_EVTCLR2_C1BECANY_CLEAR 0x00000100U 2928 #define LRFDMDM_EVTCLR2_C1BECANY_RETAIN 0x00000000U 2929 2930 // Field: [7] C1BECNEG 2931 // 2932 // Clear event EVT2.C1BECNEG 2933 // ENUMs: 2934 // CLEAR The bit is 1 2935 // RETAIN The bit is 0 2936 #define LRFDMDM_EVTCLR2_C1BECNEG 0x00000080U 2937 #define LRFDMDM_EVTCLR2_C1BECNEG_M 0x00000080U 2938 #define LRFDMDM_EVTCLR2_C1BECNEG_S 7U 2939 #define LRFDMDM_EVTCLR2_C1BECNEG_CLEAR 0x00000080U 2940 #define LRFDMDM_EVTCLR2_C1BECNEG_RETAIN 0x00000000U 2941 2942 // Field: [6] C1BECPOS 2943 // 2944 // Clear event EVT2.C1BECPOS 2945 // ENUMs: 2946 // CLEAR The bit is 1 2947 // RETAIN The bit is 0 2948 #define LRFDMDM_EVTCLR2_C1BECPOS 0x00000040U 2949 #define LRFDMDM_EVTCLR2_C1BECPOS_M 0x00000040U 2950 #define LRFDMDM_EVTCLR2_C1BECPOS_S 6U 2951 #define LRFDMDM_EVTCLR2_C1BECPOS_CLEAR 0x00000040U 2952 #define LRFDMDM_EVTCLR2_C1BECPOS_RETAIN 0x00000000U 2953 2954 // Field: [5] C1BEBANY 2955 // 2956 // Clear event EVT2.C1BEBANY 2957 // ENUMs: 2958 // CLEAR The bit is 1 2959 // RETAIN The bit is 0 2960 #define LRFDMDM_EVTCLR2_C1BEBANY 0x00000020U 2961 #define LRFDMDM_EVTCLR2_C1BEBANY_M 0x00000020U 2962 #define LRFDMDM_EVTCLR2_C1BEBANY_S 5U 2963 #define LRFDMDM_EVTCLR2_C1BEBANY_CLEAR 0x00000020U 2964 #define LRFDMDM_EVTCLR2_C1BEBANY_RETAIN 0x00000000U 2965 2966 // Field: [4] C1BEBNEG 2967 // 2968 // Clear event EVT2.C1BEBNEG 2969 // ENUMs: 2970 // CLEAR The bit is 1 2971 // RETAIN The bit is 0 2972 #define LRFDMDM_EVTCLR2_C1BEBNEG 0x00000010U 2973 #define LRFDMDM_EVTCLR2_C1BEBNEG_M 0x00000010U 2974 #define LRFDMDM_EVTCLR2_C1BEBNEG_S 4U 2975 #define LRFDMDM_EVTCLR2_C1BEBNEG_CLEAR 0x00000010U 2976 #define LRFDMDM_EVTCLR2_C1BEBNEG_RETAIN 0x00000000U 2977 2978 // Field: [3] C1BEBPOS 2979 // 2980 // Clear event EVT2.C1BEBPOS 2981 // ENUMs: 2982 // CLEAR The bit is 1 2983 // RETAIN The bit is 0 2984 #define LRFDMDM_EVTCLR2_C1BEBPOS 0x00000008U 2985 #define LRFDMDM_EVTCLR2_C1BEBPOS_M 0x00000008U 2986 #define LRFDMDM_EVTCLR2_C1BEBPOS_S 3U 2987 #define LRFDMDM_EVTCLR2_C1BEBPOS_CLEAR 0x00000008U 2988 #define LRFDMDM_EVTCLR2_C1BEBPOS_RETAIN 0x00000000U 2989 2990 // Field: [2] C1BEAANY 2991 // 2992 // Clear event EVT2.C1BEAANY 2993 // ENUMs: 2994 // CLEAR The bit is 1 2995 // RETAIN The bit is 0 2996 #define LRFDMDM_EVTCLR2_C1BEAANY 0x00000004U 2997 #define LRFDMDM_EVTCLR2_C1BEAANY_M 0x00000004U 2998 #define LRFDMDM_EVTCLR2_C1BEAANY_S 2U 2999 #define LRFDMDM_EVTCLR2_C1BEAANY_CLEAR 0x00000004U 3000 #define LRFDMDM_EVTCLR2_C1BEAANY_RETAIN 0x00000000U 3001 3002 // Field: [1] C1BEANEG 3003 // 3004 // Clear event EVT2.C1BEANEG 3005 // ENUMs: 3006 // CLEAR The bit is 1 3007 // RETAIN The bit is 0 3008 #define LRFDMDM_EVTCLR2_C1BEANEG 0x00000002U 3009 #define LRFDMDM_EVTCLR2_C1BEANEG_M 0x00000002U 3010 #define LRFDMDM_EVTCLR2_C1BEANEG_S 1U 3011 #define LRFDMDM_EVTCLR2_C1BEANEG_CLEAR 0x00000002U 3012 #define LRFDMDM_EVTCLR2_C1BEANEG_RETAIN 0x00000000U 3013 3014 // Field: [0] C1BEAPOS 3015 // 3016 // Clear event EVT2.C1BEAPOS 3017 // ENUMs: 3018 // CLEAR The bit is 1 3019 // RETAIN The bit is 0 3020 #define LRFDMDM_EVTCLR2_C1BEAPOS 0x00000001U 3021 #define LRFDMDM_EVTCLR2_C1BEAPOS_M 0x00000001U 3022 #define LRFDMDM_EVTCLR2_C1BEAPOS_S 0U 3023 #define LRFDMDM_EVTCLR2_C1BEAPOS_CLEAR 0x00000001U 3024 #define LRFDMDM_EVTCLR2_C1BEAPOS_RETAIN 0x00000000U 3025 3026 //***************************************************************************** 3027 // 3028 // Register: LRFDMDM_O_PDREQ 3029 // 3030 //***************************************************************************** 3031 // Field: [0] TOPSMPDREQ 3032 // 3033 // Requests power-down for TOPsm core. If the TOPsm has an ongoing memory 3034 // access, the hardware will safely gate the clock after the transaction has 3035 // completed. 3036 // ENUMs: 3037 // ON The bit is 1 3038 // OFF The bit is 0 3039 #define LRFDMDM_PDREQ_TOPSMPDREQ 0x00000001U 3040 #define LRFDMDM_PDREQ_TOPSMPDREQ_M 0x00000001U 3041 #define LRFDMDM_PDREQ_TOPSMPDREQ_S 0U 3042 #define LRFDMDM_PDREQ_TOPSMPDREQ_ON 0x00000001U 3043 #define LRFDMDM_PDREQ_TOPSMPDREQ_OFF 0x00000000U 3044 3045 //***************************************************************************** 3046 // 3047 // Register: LRFDMDM_O_API 3048 // 3049 //***************************************************************************** 3050 // Field: [7:4] PROTOCOLID 3051 // 3052 // Protocol ID 3053 // ENUMs: 3054 // ALLONES All the bits are 1 3055 // ALLZEROS All the bits are 0 3056 #define LRFDMDM_API_PROTOCOLID_W 4U 3057 #define LRFDMDM_API_PROTOCOLID_M 0x000000F0U 3058 #define LRFDMDM_API_PROTOCOLID_S 4U 3059 #define LRFDMDM_API_PROTOCOLID_ALLONES 0x000000F0U 3060 #define LRFDMDM_API_PROTOCOLID_ALLZEROS 0x00000000U 3061 3062 // Field: [3:0] MDMCMD 3063 // 3064 // Modem command 3065 // ENUMs: 3066 // ALLONES All the bits are 1 3067 // ALLZEROS All bits are 0 3068 #define LRFDMDM_API_MDMCMD_W 4U 3069 #define LRFDMDM_API_MDMCMD_M 0x0000000FU 3070 #define LRFDMDM_API_MDMCMD_S 0U 3071 #define LRFDMDM_API_MDMCMD_ALLONES 0x0000000FU 3072 #define LRFDMDM_API_MDMCMD_ALLZEROS 0x00000000U 3073 3074 //***************************************************************************** 3075 // 3076 // Register: LRFDMDM_O_CMDPAR0 3077 // 3078 //***************************************************************************** 3079 // Field: [15:0] VAL 3080 // 3081 // Parameter 0, software defined function 3082 // ENUMs: 3083 // ALLONES All the bits are 1 3084 // ALLZEROS All the bits are 0 3085 #define LRFDMDM_CMDPAR0_VAL_W 16U 3086 #define LRFDMDM_CMDPAR0_VAL_M 0x0000FFFFU 3087 #define LRFDMDM_CMDPAR0_VAL_S 0U 3088 #define LRFDMDM_CMDPAR0_VAL_ALLONES 0x0000FFFFU 3089 #define LRFDMDM_CMDPAR0_VAL_ALLZEROS 0x00000000U 3090 3091 //***************************************************************************** 3092 // 3093 // Register: LRFDMDM_O_CMDPAR1 3094 // 3095 //***************************************************************************** 3096 // Field: [15:0] VAL 3097 // 3098 // Parameter 1, software defined function 3099 // ENUMs: 3100 // ALLONES All the bits are 1 3101 // ALLZEROS All the bits are 0 3102 #define LRFDMDM_CMDPAR1_VAL_W 16U 3103 #define LRFDMDM_CMDPAR1_VAL_M 0x0000FFFFU 3104 #define LRFDMDM_CMDPAR1_VAL_S 0U 3105 #define LRFDMDM_CMDPAR1_VAL_ALLONES 0x0000FFFFU 3106 #define LRFDMDM_CMDPAR1_VAL_ALLZEROS 0x00000000U 3107 3108 //***************************************************************************** 3109 // 3110 // Register: LRFDMDM_O_CMDPAR2 3111 // 3112 //***************************************************************************** 3113 // Field: [15:0] VAL 3114 // 3115 // Parameter 2, software defined function 3116 // ENUMs: 3117 // ALLONES All the bits are 1 3118 // ALLZEROS All the bits are 0 3119 #define LRFDMDM_CMDPAR2_VAL_W 16U 3120 #define LRFDMDM_CMDPAR2_VAL_M 0x0000FFFFU 3121 #define LRFDMDM_CMDPAR2_VAL_S 0U 3122 #define LRFDMDM_CMDPAR2_VAL_ALLONES 0x0000FFFFU 3123 #define LRFDMDM_CMDPAR2_VAL_ALLZEROS 0x00000000U 3124 3125 //***************************************************************************** 3126 // 3127 // Register: LRFDMDM_O_MSGBOX 3128 // 3129 //***************************************************************************** 3130 // Field: [7:0] VAL 3131 // 3132 // Diverse status, error, report bits from MCE. Readable as well in PBE. 3133 // Controlled by software. 3134 // ENUMs: 3135 // ALLONES All the bits are 1 3136 // ALLZEROS All the bits are 0 3137 #define LRFDMDM_MSGBOX_VAL_W 8U 3138 #define LRFDMDM_MSGBOX_VAL_M 0x000000FFU 3139 #define LRFDMDM_MSGBOX_VAL_S 0U 3140 #define LRFDMDM_MSGBOX_VAL_ALLONES 0x000000FFU 3141 #define LRFDMDM_MSGBOX_VAL_ALLZEROS 0x00000000U 3142 3143 //***************************************************************************** 3144 // 3145 // Register: LRFDMDM_O_FREQ 3146 // 3147 //***************************************************************************** 3148 // Field: [15:0] OFFSET 3149 // 3150 // Frequency Offset from MCE, controlled by software 3151 // ENUMs: 3152 // ALLONES All the bits are 1 3153 // ALLZEROS All the bits are 0 3154 #define LRFDMDM_FREQ_OFFSET_W 16U 3155 #define LRFDMDM_FREQ_OFFSET_M 0x0000FFFFU 3156 #define LRFDMDM_FREQ_OFFSET_S 0U 3157 #define LRFDMDM_FREQ_OFFSET_ALLONES 0x0000FFFFU 3158 #define LRFDMDM_FREQ_OFFSET_ALLZEROS 0x00000000U 3159 3160 //***************************************************************************** 3161 // 3162 // Register: LRFDMDM_O_FIFOWR 3163 // 3164 //***************************************************************************** 3165 // Field: [15:0] PAYLOADIN 3166 // 3167 // FIFO write port. The actual port size is configurable in FIFOWRCTRL 3168 // ENUMs: 3169 // ALLONES All the bits are 1 3170 // ALLZEROS All the bits are 0 3171 #define LRFDMDM_FIFOWR_PAYLOADIN_W 16U 3172 #define LRFDMDM_FIFOWR_PAYLOADIN_M 0x0000FFFFU 3173 #define LRFDMDM_FIFOWR_PAYLOADIN_S 0U 3174 #define LRFDMDM_FIFOWR_PAYLOADIN_ALLONES 0x0000FFFFU 3175 #define LRFDMDM_FIFOWR_PAYLOADIN_ALLZEROS 0x00000000U 3176 3177 //***************************************************************************** 3178 // 3179 // Register: LRFDMDM_O_FIFORD 3180 // 3181 //***************************************************************************** 3182 // Field: [15:0] PAYLOADOUT 3183 // 3184 // FIFO read port. The actual port size is configurable in FIFORDCTRL 3185 // ENUMs: 3186 // ALLONES All the bits are 1 3187 // ALLZEROS All the bits are 0 3188 #define LRFDMDM_FIFORD_PAYLOADOUT_W 16U 3189 #define LRFDMDM_FIFORD_PAYLOADOUT_M 0x0000FFFFU 3190 #define LRFDMDM_FIFORD_PAYLOADOUT_S 0U 3191 #define LRFDMDM_FIFORD_PAYLOADOUT_ALLONES 0x0000FFFFU 3192 #define LRFDMDM_FIFORD_PAYLOADOUT_ALLZEROS 0x00000000U 3193 3194 //***************************************************************************** 3195 // 3196 // Register: LRFDMDM_O_FIFOWRCTRL 3197 // 3198 //***************************************************************************** 3199 // Field: [5:4] FIFOWRPORT 3200 // 3201 // FIFO write port mapping 3202 // ENUMs: 3203 // PBE PBE has write access 3204 // MODEM Modem has write access 3205 // MDMFIFOWR The FIFOWR register is used for write access 3206 #define LRFDMDM_FIFOWRCTRL_FIFOWRPORT_W 2U 3207 #define LRFDMDM_FIFOWRCTRL_FIFOWRPORT_M 0x00000030U 3208 #define LRFDMDM_FIFOWRCTRL_FIFOWRPORT_S 4U 3209 #define LRFDMDM_FIFOWRCTRL_FIFOWRPORT_PBE 0x00000020U 3210 #define LRFDMDM_FIFOWRCTRL_FIFOWRPORT_MODEM 0x00000010U 3211 #define LRFDMDM_FIFOWRCTRL_FIFOWRPORT_MDMFIFOWR 0x00000000U 3212 3213 // Field: [3:0] WORDSZWR 3214 // 3215 // Actual bits in every word write access 3216 // ENUMs: 3217 // BITS16 16 bits 3218 // BITS15 15 bits 3219 // BITS14 14 bits 3220 // BITS13 13 bits 3221 // BITS12 12 bits 3222 // BITS11 11 bits 3223 // BITS10 10 bits 3224 // BITS9 9 bits 3225 // BITS8 8 bits 3226 // BITS7 7 bits 3227 // BITS6 6 bits 3228 // BITS5 5 bits 3229 // BITS4 4 bits 3230 // BITS3 3 bits 3231 // BITS2 2 bits 3232 // BITS1 1 bit 3233 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_W 4U 3234 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_M 0x0000000FU 3235 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_S 0U 3236 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS16 0x0000000FU 3237 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS15 0x0000000EU 3238 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS14 0x0000000DU 3239 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS13 0x0000000CU 3240 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS12 0x0000000BU 3241 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS11 0x0000000AU 3242 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS10 0x00000009U 3243 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS9 0x00000008U 3244 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS8 0x00000007U 3245 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS7 0x00000006U 3246 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS6 0x00000005U 3247 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS5 0x00000004U 3248 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS4 0x00000003U 3249 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS3 0x00000002U 3250 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS2 0x00000001U 3251 #define LRFDMDM_FIFOWRCTRL_WORDSZWR_BITS1 0x00000000U 3252 3253 //***************************************************************************** 3254 // 3255 // Register: LRFDMDM_O_FIFORDCTRL 3256 // 3257 //***************************************************************************** 3258 // Field: [5:4] FIFORDPORT 3259 // 3260 // FIFO read port mapping 3261 // ENUMs: 3262 // PBE PBE has read access 3263 // MODEM Modem has read access 3264 // MDMFIFORD The FIFORD register is used for read access 3265 #define LRFDMDM_FIFORDCTRL_FIFORDPORT_W 2U 3266 #define LRFDMDM_FIFORDCTRL_FIFORDPORT_M 0x00000030U 3267 #define LRFDMDM_FIFORDCTRL_FIFORDPORT_S 4U 3268 #define LRFDMDM_FIFORDCTRL_FIFORDPORT_PBE 0x00000020U 3269 #define LRFDMDM_FIFORDCTRL_FIFORDPORT_MODEM 0x00000010U 3270 #define LRFDMDM_FIFORDCTRL_FIFORDPORT_MDMFIFORD 0x00000000U 3271 3272 // Field: [3:0] WORDSZRD 3273 // 3274 // Actual bits in every word read access 3275 // ENUMs: 3276 // BITS16 16 bits 3277 // BITS15 15 bits 3278 // BITS14 14 bits 3279 // BITS13 13 bits 3280 // BITS12 12 bits 3281 // BITS11 11 bits 3282 // BITS10 10 bits 3283 // BITS9 9 bits 3284 // BITS8 8 bits 3285 // BITS7 7 bits 3286 // BITS6 6 bits 3287 // BITS5 5 bits 3288 // BITS4 4 bits 3289 // BITS3 3 bits 3290 // BITS2 2 bits 3291 // BITS1 1 bit 3292 #define LRFDMDM_FIFORDCTRL_WORDSZRD_W 4U 3293 #define LRFDMDM_FIFORDCTRL_WORDSZRD_M 0x0000000FU 3294 #define LRFDMDM_FIFORDCTRL_WORDSZRD_S 0U 3295 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS16 0x0000000FU 3296 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS15 0x0000000EU 3297 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS14 0x0000000DU 3298 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS13 0x0000000CU 3299 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS12 0x0000000BU 3300 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS11 0x0000000AU 3301 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS10 0x00000009U 3302 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS9 0x00000008U 3303 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS8 0x00000007U 3304 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS7 0x00000006U 3305 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS6 0x00000005U 3306 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS5 0x00000004U 3307 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS4 0x00000003U 3308 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS3 0x00000002U 3309 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS2 0x00000001U 3310 #define LRFDMDM_FIFORDCTRL_WORDSZRD_BITS1 0x00000000U 3311 3312 //***************************************************************************** 3313 // 3314 // Register: LRFDMDM_O_FIFOSTA 3315 // 3316 //***************************************************************************** 3317 // Field: [5] OVERFLOW 3318 // 3319 // FIFO overflow error. If this flag is asserted the modem FIFO must be 3320 // re-initialized with INIT.TXRXFIFO to clear it. Note that re-initializing 3321 // will flush the FIFO. 3322 // ENUMs: 3323 // ONE The bit is 1 3324 // ZERO The bit is 0 3325 #define LRFDMDM_FIFOSTA_OVERFLOW 0x00000020U 3326 #define LRFDMDM_FIFOSTA_OVERFLOW_M 0x00000020U 3327 #define LRFDMDM_FIFOSTA_OVERFLOW_S 5U 3328 #define LRFDMDM_FIFOSTA_OVERFLOW_ONE 0x00000020U 3329 #define LRFDMDM_FIFOSTA_OVERFLOW_ZERO 0x00000000U 3330 3331 // Field: [4] ALMOSTFULL 3332 // 3333 // FIFO is almost full. Asserts when the FIFO fill level is above the almost 3334 // full threshold. 3335 // ENUMs: 3336 // ONE The bit is 1 3337 // ZERO The bit is 0 3338 #define LRFDMDM_FIFOSTA_ALMOSTFULL 0x00000010U 3339 #define LRFDMDM_FIFOSTA_ALMOSTFULL_M 0x00000010U 3340 #define LRFDMDM_FIFOSTA_ALMOSTFULL_S 4U 3341 #define LRFDMDM_FIFOSTA_ALMOSTFULL_ONE 0x00000010U 3342 #define LRFDMDM_FIFOSTA_ALMOSTFULL_ZERO 0x00000000U 3343 3344 // Field: [3] ALMOSTEMPTY 3345 // 3346 // FIFO is almost empty. Asserts when the FIFO fill level is below the almost 3347 // empty threshold. 3348 // ENUMs: 3349 // ONE The bit is 1 3350 // ZERO The bit is 0 3351 #define LRFDMDM_FIFOSTA_ALMOSTEMPTY 0x00000008U 3352 #define LRFDMDM_FIFOSTA_ALMOSTEMPTY_M 0x00000008U 3353 #define LRFDMDM_FIFOSTA_ALMOSTEMPTY_S 3U 3354 #define LRFDMDM_FIFOSTA_ALMOSTEMPTY_ONE 0x00000008U 3355 #define LRFDMDM_FIFOSTA_ALMOSTEMPTY_ZERO 0x00000000U 3356 3357 // Field: [2] UNDERFLOW 3358 // 3359 // FIFO underflow error. If this flag is asserted the modem FIFO must be 3360 // re-initialized with INIT.TXRXFIFO to clear it. 3361 // ENUMs: 3362 // ONE The bit is 1 3363 // ZERO The bit is 0 3364 #define LRFDMDM_FIFOSTA_UNDERFLOW 0x00000004U 3365 #define LRFDMDM_FIFOSTA_UNDERFLOW_M 0x00000004U 3366 #define LRFDMDM_FIFOSTA_UNDERFLOW_S 2U 3367 #define LRFDMDM_FIFOSTA_UNDERFLOW_ONE 0x00000004U 3368 #define LRFDMDM_FIFOSTA_UNDERFLOW_ZERO 0x00000000U 3369 3370 // Field: [1] RXVALID 3371 // 3372 // A full data word is valid and can be read in FIFORD register read port. 3373 // ENUMs: 3374 // ONE The bit is 1 3375 // ZERO The bit is 0 3376 #define LRFDMDM_FIFOSTA_RXVALID 0x00000002U 3377 #define LRFDMDM_FIFOSTA_RXVALID_M 0x00000002U 3378 #define LRFDMDM_FIFOSTA_RXVALID_S 1U 3379 #define LRFDMDM_FIFOSTA_RXVALID_ONE 0x00000002U 3380 #define LRFDMDM_FIFOSTA_RXVALID_ZERO 0x00000000U 3381 3382 // Field: [0] TXREADY 3383 // 3384 // The FIFOWR register write port is ready to receive a data word. 3385 // ENUMs: 3386 // ONE The bit is 1 3387 // ZERO The bit is 0 3388 #define LRFDMDM_FIFOSTA_TXREADY 0x00000001U 3389 #define LRFDMDM_FIFOSTA_TXREADY_M 0x00000001U 3390 #define LRFDMDM_FIFOSTA_TXREADY_S 0U 3391 #define LRFDMDM_FIFOSTA_TXREADY_ONE 0x00000001U 3392 #define LRFDMDM_FIFOSTA_TXREADY_ZERO 0x00000000U 3393 3394 //***************************************************************************** 3395 // 3396 // Register: LRFDMDM_O_RFEDATOUT0 3397 // 3398 //***************************************************************************** 3399 // Field: [15:0] VAL 3400 // 3401 // Data to send to RFE. Writing to this register will trigger an event in the 3402 // RFE, and the command value written here will be readable in 3403 // LRFDRFE:MCEDATIN0 register. 3404 // ENUMs: 3405 // ALLONES All the bits are 1 3406 // ALLZEROS All the bits are 0 3407 #define LRFDMDM_RFEDATOUT0_VAL_W 16U 3408 #define LRFDMDM_RFEDATOUT0_VAL_M 0x0000FFFFU 3409 #define LRFDMDM_RFEDATOUT0_VAL_S 0U 3410 #define LRFDMDM_RFEDATOUT0_VAL_ALLONES 0x0000FFFFU 3411 #define LRFDMDM_RFEDATOUT0_VAL_ALLZEROS 0x00000000U 3412 3413 //***************************************************************************** 3414 // 3415 // Register: LRFDMDM_O_RFEDATIN0 3416 // 3417 //***************************************************************************** 3418 // Field: [15:0] VAL 3419 // 3420 // Data received from RFE 3421 // ENUMs: 3422 // ALLONES All the bits are 1 3423 // ALLZEROS All the bits are 0 3424 #define LRFDMDM_RFEDATIN0_VAL_W 16U 3425 #define LRFDMDM_RFEDATIN0_VAL_M 0x0000FFFFU 3426 #define LRFDMDM_RFEDATIN0_VAL_S 0U 3427 #define LRFDMDM_RFEDATIN0_VAL_ALLONES 0x0000FFFFU 3428 #define LRFDMDM_RFEDATIN0_VAL_ALLZEROS 0x00000000U 3429 3430 //***************************************************************************** 3431 // 3432 // Register: LRFDMDM_O_RFECMDOUT 3433 // 3434 //***************************************************************************** 3435 // Field: [3:0] VAL 3436 // 3437 // Command to send to RFE. Writing to this register will trigger an event in 3438 // the RFE, and the command value written here will be readable in 3439 // LRFDRFE:MCECMDIN register. 3440 // ENUMs: 3441 // ALLONES All the bits are 1 3442 // ALLZEROS All the bits are 0 3443 #define LRFDMDM_RFECMDOUT_VAL_W 4U 3444 #define LRFDMDM_RFECMDOUT_VAL_M 0x0000000FU 3445 #define LRFDMDM_RFECMDOUT_VAL_S 0U 3446 #define LRFDMDM_RFECMDOUT_VAL_ALLONES 0x0000000FU 3447 #define LRFDMDM_RFECMDOUT_VAL_ALLZEROS 0x00000000U 3448 3449 //***************************************************************************** 3450 // 3451 // Register: LRFDMDM_O_RFECMDIN 3452 // 3453 //***************************************************************************** 3454 // Field: [3:0] VAL 3455 // 3456 // Command received from RFE 3457 // ENUMs: 3458 // ALLONES All the bits are 1 3459 // ALLZEROS All the bits are 0 3460 #define LRFDMDM_RFECMDIN_VAL_W 4U 3461 #define LRFDMDM_RFECMDIN_VAL_M 0x0000000FU 3462 #define LRFDMDM_RFECMDIN_VAL_S 0U 3463 #define LRFDMDM_RFECMDIN_VAL_ALLONES 0x0000000FU 3464 #define LRFDMDM_RFECMDIN_VAL_ALLZEROS 0x00000000U 3465 3466 //***************************************************************************** 3467 // 3468 // Register: LRFDMDM_O_PBEDATOUT0 3469 // 3470 //***************************************************************************** 3471 // Field: [15:0] VAL 3472 // 3473 // Data to send to PBE. Writing to this register will trigger an event in the 3474 // PBE, and the command value written here will be readable in 3475 // LRFDPBE:MCEDATIN0 register. 3476 // ENUMs: 3477 // ALLONES All the bits are 1 3478 // ALLZEROS All the bits are 0 3479 #define LRFDMDM_PBEDATOUT0_VAL_W 16U 3480 #define LRFDMDM_PBEDATOUT0_VAL_M 0x0000FFFFU 3481 #define LRFDMDM_PBEDATOUT0_VAL_S 0U 3482 #define LRFDMDM_PBEDATOUT0_VAL_ALLONES 0x0000FFFFU 3483 #define LRFDMDM_PBEDATOUT0_VAL_ALLZEROS 0x00000000U 3484 3485 //***************************************************************************** 3486 // 3487 // Register: LRFDMDM_O_PBEDATIN0 3488 // 3489 //***************************************************************************** 3490 // Field: [15:0] VAL 3491 // 3492 // Data received from PBE 3493 // ENUMs: 3494 // ALLONES All the bits are 1 3495 // ALLZEROS All the bits are 0 3496 #define LRFDMDM_PBEDATIN0_VAL_W 16U 3497 #define LRFDMDM_PBEDATIN0_VAL_M 0x0000FFFFU 3498 #define LRFDMDM_PBEDATIN0_VAL_S 0U 3499 #define LRFDMDM_PBEDATIN0_VAL_ALLONES 0x0000FFFFU 3500 #define LRFDMDM_PBEDATIN0_VAL_ALLZEROS 0x00000000U 3501 3502 //***************************************************************************** 3503 // 3504 // Register: LRFDMDM_O_PBECMDOUT 3505 // 3506 //***************************************************************************** 3507 // Field: [3:0] VAL 3508 // 3509 // Command to send to PBE. Writing to this register will trigger an event in 3510 // the PBE, and the command value written here will be readable in 3511 // LRFDPBE:MCECMDIN register. 3512 // ENUMs: 3513 // ALLONES All the bits are 1 3514 // ALLZEROS All the bits are 0 3515 #define LRFDMDM_PBECMDOUT_VAL_W 4U 3516 #define LRFDMDM_PBECMDOUT_VAL_M 0x0000000FU 3517 #define LRFDMDM_PBECMDOUT_VAL_S 0U 3518 #define LRFDMDM_PBECMDOUT_VAL_ALLONES 0x0000000FU 3519 #define LRFDMDM_PBECMDOUT_VAL_ALLZEROS 0x00000000U 3520 3521 //***************************************************************************** 3522 // 3523 // Register: LRFDMDM_O_PBECMDIN 3524 // 3525 //***************************************************************************** 3526 // Field: [3:0] VAL 3527 // 3528 // Command received from PBE 3529 // ENUMs: 3530 // ALLONES All the bits are 1 3531 // ALLZEROS All the bits are 0 3532 #define LRFDMDM_PBECMDIN_VAL_W 4U 3533 #define LRFDMDM_PBECMDIN_VAL_M 0x0000000FU 3534 #define LRFDMDM_PBECMDIN_VAL_S 0U 3535 #define LRFDMDM_PBECMDIN_VAL_ALLONES 0x0000000FU 3536 #define LRFDMDM_PBECMDIN_VAL_ALLZEROS 0x00000000U 3537 3538 //***************************************************************************** 3539 // 3540 // Register: LRFDMDM_O_LQIEST 3541 // 3542 //***************************************************************************** 3543 // Field: [7:0] VAL 3544 // 3545 // LQI Estimate value to PBE 3546 // ENUMs: 3547 // ALLONES All the bits are 1 3548 // ALLZEROS All the bits are 0 3549 #define LRFDMDM_LQIEST_VAL_W 8U 3550 #define LRFDMDM_LQIEST_VAL_M 0x000000FFU 3551 #define LRFDMDM_LQIEST_VAL_S 0U 3552 #define LRFDMDM_LQIEST_VAL_ALLONES 0x000000FFU 3553 #define LRFDMDM_LQIEST_VAL_ALLZEROS 0x00000000U 3554 3555 //***************************************************************************** 3556 // 3557 // Register: LRFDMDM_O_PBEEVTMUX 3558 // 3559 //***************************************************************************** 3560 // Field: [5:0] SEL 3561 // 3562 // Select one internal event and route to the PBE for usage in the event-unit 3563 // there 3564 // ENUMs: 3565 // ALLONES All the bits are 1 3566 // ALLZEROS All the bits are 0 3567 #define LRFDMDM_PBEEVTMUX_SEL_W 6U 3568 #define LRFDMDM_PBEEVTMUX_SEL_M 0x0000003FU 3569 #define LRFDMDM_PBEEVTMUX_SEL_S 0U 3570 #define LRFDMDM_PBEEVTMUX_SEL_ALLONES 0x0000003FU 3571 #define LRFDMDM_PBEEVTMUX_SEL_ALLZEROS 0x00000000U 3572 3573 //***************************************************************************** 3574 // 3575 // Register: LRFDMDM_O_SYSTIMEVTMUX0 3576 // 3577 //***************************************************************************** 3578 // Field: [11:6] SEL1 3579 // 3580 // Selects one source to send to the systimer output event 1 3581 // ENUMs: 3582 // ALLONES All the bits are 1 3583 // ALLZEROS All the bits are 0 3584 #define LRFDMDM_SYSTIMEVTMUX0_SEL1_W 6U 3585 #define LRFDMDM_SYSTIMEVTMUX0_SEL1_M 0x00000FC0U 3586 #define LRFDMDM_SYSTIMEVTMUX0_SEL1_S 6U 3587 #define LRFDMDM_SYSTIMEVTMUX0_SEL1_ALLONES 0x00000FC0U 3588 #define LRFDMDM_SYSTIMEVTMUX0_SEL1_ALLZEROS 0x00000000U 3589 3590 // Field: [5:0] SEL0 3591 // 3592 // Selects one source to send to the systimer output event 0 3593 // ENUMs: 3594 // ALLONES All the bits are 1 3595 // ALLZEROS All the bits are 0 3596 #define LRFDMDM_SYSTIMEVTMUX0_SEL0_W 6U 3597 #define LRFDMDM_SYSTIMEVTMUX0_SEL0_M 0x0000003FU 3598 #define LRFDMDM_SYSTIMEVTMUX0_SEL0_S 0U 3599 #define LRFDMDM_SYSTIMEVTMUX0_SEL0_ALLONES 0x0000003FU 3600 #define LRFDMDM_SYSTIMEVTMUX0_SEL0_ALLZEROS 0x00000000U 3601 3602 //***************************************************************************** 3603 // 3604 // Register: LRFDMDM_O_SYSTIMEVTMUX1 3605 // 3606 //***************************************************************************** 3607 // Field: [5:0] SEL2 3608 // 3609 // Selects one source to send to the systimer output event 2 3610 // ENUMs: 3611 // ALLONES All the bits are 1 3612 // ALLZEROS All the bits are 0 3613 #define LRFDMDM_SYSTIMEVTMUX1_SEL2_W 6U 3614 #define LRFDMDM_SYSTIMEVTMUX1_SEL2_M 0x0000003FU 3615 #define LRFDMDM_SYSTIMEVTMUX1_SEL2_S 0U 3616 #define LRFDMDM_SYSTIMEVTMUX1_SEL2_ALLONES 0x0000003FU 3617 #define LRFDMDM_SYSTIMEVTMUX1_SEL2_ALLZEROS 0x00000000U 3618 3619 //***************************************************************************** 3620 // 3621 // Register: LRFDMDM_O_ADCDIGCONF 3622 // 3623 //***************************************************************************** 3624 // Field: [1] QBRANCHEN 3625 // 3626 // Enables Q component data branch in ADCDIG 3627 // ENUMs: 3628 // ON The bit is 1 3629 // OFF The bit is 0 3630 #define LRFDMDM_ADCDIGCONF_QBRANCHEN 0x00000002U 3631 #define LRFDMDM_ADCDIGCONF_QBRANCHEN_M 0x00000002U 3632 #define LRFDMDM_ADCDIGCONF_QBRANCHEN_S 1U 3633 #define LRFDMDM_ADCDIGCONF_QBRANCHEN_ON 0x00000002U 3634 #define LRFDMDM_ADCDIGCONF_QBRANCHEN_OFF 0x00000000U 3635 3636 // Field: [0] IBRANCHEN 3637 // 3638 // Enables I component data branch in ADCDIG 3639 // ENUMs: 3640 // ON The bit is 1 3641 // OFF The bit is 0 3642 #define LRFDMDM_ADCDIGCONF_IBRANCHEN 0x00000001U 3643 #define LRFDMDM_ADCDIGCONF_IBRANCHEN_M 0x00000001U 3644 #define LRFDMDM_ADCDIGCONF_IBRANCHEN_S 0U 3645 #define LRFDMDM_ADCDIGCONF_IBRANCHEN_ON 0x00000001U 3646 #define LRFDMDM_ADCDIGCONF_IBRANCHEN_OFF 0x00000000U 3647 3648 //***************************************************************************** 3649 // 3650 // Register: LRFDMDM_O_MODPRECTRL 3651 // 3652 //***************************************************************************** 3653 // Field: [7:4] REPS 3654 // 3655 // Number of preamble repetitions of preamble pattern 3656 // ENUMs: 3657 // REPS16 16 repetitions 3658 // REPS15 15 repetitions 3659 // REPS14 14 repetitions 3660 // REPS13 13 repetitions 3661 // REPS12 12 repetitions 3662 // REPS11 11 repetitions 3663 // REPS10 10 repetitions 3664 // REPS9 9 repetitions 3665 // REPS8 8 repetitions 3666 // REPS7 7 repetitions 3667 // REPS6 6 repetitions 3668 // REPS5 5 repetitions 3669 // REPS4 4 repetitions 3670 // REPS3 3 repetitions 3671 // REPS2 2 repetitions 3672 // REPS1 1 repetition (i.e. only once) 3673 #define LRFDMDM_MODPRECTRL_REPS_W 4U 3674 #define LRFDMDM_MODPRECTRL_REPS_M 0x000000F0U 3675 #define LRFDMDM_MODPRECTRL_REPS_S 4U 3676 #define LRFDMDM_MODPRECTRL_REPS_REPS16 0x000000F0U 3677 #define LRFDMDM_MODPRECTRL_REPS_REPS15 0x000000E0U 3678 #define LRFDMDM_MODPRECTRL_REPS_REPS14 0x000000D0U 3679 #define LRFDMDM_MODPRECTRL_REPS_REPS13 0x000000C0U 3680 #define LRFDMDM_MODPRECTRL_REPS_REPS12 0x000000B0U 3681 #define LRFDMDM_MODPRECTRL_REPS_REPS11 0x000000A0U 3682 #define LRFDMDM_MODPRECTRL_REPS_REPS10 0x00000090U 3683 #define LRFDMDM_MODPRECTRL_REPS_REPS9 0x00000080U 3684 #define LRFDMDM_MODPRECTRL_REPS_REPS8 0x00000070U 3685 #define LRFDMDM_MODPRECTRL_REPS_REPS7 0x00000060U 3686 #define LRFDMDM_MODPRECTRL_REPS_REPS6 0x00000050U 3687 #define LRFDMDM_MODPRECTRL_REPS_REPS5 0x00000040U 3688 #define LRFDMDM_MODPRECTRL_REPS_REPS4 0x00000030U 3689 #define LRFDMDM_MODPRECTRL_REPS_REPS3 0x00000020U 3690 #define LRFDMDM_MODPRECTRL_REPS_REPS2 0x00000010U 3691 #define LRFDMDM_MODPRECTRL_REPS_REPS1 0x00000000U 3692 3693 // Field: [3:0] SIZE 3694 // 3695 // Preamble pattern size in bits 3696 // ENUMs: 3697 // BITS16 16 bits 3698 // BITS8 8 bits 3699 // BITS4 4 bits 3700 #define LRFDMDM_MODPRECTRL_SIZE_W 4U 3701 #define LRFDMDM_MODPRECTRL_SIZE_M 0x0000000FU 3702 #define LRFDMDM_MODPRECTRL_SIZE_S 0U 3703 #define LRFDMDM_MODPRECTRL_SIZE_BITS16 0x0000000FU 3704 #define LRFDMDM_MODPRECTRL_SIZE_BITS8 0x00000007U 3705 #define LRFDMDM_MODPRECTRL_SIZE_BITS4 0x00000003U 3706 3707 //***************************************************************************** 3708 // 3709 // Register: LRFDMDM_O_MODSYMMAP0 3710 // 3711 //***************************************************************************** 3712 // Field: [15:12] SYM3 3713 // 3714 // Decimal value for bits '11' 3715 // ENUMs: 3716 // ALLONES All the bits are 1 3717 // ALLZEROS All the bits are 0 3718 #define LRFDMDM_MODSYMMAP0_SYM3_W 4U 3719 #define LRFDMDM_MODSYMMAP0_SYM3_M 0x0000F000U 3720 #define LRFDMDM_MODSYMMAP0_SYM3_S 12U 3721 #define LRFDMDM_MODSYMMAP0_SYM3_ALLONES 0x0000F000U 3722 #define LRFDMDM_MODSYMMAP0_SYM3_ALLZEROS 0x00000000U 3723 3724 // Field: [11:8] SYM2 3725 // 3726 // Decimal value for bits '10' 3727 // ENUMs: 3728 // ALLONES All the bits are 1 3729 // ALLZEROS All the bits are 0 3730 #define LRFDMDM_MODSYMMAP0_SYM2_W 4U 3731 #define LRFDMDM_MODSYMMAP0_SYM2_M 0x00000F00U 3732 #define LRFDMDM_MODSYMMAP0_SYM2_S 8U 3733 #define LRFDMDM_MODSYMMAP0_SYM2_ALLONES 0x00000F00U 3734 #define LRFDMDM_MODSYMMAP0_SYM2_ALLZEROS 0x00000000U 3735 3736 // Field: [7:4] SYM1 3737 // 3738 // Decimal value for bit '1' 3739 // ENUMs: 3740 // ALLONES All the bits are 1 3741 // ALLZEROS All the bits are 0 3742 #define LRFDMDM_MODSYMMAP0_SYM1_W 4U 3743 #define LRFDMDM_MODSYMMAP0_SYM1_M 0x000000F0U 3744 #define LRFDMDM_MODSYMMAP0_SYM1_S 4U 3745 #define LRFDMDM_MODSYMMAP0_SYM1_ALLONES 0x000000F0U 3746 #define LRFDMDM_MODSYMMAP0_SYM1_ALLZEROS 0x00000000U 3747 3748 // Field: [3:0] SYM0 3749 // 3750 // Decimal value for bit '0' 3751 // ENUMs: 3752 // ALLONES All the bits are 1 3753 // ALLZEROS All the bits are 0 3754 #define LRFDMDM_MODSYMMAP0_SYM0_W 4U 3755 #define LRFDMDM_MODSYMMAP0_SYM0_M 0x0000000FU 3756 #define LRFDMDM_MODSYMMAP0_SYM0_S 0U 3757 #define LRFDMDM_MODSYMMAP0_SYM0_ALLONES 0x0000000FU 3758 #define LRFDMDM_MODSYMMAP0_SYM0_ALLZEROS 0x00000000U 3759 3760 //***************************************************************************** 3761 // 3762 // Register: LRFDMDM_O_MODSYMMAP1 3763 // 3764 //***************************************************************************** 3765 // Field: [15:12] SYM7 3766 // 3767 // Decimal value for bits '111' 3768 // ENUMs: 3769 // ALLONES All the bits are 1 3770 // ALLZEROS All the bits are 0 3771 #define LRFDMDM_MODSYMMAP1_SYM7_W 4U 3772 #define LRFDMDM_MODSYMMAP1_SYM7_M 0x0000F000U 3773 #define LRFDMDM_MODSYMMAP1_SYM7_S 12U 3774 #define LRFDMDM_MODSYMMAP1_SYM7_ALLONES 0x0000F000U 3775 #define LRFDMDM_MODSYMMAP1_SYM7_ALLZEROS 0x00000000U 3776 3777 // Field: [11:8] SYM6 3778 // 3779 // Decimal value for bits '110' 3780 // ENUMs: 3781 // ALLONES All the bits are 1 3782 // ALLZEROS All the bits are 0 3783 #define LRFDMDM_MODSYMMAP1_SYM6_W 4U 3784 #define LRFDMDM_MODSYMMAP1_SYM6_M 0x00000F00U 3785 #define LRFDMDM_MODSYMMAP1_SYM6_S 8U 3786 #define LRFDMDM_MODSYMMAP1_SYM6_ALLONES 0x00000F00U 3787 #define LRFDMDM_MODSYMMAP1_SYM6_ALLZEROS 0x00000000U 3788 3789 // Field: [7:4] SYM5 3790 // 3791 // Decimal value for bits '101' 3792 // ENUMs: 3793 // ALLONES All the bits are 1 3794 // ALLZEROS All the bits are 0 3795 #define LRFDMDM_MODSYMMAP1_SYM5_W 4U 3796 #define LRFDMDM_MODSYMMAP1_SYM5_M 0x000000F0U 3797 #define LRFDMDM_MODSYMMAP1_SYM5_S 4U 3798 #define LRFDMDM_MODSYMMAP1_SYM5_ALLONES 0x000000F0U 3799 #define LRFDMDM_MODSYMMAP1_SYM5_ALLZEROS 0x00000000U 3800 3801 // Field: [3:0] SYM4 3802 // 3803 // Decimal value for bits '100' 3804 // ENUMs: 3805 // ALLONES All the bits are 1 3806 // ALLZEROS All the bits are 0 3807 #define LRFDMDM_MODSYMMAP1_SYM4_W 4U 3808 #define LRFDMDM_MODSYMMAP1_SYM4_M 0x0000000FU 3809 #define LRFDMDM_MODSYMMAP1_SYM4_S 0U 3810 #define LRFDMDM_MODSYMMAP1_SYM4_ALLONES 0x0000000FU 3811 #define LRFDMDM_MODSYMMAP1_SYM4_ALLZEROS 0x00000000U 3812 3813 //***************************************************************************** 3814 // 3815 // Register: LRFDMDM_O_MODSOFTTX 3816 // 3817 //***************************************************************************** 3818 // Field: [3:0] SOFTSYMBOL 3819 // 3820 // Soft symbol {-7..+7} used when MODCTRL.SOFTTXENABLE is enabled. 3821 // ENUMs: 3822 // ALLONES All the bits are 1 3823 // ALLZEROS All the bits are 0 3824 #define LRFDMDM_MODSOFTTX_SOFTSYMBOL_W 4U 3825 #define LRFDMDM_MODSOFTTX_SOFTSYMBOL_M 0x0000000FU 3826 #define LRFDMDM_MODSOFTTX_SOFTSYMBOL_S 0U 3827 #define LRFDMDM_MODSOFTTX_SOFTSYMBOL_ALLONES 0x0000000FU 3828 #define LRFDMDM_MODSOFTTX_SOFTSYMBOL_ALLZEROS 0x00000000U 3829 3830 //***************************************************************************** 3831 // 3832 // Register: LRFDMDM_O_BAUD 3833 // 3834 //***************************************************************************** 3835 // Field: [15:0] RATEWORD 3836 // 3837 // Rate word (bits [20:5]). The 5 LSBs of the 21-bit rate word are defined in 3838 // BAUDPRE.EXTRATEWORD register. 3839 // ENUMs: 3840 // ALLONES All the bits are 1 3841 // ALLZEROS All the bits are 0 3842 #define LRFDMDM_BAUD_RATEWORD_W 16U 3843 #define LRFDMDM_BAUD_RATEWORD_M 0x0000FFFFU 3844 #define LRFDMDM_BAUD_RATEWORD_S 0U 3845 #define LRFDMDM_BAUD_RATEWORD_ALLONES 0x0000FFFFU 3846 #define LRFDMDM_BAUD_RATEWORD_ALLZEROS 0x00000000U 3847 3848 //***************************************************************************** 3849 // 3850 // Register: LRFDMDM_O_BAUDPRE 3851 // 3852 //***************************************************************************** 3853 // Field: [15:13] ALIGNVALUE 3854 // 3855 // Align value for timebase after sync 3856 // ENUMs: 3857 // ALLONES All the bits are 1 3858 // ALLZEROS All the bits are 0 3859 #define LRFDMDM_BAUDPRE_ALIGNVALUE_W 3U 3860 #define LRFDMDM_BAUDPRE_ALIGNVALUE_M 0x0000E000U 3861 #define LRFDMDM_BAUDPRE_ALIGNVALUE_S 13U 3862 #define LRFDMDM_BAUDPRE_ALIGNVALUE_ALLONES 0x0000E000U 3863 #define LRFDMDM_BAUDPRE_ALIGNVALUE_ALLZEROS 0x00000000U 3864 3865 // Field: [12:8] EXTRATEWORD 3866 // 3867 // Extended Rate Word (bits [4:0]). These are the 5 LSBs extending the 16 MSBs 3868 // configured in BAUD.RATEWORD to form a 21 bit rate word. 3869 // ENUMs: 3870 // ALLONES All the bits are 1 3871 // ALLZEROS All the bits are 0 3872 #define LRFDMDM_BAUDPRE_EXTRATEWORD_W 5U 3873 #define LRFDMDM_BAUDPRE_EXTRATEWORD_M 0x00001F00U 3874 #define LRFDMDM_BAUDPRE_EXTRATEWORD_S 8U 3875 #define LRFDMDM_BAUDPRE_EXTRATEWORD_ALLONES 0x00001F00U 3876 #define LRFDMDM_BAUDPRE_EXTRATEWORD_ALLZEROS 0x00000000U 3877 3878 // Field: [7:0] PRESCALER 3879 // 3880 // Prescaler value, range 1 to 255 3881 // ENUMs: 3882 // ALLONES All the bits are 1 3883 // ALLZEROS All the bits are 0 3884 #define LRFDMDM_BAUDPRE_PRESCALER_W 8U 3885 #define LRFDMDM_BAUDPRE_PRESCALER_M 0x000000FFU 3886 #define LRFDMDM_BAUDPRE_PRESCALER_S 0U 3887 #define LRFDMDM_BAUDPRE_PRESCALER_ALLONES 0x000000FFU 3888 #define LRFDMDM_BAUDPRE_PRESCALER_ALLZEROS 0x00000000U 3889 3890 //***************************************************************************** 3891 // 3892 // Register: LRFDMDM_O_MODMAIN 3893 // 3894 //***************************************************************************** 3895 // Field: [3:2] FECSELECT 3896 // 3897 // Forward Error Correction Selection. Used for some signal-wiring in modulator 3898 // and demodulator. 3899 // ENUMs: 3900 // BLR Bluetooth LE coded long range compatible FEC 3901 // RESERVED Reserved 3902 // IEEE15_4 IEEE 802.15.4 3903 // NOSEL No FEC encoding selected 3904 #define LRFDMDM_MODMAIN_FECSELECT_W 2U 3905 #define LRFDMDM_MODMAIN_FECSELECT_M 0x0000000CU 3906 #define LRFDMDM_MODMAIN_FECSELECT_S 2U 3907 #define LRFDMDM_MODMAIN_FECSELECT_BLR 0x0000000CU 3908 #define LRFDMDM_MODMAIN_FECSELECT_RESERVED 0x00000008U 3909 #define LRFDMDM_MODMAIN_FECSELECT_IEEE15_4 0x00000004U 3910 #define LRFDMDM_MODMAIN_FECSELECT_NOSEL 0x00000000U 3911 3912 // Field: [1:0] MODLEVELS 3913 // 3914 // Number of modulation levels 3915 // ENUMs: 3916 // LVL8 8 levels 3917 // LVL4 4 levels 3918 // LVL2 2 levels 3919 #define LRFDMDM_MODMAIN_MODLEVELS_W 2U 3920 #define LRFDMDM_MODMAIN_MODLEVELS_M 0x00000003U 3921 #define LRFDMDM_MODMAIN_MODLEVELS_S 0U 3922 #define LRFDMDM_MODMAIN_MODLEVELS_LVL8 0x00000002U 3923 #define LRFDMDM_MODMAIN_MODLEVELS_LVL4 0x00000001U 3924 #define LRFDMDM_MODMAIN_MODLEVELS_LVL2 0x00000000U 3925 3926 //***************************************************************************** 3927 // 3928 // Register: LRFDMDM_O_DEMMISC0 3929 // 3930 //***************************************************************************** 3931 // Field: [9:0] CMIXN 3932 // 3933 // Signed factor of mixer phasor, Fmix=n*Fs/1024 , where n in range [-512, 511] 3934 // ENUMs: 3935 // ALLONES All the bits are 1 3936 // ALLZEROS All the bits are 0 3937 #define LRFDMDM_DEMMISC0_CMIXN_W 10U 3938 #define LRFDMDM_DEMMISC0_CMIXN_M 0x000003FFU 3939 #define LRFDMDM_DEMMISC0_CMIXN_S 0U 3940 #define LRFDMDM_DEMMISC0_CMIXN_ALLONES 0x000003FFU 3941 #define LRFDMDM_DEMMISC0_CMIXN_ALLZEROS 0x00000000U 3942 3943 //***************************************************************************** 3944 // 3945 // Register: LRFDMDM_O_DEMMISC1 3946 // 3947 //***************************************************************************** 3948 // Field: [12:8] CDCTGAINMA 3949 // 3950 // Gives the gain mantissa of the CDC P/Q tracker 3951 // ENUMs: 3952 // ALLONES Maximum gain mantissa. 3953 // ALLZEROS When CDCTGAINMA is set to zero, the tracker loop 3954 // is disabled. 3955 #define LRFDMDM_DEMMISC1_CDCTGAINMA_W 5U 3956 #define LRFDMDM_DEMMISC1_CDCTGAINMA_M 0x00001F00U 3957 #define LRFDMDM_DEMMISC1_CDCTGAINMA_S 8U 3958 #define LRFDMDM_DEMMISC1_CDCTGAINMA_ALLONES 0x00001F00U 3959 #define LRFDMDM_DEMMISC1_CDCTGAINMA_ALLZEROS 0x00000000U 3960 3961 // Field: [7:5] CDCTGAINEX 3962 // 3963 // Gives the gain exponent of the CDC P/Q tracker 3964 // ENUMs: 3965 // ALLONES When CDCTGAINEX is set to all zeroes, the 3966 // CDCGAINMA multiplier is 512 3967 // ALLZEROS When CDCTGAINEX is set to all zeroes, the 3968 // CDCGAINMA multiplier is 4 3969 #define LRFDMDM_DEMMISC1_CDCTGAINEX_W 3U 3970 #define LRFDMDM_DEMMISC1_CDCTGAINEX_M 0x000000E0U 3971 #define LRFDMDM_DEMMISC1_CDCTGAINEX_S 5U 3972 #define LRFDMDM_DEMMISC1_CDCTGAINEX_ALLONES 0x000000E0U 3973 #define LRFDMDM_DEMMISC1_CDCTGAINEX_ALLZEROS 0x00000000U 3974 3975 // Field: [4] CDCCOLRST 3976 // 3977 // Collision restart for CDC FIFO 3978 // ENUMs: 3979 // EN Enable collision detect and restart feature 3980 // DIS Do not enable collision detect and restart feature 3981 #define LRFDMDM_DEMMISC1_CDCCOLRST 0x00000010U 3982 #define LRFDMDM_DEMMISC1_CDCCOLRST_M 0x00000010U 3983 #define LRFDMDM_DEMMISC1_CDCCOLRST_S 4U 3984 #define LRFDMDM_DEMMISC1_CDCCOLRST_EN 0x00000010U 3985 #define LRFDMDM_DEMMISC1_CDCCOLRST_DIS 0x00000000U 3986 3987 // Field: [3:2] MGE1SRCSEL 3988 // 3989 // Source select magnitude estimator 1 3990 // ENUMs: 3991 // CHFI Output of CHFI 3992 // FEXB1 Output of the FEXB, as selected by 3993 // DEMFEXB0.OUT2SRCSEL register 3994 // FIDC Output of the FIDC (x4 samples) 3995 #define LRFDMDM_DEMMISC1_MGE1SRCSEL_W 2U 3996 #define LRFDMDM_DEMMISC1_MGE1SRCSEL_M 0x0000000CU 3997 #define LRFDMDM_DEMMISC1_MGE1SRCSEL_S 2U 3998 #define LRFDMDM_DEMMISC1_MGE1SRCSEL_CHFI 0x00000008U 3999 #define LRFDMDM_DEMMISC1_MGE1SRCSEL_FEXB1 0x00000004U 4000 #define LRFDMDM_DEMMISC1_MGE1SRCSEL_FIDC 0x00000000U 4001 4002 // Field: [1:0] CHFIBW 4003 // 4004 // Select bandwidth (cut-off frequency) of demodulator channel filter 4005 // ENUMs: 4006 // BW0_29 0.29 * Fs. Using FIR filter with taps [2 3 1 -8 4007 // -18 -14 17 72 126 149 126 72 17 -14 -18 -8 1 3 4008 // 2]. 4009 // BW0_41667 0.41667 * Fs. Using FIR filter with taps [-1 -4 2 4010 // 12 4 -25 -31 38 154 213 154 38 -31 -25 4 12 2 4011 // -4 -1]. 4012 // BW0_3333 0.33333 * Fs. Using FIR filter with taps [0 4 6 0 4013 // -16 -25 0 65 138 170 138 65 0 -25 -16 0 6 4 0]. 4014 // BW0_5 0.5 * Fs. Using FIR filter with taps [3 0 -9 0 20 4015 // 0 -46 0 160 256 160 0 -46 0 20 0 -9 0 3]. 4016 #define LRFDMDM_DEMMISC1_CHFIBW_W 2U 4017 #define LRFDMDM_DEMMISC1_CHFIBW_M 0x00000003U 4018 #define LRFDMDM_DEMMISC1_CHFIBW_S 0U 4019 #define LRFDMDM_DEMMISC1_CHFIBW_BW0_29 0x00000003U 4020 #define LRFDMDM_DEMMISC1_CHFIBW_BW0_41667 0x00000002U 4021 #define LRFDMDM_DEMMISC1_CHFIBW_BW0_3333 0x00000001U 4022 #define LRFDMDM_DEMMISC1_CHFIBW_BW0_5 0x00000000U 4023 4024 //***************************************************************************** 4025 // 4026 // Register: LRFDMDM_O_DEMMISC2 4027 // 4028 //***************************************************************************** 4029 // Field: [14] MLSERUN 4030 // 4031 // Enable maximum likelihood sequence estimation (MLSE) desicions 4032 // ENUMs: 4033 // EN The bit is 1 4034 // DIS The bit is 0 4035 #define LRFDMDM_DEMMISC2_MLSERUN 0x00004000U 4036 #define LRFDMDM_DEMMISC2_MLSERUN_M 0x00004000U 4037 #define LRFDMDM_DEMMISC2_MLSERUN_S 14U 4038 #define LRFDMDM_DEMMISC2_MLSERUN_EN 0x00004000U 4039 #define LRFDMDM_DEMMISC2_MLSERUN_DIS 0x00000000U 4040 4041 // Field: [13:12] MAFCGAIN 4042 // 4043 // Set gain in MAFC. Multiplies symbols with 2^N before symbol recovery stage 4044 // ENUMs: 4045 // ALLONES All the bits are 1 4046 // ALLZEROS All the bits are 0 4047 #define LRFDMDM_DEMMISC2_MAFCGAIN_W 2U 4048 #define LRFDMDM_DEMMISC2_MAFCGAIN_M 0x00003000U 4049 #define LRFDMDM_DEMMISC2_MAFCGAIN_S 12U 4050 #define LRFDMDM_DEMMISC2_MAFCGAIN_ALLONES 0x00003000U 4051 #define LRFDMDM_DEMMISC2_MAFCGAIN_ALLZEROS 0x00000000U 4052 4053 // Field: [11] STIMBYPASS 4054 // 4055 // Use to bypass STIM estimator 4056 // ENUMs: 4057 // EN Perform estimation only (no timing correction) 4058 // DIS Perform both estimation and correct timing 4059 #define LRFDMDM_DEMMISC2_STIMBYPASS 0x00000800U 4060 #define LRFDMDM_DEMMISC2_STIMBYPASS_M 0x00000800U 4061 #define LRFDMDM_DEMMISC2_STIMBYPASS_S 11U 4062 #define LRFDMDM_DEMMISC2_STIMBYPASS_EN 0x00000800U 4063 #define LRFDMDM_DEMMISC2_STIMBYPASS_DIS 0x00000000U 4064 4065 // Field: [10] STIMESTONLY 4066 // 4067 // Only perform symbol timing error estimation in STIM, without doing timing 4068 // correction 4069 // ENUMs: 4070 // EN Perform estimation only (no timing correction) 4071 // DIS Perform both estimation and correct timing 4072 #define LRFDMDM_DEMMISC2_STIMESTONLY 0x00000400U 4073 #define LRFDMDM_DEMMISC2_STIMESTONLY_M 0x00000400U 4074 #define LRFDMDM_DEMMISC2_STIMESTONLY_S 10U 4075 #define LRFDMDM_DEMMISC2_STIMESTONLY_EN 0x00000400U 4076 #define LRFDMDM_DEMMISC2_STIMESTONLY_DIS 0x00000000U 4077 4078 // Field: [9:7] STIMTEAPERIOD 4079 // 4080 // Symbol timing error accumulator period (4 to 128 symbols) in STIM 4081 // ENUMs: 4082 // SYM128 128 symbols 4083 // SYM64 64 symbols 4084 // SYM32 32 symbols 4085 // SYM16 16 symbols 4086 // SYM8 8 symbols 4087 // SYM4 4 symbols 4088 #define LRFDMDM_DEMMISC2_STIMTEAPERIOD_W 3U 4089 #define LRFDMDM_DEMMISC2_STIMTEAPERIOD_M 0x00000380U 4090 #define LRFDMDM_DEMMISC2_STIMTEAPERIOD_S 7U 4091 #define LRFDMDM_DEMMISC2_STIMTEAPERIOD_SYM128 0x00000280U 4092 #define LRFDMDM_DEMMISC2_STIMTEAPERIOD_SYM64 0x00000200U 4093 #define LRFDMDM_DEMMISC2_STIMTEAPERIOD_SYM32 0x00000180U 4094 #define LRFDMDM_DEMMISC2_STIMTEAPERIOD_SYM16 0x00000100U 4095 #define LRFDMDM_DEMMISC2_STIMTEAPERIOD_SYM8 0x00000080U 4096 #define LRFDMDM_DEMMISC2_STIMTEAPERIOD_SYM4 0x00000000U 4097 4098 // Field: [6:4] STIMTEAGAIN 4099 // 4100 // Symbol timing error accumulator gain in STIM 4101 // ENUMs: 4102 // DIV4 Gain is 1/4 4103 // DIV8 Gain is 1/8 4104 // DIV16 Gain is 1/16 4105 // DIV32 Gain is 1/32 4106 // DIV64 Gain is 1/64 4107 // DIV128 Gain is 1/128 4108 // DIV256 Gain is 1/256 4109 // DIV512 Gain is 1/512 4110 #define LRFDMDM_DEMMISC2_STIMTEAGAIN_W 3U 4111 #define LRFDMDM_DEMMISC2_STIMTEAGAIN_M 0x00000070U 4112 #define LRFDMDM_DEMMISC2_STIMTEAGAIN_S 4U 4113 #define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV4 0x00000070U 4114 #define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV8 0x00000060U 4115 #define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV16 0x00000050U 4116 #define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV32 0x00000040U 4117 #define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV64 0x00000030U 4118 #define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV128 0x00000020U 4119 #define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV256 0x00000010U 4120 #define LRFDMDM_DEMMISC2_STIMTEAGAIN_DIV512 0x00000000U 4121 4122 // Field: [3] PDIFLINPREDEN 4123 // 4124 // Enable linear predictor in PDIF at CORDIC output 4125 // ENUMs: 4126 // ON The bit is 1 4127 // OFF The bit is 0 4128 #define LRFDMDM_DEMMISC2_PDIFLINPREDEN 0x00000008U 4129 #define LRFDMDM_DEMMISC2_PDIFLINPREDEN_M 0x00000008U 4130 #define LRFDMDM_DEMMISC2_PDIFLINPREDEN_S 3U 4131 #define LRFDMDM_DEMMISC2_PDIFLINPREDEN_ON 0x00000008U 4132 #define LRFDMDM_DEMMISC2_PDIFLINPREDEN_OFF 0x00000000U 4133 4134 // Field: [2] PDIFDESPECK 4135 // 4136 // Enable despeckler in PDIF at CORDIC output 4137 // ENUMs: 4138 // EN The bit is 1 4139 // DIS The bit is 0 4140 #define LRFDMDM_DEMMISC2_PDIFDESPECK 0x00000004U 4141 #define LRFDMDM_DEMMISC2_PDIFDESPECK_M 0x00000004U 4142 #define LRFDMDM_DEMMISC2_PDIFDESPECK_S 2U 4143 #define LRFDMDM_DEMMISC2_PDIFDESPECK_EN 0x00000004U 4144 #define LRFDMDM_DEMMISC2_PDIFDESPECK_DIS 0x00000000U 4145 4146 // Field: [1] PDIFIQCONJEN 4147 // 4148 // Conjugate the complex I/Q signal in PDIF 4149 // ENUMs: 4150 // ON The bit is 1 4151 // OFF The bit is 0 4152 #define LRFDMDM_DEMMISC2_PDIFIQCONJEN 0x00000002U 4153 #define LRFDMDM_DEMMISC2_PDIFIQCONJEN_M 0x00000002U 4154 #define LRFDMDM_DEMMISC2_PDIFIQCONJEN_S 1U 4155 #define LRFDMDM_DEMMISC2_PDIFIQCONJEN_ON 0x00000002U 4156 #define LRFDMDM_DEMMISC2_PDIFIQCONJEN_OFF 0x00000000U 4157 4158 // Field: [0] PDIFLIMITRANGE 4159 // 4160 // Limit range on maximal PDIF output, i.e. instantaneous frequency sample 4161 // ENUMs: 4162 // EN Limit the range to 7-bit, i.e. +/- 64 4163 // DIS Allow full 8-bit range, i.e. +/- 128 4164 #define LRFDMDM_DEMMISC2_PDIFLIMITRANGE 0x00000001U 4165 #define LRFDMDM_DEMMISC2_PDIFLIMITRANGE_M 0x00000001U 4166 #define LRFDMDM_DEMMISC2_PDIFLIMITRANGE_S 0U 4167 #define LRFDMDM_DEMMISC2_PDIFLIMITRANGE_EN 0x00000001U 4168 #define LRFDMDM_DEMMISC2_PDIFLIMITRANGE_DIS 0x00000000U 4169 4170 //***************************************************************************** 4171 // 4172 // Register: LRFDMDM_O_DEMMISC3 4173 // 4174 //***************************************************************************** 4175 // Field: [14:13] BDE2DVGA 4176 // 4177 // DVGA settings for BDE2. The DVGA control for BDE2 is shared with the RFE in 4178 // its LRFDRFE:GAINCTRL.BDE2DVGA register. 4179 // Software should determine who uses them. Please note that if both processors 4180 // attempt to control it, the resulting setting will be the two settings ORed 4181 // together. 4182 // ENUMs: 4183 // GAIN8 Gain 8 4184 // GAIN4 Gain 4 4185 // GAIN2 Gain 2 4186 // GAIN1 Gain 1 4187 #define LRFDMDM_DEMMISC3_BDE2DVGA_W 2U 4188 #define LRFDMDM_DEMMISC3_BDE2DVGA_M 0x00006000U 4189 #define LRFDMDM_DEMMISC3_BDE2DVGA_S 13U 4190 #define LRFDMDM_DEMMISC3_BDE2DVGA_GAIN8 0x00006000U 4191 #define LRFDMDM_DEMMISC3_BDE2DVGA_GAIN4 0x00004000U 4192 #define LRFDMDM_DEMMISC3_BDE2DVGA_GAIN2 0x00002000U 4193 #define LRFDMDM_DEMMISC3_BDE2DVGA_GAIN1 0x00000000U 4194 4195 // Field: [12] BDE1FILTMODE 4196 // 4197 // BDE1 Filter only mode. When enabled, BDE1 lp filters in signal path, but no 4198 // decimation occurs. 4199 // ENUMs: 4200 // DIV2 Decimate by 2 4201 // DIV1 Decimate by 1 (no decimation) 4202 #define LRFDMDM_DEMMISC3_BDE1FILTMODE 0x00001000U 4203 #define LRFDMDM_DEMMISC3_BDE1FILTMODE_M 0x00001000U 4204 #define LRFDMDM_DEMMISC3_BDE1FILTMODE_S 12U 4205 #define LRFDMDM_DEMMISC3_BDE1FILTMODE_DIV2 0x00001000U 4206 #define LRFDMDM_DEMMISC3_BDE1FILTMODE_DIV1 0x00000000U 4207 4208 // Field: [11:10] LQIPERIOD 4209 // 4210 // LQI measurement period 4211 // ENUMs: 4212 // SYM1024 1024 symbols 4213 // SYM256 256 symbols 4214 // SYM64 64 symbols 4215 // SYM16 16 symbols 4216 #define LRFDMDM_DEMMISC3_LQIPERIOD_W 2U 4217 #define LRFDMDM_DEMMISC3_LQIPERIOD_M 0x00000C00U 4218 #define LRFDMDM_DEMMISC3_LQIPERIOD_S 10U 4219 #define LRFDMDM_DEMMISC3_LQIPERIOD_SYM1024 0x00000C00U 4220 #define LRFDMDM_DEMMISC3_LQIPERIOD_SYM256 0x00000800U 4221 #define LRFDMDM_DEMMISC3_LQIPERIOD_SYM64 0x00000400U 4222 #define LRFDMDM_DEMMISC3_LQIPERIOD_SYM16 0x00000000U 4223 4224 // Field: [9:8] BDE1DVGA 4225 // 4226 // DVGA settings for BDE1. The DVGA control for BDE1 is shared with the RFE in 4227 // its LRFDRFE:GAINCTRL.BDE1DVGA register. 4228 // Software should determine who uses them. Please note that if both processors 4229 // attempt to control it, the resulting setting will be the two settings ORed 4230 // together. 4231 // ENUMs: 4232 // GAIN8 Gain 8 4233 // GAIN4 Gain 4 4234 // GAIN2 Gain 2 4235 // GAIN1 Gain 1 4236 #define LRFDMDM_DEMMISC3_BDE1DVGA_W 2U 4237 #define LRFDMDM_DEMMISC3_BDE1DVGA_M 0x00000300U 4238 #define LRFDMDM_DEMMISC3_BDE1DVGA_S 8U 4239 #define LRFDMDM_DEMMISC3_BDE1DVGA_GAIN8 0x00000300U 4240 #define LRFDMDM_DEMMISC3_BDE1DVGA_GAIN4 0x00000200U 4241 #define LRFDMDM_DEMMISC3_BDE1DVGA_GAIN2 0x00000100U 4242 #define LRFDMDM_DEMMISC3_BDE1DVGA_GAIN1 0x00000000U 4243 4244 // Field: [7] BDE1NUMSTAGES 4245 // 4246 // BDE1 decimation filter setting 4247 // ENUMs: 4248 // DIV2 Decimate by 2 4249 // DIV1 Decimate by 1 (no decimation) 4250 #define LRFDMDM_DEMMISC3_BDE1NUMSTAGES 0x00000080U 4251 #define LRFDMDM_DEMMISC3_BDE1NUMSTAGES_M 0x00000080U 4252 #define LRFDMDM_DEMMISC3_BDE1NUMSTAGES_S 7U 4253 #define LRFDMDM_DEMMISC3_BDE1NUMSTAGES_DIV2 0x00000080U 4254 #define LRFDMDM_DEMMISC3_BDE1NUMSTAGES_DIV1 0x00000000U 4255 4256 // Field: [6:5] PDIFDECIM 4257 // 4258 // Additional decimation in PDIF 4259 // ENUMs: 4260 // DIV4 Decimate by 4 4261 // DIV2 Decimate by 2 4262 // DIV1 No decimation 4263 #define LRFDMDM_DEMMISC3_PDIFDECIM_W 2U 4264 #define LRFDMDM_DEMMISC3_PDIFDECIM_M 0x00000060U 4265 #define LRFDMDM_DEMMISC3_PDIFDECIM_S 5U 4266 #define LRFDMDM_DEMMISC3_PDIFDECIM_DIV4 0x00000040U 4267 #define LRFDMDM_DEMMISC3_PDIFDECIM_DIV2 0x00000020U 4268 #define LRFDMDM_DEMMISC3_PDIFDECIM_DIV1 0x00000000U 4269 4270 // Field: [4:0] BDE2DECRATIO 4271 // 4272 // BDE2 decimation filter setting 4273 // ENUMs: 4274 // DIV8 Decimate by 8 4275 // DIV4 Decimate by 4 4276 // DIV2 Decimate by 2 4277 // DIV1 Decimate by 1 (no decimation) 4278 #define LRFDMDM_DEMMISC3_BDE2DECRATIO_W 5U 4279 #define LRFDMDM_DEMMISC3_BDE2DECRATIO_M 0x0000001FU 4280 #define LRFDMDM_DEMMISC3_BDE2DECRATIO_S 0U 4281 #define LRFDMDM_DEMMISC3_BDE2DECRATIO_DIV8 0x00000003U 4282 #define LRFDMDM_DEMMISC3_BDE2DECRATIO_DIV4 0x00000002U 4283 #define LRFDMDM_DEMMISC3_BDE2DECRATIO_DIV2 0x00000001U 4284 #define LRFDMDM_DEMMISC3_BDE2DECRATIO_DIV1 0x00000000U 4285 4286 //***************************************************************************** 4287 // 4288 // Register: LRFDMDM_O_DEMIQMC0 4289 // 4290 //***************************************************************************** 4291 // Field: [15:8] GAINFACTOR 4292 // 4293 // Gain factor to compensate for unequal gains between the I and Q signal paths 4294 // in the analog RF front-end. 4295 // The compensation is done by scaling the I path amplitude (no compensation of 4296 // Q path). 4297 // The gain factor is given as an unsigned number in the range [0,255] 4298 // corresponding to gain factor range [0,2], 4299 // where value 128 gives gain factor 1.0 (no gain). Any gain compensation is 4300 // applied in a stage after the phase compensation. 4301 // ENUMs: 4302 // ALLONES All the bits are 1 4303 // ALLZEROS All the bits are 0 4304 #define LRFDMDM_DEMIQMC0_GAINFACTOR_W 8U 4305 #define LRFDMDM_DEMIQMC0_GAINFACTOR_M 0x0000FF00U 4306 #define LRFDMDM_DEMIQMC0_GAINFACTOR_S 8U 4307 #define LRFDMDM_DEMIQMC0_GAINFACTOR_ALLONES 0x0000FF00U 4308 #define LRFDMDM_DEMIQMC0_GAINFACTOR_ALLZEROS 0x00000000U 4309 4310 // Field: [7:0] PHASEFACTOR 4311 // 4312 // Phase factor to compensate for unorthogonal I and Q signals. 4313 // The phase factor is given as a signed number in the range [-128,127] 4314 // corresponding to phase factor range [-0.5, 0.496], 4315 // where the phase factor can be calculated as phase_factor = tan(phase_error). 4316 // This gives an available phase error compensation range of [-26.6, 26.4] 4317 // degrees. 4318 // ENUMs: 4319 // ALLONES All the bits are 1 4320 // ALLZEROS All the bits are 0 4321 #define LRFDMDM_DEMIQMC0_PHASEFACTOR_W 8U 4322 #define LRFDMDM_DEMIQMC0_PHASEFACTOR_M 0x000000FFU 4323 #define LRFDMDM_DEMIQMC0_PHASEFACTOR_S 0U 4324 #define LRFDMDM_DEMIQMC0_PHASEFACTOR_ALLONES 0x000000FFU 4325 #define LRFDMDM_DEMIQMC0_PHASEFACTOR_ALLZEROS 0x00000000U 4326 4327 //***************************************************************************** 4328 // 4329 // Register: LRFDMDM_O_DEMDSBU 4330 // 4331 //***************************************************************************** 4332 // Field: [15:8] DSBUAVGLENGTH 4333 // 4334 // Length for moving average of the newest DSBU samples. 4335 // The buffer can hold up to 256 samples. Length of 255 is maximum. 4336 // ENUMs: 4337 // ALLONES All the bits are 1 4338 // ALLZEROS All the bits are 0 4339 #define LRFDMDM_DEMDSBU_DSBUAVGLENGTH_W 8U 4340 #define LRFDMDM_DEMDSBU_DSBUAVGLENGTH_M 0x0000FF00U 4341 #define LRFDMDM_DEMDSBU_DSBUAVGLENGTH_S 8U 4342 #define LRFDMDM_DEMDSBU_DSBUAVGLENGTH_ALLONES 0x0000FF00U 4343 #define LRFDMDM_DEMDSBU_DSBUAVGLENGTH_ALLZEROS 0x00000000U 4344 4345 // Field: [7:0] DSBUDELAY 4346 // 4347 // Output delay from sample buffer, as offset between write and read pointers. 4348 // The buffer can hold up to 256 samples. Delay of 0 means maximum. 4349 // ENUMs: 4350 // ALLONES All the bits are 1 4351 // ALLZEROS All the bits are 0 4352 #define LRFDMDM_DEMDSBU_DSBUDELAY_W 8U 4353 #define LRFDMDM_DEMDSBU_DSBUDELAY_M 0x000000FFU 4354 #define LRFDMDM_DEMDSBU_DSBUDELAY_S 0U 4355 #define LRFDMDM_DEMDSBU_DSBUDELAY_ALLONES 0x000000FFU 4356 #define LRFDMDM_DEMDSBU_DSBUDELAY_ALLZEROS 0x00000000U 4357 4358 //***************************************************************************** 4359 // 4360 // Register: LRFDMDM_O_DEMCODC0 4361 // 4362 //***************************************************************************** 4363 // Field: [11] ESTSEL 4364 // 4365 // Select which estimator to show as readable output 4366 // ENUMs: 4367 // IIR Read back latest IIR estimate 4368 // ACC Read back latest accumulator estimate 4369 #define LRFDMDM_DEMCODC0_ESTSEL 0x00000800U 4370 #define LRFDMDM_DEMCODC0_ESTSEL_M 0x00000800U 4371 #define LRFDMDM_DEMCODC0_ESTSEL_S 11U 4372 #define LRFDMDM_DEMCODC0_ESTSEL_IIR 0x00000800U 4373 #define LRFDMDM_DEMCODC0_ESTSEL_ACC 0x00000000U 4374 4375 // Field: [10:9] COMPSEL 4376 // 4377 // Select estimator to use for coarse DC offset compensation 4378 // ENUMs: 4379 // IIR Compensate with latest IIR estimate 4380 // ACC Compensate with latest accumulator estimate 4381 // MANUAL Use manually programmable values from DEMCODC1 4382 // registers 4383 #define LRFDMDM_DEMCODC0_COMPSEL_W 2U 4384 #define LRFDMDM_DEMCODC0_COMPSEL_M 0x00000600U 4385 #define LRFDMDM_DEMCODC0_COMPSEL_S 9U 4386 #define LRFDMDM_DEMCODC0_COMPSEL_IIR 0x00000600U 4387 #define LRFDMDM_DEMCODC0_COMPSEL_ACC 0x00000400U 4388 #define LRFDMDM_DEMCODC0_COMPSEL_MANUAL 0x00000000U 4389 4390 // Field: [8] IIRUSEINITIAL 4391 // 4392 // When enabled, a configurable value is loaded to initialize IIR filter when 4393 // CODC estimator is re-initialized. 4394 // ENUMs: 4395 // EN Use the manual compensation values in DEMCODC1 for 4396 // initialization 4397 // DIS Initialize IIR filter with value zero 4398 #define LRFDMDM_DEMCODC0_IIRUSEINITIAL 0x00000100U 4399 #define LRFDMDM_DEMCODC0_IIRUSEINITIAL_M 0x00000100U 4400 #define LRFDMDM_DEMCODC0_IIRUSEINITIAL_S 8U 4401 #define LRFDMDM_DEMCODC0_IIRUSEINITIAL_EN 0x00000100U 4402 #define LRFDMDM_DEMCODC0_IIRUSEINITIAL_DIS 0x00000000U 4403 4404 // Field: [7:5] IIRGAIN 4405 // 4406 // Adjust first-order IIR filter adaptation which controls filter bandwidth. 4407 // ENUMs: 4408 // DIV1024 Use 1/1024 IIR adaptation 4409 // DIV512 Use 1/512 IIR adaptation 4410 // DIV256 Use 1/256 IIR adaptation 4411 // DIV128 Use 1/128 IIR adaptation 4412 // DIV64 Use 1/64 IIR adaptation 4413 // DIV32 Use 1/32 IIR adaptation 4414 // DIV16 Use 1/16 IIR adaptation 4415 // OFF Filter disabled 4416 #define LRFDMDM_DEMCODC0_IIRGAIN_W 3U 4417 #define LRFDMDM_DEMCODC0_IIRGAIN_M 0x000000E0U 4418 #define LRFDMDM_DEMCODC0_IIRGAIN_S 5U 4419 #define LRFDMDM_DEMCODC0_IIRGAIN_DIV1024 0x000000E0U 4420 #define LRFDMDM_DEMCODC0_IIRGAIN_DIV512 0x000000C0U 4421 #define LRFDMDM_DEMCODC0_IIRGAIN_DIV256 0x000000A0U 4422 #define LRFDMDM_DEMCODC0_IIRGAIN_DIV128 0x00000080U 4423 #define LRFDMDM_DEMCODC0_IIRGAIN_DIV64 0x00000060U 4424 #define LRFDMDM_DEMCODC0_IIRGAIN_DIV32 0x00000040U 4425 #define LRFDMDM_DEMCODC0_IIRGAIN_DIV16 0x00000020U 4426 #define LRFDMDM_DEMCODC0_IIRGAIN_OFF 0x00000000U 4427 4428 // Field: [4] IIREN 4429 // 4430 // Enable first-order IIR filter inside CODC 4431 // ENUMs: 4432 // ON Enable IIR estimator 4433 // OFF Disable IIR estimator 4434 #define LRFDMDM_DEMCODC0_IIREN 0x00000010U 4435 #define LRFDMDM_DEMCODC0_IIREN_M 0x00000010U 4436 #define LRFDMDM_DEMCODC0_IIREN_S 4U 4437 #define LRFDMDM_DEMCODC0_IIREN_ON 0x00000010U 4438 #define LRFDMDM_DEMCODC0_IIREN_OFF 0x00000000U 4439 4440 // Field: [3] ACCMODE 4441 // 4442 // Accumulator estimator mode 4443 // ENUMs: 4444 // CONT Generate new DC estimates continuously 4445 // SINGLE Generate a single DC estimate only, then stop 4446 #define LRFDMDM_DEMCODC0_ACCMODE 0x00000008U 4447 #define LRFDMDM_DEMCODC0_ACCMODE_M 0x00000008U 4448 #define LRFDMDM_DEMCODC0_ACCMODE_S 3U 4449 #define LRFDMDM_DEMCODC0_ACCMODE_CONT 0x00000008U 4450 #define LRFDMDM_DEMCODC0_ACCMODE_SINGLE 0x00000000U 4451 4452 // Field: [2:1] ACCPERIOD 4453 // 4454 // Integration period for accumulator estimator 4455 // ENUMs: 4456 // SMPL512 512 samples 4457 // SMPL128 128 samples 4458 // SMPL32 32 samples 4459 // SMPL8 8 samples 4460 #define LRFDMDM_DEMCODC0_ACCPERIOD_W 2U 4461 #define LRFDMDM_DEMCODC0_ACCPERIOD_M 0x00000006U 4462 #define LRFDMDM_DEMCODC0_ACCPERIOD_S 1U 4463 #define LRFDMDM_DEMCODC0_ACCPERIOD_SMPL512 0x00000006U 4464 #define LRFDMDM_DEMCODC0_ACCPERIOD_SMPL128 0x00000004U 4465 #define LRFDMDM_DEMCODC0_ACCPERIOD_SMPL32 0x00000002U 4466 #define LRFDMDM_DEMCODC0_ACCPERIOD_SMPL8 0x00000000U 4467 4468 // Field: [0] ACCEN 4469 // 4470 // Enable accumulator based estimator inside CODC 4471 // ENUMs: 4472 // ON Enable accumulator estimator 4473 // OFF Disable accumulator estimator 4474 #define LRFDMDM_DEMCODC0_ACCEN 0x00000001U 4475 #define LRFDMDM_DEMCODC0_ACCEN_M 0x00000001U 4476 #define LRFDMDM_DEMCODC0_ACCEN_S 0U 4477 #define LRFDMDM_DEMCODC0_ACCEN_ON 0x00000001U 4478 #define LRFDMDM_DEMCODC0_ACCEN_OFF 0x00000000U 4479 4480 //***************************************************************************** 4481 // 4482 // Register: LRFDMDM_O_DEMFIDC0 4483 // 4484 //***************************************************************************** 4485 // Field: [5:4] COMPSEL 4486 // 4487 // Select estimator to use for fine DC offset compensation 4488 // ENUMs: 4489 // ACC Compensate with latest accumulator estimate 4490 // MANUAL Use manually programmable values from DEMFIDC1 4491 // registers 4492 #define LRFDMDM_DEMFIDC0_COMPSEL_W 2U 4493 #define LRFDMDM_DEMFIDC0_COMPSEL_M 0x00000030U 4494 #define LRFDMDM_DEMFIDC0_COMPSEL_S 4U 4495 #define LRFDMDM_DEMFIDC0_COMPSEL_ACC 0x00000020U 4496 #define LRFDMDM_DEMFIDC0_COMPSEL_MANUAL 0x00000000U 4497 4498 // Field: [3:2] ACCPERIOD 4499 // 4500 // Integration period for accumulator estimator 4501 // ENUMs: 4502 // SMPL512 512 samples 4503 // SMPL128 128 samples 4504 // SMPL32 32 samples 4505 // SMPL8 8 samples 4506 #define LRFDMDM_DEMFIDC0_ACCPERIOD_W 2U 4507 #define LRFDMDM_DEMFIDC0_ACCPERIOD_M 0x0000000CU 4508 #define LRFDMDM_DEMFIDC0_ACCPERIOD_S 2U 4509 #define LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL512 0x0000000CU 4510 #define LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL128 0x00000008U 4511 #define LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL32 0x00000004U 4512 #define LRFDMDM_DEMFIDC0_ACCPERIOD_SMPL8 0x00000000U 4513 4514 // Field: [1] ACCMODE 4515 // 4516 // Accumulator estimator mode 4517 // ENUMs: 4518 // CONT Generate new DC estimates continuously 4519 // SINGLE Generate a single DC estimate only, then stop 4520 #define LRFDMDM_DEMFIDC0_ACCMODE 0x00000002U 4521 #define LRFDMDM_DEMFIDC0_ACCMODE_M 0x00000002U 4522 #define LRFDMDM_DEMFIDC0_ACCMODE_S 1U 4523 #define LRFDMDM_DEMFIDC0_ACCMODE_CONT 0x00000002U 4524 #define LRFDMDM_DEMFIDC0_ACCMODE_SINGLE 0x00000000U 4525 4526 // Field: [0] ACCEN 4527 // 4528 // Enable accumulator based estimator inside FIDC 4529 // ENUMs: 4530 // ON Enable accumulator estimator 4531 // OFF Disable accumulator estimator 4532 #define LRFDMDM_DEMFIDC0_ACCEN 0x00000001U 4533 #define LRFDMDM_DEMFIDC0_ACCEN_M 0x00000001U 4534 #define LRFDMDM_DEMFIDC0_ACCEN_S 0U 4535 #define LRFDMDM_DEMFIDC0_ACCEN_ON 0x00000001U 4536 #define LRFDMDM_DEMFIDC0_ACCEN_OFF 0x00000000U 4537 4538 //***************************************************************************** 4539 // 4540 // Register: LRFDMDM_O_DEMFEXB0 4541 // 4542 //***************************************************************************** 4543 // Field: [13] OUT2PASSTHROUGH 4544 // 4545 // Front-end crossbar output #2 is direct passthrough of the crossbar input 4546 // ENUMs: 4547 // ONE The bit is 1 4548 // ZERO The bit is 0 4549 #define LRFDMDM_DEMFEXB0_OUT2PASSTHROUGH 0x00002000U 4550 #define LRFDMDM_DEMFEXB0_OUT2PASSTHROUGH_M 0x00002000U 4551 #define LRFDMDM_DEMFEXB0_OUT2PASSTHROUGH_S 13U 4552 #define LRFDMDM_DEMFEXB0_OUT2PASSTHROUGH_ONE 0x00002000U 4553 #define LRFDMDM_DEMFEXB0_OUT2PASSTHROUGH_ZERO 0x00000000U 4554 4555 // Field: [12:11] OUT2SRCSEL 4556 // 4557 // Source select for XBAR output #2 (towards magnitude estimation engine MGE0) 4558 // ENUMs: 4559 // BDE1 Source is complex N*Fs/1024 mixer (CMIX) 4560 // CMIX Source is complex N*Fs/1024 mixer (CMIX) 4561 // CODC Source is coarse DC remover (CODC) 4562 #define LRFDMDM_DEMFEXB0_OUT2SRCSEL_W 2U 4563 #define LRFDMDM_DEMFEXB0_OUT2SRCSEL_M 0x00001800U 4564 #define LRFDMDM_DEMFEXB0_OUT2SRCSEL_S 11U 4565 #define LRFDMDM_DEMFEXB0_OUT2SRCSEL_BDE1 0x00001000U 4566 #define LRFDMDM_DEMFEXB0_OUT2SRCSEL_CMIX 0x00000800U 4567 #define LRFDMDM_DEMFEXB0_OUT2SRCSEL_CODC 0x00000000U 4568 4569 // Field: [10] OUT1PASSTHROUGH 4570 // 4571 // Front-end crossbar output #1 is direct passthrough of the crossbar input 4572 // ENUMs: 4573 // ONE The bit is 1 4574 // ZERO The bit is 0 4575 #define LRFDMDM_DEMFEXB0_OUT1PASSTHROUGH 0x00000400U 4576 #define LRFDMDM_DEMFEXB0_OUT1PASSTHROUGH_M 0x00000400U 4577 #define LRFDMDM_DEMFEXB0_OUT1PASSTHROUGH_S 10U 4578 #define LRFDMDM_DEMFEXB0_OUT1PASSTHROUGH_ONE 0x00000400U 4579 #define LRFDMDM_DEMFEXB0_OUT1PASSTHROUGH_ZERO 0x00000000U 4580 4581 // Field: [9:8] OUT1SRCSEL 4582 // 4583 // Source select for XBAR output #1 (main output, towards BDE2 and rest of 4584 // demodulator) 4585 // ENUMs: 4586 // BDE1 Source is complex N*Fs/1024 mixer (CMIX) 4587 // CMIX Source is complex N*Fs/1024 mixer (CMIX) 4588 // CODC Source is coarse DC remover (CODC) 4589 #define LRFDMDM_DEMFEXB0_OUT1SRCSEL_W 2U 4590 #define LRFDMDM_DEMFEXB0_OUT1SRCSEL_M 0x00000300U 4591 #define LRFDMDM_DEMFEXB0_OUT1SRCSEL_S 8U 4592 #define LRFDMDM_DEMFEXB0_OUT1SRCSEL_BDE1 0x00000200U 4593 #define LRFDMDM_DEMFEXB0_OUT1SRCSEL_CMIX 0x00000100U 4594 #define LRFDMDM_DEMFEXB0_OUT1SRCSEL_CODC 0x00000000U 4595 4596 // Field: [7:6] B4SRCSEL 4597 // 4598 // Not used 4599 // ENUMs: 4600 // ONES Source is complex N*Fs/1024 mixer (ONES) 4601 // ZEROS Source is complex N*Fs/1024 mixer (ZEROS) 4602 #define LRFDMDM_DEMFEXB0_B4SRCSEL_W 2U 4603 #define LRFDMDM_DEMFEXB0_B4SRCSEL_M 0x000000C0U 4604 #define LRFDMDM_DEMFEXB0_B4SRCSEL_S 6U 4605 #define LRFDMDM_DEMFEXB0_B4SRCSEL_ONES 0x000000C0U 4606 #define LRFDMDM_DEMFEXB0_B4SRCSEL_ZEROS 0x00000000U 4607 4608 // Field: [5:4] B3SRCSEL 4609 // 4610 // Source select for BDE1 (XBAR block #3) 4611 // ENUMs: 4612 // CMIX Source is complex N*Fs/1024 mixer (CMIX) 4613 // CODC Source is complex N*Fs/1024 mixer (CMIX) 4614 // INPUT Source is crossbar main input 4615 #define LRFDMDM_DEMFEXB0_B3SRCSEL_W 2U 4616 #define LRFDMDM_DEMFEXB0_B3SRCSEL_M 0x00000030U 4617 #define LRFDMDM_DEMFEXB0_B3SRCSEL_S 4U 4618 #define LRFDMDM_DEMFEXB0_B3SRCSEL_CMIX 0x00000020U 4619 #define LRFDMDM_DEMFEXB0_B3SRCSEL_CODC 0x00000010U 4620 #define LRFDMDM_DEMFEXB0_B3SRCSEL_INPUT 0x00000000U 4621 4622 // Field: [3:2] B2SRCSEL 4623 // 4624 // Source select for CMIX (XBAR block #2) 4625 // ENUMs: 4626 // BDE1 Source is coarse DC remover (CODC) 4627 // CODC Source is coarse DC remover (CODC) 4628 // INPUT Source is crossbar main input 4629 #define LRFDMDM_DEMFEXB0_B2SRCSEL_W 2U 4630 #define LRFDMDM_DEMFEXB0_B2SRCSEL_M 0x0000000CU 4631 #define LRFDMDM_DEMFEXB0_B2SRCSEL_S 2U 4632 #define LRFDMDM_DEMFEXB0_B2SRCSEL_BDE1 0x00000008U 4633 #define LRFDMDM_DEMFEXB0_B2SRCSEL_CODC 0x00000004U 4634 #define LRFDMDM_DEMFEXB0_B2SRCSEL_INPUT 0x00000000U 4635 4636 // Field: [1:0] B1SRCSEL 4637 // 4638 // Source select for CODC (XBAR block #1) 4639 // ENUMs: 4640 // BDE1 Source is complex N*Fs/1024 mixer (CMIX) 4641 // CMIX Source is complex N*Fs/1024 mixer (CMIX) 4642 // INPUT Source is crossbar main input 4643 #define LRFDMDM_DEMFEXB0_B1SRCSEL_W 2U 4644 #define LRFDMDM_DEMFEXB0_B1SRCSEL_M 0x00000003U 4645 #define LRFDMDM_DEMFEXB0_B1SRCSEL_S 0U 4646 #define LRFDMDM_DEMFEXB0_B1SRCSEL_BDE1 0x00000002U 4647 #define LRFDMDM_DEMFEXB0_B1SRCSEL_CMIX 0x00000001U 4648 #define LRFDMDM_DEMFEXB0_B1SRCSEL_INPUT 0x00000000U 4649 4650 //***************************************************************************** 4651 // 4652 // Register: LRFDMDM_O_DEMDSXB0 4653 // 4654 //***************************************************************************** 4655 // Field: [5] OUT2PASSTHROUGH 4656 // 4657 // Crossbar output #2 is direct passthrough of the crossbar input 4658 // ENUMs: 4659 // ONE The bit is 1 4660 // ZERO The bit is 0 4661 #define LRFDMDM_DEMDSXB0_OUT2PASSTHROUGH 0x00000020U 4662 #define LRFDMDM_DEMDSXB0_OUT2PASSTHROUGH_M 0x00000020U 4663 #define LRFDMDM_DEMDSXB0_OUT2PASSTHROUGH_S 5U 4664 #define LRFDMDM_DEMDSXB0_OUT2PASSTHROUGH_ONE 0x00000020U 4665 #define LRFDMDM_DEMDSXB0_OUT2PASSTHROUGH_ZERO 0x00000000U 4666 4667 // Field: [4] OUT1PASSTHROUGH 4668 // 4669 // Crossbar output #1 is direct passthrough of the crossbar input 4670 // ENUMs: 4671 // ONE The bit is 1 4672 // ZERO The bit is 0 4673 #define LRFDMDM_DEMDSXB0_OUT1PASSTHROUGH 0x00000010U 4674 #define LRFDMDM_DEMDSXB0_OUT1PASSTHROUGH_M 0x00000010U 4675 #define LRFDMDM_DEMDSXB0_OUT1PASSTHROUGH_S 4U 4676 #define LRFDMDM_DEMDSXB0_OUT1PASSTHROUGH_ONE 0x00000010U 4677 #define LRFDMDM_DEMDSXB0_OUT1PASSTHROUGH_ZERO 0x00000000U 4678 4679 // Field: [3] OUTSRCSEL2 4680 // 4681 // Source select XBAR output, branch 1 (baud branch) 4682 // ENUMs: 4683 // MAFI Source is matched filter (MAFI) 4684 // FIFE Source is fine frequency offset estimator (FIFE) 4685 #define LRFDMDM_DEMDSXB0_OUTSRCSEL2 0x00000008U 4686 #define LRFDMDM_DEMDSXB0_OUTSRCSEL2_M 0x00000008U 4687 #define LRFDMDM_DEMDSXB0_OUTSRCSEL2_S 3U 4688 #define LRFDMDM_DEMDSXB0_OUTSRCSEL2_MAFI 0x00000008U 4689 #define LRFDMDM_DEMDSXB0_OUTSRCSEL2_FIFE 0x00000000U 4690 4691 // Field: [2] OUTSRCSEL1 4692 // 4693 // Source select for XBAR output, branch 2 (flushed branch) 4694 // ENUMs: 4695 // MAFI Source is matched filter (MAFI) 4696 // FIFE Source is fine frequency offset estimator (FIFE) 4697 #define LRFDMDM_DEMDSXB0_OUTSRCSEL1 0x00000004U 4698 #define LRFDMDM_DEMDSXB0_OUTSRCSEL1_M 0x00000004U 4699 #define LRFDMDM_DEMDSXB0_OUTSRCSEL1_S 2U 4700 #define LRFDMDM_DEMDSXB0_OUTSRCSEL1_MAFI 0x00000004U 4701 #define LRFDMDM_DEMDSXB0_OUTSRCSEL1_FIFE 0x00000000U 4702 4703 // Field: [1] B2SRCSEL 4704 // 4705 // Source select for MAFI (XBAR block #2) 4706 // ENUMs: 4707 // FIFE Source is fine frequency offset estimator (FIFE) 4708 // INPUT Source is crossbar main input 4709 #define LRFDMDM_DEMDSXB0_B2SRCSEL 0x00000002U 4710 #define LRFDMDM_DEMDSXB0_B2SRCSEL_M 0x00000002U 4711 #define LRFDMDM_DEMDSXB0_B2SRCSEL_S 1U 4712 #define LRFDMDM_DEMDSXB0_B2SRCSEL_FIFE 0x00000002U 4713 #define LRFDMDM_DEMDSXB0_B2SRCSEL_INPUT 0x00000000U 4714 4715 // Field: [0] B1SRCSEL 4716 // 4717 // Source select for FIFE (XBAR block #1) 4718 // ENUMs: 4719 // MAFI Source is matched filter (MAFI) 4720 // INPUT Source is crossbar main input 4721 #define LRFDMDM_DEMDSXB0_B1SRCSEL 0x00000001U 4722 #define LRFDMDM_DEMDSXB0_B1SRCSEL_M 0x00000001U 4723 #define LRFDMDM_DEMDSXB0_B1SRCSEL_S 0U 4724 #define LRFDMDM_DEMDSXB0_B1SRCSEL_MAFI 0x00000001U 4725 #define LRFDMDM_DEMDSXB0_B1SRCSEL_INPUT 0x00000000U 4726 4727 //***************************************************************************** 4728 // 4729 // Register: LRFDMDM_O_DEMFIFE0 4730 // 4731 //***************************************************************************** 4732 // Field: [11] FINEFOESEL 4733 // 4734 // Select which estimator to show as readable output 4735 // ENUMs: 4736 // ACC Latest accumulator estimate 4737 // IIR Latest IIR estimate 4738 #define LRFDMDM_DEMFIFE0_FINEFOESEL 0x00000800U 4739 #define LRFDMDM_DEMFIFE0_FINEFOESEL_M 0x00000800U 4740 #define LRFDMDM_DEMFIFE0_FINEFOESEL_S 11U 4741 #define LRFDMDM_DEMFIFE0_FINEFOESEL_ACC 0x00000800U 4742 #define LRFDMDM_DEMFIFE0_FINEFOESEL_IIR 0x00000000U 4743 4744 // Field: [10:9] FOCFFSEL 4745 // 4746 // Select which estimate source to be used in feed-forward compensation point 4747 // ENUMs: 4748 // MANUAL Use programmable manual value from register bank. 4749 // (Note: an input register is not implemented, so 4750 // the manual compensation value is tied to '0') 4751 // ACC Compensate with latest accumulator estimate 4752 // IIR Compensate with latest IIR estimate 4753 #define LRFDMDM_DEMFIFE0_FOCFFSEL_W 2U 4754 #define LRFDMDM_DEMFIFE0_FOCFFSEL_M 0x00000600U 4755 #define LRFDMDM_DEMFIFE0_FOCFFSEL_S 9U 4756 #define LRFDMDM_DEMFIFE0_FOCFFSEL_MANUAL 0x00000400U 4757 #define LRFDMDM_DEMFIFE0_FOCFFSEL_ACC 0x00000200U 4758 #define LRFDMDM_DEMFIFE0_FOCFFSEL_IIR 0x00000000U 4759 4760 // Field: [8] ACCCNTMODE 4761 // 4762 // Accumulator estimator mode 4763 // ENUMs: 4764 // CONT Generate new frequency offset estimates 4765 // continuously 4766 // SINGLE Generate a single frequency offset estimate only, 4767 // then stop 4768 #define LRFDMDM_DEMFIFE0_ACCCNTMODE 0x00000100U 4769 #define LRFDMDM_DEMFIFE0_ACCCNTMODE_M 0x00000100U 4770 #define LRFDMDM_DEMFIFE0_ACCCNTMODE_S 8U 4771 #define LRFDMDM_DEMFIFE0_ACCCNTMODE_CONT 0x00000100U 4772 #define LRFDMDM_DEMFIFE0_ACCCNTMODE_SINGLE 0x00000000U 4773 4774 // Field: [7:6] ACCPERIOD 4775 // 4776 // Integration period for accumulator 4777 // ENUMs: 4778 // PER512 512 samples 4779 // PER256 256 samples 4780 // PER128 128 samples 4781 // PER64 64 samples 4782 #define LRFDMDM_DEMFIFE0_ACCPERIOD_W 2U 4783 #define LRFDMDM_DEMFIFE0_ACCPERIOD_M 0x000000C0U 4784 #define LRFDMDM_DEMFIFE0_ACCPERIOD_S 6U 4785 #define LRFDMDM_DEMFIFE0_ACCPERIOD_PER512 0x000000C0U 4786 #define LRFDMDM_DEMFIFE0_ACCPERIOD_PER256 0x00000080U 4787 #define LRFDMDM_DEMFIFE0_ACCPERIOD_PER128 0x00000040U 4788 #define LRFDMDM_DEMFIFE0_ACCPERIOD_PER64 0x00000000U 4789 4790 // Field: [5] ACCEN 4791 // 4792 // Enable accumulator based frequency offset estimator inside FIFE 4793 // ENUMs: 4794 // ON Enable accumulator estimator 4795 // OFF Disable accumulator estimator 4796 #define LRFDMDM_DEMFIFE0_ACCEN 0x00000020U 4797 #define LRFDMDM_DEMFIFE0_ACCEN_M 0x00000020U 4798 #define LRFDMDM_DEMFIFE0_ACCEN_S 5U 4799 #define LRFDMDM_DEMFIFE0_ACCEN_ON 0x00000020U 4800 #define LRFDMDM_DEMFIFE0_ACCEN_OFF 0x00000000U 4801 4802 // Field: [4] IIRUSEINITIAL 4803 // 4804 // When enabled, a configurable value is loaded to initialize IIR filter when 4805 // FIFE estimator is re-initialized. 4806 // ENUMs: 4807 // EN Use the manual compensation value in DEMFIFE1 for 4808 // initialization 4809 // DIS Initialize IIR filter with value zero 4810 #define LRFDMDM_DEMFIFE0_IIRUSEINITIAL 0x00000010U 4811 #define LRFDMDM_DEMFIFE0_IIRUSEINITIAL_M 0x00000010U 4812 #define LRFDMDM_DEMFIFE0_IIRUSEINITIAL_S 4U 4813 #define LRFDMDM_DEMFIFE0_IIRUSEINITIAL_EN 0x00000010U 4814 #define LRFDMDM_DEMFIFE0_IIRUSEINITIAL_DIS 0x00000000U 4815 4816 // Field: [3:1] IIRGAIN 4817 // 4818 // Adjust first-order IIR filter adaptation which controls filter bandwidth 4819 // ENUMs: 4820 // DIV1024 Use 1/1024 IIR adaptation 4821 // DIV512 Use 1/512 IIR adaptation 4822 // DIV256 Use 1/256 IIR adaptation 4823 // DIV128 Use 1/128 IIR adaptation 4824 // DIV64 Use 1/64 IIR adaptation 4825 // DIV32 Use 1/32 IIR adaptation 4826 // DIV16 Use 1/16 IIR adaptation 4827 // OFF Filter disabled 4828 #define LRFDMDM_DEMFIFE0_IIRGAIN_W 3U 4829 #define LRFDMDM_DEMFIFE0_IIRGAIN_M 0x0000000EU 4830 #define LRFDMDM_DEMFIFE0_IIRGAIN_S 1U 4831 #define LRFDMDM_DEMFIFE0_IIRGAIN_DIV1024 0x0000000EU 4832 #define LRFDMDM_DEMFIFE0_IIRGAIN_DIV512 0x0000000CU 4833 #define LRFDMDM_DEMFIFE0_IIRGAIN_DIV256 0x0000000AU 4834 #define LRFDMDM_DEMFIFE0_IIRGAIN_DIV128 0x00000008U 4835 #define LRFDMDM_DEMFIFE0_IIRGAIN_DIV64 0x00000006U 4836 #define LRFDMDM_DEMFIFE0_IIRGAIN_DIV32 0x00000004U 4837 #define LRFDMDM_DEMFIFE0_IIRGAIN_DIV16 0x00000002U 4838 #define LRFDMDM_DEMFIFE0_IIRGAIN_OFF 0x00000000U 4839 4840 // Field: [0] IIREN 4841 // 4842 // Enable first-order IIR filter based freq offset estimator inside FIFE 4843 // ENUMs: 4844 // ON Enable IIR estimator 4845 // OFF Disable IIR estimator 4846 #define LRFDMDM_DEMFIFE0_IIREN 0x00000001U 4847 #define LRFDMDM_DEMFIFE0_IIREN_M 0x00000001U 4848 #define LRFDMDM_DEMFIFE0_IIREN_S 0U 4849 #define LRFDMDM_DEMFIFE0_IIREN_ON 0x00000001U 4850 #define LRFDMDM_DEMFIFE0_IIREN_OFF 0x00000000U 4851 4852 //***************************************************************************** 4853 // 4854 // Register: LRFDMDM_O_DEMMAFI0 4855 // 4856 //***************************************************************************** 4857 // Field: [15:8] C1C7 4858 // 4859 // Filter coefficient c1 (and c7) 4860 // ENUMs: 4861 // ALLONES All the bits are 1 4862 // ALLZEROS All the bits are 0 4863 #define LRFDMDM_DEMMAFI0_C1C7_W 8U 4864 #define LRFDMDM_DEMMAFI0_C1C7_M 0x0000FF00U 4865 #define LRFDMDM_DEMMAFI0_C1C7_S 8U 4866 #define LRFDMDM_DEMMAFI0_C1C7_ALLONES 0x0000FF00U 4867 #define LRFDMDM_DEMMAFI0_C1C7_ALLZEROS 0x00000000U 4868 4869 // Field: [7:0] C0C8 4870 // 4871 // Filter coefficient c0 (and c8) 4872 // ENUMs: 4873 // ALLONES All the bits are 1 4874 // ALLZEROS All the bits are 0 4875 #define LRFDMDM_DEMMAFI0_C0C8_W 8U 4876 #define LRFDMDM_DEMMAFI0_C0C8_M 0x000000FFU 4877 #define LRFDMDM_DEMMAFI0_C0C8_S 0U 4878 #define LRFDMDM_DEMMAFI0_C0C8_ALLONES 0x000000FFU 4879 #define LRFDMDM_DEMMAFI0_C0C8_ALLZEROS 0x00000000U 4880 4881 //***************************************************************************** 4882 // 4883 // Register: LRFDMDM_O_DEMMAFI1 4884 // 4885 //***************************************************************************** 4886 // Field: [15:8] C3C5 4887 // 4888 // Filter coefficient c3 (and c5) 4889 // ENUMs: 4890 // ALLONES All the bits are 1 4891 // ALLZEROS All the bits are 0 4892 #define LRFDMDM_DEMMAFI1_C3C5_W 8U 4893 #define LRFDMDM_DEMMAFI1_C3C5_M 0x0000FF00U 4894 #define LRFDMDM_DEMMAFI1_C3C5_S 8U 4895 #define LRFDMDM_DEMMAFI1_C3C5_ALLONES 0x0000FF00U 4896 #define LRFDMDM_DEMMAFI1_C3C5_ALLZEROS 0x00000000U 4897 4898 // Field: [7:0] C2C6 4899 // 4900 // Filter coefficient c2 (and c6) 4901 // ENUMs: 4902 // ALLONES All the bits are 1 4903 // ALLZEROS All the bits are 0 4904 #define LRFDMDM_DEMMAFI1_C2C6_W 8U 4905 #define LRFDMDM_DEMMAFI1_C2C6_M 0x000000FFU 4906 #define LRFDMDM_DEMMAFI1_C2C6_S 0U 4907 #define LRFDMDM_DEMMAFI1_C2C6_ALLONES 0x000000FFU 4908 #define LRFDMDM_DEMMAFI1_C2C6_ALLZEROS 0x00000000U 4909 4910 //***************************************************************************** 4911 // 4912 // Register: LRFDMDM_O_DEMMAFI2 4913 // 4914 //***************************************************************************** 4915 // Field: [8:0] C4 4916 // 4917 // Filter coefficient c4. The matched filter will have unity gain when the sum 4918 // of all coefficients c0 to c8 equals 512. 4919 // ENUMs: 4920 // ALLONES All the bits are 1 4921 // ALLZEROS All the bits are 0 4922 #define LRFDMDM_DEMMAFI2_C4_W 9U 4923 #define LRFDMDM_DEMMAFI2_C4_M 0x000001FFU 4924 #define LRFDMDM_DEMMAFI2_C4_S 0U 4925 #define LRFDMDM_DEMMAFI2_C4_ALLONES 0x000001FFU 4926 #define LRFDMDM_DEMMAFI2_C4_ALLZEROS 0x00000000U 4927 4928 //***************************************************************************** 4929 // 4930 // Register: LRFDMDM_O_DEMC1BE0 4931 // 4932 //***************************************************************************** 4933 // Field: [15:11] MASKB 4934 // 4935 // Mask for correlator B to select the correlator length to use. 4936 // The number specifies number of nibbles (i.e. 4-bit block, which typically 4937 // corresponds to one symbol) 4938 // of the correlator holding the oldest samples that will be ignored in 4939 // computations. 4940 // When set to zero, the full 128 sample (=32 symbol) correlator length will be 4941 // used. 4942 // ENUMs: 4943 // ALLONES All the bits are 1 4944 // ALLZEROS All the bits are 0 4945 #define LRFDMDM_DEMC1BE0_MASKB_W 5U 4946 #define LRFDMDM_DEMC1BE0_MASKB_M 0x0000F800U 4947 #define LRFDMDM_DEMC1BE0_MASKB_S 11U 4948 #define LRFDMDM_DEMC1BE0_MASKB_ALLONES 0x0000F800U 4949 #define LRFDMDM_DEMC1BE0_MASKB_ALLZEROS 0x00000000U 4950 4951 // Field: [10:6] MASKA 4952 // 4953 // Mask for correlator A to select the correlator length to use. 4954 // The number specifies number of nibbles (i.e. 4-bit block, which typically 4955 // corresponds to one symbol) 4956 // of the correlator holding the oldest samples that will be ignored in 4957 // computations. 4958 // When set to zero, the full 128 sample (=32 symbol) correlator length will be 4959 // used. 4960 // ENUMs: 4961 // ALLONES All the bits are 1 4962 // ALLZEROS All the bits are 0 4963 #define LRFDMDM_DEMC1BE0_MASKA_W 5U 4964 #define LRFDMDM_DEMC1BE0_MASKA_M 0x000007C0U 4965 #define LRFDMDM_DEMC1BE0_MASKA_S 6U 4966 #define LRFDMDM_DEMC1BE0_MASKA_ALLONES 0x000007C0U 4967 #define LRFDMDM_DEMC1BE0_MASKA_ALLZEROS 0x00000000U 4968 4969 // Field: [5:4] CASCCONF 4970 // 4971 // Correlator cascade configuration 4972 // ENUMs: 4973 // PARALLEL Connect correlators in parallel 4974 // SERIAL Connect correlators in series (A -> B) 4975 // SINGLE Correlator B not used 4976 #define LRFDMDM_DEMC1BE0_CASCCONF_W 2U 4977 #define LRFDMDM_DEMC1BE0_CASCCONF_M 0x00000030U 4978 #define LRFDMDM_DEMC1BE0_CASCCONF_S 4U 4979 #define LRFDMDM_DEMC1BE0_CASCCONF_PARALLEL 0x00000020U 4980 #define LRFDMDM_DEMC1BE0_CASCCONF_SERIAL 0x00000010U 4981 #define LRFDMDM_DEMC1BE0_CASCCONF_SINGLE 0x00000000U 4982 4983 // Field: [3:0] COPYCONF 4984 // 4985 // Control auto copy of contents from corr A to corr B 4986 // ENUMs: 4987 // ALLONES All the bits are 1 4988 // ALLZEROS All the bits are 0 4989 #define LRFDMDM_DEMC1BE0_COPYCONF_W 4U 4990 #define LRFDMDM_DEMC1BE0_COPYCONF_M 0x0000000FU 4991 #define LRFDMDM_DEMC1BE0_COPYCONF_S 0U 4992 #define LRFDMDM_DEMC1BE0_COPYCONF_ALLONES 0x0000000FU 4993 #define LRFDMDM_DEMC1BE0_COPYCONF_ALLZEROS 0x00000000U 4994 4995 //***************************************************************************** 4996 // 4997 // Register: LRFDMDM_O_DEMC1BE1 4998 // 4999 //***************************************************************************** 5000 // Field: [15:8] THRESHOLDB 5001 // 5002 // Correlation threshold value for correlator B 5003 // ENUMs: 5004 // ALLONES All the bits are 1 5005 // ALLZEROS All the bits are 0 5006 #define LRFDMDM_DEMC1BE1_THRESHOLDB_W 8U 5007 #define LRFDMDM_DEMC1BE1_THRESHOLDB_M 0x0000FF00U 5008 #define LRFDMDM_DEMC1BE1_THRESHOLDB_S 8U 5009 #define LRFDMDM_DEMC1BE1_THRESHOLDB_ALLONES 0x0000FF00U 5010 #define LRFDMDM_DEMC1BE1_THRESHOLDB_ALLZEROS 0x00000000U 5011 5012 // Field: [7:0] THRESHOLDA 5013 // 5014 // Correlation threshold value for correlator A 5015 // ENUMs: 5016 // ALLONES All the bits are 1 5017 // ALLZEROS All the bits are 0 5018 #define LRFDMDM_DEMC1BE1_THRESHOLDA_W 8U 5019 #define LRFDMDM_DEMC1BE1_THRESHOLDA_M 0x000000FFU 5020 #define LRFDMDM_DEMC1BE1_THRESHOLDA_S 0U 5021 #define LRFDMDM_DEMC1BE1_THRESHOLDA_ALLONES 0x000000FFU 5022 #define LRFDMDM_DEMC1BE1_THRESHOLDA_ALLZEROS 0x00000000U 5023 5024 //***************************************************************************** 5025 // 5026 // Register: LRFDMDM_O_DEMC1BE2 5027 // 5028 //***************************************************************************** 5029 // Field: [10] PARLOADCONF 5030 // 5031 // Configuration to control peak event generation (applies to correlators A, B, 5032 // D, E) 5033 // ENUMs: 5034 // ATOD Trigger peak event only if peak is highest in 5035 // correlator since search start 5036 // ATOB Trigger peak event on all peaks above threshold 5037 #define LRFDMDM_DEMC1BE2_PARLOADCONF 0x00000400U 5038 #define LRFDMDM_DEMC1BE2_PARLOADCONF_M 0x00000400U 5039 #define LRFDMDM_DEMC1BE2_PARLOADCONF_S 10U 5040 #define LRFDMDM_DEMC1BE2_PARLOADCONF_ATOD 0x00000400U 5041 #define LRFDMDM_DEMC1BE2_PARLOADCONF_ATOB 0x00000000U 5042 5043 // Field: [9:8] PEAKCONF 5044 // 5045 // Configuration to control peak event generation (applies to correlators A, B, 5046 // D, E) 5047 // ENUMs: 5048 // BESTAB Trigger peak event for combined highest peak 5049 // search for corr "A and B" and "D and E" in 5050 // pairs 5051 // BEST Trigger peak event only if peak is highest in 5052 // correlator since search start 5053 // THRESH Trigger peak event on all peaks above threshold 5054 #define LRFDMDM_DEMC1BE2_PEAKCONF_W 2U 5055 #define LRFDMDM_DEMC1BE2_PEAKCONF_M 0x00000300U 5056 #define LRFDMDM_DEMC1BE2_PEAKCONF_S 8U 5057 #define LRFDMDM_DEMC1BE2_PEAKCONF_BESTAB 0x00000200U 5058 #define LRFDMDM_DEMC1BE2_PEAKCONF_BEST 0x00000100U 5059 #define LRFDMDM_DEMC1BE2_PEAKCONF_THRESH 0x00000000U 5060 5061 // Field: [7:0] THRESHOLDC 5062 // 5063 // Correlation threshold value for correlator C (corr C is A+B concatenated) 5064 // ENUMs: 5065 // ALLONES All the bits are 1 5066 // ALLZEROS All the bits are 0 5067 #define LRFDMDM_DEMC1BE2_THRESHOLDC_W 8U 5068 #define LRFDMDM_DEMC1BE2_THRESHOLDC_M 0x000000FFU 5069 #define LRFDMDM_DEMC1BE2_THRESHOLDC_S 0U 5070 #define LRFDMDM_DEMC1BE2_THRESHOLDC_ALLONES 0x000000FFU 5071 #define LRFDMDM_DEMC1BE2_THRESHOLDC_ALLZEROS 0x00000000U 5072 5073 //***************************************************************************** 5074 // 5075 // Register: LRFDMDM_O_SPARE0 5076 // 5077 //***************************************************************************** 5078 // Field: [15:0] VAL 5079 // 5080 // Spare register for use by firmware 5081 // ENUMs: 5082 // ALLONES All the bits are 1 5083 // ALLZEROS All the bits are 0 5084 #define LRFDMDM_SPARE0_VAL_W 16U 5085 #define LRFDMDM_SPARE0_VAL_M 0x0000FFFFU 5086 #define LRFDMDM_SPARE0_VAL_S 0U 5087 #define LRFDMDM_SPARE0_VAL_ALLONES 0x0000FFFFU 5088 #define LRFDMDM_SPARE0_VAL_ALLZEROS 0x00000000U 5089 5090 //***************************************************************************** 5091 // 5092 // Register: LRFDMDM_O_SPARE1 5093 // 5094 //***************************************************************************** 5095 // Field: [15:0] VAL 5096 // 5097 // Spare register for use by firmware 5098 // ENUMs: 5099 // ALLONES All the bits are 1 5100 // ALLZEROS All the bits are 0 5101 #define LRFDMDM_SPARE1_VAL_W 16U 5102 #define LRFDMDM_SPARE1_VAL_M 0x0000FFFFU 5103 #define LRFDMDM_SPARE1_VAL_S 0U 5104 #define LRFDMDM_SPARE1_VAL_ALLONES 0x0000FFFFU 5105 #define LRFDMDM_SPARE1_VAL_ALLZEROS 0x00000000U 5106 5107 //***************************************************************************** 5108 // 5109 // Register: LRFDMDM_O_SPARE2 5110 // 5111 //***************************************************************************** 5112 // Field: [15:0] VAL 5113 // 5114 // Spare register for use by firmware 5115 // ENUMs: 5116 // ALLONES All the bits are 1 5117 // ALLZEROS All the bits are 0 5118 #define LRFDMDM_SPARE2_VAL_W 16U 5119 #define LRFDMDM_SPARE2_VAL_M 0x0000FFFFU 5120 #define LRFDMDM_SPARE2_VAL_S 0U 5121 #define LRFDMDM_SPARE2_VAL_ALLONES 0x0000FFFFU 5122 #define LRFDMDM_SPARE2_VAL_ALLZEROS 0x00000000U 5123 5124 //***************************************************************************** 5125 // 5126 // Register: LRFDMDM_O_SPARE3 5127 // 5128 //***************************************************************************** 5129 // Field: [15:0] VAL 5130 // 5131 // Spare register for use by firmware 5132 // ENUMs: 5133 // ALLONES All the bits are 1 5134 // ALLZEROS All the bits are 0 5135 #define LRFDMDM_SPARE3_VAL_W 16U 5136 #define LRFDMDM_SPARE3_VAL_M 0x0000FFFFU 5137 #define LRFDMDM_SPARE3_VAL_S 0U 5138 #define LRFDMDM_SPARE3_VAL_ALLONES 0x0000FFFFU 5139 #define LRFDMDM_SPARE3_VAL_ALLZEROS 0x00000000U 5140 5141 //***************************************************************************** 5142 // 5143 // Register: LRFDMDM_O_DEMSWQU0 5144 // 5145 //***************************************************************************** 5146 // Field: [7] SYNCMODE 5147 // 5148 // 0: Search for A and B in parallell 5149 // ENUMs: 5150 // ONE The bit is 1 5151 // ZERO The bit is 0 5152 #define LRFDMDM_DEMSWQU0_SYNCMODE 0x00000080U 5153 #define LRFDMDM_DEMSWQU0_SYNCMODE_M 0x00000080U 5154 #define LRFDMDM_DEMSWQU0_SYNCMODE_S 7U 5155 #define LRFDMDM_DEMSWQU0_SYNCMODE_ONE 0x00000080U 5156 #define LRFDMDM_DEMSWQU0_SYNCMODE_ZERO 0x00000000U 5157 5158 // Field: [6] AUTOMAFC 5159 // 5160 // Let sync word qualifier automatically control the manual frequency offset 5161 // compensation (MAFC) block when it is running. 5162 // ENUMs: 5163 // ON Give control to sync word qualifier 5164 // OFF Keep manual control over MAFC 5165 #define LRFDMDM_DEMSWQU0_AUTOMAFC 0x00000040U 5166 #define LRFDMDM_DEMSWQU0_AUTOMAFC_M 0x00000040U 5167 #define LRFDMDM_DEMSWQU0_AUTOMAFC_S 6U 5168 #define LRFDMDM_DEMSWQU0_AUTOMAFC_ON 0x00000040U 5169 #define LRFDMDM_DEMSWQU0_AUTOMAFC_OFF 0x00000000U 5170 5171 // Field: [5] RUN 5172 // 5173 // Start/stop sync word qualifier. 5174 // ENUMs: 5175 // ON The bit is 1 5176 // OFF The bit is 0 5177 #define LRFDMDM_DEMSWQU0_RUN 0x00000020U 5178 #define LRFDMDM_DEMSWQU0_RUN_M 0x00000020U 5179 #define LRFDMDM_DEMSWQU0_RUN_S 5U 5180 #define LRFDMDM_DEMSWQU0_RUN_ON 0x00000020U 5181 #define LRFDMDM_DEMSWQU0_RUN_OFF 0x00000000U 5182 5183 // Field: [4:0] REFLEN 5184 // 5185 // Bit length of sync word qualifier reference vector, constituted by (reflen + 5186 // 1) most significant bits of sync word A and/or B. 5187 // ENUMs: 5188 // ALLONES All the bits are 1 5189 // ALLZEROS All the bits are 0 5190 #define LRFDMDM_DEMSWQU0_REFLEN_W 5U 5191 #define LRFDMDM_DEMSWQU0_REFLEN_M 0x0000001FU 5192 #define LRFDMDM_DEMSWQU0_REFLEN_S 0U 5193 #define LRFDMDM_DEMSWQU0_REFLEN_ALLONES 0x0000001FU 5194 #define LRFDMDM_DEMSWQU0_REFLEN_ALLZEROS 0x00000000U 5195 5196 //***************************************************************************** 5197 // 5198 // Register: LRFDMDM_O_DEMC1BEREF0 5199 // 5200 //***************************************************************************** 5201 // Field: [15:0] CAR15C0 5202 // 5203 // Corr A reference bits 15:0 5204 // ENUMs: 5205 // ALLONES All the bits are 1 5206 // ALLZEROS All the bits are 0 5207 #define LRFDMDM_DEMC1BEREF0_CAR15C0_W 16U 5208 #define LRFDMDM_DEMC1BEREF0_CAR15C0_M 0x0000FFFFU 5209 #define LRFDMDM_DEMC1BEREF0_CAR15C0_S 0U 5210 #define LRFDMDM_DEMC1BEREF0_CAR15C0_ALLONES 0x0000FFFFU 5211 #define LRFDMDM_DEMC1BEREF0_CAR15C0_ALLZEROS 0x00000000U 5212 5213 //***************************************************************************** 5214 // 5215 // Register: LRFDMDM_O_DEMC1BEREF1 5216 // 5217 //***************************************************************************** 5218 // Field: [15:0] CAR31C16 5219 // 5220 // Corr A reference bits 31:16 5221 // ENUMs: 5222 // ALLONES All the bits are 1 5223 // ALLZEROS All the bits are 0 5224 #define LRFDMDM_DEMC1BEREF1_CAR31C16_W 16U 5225 #define LRFDMDM_DEMC1BEREF1_CAR31C16_M 0x0000FFFFU 5226 #define LRFDMDM_DEMC1BEREF1_CAR31C16_S 0U 5227 #define LRFDMDM_DEMC1BEREF1_CAR31C16_ALLONES 0x0000FFFFU 5228 #define LRFDMDM_DEMC1BEREF1_CAR31C16_ALLZEROS 0x00000000U 5229 5230 //***************************************************************************** 5231 // 5232 // Register: LRFDMDM_O_DEMC1BEREF2 5233 // 5234 //***************************************************************************** 5235 // Field: [15:0] CBR15C0 5236 // 5237 // Corr B reference bits 15:0 5238 // ENUMs: 5239 // ALLONES All the bits are 1 5240 // ALLZEROS All the bits are 0 5241 #define LRFDMDM_DEMC1BEREF2_CBR15C0_W 16U 5242 #define LRFDMDM_DEMC1BEREF2_CBR15C0_M 0x0000FFFFU 5243 #define LRFDMDM_DEMC1BEREF2_CBR15C0_S 0U 5244 #define LRFDMDM_DEMC1BEREF2_CBR15C0_ALLONES 0x0000FFFFU 5245 #define LRFDMDM_DEMC1BEREF2_CBR15C0_ALLZEROS 0x00000000U 5246 5247 //***************************************************************************** 5248 // 5249 // Register: LRFDMDM_O_DEMC1BEREF3 5250 // 5251 //***************************************************************************** 5252 // Field: [15:0] CBR31C16 5253 // 5254 // Corr B reference bits 31:16 5255 // ENUMs: 5256 // ALLONES All the bits are 1 5257 // ALLZEROS All the bits are 0 5258 #define LRFDMDM_DEMC1BEREF3_CBR31C16_W 16U 5259 #define LRFDMDM_DEMC1BEREF3_CBR31C16_M 0x0000FFFFU 5260 #define LRFDMDM_DEMC1BEREF3_CBR31C16_S 0U 5261 #define LRFDMDM_DEMC1BEREF3_CBR31C16_ALLONES 0x0000FFFFU 5262 #define LRFDMDM_DEMC1BEREF3_CBR31C16_ALLZEROS 0x00000000U 5263 5264 //***************************************************************************** 5265 // 5266 // Register: LRFDMDM_O_MODCTRL 5267 // 5268 //***************************************************************************** 5269 // Field: [11] DSBUSEL 5270 // 5271 // Select DSBU input source. It is not valid anymore. This bitfield is reserved 5272 // for future use. 5273 // ENUMs: 5274 // ONE The bit is 1 5275 // ZERO The bit is 0 5276 #define LRFDMDM_MODCTRL_DSBUSEL 0x00000800U 5277 #define LRFDMDM_MODCTRL_DSBUSEL_M 0x00000800U 5278 #define LRFDMDM_MODCTRL_DSBUSEL_S 11U 5279 #define LRFDMDM_MODCTRL_DSBUSEL_ONE 0x00000800U 5280 #define LRFDMDM_MODCTRL_DSBUSEL_ZERO 0x00000000U 5281 5282 // Field: [10] HDISMODE 5283 // 5284 // Enable Hilbert discriminator mode for data descicion 5285 // ENUMs: 5286 // EN The bit is 1 5287 // DIS The bit is 0 5288 #define LRFDMDM_MODCTRL_HDISMODE 0x00000400U 5289 #define LRFDMDM_MODCTRL_HDISMODE_M 0x00000400U 5290 #define LRFDMDM_MODCTRL_HDISMODE_S 10U 5291 #define LRFDMDM_MODCTRL_HDISMODE_EN 0x00000400U 5292 #define LRFDMDM_MODCTRL_HDISMODE_DIS 0x00000000U 5293 5294 // Field: [9] PARBITQUALEN 5295 // 5296 // Enable Parallel Bit Qualifier (read DEMC1BEA) 5297 // ENUMs: 5298 // ON The bit is 1 5299 // OFF The bit is 0 5300 #define LRFDMDM_MODCTRL_PARBITQUALEN 0x00000200U 5301 #define LRFDMDM_MODCTRL_PARBITQUALEN_M 0x00000200U 5302 #define LRFDMDM_MODCTRL_PARBITQUALEN_S 9U 5303 #define LRFDMDM_MODCTRL_PARBITQUALEN_ON 0x00000200U 5304 #define LRFDMDM_MODCTRL_PARBITQUALEN_OFF 0x00000000U 5305 5306 // Field: [8:7] STIMMODE 5307 // 5308 // Controls STIM module for different modes 5309 // ENUMs: 5310 // EARLY STIM starts early 5311 // LATE STIM starts late 5312 // NORMAL Normal Mode 5313 #define LRFDMDM_MODCTRL_STIMMODE_W 2U 5314 #define LRFDMDM_MODCTRL_STIMMODE_M 0x00000180U 5315 #define LRFDMDM_MODCTRL_STIMMODE_S 7U 5316 #define LRFDMDM_MODCTRL_STIMMODE_EARLY 0x00000100U 5317 #define LRFDMDM_MODCTRL_STIMMODE_LATE 0x00000080U 5318 #define LRFDMDM_MODCTRL_STIMMODE_NORMAL 0x00000000U 5319 5320 // Field: [6] C1BEMODE 5321 // 5322 // Controls the C1BE mode 5323 // ENUMs: 5324 // EARLYLATE Set the C1BE in special early/late mode 5325 // NORMAL Normal mode 5326 #define LRFDMDM_MODCTRL_C1BEMODE 0x00000040U 5327 #define LRFDMDM_MODCTRL_C1BEMODE_M 0x00000040U 5328 #define LRFDMDM_MODCTRL_C1BEMODE_S 6U 5329 #define LRFDMDM_MODCTRL_C1BEMODE_EARLYLATE 0x00000040U 5330 #define LRFDMDM_MODCTRL_C1BEMODE_NORMAL 0x00000000U 5331 5332 // Field: [5] SOFTPDIFFMODE 5333 // 5334 // Enable Soft PDIFF mode for RX 5335 // ENUMs: 5336 // EN The bit is 1 5337 // DIS The bit is 0 5338 #define LRFDMDM_MODCTRL_SOFTPDIFFMODE 0x00000020U 5339 #define LRFDMDM_MODCTRL_SOFTPDIFFMODE_M 0x00000020U 5340 #define LRFDMDM_MODCTRL_SOFTPDIFFMODE_S 5U 5341 #define LRFDMDM_MODCTRL_SOFTPDIFFMODE_EN 0x00000020U 5342 #define LRFDMDM_MODCTRL_SOFTPDIFFMODE_DIS 0x00000000U 5343 5344 // Field: [4] SOFTTXENABLE 5345 // 5346 // Enable SOFT TX mode, controlled via MODSOFTTX 5347 // ENUMs: 5348 // ON The bit is 1 5349 // OFF The bit is 0 5350 #define LRFDMDM_MODCTRL_SOFTTXENABLE 0x00000010U 5351 #define LRFDMDM_MODCTRL_SOFTTXENABLE_M 0x00000010U 5352 #define LRFDMDM_MODCTRL_SOFTTXENABLE_S 4U 5353 #define LRFDMDM_MODCTRL_SOFTTXENABLE_ON 0x00000010U 5354 #define LRFDMDM_MODCTRL_SOFTTXENABLE_OFF 0x00000000U 5355 5356 // Field: [3] FECENABLE 5357 // 5358 // Global FEC modes enable 5359 // ENUMs: 5360 // ON The bit is 1 5361 // OFF The bit is 0 5362 #define LRFDMDM_MODCTRL_FECENABLE 0x00000008U 5363 #define LRFDMDM_MODCTRL_FECENABLE_M 0x00000008U 5364 #define LRFDMDM_MODCTRL_FECENABLE_S 3U 5365 #define LRFDMDM_MODCTRL_FECENABLE_ON 0x00000008U 5366 #define LRFDMDM_MODCTRL_FECENABLE_OFF 0x00000000U 5367 5368 // Field: [2] FEC5TERMINATE 5369 // 5370 // Goes into termination mode in 5Mbps TX FEC. This bitfield is not valid 5371 // anymore. 5372 // ENUMs: 5373 // ON The bit is 1 5374 // OFF The bit is 0 5375 #define LRFDMDM_MODCTRL_FEC5TERMINATE 0x00000004U 5376 #define LRFDMDM_MODCTRL_FEC5TERMINATE_M 0x00000004U 5377 #define LRFDMDM_MODCTRL_FEC5TERMINATE_S 2U 5378 #define LRFDMDM_MODCTRL_FEC5TERMINATE_ON 0x00000004U 5379 #define LRFDMDM_MODCTRL_FEC5TERMINATE_OFF 0x00000000U 5380 5381 // Field: [1] TONEINSERT 5382 // 5383 // Inserts a tone 5384 // ENUMs: 5385 // EN The bit is 1 5386 // DIS The bit is 0 5387 #define LRFDMDM_MODCTRL_TONEINSERT 0x00000002U 5388 #define LRFDMDM_MODCTRL_TONEINSERT_M 0x00000002U 5389 #define LRFDMDM_MODCTRL_TONEINSERT_S 1U 5390 #define LRFDMDM_MODCTRL_TONEINSERT_EN 0x00000002U 5391 #define LRFDMDM_MODCTRL_TONEINSERT_DIS 0x00000000U 5392 5393 // Field: [0] PREAMBLEINSERT 5394 // 5395 // Inserts preamble 5396 // ENUMs: 5397 // EN The bit is 1 5398 // DIS The bit is 0 5399 #define LRFDMDM_MODCTRL_PREAMBLEINSERT 0x00000001U 5400 #define LRFDMDM_MODCTRL_PREAMBLEINSERT_M 0x00000001U 5401 #define LRFDMDM_MODCTRL_PREAMBLEINSERT_S 0U 5402 #define LRFDMDM_MODCTRL_PREAMBLEINSERT_EN 0x00000001U 5403 #define LRFDMDM_MODCTRL_PREAMBLEINSERT_DIS 0x00000000U 5404 5405 //***************************************************************************** 5406 // 5407 // Register: LRFDMDM_O_MODPREAMBLE 5408 // 5409 //***************************************************************************** 5410 // Field: [15:0] WORD 5411 // 5412 // 16 bit preamble word pattern. The LSB is transmitted first 5413 // ENUMs: 5414 // ALLONES All the bits are 1 5415 // ALLZEROS All the bits are 0 5416 #define LRFDMDM_MODPREAMBLE_WORD_W 16U 5417 #define LRFDMDM_MODPREAMBLE_WORD_M 0x0000FFFFU 5418 #define LRFDMDM_MODPREAMBLE_WORD_S 0U 5419 #define LRFDMDM_MODPREAMBLE_WORD_ALLONES 0x0000FFFFU 5420 #define LRFDMDM_MODPREAMBLE_WORD_ALLZEROS 0x00000000U 5421 5422 //***************************************************************************** 5423 // 5424 // Register: LRFDMDM_O_DEMFRAC0 5425 // 5426 //***************************************************************************** 5427 // Field: [15:0] P15C0 5428 // 5429 // Downsampler P[15:0]. Sample rate of the output signal: Fs_out = Fs_in * P/Q. 5430 // The hardware requires the resampling factor P/Q to be in the range [1/4, 1], 5431 // i.e. only down-sampling with a factor in the range [1,4] is supported. 5432 // ENUMs: 5433 // ALLONES All the bits are 1 5434 // ALLZEROS All the bits are 0 5435 #define LRFDMDM_DEMFRAC0_P15C0_W 16U 5436 #define LRFDMDM_DEMFRAC0_P15C0_M 0x0000FFFFU 5437 #define LRFDMDM_DEMFRAC0_P15C0_S 0U 5438 #define LRFDMDM_DEMFRAC0_P15C0_ALLONES 0x0000FFFFU 5439 #define LRFDMDM_DEMFRAC0_P15C0_ALLZEROS 0x00000000U 5440 5441 //***************************************************************************** 5442 // 5443 // Register: LRFDMDM_O_DEMFRAC1 5444 // 5445 //***************************************************************************** 5446 // Field: [11:0] P27C16 5447 // 5448 // Downsampler P[27:16] 5449 // ENUMs: 5450 // ALLONES All the bits are 1 5451 // ALLZEROS All the bits are 0 5452 #define LRFDMDM_DEMFRAC1_P27C16_W 12U 5453 #define LRFDMDM_DEMFRAC1_P27C16_M 0x00000FFFU 5454 #define LRFDMDM_DEMFRAC1_P27C16_S 0U 5455 #define LRFDMDM_DEMFRAC1_P27C16_ALLONES 0x00000FFFU 5456 #define LRFDMDM_DEMFRAC1_P27C16_ALLZEROS 0x00000000U 5457 5458 //***************************************************************************** 5459 // 5460 // Register: LRFDMDM_O_DEMFRAC2 5461 // 5462 //***************************************************************************** 5463 // Field: [15:0] Q15C0 5464 // 5465 // Downsampler Q[15:0]. Sample rate of the output signal: Fs_out = Fs_in * P/Q. 5466 // The hardware requires the resampling factor P/Q to be in the range [1/4, 1], 5467 // i.e. only down-sampling with a factor in the range [1,4] is supported. 5468 // ENUMs: 5469 // ALLONES All the bits are 1 5470 // ALLZEROS All the bits are 0 5471 #define LRFDMDM_DEMFRAC2_Q15C0_W 16U 5472 #define LRFDMDM_DEMFRAC2_Q15C0_M 0x0000FFFFU 5473 #define LRFDMDM_DEMFRAC2_Q15C0_S 0U 5474 #define LRFDMDM_DEMFRAC2_Q15C0_ALLONES 0x0000FFFFU 5475 #define LRFDMDM_DEMFRAC2_Q15C0_ALLZEROS 0x00000000U 5476 5477 //***************************************************************************** 5478 // 5479 // Register: LRFDMDM_O_DEMFRAC3 5480 // 5481 //***************************************************************************** 5482 // Field: [11:0] Q27C16 5483 // 5484 // Downsampler Q[27:16] 5485 // ENUMs: 5486 // ALLONES All the bits are 1 5487 // ALLZEROS All the bits are 0 5488 #define LRFDMDM_DEMFRAC3_Q27C16_W 12U 5489 #define LRFDMDM_DEMFRAC3_Q27C16_M 0x00000FFFU 5490 #define LRFDMDM_DEMFRAC3_Q27C16_S 0U 5491 #define LRFDMDM_DEMFRAC3_Q27C16_ALLONES 0x00000FFFU 5492 #define LRFDMDM_DEMFRAC3_Q27C16_ALLZEROS 0x00000000U 5493 5494 //***************************************************************************** 5495 // 5496 // Register: LRFDMDM_O_DEMCODC1 5497 // 5498 //***************************************************************************** 5499 // Field: [12:0] COMPIVAL 5500 // 5501 // Compensation value, I branch 5502 // ENUMs: 5503 // ALLONES All the bits are 1 5504 // ALLZEROS All the bits are 0 5505 #define LRFDMDM_DEMCODC1_COMPIVAL_W 13U 5506 #define LRFDMDM_DEMCODC1_COMPIVAL_M 0x00001FFFU 5507 #define LRFDMDM_DEMCODC1_COMPIVAL_S 0U 5508 #define LRFDMDM_DEMCODC1_COMPIVAL_ALLONES 0x00001FFFU 5509 #define LRFDMDM_DEMCODC1_COMPIVAL_ALLZEROS 0x00000000U 5510 5511 //***************************************************************************** 5512 // 5513 // Register: LRFDMDM_O_DEMCODC2 5514 // 5515 //***************************************************************************** 5516 // Field: [12:0] COMPQVAL 5517 // 5518 // Compensation value, Q branch 5519 // ENUMs: 5520 // ALLONES All the bits are 1 5521 // ALLZEROS All the bits are 0 5522 #define LRFDMDM_DEMCODC2_COMPQVAL_W 13U 5523 #define LRFDMDM_DEMCODC2_COMPQVAL_M 0x00001FFFU 5524 #define LRFDMDM_DEMCODC2_COMPQVAL_S 0U 5525 #define LRFDMDM_DEMCODC2_COMPQVAL_ALLONES 0x00001FFFU 5526 #define LRFDMDM_DEMCODC2_COMPQVAL_ALLZEROS 0x00000000U 5527 5528 //***************************************************************************** 5529 // 5530 // Register: LRFDMDM_O_DEMFIDC1 5531 // 5532 //***************************************************************************** 5533 // Field: [12:0] COMPIVAL 5534 // 5535 // Compensation value for I path 5536 // ENUMs: 5537 // ALLONES All the bits are 1 5538 // ALLZEROS All the bits are 0 5539 #define LRFDMDM_DEMFIDC1_COMPIVAL_W 13U 5540 #define LRFDMDM_DEMFIDC1_COMPIVAL_M 0x00001FFFU 5541 #define LRFDMDM_DEMFIDC1_COMPIVAL_S 0U 5542 #define LRFDMDM_DEMFIDC1_COMPIVAL_ALLONES 0x00001FFFU 5543 #define LRFDMDM_DEMFIDC1_COMPIVAL_ALLZEROS 0x00000000U 5544 5545 //***************************************************************************** 5546 // 5547 // Register: LRFDMDM_O_DEMFIDC2 5548 // 5549 //***************************************************************************** 5550 // Field: [12:0] COMPQVAL 5551 // 5552 // Compensation value for Q path 5553 // ENUMs: 5554 // ALLONES All the bits are 1 5555 // ALLZEROS All the bits are 0 5556 #define LRFDMDM_DEMFIDC2_COMPQVAL_W 13U 5557 #define LRFDMDM_DEMFIDC2_COMPQVAL_M 0x00001FFFU 5558 #define LRFDMDM_DEMFIDC2_COMPQVAL_S 0U 5559 #define LRFDMDM_DEMFIDC2_COMPQVAL_ALLONES 0x00001FFFU 5560 #define LRFDMDM_DEMFIDC2_COMPQVAL_ALLZEROS 0x00000000U 5561 5562 //***************************************************************************** 5563 // 5564 // Register: LRFDMDM_O_DEMFIFE1 5565 // 5566 //***************************************************************************** 5567 // Field: [7:0] FOCFBREGVAL 5568 // 5569 // Value for feed-back compensation point (signed) 5570 // ENUMs: 5571 // ALLONES All the bits are 1 5572 // ALLZEROS All the bits are 0 5573 #define LRFDMDM_DEMFIFE1_FOCFBREGVAL_W 8U 5574 #define LRFDMDM_DEMFIFE1_FOCFBREGVAL_M 0x000000FFU 5575 #define LRFDMDM_DEMFIFE1_FOCFBREGVAL_S 0U 5576 #define LRFDMDM_DEMFIFE1_FOCFBREGVAL_ALLONES 0x000000FFU 5577 #define LRFDMDM_DEMFIFE1_FOCFBREGVAL_ALLZEROS 0x00000000U 5578 5579 //***************************************************************************** 5580 // 5581 // Register: LRFDMDM_O_DEMMAFC0 5582 // 5583 //***************************************************************************** 5584 // Field: [7:0] COMPVAL 5585 // 5586 // Value for manual compensation (signed) 5587 // ENUMs: 5588 // ALLONES All the bits are 1 5589 // ALLZEROS All the bits are 0 5590 #define LRFDMDM_DEMMAFC0_COMPVAL_W 8U 5591 #define LRFDMDM_DEMMAFC0_COMPVAL_M 0x000000FFU 5592 #define LRFDMDM_DEMMAFC0_COMPVAL_S 0U 5593 #define LRFDMDM_DEMMAFC0_COMPVAL_ALLONES 0x000000FFU 5594 #define LRFDMDM_DEMMAFC0_COMPVAL_ALLZEROS 0x00000000U 5595 5596 //***************************************************************************** 5597 // 5598 // Register: LRFDMDM_O_DEMMAFI4 5599 // 5600 //***************************************************************************** 5601 // Field: [7:0] TERMVAL 5602 // 5603 // Input value to terminate matched filter with. Writing to this register 5604 // triggers the termination. 5605 // ENUMs: 5606 // ALLONES All the bits are 1 5607 // ALLZEROS All the bits are 0 5608 #define LRFDMDM_DEMMAFI4_TERMVAL_W 8U 5609 #define LRFDMDM_DEMMAFI4_TERMVAL_M 0x000000FFU 5610 #define LRFDMDM_DEMMAFI4_TERMVAL_S 0U 5611 #define LRFDMDM_DEMMAFI4_TERMVAL_ALLONES 0x000000FFU 5612 #define LRFDMDM_DEMMAFI4_TERMVAL_ALLZEROS 0x00000000U 5613 5614 //***************************************************************************** 5615 // 5616 // Register: LRFDMDM_O_DEMSWIMBAL 5617 // 5618 //***************************************************************************** 5619 // Field: [15:8] IMBALB 5620 // 5621 // DC imbalance in sync word B, applied via SWQU upon C1BE correlator A peak 5622 // event 5623 // ENUMs: 5624 // ALLONES All the bits are 1 5625 // ALLZEROS All the bits are 0 5626 #define LRFDMDM_DEMSWIMBAL_IMBALB_W 8U 5627 #define LRFDMDM_DEMSWIMBAL_IMBALB_M 0x0000FF00U 5628 #define LRFDMDM_DEMSWIMBAL_IMBALB_S 8U 5629 #define LRFDMDM_DEMSWIMBAL_IMBALB_ALLONES 0x0000FF00U 5630 #define LRFDMDM_DEMSWIMBAL_IMBALB_ALLZEROS 0x00000000U 5631 5632 // Field: [7:0] IMBALA 5633 // 5634 // DC imbalance in sync word A, applied via SWQU upon C1BE correlator B peak 5635 // event 5636 // ENUMs: 5637 // ALLONES All the bits are 1 5638 // ALLZEROS All the bits are 0 5639 #define LRFDMDM_DEMSWIMBAL_IMBALA_W 8U 5640 #define LRFDMDM_DEMSWIMBAL_IMBALA_M 0x000000FFU 5641 #define LRFDMDM_DEMSWIMBAL_IMBALA_S 0U 5642 #define LRFDMDM_DEMSWIMBAL_IMBALA_ALLONES 0x000000FFU 5643 #define LRFDMDM_DEMSWIMBAL_IMBALA_ALLZEROS 0x00000000U 5644 5645 //***************************************************************************** 5646 // 5647 // Register: LRFDMDM_O_DEMSOFTPDIFF 5648 // 5649 //***************************************************************************** 5650 // Field: [7:0] VAL 5651 // 5652 // Replaces PDIFF output when in Soft PDIFF Mode. Can be used for manually 5653 // feeding samples (e.g. on-off-keying (OOK) samples from RFE) into the 5654 // demodulator decode stage. 5655 // ENUMs: 5656 // ALLONES All the bits are 1 5657 // ALLZEROS All the bits are 0 5658 #define LRFDMDM_DEMSOFTPDIFF_VAL_W 8U 5659 #define LRFDMDM_DEMSOFTPDIFF_VAL_M 0x000000FFU 5660 #define LRFDMDM_DEMSOFTPDIFF_VAL_S 0U 5661 #define LRFDMDM_DEMSOFTPDIFF_VAL_ALLONES 0x000000FFU 5662 #define LRFDMDM_DEMSOFTPDIFF_VAL_ALLZEROS 0x00000000U 5663 5664 //***************************************************************************** 5665 // 5666 // Register: LRFDMDM_O_DEMDEBUG 5667 // 5668 //***************************************************************************** 5669 // Field: [11:9] LOOPBACKPIN 5670 // 5671 // Choose which GPI pin is connected to loopback 5672 // ENUMs: 5673 // GPI7 GPI7 connected to loopback 5674 // GPI6 GPI6 connected to loopback 5675 // GPI5 GPI5 connected to loopback 5676 // GPI4 GPI4 connected to loopback 5677 // GPI3 GPI3 connected to loopback 5678 // GPI2 GPI2 connected to loopback 5679 // GPI1 GPI1 connected to loopback 5680 // GPI0 GPI0 connected to loopback 5681 #define LRFDMDM_DEMDEBUG_LOOPBACKPIN_W 3U 5682 #define LRFDMDM_DEMDEBUG_LOOPBACKPIN_M 0x00000E00U 5683 #define LRFDMDM_DEMDEBUG_LOOPBACKPIN_S 9U 5684 #define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI7 0x00000E00U 5685 #define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI6 0x00000C00U 5686 #define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI5 0x00000A00U 5687 #define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI4 0x00000800U 5688 #define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI3 0x00000600U 5689 #define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI2 0x00000400U 5690 #define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI1 0x00000200U 5691 #define LRFDMDM_DEMDEBUG_LOOPBACKPIN_GPI0 0x00000000U 5692 5693 // Field: [8] DECSTAGETRIGGER 5694 // 5695 // Set high to trigger event to S2R module. Need to be written low again (no HW 5696 // clear) 5697 // ENUMs: 5698 // ONE The bit is 1 5699 // ZERO The bit is 0 5700 #define LRFDMDM_DEMDEBUG_DECSTAGETRIGGER 0x00000100U 5701 #define LRFDMDM_DEMDEBUG_DECSTAGETRIGGER_M 0x00000100U 5702 #define LRFDMDM_DEMDEBUG_DECSTAGETRIGGER_S 8U 5703 #define LRFDMDM_DEMDEBUG_DECSTAGETRIGGER_ONE 0x00000100U 5704 #define LRFDMDM_DEMDEBUG_DECSTAGETRIGGER_ZERO 0x00000000U 5705 5706 // Field: [7:5] DECSTAGEDEBUG 5707 // 5708 // Selects which decode stage signal source to dump for debugging via S2R 5709 // module. 5710 // The decode stage samples are signed 8-bit samples, 5711 // packed into 32-bit words with the oldest sample as the most significant 5712 // byte. 5713 // ENUMs: 5714 // SOFD Dump SOFD output samples 5715 // STIM Dump STIM output samples 5716 // MAFC Dump MAFC output samples 5717 // C1BE Dump C1BE correlator A value (truncated to 8 LSBs 5718 // only, may overflow if correlator value is 5719 // +128). 5720 // MAFI Dump MAFI output samples 5721 // FIFE Dump PDIF output samples 5722 // PDIF Dump PDIF output samples 5723 // NOSEL No source selected 5724 #define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_W 3U 5725 #define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_M 0x000000E0U 5726 #define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_S 5U 5727 #define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_SOFD 0x000000E0U 5728 #define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_STIM 0x000000C0U 5729 #define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_MAFC 0x000000A0U 5730 #define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_C1BE 0x00000080U 5731 #define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_MAFI 0x00000060U 5732 #define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_FIFE 0x00000040U 5733 #define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_PDIF 0x00000020U 5734 #define LRFDMDM_DEMDEBUG_DECSTAGEDEBUG_NOSEL 0x00000000U 5735 5736 // Field: [4] FRONTENDTRIGGER 5737 // 5738 // Set high to trigger event to S2R module. Need to be written low again (no HW 5739 // clear) 5740 // ENUMs: 5741 // ONE The bit is 1 5742 // ZERO The bit is 0 5743 #define LRFDMDM_DEMDEBUG_FRONTENDTRIGGER 0x00000010U 5744 #define LRFDMDM_DEMDEBUG_FRONTENDTRIGGER_M 0x00000010U 5745 #define LRFDMDM_DEMDEBUG_FRONTENDTRIGGER_S 4U 5746 #define LRFDMDM_DEMDEBUG_FRONTENDTRIGGER_ONE 0x00000010U 5747 #define LRFDMDM_DEMDEBUG_FRONTENDTRIGGER_ZERO 0x00000000U 5748 5749 // Field: [3:1] FRONTENDDEBUG 5750 // 5751 // Selects which front-end stage signal source to dump for debugging via S2R 5752 // module. 5753 // The front-end stage samples are signed 16-bit samples from both I and Q 5754 // signal path, 5755 // packed together into 32-bit words with the I sample as the 16 MSB and Q 5756 // sample as the 16 LSB. 5757 // ENUMs: 5758 // FIDC Dump FRAC output samples 5759 // FRAC Dump FRAC output samples 5760 // CHFI Dump CHFI output samples 5761 // BDE2 Dump BDE2 output samples 5762 // FEXB2 Dump FEXB output #2 samples, as selected by 5763 // DEMFEXB0.OUT2SRCSEL register 5764 // BDE1 Dump BDE1 output samples 5765 // IQMC Dump IQMC output samples 5766 // NOSEL No source selected 5767 #define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_W 3U 5768 #define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_M 0x0000000EU 5769 #define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_S 1U 5770 #define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_FIDC 0x0000000EU 5771 #define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_FRAC 0x0000000CU 5772 #define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_CHFI 0x0000000AU 5773 #define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_BDE2 0x00000008U 5774 #define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_FEXB2 0x00000006U 5775 #define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_BDE1 0x00000004U 5776 #define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_IQMC 0x00000002U 5777 #define LRFDMDM_DEMDEBUG_FRONTENDDEBUG_NOSEL 0x00000000U 5778 5779 // Field: [0] LOOPBACKMODE 5780 // 5781 // Enables loopback mode 5782 // ENUMs: 5783 // ONE The bit is 1 5784 // ZERO The bit is 0 5785 #define LRFDMDM_DEMDEBUG_LOOPBACKMODE 0x00000001U 5786 #define LRFDMDM_DEMDEBUG_LOOPBACKMODE_M 0x00000001U 5787 #define LRFDMDM_DEMDEBUG_LOOPBACKMODE_S 0U 5788 #define LRFDMDM_DEMDEBUG_LOOPBACKMODE_ONE 0x00000001U 5789 #define LRFDMDM_DEMDEBUG_LOOPBACKMODE_ZERO 0x00000000U 5790 5791 //***************************************************************************** 5792 // 5793 // Register: LRFDMDM_O_VITCTRL 5794 // 5795 //***************************************************************************** 5796 // Field: [7:6] METRSEL 5797 // 5798 // Selects which HW module is connected to viterbi decoder 5799 // ENUMs: 5800 // MLSE Use MLSE Metrics 5801 // SOFD Use SOFD Metrics 5802 // PHAC Use PHAC Metrics 5803 // MET5M Use 5Mbps Metrics 5804 #define LRFDMDM_VITCTRL_METRSEL_W 2U 5805 #define LRFDMDM_VITCTRL_METRSEL_M 0x000000C0U 5806 #define LRFDMDM_VITCTRL_METRSEL_S 6U 5807 #define LRFDMDM_VITCTRL_METRSEL_MLSE 0x000000C0U 5808 #define LRFDMDM_VITCTRL_METRSEL_SOFD 0x00000080U 5809 #define LRFDMDM_VITCTRL_METRSEL_PHAC 0x00000040U 5810 #define LRFDMDM_VITCTRL_METRSEL_MET5M 0x00000000U 5811 5812 // Field: [5:2] APMRDBACKSEL 5813 // 5814 // Selects the APM to read back via VITAPMRDBACK register. 5815 // ENUMs: 5816 // APM7 View APM 7 5817 // APM6 View APM 6 5818 // APM5 View APM 5 5819 // APM4 View APM 4 5820 // APM3 View APM 3 5821 // APM2 View APM 2 5822 // APM1 View APM 1 5823 // APM0 View APM 0 5824 // NOSEL No selection 5825 #define LRFDMDM_VITCTRL_APMRDBACKSEL_W 4U 5826 #define LRFDMDM_VITCTRL_APMRDBACKSEL_M 0x0000003CU 5827 #define LRFDMDM_VITCTRL_APMRDBACKSEL_S 2U 5828 #define LRFDMDM_VITCTRL_APMRDBACKSEL_APM7 0x0000003CU 5829 #define LRFDMDM_VITCTRL_APMRDBACKSEL_APM6 0x00000038U 5830 #define LRFDMDM_VITCTRL_APMRDBACKSEL_APM5 0x00000034U 5831 #define LRFDMDM_VITCTRL_APMRDBACKSEL_APM4 0x00000030U 5832 #define LRFDMDM_VITCTRL_APMRDBACKSEL_APM3 0x0000002CU 5833 #define LRFDMDM_VITCTRL_APMRDBACKSEL_APM2 0x00000028U 5834 #define LRFDMDM_VITCTRL_APMRDBACKSEL_APM1 0x00000024U 5835 #define LRFDMDM_VITCTRL_APMRDBACKSEL_APM0 0x00000020U 5836 #define LRFDMDM_VITCTRL_APMRDBACKSEL_NOSEL 0x00000000U 5837 5838 // Field: [1] ACSITERATIONS 5839 // 5840 // Number of iterations per ACS element 5841 // ENUMs: 5842 // CODE23 4 iterations per ACS (4 branches, 2/3 codes) 5843 // CODE12 2 iterations per ACS (2 branches, 1/2 codes) 5844 #define LRFDMDM_VITCTRL_ACSITERATIONS 0x00000002U 5845 #define LRFDMDM_VITCTRL_ACSITERATIONS_M 0x00000002U 5846 #define LRFDMDM_VITCTRL_ACSITERATIONS_S 1U 5847 #define LRFDMDM_VITCTRL_ACSITERATIONS_CODE23 0x00000002U 5848 #define LRFDMDM_VITCTRL_ACSITERATIONS_CODE12 0x00000000U 5849 5850 // Field: [0] METRICS 5851 // 5852 // Select Metrics 5853 // ENUMs: 5854 // SOFT Use soft Metrics (register based) 5855 // HW Use HW metrics as defined by VITCTRL.METRSEL bits 5856 #define LRFDMDM_VITCTRL_METRICS 0x00000001U 5857 #define LRFDMDM_VITCTRL_METRICS_M 0x00000001U 5858 #define LRFDMDM_VITCTRL_METRICS_S 0U 5859 #define LRFDMDM_VITCTRL_METRICS_SOFT 0x00000001U 5860 #define LRFDMDM_VITCTRL_METRICS_HW 0x00000000U 5861 5862 //***************************************************************************** 5863 // 5864 // Register: LRFDMDM_O_VITCOMPUTE 5865 // 5866 //***************************************************************************** 5867 // Field: [0] START 5868 // 5869 // Initiates a compute cycle 5870 // ENUMs: 5871 // ONE The bit is 1 5872 // ZERO The bit is 0 5873 #define LRFDMDM_VITCOMPUTE_START 0x00000001U 5874 #define LRFDMDM_VITCOMPUTE_START_M 0x00000001U 5875 #define LRFDMDM_VITCOMPUTE_START_S 0U 5876 #define LRFDMDM_VITCOMPUTE_START_ONE 0x00000001U 5877 #define LRFDMDM_VITCOMPUTE_START_ZERO 0x00000000U 5878 5879 //***************************************************************************** 5880 // 5881 // Register: LRFDMDM_O_VITAPMRDBACK 5882 // 5883 //***************************************************************************** 5884 // Field: [9:0] VALUE 5885 // 5886 // APM for element i (selected in VITCTRL register). 5887 // ENUMs: 5888 // ALLONES All the bits are 1 5889 // ALLZEROS All the bits are 0 5890 #define LRFDMDM_VITAPMRDBACK_VALUE_W 10U 5891 #define LRFDMDM_VITAPMRDBACK_VALUE_M 0x000003FFU 5892 #define LRFDMDM_VITAPMRDBACK_VALUE_S 0U 5893 #define LRFDMDM_VITAPMRDBACK_VALUE_ALLONES 0x000003FFU 5894 #define LRFDMDM_VITAPMRDBACK_VALUE_ALLZEROS 0x00000000U 5895 5896 //***************************************************************************** 5897 // 5898 // Register: LRFDMDM_O_VITSTATE 5899 // 5900 //***************************************************************************** 5901 // Field: [2:0] VALUE 5902 // 5903 // Current Winning State 5904 // ENUMs: 5905 // ALLONES All the bits are 1 5906 // ALLZEROS All the bits are 0 5907 #define LRFDMDM_VITSTATE_VALUE_W 3U 5908 #define LRFDMDM_VITSTATE_VALUE_M 0x00000007U 5909 #define LRFDMDM_VITSTATE_VALUE_S 0U 5910 #define LRFDMDM_VITSTATE_VALUE_ALLONES 0x00000007U 5911 #define LRFDMDM_VITSTATE_VALUE_ALLZEROS 0x00000000U 5912 5913 //***************************************************************************** 5914 // 5915 // Register: LRFDMDM_O_VITBRMETRIC10 5916 // 5917 //***************************************************************************** 5918 // Field: [15:8] MET1 5919 // 5920 // Branch Metric 1 5921 // ENUMs: 5922 // ALLONES All the bits are 1 5923 // ALLZEROS All the bits are 0 5924 #define LRFDMDM_VITBRMETRIC10_MET1_W 8U 5925 #define LRFDMDM_VITBRMETRIC10_MET1_M 0x0000FF00U 5926 #define LRFDMDM_VITBRMETRIC10_MET1_S 8U 5927 #define LRFDMDM_VITBRMETRIC10_MET1_ALLONES 0x0000FF00U 5928 #define LRFDMDM_VITBRMETRIC10_MET1_ALLZEROS 0x00000000U 5929 5930 // Field: [7:0] MET0 5931 // 5932 // Branch Metric 0 5933 // ENUMs: 5934 // ALLONES All the bits are 1 5935 // ALLZEROS All the bits are 0 5936 #define LRFDMDM_VITBRMETRIC10_MET0_W 8U 5937 #define LRFDMDM_VITBRMETRIC10_MET0_M 0x000000FFU 5938 #define LRFDMDM_VITBRMETRIC10_MET0_S 0U 5939 #define LRFDMDM_VITBRMETRIC10_MET0_ALLONES 0x000000FFU 5940 #define LRFDMDM_VITBRMETRIC10_MET0_ALLZEROS 0x00000000U 5941 5942 //***************************************************************************** 5943 // 5944 // Register: LRFDMDM_O_VITBRMETRIC32 5945 // 5946 //***************************************************************************** 5947 // Field: [15:8] MET3 5948 // 5949 // Branch Metric 3 5950 // ENUMs: 5951 // ALLONES All the bits are 1 5952 // ALLZEROS All the bits are 0 5953 #define LRFDMDM_VITBRMETRIC32_MET3_W 8U 5954 #define LRFDMDM_VITBRMETRIC32_MET3_M 0x0000FF00U 5955 #define LRFDMDM_VITBRMETRIC32_MET3_S 8U 5956 #define LRFDMDM_VITBRMETRIC32_MET3_ALLONES 0x0000FF00U 5957 #define LRFDMDM_VITBRMETRIC32_MET3_ALLZEROS 0x00000000U 5958 5959 // Field: [7:0] MET2 5960 // 5961 // Branch Metric 2 5962 // ENUMs: 5963 // ALLONES All the bits are 1 5964 // ALLZEROS All the bits are 0 5965 #define LRFDMDM_VITBRMETRIC32_MET2_W 8U 5966 #define LRFDMDM_VITBRMETRIC32_MET2_M 0x000000FFU 5967 #define LRFDMDM_VITBRMETRIC32_MET2_S 0U 5968 #define LRFDMDM_VITBRMETRIC32_MET2_ALLONES 0x000000FFU 5969 #define LRFDMDM_VITBRMETRIC32_MET2_ALLZEROS 0x00000000U 5970 5971 //***************************************************************************** 5972 // 5973 // Register: LRFDMDM_O_VITBRMETRIC54 5974 // 5975 //***************************************************************************** 5976 // Field: [15:8] MET5 5977 // 5978 // Branch Metric 5 5979 // ENUMs: 5980 // ALLONES All the bits are 1 5981 // ALLZEROS All the bits are 0 5982 #define LRFDMDM_VITBRMETRIC54_MET5_W 8U 5983 #define LRFDMDM_VITBRMETRIC54_MET5_M 0x0000FF00U 5984 #define LRFDMDM_VITBRMETRIC54_MET5_S 8U 5985 #define LRFDMDM_VITBRMETRIC54_MET5_ALLONES 0x0000FF00U 5986 #define LRFDMDM_VITBRMETRIC54_MET5_ALLZEROS 0x00000000U 5987 5988 // Field: [7:0] MET4 5989 // 5990 // Branch Metric 4 5991 // ENUMs: 5992 // ALLONES All the bits are 1 5993 // ALLZEROS All the bits are 0 5994 #define LRFDMDM_VITBRMETRIC54_MET4_W 8U 5995 #define LRFDMDM_VITBRMETRIC54_MET4_M 0x000000FFU 5996 #define LRFDMDM_VITBRMETRIC54_MET4_S 0U 5997 #define LRFDMDM_VITBRMETRIC54_MET4_ALLONES 0x000000FFU 5998 #define LRFDMDM_VITBRMETRIC54_MET4_ALLZEROS 0x00000000U 5999 6000 //***************************************************************************** 6001 // 6002 // Register: LRFDMDM_O_VITBRMETRIC76 6003 // 6004 //***************************************************************************** 6005 // Field: [15:8] MET7 6006 // 6007 // Branch Metric 7 6008 // ENUMs: 6009 // ALLONES All the bits are 1 6010 // ALLZEROS All the bits are 0 6011 #define LRFDMDM_VITBRMETRIC76_MET7_W 8U 6012 #define LRFDMDM_VITBRMETRIC76_MET7_M 0x0000FF00U 6013 #define LRFDMDM_VITBRMETRIC76_MET7_S 8U 6014 #define LRFDMDM_VITBRMETRIC76_MET7_ALLONES 0x0000FF00U 6015 #define LRFDMDM_VITBRMETRIC76_MET7_ALLZEROS 0x00000000U 6016 6017 // Field: [7:0] MET6 6018 // 6019 // Branch Metric 6 6020 // ENUMs: 6021 // ALLONES All the bits are 1 6022 // ALLZEROS All the bits are 0 6023 #define LRFDMDM_VITBRMETRIC76_MET6_W 8U 6024 #define LRFDMDM_VITBRMETRIC76_MET6_M 0x000000FFU 6025 #define LRFDMDM_VITBRMETRIC76_MET6_S 0U 6026 #define LRFDMDM_VITBRMETRIC76_MET6_ALLONES 0x000000FFU 6027 #define LRFDMDM_VITBRMETRIC76_MET6_ALLZEROS 0x00000000U 6028 6029 //***************************************************************************** 6030 // 6031 // Register: LRFDMDM_O_TIMCTL 6032 // 6033 //***************************************************************************** 6034 // Field: [13:8] CPTSRC 6035 // 6036 // Selects bit number from event bus for a counter capture. Event number in 6037 // range 0 to 63 6038 // ENUMs: 6039 // ALLONES All the bits are 1 6040 // ALLZEROS All the bits are 0 6041 #define LRFDMDM_TIMCTL_CPTSRC_W 6U 6042 #define LRFDMDM_TIMCTL_CPTSRC_M 0x00003F00U 6043 #define LRFDMDM_TIMCTL_CPTSRC_S 8U 6044 #define LRFDMDM_TIMCTL_CPTSRC_ALLONES 0x00003F00U 6045 #define LRFDMDM_TIMCTL_CPTSRC_ALLZEROS 0x00000000U 6046 6047 // Field: [7] CPTCTL 6048 // 6049 // Enable counter capture on event. Upon a capture event, the counter value 6050 // will be captured in TIMCAPT register. 6051 // ENUMs: 6052 // EN Enable capture mode for counter 6053 // DIS Disable capture mode for counter 6054 #define LRFDMDM_TIMCTL_CPTCTL 0x00000080U 6055 #define LRFDMDM_TIMCTL_CPTCTL_M 0x00000080U 6056 #define LRFDMDM_TIMCTL_CPTCTL_S 7U 6057 #define LRFDMDM_TIMCTL_CPTCTL_EN 0x00000080U 6058 #define LRFDMDM_TIMCTL_CPTCTL_DIS 0x00000000U 6059 6060 // Field: [6:5] CNTRSRC 6061 // 6062 // Select event source for counter 6063 // ENUMs: 6064 // CLK4BAUDF Use 4xBaud flushed event 6065 // CLK4BAUD Use 4xBaud event 6066 // CLKBAUD Use baud event 6067 // CLK Use clock 6068 #define LRFDMDM_TIMCTL_CNTRSRC_W 2U 6069 #define LRFDMDM_TIMCTL_CNTRSRC_M 0x00000060U 6070 #define LRFDMDM_TIMCTL_CNTRSRC_S 5U 6071 #define LRFDMDM_TIMCTL_CNTRSRC_CLK4BAUDF 0x00000060U 6072 #define LRFDMDM_TIMCTL_CNTRSRC_CLK4BAUD 0x00000040U 6073 #define LRFDMDM_TIMCTL_CNTRSRC_CLKBAUD 0x00000020U 6074 #define LRFDMDM_TIMCTL_CNTRSRC_CLK 0x00000000U 6075 6076 // Field: [4] CNTRCLR 6077 // 6078 // Clear counter value in TIMCNT to zero when this bit is set to 1. 6079 // ENUMs: 6080 // ONE The bit is 1 6081 // ZERO The bit is 0 6082 #define LRFDMDM_TIMCTL_CNTRCLR 0x00000010U 6083 #define LRFDMDM_TIMCTL_CNTRCLR_M 0x00000010U 6084 #define LRFDMDM_TIMCTL_CNTRCLR_S 4U 6085 #define LRFDMDM_TIMCTL_CNTRCLR_ONE 0x00000010U 6086 #define LRFDMDM_TIMCTL_CNTRCLR_ZERO 0x00000000U 6087 6088 // Field: [3] CNTRCTL 6089 // 6090 // Enable 16-bit counter when set to 1. The counter will continue from its 6091 // current value. 6092 // ENUMs: 6093 // ONE The bit is 1 6094 // ZERO The bit is 0 6095 #define LRFDMDM_TIMCTL_CNTRCTL 0x00000008U 6096 #define LRFDMDM_TIMCTL_CNTRCTL_M 0x00000008U 6097 #define LRFDMDM_TIMCTL_CNTRCTL_S 3U 6098 #define LRFDMDM_TIMCTL_CNTRCTL_ONE 0x00000008U 6099 #define LRFDMDM_TIMCTL_CNTRCTL_ZERO 0x00000000U 6100 6101 // Field: [2:1] TIMSRC 6102 // 6103 // Select timer tick source for timer 6104 // ENUMs: 6105 // CLK4BAUDF 4xBaud flushed 6106 // CLK4BAUD 4xBaud 6107 // CLKBAUD Baud 6108 // CLK Clock 6109 #define LRFDMDM_TIMCTL_TIMSRC_W 2U 6110 #define LRFDMDM_TIMCTL_TIMSRC_M 0x00000006U 6111 #define LRFDMDM_TIMCTL_TIMSRC_S 1U 6112 #define LRFDMDM_TIMCTL_TIMSRC_CLK4BAUDF 0x00000006U 6113 #define LRFDMDM_TIMCTL_TIMSRC_CLK4BAUD 0x00000004U 6114 #define LRFDMDM_TIMCTL_TIMSRC_CLKBAUD 0x00000002U 6115 #define LRFDMDM_TIMCTL_TIMSRC_CLK 0x00000000U 6116 6117 // Field: [0] TIMCTL 6118 // 6119 // Enable 16-bit timer. It will generate a timer interrupt after TIMPER timer 6120 // ticks. 6121 // Note that the internal timer value is not readable from the MCE. If this is 6122 // needed the counter should be used instead of the timer. 6123 // ENUMs: 6124 // EN Will enable timer 6125 // DIS Will disable timer and clear internal timer value 6126 #define LRFDMDM_TIMCTL_TIMCTL 0x00000001U 6127 #define LRFDMDM_TIMCTL_TIMCTL_M 0x00000001U 6128 #define LRFDMDM_TIMCTL_TIMCTL_S 0U 6129 #define LRFDMDM_TIMCTL_TIMCTL_EN 0x00000001U 6130 #define LRFDMDM_TIMCTL_TIMCTL_DIS 0x00000000U 6131 6132 //***************************************************************************** 6133 // 6134 // Register: LRFDMDM_O_TIMINC 6135 // 6136 //***************************************************************************** 6137 // Field: [15:0] VAL 6138 // 6139 // Programmable counter increment. For each counter event: TIMCNT + 1). 6140 // ENUMs: 6141 // ALLONES All the bits are 1 6142 // ALLZEROS All the bits are 0 6143 #define LRFDMDM_TIMINC_VAL_W 16U 6144 #define LRFDMDM_TIMINC_VAL_M 0x0000FFFFU 6145 #define LRFDMDM_TIMINC_VAL_S 0U 6146 #define LRFDMDM_TIMINC_VAL_ALLONES 0x0000FFFFU 6147 #define LRFDMDM_TIMINC_VAL_ALLZEROS 0x00000000U 6148 6149 //***************************************************************************** 6150 // 6151 // Register: LRFDMDM_O_TIMPER 6152 // 6153 //***************************************************************************** 6154 // Field: [15:0] VAL 6155 // 6156 // Configurable 16 bit period that can be used for either the timer or the 6157 // counter. 6158 // In timer context, when timer value reach the timer period (i.e. it expires) 6159 // a TIMER_IRQ event will occur, 6160 // and the timer will restart from zero (until the timer is manually disabled). 6161 // In counter context, a COUNTER_IRQ event will occur when the counter is equal 6162 // to or higher than the period value. 6163 // ENUMs: 6164 // ALLONES All the bits are 1 6165 // ALLZEROS All the bits are 0 6166 #define LRFDMDM_TIMPER_VAL_W 16U 6167 #define LRFDMDM_TIMPER_VAL_M 0x0000FFFFU 6168 #define LRFDMDM_TIMPER_VAL_S 0U 6169 #define LRFDMDM_TIMPER_VAL_ALLONES 0x0000FFFFU 6170 #define LRFDMDM_TIMPER_VAL_ALLZEROS 0x00000000U 6171 6172 //***************************************************************************** 6173 // 6174 // Register: LRFDMDM_O_TIMCNT 6175 // 6176 //***************************************************************************** 6177 // Field: [15:0] VAL 6178 // 6179 // 16 bit counter value that can be read by the MCE 6180 // ENUMs: 6181 // ALLONES All the bits are 1 6182 // ALLZEROS All the bits are 0 6183 #define LRFDMDM_TIMCNT_VAL_W 16U 6184 #define LRFDMDM_TIMCNT_VAL_M 0x0000FFFFU 6185 #define LRFDMDM_TIMCNT_VAL_S 0U 6186 #define LRFDMDM_TIMCNT_VAL_ALLONES 0x0000FFFFU 6187 #define LRFDMDM_TIMCNT_VAL_ALLZEROS 0x00000000U 6188 6189 //***************************************************************************** 6190 // 6191 // Register: LRFDMDM_O_TIMCAPT 6192 // 6193 //***************************************************************************** 6194 // Field: [15:0] VALUE 6195 // 6196 // Captured value of counter 6197 // ENUMs: 6198 // ALLONES All the bits are 1 6199 // ALLZEROS All the bits are 0 6200 #define LRFDMDM_TIMCAPT_VALUE_W 16U 6201 #define LRFDMDM_TIMCAPT_VALUE_M 0x0000FFFFU 6202 #define LRFDMDM_TIMCAPT_VALUE_S 0U 6203 #define LRFDMDM_TIMCAPT_VALUE_ALLONES 0x0000FFFFU 6204 #define LRFDMDM_TIMCAPT_VALUE_ALLZEROS 0x00000000U 6205 6206 //***************************************************************************** 6207 // 6208 // Register: LRFDMDM_O_TIMEBASE 6209 // 6210 //***************************************************************************** 6211 // Field: [0] FLUSH 6212 // 6213 // Starts a flushing process 6214 // ENUMs: 6215 // ONE The bit is 1 6216 // ZERO The bit is 0 6217 #define LRFDMDM_TIMEBASE_FLUSH 0x00000001U 6218 #define LRFDMDM_TIMEBASE_FLUSH_M 0x00000001U 6219 #define LRFDMDM_TIMEBASE_FLUSH_S 0U 6220 #define LRFDMDM_TIMEBASE_FLUSH_ONE 0x00000001U 6221 #define LRFDMDM_TIMEBASE_FLUSH_ZERO 0x00000000U 6222 6223 //***************************************************************************** 6224 // 6225 // Register: LRFDMDM_O_COUNT1IN 6226 // 6227 //***************************************************************************** 6228 // Field: [15:0] VAL 6229 // 6230 // Input data, which we shall find the number of 1's in 6231 // ENUMs: 6232 // ALLONES All the bits are 1 6233 // ALLZEROS All the bits are 0 6234 #define LRFDMDM_COUNT1IN_VAL_W 16U 6235 #define LRFDMDM_COUNT1IN_VAL_M 0x0000FFFFU 6236 #define LRFDMDM_COUNT1IN_VAL_S 0U 6237 #define LRFDMDM_COUNT1IN_VAL_ALLONES 0x0000FFFFU 6238 #define LRFDMDM_COUNT1IN_VAL_ALLZEROS 0x00000000U 6239 6240 //***************************************************************************** 6241 // 6242 // Register: LRFDMDM_O_COUNT1RES 6243 // 6244 //***************************************************************************** 6245 // Field: [4:0] VAL 6246 // 6247 // Number of 1's in the COUNT1IN register 6248 // ENUMs: 6249 // ALLONES All the bits are 1 6250 // ALLZEROS All the bits are 0 6251 #define LRFDMDM_COUNT1RES_VAL_W 5U 6252 #define LRFDMDM_COUNT1RES_VAL_M 0x0000001FU 6253 #define LRFDMDM_COUNT1RES_VAL_S 0U 6254 #define LRFDMDM_COUNT1RES_VAL_ALLONES 0x0000001FU 6255 #define LRFDMDM_COUNT1RES_VAL_ALLZEROS 0x00000000U 6256 6257 //***************************************************************************** 6258 // 6259 // Register: LRFDMDM_O_BRMACC1 6260 // 6261 //***************************************************************************** 6262 // Field: [15:8] METRIC01 6263 // 6264 // Metric to 01 (-1 +1) symbol. Immediately calculated when BRMACC0 register is 6265 // written. 6266 // ENUMs: 6267 // ALLONES All the bits are 1 6268 // ALLZEROS All the bits are 0 6269 #define LRFDMDM_BRMACC1_METRIC01_W 8U 6270 #define LRFDMDM_BRMACC1_METRIC01_M 0x0000FF00U 6271 #define LRFDMDM_BRMACC1_METRIC01_S 8U 6272 #define LRFDMDM_BRMACC1_METRIC01_ALLONES 0x0000FF00U 6273 #define LRFDMDM_BRMACC1_METRIC01_ALLZEROS 0x00000000U 6274 6275 // Field: [7:0] METRIC00 6276 // 6277 // Metric to 00 (-1 -1) symbol. Immediately calculated when BRMACC0 register is 6278 // written. 6279 // ENUMs: 6280 // ALLONES All the bits are 1 6281 // ALLZEROS All the bits are 0 6282 #define LRFDMDM_BRMACC1_METRIC00_W 8U 6283 #define LRFDMDM_BRMACC1_METRIC00_M 0x000000FFU 6284 #define LRFDMDM_BRMACC1_METRIC00_S 0U 6285 #define LRFDMDM_BRMACC1_METRIC00_ALLONES 0x000000FFU 6286 #define LRFDMDM_BRMACC1_METRIC00_ALLZEROS 0x00000000U 6287 6288 //***************************************************************************** 6289 // 6290 // Register: LRFDMDM_O_BRMACC2 6291 // 6292 //***************************************************************************** 6293 // Field: [15:8] METRIC11 6294 // 6295 // Metric to 11 (+1 +1) symbol. Immediately calculated when BRMACC0 register is 6296 // written. 6297 // ENUMs: 6298 // ALLONES All the bits are 1 6299 // ALLZEROS All the bits are 0 6300 #define LRFDMDM_BRMACC2_METRIC11_W 8U 6301 #define LRFDMDM_BRMACC2_METRIC11_M 0x0000FF00U 6302 #define LRFDMDM_BRMACC2_METRIC11_S 8U 6303 #define LRFDMDM_BRMACC2_METRIC11_ALLONES 0x0000FF00U 6304 #define LRFDMDM_BRMACC2_METRIC11_ALLZEROS 0x00000000U 6305 6306 // Field: [7:0] METRIC10 6307 // 6308 // Metric to 10 (+1 -1) symbol. Immediately calculated when BRMACC0 register is 6309 // written. 6310 // ENUMs: 6311 // ALLONES All the bits are 1 6312 // ALLZEROS All the bits are 0 6313 #define LRFDMDM_BRMACC2_METRIC10_W 8U 6314 #define LRFDMDM_BRMACC2_METRIC10_M 0x000000FFU 6315 #define LRFDMDM_BRMACC2_METRIC10_S 0U 6316 #define LRFDMDM_BRMACC2_METRIC10_ALLONES 0x000000FFU 6317 #define LRFDMDM_BRMACC2_METRIC10_ALLZEROS 0x00000000U 6318 6319 //***************************************************************************** 6320 // 6321 // Register: LRFDMDM_O_MCETRCCTRL 6322 // 6323 //***************************************************************************** 6324 // Field: [0] SEND 6325 // 6326 // Sends a command to the tracer 6327 // ENUMs: 6328 // ONE The bit is 1 6329 // ZERO The bit is 0 6330 #define LRFDMDM_MCETRCCTRL_SEND 0x00000001U 6331 #define LRFDMDM_MCETRCCTRL_SEND_M 0x00000001U 6332 #define LRFDMDM_MCETRCCTRL_SEND_S 0U 6333 #define LRFDMDM_MCETRCCTRL_SEND_ONE 0x00000001U 6334 #define LRFDMDM_MCETRCCTRL_SEND_ZERO 0x00000000U 6335 6336 //***************************************************************************** 6337 // 6338 // Register: LRFDMDM_O_MCETRCSTAT 6339 // 6340 //***************************************************************************** 6341 // Field: [0] BUSY 6342 // 6343 // Checks if the tracer is busy 6344 // ENUMs: 6345 // ONE The bit is 1 6346 // ZERO The bit is 0 6347 #define LRFDMDM_MCETRCSTAT_BUSY 0x00000001U 6348 #define LRFDMDM_MCETRCSTAT_BUSY_M 0x00000001U 6349 #define LRFDMDM_MCETRCSTAT_BUSY_S 0U 6350 #define LRFDMDM_MCETRCSTAT_BUSY_ONE 0x00000001U 6351 #define LRFDMDM_MCETRCSTAT_BUSY_ZERO 0x00000000U 6352 6353 //***************************************************************************** 6354 // 6355 // Register: LRFDMDM_O_MCETRCCMD 6356 // 6357 //***************************************************************************** 6358 // Field: [9:8] PARCNT 6359 // 6360 // Number of parameters 6361 // ENUMs: 6362 // ALLONES All the bits are 1 6363 // ALLZEROS All the bits are 0 6364 #define LRFDMDM_MCETRCCMD_PARCNT_W 2U 6365 #define LRFDMDM_MCETRCCMD_PARCNT_M 0x00000300U 6366 #define LRFDMDM_MCETRCCMD_PARCNT_S 8U 6367 #define LRFDMDM_MCETRCCMD_PARCNT_ALLONES 0x00000300U 6368 #define LRFDMDM_MCETRCCMD_PARCNT_ALLZEROS 0x00000000U 6369 6370 // Field: [7:0] PKTHDR 6371 // 6372 // Packet header 6373 // ENUMs: 6374 // ALLONES All the bits are 1 6375 // ALLZEROS All the bits are 0 6376 #define LRFDMDM_MCETRCCMD_PKTHDR_W 8U 6377 #define LRFDMDM_MCETRCCMD_PKTHDR_M 0x000000FFU 6378 #define LRFDMDM_MCETRCCMD_PKTHDR_S 0U 6379 #define LRFDMDM_MCETRCCMD_PKTHDR_ALLONES 0x000000FFU 6380 #define LRFDMDM_MCETRCCMD_PKTHDR_ALLZEROS 0x00000000U 6381 6382 //***************************************************************************** 6383 // 6384 // Register: LRFDMDM_O_MCETRCPAR0 6385 // 6386 //***************************************************************************** 6387 // Field: [15:0] VAL 6388 // 6389 // Parameter 0 6390 // ENUMs: 6391 // ALLONES All the bits are 1 6392 // ALLZEROS All the bits are 0 6393 #define LRFDMDM_MCETRCPAR0_VAL_W 16U 6394 #define LRFDMDM_MCETRCPAR0_VAL_M 0x0000FFFFU 6395 #define LRFDMDM_MCETRCPAR0_VAL_S 0U 6396 #define LRFDMDM_MCETRCPAR0_VAL_ALLONES 0x0000FFFFU 6397 #define LRFDMDM_MCETRCPAR0_VAL_ALLZEROS 0x00000000U 6398 6399 //***************************************************************************** 6400 // 6401 // Register: LRFDMDM_O_MCETRCPAR1 6402 // 6403 //***************************************************************************** 6404 // Field: [15:0] VAL 6405 // 6406 // Parameter 1 6407 // ENUMs: 6408 // ALLONES All the bits are 1 6409 // ALLZEROS All the bits are 0 6410 #define LRFDMDM_MCETRCPAR1_VAL_W 16U 6411 #define LRFDMDM_MCETRCPAR1_VAL_M 0x0000FFFFU 6412 #define LRFDMDM_MCETRCPAR1_VAL_S 0U 6413 #define LRFDMDM_MCETRCPAR1_VAL_ALLONES 0x0000FFFFU 6414 #define LRFDMDM_MCETRCPAR1_VAL_ALLZEROS 0x00000000U 6415 6416 //***************************************************************************** 6417 // 6418 // Register: LRFDMDM_O_RDCAPT0 6419 // 6420 //***************************************************************************** 6421 // Field: [5] CHFI 6422 // 6423 // Capture CHFI output samples into FECAPT0 and FECAPT1. 6424 // ENUMs: 6425 // ONE The bit is 1 6426 // ZERO The bit is 0 6427 #define LRFDMDM_RDCAPT0_CHFI 0x00000020U 6428 #define LRFDMDM_RDCAPT0_CHFI_M 0x00000020U 6429 #define LRFDMDM_RDCAPT0_CHFI_S 5U 6430 #define LRFDMDM_RDCAPT0_CHFI_ONE 0x00000020U 6431 #define LRFDMDM_RDCAPT0_CHFI_ZERO 0x00000000U 6432 6433 // Field: [4] BDE2 6434 // 6435 // Capture BDE2 output samples into FECAPT0 and FECAPT1. 6436 // ENUMs: 6437 // ONE The bit is 1 6438 // ZERO The bit is 0 6439 #define LRFDMDM_RDCAPT0_BDE2 0x00000010U 6440 #define LRFDMDM_RDCAPT0_BDE2_M 0x00000010U 6441 #define LRFDMDM_RDCAPT0_BDE2_S 4U 6442 #define LRFDMDM_RDCAPT0_BDE2_ONE 0x00000010U 6443 #define LRFDMDM_RDCAPT0_BDE2_ZERO 0x00000000U 6444 6445 // Field: [3] FIDC 6446 // 6447 // Capture FIDC output samples into FECAPT0 and FECAPT1. 6448 // ENUMs: 6449 // ONE The bit is 1 6450 // ZERO The bit is 0 6451 #define LRFDMDM_RDCAPT0_FIDC 0x00000008U 6452 #define LRFDMDM_RDCAPT0_FIDC_M 0x00000008U 6453 #define LRFDMDM_RDCAPT0_FIDC_S 3U 6454 #define LRFDMDM_RDCAPT0_FIDC_ONE 0x00000008U 6455 #define LRFDMDM_RDCAPT0_FIDC_ZERO 0x00000000U 6456 6457 // Field: [2] FRAC 6458 // 6459 // Capture FRAC output samples into FECAPT0 and FECAPT1. 6460 // ENUMs: 6461 // ONE The bit is 1 6462 // ZERO The bit is 0 6463 #define LRFDMDM_RDCAPT0_FRAC 0x00000004U 6464 #define LRFDMDM_RDCAPT0_FRAC_M 0x00000004U 6465 #define LRFDMDM_RDCAPT0_FRAC_S 2U 6466 #define LRFDMDM_RDCAPT0_FRAC_ONE 0x00000004U 6467 #define LRFDMDM_RDCAPT0_FRAC_ZERO 0x00000000U 6468 6469 // Field: [1] MGEX 6470 // 6471 // Capture MGE1 and MGE2 output values into FECAPT0 and FECAPT1. 6472 // ENUMs: 6473 // ONE The bit is 1 6474 // ZERO The bit is 0 6475 #define LRFDMDM_RDCAPT0_MGEX 0x00000002U 6476 #define LRFDMDM_RDCAPT0_MGEX_M 0x00000002U 6477 #define LRFDMDM_RDCAPT0_MGEX_S 1U 6478 #define LRFDMDM_RDCAPT0_MGEX_ONE 0x00000002U 6479 #define LRFDMDM_RDCAPT0_MGEX_ZERO 0x00000000U 6480 6481 // Field: [0] CODC 6482 // 6483 // Capture CODC output samples into FECAPT0 and FECAPT1. 6484 // ENUMs: 6485 // ONE The bit is 1 6486 // ZERO The bit is 0 6487 #define LRFDMDM_RDCAPT0_CODC 0x00000001U 6488 #define LRFDMDM_RDCAPT0_CODC_M 0x00000001U 6489 #define LRFDMDM_RDCAPT0_CODC_S 0U 6490 #define LRFDMDM_RDCAPT0_CODC_ONE 0x00000001U 6491 #define LRFDMDM_RDCAPT0_CODC_ZERO 0x00000000U 6492 6493 //***************************************************************************** 6494 // 6495 // Register: LRFDMDM_O_RDCAPT1 6496 // 6497 //***************************************************************************** 6498 // Field: [11] C1BEX2 6499 // 6500 // Capture C1BE B correlation peak x[n-1] value into DSCAPT0 RC register. 6501 // Capture C1BE B correlation peak value into DSCAPT1 RC register. 6502 // Capture C1BE B correlation peak x[n+1] value into DSCAPT2 RC register. 6503 // Capture C1BE B qual value into DSCAPT3 RC register. 6504 // ENUMs: 6505 // ONE The bit is 1 6506 // ZERO The bit is 0 6507 #define LRFDMDM_RDCAPT1_C1BEX2 0x00000800U 6508 #define LRFDMDM_RDCAPT1_C1BEX2_M 0x00000800U 6509 #define LRFDMDM_RDCAPT1_C1BEX2_S 11U 6510 #define LRFDMDM_RDCAPT1_C1BEX2_ONE 0x00000800U 6511 #define LRFDMDM_RDCAPT1_C1BEX2_ZERO 0x00000000U 6512 6513 // Field: [10] C1BEX1 6514 // 6515 // Capture C1BE A correlation peak x[n-1] value into DSCAPT0 RC register. 6516 // Capture C1BE A correlation peak value into DSCAPT1 RC register. 6517 // Capture C1BE A correlation peak x[n+1] value into DSCAPT2 RC register. 6518 // Capture C1BE A qual value into DSCAPT3 RC register. 6519 // ENUMs: 6520 // ONE The bit is 1 6521 // ZERO The bit is 0 6522 #define LRFDMDM_RDCAPT1_C1BEX1 0x00000400U 6523 #define LRFDMDM_RDCAPT1_C1BEX1_M 0x00000400U 6524 #define LRFDMDM_RDCAPT1_C1BEX1_S 10U 6525 #define LRFDMDM_RDCAPT1_C1BEX1_ONE 0x00000400U 6526 #define LRFDMDM_RDCAPT1_C1BEX1_ZERO 0x00000000U 6527 6528 // Field: [9] C1BEX0 6529 // 6530 // Capture C1BE A values into DSCAPT0 RC register 6531 // Capture C1BE B values into DSCAPT1 RC register 6532 // Capture C1BE C values into DSCAPT2 RC register 6533 // Capture C1BE Corr Peak C into DSCAPT3 RC register 6534 // ENUMs: 6535 // ONE The bit is 1 6536 // ZERO The bit is 0 6537 #define LRFDMDM_RDCAPT1_C1BEX0 0x00000200U 6538 #define LRFDMDM_RDCAPT1_C1BEX0_M 0x00000200U 6539 #define LRFDMDM_RDCAPT1_C1BEX0_S 9U 6540 #define LRFDMDM_RDCAPT1_C1BEX0_ONE 0x00000200U 6541 #define LRFDMDM_RDCAPT1_C1BEX0_ZERO 0x00000000U 6542 6543 // Field: [8] SOFD 6544 // 6545 // Capture SOFD soft symbol into DSCAPT0 RC register 6546 // ENUMs: 6547 // ONE The bit is 1 6548 // ZERO The bit is 0 6549 #define LRFDMDM_RDCAPT1_SOFD 0x00000100U 6550 #define LRFDMDM_RDCAPT1_SOFD_M 0x00000100U 6551 #define LRFDMDM_RDCAPT1_SOFD_S 8U 6552 #define LRFDMDM_RDCAPT1_SOFD_ONE 0x00000100U 6553 #define LRFDMDM_RDCAPT1_SOFD_ZERO 0x00000000U 6554 6555 // Field: [7] LQIE 6556 // 6557 // Capture LQIE value into DSCAPT0 RC register 6558 // ENUMs: 6559 // ONE The bit is 1 6560 // ZERO The bit is 0 6561 #define LRFDMDM_RDCAPT1_LQIE 0x00000080U 6562 #define LRFDMDM_RDCAPT1_LQIE_M 0x00000080U 6563 #define LRFDMDM_RDCAPT1_LQIE_S 7U 6564 #define LRFDMDM_RDCAPT1_LQIE_ONE 0x00000080U 6565 #define LRFDMDM_RDCAPT1_LQIE_ZERO 0x00000000U 6566 6567 // Field: [6] STIM 6568 // 6569 // Capture STIM Events value into DSCAPT0 RC register bit 50. 6570 // Capture STIM Delta value into DSCAPT1 RC register bit 3:0. 6571 // Capture STIM Gardner Error(9:8) into DSCAPT1 RC register bit 7:6. 6572 // Capture STIM Gardner Error(7:0) into DSCAPT2 RC register. 6573 // Capture STIM output sample into DSCAPT3 RC register. 6574 // ENUMs: 6575 // ONE The bit is 1 6576 // ZERO The bit is 0 6577 #define LRFDMDM_RDCAPT1_STIM 0x00000040U 6578 #define LRFDMDM_RDCAPT1_STIM_M 0x00000040U 6579 #define LRFDMDM_RDCAPT1_STIM_S 6U 6580 #define LRFDMDM_RDCAPT1_STIM_ONE 0x00000040U 6581 #define LRFDMDM_RDCAPT1_STIM_ZERO 0x00000000U 6582 6583 // Field: [5] FIFE 6584 // 6585 // Capture FIFE sample into DSCAPT0 RC register 6586 // ENUMs: 6587 // ONE The bit is 1 6588 // ZERO The bit is 0 6589 #define LRFDMDM_RDCAPT1_FIFE 0x00000020U 6590 #define LRFDMDM_RDCAPT1_FIFE_M 0x00000020U 6591 #define LRFDMDM_RDCAPT1_FIFE_S 5U 6592 #define LRFDMDM_RDCAPT1_FIFE_ONE 0x00000020U 6593 #define LRFDMDM_RDCAPT1_FIFE_ZERO 0x00000000U 6594 6595 // Field: [4] PDIF 6596 // 6597 // Capture PDIF sample into DSCAPT0 RC register 6598 // ENUMs: 6599 // ONE The bit is 1 6600 // ZERO The bit is 0 6601 #define LRFDMDM_RDCAPT1_PDIF 0x00000010U 6602 #define LRFDMDM_RDCAPT1_PDIF_M 0x00000010U 6603 #define LRFDMDM_RDCAPT1_PDIF_S 4U 6604 #define LRFDMDM_RDCAPT1_PDIF_ONE 0x00000010U 6605 #define LRFDMDM_RDCAPT1_PDIF_ZERO 0x00000000U 6606 6607 // Field: [3] CA2P 6608 // 6609 // Capture CA2P sample into DSCAPT0 RC register 6610 // ENUMs: 6611 // ONE The bit is 1 6612 // ZERO The bit is 0 6613 #define LRFDMDM_RDCAPT1_CA2P 0x00000008U 6614 #define LRFDMDM_RDCAPT1_CA2P_M 0x00000008U 6615 #define LRFDMDM_RDCAPT1_CA2P_S 3U 6616 #define LRFDMDM_RDCAPT1_CA2P_ONE 0x00000008U 6617 #define LRFDMDM_RDCAPT1_CA2P_ZERO 0x00000000U 6618 6619 // Field: [2] MAFI 6620 // 6621 // Capture MAFI sample into DSCAPT0 RC register 6622 // ENUMs: 6623 // ONE The bit is 1 6624 // ZERO The bit is 0 6625 #define LRFDMDM_RDCAPT1_MAFI 0x00000004U 6626 #define LRFDMDM_RDCAPT1_MAFI_M 0x00000004U 6627 #define LRFDMDM_RDCAPT1_MAFI_S 2U 6628 #define LRFDMDM_RDCAPT1_MAFI_ONE 0x00000004U 6629 #define LRFDMDM_RDCAPT1_MAFI_ZERO 0x00000000U 6630 6631 // Field: [1] DSBU 6632 // 6633 // Capture DSBU read pointer into DSCAPT0 register 6634 // Capture DSBU write pointer into DSCAPT1 register 6635 // Capture DSBU average value into DSCAPT2 register 6636 // ENUMs: 6637 // ONE The bit is 1 6638 // ZERO The bit is 0 6639 #define LRFDMDM_RDCAPT1_DSBU 0x00000002U 6640 #define LRFDMDM_RDCAPT1_DSBU_M 0x00000002U 6641 #define LRFDMDM_RDCAPT1_DSBU_S 1U 6642 #define LRFDMDM_RDCAPT1_DSBU_ONE 0x00000002U 6643 #define LRFDMDM_RDCAPT1_DSBU_ZERO 0x00000000U 6644 6645 // Field: [0] MLSEBIT 6646 // 6647 // Capture MLSE bit into DSCAPT0 register 6648 // ENUMs: 6649 // ONE The bit is 1 6650 // ZERO The bit is 0 6651 #define LRFDMDM_RDCAPT1_MLSEBIT 0x00000001U 6652 #define LRFDMDM_RDCAPT1_MLSEBIT_M 0x00000001U 6653 #define LRFDMDM_RDCAPT1_MLSEBIT_S 0U 6654 #define LRFDMDM_RDCAPT1_MLSEBIT_ONE 0x00000001U 6655 #define LRFDMDM_RDCAPT1_MLSEBIT_ZERO 0x00000000U 6656 6657 //***************************************************************************** 6658 // 6659 // Register: LRFDMDM_O_FECAPT0 6660 // 6661 //***************************************************************************** 6662 // Field: [12:0] VAL 6663 // 6664 // Readback value, I channel 6665 // ENUMs: 6666 // ALLONES All the bits are 1 6667 // ALLZEROS All the bits are 0 6668 #define LRFDMDM_FECAPT0_VAL_W 13U 6669 #define LRFDMDM_FECAPT0_VAL_M 0x00001FFFU 6670 #define LRFDMDM_FECAPT0_VAL_S 0U 6671 #define LRFDMDM_FECAPT0_VAL_ALLONES 0x00001FFFU 6672 #define LRFDMDM_FECAPT0_VAL_ALLZEROS 0x00000000U 6673 6674 //***************************************************************************** 6675 // 6676 // Register: LRFDMDM_O_FECAPT1 6677 // 6678 //***************************************************************************** 6679 // Field: [12:0] VAL 6680 // 6681 // Readback value, Q channel 6682 // ENUMs: 6683 // ALLONES All the bits are 1 6684 // ALLZEROS All the bits are 0 6685 #define LRFDMDM_FECAPT1_VAL_W 13U 6686 #define LRFDMDM_FECAPT1_VAL_M 0x00001FFFU 6687 #define LRFDMDM_FECAPT1_VAL_S 0U 6688 #define LRFDMDM_FECAPT1_VAL_ALLONES 0x00001FFFU 6689 #define LRFDMDM_FECAPT1_VAL_ALLZEROS 0x00000000U 6690 6691 //***************************************************************************** 6692 // 6693 // Register: LRFDMDM_O_DSCAPT0 6694 // 6695 //***************************************************************************** 6696 // Field: [7:0] VAL 6697 // 6698 // Readback channel 0 after writing to RDCAPT1 6699 // ENUMs: 6700 // ALLONES All the bits are 1 6701 // ALLZEROS All the bits are 0 6702 #define LRFDMDM_DSCAPT0_VAL_W 8U 6703 #define LRFDMDM_DSCAPT0_VAL_M 0x000000FFU 6704 #define LRFDMDM_DSCAPT0_VAL_S 0U 6705 #define LRFDMDM_DSCAPT0_VAL_ALLONES 0x000000FFU 6706 #define LRFDMDM_DSCAPT0_VAL_ALLZEROS 0x00000000U 6707 6708 //***************************************************************************** 6709 // 6710 // Register: LRFDMDM_O_DSCAPT1 6711 // 6712 //***************************************************************************** 6713 // Field: [7:0] VAL 6714 // 6715 // Readback channel 1 after writing to RDCAPT1 6716 // ENUMs: 6717 // ALLONES All the bits are 1 6718 // ALLZEROS All the bits are 0 6719 #define LRFDMDM_DSCAPT1_VAL_W 8U 6720 #define LRFDMDM_DSCAPT1_VAL_M 0x000000FFU 6721 #define LRFDMDM_DSCAPT1_VAL_S 0U 6722 #define LRFDMDM_DSCAPT1_VAL_ALLONES 0x000000FFU 6723 #define LRFDMDM_DSCAPT1_VAL_ALLZEROS 0x00000000U 6724 6725 //***************************************************************************** 6726 // 6727 // Register: LRFDMDM_O_DSCAPT2 6728 // 6729 //***************************************************************************** 6730 // Field: [7:0] VAL 6731 // 6732 // Readback channel 2 after writing to RDCAPT1 6733 // ENUMs: 6734 // ALLONES All the bits are 1 6735 // ALLZEROS All the bits are 0 6736 #define LRFDMDM_DSCAPT2_VAL_W 8U 6737 #define LRFDMDM_DSCAPT2_VAL_M 0x000000FFU 6738 #define LRFDMDM_DSCAPT2_VAL_S 0U 6739 #define LRFDMDM_DSCAPT2_VAL_ALLONES 0x000000FFU 6740 #define LRFDMDM_DSCAPT2_VAL_ALLZEROS 0x00000000U 6741 6742 //***************************************************************************** 6743 // 6744 // Register: LRFDMDM_O_DSCAPT3 6745 // 6746 //***************************************************************************** 6747 // Field: [7:0] VAL 6748 // 6749 // Readback channel 3 after writing to RDCAPT1 6750 // ENUMs: 6751 // ALLONES All the bits are 1 6752 // ALLZEROS All the bits are 0 6753 #define LRFDMDM_DSCAPT3_VAL_W 8U 6754 #define LRFDMDM_DSCAPT3_VAL_M 0x000000FFU 6755 #define LRFDMDM_DSCAPT3_VAL_S 0U 6756 #define LRFDMDM_DSCAPT3_VAL_ALLONES 0x000000FFU 6757 #define LRFDMDM_DSCAPT3_VAL_ALLZEROS 0x00000000U 6758 6759 //***************************************************************************** 6760 // 6761 // Register: LRFDMDM_O_DEMSWQU1 6762 // 6763 //***************************************************************************** 6764 // Field: [9:2] MAFCCOMPVAL 6765 // 6766 // Frequency Offset value computed by SWQU 6767 // ENUMs: 6768 // ALLONES All the bits are 1 6769 // ALLZEROS All the bits are 0 6770 #define LRFDMDM_DEMSWQU1_MAFCCOMPVAL_W 8U 6771 #define LRFDMDM_DEMSWQU1_MAFCCOMPVAL_M 0x000003FCU 6772 #define LRFDMDM_DEMSWQU1_MAFCCOMPVAL_S 2U 6773 #define LRFDMDM_DEMSWQU1_MAFCCOMPVAL_ALLONES 0x000003FCU 6774 #define LRFDMDM_DEMSWQU1_MAFCCOMPVAL_ALLZEROS 0x00000000U 6775 6776 // Field: [1] SWSEL 6777 // 6778 // Shows which sync word had a peak event and was selected for sync word 6779 // qualification test. 6780 // This is to tell which sync word was detected when radio operates in receive 6781 // mode with dual sync word search. 6782 // ENUMs: 6783 // B The C1BE emitted a correlator B peak event and 6784 // SWQU selected sync word B for qualification 6785 // test 6786 // A The C1BE emitted a correlator A peak event and 6787 // SWQU selected sync word A for qualification 6788 // test (or no SWQU sync word test has been 6789 // performed yet) 6790 #define LRFDMDM_DEMSWQU1_SWSEL 0x00000002U 6791 #define LRFDMDM_DEMSWQU1_SWSEL_M 0x00000002U 6792 #define LRFDMDM_DEMSWQU1_SWSEL_S 1U 6793 #define LRFDMDM_DEMSWQU1_SWSEL_B 0x00000002U 6794 #define LRFDMDM_DEMSWQU1_SWSEL_A 0x00000000U 6795 6796 // Field: [0] SYNCED 6797 // 6798 // Reads as '1' when the sync word specified by DEMSWQU1.SWSEL has passed 6799 // qualification, otherwise '0'. 6800 // Note that the sync word qualification is only performed on MSB portion of 6801 // the reference vector, 6802 // as specified in DEMSWQU0.REFLEN register. 6803 // ENUMs: 6804 // ONE The bit is 1 6805 // ZERO The bit is 0 6806 #define LRFDMDM_DEMSWQU1_SYNCED 0x00000001U 6807 #define LRFDMDM_DEMSWQU1_SYNCED_M 0x00000001U 6808 #define LRFDMDM_DEMSWQU1_SYNCED_S 0U 6809 #define LRFDMDM_DEMSWQU1_SYNCED_ONE 0x00000001U 6810 #define LRFDMDM_DEMSWQU1_SYNCED_ZERO 0x00000000U 6811 6812 //***************************************************************************** 6813 // 6814 // Register: LRFDMDM_O_GPOCTRL0 6815 // 6816 //***************************************************************************** 6817 // Field: [15:14] GPO7 6818 // 6819 // Direct control of MCE_GPO(7) : 6820 // 00 : FW source 7 6821 // 01: HW source 7 6822 // 10: HW source 15 6823 // 11: Reserved 6824 // ENUMs: 6825 // THREE HW Source 3 6826 // TWO HW source 2 6827 // TOPSM_WAIT Output hardware clk 6828 // SW7 Output GPOCTRL1.SW 6829 #define LRFDMDM_GPOCTRL0_GPO7_W 2U 6830 #define LRFDMDM_GPOCTRL0_GPO7_M 0x0000C000U 6831 #define LRFDMDM_GPOCTRL0_GPO7_S 14U 6832 #define LRFDMDM_GPOCTRL0_GPO7_THREE 0x0000C000U 6833 #define LRFDMDM_GPOCTRL0_GPO7_TWO 0x00008000U 6834 #define LRFDMDM_GPOCTRL0_GPO7_TOPSM_WAIT 0x00004000U 6835 #define LRFDMDM_GPOCTRL0_GPO7_SW7 0x00000000U 6836 6837 // Field: [13:12] GPO6 6838 // 6839 // Direct control of MCE_GPO(6) : 6840 // 00 : FW source 6 6841 // 01: HW source 6 6842 // 10: HW source 14 6843 // 11: Reserved 6844 // ENUMs: 6845 // THREE HW Source 3 6846 // TWO HW source 2 6847 // TRANSPARENT_OUT The bit is 1 6848 // SW6 Output GPOCTRL1.SW 6849 #define LRFDMDM_GPOCTRL0_GPO6_W 2U 6850 #define LRFDMDM_GPOCTRL0_GPO6_M 0x00003000U 6851 #define LRFDMDM_GPOCTRL0_GPO6_S 12U 6852 #define LRFDMDM_GPOCTRL0_GPO6_THREE 0x00003000U 6853 #define LRFDMDM_GPOCTRL0_GPO6_TWO 0x00002000U 6854 #define LRFDMDM_GPOCTRL0_GPO6_TRANSPARENT_OUT 0x00001000U 6855 #define LRFDMDM_GPOCTRL0_GPO6_SW6 0x00000000U 6856 6857 // Field: [11:10] GPO5 6858 // 6859 // Direct control of MCE_GPO(5) : 6860 // 00 : FW source 5 6861 // 01: HW source 5 6862 // 10: HW source 13 6863 // 11: Reserved 6864 // ENUMs: 6865 // THREE HW Source 3 6866 // TWO HW source 2 6867 // DEM_OUT_WORD The bit is 1 6868 // SW5 Output GPOCTRL1.SW 6869 #define LRFDMDM_GPOCTRL0_GPO5_W 2U 6870 #define LRFDMDM_GPOCTRL0_GPO5_M 0x00000C00U 6871 #define LRFDMDM_GPOCTRL0_GPO5_S 10U 6872 #define LRFDMDM_GPOCTRL0_GPO5_THREE 0x00000C00U 6873 #define LRFDMDM_GPOCTRL0_GPO5_TWO 0x00000800U 6874 #define LRFDMDM_GPOCTRL0_GPO5_DEM_OUT_WORD 0x00000400U 6875 #define LRFDMDM_GPOCTRL0_GPO5_SW5 0x00000000U 6876 6877 // Field: [9:8] GPO4 6878 // 6879 // Direct control of MCE_GPO(4) : 6880 // 00 : FW source 4 6881 // 01: HW source 4 6882 // 10: HW source 12 6883 // 11: Reserved 6884 // ENUMs: 6885 // THREE HW Source 3 6886 // TWO HW source 2 6887 // CORR_PEAK_C The bit is 1 6888 // SW4 Output GPOCTRL1.SW 6889 #define LRFDMDM_GPOCTRL0_GPO4_W 2U 6890 #define LRFDMDM_GPOCTRL0_GPO4_M 0x00000300U 6891 #define LRFDMDM_GPOCTRL0_GPO4_S 8U 6892 #define LRFDMDM_GPOCTRL0_GPO4_THREE 0x00000300U 6893 #define LRFDMDM_GPOCTRL0_GPO4_TWO 0x00000200U 6894 #define LRFDMDM_GPOCTRL0_GPO4_CORR_PEAK_C 0x00000100U 6895 #define LRFDMDM_GPOCTRL0_GPO4_SW4 0x00000000U 6896 6897 // Field: [7:6] GPO3 6898 // 6899 // Direct control of MCE_GPO(3) : 6900 // 00 : FW source 3 6901 // 01: HW source 3 6902 // 10: HW source 11 6903 // 11: Reserved 6904 // ENUMs: 6905 // THREE HW Source 3 6906 // TWO HW source 2 6907 // CORR_PEAK_B The bit is 1 6908 // SW3 Output GPOCTRL1.SW 6909 #define LRFDMDM_GPOCTRL0_GPO3_W 2U 6910 #define LRFDMDM_GPOCTRL0_GPO3_M 0x000000C0U 6911 #define LRFDMDM_GPOCTRL0_GPO3_S 6U 6912 #define LRFDMDM_GPOCTRL0_GPO3_THREE 0x000000C0U 6913 #define LRFDMDM_GPOCTRL0_GPO3_TWO 0x00000080U 6914 #define LRFDMDM_GPOCTRL0_GPO3_CORR_PEAK_B 0x00000040U 6915 #define LRFDMDM_GPOCTRL0_GPO3_SW3 0x00000000U 6916 6917 // Field: [5:4] GPO2 6918 // 6919 // Direct control of MCE_GPO(2) : 6920 // 00 : FW source 2 6921 // 01: HW source 2 6922 // 10: HW source 10 6923 // 11: Reserved 6924 // ENUMs: 6925 // THREE HW Source 3 6926 // TWO HW source 2 6927 // CORR_PEAK_A The bit is 1 6928 // SW2 Output GPOCTRL1.SW 6929 #define LRFDMDM_GPOCTRL0_GPO2_W 2U 6930 #define LRFDMDM_GPOCTRL0_GPO2_M 0x00000030U 6931 #define LRFDMDM_GPOCTRL0_GPO2_S 4U 6932 #define LRFDMDM_GPOCTRL0_GPO2_THREE 0x00000030U 6933 #define LRFDMDM_GPOCTRL0_GPO2_TWO 0x00000020U 6934 #define LRFDMDM_GPOCTRL0_GPO2_CORR_PEAK_A 0x00000010U 6935 #define LRFDMDM_GPOCTRL0_GPO2_SW2 0x00000000U 6936 6937 // Field: [3:2] GPO1 6938 // 6939 // Direct control of MCE_GPO(1) : 6940 // 00 : FW source 1 6941 // 01: HW source 1 6942 // 10: HW source 9 6943 // 11: Reserved 6944 // ENUMs: 6945 // THREE HW Source 3 6946 // TWO HW source 2 6947 // HWCLK1 Output Loopback symbol on pin MDMGPO1 6948 // SW1 Output GPOCTRL1.SW 6949 #define LRFDMDM_GPOCTRL0_GPO1_W 2U 6950 #define LRFDMDM_GPOCTRL0_GPO1_M 0x0000000CU 6951 #define LRFDMDM_GPOCTRL0_GPO1_S 2U 6952 #define LRFDMDM_GPOCTRL0_GPO1_THREE 0x0000000CU 6953 #define LRFDMDM_GPOCTRL0_GPO1_TWO 0x00000008U 6954 #define LRFDMDM_GPOCTRL0_GPO1_HWCLK1 0x00000004U 6955 #define LRFDMDM_GPOCTRL0_GPO1_SW1 0x00000000U 6956 6957 // Field: [1:0] GPO0 6958 // 6959 // Direct control of MCE_GPO(0) : 6960 // 00 : FW source 0 6961 // 01: HW source 0 6962 // 10: HW source 8 6963 // 11: Reserved 6964 // ENUMs: 6965 // THREE HW Source 3 6966 // LOOPBACK HW source 2 6967 // HWCLK0 Output hardware clock on pin MDMGPO0 6968 // SW0 Output GPOCTRL1.SW 6969 #define LRFDMDM_GPOCTRL0_GPO0_W 2U 6970 #define LRFDMDM_GPOCTRL0_GPO0_M 0x00000003U 6971 #define LRFDMDM_GPOCTRL0_GPO0_S 0U 6972 #define LRFDMDM_GPOCTRL0_GPO0_THREE 0x00000003U 6973 #define LRFDMDM_GPOCTRL0_GPO0_LOOPBACK 0x00000002U 6974 #define LRFDMDM_GPOCTRL0_GPO0_HWCLK0 0x00000001U 6975 #define LRFDMDM_GPOCTRL0_GPO0_SW0 0x00000000U 6976 6977 //***************************************************************************** 6978 // 6979 // Register: LRFDMDM_O_GPOCTRL1 6980 // 6981 //***************************************************************************** 6982 // Field: [15:14] HWCLKSTRETCH 6983 // 6984 // Control strech for hwclk0 and hwclk1 6985 // ENUMs: 6986 // ONE The bit is 1 6987 // ZERO The bit is 0 6988 #define LRFDMDM_GPOCTRL1_HWCLKSTRETCH_W 2U 6989 #define LRFDMDM_GPOCTRL1_HWCLKSTRETCH_M 0x0000C000U 6990 #define LRFDMDM_GPOCTRL1_HWCLKSTRETCH_S 14U 6991 #define LRFDMDM_GPOCTRL1_HWCLKSTRETCH_ONE 0x00004000U 6992 #define LRFDMDM_GPOCTRL1_HWCLKSTRETCH_ZERO 0x00000000U 6993 6994 // Field: [13:11] HWCLKMUX1 6995 // 6996 // Select clock source for hwclk1 6997 // ENUMs: 6998 // ONE The bit is 1 6999 // ZERO The bit is 0 7000 #define LRFDMDM_GPOCTRL1_HWCLKMUX1_W 3U 7001 #define LRFDMDM_GPOCTRL1_HWCLKMUX1_M 0x00003800U 7002 #define LRFDMDM_GPOCTRL1_HWCLKMUX1_S 11U 7003 #define LRFDMDM_GPOCTRL1_HWCLKMUX1_ONE 0x00000800U 7004 #define LRFDMDM_GPOCTRL1_HWCLKMUX1_ZERO 0x00000000U 7005 7006 // Field: [10:8] HWCLKMUX0 7007 // 7008 // Select clock source for hwclk0 7009 // ENUMs: 7010 // ONE The bit is 1 7011 // ZERO The bit is 0 7012 #define LRFDMDM_GPOCTRL1_HWCLKMUX0_W 3U 7013 #define LRFDMDM_GPOCTRL1_HWCLKMUX0_M 0x00000700U 7014 #define LRFDMDM_GPOCTRL1_HWCLKMUX0_S 8U 7015 #define LRFDMDM_GPOCTRL1_HWCLKMUX0_ONE 0x00000100U 7016 #define LRFDMDM_GPOCTRL1_HWCLKMUX0_ZERO 0x00000000U 7017 7018 // Field: [7:0] SW 7019 // 7020 // Software controlled GPO 7021 // ENUMs: 7022 // ONE The bit is 1 7023 // ZERO The bit is 0 7024 #define LRFDMDM_GPOCTRL1_SW_W 8U 7025 #define LRFDMDM_GPOCTRL1_SW_M 0x000000FFU 7026 #define LRFDMDM_GPOCTRL1_SW_S 0U 7027 #define LRFDMDM_GPOCTRL1_SW_ONE 0x00000001U 7028 #define LRFDMDM_GPOCTRL1_SW_ZERO 0x00000000U 7029 7030 //***************************************************************************** 7031 // 7032 // Register: LRFDMDM_O_RFERSSI 7033 // 7034 //***************************************************************************** 7035 // Field: [7:0] VAL 7036 // 7037 // Current RSSI estimate 7038 // ENUMs: 7039 // ALLONES All the bits are 1 7040 // ALLZEROS All the bits are 0 7041 #define LRFDMDM_RFERSSI_VAL_W 8U 7042 #define LRFDMDM_RFERSSI_VAL_M 0x000000FFU 7043 #define LRFDMDM_RFERSSI_VAL_S 0U 7044 #define LRFDMDM_RFERSSI_VAL_ALLONES 0x000000FFU 7045 #define LRFDMDM_RFERSSI_VAL_ALLZEROS 0x00000000U 7046 7047 //***************************************************************************** 7048 // 7049 // Register: LRFDMDM_O_RFEMAXRSSI 7050 // 7051 //***************************************************************************** 7052 // Field: [7:0] VAL 7053 // 7054 // Highest RSSI since start of reception 7055 // ENUMs: 7056 // ALLONES All the bits are 1 7057 // ALLZEROS All the bits are 0 7058 #define LRFDMDM_RFEMAXRSSI_VAL_W 8U 7059 #define LRFDMDM_RFEMAXRSSI_VAL_M 0x000000FFU 7060 #define LRFDMDM_RFEMAXRSSI_VAL_S 0U 7061 #define LRFDMDM_RFEMAXRSSI_VAL_ALLONES 0x000000FFU 7062 #define LRFDMDM_RFEMAXRSSI_VAL_ALLZEROS 0x00000000U 7063 7064 //***************************************************************************** 7065 // 7066 // Register: LRFDMDM_O_RFEDBGAIN 7067 // 7068 //***************************************************************************** 7069 // Field: [7:0] VAL 7070 // 7071 // Current gain setting 7072 // ENUMs: 7073 // ALLONES All the bits are 1 7074 // ALLZEROS All the bits are 0 7075 #define LRFDMDM_RFEDBGAIN_VAL_W 8U 7076 #define LRFDMDM_RFEDBGAIN_VAL_M 0x000000FFU 7077 #define LRFDMDM_RFEDBGAIN_VAL_S 0U 7078 #define LRFDMDM_RFEDBGAIN_VAL_ALLONES 0x000000FFU 7079 #define LRFDMDM_RFEDBGAIN_VAL_ALLZEROS 0x00000000U 7080 7081 //***************************************************************************** 7082 // 7083 // Register: LRFDMDM_O_SYNC0 7084 // 7085 //***************************************************************************** 7086 // Field: [15:0] SWA15C0 7087 // 7088 // Sync word A bits 15:0. Sync words shorter than 32 bits must be stored as 7089 // most signicant bits of sync word A. 7090 // The sync word is expected to be transmitted/received in LSB to MSB order. 7091 // ENUMs: 7092 // ALLONES All the bits are 1 7093 // ALLZEROS All the bits are 0 7094 #define LRFDMDM_SYNC0_SWA15C0_W 16U 7095 #define LRFDMDM_SYNC0_SWA15C0_M 0x0000FFFFU 7096 #define LRFDMDM_SYNC0_SWA15C0_S 0U 7097 #define LRFDMDM_SYNC0_SWA15C0_ALLONES 0x0000FFFFU 7098 #define LRFDMDM_SYNC0_SWA15C0_ALLZEROS 0x00000000U 7099 7100 //***************************************************************************** 7101 // 7102 // Register: LRFDMDM_O_SYNC1 7103 // 7104 //***************************************************************************** 7105 // Field: [15:0] SWA31C16 7106 // 7107 // Sync word A bits 31:16. Sync words shorter than 32 bits must be stored as 7108 // most significant bits of sync word A. 7109 // The sync word is expected to be transmitted/received in LSB to MSB order. 7110 // ENUMs: 7111 // ALLONES All the bits are 1 7112 // ALLZEROS All the bits are 0 7113 #define LRFDMDM_SYNC1_SWA31C16_W 16U 7114 #define LRFDMDM_SYNC1_SWA31C16_M 0x0000FFFFU 7115 #define LRFDMDM_SYNC1_SWA31C16_S 0U 7116 #define LRFDMDM_SYNC1_SWA31C16_ALLONES 0x0000FFFFU 7117 #define LRFDMDM_SYNC1_SWA31C16_ALLZEROS 0x00000000U 7118 7119 //***************************************************************************** 7120 // 7121 // Register: LRFDMDM_O_SYNC2 7122 // 7123 //***************************************************************************** 7124 // Field: [15:0] SWB15C0 7125 // 7126 // Sync word B bits 15:0. Sync words shorter than 32 bits must be stored as 7127 // most significant bits of sync word B. 7128 // The sync word is expected to be transmitted/received in LSB to MSB order. 7129 // ENUMs: 7130 // ALLONES All the bits are 1 7131 // ALLZEROS All the bits are 0 7132 #define LRFDMDM_SYNC2_SWB15C0_W 16U 7133 #define LRFDMDM_SYNC2_SWB15C0_M 0x0000FFFFU 7134 #define LRFDMDM_SYNC2_SWB15C0_S 0U 7135 #define LRFDMDM_SYNC2_SWB15C0_ALLONES 0x0000FFFFU 7136 #define LRFDMDM_SYNC2_SWB15C0_ALLZEROS 0x00000000U 7137 7138 //***************************************************************************** 7139 // 7140 // Register: LRFDMDM_O_SYNC3 7141 // 7142 //***************************************************************************** 7143 // Field: [15:0] SWB31C16 7144 // 7145 // Sync word B bits 31:16. Sync words shorter than 32 bits must be stored as 7146 // most significant bits of sync word B. 7147 // The sync word is expected to be transmitted/received in LSB to MSB order. 7148 // ENUMs: 7149 // ALLONES All the bits are 1 7150 // ALLZEROS All the bits are 0 7151 #define LRFDMDM_SYNC3_SWB31C16_W 16U 7152 #define LRFDMDM_SYNC3_SWB31C16_M 0x0000FFFFU 7153 #define LRFDMDM_SYNC3_SWB31C16_S 0U 7154 #define LRFDMDM_SYNC3_SWB31C16_ALLONES 0x0000FFFFU 7155 #define LRFDMDM_SYNC3_SWB31C16_ALLZEROS 0x00000000U 7156 7157 7158 #endif // __LRFDMDM__ 7159
