1 /****************************************************************************** 2 * Filename: hw_lrfddbell_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_LRFDDBELL_H__ 34 #define __HW_LRFDDBELL_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // LRFDDBELL component 40 // 41 //***************************************************************************** 42 // Description 43 #define LRFDDBELL_O_DESC 0x00000000U 44 45 // Clock control 46 #define LRFDDBELL_O_CLKCTL 0x00000004U 47 48 // DMA Configuration 49 #define LRFDDBELL_O_DMACFG 0x00000008U 50 51 // Systimer Output Event Control Register 52 #define LRFDDBELL_O_SYSTIMOEV 0x0000000CU 53 54 // System DMA Trigger 55 #define LRFDDBELL_O_SYSTDMATRIG 0x00000010U 56 57 // GPO control 58 #define LRFDDBELL_O_GPOSEL0 0x00000014U 59 60 // GPO control 61 #define LRFDDBELL_O_GPOSEL1 0x00000018U 62 63 // Interrupt mask 64 #define LRFDDBELL_O_IMASK0 0x00000044U 65 66 // Raw interrupt status 67 #define LRFDDBELL_O_RIS0 0x00000048U 68 69 // Masked interrupt status 70 #define LRFDDBELL_O_MIS0 0x0000004CU 71 72 // Interrupt set 73 #define LRFDDBELL_O_ISET0 0x00000050U 74 75 // Interrupt clear 76 #define LRFDDBELL_O_ICLR0 0x00000054U 77 78 // Interrupt mask 79 #define LRFDDBELL_O_IMASK1 0x00000084U 80 81 // Raw interrupt status 82 #define LRFDDBELL_O_RIS1 0x00000088U 83 84 // Masked interrupt status 85 #define LRFDDBELL_O_MIS1 0x0000008CU 86 87 // Interrupt set 88 #define LRFDDBELL_O_ISET1 0x00000090U 89 90 // Interrupt clear 91 #define LRFDDBELL_O_ICLR1 0x00000094U 92 93 // Interrupt mask 94 #define LRFDDBELL_O_IMASK2 0x000000C4U 95 96 // Raw interrupt status 97 #define LRFDDBELL_O_RIS2 0x000000C8U 98 99 // Masked interrupt status 100 #define LRFDDBELL_O_MIS2 0x000000CCU 101 102 // Interrupt set 103 #define LRFDDBELL_O_ISET2 0x000000D0U 104 105 // Interrupt clear 106 #define LRFDDBELL_O_ICLR2 0x000000D4U 107 108 //***************************************************************************** 109 // 110 // Register: LRFDDBELL_O_DESC 111 // 112 //***************************************************************************** 113 // Field: [31:16] MODULEID 114 // 115 // Module identifier used to uniquely identify this IP. 116 #define LRFDDBELL_DESC_MODULEID_W 16U 117 #define LRFDDBELL_DESC_MODULEID_M 0xFFFF0000U 118 #define LRFDDBELL_DESC_MODULEID_S 16U 119 120 // Field: [15:12] STDIPOFF 121 // 122 // Standard IP MMR block offset. Standard IP MMRs are the set of from 123 // aggregated IRQ registers till DTB. 124 // ENUMs: 125 // STDIPMMR These MMRs begin at offset 64*STDIPOFF from IP 126 // base address 127 // NO_STDIPMMR STDIP MMRs do not exist 128 #define LRFDDBELL_DESC_STDIPOFF_W 4U 129 #define LRFDDBELL_DESC_STDIPOFF_M 0x0000F000U 130 #define LRFDDBELL_DESC_STDIPOFF_S 12U 131 #define LRFDDBELL_DESC_STDIPOFF_STDIPMMR 0x00001000U 132 #define LRFDDBELL_DESC_STDIPOFF_NO_STDIPMMR 0x00000000U 133 134 // Field: [11:8] INSTNUM 135 // 136 // IP Instance Number. If multiple instances of IP exist in the device, this 137 // field can identify the instance number 138 #define LRFDDBELL_DESC_INSTNUM_W 4U 139 #define LRFDDBELL_DESC_INSTNUM_M 0x00000F00U 140 #define LRFDDBELL_DESC_INSTNUM_S 8U 141 142 // Field: [7:4] MAJREV 143 // 144 // Major rev of the IP 145 #define LRFDDBELL_DESC_MAJREV_W 4U 146 #define LRFDDBELL_DESC_MAJREV_M 0x000000F0U 147 #define LRFDDBELL_DESC_MAJREV_S 4U 148 149 // Field: [3:0] MINREV 150 // 151 // Minor rev of the IP 152 #define LRFDDBELL_DESC_MINREV_W 4U 153 #define LRFDDBELL_DESC_MINREV_M 0x0000000FU 154 #define LRFDDBELL_DESC_MINREV_S 0U 155 156 //***************************************************************************** 157 // 158 // Register: LRFDDBELL_O_CLKCTL 159 // 160 //***************************************************************************** 161 // Field: [13] DEM 162 // 163 // Enable the clock to the demodulator. The modem will request this clock 164 // automatically. This bit is to force the clock to be free running 165 // ENUMs: 166 // EN Clock is requested 167 // DIS Clock not requested 168 #define LRFDDBELL_CLKCTL_DEM 0x00002000U 169 #define LRFDDBELL_CLKCTL_DEM_M 0x00002000U 170 #define LRFDDBELL_CLKCTL_DEM_S 13U 171 #define LRFDDBELL_CLKCTL_DEM_EN 0x00002000U 172 #define LRFDDBELL_CLKCTL_DEM_DIS 0x00000000U 173 174 // Field: [12] MOD 175 // 176 // Enable the clock to the modulator. Modem will request this clock 177 // automatically, this bit is to force the modulator clock to be free running. 178 // ENUMs: 179 // EN Clock is requested 180 // DIS Clock not requested 181 #define LRFDDBELL_CLKCTL_MOD 0x00001000U 182 #define LRFDDBELL_CLKCTL_MOD_M 0x00001000U 183 #define LRFDDBELL_CLKCTL_MOD_S 12U 184 #define LRFDDBELL_CLKCTL_MOD_EN 0x00001000U 185 #define LRFDDBELL_CLKCTL_MOD_DIS 0x00000000U 186 187 // Field: [11] S2RRAM 188 // 189 // Enable the clock to the S2R RAM 190 // ENUMs: 191 // EN Clock is requested 192 // DIS Clock not requested 193 #define LRFDDBELL_CLKCTL_S2RRAM 0x00000800U 194 #define LRFDDBELL_CLKCTL_S2RRAM_M 0x00000800U 195 #define LRFDDBELL_CLKCTL_S2RRAM_S 11U 196 #define LRFDDBELL_CLKCTL_S2RRAM_EN 0x00000800U 197 #define LRFDDBELL_CLKCTL_S2RRAM_DIS 0x00000000U 198 199 // Field: [10] BUFRAM 200 // 201 // Enable the clock to the BUFRAM 202 // ENUMs: 203 // EN Clock is requested 204 // DIS Clock not requested 205 #define LRFDDBELL_CLKCTL_BUFRAM 0x00000400U 206 #define LRFDDBELL_CLKCTL_BUFRAM_M 0x00000400U 207 #define LRFDDBELL_CLKCTL_BUFRAM_S 10U 208 #define LRFDDBELL_CLKCTL_BUFRAM_EN 0x00000400U 209 #define LRFDDBELL_CLKCTL_BUFRAM_DIS 0x00000000U 210 211 // Field: [9] DSBRAM 212 // 213 // Enable the clock to the DSB RAM 214 // ENUMs: 215 // EN Clock is requested 216 // DIS Clock not requested 217 #define LRFDDBELL_CLKCTL_DSBRAM 0x00000200U 218 #define LRFDDBELL_CLKCTL_DSBRAM_M 0x00000200U 219 #define LRFDDBELL_CLKCTL_DSBRAM_S 9U 220 #define LRFDDBELL_CLKCTL_DSBRAM_EN 0x00000200U 221 #define LRFDDBELL_CLKCTL_DSBRAM_DIS 0x00000000U 222 223 // Field: [8] RFERAM 224 // 225 // Enable the clock to the RFE RAM 226 // ENUMs: 227 // EN Clock is requested 228 // DIS Clock not requested 229 #define LRFDDBELL_CLKCTL_RFERAM 0x00000100U 230 #define LRFDDBELL_CLKCTL_RFERAM_M 0x00000100U 231 #define LRFDDBELL_CLKCTL_RFERAM_S 8U 232 #define LRFDDBELL_CLKCTL_RFERAM_EN 0x00000100U 233 #define LRFDDBELL_CLKCTL_RFERAM_DIS 0x00000000U 234 235 // Field: [7] MCERAM 236 // 237 // Enable the clock to the MCE RAM 238 // ENUMs: 239 // EN Clock is requested 240 // DIS Clock not requested 241 #define LRFDDBELL_CLKCTL_MCERAM 0x00000080U 242 #define LRFDDBELL_CLKCTL_MCERAM_M 0x00000080U 243 #define LRFDDBELL_CLKCTL_MCERAM_S 7U 244 #define LRFDDBELL_CLKCTL_MCERAM_EN 0x00000080U 245 #define LRFDDBELL_CLKCTL_MCERAM_DIS 0x00000000U 246 247 // Field: [6] PBERAM 248 // 249 // Enable the clock to the PBE RAM 250 // ENUMs: 251 // EN Clock is requested 252 // DIS Clock not requested 253 #define LRFDDBELL_CLKCTL_PBERAM 0x00000040U 254 #define LRFDDBELL_CLKCTL_PBERAM_M 0x00000040U 255 #define LRFDDBELL_CLKCTL_PBERAM_S 6U 256 #define LRFDDBELL_CLKCTL_PBERAM_EN 0x00000040U 257 #define LRFDDBELL_CLKCTL_PBERAM_DIS 0x00000000U 258 259 // Field: [5] TRC 260 // 261 // Enable the clock to the Tracer 262 // ENUMs: 263 // EN Clock is requested 264 // DIS Clock not requested 265 #define LRFDDBELL_CLKCTL_TRC 0x00000020U 266 #define LRFDDBELL_CLKCTL_TRC_M 0x00000020U 267 #define LRFDDBELL_CLKCTL_TRC_S 5U 268 #define LRFDDBELL_CLKCTL_TRC_EN 0x00000020U 269 #define LRFDDBELL_CLKCTL_TRC_DIS 0x00000000U 270 271 // Field: [4] S2R 272 // 273 // Enable the clock to Samples2RAM 274 // ENUMs: 275 // EN Clock is requested 276 // DIS Clock not requested 277 #define LRFDDBELL_CLKCTL_S2R 0x00000010U 278 #define LRFDDBELL_CLKCTL_S2R_M 0x00000010U 279 #define LRFDDBELL_CLKCTL_S2R_S 4U 280 #define LRFDDBELL_CLKCTL_S2R_EN 0x00000010U 281 #define LRFDDBELL_CLKCTL_S2R_DIS 0x00000000U 282 283 // Field: [3] RFE 284 // 285 // Enable the clock to the RFE 286 // ENUMs: 287 // EN Clock is requested 288 // DIS Clock not requested 289 #define LRFDDBELL_CLKCTL_RFE 0x00000008U 290 #define LRFDDBELL_CLKCTL_RFE_M 0x00000008U 291 #define LRFDDBELL_CLKCTL_RFE_S 3U 292 #define LRFDDBELL_CLKCTL_RFE_EN 0x00000008U 293 #define LRFDDBELL_CLKCTL_RFE_DIS 0x00000000U 294 295 // Field: [2] MDM 296 // 297 // Enable the clock to the Modem 298 // ENUMs: 299 // EN Clock is requested 300 // DIS Clock not requested 301 #define LRFDDBELL_CLKCTL_MDM 0x00000004U 302 #define LRFDDBELL_CLKCTL_MDM_M 0x00000004U 303 #define LRFDDBELL_CLKCTL_MDM_S 2U 304 #define LRFDDBELL_CLKCTL_MDM_EN 0x00000004U 305 #define LRFDDBELL_CLKCTL_MDM_DIS 0x00000000U 306 307 // Field: [1] PBE 308 // 309 // Enable the clock to the PBE 310 // ENUMs: 311 // EN Clock is requested 312 // DIS Clock not requested 313 #define LRFDDBELL_CLKCTL_PBE 0x00000002U 314 #define LRFDDBELL_CLKCTL_PBE_M 0x00000002U 315 #define LRFDDBELL_CLKCTL_PBE_S 1U 316 #define LRFDDBELL_CLKCTL_PBE_EN 0x00000002U 317 #define LRFDDBELL_CLKCTL_PBE_DIS 0x00000000U 318 319 // Field: [0] BRIDGE 320 // 321 // Clock enable to AHB bridge. The bridge will request it's own clock, this bit 322 // it to override that feature to have a free running clock. 323 // ENUMs: 324 // EN Clock is requested 325 // DIS Clock not requested 326 #define LRFDDBELL_CLKCTL_BRIDGE 0x00000001U 327 #define LRFDDBELL_CLKCTL_BRIDGE_M 0x00000001U 328 #define LRFDDBELL_CLKCTL_BRIDGE_S 0U 329 #define LRFDDBELL_CLKCTL_BRIDGE_EN 0x00000001U 330 #define LRFDDBELL_CLKCTL_BRIDGE_DIS 0x00000000U 331 332 //***************************************************************************** 333 // 334 // Register: LRFDDBELL_O_DMACFG 335 // 336 //***************************************************************************** 337 // Field: [2:1] TRIGSRC 338 // 339 // Select DMA trigger source 340 // ENUMs: 341 // FIFO The DMA is triggered from the FIFO. See the FIFO 342 // configration register for what FIFO event will 343 // generate the trigger 344 // RFEFW The DMA is triggered by the MCE FW trigger 345 // MCEFW The DMA is triggered by the MCE FW trigger 346 // PBEFW The DMA is triggered by the PBE FW trigger 347 #define LRFDDBELL_DMACFG_TRIGSRC_W 2U 348 #define LRFDDBELL_DMACFG_TRIGSRC_M 0x00000006U 349 #define LRFDDBELL_DMACFG_TRIGSRC_S 1U 350 #define LRFDDBELL_DMACFG_TRIGSRC_FIFO 0x00000006U 351 #define LRFDDBELL_DMACFG_TRIGSRC_RFEFW 0x00000004U 352 #define LRFDDBELL_DMACFG_TRIGSRC_MCEFW 0x00000002U 353 #define LRFDDBELL_DMACFG_TRIGSRC_PBEFW 0x00000000U 354 355 // Field: [0] EN 356 // 357 // Enables the DMA interface 358 // ENUMs: 359 // ON Enable DMA interface. The triggers are able to 360 // give activity on the interface 361 // OFF Disable DMA interface, no activity on interface 362 #define LRFDDBELL_DMACFG_EN 0x00000001U 363 #define LRFDDBELL_DMACFG_EN_M 0x00000001U 364 #define LRFDDBELL_DMACFG_EN_S 0U 365 #define LRFDDBELL_DMACFG_EN_ON 0x00000001U 366 #define LRFDDBELL_DMACFG_EN_OFF 0x00000000U 367 368 //***************************************************************************** 369 // 370 // Register: LRFDDBELL_O_SYSTIMOEV 371 // 372 //***************************************************************************** 373 // Field: [11:8] SRC2 374 // 375 // Select source of systimer output event 2 (capture source) 376 // ENUMs: 377 // PBESYSTIM2 PBE FW systimer capture event 2 378 // PBESYSTIM1 PBE FW systimer capture event 1 379 // PBESYSTIM0 PBE FW systimer capture event 0 380 // MDMHW2 MDM HW event 2 381 // MDMHW1 MDM HW event 1 382 // MDMHW0 MDM HW event 0 383 // MCESYSTIM2 MCE FW systimer capture event 2 384 // MCESYSTIM1 MCE FW systimer capture event 1 385 // MCESYSTIM0 MCE FW systimer capture event 0 386 // RFESYSTIM2 RFE FW systimer capture event 2 387 // RFESYSTIM1 RFE FW systimer capture event 1 388 // RFESYSTIM0 RFE FW systimer capture event 0 389 // DIS Output not enabled, always 0. 390 #define LRFDDBELL_SYSTIMOEV_SRC2_W 4U 391 #define LRFDDBELL_SYSTIMOEV_SRC2_M 0x00000F00U 392 #define LRFDDBELL_SYSTIMOEV_SRC2_S 8U 393 #define LRFDDBELL_SYSTIMOEV_SRC2_PBESYSTIM2 0x00000C00U 394 #define LRFDDBELL_SYSTIMOEV_SRC2_PBESYSTIM1 0x00000B00U 395 #define LRFDDBELL_SYSTIMOEV_SRC2_PBESYSTIM0 0x00000A00U 396 #define LRFDDBELL_SYSTIMOEV_SRC2_MDMHW2 0x00000900U 397 #define LRFDDBELL_SYSTIMOEV_SRC2_MDMHW1 0x00000800U 398 #define LRFDDBELL_SYSTIMOEV_SRC2_MDMHW0 0x00000700U 399 #define LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM2 0x00000600U 400 #define LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM1 0x00000500U 401 #define LRFDDBELL_SYSTIMOEV_SRC2_MCESYSTIM0 0x00000400U 402 #define LRFDDBELL_SYSTIMOEV_SRC2_RFESYSTIM2 0x00000300U 403 #define LRFDDBELL_SYSTIMOEV_SRC2_RFESYSTIM1 0x00000200U 404 #define LRFDDBELL_SYSTIMOEV_SRC2_RFESYSTIM0 0x00000100U 405 #define LRFDDBELL_SYSTIMOEV_SRC2_DIS 0x00000000U 406 407 // Field: [7:4] SRC1 408 // 409 // Select source of systimer output event 1 (capture source) 410 // ENUMs: 411 // PBESYSTIM2 PBE FW systimer capture event 2 412 // PBESYSTIM1 PBE FW systimer capture event 1 413 // PBESYSTIM0 PBE FW systimer capture event 0 414 // MDMHW2 MDM HW event 2 415 // MDMHW1 MDM HW event 1 416 // MDMHW0 MDM HW event 0 417 // MCESYSTIM2 MCE FW systimer capture event 2 418 // MCESYSTIM1 MCE FW systimer capture event 1 419 // MCESYSTIM0 MCE FW systimer capture event 0 420 // RFESYSTIM2 RFE FW systimer capture event 2 421 // RFESYSTIM1 RFE FW systimer capture event 1 422 // RFESYSTIM0 RFE FW systimer capture event 0 423 // DIS Output not enabled, always 0. 424 #define LRFDDBELL_SYSTIMOEV_SRC1_W 4U 425 #define LRFDDBELL_SYSTIMOEV_SRC1_M 0x000000F0U 426 #define LRFDDBELL_SYSTIMOEV_SRC1_S 4U 427 #define LRFDDBELL_SYSTIMOEV_SRC1_PBESYSTIM2 0x000000C0U 428 #define LRFDDBELL_SYSTIMOEV_SRC1_PBESYSTIM1 0x000000B0U 429 #define LRFDDBELL_SYSTIMOEV_SRC1_PBESYSTIM0 0x000000A0U 430 #define LRFDDBELL_SYSTIMOEV_SRC1_MDMHW2 0x00000090U 431 #define LRFDDBELL_SYSTIMOEV_SRC1_MDMHW1 0x00000080U 432 #define LRFDDBELL_SYSTIMOEV_SRC1_MDMHW0 0x00000070U 433 #define LRFDDBELL_SYSTIMOEV_SRC1_MCESYSTIM2 0x00000060U 434 #define LRFDDBELL_SYSTIMOEV_SRC1_MCESYSTIM1 0x00000050U 435 #define LRFDDBELL_SYSTIMOEV_SRC1_MCESYSTIM0 0x00000040U 436 #define LRFDDBELL_SYSTIMOEV_SRC1_RFESYSTIM2 0x00000030U 437 #define LRFDDBELL_SYSTIMOEV_SRC1_RFESYSTIM1 0x00000020U 438 #define LRFDDBELL_SYSTIMOEV_SRC1_RFESYSTIM0 0x00000010U 439 #define LRFDDBELL_SYSTIMOEV_SRC1_DIS 0x00000000U 440 441 // Field: [3:0] SRC0 442 // 443 // Select source of systimer output event 0 (capture source) 444 // ENUMs: 445 // PBESYSTIM2 PBE FW systimer capture event 2 446 // PBESYSTIM1 PBE FW systimer capture event 1 447 // PBESYSTIM0 PBE FW systimer capture event 0 448 // MDMHW2 MDM HW event 2 449 // MDMHW1 MDM HW event 1 450 // MDMHW0 MDM HW event 0 451 // MCESYSTIM2 MCE FW systimer capture event 2 452 // MCESYSTIM1 MCE FW systimer capture event 1 453 // MCESYSTIM0 MCE FW systimer capture event 0 454 // RFESYSTIM2 RFE FW systimer capture event 2 455 // RFESYSTIM1 RFE FW systimer capture event 1 456 // RFESYSTIM0 RFE FW systimer capture event 0 457 // DIS Output not enabled, always 0. 458 #define LRFDDBELL_SYSTIMOEV_SRC0_W 4U 459 #define LRFDDBELL_SYSTIMOEV_SRC0_M 0x0000000FU 460 #define LRFDDBELL_SYSTIMOEV_SRC0_S 0U 461 #define LRFDDBELL_SYSTIMOEV_SRC0_PBESYSTIM2 0x0000000CU 462 #define LRFDDBELL_SYSTIMOEV_SRC0_PBESYSTIM1 0x0000000BU 463 #define LRFDDBELL_SYSTIMOEV_SRC0_PBESYSTIM0 0x0000000AU 464 #define LRFDDBELL_SYSTIMOEV_SRC0_MDMHW2 0x00000009U 465 #define LRFDDBELL_SYSTIMOEV_SRC0_MDMHW1 0x00000008U 466 #define LRFDDBELL_SYSTIMOEV_SRC0_MDMHW0 0x00000007U 467 #define LRFDDBELL_SYSTIMOEV_SRC0_MCESYSTIM2 0x00000006U 468 #define LRFDDBELL_SYSTIMOEV_SRC0_MCESYSTIM1 0x00000005U 469 #define LRFDDBELL_SYSTIMOEV_SRC0_MCESYSTIM0 0x00000004U 470 #define LRFDDBELL_SYSTIMOEV_SRC0_RFESYSTIM2 0x00000003U 471 #define LRFDDBELL_SYSTIMOEV_SRC0_RFESYSTIM1 0x00000002U 472 #define LRFDDBELL_SYSTIMOEV_SRC0_RFESYSTIM0 0x00000001U 473 #define LRFDDBELL_SYSTIMOEV_SRC0_DIS 0x00000000U 474 475 //***************************************************************************** 476 // 477 // Register: LRFDDBELL_O_SYSTDMATRIG 478 // 479 //***************************************************************************** 480 // Field: [3] DMA 481 // 482 // Trigger a DMA request from the Radio 483 // ENUMs: 484 // TRIG DMA request manually triggered 485 // NOTRIG DMA not manually triggered 486 #define LRFDDBELL_SYSTDMATRIG_DMA 0x00000008U 487 #define LRFDDBELL_SYSTDMATRIG_DMA_M 0x00000008U 488 #define LRFDDBELL_SYSTDMATRIG_DMA_S 3U 489 #define LRFDDBELL_SYSTDMATRIG_DMA_TRIG 0x00000008U 490 #define LRFDDBELL_SYSTDMATRIG_DMA_NOTRIG 0x00000000U 491 492 // Field: [2] SYST2 493 // 494 // Trigger a capture event on systimer event 0 from the radio 495 // ENUMs: 496 // TRIG Capture event triggered 497 // NOTRIG Not capture event triggered 498 #define LRFDDBELL_SYSTDMATRIG_SYST2 0x00000004U 499 #define LRFDDBELL_SYSTDMATRIG_SYST2_M 0x00000004U 500 #define LRFDDBELL_SYSTDMATRIG_SYST2_S 2U 501 #define LRFDDBELL_SYSTDMATRIG_SYST2_TRIG 0x00000004U 502 #define LRFDDBELL_SYSTDMATRIG_SYST2_NOTRIG 0x00000000U 503 504 // Field: [1] SYST1 505 // 506 // Trigger a capture event on systimer event 0 from the radio 507 // ENUMs: 508 // TRIG Capture event triggered 509 // NOTRIG Not capture event triggered 510 #define LRFDDBELL_SYSTDMATRIG_SYST1 0x00000002U 511 #define LRFDDBELL_SYSTDMATRIG_SYST1_M 0x00000002U 512 #define LRFDDBELL_SYSTDMATRIG_SYST1_S 1U 513 #define LRFDDBELL_SYSTDMATRIG_SYST1_TRIG 0x00000002U 514 #define LRFDDBELL_SYSTDMATRIG_SYST1_NOTRIG 0x00000000U 515 516 // Field: [0] SYST0 517 // 518 // Trigger a capture event on systimer event 0 from the radio 519 // ENUMs: 520 // TRIG Capture event triggered 521 // NOTRIG Not capture event triggered 522 #define LRFDDBELL_SYSTDMATRIG_SYST0 0x00000001U 523 #define LRFDDBELL_SYSTDMATRIG_SYST0_M 0x00000001U 524 #define LRFDDBELL_SYSTDMATRIG_SYST0_S 0U 525 #define LRFDDBELL_SYSTDMATRIG_SYST0_TRIG 0x00000001U 526 #define LRFDDBELL_SYSTDMATRIG_SYST0_NOTRIG 0x00000000U 527 528 //***************************************************************************** 529 // 530 // Register: LRFDDBELL_O_GPOSEL0 531 // 532 //***************************************************************************** 533 // Field: [28:24] SRC3 534 // 535 // Select source of radio GPO line 3 536 // ENUMs: 537 // RFCTRC Select RFCTRC GPO line 3 538 // RFEGPO7 Select RFE GPO line 7 539 // RFEGPO6 Select RFE GPO line 6 540 // RFEGPO5 Select RFE GPO line 5 541 // RFEGPO4 Select RFE GPO line 4 542 // RFEGPO3 Select RFE GPO line 3 543 // RFEGPO2 Select RFE GPO line 2 544 // RFEGPO1 Select RFE GPO line 1 545 // RFEGPO0 Select RFE GPO line 0 546 // MCEGPO7 Select MCE GPO line 7 547 // MCEGPO6 Select MCE GPO line 6 548 // MCEGPO5 Select MCE GPO line 5 549 // MCEGPO4 Select MCE GPO line 4 550 // MCEGPO3 Select MCE GPO line 3 551 // MCEGPO2 Select MCE GPO line 2 552 // MCEGPO1 Select MCE GPO line 1 553 // MCEGPO0 Select MCE GPO line 0 554 // PBEGPO7 Select PBE GPO line 7 555 // PBEGPO6 Select PBE GPO line 6 556 // PBEGPO5 Select PBE GPO line 5 557 // PBEGPO4 Select PBE GPO line 4 558 // PBEGPO3 Select PBE GPO line 3 559 // PBEGPO2 Select PBE GPO line 2 560 // PBEGPO1 Select PBE GPO line 1 561 // PBEGPO0 Select PBE GPO line 0 562 // DIS Output not enabled 563 #define LRFDDBELL_GPOSEL0_SRC3_W 5U 564 #define LRFDDBELL_GPOSEL0_SRC3_M 0x1F000000U 565 #define LRFDDBELL_GPOSEL0_SRC3_S 24U 566 #define LRFDDBELL_GPOSEL0_SRC3_RFCTRC 0x19000000U 567 #define LRFDDBELL_GPOSEL0_SRC3_RFEGPO7 0x18000000U 568 #define LRFDDBELL_GPOSEL0_SRC3_RFEGPO6 0x17000000U 569 #define LRFDDBELL_GPOSEL0_SRC3_RFEGPO5 0x16000000U 570 #define LRFDDBELL_GPOSEL0_SRC3_RFEGPO4 0x15000000U 571 #define LRFDDBELL_GPOSEL0_SRC3_RFEGPO3 0x14000000U 572 #define LRFDDBELL_GPOSEL0_SRC3_RFEGPO2 0x13000000U 573 #define LRFDDBELL_GPOSEL0_SRC3_RFEGPO1 0x12000000U 574 #define LRFDDBELL_GPOSEL0_SRC3_RFEGPO0 0x11000000U 575 #define LRFDDBELL_GPOSEL0_SRC3_MCEGPO7 0x10000000U 576 #define LRFDDBELL_GPOSEL0_SRC3_MCEGPO6 0x0F000000U 577 #define LRFDDBELL_GPOSEL0_SRC3_MCEGPO5 0x0E000000U 578 #define LRFDDBELL_GPOSEL0_SRC3_MCEGPO4 0x0D000000U 579 #define LRFDDBELL_GPOSEL0_SRC3_MCEGPO3 0x0C000000U 580 #define LRFDDBELL_GPOSEL0_SRC3_MCEGPO2 0x0B000000U 581 #define LRFDDBELL_GPOSEL0_SRC3_MCEGPO1 0x0A000000U 582 #define LRFDDBELL_GPOSEL0_SRC3_MCEGPO0 0x09000000U 583 #define LRFDDBELL_GPOSEL0_SRC3_PBEGPO7 0x08000000U 584 #define LRFDDBELL_GPOSEL0_SRC3_PBEGPO6 0x07000000U 585 #define LRFDDBELL_GPOSEL0_SRC3_PBEGPO5 0x06000000U 586 #define LRFDDBELL_GPOSEL0_SRC3_PBEGPO4 0x05000000U 587 #define LRFDDBELL_GPOSEL0_SRC3_PBEGPO3 0x04000000U 588 #define LRFDDBELL_GPOSEL0_SRC3_PBEGPO2 0x03000000U 589 #define LRFDDBELL_GPOSEL0_SRC3_PBEGPO1 0x02000000U 590 #define LRFDDBELL_GPOSEL0_SRC3_PBEGPO0 0x01000000U 591 #define LRFDDBELL_GPOSEL0_SRC3_DIS 0x00000000U 592 593 // Field: [20:16] SRC2 594 // 595 // Select source of radio GPO line 2 596 // ENUMs: 597 // RFCTRC Select RFCTRC GPO line 2 598 // RFEGPO7 Select RFE GPO line 7 599 // RFEGPO6 Select RFE GPO line 6 600 // RFEGPO5 Select RFE GPO line 5 601 // RFEGPO4 Select RFE GPO line 4 602 // RFEGPO3 Select RFE GPO line 3 603 // RFEGPO2 Select RFE GPO line 2 604 // RFEGPO1 Select RFE GPO line 1 605 // RFEGPO0 Select RFE GPO line 0 606 // MCEGPO7 Select MCE GPO line 7 607 // MCEGPO6 Select MCE GPO line 6 608 // MCEGPO5 Select MCE GPO line 5 609 // MCEGPO4 Select MCE GPO line 4 610 // MCEGPO3 Select MCE GPO line 3 611 // MCEGPO2 Select MCE GPO line 2 612 // MCEGPO1 Select MCE GPO line 1 613 // MCEGPO0 Select MCE GPO line 0 614 // PBEGPO7 Select PBE GPO line 7 615 // PBEGPO6 Select PBE GPO line 6 616 // PBEGPO5 Select PBE GPO line 5 617 // PBEGPO4 Select PBE GPO line 4 618 // PBEGPO3 Select PBE GPO line 3 619 // PBEGPO2 Select PBE GPO line 2 620 // PBEGPO1 Select PBE GPO line 1 621 // PBEGPO0 Select PBE GPO line 0 622 // DIS Output not enabled 623 #define LRFDDBELL_GPOSEL0_SRC2_W 5U 624 #define LRFDDBELL_GPOSEL0_SRC2_M 0x001F0000U 625 #define LRFDDBELL_GPOSEL0_SRC2_S 16U 626 #define LRFDDBELL_GPOSEL0_SRC2_RFCTRC 0x00190000U 627 #define LRFDDBELL_GPOSEL0_SRC2_RFEGPO7 0x00180000U 628 #define LRFDDBELL_GPOSEL0_SRC2_RFEGPO6 0x00170000U 629 #define LRFDDBELL_GPOSEL0_SRC2_RFEGPO5 0x00160000U 630 #define LRFDDBELL_GPOSEL0_SRC2_RFEGPO4 0x00150000U 631 #define LRFDDBELL_GPOSEL0_SRC2_RFEGPO3 0x00140000U 632 #define LRFDDBELL_GPOSEL0_SRC2_RFEGPO2 0x00130000U 633 #define LRFDDBELL_GPOSEL0_SRC2_RFEGPO1 0x00120000U 634 #define LRFDDBELL_GPOSEL0_SRC2_RFEGPO0 0x00110000U 635 #define LRFDDBELL_GPOSEL0_SRC2_MCEGPO7 0x00100000U 636 #define LRFDDBELL_GPOSEL0_SRC2_MCEGPO6 0x000F0000U 637 #define LRFDDBELL_GPOSEL0_SRC2_MCEGPO5 0x000E0000U 638 #define LRFDDBELL_GPOSEL0_SRC2_MCEGPO4 0x000D0000U 639 #define LRFDDBELL_GPOSEL0_SRC2_MCEGPO3 0x000C0000U 640 #define LRFDDBELL_GPOSEL0_SRC2_MCEGPO2 0x000B0000U 641 #define LRFDDBELL_GPOSEL0_SRC2_MCEGPO1 0x000A0000U 642 #define LRFDDBELL_GPOSEL0_SRC2_MCEGPO0 0x00090000U 643 #define LRFDDBELL_GPOSEL0_SRC2_PBEGPO7 0x00080000U 644 #define LRFDDBELL_GPOSEL0_SRC2_PBEGPO6 0x00070000U 645 #define LRFDDBELL_GPOSEL0_SRC2_PBEGPO5 0x00060000U 646 #define LRFDDBELL_GPOSEL0_SRC2_PBEGPO4 0x00050000U 647 #define LRFDDBELL_GPOSEL0_SRC2_PBEGPO3 0x00040000U 648 #define LRFDDBELL_GPOSEL0_SRC2_PBEGPO2 0x00030000U 649 #define LRFDDBELL_GPOSEL0_SRC2_PBEGPO1 0x00020000U 650 #define LRFDDBELL_GPOSEL0_SRC2_PBEGPO0 0x00010000U 651 #define LRFDDBELL_GPOSEL0_SRC2_DIS 0x00000000U 652 653 // Field: [12:8] SRC1 654 // 655 // Select source of radio GPO line 1 656 // ENUMs: 657 // RFCTRC Select RFCTRC GPO line 1 658 // RFEGPO7 Select RFE GPO line 7 659 // RFEGPO6 Select RFE GPO line 6 660 // RFEGPO5 Select RFE GPO line 5 661 // RFEGPO4 Select RFE GPO line 4 662 // RFEGPO3 Select RFE GPO line 3 663 // RFEGPO2 Select RFE GPO line 2 664 // RFEGPO1 Select RFE GPO line 1 665 // RFEGPO0 Select RFE GPO line 0 666 // MCEGPO7 Select MCE GPO line 7 667 // MCEGPO6 Select MCE GPO line 6 668 // MCEGPO5 Select MCE GPO line 5 669 // MCEGPO4 Select MCE GPO line 4 670 // MCEGPO3 Select MCE GPO line 3 671 // MCEGPO2 Select MCE GPO line 2 672 // MCEGPO1 Select MCE GPO line 1 673 // MCEGPO0 Select MCE GPO line 0 674 // PBEGPO7 Select PBE GPO line 7 675 // PBEGPO6 Select PBE GPO line 6 676 // PBEGPO5 Select PBE GPO line 5 677 // PBEGPO4 Select PBE GPO line 4 678 // PBEGPO3 Select PBE GPO line 3 679 // PBEGPO2 Select PBE GPO line 2 680 // PBEGPO1 Select PBE GPO line 1 681 // PBEGPO0 Select PBE GPO line 0 682 // DIS Output not enabled 683 #define LRFDDBELL_GPOSEL0_SRC1_W 5U 684 #define LRFDDBELL_GPOSEL0_SRC1_M 0x00001F00U 685 #define LRFDDBELL_GPOSEL0_SRC1_S 8U 686 #define LRFDDBELL_GPOSEL0_SRC1_RFCTRC 0x00001900U 687 #define LRFDDBELL_GPOSEL0_SRC1_RFEGPO7 0x00001800U 688 #define LRFDDBELL_GPOSEL0_SRC1_RFEGPO6 0x00001700U 689 #define LRFDDBELL_GPOSEL0_SRC1_RFEGPO5 0x00001600U 690 #define LRFDDBELL_GPOSEL0_SRC1_RFEGPO4 0x00001500U 691 #define LRFDDBELL_GPOSEL0_SRC1_RFEGPO3 0x00001400U 692 #define LRFDDBELL_GPOSEL0_SRC1_RFEGPO2 0x00001300U 693 #define LRFDDBELL_GPOSEL0_SRC1_RFEGPO1 0x00001200U 694 #define LRFDDBELL_GPOSEL0_SRC1_RFEGPO0 0x00001100U 695 #define LRFDDBELL_GPOSEL0_SRC1_MCEGPO7 0x00001000U 696 #define LRFDDBELL_GPOSEL0_SRC1_MCEGPO6 0x00000F00U 697 #define LRFDDBELL_GPOSEL0_SRC1_MCEGPO5 0x00000E00U 698 #define LRFDDBELL_GPOSEL0_SRC1_MCEGPO4 0x00000D00U 699 #define LRFDDBELL_GPOSEL0_SRC1_MCEGPO3 0x00000C00U 700 #define LRFDDBELL_GPOSEL0_SRC1_MCEGPO2 0x00000B00U 701 #define LRFDDBELL_GPOSEL0_SRC1_MCEGPO1 0x00000A00U 702 #define LRFDDBELL_GPOSEL0_SRC1_MCEGPO0 0x00000900U 703 #define LRFDDBELL_GPOSEL0_SRC1_PBEGPO7 0x00000800U 704 #define LRFDDBELL_GPOSEL0_SRC1_PBEGPO6 0x00000700U 705 #define LRFDDBELL_GPOSEL0_SRC1_PBEGPO5 0x00000600U 706 #define LRFDDBELL_GPOSEL0_SRC1_PBEGPO4 0x00000500U 707 #define LRFDDBELL_GPOSEL0_SRC1_PBEGPO3 0x00000400U 708 #define LRFDDBELL_GPOSEL0_SRC1_PBEGPO2 0x00000300U 709 #define LRFDDBELL_GPOSEL0_SRC1_PBEGPO1 0x00000200U 710 #define LRFDDBELL_GPOSEL0_SRC1_PBEGPO0 0x00000100U 711 #define LRFDDBELL_GPOSEL0_SRC1_DIS 0x00000000U 712 713 // Field: [4:0] SRC0 714 // 715 // Select source of radio GPO line 0 716 // ENUMs: 717 // RFCTRC Select RFCTRC GPO line 0 718 // RFEGPO7 Select RFE GPO line 7 719 // RFEGPO6 Select RFE GPO line 6 720 // RFEGPO5 Select RFE GPO line 5 721 // RFEGPO4 Select RFE GPO line 4 722 // RFEGPO3 Select RFE GPO line 3 723 // RFEGPO2 Select RFE GPO line 2 724 // RFEGPO1 Select RFE GPO line 1 725 // RFEGPO0 Select RFE GPO line 0 726 // MCEGPO7 Select MCE GPO line 7 727 // MCEGPO6 Select MCE GPO line 6 728 // MCEGPO5 Select MCE GPO line 5 729 // MCEGPO4 Select MCE GPO line 4 730 // MCEGPO3 Select MCE GPO line 3 731 // MCEGPO2 Select MCE GPO line 2 732 // MCEGPO1 Select MCE GPO line 1 733 // MCEGPO0 Select MCE GPO line 0 734 // PBEGPO7 Select PBE GPO line 7 735 // PBEGPO6 Select PBE GPO line 6 736 // PBEGPO5 Select PBE GPO line 5 737 // PBEGPO4 Select PBE GPO line 4 738 // PBEGPO3 Select PBE GPO line 3 739 // PBEGPO2 Select PBE GPO line 2 740 // PBEGPO1 Select PBE GPO line 1 741 // PBEGPO0 Select PBE GPO line 0 742 // DIS Output not enabled 743 #define LRFDDBELL_GPOSEL0_SRC0_W 5U 744 #define LRFDDBELL_GPOSEL0_SRC0_M 0x0000001FU 745 #define LRFDDBELL_GPOSEL0_SRC0_S 0U 746 #define LRFDDBELL_GPOSEL0_SRC0_RFCTRC 0x00000019U 747 #define LRFDDBELL_GPOSEL0_SRC0_RFEGPO7 0x00000018U 748 #define LRFDDBELL_GPOSEL0_SRC0_RFEGPO6 0x00000017U 749 #define LRFDDBELL_GPOSEL0_SRC0_RFEGPO5 0x00000016U 750 #define LRFDDBELL_GPOSEL0_SRC0_RFEGPO4 0x00000015U 751 #define LRFDDBELL_GPOSEL0_SRC0_RFEGPO3 0x00000014U 752 #define LRFDDBELL_GPOSEL0_SRC0_RFEGPO2 0x00000013U 753 #define LRFDDBELL_GPOSEL0_SRC0_RFEGPO1 0x00000012U 754 #define LRFDDBELL_GPOSEL0_SRC0_RFEGPO0 0x00000011U 755 #define LRFDDBELL_GPOSEL0_SRC0_MCEGPO7 0x00000010U 756 #define LRFDDBELL_GPOSEL0_SRC0_MCEGPO6 0x0000000FU 757 #define LRFDDBELL_GPOSEL0_SRC0_MCEGPO5 0x0000000EU 758 #define LRFDDBELL_GPOSEL0_SRC0_MCEGPO4 0x0000000DU 759 #define LRFDDBELL_GPOSEL0_SRC0_MCEGPO3 0x0000000CU 760 #define LRFDDBELL_GPOSEL0_SRC0_MCEGPO2 0x0000000BU 761 #define LRFDDBELL_GPOSEL0_SRC0_MCEGPO1 0x0000000AU 762 #define LRFDDBELL_GPOSEL0_SRC0_MCEGPO0 0x00000009U 763 #define LRFDDBELL_GPOSEL0_SRC0_PBEGPO7 0x00000008U 764 #define LRFDDBELL_GPOSEL0_SRC0_PBEGPO6 0x00000007U 765 #define LRFDDBELL_GPOSEL0_SRC0_PBEGPO5 0x00000006U 766 #define LRFDDBELL_GPOSEL0_SRC0_PBEGPO4 0x00000005U 767 #define LRFDDBELL_GPOSEL0_SRC0_PBEGPO3 0x00000004U 768 #define LRFDDBELL_GPOSEL0_SRC0_PBEGPO2 0x00000003U 769 #define LRFDDBELL_GPOSEL0_SRC0_PBEGPO1 0x00000002U 770 #define LRFDDBELL_GPOSEL0_SRC0_PBEGPO0 0x00000001U 771 #define LRFDDBELL_GPOSEL0_SRC0_DIS 0x00000000U 772 773 //***************************************************************************** 774 // 775 // Register: LRFDDBELL_O_GPOSEL1 776 // 777 //***************************************************************************** 778 // Field: [28:24] SRC7 779 // 780 // Select source of radio GPO line 7 781 // ENUMs: 782 // RFCTRC Select RFCTRC GPO line 7 783 // RFEGPO7 Select RFE GPO line 7 784 // RFEGPO6 Select RFE GPO line 6 785 // RFEGPO5 Select RFE GPO line 5 786 // RFEGPO4 Select RFE GPO line 4 787 // RFEGPO3 Select RFE GPO line 3 788 // RFEGPO2 Select RFE GPO line 2 789 // RFEGPO1 Select RFE GPO line 1 790 // RFEGPO0 Select RFE GPO line 0 791 // MCEGPO7 Select MCE GPO line 7 792 // MCEGPO6 Select MCE GPO line 6 793 // MCEGPO5 Select MCE GPO line 5 794 // MCEGPO4 Select MCE GPO line 4 795 // MCEGPO3 Select MCE GPO line 3 796 // MCEGPO2 Select MCE GPO line 2 797 // MCEGPO1 Select MCE GPO line 1 798 // MCEGPO0 Select MCE GPO line 0 799 // PBEGPO7 Select PBE GPO line 7 800 // PBEGPO6 Select PBE GPO line 6 801 // PBEGPO5 Select PBE GPO line 5 802 // PBEGPO4 Select PBE GPO line 4 803 // PBEGPO3 Select PBE GPO line 3 804 // PBEGPO2 Select PBE GPO line 2 805 // PBEGPO1 Select PBE GPO line 1 806 // PBEGPO0 Select PBE GPO line 0 807 // DIS No output not enabled 808 #define LRFDDBELL_GPOSEL1_SRC7_W 5U 809 #define LRFDDBELL_GPOSEL1_SRC7_M 0x1F000000U 810 #define LRFDDBELL_GPOSEL1_SRC7_S 24U 811 #define LRFDDBELL_GPOSEL1_SRC7_RFCTRC 0x19000000U 812 #define LRFDDBELL_GPOSEL1_SRC7_RFEGPO7 0x18000000U 813 #define LRFDDBELL_GPOSEL1_SRC7_RFEGPO6 0x17000000U 814 #define LRFDDBELL_GPOSEL1_SRC7_RFEGPO5 0x16000000U 815 #define LRFDDBELL_GPOSEL1_SRC7_RFEGPO4 0x15000000U 816 #define LRFDDBELL_GPOSEL1_SRC7_RFEGPO3 0x14000000U 817 #define LRFDDBELL_GPOSEL1_SRC7_RFEGPO2 0x13000000U 818 #define LRFDDBELL_GPOSEL1_SRC7_RFEGPO1 0x12000000U 819 #define LRFDDBELL_GPOSEL1_SRC7_RFEGPO0 0x11000000U 820 #define LRFDDBELL_GPOSEL1_SRC7_MCEGPO7 0x10000000U 821 #define LRFDDBELL_GPOSEL1_SRC7_MCEGPO6 0x0F000000U 822 #define LRFDDBELL_GPOSEL1_SRC7_MCEGPO5 0x0E000000U 823 #define LRFDDBELL_GPOSEL1_SRC7_MCEGPO4 0x0D000000U 824 #define LRFDDBELL_GPOSEL1_SRC7_MCEGPO3 0x0C000000U 825 #define LRFDDBELL_GPOSEL1_SRC7_MCEGPO2 0x0B000000U 826 #define LRFDDBELL_GPOSEL1_SRC7_MCEGPO1 0x0A000000U 827 #define LRFDDBELL_GPOSEL1_SRC7_MCEGPO0 0x09000000U 828 #define LRFDDBELL_GPOSEL1_SRC7_PBEGPO7 0x08000000U 829 #define LRFDDBELL_GPOSEL1_SRC7_PBEGPO6 0x07000000U 830 #define LRFDDBELL_GPOSEL1_SRC7_PBEGPO5 0x06000000U 831 #define LRFDDBELL_GPOSEL1_SRC7_PBEGPO4 0x05000000U 832 #define LRFDDBELL_GPOSEL1_SRC7_PBEGPO3 0x04000000U 833 #define LRFDDBELL_GPOSEL1_SRC7_PBEGPO2 0x03000000U 834 #define LRFDDBELL_GPOSEL1_SRC7_PBEGPO1 0x02000000U 835 #define LRFDDBELL_GPOSEL1_SRC7_PBEGPO0 0x01000000U 836 #define LRFDDBELL_GPOSEL1_SRC7_DIS 0x00000000U 837 838 // Field: [20:16] SRC6 839 // 840 // Select source of radio GPO line 6 841 // ENUMs: 842 // RFCTRC Select RFCTRC GPO line 6 843 // RFEGPO7 Select RFE GPO line 7 844 // RFEGPO6 Select RFE GPO line 6 845 // RFEGPO5 Select RFE GPO line 5 846 // RFEGPO4 Select RFE GPO line 4 847 // RFEGPO3 Select RFE GPO line 3 848 // RFEGPO2 Selevt RFE GPO line 2 849 // RFEGPO1 Select RFE GPO line 1 850 // RFEGPO0 Select RFE GPO line 0 851 // MCEGPO7 Select MCE GPO line 7 852 // MCEGPO6 Select MCE GPO line 6 853 // MCEGPO5 Select MCE GPO line 5 854 // MCEGPO4 Select MCE GPO line 4 855 // MCEGPO3 Select MCE GPO line 3 856 // MCEGPO2 Select MCE GPO line 2 857 // MCEGPO1 Select MCE GPO line 1 858 // MCEGPO0 Select MCE GPO line 0 859 // PBEGPO7 Select PBE GPO line 7 860 // PBEGPO6 Select PBE GPO line 6 861 // PBEGPO5 Select PBE GPO line 5 862 // PBEGPO4 Select PBE GPO line 4 863 // PBEGPO3 Select PBE GPO line 3 864 // PBEGPO2 Select PBE GPO line 2 865 // PBEGPO1 Select PBE GPO line 1 866 // PBEGPO0 Select PBE GPO line 0 867 // DIS No output not enabled 868 #define LRFDDBELL_GPOSEL1_SRC6_W 5U 869 #define LRFDDBELL_GPOSEL1_SRC6_M 0x001F0000U 870 #define LRFDDBELL_GPOSEL1_SRC6_S 16U 871 #define LRFDDBELL_GPOSEL1_SRC6_RFCTRC 0x00190000U 872 #define LRFDDBELL_GPOSEL1_SRC6_RFEGPO7 0x00180000U 873 #define LRFDDBELL_GPOSEL1_SRC6_RFEGPO6 0x00170000U 874 #define LRFDDBELL_GPOSEL1_SRC6_RFEGPO5 0x00160000U 875 #define LRFDDBELL_GPOSEL1_SRC6_RFEGPO4 0x00150000U 876 #define LRFDDBELL_GPOSEL1_SRC6_RFEGPO3 0x00140000U 877 #define LRFDDBELL_GPOSEL1_SRC6_RFEGPO2 0x00130000U 878 #define LRFDDBELL_GPOSEL1_SRC6_RFEGPO1 0x00120000U 879 #define LRFDDBELL_GPOSEL1_SRC6_RFEGPO0 0x00110000U 880 #define LRFDDBELL_GPOSEL1_SRC6_MCEGPO7 0x00100000U 881 #define LRFDDBELL_GPOSEL1_SRC6_MCEGPO6 0x000F0000U 882 #define LRFDDBELL_GPOSEL1_SRC6_MCEGPO5 0x000E0000U 883 #define LRFDDBELL_GPOSEL1_SRC6_MCEGPO4 0x000D0000U 884 #define LRFDDBELL_GPOSEL1_SRC6_MCEGPO3 0x000C0000U 885 #define LRFDDBELL_GPOSEL1_SRC6_MCEGPO2 0x000B0000U 886 #define LRFDDBELL_GPOSEL1_SRC6_MCEGPO1 0x000A0000U 887 #define LRFDDBELL_GPOSEL1_SRC6_MCEGPO0 0x00090000U 888 #define LRFDDBELL_GPOSEL1_SRC6_PBEGPO7 0x00080000U 889 #define LRFDDBELL_GPOSEL1_SRC6_PBEGPO6 0x00070000U 890 #define LRFDDBELL_GPOSEL1_SRC6_PBEGPO5 0x00060000U 891 #define LRFDDBELL_GPOSEL1_SRC6_PBEGPO4 0x00050000U 892 #define LRFDDBELL_GPOSEL1_SRC6_PBEGPO3 0x00040000U 893 #define LRFDDBELL_GPOSEL1_SRC6_PBEGPO2 0x00030000U 894 #define LRFDDBELL_GPOSEL1_SRC6_PBEGPO1 0x00020000U 895 #define LRFDDBELL_GPOSEL1_SRC6_PBEGPO0 0x00010000U 896 #define LRFDDBELL_GPOSEL1_SRC6_DIS 0x00000000U 897 898 // Field: [12:8] SRC5 899 // 900 // Select source of radio GPO line 5 901 // ENUMs: 902 // RFCTRC Select RFCTRC GPO line 5 903 // RFEGPO7 Select RFE GPO line 7 904 // RFEGPO6 Select RFE GPO line 6 905 // RFEGPO5 Select RFE GPO line 5 906 // RFEGPO4 Select RFE GPO line 4 907 // RFEGPO3 Select RFE GPO line 3 908 // RFEGPO2 Select RFE GPO line 2 909 // RFEGPO1 Select RFE GPO line 1 910 // RFEGPO0 Select RFE GPO line 0 911 // MCEGPO7 Select MCE GPO line 7 912 // MCEGPO6 Select MCE GPO line 6 913 // MCEGPO5 Select MCE GPO line 5 914 // MCEGPO4 Select MCE GPO line 4 915 // MCEGPO3 Select MCE GPO line 3 916 // MCEGPO2 Select MCE GPO line 2 917 // MCEGPO1 Select MCE GPO line 1 918 // MCEGPO0 Select MCE GPO line 0 919 // PBEGPO7 Select PBE GPO line 7 920 // PBEGPO6 Select PBE GPO line 6 921 // PBEGPO5 Select PBE GPO line 5 922 // PBEGPO4 Select PBE GPO line 4 923 // PBEGPO3 Select PBE GPO line 3 924 // PBEGPO2 Select PBE GPO line 2 925 // PBEGPO1 Select PBE GPO line 1 926 // PBEGPO0 Select PBE GPO line 0 927 // DIS No output not enabled 928 #define LRFDDBELL_GPOSEL1_SRC5_W 5U 929 #define LRFDDBELL_GPOSEL1_SRC5_M 0x00001F00U 930 #define LRFDDBELL_GPOSEL1_SRC5_S 8U 931 #define LRFDDBELL_GPOSEL1_SRC5_RFCTRC 0x00001900U 932 #define LRFDDBELL_GPOSEL1_SRC5_RFEGPO7 0x00001800U 933 #define LRFDDBELL_GPOSEL1_SRC5_RFEGPO6 0x00001700U 934 #define LRFDDBELL_GPOSEL1_SRC5_RFEGPO5 0x00001600U 935 #define LRFDDBELL_GPOSEL1_SRC5_RFEGPO4 0x00001500U 936 #define LRFDDBELL_GPOSEL1_SRC5_RFEGPO3 0x00001400U 937 #define LRFDDBELL_GPOSEL1_SRC5_RFEGPO2 0x00001300U 938 #define LRFDDBELL_GPOSEL1_SRC5_RFEGPO1 0x00001200U 939 #define LRFDDBELL_GPOSEL1_SRC5_RFEGPO0 0x00001100U 940 #define LRFDDBELL_GPOSEL1_SRC5_MCEGPO7 0x00001000U 941 #define LRFDDBELL_GPOSEL1_SRC5_MCEGPO6 0x00000F00U 942 #define LRFDDBELL_GPOSEL1_SRC5_MCEGPO5 0x00000E00U 943 #define LRFDDBELL_GPOSEL1_SRC5_MCEGPO4 0x00000D00U 944 #define LRFDDBELL_GPOSEL1_SRC5_MCEGPO3 0x00000C00U 945 #define LRFDDBELL_GPOSEL1_SRC5_MCEGPO2 0x00000B00U 946 #define LRFDDBELL_GPOSEL1_SRC5_MCEGPO1 0x00000A00U 947 #define LRFDDBELL_GPOSEL1_SRC5_MCEGPO0 0x00000900U 948 #define LRFDDBELL_GPOSEL1_SRC5_PBEGPO7 0x00000800U 949 #define LRFDDBELL_GPOSEL1_SRC5_PBEGPO6 0x00000700U 950 #define LRFDDBELL_GPOSEL1_SRC5_PBEGPO5 0x00000600U 951 #define LRFDDBELL_GPOSEL1_SRC5_PBEGPO4 0x00000500U 952 #define LRFDDBELL_GPOSEL1_SRC5_PBEGPO3 0x00000400U 953 #define LRFDDBELL_GPOSEL1_SRC5_PBEGPO2 0x00000300U 954 #define LRFDDBELL_GPOSEL1_SRC5_PBEGPO1 0x00000200U 955 #define LRFDDBELL_GPOSEL1_SRC5_PBEGPO0 0x00000100U 956 #define LRFDDBELL_GPOSEL1_SRC5_DIS 0x00000000U 957 958 // Field: [4:0] SRC4 959 // 960 // Select source of radio GPO line 4 961 // ENUMs: 962 // RFCTRC Select RFCTRC GPO line 4 963 // RFEGPO7 Select RFE GPO line 7 964 // RFEGPO6 Select RFE GPO line 6 965 // RFEGPO5 Select RFE GPO line 5 966 // RFEGPO4 Select RFE GPO line 4 967 // RFEGPO3 Select RFE GPO line 3 968 // RFEGPO2 Select RFE GPO line 2 969 // RFEGPO1 Select RFE GPO line 1 970 // RFEGPO0 Select RFE GPO line 0 971 // MCEGPO7 Select MCE GPO line 7 972 // MCEGPO6 Select MCE GPO line 6 973 // MCEGPO5 Select MCE GPO line 5 974 // MCEGPO4 Select MCE GPO line 4 975 // MCEGPO3 Select MCE GPO line 3 976 // MCEGPO2 Select MCE GPO line 2 977 // MCEGPO1 Select MCE GPO line 1 978 // MCEGPO0 Select MCE GPO line 0 979 // PBEGPO7 Select PBE GPO line 7 980 // PBEGPO6 Select PBE GPO line 6 981 // PBEGPO5 Select PBE GPO line 5 982 // PBEGPO4 Select PBE GPO line 4 983 // PBEGPO3 Select PBE GPO line 3 984 // PBEGPO2 Select PBE GPO line 2 985 // PBEGPO1 Select PBE GPO line 1 986 // PBEGPO0 Select PBE GPO line 0 987 // DIS No output not enabled 988 #define LRFDDBELL_GPOSEL1_SRC4_W 5U 989 #define LRFDDBELL_GPOSEL1_SRC4_M 0x0000001FU 990 #define LRFDDBELL_GPOSEL1_SRC4_S 0U 991 #define LRFDDBELL_GPOSEL1_SRC4_RFCTRC 0x00000019U 992 #define LRFDDBELL_GPOSEL1_SRC4_RFEGPO7 0x00000018U 993 #define LRFDDBELL_GPOSEL1_SRC4_RFEGPO6 0x00000017U 994 #define LRFDDBELL_GPOSEL1_SRC4_RFEGPO5 0x00000016U 995 #define LRFDDBELL_GPOSEL1_SRC4_RFEGPO4 0x00000015U 996 #define LRFDDBELL_GPOSEL1_SRC4_RFEGPO3 0x00000014U 997 #define LRFDDBELL_GPOSEL1_SRC4_RFEGPO2 0x00000013U 998 #define LRFDDBELL_GPOSEL1_SRC4_RFEGPO1 0x00000012U 999 #define LRFDDBELL_GPOSEL1_SRC4_RFEGPO0 0x00000011U 1000 #define LRFDDBELL_GPOSEL1_SRC4_MCEGPO7 0x00000010U 1001 #define LRFDDBELL_GPOSEL1_SRC4_MCEGPO6 0x0000000FU 1002 #define LRFDDBELL_GPOSEL1_SRC4_MCEGPO5 0x0000000EU 1003 #define LRFDDBELL_GPOSEL1_SRC4_MCEGPO4 0x0000000DU 1004 #define LRFDDBELL_GPOSEL1_SRC4_MCEGPO3 0x0000000CU 1005 #define LRFDDBELL_GPOSEL1_SRC4_MCEGPO2 0x0000000BU 1006 #define LRFDDBELL_GPOSEL1_SRC4_MCEGPO1 0x0000000AU 1007 #define LRFDDBELL_GPOSEL1_SRC4_MCEGPO0 0x00000009U 1008 #define LRFDDBELL_GPOSEL1_SRC4_PBEGPO7 0x00000008U 1009 #define LRFDDBELL_GPOSEL1_SRC4_PBEGPO6 0x00000007U 1010 #define LRFDDBELL_GPOSEL1_SRC4_PBEGPO5 0x00000006U 1011 #define LRFDDBELL_GPOSEL1_SRC4_PBEGPO4 0x00000005U 1012 #define LRFDDBELL_GPOSEL1_SRC4_PBEGPO3 0x00000004U 1013 #define LRFDDBELL_GPOSEL1_SRC4_PBEGPO2 0x00000003U 1014 #define LRFDDBELL_GPOSEL1_SRC4_PBEGPO1 0x00000002U 1015 #define LRFDDBELL_GPOSEL1_SRC4_PBEGPO0 0x00000001U 1016 #define LRFDDBELL_GPOSEL1_SRC4_DIS 0x00000000U 1017 1018 //***************************************************************************** 1019 // 1020 // Register: LRFDDBELL_O_IMASK0 1021 // 1022 //***************************************************************************** 1023 // Field: [31] SYSTIM2 1024 // 1025 // SYSTIM2 event 1026 // ENUMs: 1027 // EN Enable interrupt mask 1028 // DIS Disable interrupt mask 1029 #define LRFDDBELL_IMASK0_SYSTIM2 0x80000000U 1030 #define LRFDDBELL_IMASK0_SYSTIM2_M 0x80000000U 1031 #define LRFDDBELL_IMASK0_SYSTIM2_S 31U 1032 #define LRFDDBELL_IMASK0_SYSTIM2_EN 0x80000000U 1033 #define LRFDDBELL_IMASK0_SYSTIM2_DIS 0x00000000U 1034 1035 // Field: [30] SYSTIM1 1036 // 1037 // SYSTIM1 event 1038 // ENUMs: 1039 // EN Enable interrupt mask 1040 // DIS Disable interrupt mask 1041 #define LRFDDBELL_IMASK0_SYSTIM1 0x40000000U 1042 #define LRFDDBELL_IMASK0_SYSTIM1_M 0x40000000U 1043 #define LRFDDBELL_IMASK0_SYSTIM1_S 30U 1044 #define LRFDDBELL_IMASK0_SYSTIM1_EN 0x40000000U 1045 #define LRFDDBELL_IMASK0_SYSTIM1_DIS 0x00000000U 1046 1047 // Field: [29] SYSTIM0 1048 // 1049 // SYSTIM0 event 1050 // ENUMs: 1051 // EN Enable interrupt mask 1052 // DIS Disable interrupt mask 1053 #define LRFDDBELL_IMASK0_SYSTIM0 0x20000000U 1054 #define LRFDDBELL_IMASK0_SYSTIM0_M 0x20000000U 1055 #define LRFDDBELL_IMASK0_SYSTIM0_S 29U 1056 #define LRFDDBELL_IMASK0_SYSTIM0_EN 0x20000000U 1057 #define LRFDDBELL_IMASK0_SYSTIM0_DIS 0x00000000U 1058 1059 // Field: [28] MDMDONE 1060 // 1061 // MDMDONE event 1062 // ENUMs: 1063 // EN Enable interrupt mask 1064 // DIS Disable interrupt mask 1065 #define LRFDDBELL_IMASK0_MDMDONE 0x10000000U 1066 #define LRFDDBELL_IMASK0_MDMDONE_M 0x10000000U 1067 #define LRFDDBELL_IMASK0_MDMDONE_S 28U 1068 #define LRFDDBELL_IMASK0_MDMDONE_EN 0x10000000U 1069 #define LRFDDBELL_IMASK0_MDMDONE_DIS 0x00000000U 1070 1071 // Field: [27] MDMIN 1072 // 1073 // MDMIN event 1074 // ENUMs: 1075 // EN Enable interrupt mask 1076 // DIS Disable interrupt mask 1077 #define LRFDDBELL_IMASK0_MDMIN 0x08000000U 1078 #define LRFDDBELL_IMASK0_MDMIN_M 0x08000000U 1079 #define LRFDDBELL_IMASK0_MDMIN_S 27U 1080 #define LRFDDBELL_IMASK0_MDMIN_EN 0x08000000U 1081 #define LRFDDBELL_IMASK0_MDMIN_DIS 0x00000000U 1082 1083 // Field: [26] MDMOUT 1084 // 1085 // MDMOUT event 1086 // ENUMs: 1087 // EN Enable interrupt mask 1088 // DIS Disable interrupt mask 1089 #define LRFDDBELL_IMASK0_MDMOUT 0x04000000U 1090 #define LRFDDBELL_IMASK0_MDMOUT_M 0x04000000U 1091 #define LRFDDBELL_IMASK0_MDMOUT_S 26U 1092 #define LRFDDBELL_IMASK0_MDMOUT_EN 0x04000000U 1093 #define LRFDDBELL_IMASK0_MDMOUT_DIS 0x00000000U 1094 1095 // Field: [25] MDMSOFT2 1096 // 1097 // MDMSOFT2 event 1098 // ENUMs: 1099 // EN Enable interrupt mask 1100 // DIS Disable interrupt mask 1101 #define LRFDDBELL_IMASK0_MDMSOFT2 0x02000000U 1102 #define LRFDDBELL_IMASK0_MDMSOFT2_M 0x02000000U 1103 #define LRFDDBELL_IMASK0_MDMSOFT2_S 25U 1104 #define LRFDDBELL_IMASK0_MDMSOFT2_EN 0x02000000U 1105 #define LRFDDBELL_IMASK0_MDMSOFT2_DIS 0x00000000U 1106 1107 // Field: [24] MDMSOFT1 1108 // 1109 // MDMSOFT2 event 1110 // ENUMs: 1111 // EN Enable interrupt mask 1112 // DIS Disable interrupt mask 1113 #define LRFDDBELL_IMASK0_MDMSOFT1 0x01000000U 1114 #define LRFDDBELL_IMASK0_MDMSOFT1_M 0x01000000U 1115 #define LRFDDBELL_IMASK0_MDMSOFT1_S 24U 1116 #define LRFDDBELL_IMASK0_MDMSOFT1_EN 0x01000000U 1117 #define LRFDDBELL_IMASK0_MDMSOFT1_DIS 0x00000000U 1118 1119 // Field: [23] MDMSOFT0 1120 // 1121 // MDMSOFT2 event 1122 // ENUMs: 1123 // EN Enable interrupt mask 1124 // DIS Disable interrupt mask 1125 #define LRFDDBELL_IMASK0_MDMSOFT0 0x00800000U 1126 #define LRFDDBELL_IMASK0_MDMSOFT0_M 0x00800000U 1127 #define LRFDDBELL_IMASK0_MDMSOFT0_S 23U 1128 #define LRFDDBELL_IMASK0_MDMSOFT0_EN 0x00800000U 1129 #define LRFDDBELL_IMASK0_MDMSOFT0_DIS 0x00000000U 1130 1131 // Field: [22] RFEDONE 1132 // 1133 // RFEDONE event 1134 // ENUMs: 1135 // EN Enable interrupt mask 1136 // DIS Disable interrupt mask 1137 #define LRFDDBELL_IMASK0_RFEDONE 0x00400000U 1138 #define LRFDDBELL_IMASK0_RFEDONE_M 0x00400000U 1139 #define LRFDDBELL_IMASK0_RFEDONE_S 22U 1140 #define LRFDDBELL_IMASK0_RFEDONE_EN 0x00400000U 1141 #define LRFDDBELL_IMASK0_RFEDONE_DIS 0x00000000U 1142 1143 // Field: [21] RFESOFT1 1144 // 1145 // RFESOFT1 event 1146 // ENUMs: 1147 // EN Enable interrupt mask 1148 // DIS Disable interrupt mask 1149 #define LRFDDBELL_IMASK0_RFESOFT1 0x00200000U 1150 #define LRFDDBELL_IMASK0_RFESOFT1_M 0x00200000U 1151 #define LRFDDBELL_IMASK0_RFESOFT1_S 21U 1152 #define LRFDDBELL_IMASK0_RFESOFT1_EN 0x00200000U 1153 #define LRFDDBELL_IMASK0_RFESOFT1_DIS 0x00000000U 1154 1155 // Field: [20] RFESOFT0 1156 // 1157 // RFESOFT0 event 1158 // ENUMs: 1159 // EN Enable interrupt mask 1160 // DIS Disable interrupt mask 1161 #define LRFDDBELL_IMASK0_RFESOFT0 0x00100000U 1162 #define LRFDDBELL_IMASK0_RFESOFT0_M 0x00100000U 1163 #define LRFDDBELL_IMASK0_RFESOFT0_S 20U 1164 #define LRFDDBELL_IMASK0_RFESOFT0_EN 0x00100000U 1165 #define LRFDDBELL_IMASK0_RFESOFT0_DIS 0x00000000U 1166 1167 // Field: [19] LOCK 1168 // 1169 // LOCK event 1170 // ENUMs: 1171 // EN Enable interrupt mask 1172 // DIS Disable interrupt mask 1173 #define LRFDDBELL_IMASK0_LOCK 0x00080000U 1174 #define LRFDDBELL_IMASK0_LOCK_M 0x00080000U 1175 #define LRFDDBELL_IMASK0_LOCK_S 19U 1176 #define LRFDDBELL_IMASK0_LOCK_EN 0x00080000U 1177 #define LRFDDBELL_IMASK0_LOCK_DIS 0x00000000U 1178 1179 // Field: [18] LOL 1180 // 1181 // LOSS_OF_LOCK event 1182 // ENUMs: 1183 // EN Enable interrupt mask 1184 // DIS Disable interrupt mask 1185 #define LRFDDBELL_IMASK0_LOL 0x00040000U 1186 #define LRFDDBELL_IMASK0_LOL_M 0x00040000U 1187 #define LRFDDBELL_IMASK0_LOL_S 18U 1188 #define LRFDDBELL_IMASK0_LOL_EN 0x00040000U 1189 #define LRFDDBELL_IMASK0_LOL_DIS 0x00000000U 1190 1191 // Field: [17] TXFIFO 1192 // 1193 // TXFIFO event 1194 // ENUMs: 1195 // EN Enable interrupt mask 1196 // DIS Disable interrupt mask 1197 #define LRFDDBELL_IMASK0_TXFIFO 0x00020000U 1198 #define LRFDDBELL_IMASK0_TXFIFO_M 0x00020000U 1199 #define LRFDDBELL_IMASK0_TXFIFO_S 17U 1200 #define LRFDDBELL_IMASK0_TXFIFO_EN 0x00020000U 1201 #define LRFDDBELL_IMASK0_TXFIFO_DIS 0x00000000U 1202 1203 // Field: [16] RXFIFO 1204 // 1205 // RXFIFO event 1206 // ENUMs: 1207 // EN Enable interrupt mask 1208 // DIS Disable interrupt mask 1209 #define LRFDDBELL_IMASK0_RXFIFO 0x00010000U 1210 #define LRFDDBELL_IMASK0_RXFIFO_M 0x00010000U 1211 #define LRFDDBELL_IMASK0_RXFIFO_S 16U 1212 #define LRFDDBELL_IMASK0_RXFIFO_EN 0x00010000U 1213 #define LRFDDBELL_IMASK0_RXFIFO_DIS 0x00000000U 1214 1215 // Field: [15] PBE15 1216 // 1217 // PBE15 event 1218 // ENUMs: 1219 // EN Enable interrupt mask 1220 // DIS Disable interrupt mask 1221 #define LRFDDBELL_IMASK0_PBE15 0x00008000U 1222 #define LRFDDBELL_IMASK0_PBE15_M 0x00008000U 1223 #define LRFDDBELL_IMASK0_PBE15_S 15U 1224 #define LRFDDBELL_IMASK0_PBE15_EN 0x00008000U 1225 #define LRFDDBELL_IMASK0_PBE15_DIS 0x00000000U 1226 1227 // Field: [14] PBE14 1228 // 1229 // PBE14 event 1230 // ENUMs: 1231 // EN Enable interrupt mask 1232 // DIS Disable interrupt mask 1233 #define LRFDDBELL_IMASK0_PBE14 0x00004000U 1234 #define LRFDDBELL_IMASK0_PBE14_M 0x00004000U 1235 #define LRFDDBELL_IMASK0_PBE14_S 14U 1236 #define LRFDDBELL_IMASK0_PBE14_EN 0x00004000U 1237 #define LRFDDBELL_IMASK0_PBE14_DIS 0x00000000U 1238 1239 // Field: [13] PBE13 1240 // 1241 // PBE13 event 1242 // ENUMs: 1243 // EN Enable interrupt mask 1244 // DIS Disable interrupt mask 1245 #define LRFDDBELL_IMASK0_PBE13 0x00002000U 1246 #define LRFDDBELL_IMASK0_PBE13_M 0x00002000U 1247 #define LRFDDBELL_IMASK0_PBE13_S 13U 1248 #define LRFDDBELL_IMASK0_PBE13_EN 0x00002000U 1249 #define LRFDDBELL_IMASK0_PBE13_DIS 0x00000000U 1250 1251 // Field: [12] PBE12 1252 // 1253 // PBE12 event 1254 // ENUMs: 1255 // EN Enable interrupt mask 1256 // DIS Disable interrupt mask 1257 #define LRFDDBELL_IMASK0_PBE12 0x00001000U 1258 #define LRFDDBELL_IMASK0_PBE12_M 0x00001000U 1259 #define LRFDDBELL_IMASK0_PBE12_S 12U 1260 #define LRFDDBELL_IMASK0_PBE12_EN 0x00001000U 1261 #define LRFDDBELL_IMASK0_PBE12_DIS 0x00000000U 1262 1263 // Field: [11] PBE11 1264 // 1265 // PBE11 event 1266 // ENUMs: 1267 // EN Enable interrupt mask 1268 // DIS Disable interrupt mask 1269 #define LRFDDBELL_IMASK0_PBE11 0x00000800U 1270 #define LRFDDBELL_IMASK0_PBE11_M 0x00000800U 1271 #define LRFDDBELL_IMASK0_PBE11_S 11U 1272 #define LRFDDBELL_IMASK0_PBE11_EN 0x00000800U 1273 #define LRFDDBELL_IMASK0_PBE11_DIS 0x00000000U 1274 1275 // Field: [10] PBE10 1276 // 1277 // PBE10 event 1278 // ENUMs: 1279 // EN Enable interrupt mask 1280 // DIS Disable interrupt mask 1281 #define LRFDDBELL_IMASK0_PBE10 0x00000400U 1282 #define LRFDDBELL_IMASK0_PBE10_M 0x00000400U 1283 #define LRFDDBELL_IMASK0_PBE10_S 10U 1284 #define LRFDDBELL_IMASK0_PBE10_EN 0x00000400U 1285 #define LRFDDBELL_IMASK0_PBE10_DIS 0x00000000U 1286 1287 // Field: [8] PBE8 1288 // 1289 // PBE8 event 1290 // ENUMs: 1291 // EN Enable interrupt mask 1292 // DIS Disable interrupt mask 1293 #define LRFDDBELL_IMASK0_PBE8 0x00000100U 1294 #define LRFDDBELL_IMASK0_PBE8_M 0x00000100U 1295 #define LRFDDBELL_IMASK0_PBE8_S 8U 1296 #define LRFDDBELL_IMASK0_PBE8_EN 0x00000100U 1297 #define LRFDDBELL_IMASK0_PBE8_DIS 0x00000000U 1298 1299 // Field: [7] PBE7 1300 // 1301 // PBE7 event 1302 // ENUMs: 1303 // EN Enable interrupt mask 1304 // DIS Disable interrupt mask 1305 #define LRFDDBELL_IMASK0_PBE7 0x00000080U 1306 #define LRFDDBELL_IMASK0_PBE7_M 0x00000080U 1307 #define LRFDDBELL_IMASK0_PBE7_S 7U 1308 #define LRFDDBELL_IMASK0_PBE7_EN 0x00000080U 1309 #define LRFDDBELL_IMASK0_PBE7_DIS 0x00000000U 1310 1311 // Field: [6] PBE6 1312 // 1313 // PBE6 event 1314 // ENUMs: 1315 // EN Enable interrupt mask 1316 // DIS Disable interrupt mask 1317 #define LRFDDBELL_IMASK0_PBE6 0x00000040U 1318 #define LRFDDBELL_IMASK0_PBE6_M 0x00000040U 1319 #define LRFDDBELL_IMASK0_PBE6_S 6U 1320 #define LRFDDBELL_IMASK0_PBE6_EN 0x00000040U 1321 #define LRFDDBELL_IMASK0_PBE6_DIS 0x00000000U 1322 1323 // Field: [5] PBE5 1324 // 1325 // PBE5 event 1326 // ENUMs: 1327 // EN Enable interrupt mask 1328 // DIS Disable interrupt mask 1329 #define LRFDDBELL_IMASK0_PBE5 0x00000020U 1330 #define LRFDDBELL_IMASK0_PBE5_M 0x00000020U 1331 #define LRFDDBELL_IMASK0_PBE5_S 5U 1332 #define LRFDDBELL_IMASK0_PBE5_EN 0x00000020U 1333 #define LRFDDBELL_IMASK0_PBE5_DIS 0x00000000U 1334 1335 // Field: [4] PBE4 1336 // 1337 // PBE4 event 1338 // ENUMs: 1339 // EN Enable interrupt mask 1340 // DIS Disable interrupt mask 1341 #define LRFDDBELL_IMASK0_PBE4 0x00000010U 1342 #define LRFDDBELL_IMASK0_PBE4_M 0x00000010U 1343 #define LRFDDBELL_IMASK0_PBE4_S 4U 1344 #define LRFDDBELL_IMASK0_PBE4_EN 0x00000010U 1345 #define LRFDDBELL_IMASK0_PBE4_DIS 0x00000000U 1346 1347 // Field: [3] PBE3 1348 // 1349 // PBE3 event 1350 // ENUMs: 1351 // EN Enable interrupt mask 1352 // DIS Disable interrupt mask 1353 #define LRFDDBELL_IMASK0_PBE3 0x00000008U 1354 #define LRFDDBELL_IMASK0_PBE3_M 0x00000008U 1355 #define LRFDDBELL_IMASK0_PBE3_S 3U 1356 #define LRFDDBELL_IMASK0_PBE3_EN 0x00000008U 1357 #define LRFDDBELL_IMASK0_PBE3_DIS 0x00000000U 1358 1359 // Field: [2] PBE2 1360 // 1361 // PBE2 event 1362 // ENUMs: 1363 // EN Enable interrupt mask 1364 // DIS Disable interrupt mask 1365 #define LRFDDBELL_IMASK0_PBE2 0x00000004U 1366 #define LRFDDBELL_IMASK0_PBE2_M 0x00000004U 1367 #define LRFDDBELL_IMASK0_PBE2_S 2U 1368 #define LRFDDBELL_IMASK0_PBE2_EN 0x00000004U 1369 #define LRFDDBELL_IMASK0_PBE2_DIS 0x00000000U 1370 1371 // Field: [1] PBE1 1372 // 1373 // PBE1 event 1374 // ENUMs: 1375 // EN Enable interrupt mask 1376 // DIS Disable interrupt mask 1377 #define LRFDDBELL_IMASK0_PBE1 0x00000002U 1378 #define LRFDDBELL_IMASK0_PBE1_M 0x00000002U 1379 #define LRFDDBELL_IMASK0_PBE1_S 1U 1380 #define LRFDDBELL_IMASK0_PBE1_EN 0x00000002U 1381 #define LRFDDBELL_IMASK0_PBE1_DIS 0x00000000U 1382 1383 // Field: [0] PBE0 1384 // 1385 // PBE0 event 1386 // ENUMs: 1387 // EN Enable interrupt mask 1388 // DIS Disable interrupt mask 1389 #define LRFDDBELL_IMASK0_PBE0 0x00000001U 1390 #define LRFDDBELL_IMASK0_PBE0_M 0x00000001U 1391 #define LRFDDBELL_IMASK0_PBE0_S 0U 1392 #define LRFDDBELL_IMASK0_PBE0_EN 0x00000001U 1393 #define LRFDDBELL_IMASK0_PBE0_DIS 0x00000000U 1394 1395 //***************************************************************************** 1396 // 1397 // Register: LRFDDBELL_O_RIS0 1398 // 1399 //***************************************************************************** 1400 // Field: [31] SYSTIM2 1401 // 1402 // SYSTIM2 event 1403 // ENUMs: 1404 // SET Interrupt occurred 1405 // CLR Interrupt did not occur 1406 #define LRFDDBELL_RIS0_SYSTIM2 0x80000000U 1407 #define LRFDDBELL_RIS0_SYSTIM2_M 0x80000000U 1408 #define LRFDDBELL_RIS0_SYSTIM2_S 31U 1409 #define LRFDDBELL_RIS0_SYSTIM2_SET 0x80000000U 1410 #define LRFDDBELL_RIS0_SYSTIM2_CLR 0x00000000U 1411 1412 // Field: [30] SYSTIM1 1413 // 1414 // SYSTIM1 event 1415 // ENUMs: 1416 // SET Interrupt occurred 1417 // CLR Interrupt did not occur 1418 #define LRFDDBELL_RIS0_SYSTIM1 0x40000000U 1419 #define LRFDDBELL_RIS0_SYSTIM1_M 0x40000000U 1420 #define LRFDDBELL_RIS0_SYSTIM1_S 30U 1421 #define LRFDDBELL_RIS0_SYSTIM1_SET 0x40000000U 1422 #define LRFDDBELL_RIS0_SYSTIM1_CLR 0x00000000U 1423 1424 // Field: [29] SYSTIM0 1425 // 1426 // SYSTIM0 event 1427 // ENUMs: 1428 // SET Interrupt occurred 1429 // CLR Interrupt did not occur 1430 #define LRFDDBELL_RIS0_SYSTIM0 0x20000000U 1431 #define LRFDDBELL_RIS0_SYSTIM0_M 0x20000000U 1432 #define LRFDDBELL_RIS0_SYSTIM0_S 29U 1433 #define LRFDDBELL_RIS0_SYSTIM0_SET 0x20000000U 1434 #define LRFDDBELL_RIS0_SYSTIM0_CLR 0x00000000U 1435 1436 // Field: [28] MDMDONE 1437 // 1438 // MDMDONE event 1439 // ENUMs: 1440 // SET Interrupt occurred 1441 // CLR Interrupt did not occur 1442 #define LRFDDBELL_RIS0_MDMDONE 0x10000000U 1443 #define LRFDDBELL_RIS0_MDMDONE_M 0x10000000U 1444 #define LRFDDBELL_RIS0_MDMDONE_S 28U 1445 #define LRFDDBELL_RIS0_MDMDONE_SET 0x10000000U 1446 #define LRFDDBELL_RIS0_MDMDONE_CLR 0x00000000U 1447 1448 // Field: [27] MDMIN 1449 // 1450 // MDMIN event 1451 // ENUMs: 1452 // SET Interrupt occurred 1453 // CLR Interrupt did not occur 1454 #define LRFDDBELL_RIS0_MDMIN 0x08000000U 1455 #define LRFDDBELL_RIS0_MDMIN_M 0x08000000U 1456 #define LRFDDBELL_RIS0_MDMIN_S 27U 1457 #define LRFDDBELL_RIS0_MDMIN_SET 0x08000000U 1458 #define LRFDDBELL_RIS0_MDMIN_CLR 0x00000000U 1459 1460 // Field: [26] MDMOUT 1461 // 1462 // MDMOUT event 1463 // ENUMs: 1464 // SET Interrupt occurred 1465 // CLR Interrupt did not occur 1466 #define LRFDDBELL_RIS0_MDMOUT 0x04000000U 1467 #define LRFDDBELL_RIS0_MDMOUT_M 0x04000000U 1468 #define LRFDDBELL_RIS0_MDMOUT_S 26U 1469 #define LRFDDBELL_RIS0_MDMOUT_SET 0x04000000U 1470 #define LRFDDBELL_RIS0_MDMOUT_CLR 0x00000000U 1471 1472 // Field: [25] MDMSOFT2 1473 // 1474 // MDMSOFT event 1475 // ENUMs: 1476 // SET Interrupt occurred 1477 // CLR Interrupt did not occur 1478 #define LRFDDBELL_RIS0_MDMSOFT2 0x02000000U 1479 #define LRFDDBELL_RIS0_MDMSOFT2_M 0x02000000U 1480 #define LRFDDBELL_RIS0_MDMSOFT2_S 25U 1481 #define LRFDDBELL_RIS0_MDMSOFT2_SET 0x02000000U 1482 #define LRFDDBELL_RIS0_MDMSOFT2_CLR 0x00000000U 1483 1484 // Field: [24] MDMSOFT1 1485 // 1486 // MDMSOFT1 event 1487 // ENUMs: 1488 // SET Interrupt occurred 1489 // CLR Interrupt did not occur 1490 #define LRFDDBELL_RIS0_MDMSOFT1 0x01000000U 1491 #define LRFDDBELL_RIS0_MDMSOFT1_M 0x01000000U 1492 #define LRFDDBELL_RIS0_MDMSOFT1_S 24U 1493 #define LRFDDBELL_RIS0_MDMSOFT1_SET 0x01000000U 1494 #define LRFDDBELL_RIS0_MDMSOFT1_CLR 0x00000000U 1495 1496 // Field: [23] MDMSOFT0 1497 // 1498 // MDMSOFT event 1499 // ENUMs: 1500 // SET Interrupt occurred 1501 // CLR Interrupt did not occur 1502 #define LRFDDBELL_RIS0_MDMSOFT0 0x00800000U 1503 #define LRFDDBELL_RIS0_MDMSOFT0_M 0x00800000U 1504 #define LRFDDBELL_RIS0_MDMSOFT0_S 23U 1505 #define LRFDDBELL_RIS0_MDMSOFT0_SET 0x00800000U 1506 #define LRFDDBELL_RIS0_MDMSOFT0_CLR 0x00000000U 1507 1508 // Field: [22] RFEDONE 1509 // 1510 // RFEDONE event 1511 // ENUMs: 1512 // SET Interrupt occurred 1513 // CLR Interrupt did not occur 1514 #define LRFDDBELL_RIS0_RFEDONE 0x00400000U 1515 #define LRFDDBELL_RIS0_RFEDONE_M 0x00400000U 1516 #define LRFDDBELL_RIS0_RFEDONE_S 22U 1517 #define LRFDDBELL_RIS0_RFEDONE_SET 0x00400000U 1518 #define LRFDDBELL_RIS0_RFEDONE_CLR 0x00000000U 1519 1520 // Field: [21] RFESOFT1 1521 // 1522 // RFESOFT1 event 1523 // ENUMs: 1524 // SET Interrupt occurred 1525 // CLR Interrupt did not occur 1526 #define LRFDDBELL_RIS0_RFESOFT1 0x00200000U 1527 #define LRFDDBELL_RIS0_RFESOFT1_M 0x00200000U 1528 #define LRFDDBELL_RIS0_RFESOFT1_S 21U 1529 #define LRFDDBELL_RIS0_RFESOFT1_SET 0x00200000U 1530 #define LRFDDBELL_RIS0_RFESOFT1_CLR 0x00000000U 1531 1532 // Field: [20] RFESOFT0 1533 // 1534 // RFESOFT0 event 1535 // ENUMs: 1536 // SET Interrupt occurred 1537 // CLR Interrupt did not occur 1538 #define LRFDDBELL_RIS0_RFESOFT0 0x00100000U 1539 #define LRFDDBELL_RIS0_RFESOFT0_M 0x00100000U 1540 #define LRFDDBELL_RIS0_RFESOFT0_S 20U 1541 #define LRFDDBELL_RIS0_RFESOFT0_SET 0x00100000U 1542 #define LRFDDBELL_RIS0_RFESOFT0_CLR 0x00000000U 1543 1544 // Field: [19] LOCK 1545 // 1546 // LOCK event 1547 // ENUMs: 1548 // SET Interrupt occurred 1549 // CLR Interrupt did not occur 1550 #define LRFDDBELL_RIS0_LOCK 0x00080000U 1551 #define LRFDDBELL_RIS0_LOCK_M 0x00080000U 1552 #define LRFDDBELL_RIS0_LOCK_S 19U 1553 #define LRFDDBELL_RIS0_LOCK_SET 0x00080000U 1554 #define LRFDDBELL_RIS0_LOCK_CLR 0x00000000U 1555 1556 // Field: [18] LOL 1557 // 1558 // LOSS_OF_LOCK event 1559 // ENUMs: 1560 // SET Interrupt occurred 1561 // CLR Interrupt did not occur 1562 #define LRFDDBELL_RIS0_LOL 0x00040000U 1563 #define LRFDDBELL_RIS0_LOL_M 0x00040000U 1564 #define LRFDDBELL_RIS0_LOL_S 18U 1565 #define LRFDDBELL_RIS0_LOL_SET 0x00040000U 1566 #define LRFDDBELL_RIS0_LOL_CLR 0x00000000U 1567 1568 // Field: [17] TXFIFO 1569 // 1570 // TXFIFO event 1571 // ENUMs: 1572 // SET Interrupt occurred 1573 // CLR Interrupt did not occur 1574 #define LRFDDBELL_RIS0_TXFIFO 0x00020000U 1575 #define LRFDDBELL_RIS0_TXFIFO_M 0x00020000U 1576 #define LRFDDBELL_RIS0_TXFIFO_S 17U 1577 #define LRFDDBELL_RIS0_TXFIFO_SET 0x00020000U 1578 #define LRFDDBELL_RIS0_TXFIFO_CLR 0x00000000U 1579 1580 // Field: [16] RXFIFO 1581 // 1582 // RXFIFO event 1583 // ENUMs: 1584 // SET Interrupt occurred 1585 // CLR Interrupt did not occur 1586 #define LRFDDBELL_RIS0_RXFIFO 0x00010000U 1587 #define LRFDDBELL_RIS0_RXFIFO_M 0x00010000U 1588 #define LRFDDBELL_RIS0_RXFIFO_S 16U 1589 #define LRFDDBELL_RIS0_RXFIFO_SET 0x00010000U 1590 #define LRFDDBELL_RIS0_RXFIFO_CLR 0x00000000U 1591 1592 // Field: [15] PBE15 1593 // 1594 // PBE15 event 1595 // ENUMs: 1596 // SET Interrupt occurred 1597 // CLR Interrupt did not occur 1598 #define LRFDDBELL_RIS0_PBE15 0x00008000U 1599 #define LRFDDBELL_RIS0_PBE15_M 0x00008000U 1600 #define LRFDDBELL_RIS0_PBE15_S 15U 1601 #define LRFDDBELL_RIS0_PBE15_SET 0x00008000U 1602 #define LRFDDBELL_RIS0_PBE15_CLR 0x00000000U 1603 1604 // Field: [14] PBE14 1605 // 1606 // PBE14 event 1607 // ENUMs: 1608 // SET Interrupt occurred 1609 // CLR Interrupt did not occur 1610 #define LRFDDBELL_RIS0_PBE14 0x00004000U 1611 #define LRFDDBELL_RIS0_PBE14_M 0x00004000U 1612 #define LRFDDBELL_RIS0_PBE14_S 14U 1613 #define LRFDDBELL_RIS0_PBE14_SET 0x00004000U 1614 #define LRFDDBELL_RIS0_PBE14_CLR 0x00000000U 1615 1616 // Field: [13] PBE13 1617 // 1618 // PBE13 event 1619 // ENUMs: 1620 // SET Interrupt occurred 1621 // CLR Interrupt did not occur 1622 #define LRFDDBELL_RIS0_PBE13 0x00002000U 1623 #define LRFDDBELL_RIS0_PBE13_M 0x00002000U 1624 #define LRFDDBELL_RIS0_PBE13_S 13U 1625 #define LRFDDBELL_RIS0_PBE13_SET 0x00002000U 1626 #define LRFDDBELL_RIS0_PBE13_CLR 0x00000000U 1627 1628 // Field: [12] PBE12 1629 // 1630 // PBE12 event 1631 // ENUMs: 1632 // SET Interrupt occurred 1633 // CLR Interrupt did not occur 1634 #define LRFDDBELL_RIS0_PBE12 0x00001000U 1635 #define LRFDDBELL_RIS0_PBE12_M 0x00001000U 1636 #define LRFDDBELL_RIS0_PBE12_S 12U 1637 #define LRFDDBELL_RIS0_PBE12_SET 0x00001000U 1638 #define LRFDDBELL_RIS0_PBE12_CLR 0x00000000U 1639 1640 // Field: [11] PBE11 1641 // 1642 // PBE11 event 1643 // ENUMs: 1644 // SET Interrupt occurred 1645 // CLR Interrupt did not occur 1646 #define LRFDDBELL_RIS0_PBE11 0x00000800U 1647 #define LRFDDBELL_RIS0_PBE11_M 0x00000800U 1648 #define LRFDDBELL_RIS0_PBE11_S 11U 1649 #define LRFDDBELL_RIS0_PBE11_SET 0x00000800U 1650 #define LRFDDBELL_RIS0_PBE11_CLR 0x00000000U 1651 1652 // Field: [10] PBE10 1653 // 1654 // PBE10 event 1655 // ENUMs: 1656 // SET Interrupt occurred 1657 // CLR Interrupt did not occur 1658 #define LRFDDBELL_RIS0_PBE10 0x00000400U 1659 #define LRFDDBELL_RIS0_PBE10_M 0x00000400U 1660 #define LRFDDBELL_RIS0_PBE10_S 10U 1661 #define LRFDDBELL_RIS0_PBE10_SET 0x00000400U 1662 #define LRFDDBELL_RIS0_PBE10_CLR 0x00000000U 1663 1664 // Field: [9] PBE9 1665 // 1666 // PBE9 event 1667 // ENUMs: 1668 // SET Interrupt occurred 1669 // CLR Interrupt did not occur 1670 #define LRFDDBELL_RIS0_PBE9 0x00000200U 1671 #define LRFDDBELL_RIS0_PBE9_M 0x00000200U 1672 #define LRFDDBELL_RIS0_PBE9_S 9U 1673 #define LRFDDBELL_RIS0_PBE9_SET 0x00000200U 1674 #define LRFDDBELL_RIS0_PBE9_CLR 0x00000000U 1675 1676 // Field: [8] PBE8 1677 // 1678 // PBE8 event 1679 // ENUMs: 1680 // SET Interrupt occurred 1681 // CLR Interrupt did not occur 1682 #define LRFDDBELL_RIS0_PBE8 0x00000100U 1683 #define LRFDDBELL_RIS0_PBE8_M 0x00000100U 1684 #define LRFDDBELL_RIS0_PBE8_S 8U 1685 #define LRFDDBELL_RIS0_PBE8_SET 0x00000100U 1686 #define LRFDDBELL_RIS0_PBE8_CLR 0x00000000U 1687 1688 // Field: [7] PBE7 1689 // 1690 // PBE7 event 1691 // ENUMs: 1692 // SET Interrupt occurred 1693 // CLR Interrupt did not occur 1694 #define LRFDDBELL_RIS0_PBE7 0x00000080U 1695 #define LRFDDBELL_RIS0_PBE7_M 0x00000080U 1696 #define LRFDDBELL_RIS0_PBE7_S 7U 1697 #define LRFDDBELL_RIS0_PBE7_SET 0x00000080U 1698 #define LRFDDBELL_RIS0_PBE7_CLR 0x00000000U 1699 1700 // Field: [6] PBE6 1701 // 1702 // PBE6 event 1703 // ENUMs: 1704 // SET Interrupt occurred 1705 // CLR Interrupt did not occur 1706 #define LRFDDBELL_RIS0_PBE6 0x00000040U 1707 #define LRFDDBELL_RIS0_PBE6_M 0x00000040U 1708 #define LRFDDBELL_RIS0_PBE6_S 6U 1709 #define LRFDDBELL_RIS0_PBE6_SET 0x00000040U 1710 #define LRFDDBELL_RIS0_PBE6_CLR 0x00000000U 1711 1712 // Field: [5] PBE5 1713 // 1714 // PBE5 event 1715 // ENUMs: 1716 // SET Interrupt occurred 1717 // CLR Interrupt did not occur 1718 #define LRFDDBELL_RIS0_PBE5 0x00000020U 1719 #define LRFDDBELL_RIS0_PBE5_M 0x00000020U 1720 #define LRFDDBELL_RIS0_PBE5_S 5U 1721 #define LRFDDBELL_RIS0_PBE5_SET 0x00000020U 1722 #define LRFDDBELL_RIS0_PBE5_CLR 0x00000000U 1723 1724 // Field: [4] PBE4 1725 // 1726 // PBE4 event 1727 // ENUMs: 1728 // SET Interrupt occurred 1729 // CLR Interrupt did not occur 1730 #define LRFDDBELL_RIS0_PBE4 0x00000010U 1731 #define LRFDDBELL_RIS0_PBE4_M 0x00000010U 1732 #define LRFDDBELL_RIS0_PBE4_S 4U 1733 #define LRFDDBELL_RIS0_PBE4_SET 0x00000010U 1734 #define LRFDDBELL_RIS0_PBE4_CLR 0x00000000U 1735 1736 // Field: [3] PBE3 1737 // 1738 // PBE3 event 1739 // ENUMs: 1740 // SET Interrupt occurred 1741 // CLR Interrupt did not occur 1742 #define LRFDDBELL_RIS0_PBE3 0x00000008U 1743 #define LRFDDBELL_RIS0_PBE3_M 0x00000008U 1744 #define LRFDDBELL_RIS0_PBE3_S 3U 1745 #define LRFDDBELL_RIS0_PBE3_SET 0x00000008U 1746 #define LRFDDBELL_RIS0_PBE3_CLR 0x00000000U 1747 1748 // Field: [2] PBE2 1749 // 1750 // PBE2 event 1751 // ENUMs: 1752 // SET Interrupt occurred 1753 // CLR Interrupt did not occur 1754 #define LRFDDBELL_RIS0_PBE2 0x00000004U 1755 #define LRFDDBELL_RIS0_PBE2_M 0x00000004U 1756 #define LRFDDBELL_RIS0_PBE2_S 2U 1757 #define LRFDDBELL_RIS0_PBE2_SET 0x00000004U 1758 #define LRFDDBELL_RIS0_PBE2_CLR 0x00000000U 1759 1760 // Field: [1] PBE1 1761 // 1762 // PBE1 event 1763 // ENUMs: 1764 // SET Interrupt occurred 1765 // CLR Interrupt did not occur 1766 #define LRFDDBELL_RIS0_PBE1 0x00000002U 1767 #define LRFDDBELL_RIS0_PBE1_M 0x00000002U 1768 #define LRFDDBELL_RIS0_PBE1_S 1U 1769 #define LRFDDBELL_RIS0_PBE1_SET 0x00000002U 1770 #define LRFDDBELL_RIS0_PBE1_CLR 0x00000000U 1771 1772 // Field: [0] PBE0 1773 // 1774 // PBE0 event 1775 // ENUMs: 1776 // SET Interrupt occurred 1777 // CLR Interrupt did not occur 1778 #define LRFDDBELL_RIS0_PBE0 0x00000001U 1779 #define LRFDDBELL_RIS0_PBE0_M 0x00000001U 1780 #define LRFDDBELL_RIS0_PBE0_S 0U 1781 #define LRFDDBELL_RIS0_PBE0_SET 0x00000001U 1782 #define LRFDDBELL_RIS0_PBE0_CLR 0x00000000U 1783 1784 //***************************************************************************** 1785 // 1786 // Register: LRFDDBELL_O_MIS0 1787 // 1788 //***************************************************************************** 1789 // Field: [31] SYSTIM2 1790 // 1791 // SYSTIM2 event 1792 // ENUMs: 1793 // SET Interrupt occurred 1794 // CLR Interrupt did not occur 1795 #define LRFDDBELL_MIS0_SYSTIM2 0x80000000U 1796 #define LRFDDBELL_MIS0_SYSTIM2_M 0x80000000U 1797 #define LRFDDBELL_MIS0_SYSTIM2_S 31U 1798 #define LRFDDBELL_MIS0_SYSTIM2_SET 0x80000000U 1799 #define LRFDDBELL_MIS0_SYSTIM2_CLR 0x00000000U 1800 1801 // Field: [30] SYSTIM1 1802 // 1803 // SYSTIM1 event 1804 // ENUMs: 1805 // SET Interrupt occurred 1806 // CLR Interrupt did not occur 1807 #define LRFDDBELL_MIS0_SYSTIM1 0x40000000U 1808 #define LRFDDBELL_MIS0_SYSTIM1_M 0x40000000U 1809 #define LRFDDBELL_MIS0_SYSTIM1_S 30U 1810 #define LRFDDBELL_MIS0_SYSTIM1_SET 0x40000000U 1811 #define LRFDDBELL_MIS0_SYSTIM1_CLR 0x00000000U 1812 1813 // Field: [29] SYSTIM0 1814 // 1815 // SYSTIM0 event 1816 // ENUMs: 1817 // SET Interrupt occurred 1818 // CLR Interrupt did not occur 1819 #define LRFDDBELL_MIS0_SYSTIM0 0x20000000U 1820 #define LRFDDBELL_MIS0_SYSTIM0_M 0x20000000U 1821 #define LRFDDBELL_MIS0_SYSTIM0_S 29U 1822 #define LRFDDBELL_MIS0_SYSTIM0_SET 0x20000000U 1823 #define LRFDDBELL_MIS0_SYSTIM0_CLR 0x00000000U 1824 1825 // Field: [28] MDMDONE 1826 // 1827 // MDMDONE event 1828 // ENUMs: 1829 // SET Interrupt occurred 1830 // CLR Interrupt did not occur 1831 #define LRFDDBELL_MIS0_MDMDONE 0x10000000U 1832 #define LRFDDBELL_MIS0_MDMDONE_M 0x10000000U 1833 #define LRFDDBELL_MIS0_MDMDONE_S 28U 1834 #define LRFDDBELL_MIS0_MDMDONE_SET 0x10000000U 1835 #define LRFDDBELL_MIS0_MDMDONE_CLR 0x00000000U 1836 1837 // Field: [27] MDMIN 1838 // 1839 // MDMIN event 1840 // ENUMs: 1841 // SET Interrupt occurred 1842 // CLR Interrupt did not occur 1843 #define LRFDDBELL_MIS0_MDMIN 0x08000000U 1844 #define LRFDDBELL_MIS0_MDMIN_M 0x08000000U 1845 #define LRFDDBELL_MIS0_MDMIN_S 27U 1846 #define LRFDDBELL_MIS0_MDMIN_SET 0x08000000U 1847 #define LRFDDBELL_MIS0_MDMIN_CLR 0x00000000U 1848 1849 // Field: [26] MDMOUT 1850 // 1851 // MDMOUT event 1852 // ENUMs: 1853 // SET Interrupt occurred 1854 // CLR Interrupt did not occur 1855 #define LRFDDBELL_MIS0_MDMOUT 0x04000000U 1856 #define LRFDDBELL_MIS0_MDMOUT_M 0x04000000U 1857 #define LRFDDBELL_MIS0_MDMOUT_S 26U 1858 #define LRFDDBELL_MIS0_MDMOUT_SET 0x04000000U 1859 #define LRFDDBELL_MIS0_MDMOUT_CLR 0x00000000U 1860 1861 // Field: [25] MDMSOFT2 1862 // 1863 // MDMSOFT event 1864 // ENUMs: 1865 // SET Interrupt occurred 1866 // CLR Interrupt did not occur 1867 #define LRFDDBELL_MIS0_MDMSOFT2 0x02000000U 1868 #define LRFDDBELL_MIS0_MDMSOFT2_M 0x02000000U 1869 #define LRFDDBELL_MIS0_MDMSOFT2_S 25U 1870 #define LRFDDBELL_MIS0_MDMSOFT2_SET 0x02000000U 1871 #define LRFDDBELL_MIS0_MDMSOFT2_CLR 0x00000000U 1872 1873 // Field: [24] MDMSOFT1 1874 // 1875 // MDMSOFT1 event 1876 // ENUMs: 1877 // SET Interrupt occurred 1878 // CLR Interrupt did not occur 1879 #define LRFDDBELL_MIS0_MDMSOFT1 0x01000000U 1880 #define LRFDDBELL_MIS0_MDMSOFT1_M 0x01000000U 1881 #define LRFDDBELL_MIS0_MDMSOFT1_S 24U 1882 #define LRFDDBELL_MIS0_MDMSOFT1_SET 0x01000000U 1883 #define LRFDDBELL_MIS0_MDMSOFT1_CLR 0x00000000U 1884 1885 // Field: [23] MDMSOFT0 1886 // 1887 // MDMSOFT event 1888 // ENUMs: 1889 // SET Interrupt occurred 1890 // CLR Interrupt did not occur 1891 #define LRFDDBELL_MIS0_MDMSOFT0 0x00800000U 1892 #define LRFDDBELL_MIS0_MDMSOFT0_M 0x00800000U 1893 #define LRFDDBELL_MIS0_MDMSOFT0_S 23U 1894 #define LRFDDBELL_MIS0_MDMSOFT0_SET 0x00800000U 1895 #define LRFDDBELL_MIS0_MDMSOFT0_CLR 0x00000000U 1896 1897 // Field: [22] RFEDONE 1898 // 1899 // RFEDONE event 1900 // ENUMs: 1901 // SET Interrupt occurred 1902 // CLR Interrupt did not occur 1903 #define LRFDDBELL_MIS0_RFEDONE 0x00400000U 1904 #define LRFDDBELL_MIS0_RFEDONE_M 0x00400000U 1905 #define LRFDDBELL_MIS0_RFEDONE_S 22U 1906 #define LRFDDBELL_MIS0_RFEDONE_SET 0x00400000U 1907 #define LRFDDBELL_MIS0_RFEDONE_CLR 0x00000000U 1908 1909 // Field: [21] RFESOFT1 1910 // 1911 // RFESOFT1 event 1912 // ENUMs: 1913 // SET Interrupt occurred 1914 // CLR Interrupt did not occur 1915 #define LRFDDBELL_MIS0_RFESOFT1 0x00200000U 1916 #define LRFDDBELL_MIS0_RFESOFT1_M 0x00200000U 1917 #define LRFDDBELL_MIS0_RFESOFT1_S 21U 1918 #define LRFDDBELL_MIS0_RFESOFT1_SET 0x00200000U 1919 #define LRFDDBELL_MIS0_RFESOFT1_CLR 0x00000000U 1920 1921 // Field: [20] RFESOFT0 1922 // 1923 // RFESOFT0 event 1924 // ENUMs: 1925 // SET Interrupt occurred 1926 // CLR Interrupt did not occur 1927 #define LRFDDBELL_MIS0_RFESOFT0 0x00100000U 1928 #define LRFDDBELL_MIS0_RFESOFT0_M 0x00100000U 1929 #define LRFDDBELL_MIS0_RFESOFT0_S 20U 1930 #define LRFDDBELL_MIS0_RFESOFT0_SET 0x00100000U 1931 #define LRFDDBELL_MIS0_RFESOFT0_CLR 0x00000000U 1932 1933 // Field: [19] LOCK 1934 // 1935 // LOCK event 1936 // ENUMs: 1937 // SET Interrupt occurred 1938 // CLR Interrupt did not occur 1939 #define LRFDDBELL_MIS0_LOCK 0x00080000U 1940 #define LRFDDBELL_MIS0_LOCK_M 0x00080000U 1941 #define LRFDDBELL_MIS0_LOCK_S 19U 1942 #define LRFDDBELL_MIS0_LOCK_SET 0x00080000U 1943 #define LRFDDBELL_MIS0_LOCK_CLR 0x00000000U 1944 1945 // Field: [18] LOL 1946 // 1947 // LOSS_OF_LOCK event 1948 // ENUMs: 1949 // SET Interrupt occurred 1950 // CLR Interrupt did not occur 1951 #define LRFDDBELL_MIS0_LOL 0x00040000U 1952 #define LRFDDBELL_MIS0_LOL_M 0x00040000U 1953 #define LRFDDBELL_MIS0_LOL_S 18U 1954 #define LRFDDBELL_MIS0_LOL_SET 0x00040000U 1955 #define LRFDDBELL_MIS0_LOL_CLR 0x00000000U 1956 1957 // Field: [17] TXFIFO 1958 // 1959 // TXFIFO event 1960 // ENUMs: 1961 // SET Interrupt occurred 1962 // CLR Interrupt did not occur 1963 #define LRFDDBELL_MIS0_TXFIFO 0x00020000U 1964 #define LRFDDBELL_MIS0_TXFIFO_M 0x00020000U 1965 #define LRFDDBELL_MIS0_TXFIFO_S 17U 1966 #define LRFDDBELL_MIS0_TXFIFO_SET 0x00020000U 1967 #define LRFDDBELL_MIS0_TXFIFO_CLR 0x00000000U 1968 1969 // Field: [16] RXFIFO 1970 // 1971 // RXFIFO event 1972 // ENUMs: 1973 // SET Interrupt occurred 1974 // CLR Interrupt did not occur 1975 #define LRFDDBELL_MIS0_RXFIFO 0x00010000U 1976 #define LRFDDBELL_MIS0_RXFIFO_M 0x00010000U 1977 #define LRFDDBELL_MIS0_RXFIFO_S 16U 1978 #define LRFDDBELL_MIS0_RXFIFO_SET 0x00010000U 1979 #define LRFDDBELL_MIS0_RXFIFO_CLR 0x00000000U 1980 1981 // Field: [15] PBE15 1982 // 1983 // PBE15 event 1984 // ENUMs: 1985 // SET Interrupt occurred 1986 // CLR Interrupt did not occur 1987 #define LRFDDBELL_MIS0_PBE15 0x00008000U 1988 #define LRFDDBELL_MIS0_PBE15_M 0x00008000U 1989 #define LRFDDBELL_MIS0_PBE15_S 15U 1990 #define LRFDDBELL_MIS0_PBE15_SET 0x00008000U 1991 #define LRFDDBELL_MIS0_PBE15_CLR 0x00000000U 1992 1993 // Field: [14] PBE14 1994 // 1995 // PBE14 event 1996 // ENUMs: 1997 // SET Interrupt occurred 1998 // CLR Interrupt did not occur 1999 #define LRFDDBELL_MIS0_PBE14 0x00004000U 2000 #define LRFDDBELL_MIS0_PBE14_M 0x00004000U 2001 #define LRFDDBELL_MIS0_PBE14_S 14U 2002 #define LRFDDBELL_MIS0_PBE14_SET 0x00004000U 2003 #define LRFDDBELL_MIS0_PBE14_CLR 0x00000000U 2004 2005 // Field: [13] PBE13 2006 // 2007 // PBE13 event 2008 // ENUMs: 2009 // SET Interrupt occurred 2010 // CLR Interrupt did not occur 2011 #define LRFDDBELL_MIS0_PBE13 0x00002000U 2012 #define LRFDDBELL_MIS0_PBE13_M 0x00002000U 2013 #define LRFDDBELL_MIS0_PBE13_S 13U 2014 #define LRFDDBELL_MIS0_PBE13_SET 0x00002000U 2015 #define LRFDDBELL_MIS0_PBE13_CLR 0x00000000U 2016 2017 // Field: [12] PBE12 2018 // 2019 // PBE12 event 2020 // ENUMs: 2021 // SET Interrupt occurred 2022 // CLR Interrupt did not occur 2023 #define LRFDDBELL_MIS0_PBE12 0x00001000U 2024 #define LRFDDBELL_MIS0_PBE12_M 0x00001000U 2025 #define LRFDDBELL_MIS0_PBE12_S 12U 2026 #define LRFDDBELL_MIS0_PBE12_SET 0x00001000U 2027 #define LRFDDBELL_MIS0_PBE12_CLR 0x00000000U 2028 2029 // Field: [11] PBE11 2030 // 2031 // PBE11 event 2032 // ENUMs: 2033 // SET Interrupt occurred 2034 // CLR Interrupt did not occur 2035 #define LRFDDBELL_MIS0_PBE11 0x00000800U 2036 #define LRFDDBELL_MIS0_PBE11_M 0x00000800U 2037 #define LRFDDBELL_MIS0_PBE11_S 11U 2038 #define LRFDDBELL_MIS0_PBE11_SET 0x00000800U 2039 #define LRFDDBELL_MIS0_PBE11_CLR 0x00000000U 2040 2041 // Field: [10] PBE10 2042 // 2043 // PBE10 event 2044 // ENUMs: 2045 // SET Interrupt occurred 2046 // CLR Interrupt did not occur 2047 #define LRFDDBELL_MIS0_PBE10 0x00000400U 2048 #define LRFDDBELL_MIS0_PBE10_M 0x00000400U 2049 #define LRFDDBELL_MIS0_PBE10_S 10U 2050 #define LRFDDBELL_MIS0_PBE10_SET 0x00000400U 2051 #define LRFDDBELL_MIS0_PBE10_CLR 0x00000000U 2052 2053 // Field: [9] PBE9 2054 // 2055 // PBE9 event 2056 // ENUMs: 2057 // SET Interrupt occurred 2058 // CLR Interrupt did not occur 2059 #define LRFDDBELL_MIS0_PBE9 0x00000200U 2060 #define LRFDDBELL_MIS0_PBE9_M 0x00000200U 2061 #define LRFDDBELL_MIS0_PBE9_S 9U 2062 #define LRFDDBELL_MIS0_PBE9_SET 0x00000200U 2063 #define LRFDDBELL_MIS0_PBE9_CLR 0x00000000U 2064 2065 // Field: [8] PBE8 2066 // 2067 // PBE8 event 2068 // ENUMs: 2069 // SET Interrupt occurred 2070 // CLR Interrupt did not occur 2071 #define LRFDDBELL_MIS0_PBE8 0x00000100U 2072 #define LRFDDBELL_MIS0_PBE8_M 0x00000100U 2073 #define LRFDDBELL_MIS0_PBE8_S 8U 2074 #define LRFDDBELL_MIS0_PBE8_SET 0x00000100U 2075 #define LRFDDBELL_MIS0_PBE8_CLR 0x00000000U 2076 2077 // Field: [7] PBE7 2078 // 2079 // PBE7 event 2080 // ENUMs: 2081 // SET Interrupt occurred 2082 // CLR Interrupt did not occur 2083 #define LRFDDBELL_MIS0_PBE7 0x00000080U 2084 #define LRFDDBELL_MIS0_PBE7_M 0x00000080U 2085 #define LRFDDBELL_MIS0_PBE7_S 7U 2086 #define LRFDDBELL_MIS0_PBE7_SET 0x00000080U 2087 #define LRFDDBELL_MIS0_PBE7_CLR 0x00000000U 2088 2089 // Field: [6] PBE6 2090 // 2091 // PBE6 event 2092 // ENUMs: 2093 // SET Interrupt occurred 2094 // CLR Interrupt did not occur 2095 #define LRFDDBELL_MIS0_PBE6 0x00000040U 2096 #define LRFDDBELL_MIS0_PBE6_M 0x00000040U 2097 #define LRFDDBELL_MIS0_PBE6_S 6U 2098 #define LRFDDBELL_MIS0_PBE6_SET 0x00000040U 2099 #define LRFDDBELL_MIS0_PBE6_CLR 0x00000000U 2100 2101 // Field: [5] PBE5 2102 // 2103 // PBE5 event 2104 // ENUMs: 2105 // SET Interrupt occurred 2106 // CLR Interrupt did not occur 2107 #define LRFDDBELL_MIS0_PBE5 0x00000020U 2108 #define LRFDDBELL_MIS0_PBE5_M 0x00000020U 2109 #define LRFDDBELL_MIS0_PBE5_S 5U 2110 #define LRFDDBELL_MIS0_PBE5_SET 0x00000020U 2111 #define LRFDDBELL_MIS0_PBE5_CLR 0x00000000U 2112 2113 // Field: [4] PBE4 2114 // 2115 // PBE4 event 2116 // ENUMs: 2117 // SET Interrupt occurred 2118 // CLR Interrupt did not occur 2119 #define LRFDDBELL_MIS0_PBE4 0x00000010U 2120 #define LRFDDBELL_MIS0_PBE4_M 0x00000010U 2121 #define LRFDDBELL_MIS0_PBE4_S 4U 2122 #define LRFDDBELL_MIS0_PBE4_SET 0x00000010U 2123 #define LRFDDBELL_MIS0_PBE4_CLR 0x00000000U 2124 2125 // Field: [3] PBE3 2126 // 2127 // PBE3 event 2128 // ENUMs: 2129 // SET Interrupt occurred 2130 // CLR Interrupt did not occur 2131 #define LRFDDBELL_MIS0_PBE3 0x00000008U 2132 #define LRFDDBELL_MIS0_PBE3_M 0x00000008U 2133 #define LRFDDBELL_MIS0_PBE3_S 3U 2134 #define LRFDDBELL_MIS0_PBE3_SET 0x00000008U 2135 #define LRFDDBELL_MIS0_PBE3_CLR 0x00000000U 2136 2137 // Field: [2] PBE2 2138 // 2139 // PBE2 event 2140 // ENUMs: 2141 // SET Interrupt occurred 2142 // CLR Interrupt did not occur 2143 #define LRFDDBELL_MIS0_PBE2 0x00000004U 2144 #define LRFDDBELL_MIS0_PBE2_M 0x00000004U 2145 #define LRFDDBELL_MIS0_PBE2_S 2U 2146 #define LRFDDBELL_MIS0_PBE2_SET 0x00000004U 2147 #define LRFDDBELL_MIS0_PBE2_CLR 0x00000000U 2148 2149 // Field: [1] PBE1 2150 // 2151 // PBE1 event 2152 // ENUMs: 2153 // SET Interrupt occurred 2154 // CLR Interrupt did not occur 2155 #define LRFDDBELL_MIS0_PBE1 0x00000002U 2156 #define LRFDDBELL_MIS0_PBE1_M 0x00000002U 2157 #define LRFDDBELL_MIS0_PBE1_S 1U 2158 #define LRFDDBELL_MIS0_PBE1_SET 0x00000002U 2159 #define LRFDDBELL_MIS0_PBE1_CLR 0x00000000U 2160 2161 // Field: [0] PBE0 2162 // 2163 // PBE0 event 2164 // ENUMs: 2165 // SET Interrupt occurred 2166 // CLR Interrupt did not occur 2167 #define LRFDDBELL_MIS0_PBE0 0x00000001U 2168 #define LRFDDBELL_MIS0_PBE0_M 0x00000001U 2169 #define LRFDDBELL_MIS0_PBE0_S 0U 2170 #define LRFDDBELL_MIS0_PBE0_SET 0x00000001U 2171 #define LRFDDBELL_MIS0_PBE0_CLR 0x00000000U 2172 2173 //***************************************************************************** 2174 // 2175 // Register: LRFDDBELL_O_ISET0 2176 // 2177 //***************************************************************************** 2178 // Field: [31] SYSTIM2 2179 // 2180 // SYSTIM2 event 2181 // ENUMs: 2182 // SET Set Interrupt 2183 // NOEFF Writing 0 has no effect 2184 #define LRFDDBELL_ISET0_SYSTIM2 0x80000000U 2185 #define LRFDDBELL_ISET0_SYSTIM2_M 0x80000000U 2186 #define LRFDDBELL_ISET0_SYSTIM2_S 31U 2187 #define LRFDDBELL_ISET0_SYSTIM2_SET 0x80000000U 2188 #define LRFDDBELL_ISET0_SYSTIM2_NOEFF 0x00000000U 2189 2190 // Field: [30] SYSTIM1 2191 // 2192 // SYSTIM1 event 2193 // ENUMs: 2194 // SET Set Interrupt 2195 // NOEFF Writing 0 has no effect 2196 #define LRFDDBELL_ISET0_SYSTIM1 0x40000000U 2197 #define LRFDDBELL_ISET0_SYSTIM1_M 0x40000000U 2198 #define LRFDDBELL_ISET0_SYSTIM1_S 30U 2199 #define LRFDDBELL_ISET0_SYSTIM1_SET 0x40000000U 2200 #define LRFDDBELL_ISET0_SYSTIM1_NOEFF 0x00000000U 2201 2202 // Field: [29] SYSTIM0 2203 // 2204 // SYSTIM0 event 2205 // ENUMs: 2206 // SET Set Interrupt 2207 // NOEFF Writing 0 has no effect 2208 #define LRFDDBELL_ISET0_SYSTIM0 0x20000000U 2209 #define LRFDDBELL_ISET0_SYSTIM0_M 0x20000000U 2210 #define LRFDDBELL_ISET0_SYSTIM0_S 29U 2211 #define LRFDDBELL_ISET0_SYSTIM0_SET 0x20000000U 2212 #define LRFDDBELL_ISET0_SYSTIM0_NOEFF 0x00000000U 2213 2214 // Field: [28] MDMDONE 2215 // 2216 // MDMDONE event 2217 // ENUMs: 2218 // SET Set Interrupt 2219 // NOEFF Writing 0 has no effect 2220 #define LRFDDBELL_ISET0_MDMDONE 0x10000000U 2221 #define LRFDDBELL_ISET0_MDMDONE_M 0x10000000U 2222 #define LRFDDBELL_ISET0_MDMDONE_S 28U 2223 #define LRFDDBELL_ISET0_MDMDONE_SET 0x10000000U 2224 #define LRFDDBELL_ISET0_MDMDONE_NOEFF 0x00000000U 2225 2226 // Field: [27] MDMIN 2227 // 2228 // MDMIN event 2229 // ENUMs: 2230 // SET Set Interrupt 2231 // NOEFF Writing 0 has no effect 2232 #define LRFDDBELL_ISET0_MDMIN 0x08000000U 2233 #define LRFDDBELL_ISET0_MDMIN_M 0x08000000U 2234 #define LRFDDBELL_ISET0_MDMIN_S 27U 2235 #define LRFDDBELL_ISET0_MDMIN_SET 0x08000000U 2236 #define LRFDDBELL_ISET0_MDMIN_NOEFF 0x00000000U 2237 2238 // Field: [26] MDMOUT 2239 // 2240 // MDMOUT event 2241 // ENUMs: 2242 // SET Set Interrupt 2243 // NOEFF Writing 0 has no effect 2244 #define LRFDDBELL_ISET0_MDMOUT 0x04000000U 2245 #define LRFDDBELL_ISET0_MDMOUT_M 0x04000000U 2246 #define LRFDDBELL_ISET0_MDMOUT_S 26U 2247 #define LRFDDBELL_ISET0_MDMOUT_SET 0x04000000U 2248 #define LRFDDBELL_ISET0_MDMOUT_NOEFF 0x00000000U 2249 2250 // Field: [25] MDMSOFT2 2251 // 2252 // MDMSOFT event 2253 // ENUMs: 2254 // SET Set Interrupt 2255 // NOEFF Writing 0 has no effect 2256 #define LRFDDBELL_ISET0_MDMSOFT2 0x02000000U 2257 #define LRFDDBELL_ISET0_MDMSOFT2_M 0x02000000U 2258 #define LRFDDBELL_ISET0_MDMSOFT2_S 25U 2259 #define LRFDDBELL_ISET0_MDMSOFT2_SET 0x02000000U 2260 #define LRFDDBELL_ISET0_MDMSOFT2_NOEFF 0x00000000U 2261 2262 // Field: [24] MDMSOFT1 2263 // 2264 // MDMSOFT1 event 2265 // ENUMs: 2266 // SET Set Interrupt 2267 // NOEFF Writing 0 has no effect 2268 #define LRFDDBELL_ISET0_MDMSOFT1 0x01000000U 2269 #define LRFDDBELL_ISET0_MDMSOFT1_M 0x01000000U 2270 #define LRFDDBELL_ISET0_MDMSOFT1_S 24U 2271 #define LRFDDBELL_ISET0_MDMSOFT1_SET 0x01000000U 2272 #define LRFDDBELL_ISET0_MDMSOFT1_NOEFF 0x00000000U 2273 2274 // Field: [23] MDMSOFT0 2275 // 2276 // MDMSOFT event 2277 // ENUMs: 2278 // SET Set Interrupt 2279 // NOEFF Writing 0 has no effect 2280 #define LRFDDBELL_ISET0_MDMSOFT0 0x00800000U 2281 #define LRFDDBELL_ISET0_MDMSOFT0_M 0x00800000U 2282 #define LRFDDBELL_ISET0_MDMSOFT0_S 23U 2283 #define LRFDDBELL_ISET0_MDMSOFT0_SET 0x00800000U 2284 #define LRFDDBELL_ISET0_MDMSOFT0_NOEFF 0x00000000U 2285 2286 // Field: [22] RFEDONE 2287 // 2288 // RFEDONE event 2289 // ENUMs: 2290 // SET Set Interrupt 2291 // NOEFF Writing 0 has no effect 2292 #define LRFDDBELL_ISET0_RFEDONE 0x00400000U 2293 #define LRFDDBELL_ISET0_RFEDONE_M 0x00400000U 2294 #define LRFDDBELL_ISET0_RFEDONE_S 22U 2295 #define LRFDDBELL_ISET0_RFEDONE_SET 0x00400000U 2296 #define LRFDDBELL_ISET0_RFEDONE_NOEFF 0x00000000U 2297 2298 // Field: [21] RFESOFT1 2299 // 2300 // RFESOFT1 event 2301 // ENUMs: 2302 // SET Set Interrupt 2303 // NOEFF Writing 0 has no effect 2304 #define LRFDDBELL_ISET0_RFESOFT1 0x00200000U 2305 #define LRFDDBELL_ISET0_RFESOFT1_M 0x00200000U 2306 #define LRFDDBELL_ISET0_RFESOFT1_S 21U 2307 #define LRFDDBELL_ISET0_RFESOFT1_SET 0x00200000U 2308 #define LRFDDBELL_ISET0_RFESOFT1_NOEFF 0x00000000U 2309 2310 // Field: [20] RFESOFT0 2311 // 2312 // RFESOFT0 event 2313 // ENUMs: 2314 // SET Set Interrupt 2315 // NOEFF Writing 0 has no effect 2316 #define LRFDDBELL_ISET0_RFESOFT0 0x00100000U 2317 #define LRFDDBELL_ISET0_RFESOFT0_M 0x00100000U 2318 #define LRFDDBELL_ISET0_RFESOFT0_S 20U 2319 #define LRFDDBELL_ISET0_RFESOFT0_SET 0x00100000U 2320 #define LRFDDBELL_ISET0_RFESOFT0_NOEFF 0x00000000U 2321 2322 // Field: [19] LOCK 2323 // 2324 // LOCK event 2325 // ENUMs: 2326 // SET Set Interrupt 2327 // NOEFF Writing 0 has no effect 2328 #define LRFDDBELL_ISET0_LOCK 0x00080000U 2329 #define LRFDDBELL_ISET0_LOCK_M 0x00080000U 2330 #define LRFDDBELL_ISET0_LOCK_S 19U 2331 #define LRFDDBELL_ISET0_LOCK_SET 0x00080000U 2332 #define LRFDDBELL_ISET0_LOCK_NOEFF 0x00000000U 2333 2334 // Field: [18] LOL 2335 // 2336 // LOSS_OF_LOCK event 2337 // ENUMs: 2338 // SET Set Interrupt 2339 // NOEFF Writing 0 has no effect 2340 #define LRFDDBELL_ISET0_LOL 0x00040000U 2341 #define LRFDDBELL_ISET0_LOL_M 0x00040000U 2342 #define LRFDDBELL_ISET0_LOL_S 18U 2343 #define LRFDDBELL_ISET0_LOL_SET 0x00040000U 2344 #define LRFDDBELL_ISET0_LOL_NOEFF 0x00000000U 2345 2346 // Field: [17] TXFIFO 2347 // 2348 // TXFIFO event 2349 // ENUMs: 2350 // SET Set Interrupt 2351 // NOEFF Writing 0 has no effect 2352 #define LRFDDBELL_ISET0_TXFIFO 0x00020000U 2353 #define LRFDDBELL_ISET0_TXFIFO_M 0x00020000U 2354 #define LRFDDBELL_ISET0_TXFIFO_S 17U 2355 #define LRFDDBELL_ISET0_TXFIFO_SET 0x00020000U 2356 #define LRFDDBELL_ISET0_TXFIFO_NOEFF 0x00000000U 2357 2358 // Field: [16] RXFIFO 2359 // 2360 // RXFIFO event 2361 // ENUMs: 2362 // SET Set Interrupt 2363 // NOEFF Writing 0 has no effect 2364 #define LRFDDBELL_ISET0_RXFIFO 0x00010000U 2365 #define LRFDDBELL_ISET0_RXFIFO_M 0x00010000U 2366 #define LRFDDBELL_ISET0_RXFIFO_S 16U 2367 #define LRFDDBELL_ISET0_RXFIFO_SET 0x00010000U 2368 #define LRFDDBELL_ISET0_RXFIFO_NOEFF 0x00000000U 2369 2370 // Field: [15] PBE15 2371 // 2372 // PBE15 event 2373 // ENUMs: 2374 // SET Set Interrupt 2375 // NOEFF Writing 0 has no effect 2376 #define LRFDDBELL_ISET0_PBE15 0x00008000U 2377 #define LRFDDBELL_ISET0_PBE15_M 0x00008000U 2378 #define LRFDDBELL_ISET0_PBE15_S 15U 2379 #define LRFDDBELL_ISET0_PBE15_SET 0x00008000U 2380 #define LRFDDBELL_ISET0_PBE15_NOEFF 0x00000000U 2381 2382 // Field: [14] PBE14 2383 // 2384 // PBE14 event 2385 // ENUMs: 2386 // SET Set Interrupt 2387 // NOEFF Writing 0 has no effect 2388 #define LRFDDBELL_ISET0_PBE14 0x00004000U 2389 #define LRFDDBELL_ISET0_PBE14_M 0x00004000U 2390 #define LRFDDBELL_ISET0_PBE14_S 14U 2391 #define LRFDDBELL_ISET0_PBE14_SET 0x00004000U 2392 #define LRFDDBELL_ISET0_PBE14_NOEFF 0x00000000U 2393 2394 // Field: [13] PBE13 2395 // 2396 // PBE13 event 2397 // ENUMs: 2398 // SET Set Interrupt 2399 // NOEFF Writing 0 has no effect 2400 #define LRFDDBELL_ISET0_PBE13 0x00002000U 2401 #define LRFDDBELL_ISET0_PBE13_M 0x00002000U 2402 #define LRFDDBELL_ISET0_PBE13_S 13U 2403 #define LRFDDBELL_ISET0_PBE13_SET 0x00002000U 2404 #define LRFDDBELL_ISET0_PBE13_NOEFF 0x00000000U 2405 2406 // Field: [12] PBE12 2407 // 2408 // PBE12 event 2409 // ENUMs: 2410 // SET Set Interrupt 2411 // NOEFF Writing 0 has no effect 2412 #define LRFDDBELL_ISET0_PBE12 0x00001000U 2413 #define LRFDDBELL_ISET0_PBE12_M 0x00001000U 2414 #define LRFDDBELL_ISET0_PBE12_S 12U 2415 #define LRFDDBELL_ISET0_PBE12_SET 0x00001000U 2416 #define LRFDDBELL_ISET0_PBE12_NOEFF 0x00000000U 2417 2418 // Field: [11] PBE11 2419 // 2420 // PBE11 event 2421 // ENUMs: 2422 // SET Set Interrupt 2423 // NOEFF Writing 0 has no effect 2424 #define LRFDDBELL_ISET0_PBE11 0x00000800U 2425 #define LRFDDBELL_ISET0_PBE11_M 0x00000800U 2426 #define LRFDDBELL_ISET0_PBE11_S 11U 2427 #define LRFDDBELL_ISET0_PBE11_SET 0x00000800U 2428 #define LRFDDBELL_ISET0_PBE11_NOEFF 0x00000000U 2429 2430 // Field: [10] PBE10 2431 // 2432 // PBE10 event 2433 // ENUMs: 2434 // SET Set Interrupt 2435 // NOEFF Writing 0 has no effect 2436 #define LRFDDBELL_ISET0_PBE10 0x00000400U 2437 #define LRFDDBELL_ISET0_PBE10_M 0x00000400U 2438 #define LRFDDBELL_ISET0_PBE10_S 10U 2439 #define LRFDDBELL_ISET0_PBE10_SET 0x00000400U 2440 #define LRFDDBELL_ISET0_PBE10_NOEFF 0x00000000U 2441 2442 // Field: [9] PBE9 2443 // 2444 // PBE9 event 2445 // ENUMs: 2446 // SET Set Interrupt 2447 // NOEFF Writing 0 has no effect 2448 #define LRFDDBELL_ISET0_PBE9 0x00000200U 2449 #define LRFDDBELL_ISET0_PBE9_M 0x00000200U 2450 #define LRFDDBELL_ISET0_PBE9_S 9U 2451 #define LRFDDBELL_ISET0_PBE9_SET 0x00000200U 2452 #define LRFDDBELL_ISET0_PBE9_NOEFF 0x00000000U 2453 2454 // Field: [8] PBE8 2455 // 2456 // PBE8 event 2457 // ENUMs: 2458 // SET Set Interrupt 2459 // NOEFF Writing 0 has no effect 2460 #define LRFDDBELL_ISET0_PBE8 0x00000100U 2461 #define LRFDDBELL_ISET0_PBE8_M 0x00000100U 2462 #define LRFDDBELL_ISET0_PBE8_S 8U 2463 #define LRFDDBELL_ISET0_PBE8_SET 0x00000100U 2464 #define LRFDDBELL_ISET0_PBE8_NOEFF 0x00000000U 2465 2466 // Field: [7] PBE7 2467 // 2468 // PBE7 event 2469 // ENUMs: 2470 // SET Set Interrupt 2471 // NOEFF Writing 0 has no effect 2472 #define LRFDDBELL_ISET0_PBE7 0x00000080U 2473 #define LRFDDBELL_ISET0_PBE7_M 0x00000080U 2474 #define LRFDDBELL_ISET0_PBE7_S 7U 2475 #define LRFDDBELL_ISET0_PBE7_SET 0x00000080U 2476 #define LRFDDBELL_ISET0_PBE7_NOEFF 0x00000000U 2477 2478 // Field: [6] PBE6 2479 // 2480 // PBE6 event 2481 // ENUMs: 2482 // SET Set Interrupt 2483 // NOEFF Writing 0 has no effect 2484 #define LRFDDBELL_ISET0_PBE6 0x00000040U 2485 #define LRFDDBELL_ISET0_PBE6_M 0x00000040U 2486 #define LRFDDBELL_ISET0_PBE6_S 6U 2487 #define LRFDDBELL_ISET0_PBE6_SET 0x00000040U 2488 #define LRFDDBELL_ISET0_PBE6_NOEFF 0x00000000U 2489 2490 // Field: [5] PBE5 2491 // 2492 // PBE5 event 2493 // ENUMs: 2494 // SET Set Interrupt 2495 // NOEFF Writing 0 has no effect 2496 #define LRFDDBELL_ISET0_PBE5 0x00000020U 2497 #define LRFDDBELL_ISET0_PBE5_M 0x00000020U 2498 #define LRFDDBELL_ISET0_PBE5_S 5U 2499 #define LRFDDBELL_ISET0_PBE5_SET 0x00000020U 2500 #define LRFDDBELL_ISET0_PBE5_NOEFF 0x00000000U 2501 2502 // Field: [4] PBE4 2503 // 2504 // PBE4 event 2505 // ENUMs: 2506 // SET Set Interrupt 2507 // NOEFF Writing 0 has no effect 2508 #define LRFDDBELL_ISET0_PBE4 0x00000010U 2509 #define LRFDDBELL_ISET0_PBE4_M 0x00000010U 2510 #define LRFDDBELL_ISET0_PBE4_S 4U 2511 #define LRFDDBELL_ISET0_PBE4_SET 0x00000010U 2512 #define LRFDDBELL_ISET0_PBE4_NOEFF 0x00000000U 2513 2514 // Field: [3] PBE3 2515 // 2516 // PBE3 event 2517 // ENUMs: 2518 // SET Set Interrupt 2519 // NOEFF Writing 0 has no effect 2520 #define LRFDDBELL_ISET0_PBE3 0x00000008U 2521 #define LRFDDBELL_ISET0_PBE3_M 0x00000008U 2522 #define LRFDDBELL_ISET0_PBE3_S 3U 2523 #define LRFDDBELL_ISET0_PBE3_SET 0x00000008U 2524 #define LRFDDBELL_ISET0_PBE3_NOEFF 0x00000000U 2525 2526 // Field: [2] PBE2 2527 // 2528 // PBE2 event 2529 // ENUMs: 2530 // SET Set Interrupt 2531 // NOEFF Writing 0 has no effect 2532 #define LRFDDBELL_ISET0_PBE2 0x00000004U 2533 #define LRFDDBELL_ISET0_PBE2_M 0x00000004U 2534 #define LRFDDBELL_ISET0_PBE2_S 2U 2535 #define LRFDDBELL_ISET0_PBE2_SET 0x00000004U 2536 #define LRFDDBELL_ISET0_PBE2_NOEFF 0x00000000U 2537 2538 // Field: [1] PBE1 2539 // 2540 // PBE1 event 2541 // ENUMs: 2542 // SET Set Interrupt 2543 // NOEFF Writing 0 has no effect 2544 #define LRFDDBELL_ISET0_PBE1 0x00000002U 2545 #define LRFDDBELL_ISET0_PBE1_M 0x00000002U 2546 #define LRFDDBELL_ISET0_PBE1_S 1U 2547 #define LRFDDBELL_ISET0_PBE1_SET 0x00000002U 2548 #define LRFDDBELL_ISET0_PBE1_NOEFF 0x00000000U 2549 2550 // Field: [0] PBE0 2551 // 2552 // PBE0 event 2553 // ENUMs: 2554 // SET Set Interrupt 2555 // NOEFF Writing 0 has no effect 2556 #define LRFDDBELL_ISET0_PBE0 0x00000001U 2557 #define LRFDDBELL_ISET0_PBE0_M 0x00000001U 2558 #define LRFDDBELL_ISET0_PBE0_S 0U 2559 #define LRFDDBELL_ISET0_PBE0_SET 0x00000001U 2560 #define LRFDDBELL_ISET0_PBE0_NOEFF 0x00000000U 2561 2562 //***************************************************************************** 2563 // 2564 // Register: LRFDDBELL_O_ICLR0 2565 // 2566 //***************************************************************************** 2567 // Field: [31] SYSTIM2 2568 // 2569 // SYSTIM2 event 2570 // ENUMs: 2571 // CLR Clear Interrupt 2572 // NOEFF Writing 0 has no effect 2573 #define LRFDDBELL_ICLR0_SYSTIM2 0x80000000U 2574 #define LRFDDBELL_ICLR0_SYSTIM2_M 0x80000000U 2575 #define LRFDDBELL_ICLR0_SYSTIM2_S 31U 2576 #define LRFDDBELL_ICLR0_SYSTIM2_CLR 0x80000000U 2577 #define LRFDDBELL_ICLR0_SYSTIM2_NOEFF 0x00000000U 2578 2579 // Field: [30] SYSTIM1 2580 // 2581 // SYSTIM1 event 2582 // ENUMs: 2583 // CLR Clear Interrupt 2584 // NOEFF Writing 0 has no effect 2585 #define LRFDDBELL_ICLR0_SYSTIM1 0x40000000U 2586 #define LRFDDBELL_ICLR0_SYSTIM1_M 0x40000000U 2587 #define LRFDDBELL_ICLR0_SYSTIM1_S 30U 2588 #define LRFDDBELL_ICLR0_SYSTIM1_CLR 0x40000000U 2589 #define LRFDDBELL_ICLR0_SYSTIM1_NOEFF 0x00000000U 2590 2591 // Field: [29] SYSTIM0 2592 // 2593 // SYSTIM0 event 2594 // ENUMs: 2595 // CLR Clear Interrupt 2596 // NOEFF Writing 0 has no effect 2597 #define LRFDDBELL_ICLR0_SYSTIM0 0x20000000U 2598 #define LRFDDBELL_ICLR0_SYSTIM0_M 0x20000000U 2599 #define LRFDDBELL_ICLR0_SYSTIM0_S 29U 2600 #define LRFDDBELL_ICLR0_SYSTIM0_CLR 0x20000000U 2601 #define LRFDDBELL_ICLR0_SYSTIM0_NOEFF 0x00000000U 2602 2603 // Field: [28] MDMDONE 2604 // 2605 // MDMDONE event 2606 // ENUMs: 2607 // CLR Clear Interrupt 2608 // NOEFF Writing 0 has no effect 2609 #define LRFDDBELL_ICLR0_MDMDONE 0x10000000U 2610 #define LRFDDBELL_ICLR0_MDMDONE_M 0x10000000U 2611 #define LRFDDBELL_ICLR0_MDMDONE_S 28U 2612 #define LRFDDBELL_ICLR0_MDMDONE_CLR 0x10000000U 2613 #define LRFDDBELL_ICLR0_MDMDONE_NOEFF 0x00000000U 2614 2615 // Field: [27] MDMIN 2616 // 2617 // MDMIN event 2618 // ENUMs: 2619 // CLR Clear Interrupt 2620 // NOEFF Writing 0 has no effect 2621 #define LRFDDBELL_ICLR0_MDMIN 0x08000000U 2622 #define LRFDDBELL_ICLR0_MDMIN_M 0x08000000U 2623 #define LRFDDBELL_ICLR0_MDMIN_S 27U 2624 #define LRFDDBELL_ICLR0_MDMIN_CLR 0x08000000U 2625 #define LRFDDBELL_ICLR0_MDMIN_NOEFF 0x00000000U 2626 2627 // Field: [26] MDMOUT 2628 // 2629 // MDMOUT event 2630 // ENUMs: 2631 // CLR Clear Interrupt 2632 // NOEFF Writing 0 has no effect 2633 #define LRFDDBELL_ICLR0_MDMOUT 0x04000000U 2634 #define LRFDDBELL_ICLR0_MDMOUT_M 0x04000000U 2635 #define LRFDDBELL_ICLR0_MDMOUT_S 26U 2636 #define LRFDDBELL_ICLR0_MDMOUT_CLR 0x04000000U 2637 #define LRFDDBELL_ICLR0_MDMOUT_NOEFF 0x00000000U 2638 2639 // Field: [25] MDMSOFT2 2640 // 2641 // MDMSOFT event 2642 // ENUMs: 2643 // CLR Clear Interrupt 2644 // NOEFF Writing 0 has no effect 2645 #define LRFDDBELL_ICLR0_MDMSOFT2 0x02000000U 2646 #define LRFDDBELL_ICLR0_MDMSOFT2_M 0x02000000U 2647 #define LRFDDBELL_ICLR0_MDMSOFT2_S 25U 2648 #define LRFDDBELL_ICLR0_MDMSOFT2_CLR 0x02000000U 2649 #define LRFDDBELL_ICLR0_MDMSOFT2_NOEFF 0x00000000U 2650 2651 // Field: [24] MDMSOFT1 2652 // 2653 // MDMSOFT1 event 2654 // ENUMs: 2655 // CLR Clear Interrupt 2656 // NOEFF Writing 0 has no effect 2657 #define LRFDDBELL_ICLR0_MDMSOFT1 0x01000000U 2658 #define LRFDDBELL_ICLR0_MDMSOFT1_M 0x01000000U 2659 #define LRFDDBELL_ICLR0_MDMSOFT1_S 24U 2660 #define LRFDDBELL_ICLR0_MDMSOFT1_CLR 0x01000000U 2661 #define LRFDDBELL_ICLR0_MDMSOFT1_NOEFF 0x00000000U 2662 2663 // Field: [23] MDMSOFT0 2664 // 2665 // MDMSOFT event 2666 // ENUMs: 2667 // CLR Clear Interrupt 2668 // NOEFF Writing 0 has no effect 2669 #define LRFDDBELL_ICLR0_MDMSOFT0 0x00800000U 2670 #define LRFDDBELL_ICLR0_MDMSOFT0_M 0x00800000U 2671 #define LRFDDBELL_ICLR0_MDMSOFT0_S 23U 2672 #define LRFDDBELL_ICLR0_MDMSOFT0_CLR 0x00800000U 2673 #define LRFDDBELL_ICLR0_MDMSOFT0_NOEFF 0x00000000U 2674 2675 // Field: [22] RFEDONE 2676 // 2677 // RFEDONE event 2678 // ENUMs: 2679 // CLR Clear Interrupt 2680 // NOEFF Writing 0 has no effect 2681 #define LRFDDBELL_ICLR0_RFEDONE 0x00400000U 2682 #define LRFDDBELL_ICLR0_RFEDONE_M 0x00400000U 2683 #define LRFDDBELL_ICLR0_RFEDONE_S 22U 2684 #define LRFDDBELL_ICLR0_RFEDONE_CLR 0x00400000U 2685 #define LRFDDBELL_ICLR0_RFEDONE_NOEFF 0x00000000U 2686 2687 // Field: [21] RFESOFT1 2688 // 2689 // RFESOFT1 event 2690 // ENUMs: 2691 // CLR Clear Interrupt 2692 // NOEFF Writing 0 has no effect 2693 #define LRFDDBELL_ICLR0_RFESOFT1 0x00200000U 2694 #define LRFDDBELL_ICLR0_RFESOFT1_M 0x00200000U 2695 #define LRFDDBELL_ICLR0_RFESOFT1_S 21U 2696 #define LRFDDBELL_ICLR0_RFESOFT1_CLR 0x00200000U 2697 #define LRFDDBELL_ICLR0_RFESOFT1_NOEFF 0x00000000U 2698 2699 // Field: [20] RFESOFT0 2700 // 2701 // RFESOFT0 event 2702 // ENUMs: 2703 // CLR Clear Interrupt 2704 // NOEFF Writing 0 has no effect 2705 #define LRFDDBELL_ICLR0_RFESOFT0 0x00100000U 2706 #define LRFDDBELL_ICLR0_RFESOFT0_M 0x00100000U 2707 #define LRFDDBELL_ICLR0_RFESOFT0_S 20U 2708 #define LRFDDBELL_ICLR0_RFESOFT0_CLR 0x00100000U 2709 #define LRFDDBELL_ICLR0_RFESOFT0_NOEFF 0x00000000U 2710 2711 // Field: [19] LOCK 2712 // 2713 // LOCK event 2714 // ENUMs: 2715 // CLR Clear Interrupt 2716 // NOEFF Writing 0 has no effect 2717 #define LRFDDBELL_ICLR0_LOCK 0x00080000U 2718 #define LRFDDBELL_ICLR0_LOCK_M 0x00080000U 2719 #define LRFDDBELL_ICLR0_LOCK_S 19U 2720 #define LRFDDBELL_ICLR0_LOCK_CLR 0x00080000U 2721 #define LRFDDBELL_ICLR0_LOCK_NOEFF 0x00000000U 2722 2723 // Field: [18] LOL 2724 // 2725 // LOSS_OF_LOCK event 2726 // ENUMs: 2727 // CLR Clear Interrupt 2728 // NOEFF Writing 0 has no effect 2729 #define LRFDDBELL_ICLR0_LOL 0x00040000U 2730 #define LRFDDBELL_ICLR0_LOL_M 0x00040000U 2731 #define LRFDDBELL_ICLR0_LOL_S 18U 2732 #define LRFDDBELL_ICLR0_LOL_CLR 0x00040000U 2733 #define LRFDDBELL_ICLR0_LOL_NOEFF 0x00000000U 2734 2735 // Field: [17] TXFIFO 2736 // 2737 // TXFIFO event 2738 // ENUMs: 2739 // CLR Clear Interrupt 2740 // NOEFF Writing 0 has no effect 2741 #define LRFDDBELL_ICLR0_TXFIFO 0x00020000U 2742 #define LRFDDBELL_ICLR0_TXFIFO_M 0x00020000U 2743 #define LRFDDBELL_ICLR0_TXFIFO_S 17U 2744 #define LRFDDBELL_ICLR0_TXFIFO_CLR 0x00020000U 2745 #define LRFDDBELL_ICLR0_TXFIFO_NOEFF 0x00000000U 2746 2747 // Field: [16] RXFIFO 2748 // 2749 // RXFIFO event 2750 // ENUMs: 2751 // CLR Clear Interrupt 2752 // NOEFF Writing 0 has no effect 2753 #define LRFDDBELL_ICLR0_RXFIFO 0x00010000U 2754 #define LRFDDBELL_ICLR0_RXFIFO_M 0x00010000U 2755 #define LRFDDBELL_ICLR0_RXFIFO_S 16U 2756 #define LRFDDBELL_ICLR0_RXFIFO_CLR 0x00010000U 2757 #define LRFDDBELL_ICLR0_RXFIFO_NOEFF 0x00000000U 2758 2759 // Field: [15] PBE15 2760 // 2761 // PBE15 event 2762 // ENUMs: 2763 // CLR Clear Interrupt 2764 // NOEFF Writing 0 has no effect 2765 #define LRFDDBELL_ICLR0_PBE15 0x00008000U 2766 #define LRFDDBELL_ICLR0_PBE15_M 0x00008000U 2767 #define LRFDDBELL_ICLR0_PBE15_S 15U 2768 #define LRFDDBELL_ICLR0_PBE15_CLR 0x00008000U 2769 #define LRFDDBELL_ICLR0_PBE15_NOEFF 0x00000000U 2770 2771 // Field: [14] PBE14 2772 // 2773 // PBE14 event 2774 // ENUMs: 2775 // CLR Clear Interrupt 2776 // NOEFF Writing 0 has no effect 2777 #define LRFDDBELL_ICLR0_PBE14 0x00004000U 2778 #define LRFDDBELL_ICLR0_PBE14_M 0x00004000U 2779 #define LRFDDBELL_ICLR0_PBE14_S 14U 2780 #define LRFDDBELL_ICLR0_PBE14_CLR 0x00004000U 2781 #define LRFDDBELL_ICLR0_PBE14_NOEFF 0x00000000U 2782 2783 // Field: [13] PBE13 2784 // 2785 // PBE13 event 2786 // ENUMs: 2787 // CLR Clear Interrupt 2788 // NOEFF Writing 0 has no effect 2789 #define LRFDDBELL_ICLR0_PBE13 0x00002000U 2790 #define LRFDDBELL_ICLR0_PBE13_M 0x00002000U 2791 #define LRFDDBELL_ICLR0_PBE13_S 13U 2792 #define LRFDDBELL_ICLR0_PBE13_CLR 0x00002000U 2793 #define LRFDDBELL_ICLR0_PBE13_NOEFF 0x00000000U 2794 2795 // Field: [12] PBE12 2796 // 2797 // PBE12 event 2798 // ENUMs: 2799 // CLR Clear Interrupt 2800 // NOEFF Writing 0 has no effect 2801 #define LRFDDBELL_ICLR0_PBE12 0x00001000U 2802 #define LRFDDBELL_ICLR0_PBE12_M 0x00001000U 2803 #define LRFDDBELL_ICLR0_PBE12_S 12U 2804 #define LRFDDBELL_ICLR0_PBE12_CLR 0x00001000U 2805 #define LRFDDBELL_ICLR0_PBE12_NOEFF 0x00000000U 2806 2807 // Field: [11] PBE11 2808 // 2809 // PBE11 event 2810 // ENUMs: 2811 // CLR Clear Interrupt 2812 // NOEFF Writing 0 has no effect 2813 #define LRFDDBELL_ICLR0_PBE11 0x00000800U 2814 #define LRFDDBELL_ICLR0_PBE11_M 0x00000800U 2815 #define LRFDDBELL_ICLR0_PBE11_S 11U 2816 #define LRFDDBELL_ICLR0_PBE11_CLR 0x00000800U 2817 #define LRFDDBELL_ICLR0_PBE11_NOEFF 0x00000000U 2818 2819 // Field: [10] PBE10 2820 // 2821 // PBE10 event 2822 // ENUMs: 2823 // CLR Clear Interrupt 2824 // NOEFF Writing 0 has no effect 2825 #define LRFDDBELL_ICLR0_PBE10 0x00000400U 2826 #define LRFDDBELL_ICLR0_PBE10_M 0x00000400U 2827 #define LRFDDBELL_ICLR0_PBE10_S 10U 2828 #define LRFDDBELL_ICLR0_PBE10_CLR 0x00000400U 2829 #define LRFDDBELL_ICLR0_PBE10_NOEFF 0x00000000U 2830 2831 // Field: [9] PBE9 2832 // 2833 // PBE9 event 2834 // ENUMs: 2835 // CLR Clear Interrupt 2836 // NOEFF Writing 0 has no effect 2837 #define LRFDDBELL_ICLR0_PBE9 0x00000200U 2838 #define LRFDDBELL_ICLR0_PBE9_M 0x00000200U 2839 #define LRFDDBELL_ICLR0_PBE9_S 9U 2840 #define LRFDDBELL_ICLR0_PBE9_CLR 0x00000200U 2841 #define LRFDDBELL_ICLR0_PBE9_NOEFF 0x00000000U 2842 2843 // Field: [8] PBE8 2844 // 2845 // PBE8 event 2846 // ENUMs: 2847 // CLR Clear Interrupt 2848 // NOEFF Writing 0 has no effect 2849 #define LRFDDBELL_ICLR0_PBE8 0x00000100U 2850 #define LRFDDBELL_ICLR0_PBE8_M 0x00000100U 2851 #define LRFDDBELL_ICLR0_PBE8_S 8U 2852 #define LRFDDBELL_ICLR0_PBE8_CLR 0x00000100U 2853 #define LRFDDBELL_ICLR0_PBE8_NOEFF 0x00000000U 2854 2855 // Field: [7] PBE7 2856 // 2857 // PBE7 event 2858 // ENUMs: 2859 // CLR Clear Interrupt 2860 // NOEFF Writing 0 has no effect 2861 #define LRFDDBELL_ICLR0_PBE7 0x00000080U 2862 #define LRFDDBELL_ICLR0_PBE7_M 0x00000080U 2863 #define LRFDDBELL_ICLR0_PBE7_S 7U 2864 #define LRFDDBELL_ICLR0_PBE7_CLR 0x00000080U 2865 #define LRFDDBELL_ICLR0_PBE7_NOEFF 0x00000000U 2866 2867 // Field: [6] PBE6 2868 // 2869 // PBE6 event 2870 // ENUMs: 2871 // CLR Clear Interrupt 2872 // NOEFF Writing 0 has no effect 2873 #define LRFDDBELL_ICLR0_PBE6 0x00000040U 2874 #define LRFDDBELL_ICLR0_PBE6_M 0x00000040U 2875 #define LRFDDBELL_ICLR0_PBE6_S 6U 2876 #define LRFDDBELL_ICLR0_PBE6_CLR 0x00000040U 2877 #define LRFDDBELL_ICLR0_PBE6_NOEFF 0x00000000U 2878 2879 // Field: [5] PBE5 2880 // 2881 // PBE5 event 2882 // ENUMs: 2883 // CLR Clear Interrupt 2884 // NOEFF Writing 0 has no effect 2885 #define LRFDDBELL_ICLR0_PBE5 0x00000020U 2886 #define LRFDDBELL_ICLR0_PBE5_M 0x00000020U 2887 #define LRFDDBELL_ICLR0_PBE5_S 5U 2888 #define LRFDDBELL_ICLR0_PBE5_CLR 0x00000020U 2889 #define LRFDDBELL_ICLR0_PBE5_NOEFF 0x00000000U 2890 2891 // Field: [4] PBE4 2892 // 2893 // PBE4 event 2894 // ENUMs: 2895 // CLR Clear Interrupt 2896 // NOEFF Writing 0 has no effect 2897 #define LRFDDBELL_ICLR0_PBE4 0x00000010U 2898 #define LRFDDBELL_ICLR0_PBE4_M 0x00000010U 2899 #define LRFDDBELL_ICLR0_PBE4_S 4U 2900 #define LRFDDBELL_ICLR0_PBE4_CLR 0x00000010U 2901 #define LRFDDBELL_ICLR0_PBE4_NOEFF 0x00000000U 2902 2903 // Field: [3] PBE3 2904 // 2905 // PBE3 event 2906 // ENUMs: 2907 // CLR Clear Interrupt 2908 // NOEFF Writing 0 has no effect 2909 #define LRFDDBELL_ICLR0_PBE3 0x00000008U 2910 #define LRFDDBELL_ICLR0_PBE3_M 0x00000008U 2911 #define LRFDDBELL_ICLR0_PBE3_S 3U 2912 #define LRFDDBELL_ICLR0_PBE3_CLR 0x00000008U 2913 #define LRFDDBELL_ICLR0_PBE3_NOEFF 0x00000000U 2914 2915 // Field: [2] PBE2 2916 // 2917 // PBE2 event 2918 // ENUMs: 2919 // CLR Clear Interrupt 2920 // NOEFF Writing 0 has no effect 2921 #define LRFDDBELL_ICLR0_PBE2 0x00000004U 2922 #define LRFDDBELL_ICLR0_PBE2_M 0x00000004U 2923 #define LRFDDBELL_ICLR0_PBE2_S 2U 2924 #define LRFDDBELL_ICLR0_PBE2_CLR 0x00000004U 2925 #define LRFDDBELL_ICLR0_PBE2_NOEFF 0x00000000U 2926 2927 // Field: [1] PBE1 2928 // 2929 // PBE1 event 2930 // ENUMs: 2931 // CLR Clear Interrupt 2932 // NOEFF Writing 0 has no effect 2933 #define LRFDDBELL_ICLR0_PBE1 0x00000002U 2934 #define LRFDDBELL_ICLR0_PBE1_M 0x00000002U 2935 #define LRFDDBELL_ICLR0_PBE1_S 1U 2936 #define LRFDDBELL_ICLR0_PBE1_CLR 0x00000002U 2937 #define LRFDDBELL_ICLR0_PBE1_NOEFF 0x00000000U 2938 2939 // Field: [0] PBE0 2940 // 2941 // PBE0 event 2942 // ENUMs: 2943 // CLR Clear Interrupt 2944 // NOEFF Writing 0 has no effect 2945 #define LRFDDBELL_ICLR0_PBE0 0x00000001U 2946 #define LRFDDBELL_ICLR0_PBE0_M 0x00000001U 2947 #define LRFDDBELL_ICLR0_PBE0_S 0U 2948 #define LRFDDBELL_ICLR0_PBE0_CLR 0x00000001U 2949 #define LRFDDBELL_ICLR0_PBE0_NOEFF 0x00000000U 2950 2951 //***************************************************************************** 2952 // 2953 // Register: LRFDDBELL_O_IMASK1 2954 // 2955 //***************************************************************************** 2956 // Field: [30] SYSTIM2 2957 // 2958 // SYSTIM2 event 2959 // ENUMs: 2960 // EN Enable interrupt mask 2961 // DIS Disable interrupt mask 2962 #define LRFDDBELL_IMASK1_SYSTIM2 0x40000000U 2963 #define LRFDDBELL_IMASK1_SYSTIM2_M 0x40000000U 2964 #define LRFDDBELL_IMASK1_SYSTIM2_S 30U 2965 #define LRFDDBELL_IMASK1_SYSTIM2_EN 0x40000000U 2966 #define LRFDDBELL_IMASK1_SYSTIM2_DIS 0x00000000U 2967 2968 // Field: [29] SYSTIM1 2969 // 2970 // SYSTIM1 event 2971 // ENUMs: 2972 // EN Enable interrupt mask 2973 // DIS Disable interrupt mask 2974 #define LRFDDBELL_IMASK1_SYSTIM1 0x20000000U 2975 #define LRFDDBELL_IMASK1_SYSTIM1_M 0x20000000U 2976 #define LRFDDBELL_IMASK1_SYSTIM1_S 29U 2977 #define LRFDDBELL_IMASK1_SYSTIM1_EN 0x20000000U 2978 #define LRFDDBELL_IMASK1_SYSTIM1_DIS 0x00000000U 2979 2980 // Field: [28] SYSTIM0 2981 // 2982 // SYSTIM0 event 2983 // ENUMs: 2984 // EN Enable interrupt mask 2985 // DIS Disable interrupt mask 2986 #define LRFDDBELL_IMASK1_SYSTIM0 0x10000000U 2987 #define LRFDDBELL_IMASK1_SYSTIM0_M 0x10000000U 2988 #define LRFDDBELL_IMASK1_SYSTIM0_S 28U 2989 #define LRFDDBELL_IMASK1_SYSTIM0_EN 0x10000000U 2990 #define LRFDDBELL_IMASK1_SYSTIM0_DIS 0x00000000U 2991 2992 // Field: [27] MDMDONE 2993 // 2994 // MDMDONE event 2995 // ENUMs: 2996 // EN Enable interrupt mask 2997 // DIS Disable interrupt mask 2998 #define LRFDDBELL_IMASK1_MDMDONE 0x08000000U 2999 #define LRFDDBELL_IMASK1_MDMDONE_M 0x08000000U 3000 #define LRFDDBELL_IMASK1_MDMDONE_S 27U 3001 #define LRFDDBELL_IMASK1_MDMDONE_EN 0x08000000U 3002 #define LRFDDBELL_IMASK1_MDMDONE_DIS 0x00000000U 3003 3004 // Field: [26] MDMIN 3005 // 3006 // MDMIN event 3007 // ENUMs: 3008 // EN Enable interrupt mask 3009 // DIS Disable interrupt mask 3010 #define LRFDDBELL_IMASK1_MDMIN 0x04000000U 3011 #define LRFDDBELL_IMASK1_MDMIN_M 0x04000000U 3012 #define LRFDDBELL_IMASK1_MDMIN_S 26U 3013 #define LRFDDBELL_IMASK1_MDMIN_EN 0x04000000U 3014 #define LRFDDBELL_IMASK1_MDMIN_DIS 0x00000000U 3015 3016 // Field: [25] MDMOUT 3017 // 3018 // MDMOUT event 3019 // ENUMs: 3020 // EN Enable interrupt mask 3021 // DIS Disable interrupt mask 3022 #define LRFDDBELL_IMASK1_MDMOUT 0x02000000U 3023 #define LRFDDBELL_IMASK1_MDMOUT_M 0x02000000U 3024 #define LRFDDBELL_IMASK1_MDMOUT_S 25U 3025 #define LRFDDBELL_IMASK1_MDMOUT_EN 0x02000000U 3026 #define LRFDDBELL_IMASK1_MDMOUT_DIS 0x00000000U 3027 3028 // Field: [24] MDMSOFT2 3029 // 3030 // MDMSOFT2 event 3031 // ENUMs: 3032 // EN Enable interrupt mask 3033 // DIS Disable interrupt mask 3034 #define LRFDDBELL_IMASK1_MDMSOFT2 0x01000000U 3035 #define LRFDDBELL_IMASK1_MDMSOFT2_M 0x01000000U 3036 #define LRFDDBELL_IMASK1_MDMSOFT2_S 24U 3037 #define LRFDDBELL_IMASK1_MDMSOFT2_EN 0x01000000U 3038 #define LRFDDBELL_IMASK1_MDMSOFT2_DIS 0x00000000U 3039 3040 // Field: [23] MDMSOFT1 3041 // 3042 // MDMSOFT2 event 3043 // ENUMs: 3044 // EN Enable interrupt mask 3045 // DIS Disable interrupt mask 3046 #define LRFDDBELL_IMASK1_MDMSOFT1 0x00800000U 3047 #define LRFDDBELL_IMASK1_MDMSOFT1_M 0x00800000U 3048 #define LRFDDBELL_IMASK1_MDMSOFT1_S 23U 3049 #define LRFDDBELL_IMASK1_MDMSOFT1_EN 0x00800000U 3050 #define LRFDDBELL_IMASK1_MDMSOFT1_DIS 0x00000000U 3051 3052 // Field: [22] MDMSOFT0 3053 // 3054 // MDMSOFT2 event 3055 // ENUMs: 3056 // EN Enable interrupt mask 3057 // DIS Disable interrupt mask 3058 #define LRFDDBELL_IMASK1_MDMSOFT0 0x00400000U 3059 #define LRFDDBELL_IMASK1_MDMSOFT0_M 0x00400000U 3060 #define LRFDDBELL_IMASK1_MDMSOFT0_S 22U 3061 #define LRFDDBELL_IMASK1_MDMSOFT0_EN 0x00400000U 3062 #define LRFDDBELL_IMASK1_MDMSOFT0_DIS 0x00000000U 3063 3064 // Field: [21] RFEDONE 3065 // 3066 // RFEDONE event 3067 // ENUMs: 3068 // EN Enable interrupt mask 3069 // DIS Disable interrupt mask 3070 #define LRFDDBELL_IMASK1_RFEDONE 0x00200000U 3071 #define LRFDDBELL_IMASK1_RFEDONE_M 0x00200000U 3072 #define LRFDDBELL_IMASK1_RFEDONE_S 21U 3073 #define LRFDDBELL_IMASK1_RFEDONE_EN 0x00200000U 3074 #define LRFDDBELL_IMASK1_RFEDONE_DIS 0x00000000U 3075 3076 // Field: [20] RFESOFT1 3077 // 3078 // RFESOFT1 event 3079 // ENUMs: 3080 // EN Enable interrupt mask 3081 // DIS Disable interrupt mask 3082 #define LRFDDBELL_IMASK1_RFESOFT1 0x00100000U 3083 #define LRFDDBELL_IMASK1_RFESOFT1_M 0x00100000U 3084 #define LRFDDBELL_IMASK1_RFESOFT1_S 20U 3085 #define LRFDDBELL_IMASK1_RFESOFT1_EN 0x00100000U 3086 #define LRFDDBELL_IMASK1_RFESOFT1_DIS 0x00000000U 3087 3088 // Field: [19] RFESOFT0 3089 // 3090 // RFESOFT0 event 3091 // ENUMs: 3092 // EN Enable interrupt mask 3093 // DIS Disable interrupt mask 3094 #define LRFDDBELL_IMASK1_RFESOFT0 0x00080000U 3095 #define LRFDDBELL_IMASK1_RFESOFT0_M 0x00080000U 3096 #define LRFDDBELL_IMASK1_RFESOFT0_S 19U 3097 #define LRFDDBELL_IMASK1_RFESOFT0_EN 0x00080000U 3098 #define LRFDDBELL_IMASK1_RFESOFT0_DIS 0x00000000U 3099 3100 // Field: [18] LOCK 3101 // 3102 // LOCK event 3103 // ENUMs: 3104 // EN Enable interrupt mask 3105 // DIS Disable interrupt mask 3106 #define LRFDDBELL_IMASK1_LOCK 0x00040000U 3107 #define LRFDDBELL_IMASK1_LOCK_M 0x00040000U 3108 #define LRFDDBELL_IMASK1_LOCK_S 18U 3109 #define LRFDDBELL_IMASK1_LOCK_EN 0x00040000U 3110 #define LRFDDBELL_IMASK1_LOCK_DIS 0x00000000U 3111 3112 // Field: [17] LOL 3113 // 3114 // LOSS_OF_LOCK event 3115 // ENUMs: 3116 // EN Enable interrupt mask 3117 // DIS Disable interrupt mask 3118 #define LRFDDBELL_IMASK1_LOL 0x00020000U 3119 #define LRFDDBELL_IMASK1_LOL_M 0x00020000U 3120 #define LRFDDBELL_IMASK1_LOL_S 17U 3121 #define LRFDDBELL_IMASK1_LOL_EN 0x00020000U 3122 #define LRFDDBELL_IMASK1_LOL_DIS 0x00000000U 3123 3124 // Field: [16] TXFIFO 3125 // 3126 // TXFIFO event 3127 // ENUMs: 3128 // EN Enable interrupt mask 3129 // DIS Disable interrupt mask 3130 #define LRFDDBELL_IMASK1_TXFIFO 0x00010000U 3131 #define LRFDDBELL_IMASK1_TXFIFO_M 0x00010000U 3132 #define LRFDDBELL_IMASK1_TXFIFO_S 16U 3133 #define LRFDDBELL_IMASK1_TXFIFO_EN 0x00010000U 3134 #define LRFDDBELL_IMASK1_TXFIFO_DIS 0x00000000U 3135 3136 // Field: [15] RXFIFO 3137 // 3138 // RXFIFO event 3139 // ENUMs: 3140 // EN Enable interrupt mask 3141 // DIS Disable interrupt mask 3142 #define LRFDDBELL_IMASK1_RXFIFO 0x00008000U 3143 #define LRFDDBELL_IMASK1_RXFIFO_M 0x00008000U 3144 #define LRFDDBELL_IMASK1_RXFIFO_S 15U 3145 #define LRFDDBELL_IMASK1_RXFIFO_EN 0x00008000U 3146 #define LRFDDBELL_IMASK1_RXFIFO_DIS 0x00000000U 3147 3148 // Field: [14] PBE15 3149 // 3150 // PBE15 event 3151 // ENUMs: 3152 // EN Enable interrupt mask 3153 // DIS Disable interrupt mask 3154 #define LRFDDBELL_IMASK1_PBE15 0x00004000U 3155 #define LRFDDBELL_IMASK1_PBE15_M 0x00004000U 3156 #define LRFDDBELL_IMASK1_PBE15_S 14U 3157 #define LRFDDBELL_IMASK1_PBE15_EN 0x00004000U 3158 #define LRFDDBELL_IMASK1_PBE15_DIS 0x00000000U 3159 3160 // Field: [13] PBE14 3161 // 3162 // PBE14 event 3163 // ENUMs: 3164 // EN Enable interrupt mask 3165 // DIS Disable interrupt mask 3166 #define LRFDDBELL_IMASK1_PBE14 0x00002000U 3167 #define LRFDDBELL_IMASK1_PBE14_M 0x00002000U 3168 #define LRFDDBELL_IMASK1_PBE14_S 13U 3169 #define LRFDDBELL_IMASK1_PBE14_EN 0x00002000U 3170 #define LRFDDBELL_IMASK1_PBE14_DIS 0x00000000U 3171 3172 // Field: [12] PBE13 3173 // 3174 // PBE13 event 3175 // ENUMs: 3176 // EN Enable interrupt mask 3177 // DIS Disable interrupt mask 3178 #define LRFDDBELL_IMASK1_PBE13 0x00001000U 3179 #define LRFDDBELL_IMASK1_PBE13_M 0x00001000U 3180 #define LRFDDBELL_IMASK1_PBE13_S 12U 3181 #define LRFDDBELL_IMASK1_PBE13_EN 0x00001000U 3182 #define LRFDDBELL_IMASK1_PBE13_DIS 0x00000000U 3183 3184 // Field: [11] PBE12 3185 // 3186 // PBE12 event 3187 // ENUMs: 3188 // EN Enable interrupt mask 3189 // DIS Disable interrupt mask 3190 #define LRFDDBELL_IMASK1_PBE12 0x00000800U 3191 #define LRFDDBELL_IMASK1_PBE12_M 0x00000800U 3192 #define LRFDDBELL_IMASK1_PBE12_S 11U 3193 #define LRFDDBELL_IMASK1_PBE12_EN 0x00000800U 3194 #define LRFDDBELL_IMASK1_PBE12_DIS 0x00000000U 3195 3196 // Field: [10] PBE11 3197 // 3198 // PBE11 event 3199 // ENUMs: 3200 // EN Enable interrupt mask 3201 // DIS Disable interrupt mask 3202 #define LRFDDBELL_IMASK1_PBE11 0x00000400U 3203 #define LRFDDBELL_IMASK1_PBE11_M 0x00000400U 3204 #define LRFDDBELL_IMASK1_PBE11_S 10U 3205 #define LRFDDBELL_IMASK1_PBE11_EN 0x00000400U 3206 #define LRFDDBELL_IMASK1_PBE11_DIS 0x00000000U 3207 3208 // Field: [9] PBE10 3209 // 3210 // PBE10 event 3211 // ENUMs: 3212 // EN Enable interrupt mask 3213 // DIS Disable interrupt mask 3214 #define LRFDDBELL_IMASK1_PBE10 0x00000200U 3215 #define LRFDDBELL_IMASK1_PBE10_M 0x00000200U 3216 #define LRFDDBELL_IMASK1_PBE10_S 9U 3217 #define LRFDDBELL_IMASK1_PBE10_EN 0x00000200U 3218 #define LRFDDBELL_IMASK1_PBE10_DIS 0x00000000U 3219 3220 // Field: [8] PBE8 3221 // 3222 // PBE8 event 3223 // ENUMs: 3224 // EN Enable interrupt mask 3225 // DIS Disable interrupt mask 3226 #define LRFDDBELL_IMASK1_PBE8 0x00000100U 3227 #define LRFDDBELL_IMASK1_PBE8_M 0x00000100U 3228 #define LRFDDBELL_IMASK1_PBE8_S 8U 3229 #define LRFDDBELL_IMASK1_PBE8_EN 0x00000100U 3230 #define LRFDDBELL_IMASK1_PBE8_DIS 0x00000000U 3231 3232 // Field: [7] PBE7 3233 // 3234 // PBE7 event 3235 // ENUMs: 3236 // EN Enable interrupt mask 3237 // DIS Disable interrupt mask 3238 #define LRFDDBELL_IMASK1_PBE7 0x00000080U 3239 #define LRFDDBELL_IMASK1_PBE7_M 0x00000080U 3240 #define LRFDDBELL_IMASK1_PBE7_S 7U 3241 #define LRFDDBELL_IMASK1_PBE7_EN 0x00000080U 3242 #define LRFDDBELL_IMASK1_PBE7_DIS 0x00000000U 3243 3244 // Field: [6] PBE6 3245 // 3246 // PBE6 event 3247 // ENUMs: 3248 // EN Enable interrupt mask 3249 // DIS Disable interrupt mask 3250 #define LRFDDBELL_IMASK1_PBE6 0x00000040U 3251 #define LRFDDBELL_IMASK1_PBE6_M 0x00000040U 3252 #define LRFDDBELL_IMASK1_PBE6_S 6U 3253 #define LRFDDBELL_IMASK1_PBE6_EN 0x00000040U 3254 #define LRFDDBELL_IMASK1_PBE6_DIS 0x00000000U 3255 3256 // Field: [5] PBE5 3257 // 3258 // PBE5 event 3259 // ENUMs: 3260 // EN Enable interrupt mask 3261 // DIS Disable interrupt mask 3262 #define LRFDDBELL_IMASK1_PBE5 0x00000020U 3263 #define LRFDDBELL_IMASK1_PBE5_M 0x00000020U 3264 #define LRFDDBELL_IMASK1_PBE5_S 5U 3265 #define LRFDDBELL_IMASK1_PBE5_EN 0x00000020U 3266 #define LRFDDBELL_IMASK1_PBE5_DIS 0x00000000U 3267 3268 // Field: [4] PBE4 3269 // 3270 // PBE4 event 3271 // ENUMs: 3272 // EN Enable interrupt mask 3273 // DIS Disable interrupt mask 3274 #define LRFDDBELL_IMASK1_PBE4 0x00000010U 3275 #define LRFDDBELL_IMASK1_PBE4_M 0x00000010U 3276 #define LRFDDBELL_IMASK1_PBE4_S 4U 3277 #define LRFDDBELL_IMASK1_PBE4_EN 0x00000010U 3278 #define LRFDDBELL_IMASK1_PBE4_DIS 0x00000000U 3279 3280 // Field: [3] PBE3 3281 // 3282 // PBE3 event 3283 // ENUMs: 3284 // EN Enable interrupt mask 3285 // DIS Disable interrupt mask 3286 #define LRFDDBELL_IMASK1_PBE3 0x00000008U 3287 #define LRFDDBELL_IMASK1_PBE3_M 0x00000008U 3288 #define LRFDDBELL_IMASK1_PBE3_S 3U 3289 #define LRFDDBELL_IMASK1_PBE3_EN 0x00000008U 3290 #define LRFDDBELL_IMASK1_PBE3_DIS 0x00000000U 3291 3292 // Field: [2] PBE2 3293 // 3294 // PBE2 event 3295 // ENUMs: 3296 // EN Enable interrupt mask 3297 // DIS Disable interrupt mask 3298 #define LRFDDBELL_IMASK1_PBE2 0x00000004U 3299 #define LRFDDBELL_IMASK1_PBE2_M 0x00000004U 3300 #define LRFDDBELL_IMASK1_PBE2_S 2U 3301 #define LRFDDBELL_IMASK1_PBE2_EN 0x00000004U 3302 #define LRFDDBELL_IMASK1_PBE2_DIS 0x00000000U 3303 3304 // Field: [1] PBE1 3305 // 3306 // PBE1 event 3307 // ENUMs: 3308 // EN Enable interrupt mask 3309 // DIS Disable interrupt mask 3310 #define LRFDDBELL_IMASK1_PBE1 0x00000002U 3311 #define LRFDDBELL_IMASK1_PBE1_M 0x00000002U 3312 #define LRFDDBELL_IMASK1_PBE1_S 1U 3313 #define LRFDDBELL_IMASK1_PBE1_EN 0x00000002U 3314 #define LRFDDBELL_IMASK1_PBE1_DIS 0x00000000U 3315 3316 // Field: [0] PBE0 3317 // 3318 // PBE0 event 3319 // ENUMs: 3320 // EN Enable interrupt mask 3321 // DIS Disable interrupt mask 3322 #define LRFDDBELL_IMASK1_PBE0 0x00000001U 3323 #define LRFDDBELL_IMASK1_PBE0_M 0x00000001U 3324 #define LRFDDBELL_IMASK1_PBE0_S 0U 3325 #define LRFDDBELL_IMASK1_PBE0_EN 0x00000001U 3326 #define LRFDDBELL_IMASK1_PBE0_DIS 0x00000000U 3327 3328 //***************************************************************************** 3329 // 3330 // Register: LRFDDBELL_O_RIS1 3331 // 3332 //***************************************************************************** 3333 // Field: [31] SYSTIM2 3334 // 3335 // SYSTIM2 event 3336 // ENUMs: 3337 // SET Interrupt occurred 3338 // CLR Interrupt did not occur 3339 #define LRFDDBELL_RIS1_SYSTIM2 0x80000000U 3340 #define LRFDDBELL_RIS1_SYSTIM2_M 0x80000000U 3341 #define LRFDDBELL_RIS1_SYSTIM2_S 31U 3342 #define LRFDDBELL_RIS1_SYSTIM2_SET 0x80000000U 3343 #define LRFDDBELL_RIS1_SYSTIM2_CLR 0x00000000U 3344 3345 // Field: [30] SYSTIM1 3346 // 3347 // SYSTIM1 event 3348 // ENUMs: 3349 // SET Interrupt occurred 3350 // CLR Interrupt did not occur 3351 #define LRFDDBELL_RIS1_SYSTIM1 0x40000000U 3352 #define LRFDDBELL_RIS1_SYSTIM1_M 0x40000000U 3353 #define LRFDDBELL_RIS1_SYSTIM1_S 30U 3354 #define LRFDDBELL_RIS1_SYSTIM1_SET 0x40000000U 3355 #define LRFDDBELL_RIS1_SYSTIM1_CLR 0x00000000U 3356 3357 // Field: [29] SYSTIM0 3358 // 3359 // SYSTIM0 event 3360 // ENUMs: 3361 // SET Interrupt occurred 3362 // CLR Interrupt did not occur 3363 #define LRFDDBELL_RIS1_SYSTIM0 0x20000000U 3364 #define LRFDDBELL_RIS1_SYSTIM0_M 0x20000000U 3365 #define LRFDDBELL_RIS1_SYSTIM0_S 29U 3366 #define LRFDDBELL_RIS1_SYSTIM0_SET 0x20000000U 3367 #define LRFDDBELL_RIS1_SYSTIM0_CLR 0x00000000U 3368 3369 // Field: [28] MDMDONE 3370 // 3371 // MDMDONE event 3372 // ENUMs: 3373 // SET Interrupt occurred 3374 // CLR Interrupt did not occur 3375 #define LRFDDBELL_RIS1_MDMDONE 0x10000000U 3376 #define LRFDDBELL_RIS1_MDMDONE_M 0x10000000U 3377 #define LRFDDBELL_RIS1_MDMDONE_S 28U 3378 #define LRFDDBELL_RIS1_MDMDONE_SET 0x10000000U 3379 #define LRFDDBELL_RIS1_MDMDONE_CLR 0x00000000U 3380 3381 // Field: [27] MDMIN 3382 // 3383 // MDMIN event 3384 // ENUMs: 3385 // SET Interrupt occurred 3386 // CLR Interrupt did not occur 3387 #define LRFDDBELL_RIS1_MDMIN 0x08000000U 3388 #define LRFDDBELL_RIS1_MDMIN_M 0x08000000U 3389 #define LRFDDBELL_RIS1_MDMIN_S 27U 3390 #define LRFDDBELL_RIS1_MDMIN_SET 0x08000000U 3391 #define LRFDDBELL_RIS1_MDMIN_CLR 0x00000000U 3392 3393 // Field: [26] MDMOUT 3394 // 3395 // MDMOUT event 3396 // ENUMs: 3397 // SET Interrupt occurred 3398 // CLR Interrupt did not occur 3399 #define LRFDDBELL_RIS1_MDMOUT 0x04000000U 3400 #define LRFDDBELL_RIS1_MDMOUT_M 0x04000000U 3401 #define LRFDDBELL_RIS1_MDMOUT_S 26U 3402 #define LRFDDBELL_RIS1_MDMOUT_SET 0x04000000U 3403 #define LRFDDBELL_RIS1_MDMOUT_CLR 0x00000000U 3404 3405 // Field: [25] MDMSOFT2 3406 // 3407 // MDMSOFT event 3408 // ENUMs: 3409 // SET Interrupt occurred 3410 // CLR Interrupt did not occur 3411 #define LRFDDBELL_RIS1_MDMSOFT2 0x02000000U 3412 #define LRFDDBELL_RIS1_MDMSOFT2_M 0x02000000U 3413 #define LRFDDBELL_RIS1_MDMSOFT2_S 25U 3414 #define LRFDDBELL_RIS1_MDMSOFT2_SET 0x02000000U 3415 #define LRFDDBELL_RIS1_MDMSOFT2_CLR 0x00000000U 3416 3417 // Field: [24] MDMSOFT1 3418 // 3419 // MDMSOFT1 event 3420 // ENUMs: 3421 // SET Interrupt occurred 3422 // CLR Interrupt did not occur 3423 #define LRFDDBELL_RIS1_MDMSOFT1 0x01000000U 3424 #define LRFDDBELL_RIS1_MDMSOFT1_M 0x01000000U 3425 #define LRFDDBELL_RIS1_MDMSOFT1_S 24U 3426 #define LRFDDBELL_RIS1_MDMSOFT1_SET 0x01000000U 3427 #define LRFDDBELL_RIS1_MDMSOFT1_CLR 0x00000000U 3428 3429 // Field: [23] MDMSOFT0 3430 // 3431 // MDMSOFT event 3432 // ENUMs: 3433 // SET Interrupt occurred 3434 // CLR Interrupt did not occur 3435 #define LRFDDBELL_RIS1_MDMSOFT0 0x00800000U 3436 #define LRFDDBELL_RIS1_MDMSOFT0_M 0x00800000U 3437 #define LRFDDBELL_RIS1_MDMSOFT0_S 23U 3438 #define LRFDDBELL_RIS1_MDMSOFT0_SET 0x00800000U 3439 #define LRFDDBELL_RIS1_MDMSOFT0_CLR 0x00000000U 3440 3441 // Field: [22] RFEDONE 3442 // 3443 // RFEDONE event 3444 // ENUMs: 3445 // SET Interrupt occurred 3446 // CLR Interrupt did not occur 3447 #define LRFDDBELL_RIS1_RFEDONE 0x00400000U 3448 #define LRFDDBELL_RIS1_RFEDONE_M 0x00400000U 3449 #define LRFDDBELL_RIS1_RFEDONE_S 22U 3450 #define LRFDDBELL_RIS1_RFEDONE_SET 0x00400000U 3451 #define LRFDDBELL_RIS1_RFEDONE_CLR 0x00000000U 3452 3453 // Field: [21] RFESOFT1 3454 // 3455 // RFESOFT1 event 3456 // ENUMs: 3457 // SET Interrupt occurred 3458 // CLR Interrupt did not occur 3459 #define LRFDDBELL_RIS1_RFESOFT1 0x00200000U 3460 #define LRFDDBELL_RIS1_RFESOFT1_M 0x00200000U 3461 #define LRFDDBELL_RIS1_RFESOFT1_S 21U 3462 #define LRFDDBELL_RIS1_RFESOFT1_SET 0x00200000U 3463 #define LRFDDBELL_RIS1_RFESOFT1_CLR 0x00000000U 3464 3465 // Field: [20] RFESOFT0 3466 // 3467 // RFESOFT0 event 3468 // ENUMs: 3469 // SET Interrupt occurred 3470 // CLR Interrupt did not occur 3471 #define LRFDDBELL_RIS1_RFESOFT0 0x00100000U 3472 #define LRFDDBELL_RIS1_RFESOFT0_M 0x00100000U 3473 #define LRFDDBELL_RIS1_RFESOFT0_S 20U 3474 #define LRFDDBELL_RIS1_RFESOFT0_SET 0x00100000U 3475 #define LRFDDBELL_RIS1_RFESOFT0_CLR 0x00000000U 3476 3477 // Field: [19] LOCK 3478 // 3479 // LOCK event 3480 // ENUMs: 3481 // SET Interrupt occurred 3482 // CLR Interrupt did not occur 3483 #define LRFDDBELL_RIS1_LOCK 0x00080000U 3484 #define LRFDDBELL_RIS1_LOCK_M 0x00080000U 3485 #define LRFDDBELL_RIS1_LOCK_S 19U 3486 #define LRFDDBELL_RIS1_LOCK_SET 0x00080000U 3487 #define LRFDDBELL_RIS1_LOCK_CLR 0x00000000U 3488 3489 // Field: [18] LOL 3490 // 3491 // LOSS_OF_LOCK event 3492 // ENUMs: 3493 // SET Interrupt occurred 3494 // CLR Interrupt did not occur 3495 #define LRFDDBELL_RIS1_LOL 0x00040000U 3496 #define LRFDDBELL_RIS1_LOL_M 0x00040000U 3497 #define LRFDDBELL_RIS1_LOL_S 18U 3498 #define LRFDDBELL_RIS1_LOL_SET 0x00040000U 3499 #define LRFDDBELL_RIS1_LOL_CLR 0x00000000U 3500 3501 // Field: [17] TXFIFO 3502 // 3503 // TXFIFO event 3504 // ENUMs: 3505 // SET Interrupt occurred 3506 // CLR Interrupt did not occur 3507 #define LRFDDBELL_RIS1_TXFIFO 0x00020000U 3508 #define LRFDDBELL_RIS1_TXFIFO_M 0x00020000U 3509 #define LRFDDBELL_RIS1_TXFIFO_S 17U 3510 #define LRFDDBELL_RIS1_TXFIFO_SET 0x00020000U 3511 #define LRFDDBELL_RIS1_TXFIFO_CLR 0x00000000U 3512 3513 // Field: [16] RXFIFO 3514 // 3515 // RXFIFO event 3516 // ENUMs: 3517 // SET Interrupt occurred 3518 // CLR Interrupt did not occur 3519 #define LRFDDBELL_RIS1_RXFIFO 0x00010000U 3520 #define LRFDDBELL_RIS1_RXFIFO_M 0x00010000U 3521 #define LRFDDBELL_RIS1_RXFIFO_S 16U 3522 #define LRFDDBELL_RIS1_RXFIFO_SET 0x00010000U 3523 #define LRFDDBELL_RIS1_RXFIFO_CLR 0x00000000U 3524 3525 // Field: [15] PBE15 3526 // 3527 // PBE15 event 3528 // ENUMs: 3529 // SET Interrupt occurred 3530 // CLR Interrupt did not occur 3531 #define LRFDDBELL_RIS1_PBE15 0x00008000U 3532 #define LRFDDBELL_RIS1_PBE15_M 0x00008000U 3533 #define LRFDDBELL_RIS1_PBE15_S 15U 3534 #define LRFDDBELL_RIS1_PBE15_SET 0x00008000U 3535 #define LRFDDBELL_RIS1_PBE15_CLR 0x00000000U 3536 3537 // Field: [14] PBE14 3538 // 3539 // PBE14 event 3540 // ENUMs: 3541 // SET Interrupt occurred 3542 // CLR Interrupt did not occur 3543 #define LRFDDBELL_RIS1_PBE14 0x00004000U 3544 #define LRFDDBELL_RIS1_PBE14_M 0x00004000U 3545 #define LRFDDBELL_RIS1_PBE14_S 14U 3546 #define LRFDDBELL_RIS1_PBE14_SET 0x00004000U 3547 #define LRFDDBELL_RIS1_PBE14_CLR 0x00000000U 3548 3549 // Field: [13] PBE13 3550 // 3551 // PBE13 event 3552 // ENUMs: 3553 // SET Interrupt occurred 3554 // CLR Interrupt did not occur 3555 #define LRFDDBELL_RIS1_PBE13 0x00002000U 3556 #define LRFDDBELL_RIS1_PBE13_M 0x00002000U 3557 #define LRFDDBELL_RIS1_PBE13_S 13U 3558 #define LRFDDBELL_RIS1_PBE13_SET 0x00002000U 3559 #define LRFDDBELL_RIS1_PBE13_CLR 0x00000000U 3560 3561 // Field: [12] PBE12 3562 // 3563 // PBE12 event 3564 // ENUMs: 3565 // SET Interrupt occurred 3566 // CLR Interrupt did not occur 3567 #define LRFDDBELL_RIS1_PBE12 0x00001000U 3568 #define LRFDDBELL_RIS1_PBE12_M 0x00001000U 3569 #define LRFDDBELL_RIS1_PBE12_S 12U 3570 #define LRFDDBELL_RIS1_PBE12_SET 0x00001000U 3571 #define LRFDDBELL_RIS1_PBE12_CLR 0x00000000U 3572 3573 // Field: [11] PBE11 3574 // 3575 // PBE11 event 3576 // ENUMs: 3577 // SET Interrupt occurred 3578 // CLR Interrupt did not occur 3579 #define LRFDDBELL_RIS1_PBE11 0x00000800U 3580 #define LRFDDBELL_RIS1_PBE11_M 0x00000800U 3581 #define LRFDDBELL_RIS1_PBE11_S 11U 3582 #define LRFDDBELL_RIS1_PBE11_SET 0x00000800U 3583 #define LRFDDBELL_RIS1_PBE11_CLR 0x00000000U 3584 3585 // Field: [10] PBE10 3586 // 3587 // PBE10 event 3588 // ENUMs: 3589 // SET Interrupt occurred 3590 // CLR Interrupt did not occur 3591 #define LRFDDBELL_RIS1_PBE10 0x00000400U 3592 #define LRFDDBELL_RIS1_PBE10_M 0x00000400U 3593 #define LRFDDBELL_RIS1_PBE10_S 10U 3594 #define LRFDDBELL_RIS1_PBE10_SET 0x00000400U 3595 #define LRFDDBELL_RIS1_PBE10_CLR 0x00000000U 3596 3597 // Field: [9] PBE9 3598 // 3599 // PBE9 event 3600 // ENUMs: 3601 // SET Interrupt occurred 3602 // CLR Interrupt did not occur 3603 #define LRFDDBELL_RIS1_PBE9 0x00000200U 3604 #define LRFDDBELL_RIS1_PBE9_M 0x00000200U 3605 #define LRFDDBELL_RIS1_PBE9_S 9U 3606 #define LRFDDBELL_RIS1_PBE9_SET 0x00000200U 3607 #define LRFDDBELL_RIS1_PBE9_CLR 0x00000000U 3608 3609 // Field: [8] PBE8 3610 // 3611 // PBE8 event 3612 // ENUMs: 3613 // SET Interrupt occurred 3614 // CLR Interrupt did not occur 3615 #define LRFDDBELL_RIS1_PBE8 0x00000100U 3616 #define LRFDDBELL_RIS1_PBE8_M 0x00000100U 3617 #define LRFDDBELL_RIS1_PBE8_S 8U 3618 #define LRFDDBELL_RIS1_PBE8_SET 0x00000100U 3619 #define LRFDDBELL_RIS1_PBE8_CLR 0x00000000U 3620 3621 // Field: [7] PBE7 3622 // 3623 // PBE7 event 3624 // ENUMs: 3625 // SET Interrupt occurred 3626 // CLR Interrupt did not occur 3627 #define LRFDDBELL_RIS1_PBE7 0x00000080U 3628 #define LRFDDBELL_RIS1_PBE7_M 0x00000080U 3629 #define LRFDDBELL_RIS1_PBE7_S 7U 3630 #define LRFDDBELL_RIS1_PBE7_SET 0x00000080U 3631 #define LRFDDBELL_RIS1_PBE7_CLR 0x00000000U 3632 3633 // Field: [6] PBE6 3634 // 3635 // PBE6 event 3636 // ENUMs: 3637 // SET Interrupt occurred 3638 // CLR Interrupt did not occur 3639 #define LRFDDBELL_RIS1_PBE6 0x00000040U 3640 #define LRFDDBELL_RIS1_PBE6_M 0x00000040U 3641 #define LRFDDBELL_RIS1_PBE6_S 6U 3642 #define LRFDDBELL_RIS1_PBE6_SET 0x00000040U 3643 #define LRFDDBELL_RIS1_PBE6_CLR 0x00000000U 3644 3645 // Field: [5] PBE5 3646 // 3647 // PBE5 event 3648 // ENUMs: 3649 // SET Interrupt occurred 3650 // CLR Interrupt did not occur 3651 #define LRFDDBELL_RIS1_PBE5 0x00000020U 3652 #define LRFDDBELL_RIS1_PBE5_M 0x00000020U 3653 #define LRFDDBELL_RIS1_PBE5_S 5U 3654 #define LRFDDBELL_RIS1_PBE5_SET 0x00000020U 3655 #define LRFDDBELL_RIS1_PBE5_CLR 0x00000000U 3656 3657 // Field: [4] PBE4 3658 // 3659 // PBE4 event 3660 // ENUMs: 3661 // SET Interrupt occurred 3662 // CLR Interrupt did not occur 3663 #define LRFDDBELL_RIS1_PBE4 0x00000010U 3664 #define LRFDDBELL_RIS1_PBE4_M 0x00000010U 3665 #define LRFDDBELL_RIS1_PBE4_S 4U 3666 #define LRFDDBELL_RIS1_PBE4_SET 0x00000010U 3667 #define LRFDDBELL_RIS1_PBE4_CLR 0x00000000U 3668 3669 // Field: [3] PBE3 3670 // 3671 // PBE3 event 3672 // ENUMs: 3673 // SET Interrupt occurred 3674 // CLR Interrupt did not occur 3675 #define LRFDDBELL_RIS1_PBE3 0x00000008U 3676 #define LRFDDBELL_RIS1_PBE3_M 0x00000008U 3677 #define LRFDDBELL_RIS1_PBE3_S 3U 3678 #define LRFDDBELL_RIS1_PBE3_SET 0x00000008U 3679 #define LRFDDBELL_RIS1_PBE3_CLR 0x00000000U 3680 3681 // Field: [2] PBE2 3682 // 3683 // PBE2 event 3684 // ENUMs: 3685 // SET Interrupt occurred 3686 // CLR Interrupt did not occur 3687 #define LRFDDBELL_RIS1_PBE2 0x00000004U 3688 #define LRFDDBELL_RIS1_PBE2_M 0x00000004U 3689 #define LRFDDBELL_RIS1_PBE2_S 2U 3690 #define LRFDDBELL_RIS1_PBE2_SET 0x00000004U 3691 #define LRFDDBELL_RIS1_PBE2_CLR 0x00000000U 3692 3693 // Field: [1] PBE1 3694 // 3695 // PBE1 event 3696 // ENUMs: 3697 // SET Interrupt occurred 3698 // CLR Interrupt did not occur 3699 #define LRFDDBELL_RIS1_PBE1 0x00000002U 3700 #define LRFDDBELL_RIS1_PBE1_M 0x00000002U 3701 #define LRFDDBELL_RIS1_PBE1_S 1U 3702 #define LRFDDBELL_RIS1_PBE1_SET 0x00000002U 3703 #define LRFDDBELL_RIS1_PBE1_CLR 0x00000000U 3704 3705 // Field: [0] PBE0 3706 // 3707 // PBE0 event 3708 // ENUMs: 3709 // SET Interrupt occurred 3710 // CLR Interrupt did not occur 3711 #define LRFDDBELL_RIS1_PBE0 0x00000001U 3712 #define LRFDDBELL_RIS1_PBE0_M 0x00000001U 3713 #define LRFDDBELL_RIS1_PBE0_S 0U 3714 #define LRFDDBELL_RIS1_PBE0_SET 0x00000001U 3715 #define LRFDDBELL_RIS1_PBE0_CLR 0x00000000U 3716 3717 //***************************************************************************** 3718 // 3719 // Register: LRFDDBELL_O_MIS1 3720 // 3721 //***************************************************************************** 3722 // Field: [31] SYSTIM2 3723 // 3724 // SYSTIM2 event 3725 // ENUMs: 3726 // SET Interrupt occurred 3727 // CLR Interrupt did not occur 3728 #define LRFDDBELL_MIS1_SYSTIM2 0x80000000U 3729 #define LRFDDBELL_MIS1_SYSTIM2_M 0x80000000U 3730 #define LRFDDBELL_MIS1_SYSTIM2_S 31U 3731 #define LRFDDBELL_MIS1_SYSTIM2_SET 0x80000000U 3732 #define LRFDDBELL_MIS1_SYSTIM2_CLR 0x00000000U 3733 3734 // Field: [30] SYSTIM1 3735 // 3736 // SYSTIM1 event 3737 // ENUMs: 3738 // SET Interrupt occurred 3739 // CLR Interrupt did not occur 3740 #define LRFDDBELL_MIS1_SYSTIM1 0x40000000U 3741 #define LRFDDBELL_MIS1_SYSTIM1_M 0x40000000U 3742 #define LRFDDBELL_MIS1_SYSTIM1_S 30U 3743 #define LRFDDBELL_MIS1_SYSTIM1_SET 0x40000000U 3744 #define LRFDDBELL_MIS1_SYSTIM1_CLR 0x00000000U 3745 3746 // Field: [29] SYSTIM0 3747 // 3748 // SYSTIM0 event 3749 // ENUMs: 3750 // SET Interrupt occurred 3751 // CLR Interrupt did not occur 3752 #define LRFDDBELL_MIS1_SYSTIM0 0x20000000U 3753 #define LRFDDBELL_MIS1_SYSTIM0_M 0x20000000U 3754 #define LRFDDBELL_MIS1_SYSTIM0_S 29U 3755 #define LRFDDBELL_MIS1_SYSTIM0_SET 0x20000000U 3756 #define LRFDDBELL_MIS1_SYSTIM0_CLR 0x00000000U 3757 3758 // Field: [28] MDMDONE 3759 // 3760 // MDMDONE event 3761 // ENUMs: 3762 // SET Interrupt occurred 3763 // CLR Interrupt did not occur 3764 #define LRFDDBELL_MIS1_MDMDONE 0x10000000U 3765 #define LRFDDBELL_MIS1_MDMDONE_M 0x10000000U 3766 #define LRFDDBELL_MIS1_MDMDONE_S 28U 3767 #define LRFDDBELL_MIS1_MDMDONE_SET 0x10000000U 3768 #define LRFDDBELL_MIS1_MDMDONE_CLR 0x00000000U 3769 3770 // Field: [27] MDMIN 3771 // 3772 // MDMIN event 3773 // ENUMs: 3774 // SET Interrupt occurred 3775 // CLR Interrupt did not occur 3776 #define LRFDDBELL_MIS1_MDMIN 0x08000000U 3777 #define LRFDDBELL_MIS1_MDMIN_M 0x08000000U 3778 #define LRFDDBELL_MIS1_MDMIN_S 27U 3779 #define LRFDDBELL_MIS1_MDMIN_SET 0x08000000U 3780 #define LRFDDBELL_MIS1_MDMIN_CLR 0x00000000U 3781 3782 // Field: [26] MDMOUT 3783 // 3784 // MDMOUT event 3785 // ENUMs: 3786 // SET Interrupt occurred 3787 // CLR Interrupt did not occur 3788 #define LRFDDBELL_MIS1_MDMOUT 0x04000000U 3789 #define LRFDDBELL_MIS1_MDMOUT_M 0x04000000U 3790 #define LRFDDBELL_MIS1_MDMOUT_S 26U 3791 #define LRFDDBELL_MIS1_MDMOUT_SET 0x04000000U 3792 #define LRFDDBELL_MIS1_MDMOUT_CLR 0x00000000U 3793 3794 // Field: [25] MDMSOFT2 3795 // 3796 // MDMSOFT event 3797 // ENUMs: 3798 // SET Interrupt occurred 3799 // CLR Interrupt did not occur 3800 #define LRFDDBELL_MIS1_MDMSOFT2 0x02000000U 3801 #define LRFDDBELL_MIS1_MDMSOFT2_M 0x02000000U 3802 #define LRFDDBELL_MIS1_MDMSOFT2_S 25U 3803 #define LRFDDBELL_MIS1_MDMSOFT2_SET 0x02000000U 3804 #define LRFDDBELL_MIS1_MDMSOFT2_CLR 0x00000000U 3805 3806 // Field: [24] MDMSOFT1 3807 // 3808 // MDMSOFT1 event 3809 // ENUMs: 3810 // SET Interrupt occurred 3811 // CLR Interrupt did not occur 3812 #define LRFDDBELL_MIS1_MDMSOFT1 0x01000000U 3813 #define LRFDDBELL_MIS1_MDMSOFT1_M 0x01000000U 3814 #define LRFDDBELL_MIS1_MDMSOFT1_S 24U 3815 #define LRFDDBELL_MIS1_MDMSOFT1_SET 0x01000000U 3816 #define LRFDDBELL_MIS1_MDMSOFT1_CLR 0x00000000U 3817 3818 // Field: [23] MDMSOFT0 3819 // 3820 // MDMSOFT event 3821 // ENUMs: 3822 // SET Interrupt occurred 3823 // CLR Interrupt did not occur 3824 #define LRFDDBELL_MIS1_MDMSOFT0 0x00800000U 3825 #define LRFDDBELL_MIS1_MDMSOFT0_M 0x00800000U 3826 #define LRFDDBELL_MIS1_MDMSOFT0_S 23U 3827 #define LRFDDBELL_MIS1_MDMSOFT0_SET 0x00800000U 3828 #define LRFDDBELL_MIS1_MDMSOFT0_CLR 0x00000000U 3829 3830 // Field: [22] RFEDONE 3831 // 3832 // RFEDONE event 3833 // ENUMs: 3834 // SET Interrupt occurred 3835 // CLR Interrupt did not occur 3836 #define LRFDDBELL_MIS1_RFEDONE 0x00400000U 3837 #define LRFDDBELL_MIS1_RFEDONE_M 0x00400000U 3838 #define LRFDDBELL_MIS1_RFEDONE_S 22U 3839 #define LRFDDBELL_MIS1_RFEDONE_SET 0x00400000U 3840 #define LRFDDBELL_MIS1_RFEDONE_CLR 0x00000000U 3841 3842 // Field: [21] RFESOFT1 3843 // 3844 // RFESOFT1 event 3845 // ENUMs: 3846 // SET Interrupt occurred 3847 // CLR Interrupt did not occur 3848 #define LRFDDBELL_MIS1_RFESOFT1 0x00200000U 3849 #define LRFDDBELL_MIS1_RFESOFT1_M 0x00200000U 3850 #define LRFDDBELL_MIS1_RFESOFT1_S 21U 3851 #define LRFDDBELL_MIS1_RFESOFT1_SET 0x00200000U 3852 #define LRFDDBELL_MIS1_RFESOFT1_CLR 0x00000000U 3853 3854 // Field: [20] RFESOFT0 3855 // 3856 // RFESOFT0 event 3857 // ENUMs: 3858 // SET Interrupt occurred 3859 // CLR Interrupt did not occur 3860 #define LRFDDBELL_MIS1_RFESOFT0 0x00100000U 3861 #define LRFDDBELL_MIS1_RFESOFT0_M 0x00100000U 3862 #define LRFDDBELL_MIS1_RFESOFT0_S 20U 3863 #define LRFDDBELL_MIS1_RFESOFT0_SET 0x00100000U 3864 #define LRFDDBELL_MIS1_RFESOFT0_CLR 0x00000000U 3865 3866 // Field: [19] LOCK 3867 // 3868 // LOCK event 3869 // ENUMs: 3870 // SET Interrupt occurred 3871 // CLR Interrupt did not occur 3872 #define LRFDDBELL_MIS1_LOCK 0x00080000U 3873 #define LRFDDBELL_MIS1_LOCK_M 0x00080000U 3874 #define LRFDDBELL_MIS1_LOCK_S 19U 3875 #define LRFDDBELL_MIS1_LOCK_SET 0x00080000U 3876 #define LRFDDBELL_MIS1_LOCK_CLR 0x00000000U 3877 3878 // Field: [18] LOL 3879 // 3880 // LOSS_OF_LOCK event 3881 // ENUMs: 3882 // SET Interrupt occurred 3883 // CLR Interrupt did not occur 3884 #define LRFDDBELL_MIS1_LOL 0x00040000U 3885 #define LRFDDBELL_MIS1_LOL_M 0x00040000U 3886 #define LRFDDBELL_MIS1_LOL_S 18U 3887 #define LRFDDBELL_MIS1_LOL_SET 0x00040000U 3888 #define LRFDDBELL_MIS1_LOL_CLR 0x00000000U 3889 3890 // Field: [17] TXFIFO 3891 // 3892 // TXFIFO event 3893 // ENUMs: 3894 // SET Interrupt occurred 3895 // CLR Interrupt did not occur 3896 #define LRFDDBELL_MIS1_TXFIFO 0x00020000U 3897 #define LRFDDBELL_MIS1_TXFIFO_M 0x00020000U 3898 #define LRFDDBELL_MIS1_TXFIFO_S 17U 3899 #define LRFDDBELL_MIS1_TXFIFO_SET 0x00020000U 3900 #define LRFDDBELL_MIS1_TXFIFO_CLR 0x00000000U 3901 3902 // Field: [16] RXFIFO 3903 // 3904 // RXFIFO event 3905 // ENUMs: 3906 // SET Interrupt occurred 3907 // CLR Interrupt did not occur 3908 #define LRFDDBELL_MIS1_RXFIFO 0x00010000U 3909 #define LRFDDBELL_MIS1_RXFIFO_M 0x00010000U 3910 #define LRFDDBELL_MIS1_RXFIFO_S 16U 3911 #define LRFDDBELL_MIS1_RXFIFO_SET 0x00010000U 3912 #define LRFDDBELL_MIS1_RXFIFO_CLR 0x00000000U 3913 3914 // Field: [15] PBE15 3915 // 3916 // PBE15 event 3917 // ENUMs: 3918 // SET Interrupt occurred 3919 // CLR Interrupt did not occur 3920 #define LRFDDBELL_MIS1_PBE15 0x00008000U 3921 #define LRFDDBELL_MIS1_PBE15_M 0x00008000U 3922 #define LRFDDBELL_MIS1_PBE15_S 15U 3923 #define LRFDDBELL_MIS1_PBE15_SET 0x00008000U 3924 #define LRFDDBELL_MIS1_PBE15_CLR 0x00000000U 3925 3926 // Field: [14] PBE14 3927 // 3928 // PBE14 event 3929 // ENUMs: 3930 // SET Interrupt occurred 3931 // CLR Interrupt did not occur 3932 #define LRFDDBELL_MIS1_PBE14 0x00004000U 3933 #define LRFDDBELL_MIS1_PBE14_M 0x00004000U 3934 #define LRFDDBELL_MIS1_PBE14_S 14U 3935 #define LRFDDBELL_MIS1_PBE14_SET 0x00004000U 3936 #define LRFDDBELL_MIS1_PBE14_CLR 0x00000000U 3937 3938 // Field: [13] PBE13 3939 // 3940 // PBE13 event 3941 // ENUMs: 3942 // SET Interrupt occurred 3943 // CLR Interrupt did not occur 3944 #define LRFDDBELL_MIS1_PBE13 0x00002000U 3945 #define LRFDDBELL_MIS1_PBE13_M 0x00002000U 3946 #define LRFDDBELL_MIS1_PBE13_S 13U 3947 #define LRFDDBELL_MIS1_PBE13_SET 0x00002000U 3948 #define LRFDDBELL_MIS1_PBE13_CLR 0x00000000U 3949 3950 // Field: [12] PBE12 3951 // 3952 // PBE12 event 3953 // ENUMs: 3954 // SET Interrupt occurred 3955 // CLR Interrupt did not occur 3956 #define LRFDDBELL_MIS1_PBE12 0x00001000U 3957 #define LRFDDBELL_MIS1_PBE12_M 0x00001000U 3958 #define LRFDDBELL_MIS1_PBE12_S 12U 3959 #define LRFDDBELL_MIS1_PBE12_SET 0x00001000U 3960 #define LRFDDBELL_MIS1_PBE12_CLR 0x00000000U 3961 3962 // Field: [11] PBE11 3963 // 3964 // PBE11 event 3965 // ENUMs: 3966 // SET Interrupt occurred 3967 // CLR Interrupt did not occur 3968 #define LRFDDBELL_MIS1_PBE11 0x00000800U 3969 #define LRFDDBELL_MIS1_PBE11_M 0x00000800U 3970 #define LRFDDBELL_MIS1_PBE11_S 11U 3971 #define LRFDDBELL_MIS1_PBE11_SET 0x00000800U 3972 #define LRFDDBELL_MIS1_PBE11_CLR 0x00000000U 3973 3974 // Field: [10] PBE10 3975 // 3976 // PBE10 event 3977 // ENUMs: 3978 // SET Interrupt occurred 3979 // CLR Interrupt did not occur 3980 #define LRFDDBELL_MIS1_PBE10 0x00000400U 3981 #define LRFDDBELL_MIS1_PBE10_M 0x00000400U 3982 #define LRFDDBELL_MIS1_PBE10_S 10U 3983 #define LRFDDBELL_MIS1_PBE10_SET 0x00000400U 3984 #define LRFDDBELL_MIS1_PBE10_CLR 0x00000000U 3985 3986 // Field: [9] PBE9 3987 // 3988 // PBE9 event 3989 // ENUMs: 3990 // SET Interrupt occurred 3991 // CLR Interrupt did not occur 3992 #define LRFDDBELL_MIS1_PBE9 0x00000200U 3993 #define LRFDDBELL_MIS1_PBE9_M 0x00000200U 3994 #define LRFDDBELL_MIS1_PBE9_S 9U 3995 #define LRFDDBELL_MIS1_PBE9_SET 0x00000200U 3996 #define LRFDDBELL_MIS1_PBE9_CLR 0x00000000U 3997 3998 // Field: [8] PBE8 3999 // 4000 // PBE8 event 4001 // ENUMs: 4002 // SET Interrupt occurred 4003 // CLR Interrupt did not occur 4004 #define LRFDDBELL_MIS1_PBE8 0x00000100U 4005 #define LRFDDBELL_MIS1_PBE8_M 0x00000100U 4006 #define LRFDDBELL_MIS1_PBE8_S 8U 4007 #define LRFDDBELL_MIS1_PBE8_SET 0x00000100U 4008 #define LRFDDBELL_MIS1_PBE8_CLR 0x00000000U 4009 4010 // Field: [7] PBE7 4011 // 4012 // PBE7 event 4013 // ENUMs: 4014 // SET Interrupt occurred 4015 // CLR Interrupt did not occur 4016 #define LRFDDBELL_MIS1_PBE7 0x00000080U 4017 #define LRFDDBELL_MIS1_PBE7_M 0x00000080U 4018 #define LRFDDBELL_MIS1_PBE7_S 7U 4019 #define LRFDDBELL_MIS1_PBE7_SET 0x00000080U 4020 #define LRFDDBELL_MIS1_PBE7_CLR 0x00000000U 4021 4022 // Field: [6] PBE6 4023 // 4024 // PBE6 event 4025 // ENUMs: 4026 // SET Interrupt occurred 4027 // CLR Interrupt did not occur 4028 #define LRFDDBELL_MIS1_PBE6 0x00000040U 4029 #define LRFDDBELL_MIS1_PBE6_M 0x00000040U 4030 #define LRFDDBELL_MIS1_PBE6_S 6U 4031 #define LRFDDBELL_MIS1_PBE6_SET 0x00000040U 4032 #define LRFDDBELL_MIS1_PBE6_CLR 0x00000000U 4033 4034 // Field: [5] PBE5 4035 // 4036 // PBE5 event 4037 // ENUMs: 4038 // SET Interrupt occurred 4039 // CLR Interrupt did not occur 4040 #define LRFDDBELL_MIS1_PBE5 0x00000020U 4041 #define LRFDDBELL_MIS1_PBE5_M 0x00000020U 4042 #define LRFDDBELL_MIS1_PBE5_S 5U 4043 #define LRFDDBELL_MIS1_PBE5_SET 0x00000020U 4044 #define LRFDDBELL_MIS1_PBE5_CLR 0x00000000U 4045 4046 // Field: [4] PBE4 4047 // 4048 // PBE4 event 4049 // ENUMs: 4050 // SET Interrupt occurred 4051 // CLR Interrupt did not occur 4052 #define LRFDDBELL_MIS1_PBE4 0x00000010U 4053 #define LRFDDBELL_MIS1_PBE4_M 0x00000010U 4054 #define LRFDDBELL_MIS1_PBE4_S 4U 4055 #define LRFDDBELL_MIS1_PBE4_SET 0x00000010U 4056 #define LRFDDBELL_MIS1_PBE4_CLR 0x00000000U 4057 4058 // Field: [3] PBE3 4059 // 4060 // PBE3 event 4061 // ENUMs: 4062 // SET Interrupt occurred 4063 // CLR Interrupt did not occur 4064 #define LRFDDBELL_MIS1_PBE3 0x00000008U 4065 #define LRFDDBELL_MIS1_PBE3_M 0x00000008U 4066 #define LRFDDBELL_MIS1_PBE3_S 3U 4067 #define LRFDDBELL_MIS1_PBE3_SET 0x00000008U 4068 #define LRFDDBELL_MIS1_PBE3_CLR 0x00000000U 4069 4070 // Field: [2] PBE2 4071 // 4072 // PBE2 event 4073 // ENUMs: 4074 // SET Interrupt occurred 4075 // CLR Interrupt did not occur 4076 #define LRFDDBELL_MIS1_PBE2 0x00000004U 4077 #define LRFDDBELL_MIS1_PBE2_M 0x00000004U 4078 #define LRFDDBELL_MIS1_PBE2_S 2U 4079 #define LRFDDBELL_MIS1_PBE2_SET 0x00000004U 4080 #define LRFDDBELL_MIS1_PBE2_CLR 0x00000000U 4081 4082 // Field: [1] PBE1 4083 // 4084 // PBE1 event 4085 // ENUMs: 4086 // SET Interrupt occurred 4087 // CLR Interrupt did not occur 4088 #define LRFDDBELL_MIS1_PBE1 0x00000002U 4089 #define LRFDDBELL_MIS1_PBE1_M 0x00000002U 4090 #define LRFDDBELL_MIS1_PBE1_S 1U 4091 #define LRFDDBELL_MIS1_PBE1_SET 0x00000002U 4092 #define LRFDDBELL_MIS1_PBE1_CLR 0x00000000U 4093 4094 // Field: [0] PBE0 4095 // 4096 // PBE0 event 4097 // ENUMs: 4098 // SET Interrupt occurred 4099 // CLR Interrupt did not occur 4100 #define LRFDDBELL_MIS1_PBE0 0x00000001U 4101 #define LRFDDBELL_MIS1_PBE0_M 0x00000001U 4102 #define LRFDDBELL_MIS1_PBE0_S 0U 4103 #define LRFDDBELL_MIS1_PBE0_SET 0x00000001U 4104 #define LRFDDBELL_MIS1_PBE0_CLR 0x00000000U 4105 4106 //***************************************************************************** 4107 // 4108 // Register: LRFDDBELL_O_ISET1 4109 // 4110 //***************************************************************************** 4111 // Field: [31] SYSTIM2 4112 // 4113 // SYSTIM2 event 4114 // ENUMs: 4115 // SET Set Interrupt 4116 // NOEFF Writing 0 has no effect 4117 #define LRFDDBELL_ISET1_SYSTIM2 0x80000000U 4118 #define LRFDDBELL_ISET1_SYSTIM2_M 0x80000000U 4119 #define LRFDDBELL_ISET1_SYSTIM2_S 31U 4120 #define LRFDDBELL_ISET1_SYSTIM2_SET 0x80000000U 4121 #define LRFDDBELL_ISET1_SYSTIM2_NOEFF 0x00000000U 4122 4123 // Field: [30] SYSTIM1 4124 // 4125 // SYSTIM1 event 4126 // ENUMs: 4127 // SET Set Interrupt 4128 // NOEFF Writing 0 has no effect 4129 #define LRFDDBELL_ISET1_SYSTIM1 0x40000000U 4130 #define LRFDDBELL_ISET1_SYSTIM1_M 0x40000000U 4131 #define LRFDDBELL_ISET1_SYSTIM1_S 30U 4132 #define LRFDDBELL_ISET1_SYSTIM1_SET 0x40000000U 4133 #define LRFDDBELL_ISET1_SYSTIM1_NOEFF 0x00000000U 4134 4135 // Field: [29] SYSTIM0 4136 // 4137 // SYSTIM0 event 4138 // ENUMs: 4139 // SET Set Interrupt 4140 // NOEFF Writing 0 has no effect 4141 #define LRFDDBELL_ISET1_SYSTIM0 0x20000000U 4142 #define LRFDDBELL_ISET1_SYSTIM0_M 0x20000000U 4143 #define LRFDDBELL_ISET1_SYSTIM0_S 29U 4144 #define LRFDDBELL_ISET1_SYSTIM0_SET 0x20000000U 4145 #define LRFDDBELL_ISET1_SYSTIM0_NOEFF 0x00000000U 4146 4147 // Field: [28] MDMDONE 4148 // 4149 // MDMDONE event 4150 // ENUMs: 4151 // SET Set Interrupt 4152 // NOEFF Writing 0 has no effect 4153 #define LRFDDBELL_ISET1_MDMDONE 0x10000000U 4154 #define LRFDDBELL_ISET1_MDMDONE_M 0x10000000U 4155 #define LRFDDBELL_ISET1_MDMDONE_S 28U 4156 #define LRFDDBELL_ISET1_MDMDONE_SET 0x10000000U 4157 #define LRFDDBELL_ISET1_MDMDONE_NOEFF 0x00000000U 4158 4159 // Field: [27] MDMIN 4160 // 4161 // MDMIN event 4162 // ENUMs: 4163 // SET Set Interrupt 4164 // NOEFF Writing 0 has no effect 4165 #define LRFDDBELL_ISET1_MDMIN 0x08000000U 4166 #define LRFDDBELL_ISET1_MDMIN_M 0x08000000U 4167 #define LRFDDBELL_ISET1_MDMIN_S 27U 4168 #define LRFDDBELL_ISET1_MDMIN_SET 0x08000000U 4169 #define LRFDDBELL_ISET1_MDMIN_NOEFF 0x00000000U 4170 4171 // Field: [26] MDMOUT 4172 // 4173 // MDMOUT event 4174 // ENUMs: 4175 // SET Set Interrupt 4176 // NOEFF Writing 0 has no effect 4177 #define LRFDDBELL_ISET1_MDMOUT 0x04000000U 4178 #define LRFDDBELL_ISET1_MDMOUT_M 0x04000000U 4179 #define LRFDDBELL_ISET1_MDMOUT_S 26U 4180 #define LRFDDBELL_ISET1_MDMOUT_SET 0x04000000U 4181 #define LRFDDBELL_ISET1_MDMOUT_NOEFF 0x00000000U 4182 4183 // Field: [25] MDMSOFT2 4184 // 4185 // MDMSOFT event 4186 // ENUMs: 4187 // SET Set Interrupt 4188 // NOEFF Writing 0 has no effect 4189 #define LRFDDBELL_ISET1_MDMSOFT2 0x02000000U 4190 #define LRFDDBELL_ISET1_MDMSOFT2_M 0x02000000U 4191 #define LRFDDBELL_ISET1_MDMSOFT2_S 25U 4192 #define LRFDDBELL_ISET1_MDMSOFT2_SET 0x02000000U 4193 #define LRFDDBELL_ISET1_MDMSOFT2_NOEFF 0x00000000U 4194 4195 // Field: [24] MDMSOFT1 4196 // 4197 // MDMSOFT1 event 4198 // ENUMs: 4199 // SET Set Interrupt 4200 // NOEFF Writing 0 has no effect 4201 #define LRFDDBELL_ISET1_MDMSOFT1 0x01000000U 4202 #define LRFDDBELL_ISET1_MDMSOFT1_M 0x01000000U 4203 #define LRFDDBELL_ISET1_MDMSOFT1_S 24U 4204 #define LRFDDBELL_ISET1_MDMSOFT1_SET 0x01000000U 4205 #define LRFDDBELL_ISET1_MDMSOFT1_NOEFF 0x00000000U 4206 4207 // Field: [23] MDMSOFT0 4208 // 4209 // MDMSOFT event 4210 // ENUMs: 4211 // SET Set Interrupt 4212 // NOEFF Writing 0 has no effect 4213 #define LRFDDBELL_ISET1_MDMSOFT0 0x00800000U 4214 #define LRFDDBELL_ISET1_MDMSOFT0_M 0x00800000U 4215 #define LRFDDBELL_ISET1_MDMSOFT0_S 23U 4216 #define LRFDDBELL_ISET1_MDMSOFT0_SET 0x00800000U 4217 #define LRFDDBELL_ISET1_MDMSOFT0_NOEFF 0x00000000U 4218 4219 // Field: [22] RFEDONE 4220 // 4221 // RFEDONE event 4222 // ENUMs: 4223 // SET Set Interrupt 4224 // NOEFF Writing 0 has no effect 4225 #define LRFDDBELL_ISET1_RFEDONE 0x00400000U 4226 #define LRFDDBELL_ISET1_RFEDONE_M 0x00400000U 4227 #define LRFDDBELL_ISET1_RFEDONE_S 22U 4228 #define LRFDDBELL_ISET1_RFEDONE_SET 0x00400000U 4229 #define LRFDDBELL_ISET1_RFEDONE_NOEFF 0x00000000U 4230 4231 // Field: [21] RFESOFT1 4232 // 4233 // RFESOFT1 event 4234 // ENUMs: 4235 // SET Set Interrupt 4236 // NOEFF Writing 0 has no effect 4237 #define LRFDDBELL_ISET1_RFESOFT1 0x00200000U 4238 #define LRFDDBELL_ISET1_RFESOFT1_M 0x00200000U 4239 #define LRFDDBELL_ISET1_RFESOFT1_S 21U 4240 #define LRFDDBELL_ISET1_RFESOFT1_SET 0x00200000U 4241 #define LRFDDBELL_ISET1_RFESOFT1_NOEFF 0x00000000U 4242 4243 // Field: [20] RFESOFT0 4244 // 4245 // RFESOFT0 event 4246 // ENUMs: 4247 // SET Set Interrupt 4248 // NOEFF Writing 0 has no effect 4249 #define LRFDDBELL_ISET1_RFESOFT0 0x00100000U 4250 #define LRFDDBELL_ISET1_RFESOFT0_M 0x00100000U 4251 #define LRFDDBELL_ISET1_RFESOFT0_S 20U 4252 #define LRFDDBELL_ISET1_RFESOFT0_SET 0x00100000U 4253 #define LRFDDBELL_ISET1_RFESOFT0_NOEFF 0x00000000U 4254 4255 // Field: [19] LOCK 4256 // 4257 // LOCK event 4258 // ENUMs: 4259 // SET Set Interrupt 4260 // NOEFF Writing 0 has no effect 4261 #define LRFDDBELL_ISET1_LOCK 0x00080000U 4262 #define LRFDDBELL_ISET1_LOCK_M 0x00080000U 4263 #define LRFDDBELL_ISET1_LOCK_S 19U 4264 #define LRFDDBELL_ISET1_LOCK_SET 0x00080000U 4265 #define LRFDDBELL_ISET1_LOCK_NOEFF 0x00000000U 4266 4267 // Field: [18] LOL 4268 // 4269 // LOSS_OF_LOCK event 4270 // ENUMs: 4271 // SET Set Interrupt 4272 // NOEFF Writing 0 has no effect 4273 #define LRFDDBELL_ISET1_LOL 0x00040000U 4274 #define LRFDDBELL_ISET1_LOL_M 0x00040000U 4275 #define LRFDDBELL_ISET1_LOL_S 18U 4276 #define LRFDDBELL_ISET1_LOL_SET 0x00040000U 4277 #define LRFDDBELL_ISET1_LOL_NOEFF 0x00000000U 4278 4279 // Field: [17] TXFIFO 4280 // 4281 // TXFIFO event 4282 // ENUMs: 4283 // SET Set Interrupt 4284 // NOEFF Writing 0 has no effect 4285 #define LRFDDBELL_ISET1_TXFIFO 0x00020000U 4286 #define LRFDDBELL_ISET1_TXFIFO_M 0x00020000U 4287 #define LRFDDBELL_ISET1_TXFIFO_S 17U 4288 #define LRFDDBELL_ISET1_TXFIFO_SET 0x00020000U 4289 #define LRFDDBELL_ISET1_TXFIFO_NOEFF 0x00000000U 4290 4291 // Field: [16] RXFIFO 4292 // 4293 // RXFIFO event 4294 // ENUMs: 4295 // SET Set Interrupt 4296 // NOEFF Writing 0 has no effect 4297 #define LRFDDBELL_ISET1_RXFIFO 0x00010000U 4298 #define LRFDDBELL_ISET1_RXFIFO_M 0x00010000U 4299 #define LRFDDBELL_ISET1_RXFIFO_S 16U 4300 #define LRFDDBELL_ISET1_RXFIFO_SET 0x00010000U 4301 #define LRFDDBELL_ISET1_RXFIFO_NOEFF 0x00000000U 4302 4303 // Field: [15] PBE15 4304 // 4305 // PBE15 event 4306 // ENUMs: 4307 // SET Set Interrupt 4308 // NOEFF Writing 0 has no effect 4309 #define LRFDDBELL_ISET1_PBE15 0x00008000U 4310 #define LRFDDBELL_ISET1_PBE15_M 0x00008000U 4311 #define LRFDDBELL_ISET1_PBE15_S 15U 4312 #define LRFDDBELL_ISET1_PBE15_SET 0x00008000U 4313 #define LRFDDBELL_ISET1_PBE15_NOEFF 0x00000000U 4314 4315 // Field: [14] PBE14 4316 // 4317 // PBE14 event 4318 // ENUMs: 4319 // SET Set Interrupt 4320 // NOEFF Writing 0 has no effect 4321 #define LRFDDBELL_ISET1_PBE14 0x00004000U 4322 #define LRFDDBELL_ISET1_PBE14_M 0x00004000U 4323 #define LRFDDBELL_ISET1_PBE14_S 14U 4324 #define LRFDDBELL_ISET1_PBE14_SET 0x00004000U 4325 #define LRFDDBELL_ISET1_PBE14_NOEFF 0x00000000U 4326 4327 // Field: [13] PBE13 4328 // 4329 // PBE13 event 4330 // ENUMs: 4331 // SET Set Interrupt 4332 // NOEFF Writing 0 has no effect 4333 #define LRFDDBELL_ISET1_PBE13 0x00002000U 4334 #define LRFDDBELL_ISET1_PBE13_M 0x00002000U 4335 #define LRFDDBELL_ISET1_PBE13_S 13U 4336 #define LRFDDBELL_ISET1_PBE13_SET 0x00002000U 4337 #define LRFDDBELL_ISET1_PBE13_NOEFF 0x00000000U 4338 4339 // Field: [12] PBE12 4340 // 4341 // PBE12 event 4342 // ENUMs: 4343 // SET Set Interrupt 4344 // NOEFF Writing 0 has no effect 4345 #define LRFDDBELL_ISET1_PBE12 0x00001000U 4346 #define LRFDDBELL_ISET1_PBE12_M 0x00001000U 4347 #define LRFDDBELL_ISET1_PBE12_S 12U 4348 #define LRFDDBELL_ISET1_PBE12_SET 0x00001000U 4349 #define LRFDDBELL_ISET1_PBE12_NOEFF 0x00000000U 4350 4351 // Field: [11] PBE11 4352 // 4353 // PBE11 event 4354 // ENUMs: 4355 // SET Set Interrupt 4356 // NOEFF Writing 0 has no effect 4357 #define LRFDDBELL_ISET1_PBE11 0x00000800U 4358 #define LRFDDBELL_ISET1_PBE11_M 0x00000800U 4359 #define LRFDDBELL_ISET1_PBE11_S 11U 4360 #define LRFDDBELL_ISET1_PBE11_SET 0x00000800U 4361 #define LRFDDBELL_ISET1_PBE11_NOEFF 0x00000000U 4362 4363 // Field: [10] PBE10 4364 // 4365 // PBE10 event 4366 // ENUMs: 4367 // SET Set Interrupt 4368 // NOEFF Writing 0 has no effect 4369 #define LRFDDBELL_ISET1_PBE10 0x00000400U 4370 #define LRFDDBELL_ISET1_PBE10_M 0x00000400U 4371 #define LRFDDBELL_ISET1_PBE10_S 10U 4372 #define LRFDDBELL_ISET1_PBE10_SET 0x00000400U 4373 #define LRFDDBELL_ISET1_PBE10_NOEFF 0x00000000U 4374 4375 // Field: [9] PBE9 4376 // 4377 // PBE9 event 4378 // ENUMs: 4379 // SET Set Interrupt 4380 // NOEFF Writing 0 has no effect 4381 #define LRFDDBELL_ISET1_PBE9 0x00000200U 4382 #define LRFDDBELL_ISET1_PBE9_M 0x00000200U 4383 #define LRFDDBELL_ISET1_PBE9_S 9U 4384 #define LRFDDBELL_ISET1_PBE9_SET 0x00000200U 4385 #define LRFDDBELL_ISET1_PBE9_NOEFF 0x00000000U 4386 4387 // Field: [8] PBE8 4388 // 4389 // PBE8 event 4390 // ENUMs: 4391 // SET Set Interrupt 4392 // NOEFF Writing 0 has no effect 4393 #define LRFDDBELL_ISET1_PBE8 0x00000100U 4394 #define LRFDDBELL_ISET1_PBE8_M 0x00000100U 4395 #define LRFDDBELL_ISET1_PBE8_S 8U 4396 #define LRFDDBELL_ISET1_PBE8_SET 0x00000100U 4397 #define LRFDDBELL_ISET1_PBE8_NOEFF 0x00000000U 4398 4399 // Field: [7] PBE7 4400 // 4401 // PBE7 event 4402 // ENUMs: 4403 // SET Set Interrupt 4404 // NOEFF Writing 0 has no effect 4405 #define LRFDDBELL_ISET1_PBE7 0x00000080U 4406 #define LRFDDBELL_ISET1_PBE7_M 0x00000080U 4407 #define LRFDDBELL_ISET1_PBE7_S 7U 4408 #define LRFDDBELL_ISET1_PBE7_SET 0x00000080U 4409 #define LRFDDBELL_ISET1_PBE7_NOEFF 0x00000000U 4410 4411 // Field: [6] PBE6 4412 // 4413 // PBE6 event 4414 // ENUMs: 4415 // SET Set Interrupt 4416 // NOEFF Writing 0 has no effect 4417 #define LRFDDBELL_ISET1_PBE6 0x00000040U 4418 #define LRFDDBELL_ISET1_PBE6_M 0x00000040U 4419 #define LRFDDBELL_ISET1_PBE6_S 6U 4420 #define LRFDDBELL_ISET1_PBE6_SET 0x00000040U 4421 #define LRFDDBELL_ISET1_PBE6_NOEFF 0x00000000U 4422 4423 // Field: [5] PBE5 4424 // 4425 // PBE5 event 4426 // ENUMs: 4427 // SET Set Interrupt 4428 // NOEFF Writing 0 has no effect 4429 #define LRFDDBELL_ISET1_PBE5 0x00000020U 4430 #define LRFDDBELL_ISET1_PBE5_M 0x00000020U 4431 #define LRFDDBELL_ISET1_PBE5_S 5U 4432 #define LRFDDBELL_ISET1_PBE5_SET 0x00000020U 4433 #define LRFDDBELL_ISET1_PBE5_NOEFF 0x00000000U 4434 4435 // Field: [4] PBE4 4436 // 4437 // PBE4 event 4438 // ENUMs: 4439 // SET Set Interrupt 4440 // NOEFF Writing 0 has no effect 4441 #define LRFDDBELL_ISET1_PBE4 0x00000010U 4442 #define LRFDDBELL_ISET1_PBE4_M 0x00000010U 4443 #define LRFDDBELL_ISET1_PBE4_S 4U 4444 #define LRFDDBELL_ISET1_PBE4_SET 0x00000010U 4445 #define LRFDDBELL_ISET1_PBE4_NOEFF 0x00000000U 4446 4447 // Field: [3] PBE3 4448 // 4449 // PBE3 event 4450 // ENUMs: 4451 // SET Set Interrupt 4452 // NOEFF Writing 0 has no effect 4453 #define LRFDDBELL_ISET1_PBE3 0x00000008U 4454 #define LRFDDBELL_ISET1_PBE3_M 0x00000008U 4455 #define LRFDDBELL_ISET1_PBE3_S 3U 4456 #define LRFDDBELL_ISET1_PBE3_SET 0x00000008U 4457 #define LRFDDBELL_ISET1_PBE3_NOEFF 0x00000000U 4458 4459 // Field: [2] PBE2 4460 // 4461 // PBE2 event 4462 // ENUMs: 4463 // SET Set Interrupt 4464 // NOEFF Writing 0 has no effect 4465 #define LRFDDBELL_ISET1_PBE2 0x00000004U 4466 #define LRFDDBELL_ISET1_PBE2_M 0x00000004U 4467 #define LRFDDBELL_ISET1_PBE2_S 2U 4468 #define LRFDDBELL_ISET1_PBE2_SET 0x00000004U 4469 #define LRFDDBELL_ISET1_PBE2_NOEFF 0x00000000U 4470 4471 // Field: [1] PBE1 4472 // 4473 // PBE1 event 4474 // ENUMs: 4475 // SET Set Interrupt 4476 // NOEFF Writing 0 has no effect 4477 #define LRFDDBELL_ISET1_PBE1 0x00000002U 4478 #define LRFDDBELL_ISET1_PBE1_M 0x00000002U 4479 #define LRFDDBELL_ISET1_PBE1_S 1U 4480 #define LRFDDBELL_ISET1_PBE1_SET 0x00000002U 4481 #define LRFDDBELL_ISET1_PBE1_NOEFF 0x00000000U 4482 4483 // Field: [0] PBE0 4484 // 4485 // PBE0 event 4486 // ENUMs: 4487 // SET Set Interrupt 4488 // NOEFF Writing 0 has no effect 4489 #define LRFDDBELL_ISET1_PBE0 0x00000001U 4490 #define LRFDDBELL_ISET1_PBE0_M 0x00000001U 4491 #define LRFDDBELL_ISET1_PBE0_S 0U 4492 #define LRFDDBELL_ISET1_PBE0_SET 0x00000001U 4493 #define LRFDDBELL_ISET1_PBE0_NOEFF 0x00000000U 4494 4495 //***************************************************************************** 4496 // 4497 // Register: LRFDDBELL_O_ICLR1 4498 // 4499 //***************************************************************************** 4500 // Field: [31] SYSTIM2 4501 // 4502 // SYSTIM2 event 4503 // ENUMs: 4504 // CLR Clear Interrupt 4505 // NOEFF Writing 0 has no effect 4506 #define LRFDDBELL_ICLR1_SYSTIM2 0x80000000U 4507 #define LRFDDBELL_ICLR1_SYSTIM2_M 0x80000000U 4508 #define LRFDDBELL_ICLR1_SYSTIM2_S 31U 4509 #define LRFDDBELL_ICLR1_SYSTIM2_CLR 0x80000000U 4510 #define LRFDDBELL_ICLR1_SYSTIM2_NOEFF 0x00000000U 4511 4512 // Field: [30] SYSTIM1 4513 // 4514 // SYSTIM1 event 4515 // ENUMs: 4516 // CLR Clear Interrupt 4517 // NOEFF Writing 0 has no effect 4518 #define LRFDDBELL_ICLR1_SYSTIM1 0x40000000U 4519 #define LRFDDBELL_ICLR1_SYSTIM1_M 0x40000000U 4520 #define LRFDDBELL_ICLR1_SYSTIM1_S 30U 4521 #define LRFDDBELL_ICLR1_SYSTIM1_CLR 0x40000000U 4522 #define LRFDDBELL_ICLR1_SYSTIM1_NOEFF 0x00000000U 4523 4524 // Field: [29] SYSTIM0 4525 // 4526 // SYSTIM0 event 4527 // ENUMs: 4528 // CLR Clear Interrupt 4529 // NOEFF Writing 0 has no effect 4530 #define LRFDDBELL_ICLR1_SYSTIM0 0x20000000U 4531 #define LRFDDBELL_ICLR1_SYSTIM0_M 0x20000000U 4532 #define LRFDDBELL_ICLR1_SYSTIM0_S 29U 4533 #define LRFDDBELL_ICLR1_SYSTIM0_CLR 0x20000000U 4534 #define LRFDDBELL_ICLR1_SYSTIM0_NOEFF 0x00000000U 4535 4536 // Field: [28] MDMDONE 4537 // 4538 // MDMDONE event 4539 // ENUMs: 4540 // CLR Clear Interrupt 4541 // NOEFF Writing 0 has no effect 4542 #define LRFDDBELL_ICLR1_MDMDONE 0x10000000U 4543 #define LRFDDBELL_ICLR1_MDMDONE_M 0x10000000U 4544 #define LRFDDBELL_ICLR1_MDMDONE_S 28U 4545 #define LRFDDBELL_ICLR1_MDMDONE_CLR 0x10000000U 4546 #define LRFDDBELL_ICLR1_MDMDONE_NOEFF 0x00000000U 4547 4548 // Field: [27] MDMIN 4549 // 4550 // MDMIN event 4551 // ENUMs: 4552 // CLR Clear Interrupt 4553 // NOEFF Writing 0 has no effect 4554 #define LRFDDBELL_ICLR1_MDMIN 0x08000000U 4555 #define LRFDDBELL_ICLR1_MDMIN_M 0x08000000U 4556 #define LRFDDBELL_ICLR1_MDMIN_S 27U 4557 #define LRFDDBELL_ICLR1_MDMIN_CLR 0x08000000U 4558 #define LRFDDBELL_ICLR1_MDMIN_NOEFF 0x00000000U 4559 4560 // Field: [26] MDMOUT 4561 // 4562 // MDMOUT event 4563 // ENUMs: 4564 // CLR Clear Interrupt 4565 // NOEFF Writing 0 has no effect 4566 #define LRFDDBELL_ICLR1_MDMOUT 0x04000000U 4567 #define LRFDDBELL_ICLR1_MDMOUT_M 0x04000000U 4568 #define LRFDDBELL_ICLR1_MDMOUT_S 26U 4569 #define LRFDDBELL_ICLR1_MDMOUT_CLR 0x04000000U 4570 #define LRFDDBELL_ICLR1_MDMOUT_NOEFF 0x00000000U 4571 4572 // Field: [25] MDMSOFT2 4573 // 4574 // MDMSOFT event 4575 // ENUMs: 4576 // CLR Clear Interrupt 4577 // NOEFF Writing 0 has no effect 4578 #define LRFDDBELL_ICLR1_MDMSOFT2 0x02000000U 4579 #define LRFDDBELL_ICLR1_MDMSOFT2_M 0x02000000U 4580 #define LRFDDBELL_ICLR1_MDMSOFT2_S 25U 4581 #define LRFDDBELL_ICLR1_MDMSOFT2_CLR 0x02000000U 4582 #define LRFDDBELL_ICLR1_MDMSOFT2_NOEFF 0x00000000U 4583 4584 // Field: [24] MDMSOFT1 4585 // 4586 // MDMSOFT1 event 4587 // ENUMs: 4588 // CLR Clear Interrupt 4589 // NOEFF Writing 0 has no effect 4590 #define LRFDDBELL_ICLR1_MDMSOFT1 0x01000000U 4591 #define LRFDDBELL_ICLR1_MDMSOFT1_M 0x01000000U 4592 #define LRFDDBELL_ICLR1_MDMSOFT1_S 24U 4593 #define LRFDDBELL_ICLR1_MDMSOFT1_CLR 0x01000000U 4594 #define LRFDDBELL_ICLR1_MDMSOFT1_NOEFF 0x00000000U 4595 4596 // Field: [23] MDMSOFT0 4597 // 4598 // MDMSOFT event 4599 // ENUMs: 4600 // CLR Clear Interrupt 4601 // NOEFF Writing 0 has no effect 4602 #define LRFDDBELL_ICLR1_MDMSOFT0 0x00800000U 4603 #define LRFDDBELL_ICLR1_MDMSOFT0_M 0x00800000U 4604 #define LRFDDBELL_ICLR1_MDMSOFT0_S 23U 4605 #define LRFDDBELL_ICLR1_MDMSOFT0_CLR 0x00800000U 4606 #define LRFDDBELL_ICLR1_MDMSOFT0_NOEFF 0x00000000U 4607 4608 // Field: [22] RFEDONE 4609 // 4610 // RFEDONE event 4611 // ENUMs: 4612 // CLR Clear Interrupt 4613 // NOEFF Writing 0 has no effect 4614 #define LRFDDBELL_ICLR1_RFEDONE 0x00400000U 4615 #define LRFDDBELL_ICLR1_RFEDONE_M 0x00400000U 4616 #define LRFDDBELL_ICLR1_RFEDONE_S 22U 4617 #define LRFDDBELL_ICLR1_RFEDONE_CLR 0x00400000U 4618 #define LRFDDBELL_ICLR1_RFEDONE_NOEFF 0x00000000U 4619 4620 // Field: [21] RFESOFT1 4621 // 4622 // RFESOFT1 event 4623 // ENUMs: 4624 // CLR Clear Interrupt 4625 // NOEFF Writing 0 has no effect 4626 #define LRFDDBELL_ICLR1_RFESOFT1 0x00200000U 4627 #define LRFDDBELL_ICLR1_RFESOFT1_M 0x00200000U 4628 #define LRFDDBELL_ICLR1_RFESOFT1_S 21U 4629 #define LRFDDBELL_ICLR1_RFESOFT1_CLR 0x00200000U 4630 #define LRFDDBELL_ICLR1_RFESOFT1_NOEFF 0x00000000U 4631 4632 // Field: [20] RFESOFT0 4633 // 4634 // RFESOFT0 event 4635 // ENUMs: 4636 // CLR Clear Interrupt 4637 // NOEFF Writing 0 has no effect 4638 #define LRFDDBELL_ICLR1_RFESOFT0 0x00100000U 4639 #define LRFDDBELL_ICLR1_RFESOFT0_M 0x00100000U 4640 #define LRFDDBELL_ICLR1_RFESOFT0_S 20U 4641 #define LRFDDBELL_ICLR1_RFESOFT0_CLR 0x00100000U 4642 #define LRFDDBELL_ICLR1_RFESOFT0_NOEFF 0x00000000U 4643 4644 // Field: [19] LOCK 4645 // 4646 // LOCK event 4647 // ENUMs: 4648 // CLR Clear Interrupt 4649 // NOEFF Writing 0 has no effect 4650 #define LRFDDBELL_ICLR1_LOCK 0x00080000U 4651 #define LRFDDBELL_ICLR1_LOCK_M 0x00080000U 4652 #define LRFDDBELL_ICLR1_LOCK_S 19U 4653 #define LRFDDBELL_ICLR1_LOCK_CLR 0x00080000U 4654 #define LRFDDBELL_ICLR1_LOCK_NOEFF 0x00000000U 4655 4656 // Field: [18] LOL 4657 // 4658 // LOSS_OF_LOCK event 4659 // ENUMs: 4660 // CLR Clear Interrupt 4661 // NOEFF Writing 0 has no effect 4662 #define LRFDDBELL_ICLR1_LOL 0x00040000U 4663 #define LRFDDBELL_ICLR1_LOL_M 0x00040000U 4664 #define LRFDDBELL_ICLR1_LOL_S 18U 4665 #define LRFDDBELL_ICLR1_LOL_CLR 0x00040000U 4666 #define LRFDDBELL_ICLR1_LOL_NOEFF 0x00000000U 4667 4668 // Field: [17] TXFIFO 4669 // 4670 // TXFIFO event 4671 // ENUMs: 4672 // CLR Clear Interrupt 4673 // NOEFF Writing 0 has no effect 4674 #define LRFDDBELL_ICLR1_TXFIFO 0x00020000U 4675 #define LRFDDBELL_ICLR1_TXFIFO_M 0x00020000U 4676 #define LRFDDBELL_ICLR1_TXFIFO_S 17U 4677 #define LRFDDBELL_ICLR1_TXFIFO_CLR 0x00020000U 4678 #define LRFDDBELL_ICLR1_TXFIFO_NOEFF 0x00000000U 4679 4680 // Field: [16] RXFIFO 4681 // 4682 // RXFIFO event 4683 // ENUMs: 4684 // CLR Clear Interrupt 4685 // NOEFF Writing 0 has no effect 4686 #define LRFDDBELL_ICLR1_RXFIFO 0x00010000U 4687 #define LRFDDBELL_ICLR1_RXFIFO_M 0x00010000U 4688 #define LRFDDBELL_ICLR1_RXFIFO_S 16U 4689 #define LRFDDBELL_ICLR1_RXFIFO_CLR 0x00010000U 4690 #define LRFDDBELL_ICLR1_RXFIFO_NOEFF 0x00000000U 4691 4692 // Field: [15] PBE15 4693 // 4694 // PBE15 event 4695 // ENUMs: 4696 // CLR Clear Interrupt 4697 // NOEFF Writing 0 has no effect 4698 #define LRFDDBELL_ICLR1_PBE15 0x00008000U 4699 #define LRFDDBELL_ICLR1_PBE15_M 0x00008000U 4700 #define LRFDDBELL_ICLR1_PBE15_S 15U 4701 #define LRFDDBELL_ICLR1_PBE15_CLR 0x00008000U 4702 #define LRFDDBELL_ICLR1_PBE15_NOEFF 0x00000000U 4703 4704 // Field: [14] PBE14 4705 // 4706 // PBE14 event 4707 // ENUMs: 4708 // CLR Clear Interrupt 4709 // NOEFF Writing 0 has no effect 4710 #define LRFDDBELL_ICLR1_PBE14 0x00004000U 4711 #define LRFDDBELL_ICLR1_PBE14_M 0x00004000U 4712 #define LRFDDBELL_ICLR1_PBE14_S 14U 4713 #define LRFDDBELL_ICLR1_PBE14_CLR 0x00004000U 4714 #define LRFDDBELL_ICLR1_PBE14_NOEFF 0x00000000U 4715 4716 // Field: [13] PBE13 4717 // 4718 // PBE13 event 4719 // ENUMs: 4720 // CLR Clear Interrupt 4721 // NOEFF Writing 0 has no effect 4722 #define LRFDDBELL_ICLR1_PBE13 0x00002000U 4723 #define LRFDDBELL_ICLR1_PBE13_M 0x00002000U 4724 #define LRFDDBELL_ICLR1_PBE13_S 13U 4725 #define LRFDDBELL_ICLR1_PBE13_CLR 0x00002000U 4726 #define LRFDDBELL_ICLR1_PBE13_NOEFF 0x00000000U 4727 4728 // Field: [12] PBE12 4729 // 4730 // PBE12 event 4731 // ENUMs: 4732 // CLR Clear Interrupt 4733 // NOEFF Writing 0 has no effect 4734 #define LRFDDBELL_ICLR1_PBE12 0x00001000U 4735 #define LRFDDBELL_ICLR1_PBE12_M 0x00001000U 4736 #define LRFDDBELL_ICLR1_PBE12_S 12U 4737 #define LRFDDBELL_ICLR1_PBE12_CLR 0x00001000U 4738 #define LRFDDBELL_ICLR1_PBE12_NOEFF 0x00000000U 4739 4740 // Field: [11] PBE11 4741 // 4742 // PBE11 event 4743 // ENUMs: 4744 // CLR Clear Interrupt 4745 // NOEFF Writing 0 has no effect 4746 #define LRFDDBELL_ICLR1_PBE11 0x00000800U 4747 #define LRFDDBELL_ICLR1_PBE11_M 0x00000800U 4748 #define LRFDDBELL_ICLR1_PBE11_S 11U 4749 #define LRFDDBELL_ICLR1_PBE11_CLR 0x00000800U 4750 #define LRFDDBELL_ICLR1_PBE11_NOEFF 0x00000000U 4751 4752 // Field: [10] PBE10 4753 // 4754 // PBE10 event 4755 // ENUMs: 4756 // CLR Clear Interrupt 4757 // NOEFF Writing 0 has no effect 4758 #define LRFDDBELL_ICLR1_PBE10 0x00000400U 4759 #define LRFDDBELL_ICLR1_PBE10_M 0x00000400U 4760 #define LRFDDBELL_ICLR1_PBE10_S 10U 4761 #define LRFDDBELL_ICLR1_PBE10_CLR 0x00000400U 4762 #define LRFDDBELL_ICLR1_PBE10_NOEFF 0x00000000U 4763 4764 // Field: [9] PBE9 4765 // 4766 // PBE9 event 4767 // ENUMs: 4768 // CLR Clear Interrupt 4769 // NOEFF Writing 0 has no effect 4770 #define LRFDDBELL_ICLR1_PBE9 0x00000200U 4771 #define LRFDDBELL_ICLR1_PBE9_M 0x00000200U 4772 #define LRFDDBELL_ICLR1_PBE9_S 9U 4773 #define LRFDDBELL_ICLR1_PBE9_CLR 0x00000200U 4774 #define LRFDDBELL_ICLR1_PBE9_NOEFF 0x00000000U 4775 4776 // Field: [8] PBE8 4777 // 4778 // PBE8 event 4779 // ENUMs: 4780 // CLR Clear Interrupt 4781 // NOEFF Writing 0 has no effect 4782 #define LRFDDBELL_ICLR1_PBE8 0x00000100U 4783 #define LRFDDBELL_ICLR1_PBE8_M 0x00000100U 4784 #define LRFDDBELL_ICLR1_PBE8_S 8U 4785 #define LRFDDBELL_ICLR1_PBE8_CLR 0x00000100U 4786 #define LRFDDBELL_ICLR1_PBE8_NOEFF 0x00000000U 4787 4788 // Field: [7] PBE7 4789 // 4790 // PBE7 event 4791 // ENUMs: 4792 // CLR Clear Interrupt 4793 // NOEFF Writing 0 has no effect 4794 #define LRFDDBELL_ICLR1_PBE7 0x00000080U 4795 #define LRFDDBELL_ICLR1_PBE7_M 0x00000080U 4796 #define LRFDDBELL_ICLR1_PBE7_S 7U 4797 #define LRFDDBELL_ICLR1_PBE7_CLR 0x00000080U 4798 #define LRFDDBELL_ICLR1_PBE7_NOEFF 0x00000000U 4799 4800 // Field: [6] PBE6 4801 // 4802 // PBE6 event 4803 // ENUMs: 4804 // CLR Clear Interrupt 4805 // NOEFF Writing 0 has no effect 4806 #define LRFDDBELL_ICLR1_PBE6 0x00000040U 4807 #define LRFDDBELL_ICLR1_PBE6_M 0x00000040U 4808 #define LRFDDBELL_ICLR1_PBE6_S 6U 4809 #define LRFDDBELL_ICLR1_PBE6_CLR 0x00000040U 4810 #define LRFDDBELL_ICLR1_PBE6_NOEFF 0x00000000U 4811 4812 // Field: [5] PBE5 4813 // 4814 // PBE5 event 4815 // ENUMs: 4816 // CLR Clear Interrupt 4817 // NOEFF Writing 0 has no effect 4818 #define LRFDDBELL_ICLR1_PBE5 0x00000020U 4819 #define LRFDDBELL_ICLR1_PBE5_M 0x00000020U 4820 #define LRFDDBELL_ICLR1_PBE5_S 5U 4821 #define LRFDDBELL_ICLR1_PBE5_CLR 0x00000020U 4822 #define LRFDDBELL_ICLR1_PBE5_NOEFF 0x00000000U 4823 4824 // Field: [4] PBE4 4825 // 4826 // PBE4 event 4827 // ENUMs: 4828 // CLR Clear Interrupt 4829 // NOEFF Writing 0 has no effect 4830 #define LRFDDBELL_ICLR1_PBE4 0x00000010U 4831 #define LRFDDBELL_ICLR1_PBE4_M 0x00000010U 4832 #define LRFDDBELL_ICLR1_PBE4_S 4U 4833 #define LRFDDBELL_ICLR1_PBE4_CLR 0x00000010U 4834 #define LRFDDBELL_ICLR1_PBE4_NOEFF 0x00000000U 4835 4836 // Field: [3] PBE3 4837 // 4838 // PBE3 event 4839 // ENUMs: 4840 // CLR Clear Interrupt 4841 // NOEFF Writing 0 has no effect 4842 #define LRFDDBELL_ICLR1_PBE3 0x00000008U 4843 #define LRFDDBELL_ICLR1_PBE3_M 0x00000008U 4844 #define LRFDDBELL_ICLR1_PBE3_S 3U 4845 #define LRFDDBELL_ICLR1_PBE3_CLR 0x00000008U 4846 #define LRFDDBELL_ICLR1_PBE3_NOEFF 0x00000000U 4847 4848 // Field: [2] PBE2 4849 // 4850 // PBE2 event 4851 // ENUMs: 4852 // CLR Clear Interrupt 4853 // NOEFF Writing 0 has no effect 4854 #define LRFDDBELL_ICLR1_PBE2 0x00000004U 4855 #define LRFDDBELL_ICLR1_PBE2_M 0x00000004U 4856 #define LRFDDBELL_ICLR1_PBE2_S 2U 4857 #define LRFDDBELL_ICLR1_PBE2_CLR 0x00000004U 4858 #define LRFDDBELL_ICLR1_PBE2_NOEFF 0x00000000U 4859 4860 // Field: [1] PBE1 4861 // 4862 // PBE1 event 4863 // ENUMs: 4864 // CLR Clear Interrupt 4865 // NOEFF Writing 0 has no effect 4866 #define LRFDDBELL_ICLR1_PBE1 0x00000002U 4867 #define LRFDDBELL_ICLR1_PBE1_M 0x00000002U 4868 #define LRFDDBELL_ICLR1_PBE1_S 1U 4869 #define LRFDDBELL_ICLR1_PBE1_CLR 0x00000002U 4870 #define LRFDDBELL_ICLR1_PBE1_NOEFF 0x00000000U 4871 4872 // Field: [0] PBE0 4873 // 4874 // PBE0 event 4875 // ENUMs: 4876 // CLR Clear Interrupt 4877 // NOEFF Writing 0 has no effect 4878 #define LRFDDBELL_ICLR1_PBE0 0x00000001U 4879 #define LRFDDBELL_ICLR1_PBE0_M 0x00000001U 4880 #define LRFDDBELL_ICLR1_PBE0_S 0U 4881 #define LRFDDBELL_ICLR1_PBE0_CLR 0x00000001U 4882 #define LRFDDBELL_ICLR1_PBE0_NOEFF 0x00000000U 4883 4884 //***************************************************************************** 4885 // 4886 // Register: LRFDDBELL_O_IMASK2 4887 // 4888 //***************************************************************************** 4889 // Field: [30] SYSTIM2 4890 // 4891 // SYSTIM2 event 4892 // ENUMs: 4893 // EN Enable interrupt mask 4894 // DIS Disable interrupt mask 4895 #define LRFDDBELL_IMASK2_SYSTIM2 0x40000000U 4896 #define LRFDDBELL_IMASK2_SYSTIM2_M 0x40000000U 4897 #define LRFDDBELL_IMASK2_SYSTIM2_S 30U 4898 #define LRFDDBELL_IMASK2_SYSTIM2_EN 0x40000000U 4899 #define LRFDDBELL_IMASK2_SYSTIM2_DIS 0x00000000U 4900 4901 // Field: [29] SYSTIM1 4902 // 4903 // SYSTIM1 event 4904 // ENUMs: 4905 // EN Enable interrupt mask 4906 // DIS Disable interrupt mask 4907 #define LRFDDBELL_IMASK2_SYSTIM1 0x20000000U 4908 #define LRFDDBELL_IMASK2_SYSTIM1_M 0x20000000U 4909 #define LRFDDBELL_IMASK2_SYSTIM1_S 29U 4910 #define LRFDDBELL_IMASK2_SYSTIM1_EN 0x20000000U 4911 #define LRFDDBELL_IMASK2_SYSTIM1_DIS 0x00000000U 4912 4913 // Field: [28] SYSTIM0 4914 // 4915 // SYSTIM0 event 4916 // ENUMs: 4917 // EN Enable interrupt mask 4918 // DIS Disable interrupt mask 4919 #define LRFDDBELL_IMASK2_SYSTIM0 0x10000000U 4920 #define LRFDDBELL_IMASK2_SYSTIM0_M 0x10000000U 4921 #define LRFDDBELL_IMASK2_SYSTIM0_S 28U 4922 #define LRFDDBELL_IMASK2_SYSTIM0_EN 0x10000000U 4923 #define LRFDDBELL_IMASK2_SYSTIM0_DIS 0x00000000U 4924 4925 // Field: [27] MDMDONE 4926 // 4927 // MDMDONE event 4928 // ENUMs: 4929 // EN Enable interrupt mask 4930 // DIS Disable interrupt mask 4931 #define LRFDDBELL_IMASK2_MDMDONE 0x08000000U 4932 #define LRFDDBELL_IMASK2_MDMDONE_M 0x08000000U 4933 #define LRFDDBELL_IMASK2_MDMDONE_S 27U 4934 #define LRFDDBELL_IMASK2_MDMDONE_EN 0x08000000U 4935 #define LRFDDBELL_IMASK2_MDMDONE_DIS 0x00000000U 4936 4937 // Field: [26] MDMIN 4938 // 4939 // MDMIN event 4940 // ENUMs: 4941 // EN Enable interrupt mask 4942 // DIS Disable interrupt mask 4943 #define LRFDDBELL_IMASK2_MDMIN 0x04000000U 4944 #define LRFDDBELL_IMASK2_MDMIN_M 0x04000000U 4945 #define LRFDDBELL_IMASK2_MDMIN_S 26U 4946 #define LRFDDBELL_IMASK2_MDMIN_EN 0x04000000U 4947 #define LRFDDBELL_IMASK2_MDMIN_DIS 0x00000000U 4948 4949 // Field: [25] MDMOUT 4950 // 4951 // MDMOUT event 4952 // ENUMs: 4953 // EN Enable interrupt mask 4954 // DIS Disable interrupt mask 4955 #define LRFDDBELL_IMASK2_MDMOUT 0x02000000U 4956 #define LRFDDBELL_IMASK2_MDMOUT_M 0x02000000U 4957 #define LRFDDBELL_IMASK2_MDMOUT_S 25U 4958 #define LRFDDBELL_IMASK2_MDMOUT_EN 0x02000000U 4959 #define LRFDDBELL_IMASK2_MDMOUT_DIS 0x00000000U 4960 4961 // Field: [24] MDMSOFT2 4962 // 4963 // MDMSOFT2 event 4964 // ENUMs: 4965 // EN Enable interrupt mask 4966 // DIS Disable interrupt mask 4967 #define LRFDDBELL_IMASK2_MDMSOFT2 0x01000000U 4968 #define LRFDDBELL_IMASK2_MDMSOFT2_M 0x01000000U 4969 #define LRFDDBELL_IMASK2_MDMSOFT2_S 24U 4970 #define LRFDDBELL_IMASK2_MDMSOFT2_EN 0x01000000U 4971 #define LRFDDBELL_IMASK2_MDMSOFT2_DIS 0x00000000U 4972 4973 // Field: [23] MDMSOFT1 4974 // 4975 // MDMSOFT2 event 4976 // ENUMs: 4977 // EN Enable interrupt mask 4978 // DIS Disable interrupt mask 4979 #define LRFDDBELL_IMASK2_MDMSOFT1 0x00800000U 4980 #define LRFDDBELL_IMASK2_MDMSOFT1_M 0x00800000U 4981 #define LRFDDBELL_IMASK2_MDMSOFT1_S 23U 4982 #define LRFDDBELL_IMASK2_MDMSOFT1_EN 0x00800000U 4983 #define LRFDDBELL_IMASK2_MDMSOFT1_DIS 0x00000000U 4984 4985 // Field: [22] MDMSOFT0 4986 // 4987 // MDMSOFT2 event 4988 // ENUMs: 4989 // EN Enable interrupt mask 4990 // DIS Disable interrupt mask 4991 #define LRFDDBELL_IMASK2_MDMSOFT0 0x00400000U 4992 #define LRFDDBELL_IMASK2_MDMSOFT0_M 0x00400000U 4993 #define LRFDDBELL_IMASK2_MDMSOFT0_S 22U 4994 #define LRFDDBELL_IMASK2_MDMSOFT0_EN 0x00400000U 4995 #define LRFDDBELL_IMASK2_MDMSOFT0_DIS 0x00000000U 4996 4997 // Field: [21] RFEDONE 4998 // 4999 // RFEDONE event 5000 // ENUMs: 5001 // EN Enable interrupt mask 5002 // DIS Disable interrupt mask 5003 #define LRFDDBELL_IMASK2_RFEDONE 0x00200000U 5004 #define LRFDDBELL_IMASK2_RFEDONE_M 0x00200000U 5005 #define LRFDDBELL_IMASK2_RFEDONE_S 21U 5006 #define LRFDDBELL_IMASK2_RFEDONE_EN 0x00200000U 5007 #define LRFDDBELL_IMASK2_RFEDONE_DIS 0x00000000U 5008 5009 // Field: [20] RFESOFT1 5010 // 5011 // RFESOFT1 event 5012 // ENUMs: 5013 // EN Enable interrupt mask 5014 // DIS Disable interrupt mask 5015 #define LRFDDBELL_IMASK2_RFESOFT1 0x00100000U 5016 #define LRFDDBELL_IMASK2_RFESOFT1_M 0x00100000U 5017 #define LRFDDBELL_IMASK2_RFESOFT1_S 20U 5018 #define LRFDDBELL_IMASK2_RFESOFT1_EN 0x00100000U 5019 #define LRFDDBELL_IMASK2_RFESOFT1_DIS 0x00000000U 5020 5021 // Field: [19] RFESOFT0 5022 // 5023 // RFESOFT0 event 5024 // ENUMs: 5025 // EN Enable interrupt mask 5026 // DIS Disable interrupt mask 5027 #define LRFDDBELL_IMASK2_RFESOFT0 0x00080000U 5028 #define LRFDDBELL_IMASK2_RFESOFT0_M 0x00080000U 5029 #define LRFDDBELL_IMASK2_RFESOFT0_S 19U 5030 #define LRFDDBELL_IMASK2_RFESOFT0_EN 0x00080000U 5031 #define LRFDDBELL_IMASK2_RFESOFT0_DIS 0x00000000U 5032 5033 // Field: [18] LOCK 5034 // 5035 // LOCK event 5036 // ENUMs: 5037 // EN Enable interrupt mask 5038 // DIS Disable interrupt mask 5039 #define LRFDDBELL_IMASK2_LOCK 0x00040000U 5040 #define LRFDDBELL_IMASK2_LOCK_M 0x00040000U 5041 #define LRFDDBELL_IMASK2_LOCK_S 18U 5042 #define LRFDDBELL_IMASK2_LOCK_EN 0x00040000U 5043 #define LRFDDBELL_IMASK2_LOCK_DIS 0x00000000U 5044 5045 // Field: [17] LOL 5046 // 5047 // LOSS_OF_LOCK event 5048 // ENUMs: 5049 // EN Enable interrupt mask 5050 // DIS Disable interrupt mask 5051 #define LRFDDBELL_IMASK2_LOL 0x00020000U 5052 #define LRFDDBELL_IMASK2_LOL_M 0x00020000U 5053 #define LRFDDBELL_IMASK2_LOL_S 17U 5054 #define LRFDDBELL_IMASK2_LOL_EN 0x00020000U 5055 #define LRFDDBELL_IMASK2_LOL_DIS 0x00000000U 5056 5057 // Field: [16] TXFIFO 5058 // 5059 // TXFIFO event 5060 // ENUMs: 5061 // EN Enable interrupt mask 5062 // DIS Disable interrupt mask 5063 #define LRFDDBELL_IMASK2_TXFIFO 0x00010000U 5064 #define LRFDDBELL_IMASK2_TXFIFO_M 0x00010000U 5065 #define LRFDDBELL_IMASK2_TXFIFO_S 16U 5066 #define LRFDDBELL_IMASK2_TXFIFO_EN 0x00010000U 5067 #define LRFDDBELL_IMASK2_TXFIFO_DIS 0x00000000U 5068 5069 // Field: [15] RXFIFO 5070 // 5071 // RXFIFO event 5072 // ENUMs: 5073 // EN Enable interrupt mask 5074 // DIS Disable interrupt mask 5075 #define LRFDDBELL_IMASK2_RXFIFO 0x00008000U 5076 #define LRFDDBELL_IMASK2_RXFIFO_M 0x00008000U 5077 #define LRFDDBELL_IMASK2_RXFIFO_S 15U 5078 #define LRFDDBELL_IMASK2_RXFIFO_EN 0x00008000U 5079 #define LRFDDBELL_IMASK2_RXFIFO_DIS 0x00000000U 5080 5081 // Field: [14] PBE15 5082 // 5083 // PBE15 event 5084 // ENUMs: 5085 // EN Enable interrupt mask 5086 // DIS Disable interrupt mask 5087 #define LRFDDBELL_IMASK2_PBE15 0x00004000U 5088 #define LRFDDBELL_IMASK2_PBE15_M 0x00004000U 5089 #define LRFDDBELL_IMASK2_PBE15_S 14U 5090 #define LRFDDBELL_IMASK2_PBE15_EN 0x00004000U 5091 #define LRFDDBELL_IMASK2_PBE15_DIS 0x00000000U 5092 5093 // Field: [13] PBE14 5094 // 5095 // PBE14 event 5096 // ENUMs: 5097 // EN Enable interrupt mask 5098 // DIS Disable interrupt mask 5099 #define LRFDDBELL_IMASK2_PBE14 0x00002000U 5100 #define LRFDDBELL_IMASK2_PBE14_M 0x00002000U 5101 #define LRFDDBELL_IMASK2_PBE14_S 13U 5102 #define LRFDDBELL_IMASK2_PBE14_EN 0x00002000U 5103 #define LRFDDBELL_IMASK2_PBE14_DIS 0x00000000U 5104 5105 // Field: [12] PBE13 5106 // 5107 // PBE13 event 5108 // ENUMs: 5109 // EN Enable interrupt mask 5110 // DIS Disable interrupt mask 5111 #define LRFDDBELL_IMASK2_PBE13 0x00001000U 5112 #define LRFDDBELL_IMASK2_PBE13_M 0x00001000U 5113 #define LRFDDBELL_IMASK2_PBE13_S 12U 5114 #define LRFDDBELL_IMASK2_PBE13_EN 0x00001000U 5115 #define LRFDDBELL_IMASK2_PBE13_DIS 0x00000000U 5116 5117 // Field: [11] PBE12 5118 // 5119 // PBE12 event 5120 // ENUMs: 5121 // EN Enable interrupt mask 5122 // DIS Disable interrupt mask 5123 #define LRFDDBELL_IMASK2_PBE12 0x00000800U 5124 #define LRFDDBELL_IMASK2_PBE12_M 0x00000800U 5125 #define LRFDDBELL_IMASK2_PBE12_S 11U 5126 #define LRFDDBELL_IMASK2_PBE12_EN 0x00000800U 5127 #define LRFDDBELL_IMASK2_PBE12_DIS 0x00000000U 5128 5129 // Field: [10] PBE11 5130 // 5131 // PBE11 event 5132 // ENUMs: 5133 // EN Enable interrupt mask 5134 // DIS Disable interrupt mask 5135 #define LRFDDBELL_IMASK2_PBE11 0x00000400U 5136 #define LRFDDBELL_IMASK2_PBE11_M 0x00000400U 5137 #define LRFDDBELL_IMASK2_PBE11_S 10U 5138 #define LRFDDBELL_IMASK2_PBE11_EN 0x00000400U 5139 #define LRFDDBELL_IMASK2_PBE11_DIS 0x00000000U 5140 5141 // Field: [9] PBE10 5142 // 5143 // PBE10 event 5144 // ENUMs: 5145 // EN Enable interrupt mask 5146 // DIS Disable interrupt mask 5147 #define LRFDDBELL_IMASK2_PBE10 0x00000200U 5148 #define LRFDDBELL_IMASK2_PBE10_M 0x00000200U 5149 #define LRFDDBELL_IMASK2_PBE10_S 9U 5150 #define LRFDDBELL_IMASK2_PBE10_EN 0x00000200U 5151 #define LRFDDBELL_IMASK2_PBE10_DIS 0x00000000U 5152 5153 // Field: [8] PBE8 5154 // 5155 // PBE8 event 5156 // ENUMs: 5157 // EN Enable interrupt mask 5158 // DIS Disable interrupt mask 5159 #define LRFDDBELL_IMASK2_PBE8 0x00000100U 5160 #define LRFDDBELL_IMASK2_PBE8_M 0x00000100U 5161 #define LRFDDBELL_IMASK2_PBE8_S 8U 5162 #define LRFDDBELL_IMASK2_PBE8_EN 0x00000100U 5163 #define LRFDDBELL_IMASK2_PBE8_DIS 0x00000000U 5164 5165 // Field: [7] PBE7 5166 // 5167 // PBE7 event 5168 // ENUMs: 5169 // EN Enable interrupt mask 5170 // DIS Disable interrupt mask 5171 #define LRFDDBELL_IMASK2_PBE7 0x00000080U 5172 #define LRFDDBELL_IMASK2_PBE7_M 0x00000080U 5173 #define LRFDDBELL_IMASK2_PBE7_S 7U 5174 #define LRFDDBELL_IMASK2_PBE7_EN 0x00000080U 5175 #define LRFDDBELL_IMASK2_PBE7_DIS 0x00000000U 5176 5177 // Field: [6] PBE6 5178 // 5179 // PBE6 event 5180 // ENUMs: 5181 // EN Enable interrupt mask 5182 // DIS Disable interrupt mask 5183 #define LRFDDBELL_IMASK2_PBE6 0x00000040U 5184 #define LRFDDBELL_IMASK2_PBE6_M 0x00000040U 5185 #define LRFDDBELL_IMASK2_PBE6_S 6U 5186 #define LRFDDBELL_IMASK2_PBE6_EN 0x00000040U 5187 #define LRFDDBELL_IMASK2_PBE6_DIS 0x00000000U 5188 5189 // Field: [5] PBE5 5190 // 5191 // PBE5 event 5192 // ENUMs: 5193 // EN Enable interrupt mask 5194 // DIS Disable interrupt mask 5195 #define LRFDDBELL_IMASK2_PBE5 0x00000020U 5196 #define LRFDDBELL_IMASK2_PBE5_M 0x00000020U 5197 #define LRFDDBELL_IMASK2_PBE5_S 5U 5198 #define LRFDDBELL_IMASK2_PBE5_EN 0x00000020U 5199 #define LRFDDBELL_IMASK2_PBE5_DIS 0x00000000U 5200 5201 // Field: [4] PBE4 5202 // 5203 // PBE4 event 5204 // ENUMs: 5205 // EN Enable interrupt mask 5206 // DIS Disable interrupt mask 5207 #define LRFDDBELL_IMASK2_PBE4 0x00000010U 5208 #define LRFDDBELL_IMASK2_PBE4_M 0x00000010U 5209 #define LRFDDBELL_IMASK2_PBE4_S 4U 5210 #define LRFDDBELL_IMASK2_PBE4_EN 0x00000010U 5211 #define LRFDDBELL_IMASK2_PBE4_DIS 0x00000000U 5212 5213 // Field: [3] PBE3 5214 // 5215 // PBE3 event 5216 // ENUMs: 5217 // EN Enable interrupt mask 5218 // DIS Disable interrupt mask 5219 #define LRFDDBELL_IMASK2_PBE3 0x00000008U 5220 #define LRFDDBELL_IMASK2_PBE3_M 0x00000008U 5221 #define LRFDDBELL_IMASK2_PBE3_S 3U 5222 #define LRFDDBELL_IMASK2_PBE3_EN 0x00000008U 5223 #define LRFDDBELL_IMASK2_PBE3_DIS 0x00000000U 5224 5225 // Field: [2] PBE2 5226 // 5227 // PBE2 event 5228 // ENUMs: 5229 // EN Enable interrupt mask 5230 // DIS Disable interrupt mask 5231 #define LRFDDBELL_IMASK2_PBE2 0x00000004U 5232 #define LRFDDBELL_IMASK2_PBE2_M 0x00000004U 5233 #define LRFDDBELL_IMASK2_PBE2_S 2U 5234 #define LRFDDBELL_IMASK2_PBE2_EN 0x00000004U 5235 #define LRFDDBELL_IMASK2_PBE2_DIS 0x00000000U 5236 5237 // Field: [1] PBE1 5238 // 5239 // PBE1 event 5240 // ENUMs: 5241 // EN Enable interrupt mask 5242 // DIS Disable interrupt mask 5243 #define LRFDDBELL_IMASK2_PBE1 0x00000002U 5244 #define LRFDDBELL_IMASK2_PBE1_M 0x00000002U 5245 #define LRFDDBELL_IMASK2_PBE1_S 1U 5246 #define LRFDDBELL_IMASK2_PBE1_EN 0x00000002U 5247 #define LRFDDBELL_IMASK2_PBE1_DIS 0x00000000U 5248 5249 // Field: [0] PBE0 5250 // 5251 // PBE0 event 5252 // ENUMs: 5253 // EN Enable interrupt mask 5254 // DIS Disable interrupt mask 5255 #define LRFDDBELL_IMASK2_PBE0 0x00000001U 5256 #define LRFDDBELL_IMASK2_PBE0_M 0x00000001U 5257 #define LRFDDBELL_IMASK2_PBE0_S 0U 5258 #define LRFDDBELL_IMASK2_PBE0_EN 0x00000001U 5259 #define LRFDDBELL_IMASK2_PBE0_DIS 0x00000000U 5260 5261 //***************************************************************************** 5262 // 5263 // Register: LRFDDBELL_O_RIS2 5264 // 5265 //***************************************************************************** 5266 // Field: [31] SYSTIM2 5267 // 5268 // SYSTIM2 event 5269 // ENUMs: 5270 // SET Interrupt occurred 5271 // CLR Interrupt did not occur 5272 #define LRFDDBELL_RIS2_SYSTIM2 0x80000000U 5273 #define LRFDDBELL_RIS2_SYSTIM2_M 0x80000000U 5274 #define LRFDDBELL_RIS2_SYSTIM2_S 31U 5275 #define LRFDDBELL_RIS2_SYSTIM2_SET 0x80000000U 5276 #define LRFDDBELL_RIS2_SYSTIM2_CLR 0x00000000U 5277 5278 // Field: [30] SYSTIM1 5279 // 5280 // SYSTIM1 event 5281 // ENUMs: 5282 // SET Interrupt occurred 5283 // CLR Interrupt did not occur 5284 #define LRFDDBELL_RIS2_SYSTIM1 0x40000000U 5285 #define LRFDDBELL_RIS2_SYSTIM1_M 0x40000000U 5286 #define LRFDDBELL_RIS2_SYSTIM1_S 30U 5287 #define LRFDDBELL_RIS2_SYSTIM1_SET 0x40000000U 5288 #define LRFDDBELL_RIS2_SYSTIM1_CLR 0x00000000U 5289 5290 // Field: [29] SYSTIM0 5291 // 5292 // SYSTIM0 event 5293 // ENUMs: 5294 // SET Interrupt occurred 5295 // CLR Interrupt did not occur 5296 #define LRFDDBELL_RIS2_SYSTIM0 0x20000000U 5297 #define LRFDDBELL_RIS2_SYSTIM0_M 0x20000000U 5298 #define LRFDDBELL_RIS2_SYSTIM0_S 29U 5299 #define LRFDDBELL_RIS2_SYSTIM0_SET 0x20000000U 5300 #define LRFDDBELL_RIS2_SYSTIM0_CLR 0x00000000U 5301 5302 // Field: [28] MDMDONE 5303 // 5304 // MDMDONE event 5305 // ENUMs: 5306 // SET Interrupt occurred 5307 // CLR Interrupt did not occur 5308 #define LRFDDBELL_RIS2_MDMDONE 0x10000000U 5309 #define LRFDDBELL_RIS2_MDMDONE_M 0x10000000U 5310 #define LRFDDBELL_RIS2_MDMDONE_S 28U 5311 #define LRFDDBELL_RIS2_MDMDONE_SET 0x10000000U 5312 #define LRFDDBELL_RIS2_MDMDONE_CLR 0x00000000U 5313 5314 // Field: [27] MDMIN 5315 // 5316 // MDMIN event 5317 // ENUMs: 5318 // SET Interrupt occurred 5319 // CLR Interrupt did not occur 5320 #define LRFDDBELL_RIS2_MDMIN 0x08000000U 5321 #define LRFDDBELL_RIS2_MDMIN_M 0x08000000U 5322 #define LRFDDBELL_RIS2_MDMIN_S 27U 5323 #define LRFDDBELL_RIS2_MDMIN_SET 0x08000000U 5324 #define LRFDDBELL_RIS2_MDMIN_CLR 0x00000000U 5325 5326 // Field: [26] MDMOUT 5327 // 5328 // MDMOUT event 5329 // ENUMs: 5330 // SET Interrupt occurred 5331 // CLR Interrupt did not occur 5332 #define LRFDDBELL_RIS2_MDMOUT 0x04000000U 5333 #define LRFDDBELL_RIS2_MDMOUT_M 0x04000000U 5334 #define LRFDDBELL_RIS2_MDMOUT_S 26U 5335 #define LRFDDBELL_RIS2_MDMOUT_SET 0x04000000U 5336 #define LRFDDBELL_RIS2_MDMOUT_CLR 0x00000000U 5337 5338 // Field: [25] MDMSOFT2 5339 // 5340 // MDMSOFT event 5341 // ENUMs: 5342 // SET Interrupt occurred 5343 // CLR Interrupt did not occur 5344 #define LRFDDBELL_RIS2_MDMSOFT2 0x02000000U 5345 #define LRFDDBELL_RIS2_MDMSOFT2_M 0x02000000U 5346 #define LRFDDBELL_RIS2_MDMSOFT2_S 25U 5347 #define LRFDDBELL_RIS2_MDMSOFT2_SET 0x02000000U 5348 #define LRFDDBELL_RIS2_MDMSOFT2_CLR 0x00000000U 5349 5350 // Field: [24] MDMSOFT1 5351 // 5352 // MDMSOFT1 event 5353 // ENUMs: 5354 // SET Interrupt occurred 5355 // CLR Interrupt did not occur 5356 #define LRFDDBELL_RIS2_MDMSOFT1 0x01000000U 5357 #define LRFDDBELL_RIS2_MDMSOFT1_M 0x01000000U 5358 #define LRFDDBELL_RIS2_MDMSOFT1_S 24U 5359 #define LRFDDBELL_RIS2_MDMSOFT1_SET 0x01000000U 5360 #define LRFDDBELL_RIS2_MDMSOFT1_CLR 0x00000000U 5361 5362 // Field: [23] MDMSOFT0 5363 // 5364 // MDMSOFT event 5365 // ENUMs: 5366 // SET Interrupt occurred 5367 // CLR Interrupt did not occur 5368 #define LRFDDBELL_RIS2_MDMSOFT0 0x00800000U 5369 #define LRFDDBELL_RIS2_MDMSOFT0_M 0x00800000U 5370 #define LRFDDBELL_RIS2_MDMSOFT0_S 23U 5371 #define LRFDDBELL_RIS2_MDMSOFT0_SET 0x00800000U 5372 #define LRFDDBELL_RIS2_MDMSOFT0_CLR 0x00000000U 5373 5374 // Field: [22] RFEDONE 5375 // 5376 // RFEDONE event 5377 // ENUMs: 5378 // SET Interrupt occurred 5379 // CLR Interrupt did not occur 5380 #define LRFDDBELL_RIS2_RFEDONE 0x00400000U 5381 #define LRFDDBELL_RIS2_RFEDONE_M 0x00400000U 5382 #define LRFDDBELL_RIS2_RFEDONE_S 22U 5383 #define LRFDDBELL_RIS2_RFEDONE_SET 0x00400000U 5384 #define LRFDDBELL_RIS2_RFEDONE_CLR 0x00000000U 5385 5386 // Field: [21] RFESOFT1 5387 // 5388 // RFESOFT1 event 5389 // ENUMs: 5390 // SET Interrupt occurred 5391 // CLR Interrupt did not occur 5392 #define LRFDDBELL_RIS2_RFESOFT1 0x00200000U 5393 #define LRFDDBELL_RIS2_RFESOFT1_M 0x00200000U 5394 #define LRFDDBELL_RIS2_RFESOFT1_S 21U 5395 #define LRFDDBELL_RIS2_RFESOFT1_SET 0x00200000U 5396 #define LRFDDBELL_RIS2_RFESOFT1_CLR 0x00000000U 5397 5398 // Field: [20] RFESOFT0 5399 // 5400 // RFESOFT0 event 5401 // ENUMs: 5402 // SET Interrupt occurred 5403 // CLR Interrupt did not occur 5404 #define LRFDDBELL_RIS2_RFESOFT0 0x00100000U 5405 #define LRFDDBELL_RIS2_RFESOFT0_M 0x00100000U 5406 #define LRFDDBELL_RIS2_RFESOFT0_S 20U 5407 #define LRFDDBELL_RIS2_RFESOFT0_SET 0x00100000U 5408 #define LRFDDBELL_RIS2_RFESOFT0_CLR 0x00000000U 5409 5410 // Field: [19] LOCK 5411 // 5412 // LOCK event 5413 // ENUMs: 5414 // SET Interrupt occurred 5415 // CLR Interrupt did not occur 5416 #define LRFDDBELL_RIS2_LOCK 0x00080000U 5417 #define LRFDDBELL_RIS2_LOCK_M 0x00080000U 5418 #define LRFDDBELL_RIS2_LOCK_S 19U 5419 #define LRFDDBELL_RIS2_LOCK_SET 0x00080000U 5420 #define LRFDDBELL_RIS2_LOCK_CLR 0x00000000U 5421 5422 // Field: [18] LOL 5423 // 5424 // LOSS_OF_LOCK event 5425 // ENUMs: 5426 // SET Interrupt occurred 5427 // CLR Interrupt did not occur 5428 #define LRFDDBELL_RIS2_LOL 0x00040000U 5429 #define LRFDDBELL_RIS2_LOL_M 0x00040000U 5430 #define LRFDDBELL_RIS2_LOL_S 18U 5431 #define LRFDDBELL_RIS2_LOL_SET 0x00040000U 5432 #define LRFDDBELL_RIS2_LOL_CLR 0x00000000U 5433 5434 // Field: [17] TXFIFO 5435 // 5436 // TXFIFO event 5437 // ENUMs: 5438 // SET Interrupt occurred 5439 // CLR Interrupt did not occur 5440 #define LRFDDBELL_RIS2_TXFIFO 0x00020000U 5441 #define LRFDDBELL_RIS2_TXFIFO_M 0x00020000U 5442 #define LRFDDBELL_RIS2_TXFIFO_S 17U 5443 #define LRFDDBELL_RIS2_TXFIFO_SET 0x00020000U 5444 #define LRFDDBELL_RIS2_TXFIFO_CLR 0x00000000U 5445 5446 // Field: [16] RXFIFO 5447 // 5448 // RXFIFO event 5449 // ENUMs: 5450 // SET Interrupt occurred 5451 // CLR Interrupt did not occur 5452 #define LRFDDBELL_RIS2_RXFIFO 0x00010000U 5453 #define LRFDDBELL_RIS2_RXFIFO_M 0x00010000U 5454 #define LRFDDBELL_RIS2_RXFIFO_S 16U 5455 #define LRFDDBELL_RIS2_RXFIFO_SET 0x00010000U 5456 #define LRFDDBELL_RIS2_RXFIFO_CLR 0x00000000U 5457 5458 // Field: [15] PBE15 5459 // 5460 // PBE15 event 5461 // ENUMs: 5462 // SET Interrupt occurred 5463 // CLR Interrupt did not occur 5464 #define LRFDDBELL_RIS2_PBE15 0x00008000U 5465 #define LRFDDBELL_RIS2_PBE15_M 0x00008000U 5466 #define LRFDDBELL_RIS2_PBE15_S 15U 5467 #define LRFDDBELL_RIS2_PBE15_SET 0x00008000U 5468 #define LRFDDBELL_RIS2_PBE15_CLR 0x00000000U 5469 5470 // Field: [14] PBE14 5471 // 5472 // PBE14 event 5473 // ENUMs: 5474 // SET Interrupt occurred 5475 // CLR Interrupt did not occur 5476 #define LRFDDBELL_RIS2_PBE14 0x00004000U 5477 #define LRFDDBELL_RIS2_PBE14_M 0x00004000U 5478 #define LRFDDBELL_RIS2_PBE14_S 14U 5479 #define LRFDDBELL_RIS2_PBE14_SET 0x00004000U 5480 #define LRFDDBELL_RIS2_PBE14_CLR 0x00000000U 5481 5482 // Field: [13] PBE13 5483 // 5484 // PBE13 event 5485 // ENUMs: 5486 // SET Interrupt occurred 5487 // CLR Interrupt did not occur 5488 #define LRFDDBELL_RIS2_PBE13 0x00002000U 5489 #define LRFDDBELL_RIS2_PBE13_M 0x00002000U 5490 #define LRFDDBELL_RIS2_PBE13_S 13U 5491 #define LRFDDBELL_RIS2_PBE13_SET 0x00002000U 5492 #define LRFDDBELL_RIS2_PBE13_CLR 0x00000000U 5493 5494 // Field: [12] PBE12 5495 // 5496 // PBE12 event 5497 // ENUMs: 5498 // SET Interrupt occurred 5499 // CLR Interrupt did not occur 5500 #define LRFDDBELL_RIS2_PBE12 0x00001000U 5501 #define LRFDDBELL_RIS2_PBE12_M 0x00001000U 5502 #define LRFDDBELL_RIS2_PBE12_S 12U 5503 #define LRFDDBELL_RIS2_PBE12_SET 0x00001000U 5504 #define LRFDDBELL_RIS2_PBE12_CLR 0x00000000U 5505 5506 // Field: [11] PBE11 5507 // 5508 // PBE11 event 5509 // ENUMs: 5510 // SET Interrupt occurred 5511 // CLR Interrupt did not occur 5512 #define LRFDDBELL_RIS2_PBE11 0x00000800U 5513 #define LRFDDBELL_RIS2_PBE11_M 0x00000800U 5514 #define LRFDDBELL_RIS2_PBE11_S 11U 5515 #define LRFDDBELL_RIS2_PBE11_SET 0x00000800U 5516 #define LRFDDBELL_RIS2_PBE11_CLR 0x00000000U 5517 5518 // Field: [10] PBE10 5519 // 5520 // PBE10 event 5521 // ENUMs: 5522 // SET Interrupt occurred 5523 // CLR Interrupt did not occur 5524 #define LRFDDBELL_RIS2_PBE10 0x00000400U 5525 #define LRFDDBELL_RIS2_PBE10_M 0x00000400U 5526 #define LRFDDBELL_RIS2_PBE10_S 10U 5527 #define LRFDDBELL_RIS2_PBE10_SET 0x00000400U 5528 #define LRFDDBELL_RIS2_PBE10_CLR 0x00000000U 5529 5530 // Field: [9] PBE9 5531 // 5532 // PBE9 event 5533 // ENUMs: 5534 // SET Interrupt occurred 5535 // CLR Interrupt did not occur 5536 #define LRFDDBELL_RIS2_PBE9 0x00000200U 5537 #define LRFDDBELL_RIS2_PBE9_M 0x00000200U 5538 #define LRFDDBELL_RIS2_PBE9_S 9U 5539 #define LRFDDBELL_RIS2_PBE9_SET 0x00000200U 5540 #define LRFDDBELL_RIS2_PBE9_CLR 0x00000000U 5541 5542 // Field: [8] PBE8 5543 // 5544 // PBE8 event 5545 // ENUMs: 5546 // SET Interrupt occurred 5547 // CLR Interrupt did not occur 5548 #define LRFDDBELL_RIS2_PBE8 0x00000100U 5549 #define LRFDDBELL_RIS2_PBE8_M 0x00000100U 5550 #define LRFDDBELL_RIS2_PBE8_S 8U 5551 #define LRFDDBELL_RIS2_PBE8_SET 0x00000100U 5552 #define LRFDDBELL_RIS2_PBE8_CLR 0x00000000U 5553 5554 // Field: [7] PBE7 5555 // 5556 // PBE7 event 5557 // ENUMs: 5558 // SET Interrupt occurred 5559 // CLR Interrupt did not occur 5560 #define LRFDDBELL_RIS2_PBE7 0x00000080U 5561 #define LRFDDBELL_RIS2_PBE7_M 0x00000080U 5562 #define LRFDDBELL_RIS2_PBE7_S 7U 5563 #define LRFDDBELL_RIS2_PBE7_SET 0x00000080U 5564 #define LRFDDBELL_RIS2_PBE7_CLR 0x00000000U 5565 5566 // Field: [6] PBE6 5567 // 5568 // PBE6 event 5569 // ENUMs: 5570 // SET Interrupt occurred 5571 // CLR Interrupt did not occur 5572 #define LRFDDBELL_RIS2_PBE6 0x00000040U 5573 #define LRFDDBELL_RIS2_PBE6_M 0x00000040U 5574 #define LRFDDBELL_RIS2_PBE6_S 6U 5575 #define LRFDDBELL_RIS2_PBE6_SET 0x00000040U 5576 #define LRFDDBELL_RIS2_PBE6_CLR 0x00000000U 5577 5578 // Field: [5] PBE5 5579 // 5580 // PBE5 event 5581 // ENUMs: 5582 // SET Interrupt occurred 5583 // CLR Interrupt did not occur 5584 #define LRFDDBELL_RIS2_PBE5 0x00000020U 5585 #define LRFDDBELL_RIS2_PBE5_M 0x00000020U 5586 #define LRFDDBELL_RIS2_PBE5_S 5U 5587 #define LRFDDBELL_RIS2_PBE5_SET 0x00000020U 5588 #define LRFDDBELL_RIS2_PBE5_CLR 0x00000000U 5589 5590 // Field: [4] PBE4 5591 // 5592 // PBE4 event 5593 // ENUMs: 5594 // SET Interrupt occurred 5595 // CLR Interrupt did not occur 5596 #define LRFDDBELL_RIS2_PBE4 0x00000010U 5597 #define LRFDDBELL_RIS2_PBE4_M 0x00000010U 5598 #define LRFDDBELL_RIS2_PBE4_S 4U 5599 #define LRFDDBELL_RIS2_PBE4_SET 0x00000010U 5600 #define LRFDDBELL_RIS2_PBE4_CLR 0x00000000U 5601 5602 // Field: [3] PBE3 5603 // 5604 // PBE3 event 5605 // ENUMs: 5606 // SET Interrupt occurred 5607 // CLR Interrupt did not occur 5608 #define LRFDDBELL_RIS2_PBE3 0x00000008U 5609 #define LRFDDBELL_RIS2_PBE3_M 0x00000008U 5610 #define LRFDDBELL_RIS2_PBE3_S 3U 5611 #define LRFDDBELL_RIS2_PBE3_SET 0x00000008U 5612 #define LRFDDBELL_RIS2_PBE3_CLR 0x00000000U 5613 5614 // Field: [2] PBE2 5615 // 5616 // PBE2 event 5617 // ENUMs: 5618 // SET Interrupt occurred 5619 // CLR Interrupt did not occur 5620 #define LRFDDBELL_RIS2_PBE2 0x00000004U 5621 #define LRFDDBELL_RIS2_PBE2_M 0x00000004U 5622 #define LRFDDBELL_RIS2_PBE2_S 2U 5623 #define LRFDDBELL_RIS2_PBE2_SET 0x00000004U 5624 #define LRFDDBELL_RIS2_PBE2_CLR 0x00000000U 5625 5626 // Field: [1] PBE1 5627 // 5628 // PBE1 event 5629 // ENUMs: 5630 // SET Interrupt occurred 5631 // CLR Interrupt did not occur 5632 #define LRFDDBELL_RIS2_PBE1 0x00000002U 5633 #define LRFDDBELL_RIS2_PBE1_M 0x00000002U 5634 #define LRFDDBELL_RIS2_PBE1_S 1U 5635 #define LRFDDBELL_RIS2_PBE1_SET 0x00000002U 5636 #define LRFDDBELL_RIS2_PBE1_CLR 0x00000000U 5637 5638 // Field: [0] PBE0 5639 // 5640 // PBE0 event 5641 // ENUMs: 5642 // SET Interrupt occurred 5643 // CLR Interrupt did not occur 5644 #define LRFDDBELL_RIS2_PBE0 0x00000001U 5645 #define LRFDDBELL_RIS2_PBE0_M 0x00000001U 5646 #define LRFDDBELL_RIS2_PBE0_S 0U 5647 #define LRFDDBELL_RIS2_PBE0_SET 0x00000001U 5648 #define LRFDDBELL_RIS2_PBE0_CLR 0x00000000U 5649 5650 //***************************************************************************** 5651 // 5652 // Register: LRFDDBELL_O_MIS2 5653 // 5654 //***************************************************************************** 5655 // Field: [31] SYSTIM2 5656 // 5657 // SYSTIM2 event 5658 // ENUMs: 5659 // SET Interrupt occurred 5660 // CLR Interrupt did not occur 5661 #define LRFDDBELL_MIS2_SYSTIM2 0x80000000U 5662 #define LRFDDBELL_MIS2_SYSTIM2_M 0x80000000U 5663 #define LRFDDBELL_MIS2_SYSTIM2_S 31U 5664 #define LRFDDBELL_MIS2_SYSTIM2_SET 0x80000000U 5665 #define LRFDDBELL_MIS2_SYSTIM2_CLR 0x00000000U 5666 5667 // Field: [30] SYSTIM1 5668 // 5669 // SYSTIM1 event 5670 // ENUMs: 5671 // SET Interrupt occurred 5672 // CLR Interrupt did not occur 5673 #define LRFDDBELL_MIS2_SYSTIM1 0x40000000U 5674 #define LRFDDBELL_MIS2_SYSTIM1_M 0x40000000U 5675 #define LRFDDBELL_MIS2_SYSTIM1_S 30U 5676 #define LRFDDBELL_MIS2_SYSTIM1_SET 0x40000000U 5677 #define LRFDDBELL_MIS2_SYSTIM1_CLR 0x00000000U 5678 5679 // Field: [29] SYSTIM0 5680 // 5681 // SYSTIM0 event 5682 // ENUMs: 5683 // SET Interrupt occurred 5684 // CLR Interrupt did not occur 5685 #define LRFDDBELL_MIS2_SYSTIM0 0x20000000U 5686 #define LRFDDBELL_MIS2_SYSTIM0_M 0x20000000U 5687 #define LRFDDBELL_MIS2_SYSTIM0_S 29U 5688 #define LRFDDBELL_MIS2_SYSTIM0_SET 0x20000000U 5689 #define LRFDDBELL_MIS2_SYSTIM0_CLR 0x00000000U 5690 5691 // Field: [28] MDMDONE 5692 // 5693 // MDMDONE event 5694 // ENUMs: 5695 // SET Interrupt occurred 5696 // CLR Interrupt did not occur 5697 #define LRFDDBELL_MIS2_MDMDONE 0x10000000U 5698 #define LRFDDBELL_MIS2_MDMDONE_M 0x10000000U 5699 #define LRFDDBELL_MIS2_MDMDONE_S 28U 5700 #define LRFDDBELL_MIS2_MDMDONE_SET 0x10000000U 5701 #define LRFDDBELL_MIS2_MDMDONE_CLR 0x00000000U 5702 5703 // Field: [27] MDMIN 5704 // 5705 // MDMIN event 5706 // ENUMs: 5707 // SET Interrupt occurred 5708 // CLR Interrupt did not occur 5709 #define LRFDDBELL_MIS2_MDMIN 0x08000000U 5710 #define LRFDDBELL_MIS2_MDMIN_M 0x08000000U 5711 #define LRFDDBELL_MIS2_MDMIN_S 27U 5712 #define LRFDDBELL_MIS2_MDMIN_SET 0x08000000U 5713 #define LRFDDBELL_MIS2_MDMIN_CLR 0x00000000U 5714 5715 // Field: [26] MDMOUT 5716 // 5717 // MDMOUT event 5718 // ENUMs: 5719 // SET Interrupt occurred 5720 // CLR Interrupt did not occur 5721 #define LRFDDBELL_MIS2_MDMOUT 0x04000000U 5722 #define LRFDDBELL_MIS2_MDMOUT_M 0x04000000U 5723 #define LRFDDBELL_MIS2_MDMOUT_S 26U 5724 #define LRFDDBELL_MIS2_MDMOUT_SET 0x04000000U 5725 #define LRFDDBELL_MIS2_MDMOUT_CLR 0x00000000U 5726 5727 // Field: [25] MDMSOFT2 5728 // 5729 // MDMSOFT event 5730 // ENUMs: 5731 // SET Interrupt occurred 5732 // CLR Interrupt did not occur 5733 #define LRFDDBELL_MIS2_MDMSOFT2 0x02000000U 5734 #define LRFDDBELL_MIS2_MDMSOFT2_M 0x02000000U 5735 #define LRFDDBELL_MIS2_MDMSOFT2_S 25U 5736 #define LRFDDBELL_MIS2_MDMSOFT2_SET 0x02000000U 5737 #define LRFDDBELL_MIS2_MDMSOFT2_CLR 0x00000000U 5738 5739 // Field: [24] MDMSOFT1 5740 // 5741 // MDMSOFT1 event 5742 // ENUMs: 5743 // SET Interrupt occurred 5744 // CLR Interrupt did not occur 5745 #define LRFDDBELL_MIS2_MDMSOFT1 0x01000000U 5746 #define LRFDDBELL_MIS2_MDMSOFT1_M 0x01000000U 5747 #define LRFDDBELL_MIS2_MDMSOFT1_S 24U 5748 #define LRFDDBELL_MIS2_MDMSOFT1_SET 0x01000000U 5749 #define LRFDDBELL_MIS2_MDMSOFT1_CLR 0x00000000U 5750 5751 // Field: [23] MDMSOFT0 5752 // 5753 // MDMSOFT event 5754 // ENUMs: 5755 // SET Interrupt occurred 5756 // CLR Interrupt did not occur 5757 #define LRFDDBELL_MIS2_MDMSOFT0 0x00800000U 5758 #define LRFDDBELL_MIS2_MDMSOFT0_M 0x00800000U 5759 #define LRFDDBELL_MIS2_MDMSOFT0_S 23U 5760 #define LRFDDBELL_MIS2_MDMSOFT0_SET 0x00800000U 5761 #define LRFDDBELL_MIS2_MDMSOFT0_CLR 0x00000000U 5762 5763 // Field: [22] RFEDONE 5764 // 5765 // RFEDONE event 5766 // ENUMs: 5767 // SET Interrupt occurred 5768 // CLR Interrupt did not occur 5769 #define LRFDDBELL_MIS2_RFEDONE 0x00400000U 5770 #define LRFDDBELL_MIS2_RFEDONE_M 0x00400000U 5771 #define LRFDDBELL_MIS2_RFEDONE_S 22U 5772 #define LRFDDBELL_MIS2_RFEDONE_SET 0x00400000U 5773 #define LRFDDBELL_MIS2_RFEDONE_CLR 0x00000000U 5774 5775 // Field: [21] RFESOFT1 5776 // 5777 // RFESOFT1 event 5778 // ENUMs: 5779 // SET Interrupt occurred 5780 // CLR Interrupt did not occur 5781 #define LRFDDBELL_MIS2_RFESOFT1 0x00200000U 5782 #define LRFDDBELL_MIS2_RFESOFT1_M 0x00200000U 5783 #define LRFDDBELL_MIS2_RFESOFT1_S 21U 5784 #define LRFDDBELL_MIS2_RFESOFT1_SET 0x00200000U 5785 #define LRFDDBELL_MIS2_RFESOFT1_CLR 0x00000000U 5786 5787 // Field: [20] RFESOFT0 5788 // 5789 // RFESOFT0 event 5790 // ENUMs: 5791 // SET Interrupt occurred 5792 // CLR Interrupt did not occur 5793 #define LRFDDBELL_MIS2_RFESOFT0 0x00100000U 5794 #define LRFDDBELL_MIS2_RFESOFT0_M 0x00100000U 5795 #define LRFDDBELL_MIS2_RFESOFT0_S 20U 5796 #define LRFDDBELL_MIS2_RFESOFT0_SET 0x00100000U 5797 #define LRFDDBELL_MIS2_RFESOFT0_CLR 0x00000000U 5798 5799 // Field: [19] LOCK 5800 // 5801 // LOCK event 5802 // ENUMs: 5803 // SET Interrupt occurred 5804 // CLR Interrupt did not occur 5805 #define LRFDDBELL_MIS2_LOCK 0x00080000U 5806 #define LRFDDBELL_MIS2_LOCK_M 0x00080000U 5807 #define LRFDDBELL_MIS2_LOCK_S 19U 5808 #define LRFDDBELL_MIS2_LOCK_SET 0x00080000U 5809 #define LRFDDBELL_MIS2_LOCK_CLR 0x00000000U 5810 5811 // Field: [18] LOL 5812 // 5813 // LOSS_OF_LOCK event 5814 // ENUMs: 5815 // SET Interrupt occurred 5816 // CLR Interrupt did not occur 5817 #define LRFDDBELL_MIS2_LOL 0x00040000U 5818 #define LRFDDBELL_MIS2_LOL_M 0x00040000U 5819 #define LRFDDBELL_MIS2_LOL_S 18U 5820 #define LRFDDBELL_MIS2_LOL_SET 0x00040000U 5821 #define LRFDDBELL_MIS2_LOL_CLR 0x00000000U 5822 5823 // Field: [17] TXFIFO 5824 // 5825 // TXFIFO event 5826 // ENUMs: 5827 // SET Interrupt occurred 5828 // CLR Interrupt did not occur 5829 #define LRFDDBELL_MIS2_TXFIFO 0x00020000U 5830 #define LRFDDBELL_MIS2_TXFIFO_M 0x00020000U 5831 #define LRFDDBELL_MIS2_TXFIFO_S 17U 5832 #define LRFDDBELL_MIS2_TXFIFO_SET 0x00020000U 5833 #define LRFDDBELL_MIS2_TXFIFO_CLR 0x00000000U 5834 5835 // Field: [16] RXFIFO 5836 // 5837 // RXFIFO event 5838 // ENUMs: 5839 // SET Interrupt occurred 5840 // CLR Interrupt did not occur 5841 #define LRFDDBELL_MIS2_RXFIFO 0x00010000U 5842 #define LRFDDBELL_MIS2_RXFIFO_M 0x00010000U 5843 #define LRFDDBELL_MIS2_RXFIFO_S 16U 5844 #define LRFDDBELL_MIS2_RXFIFO_SET 0x00010000U 5845 #define LRFDDBELL_MIS2_RXFIFO_CLR 0x00000000U 5846 5847 // Field: [15] PBE15 5848 // 5849 // PBE15 event 5850 // ENUMs: 5851 // SET Interrupt occurred 5852 // CLR Interrupt did not occur 5853 #define LRFDDBELL_MIS2_PBE15 0x00008000U 5854 #define LRFDDBELL_MIS2_PBE15_M 0x00008000U 5855 #define LRFDDBELL_MIS2_PBE15_S 15U 5856 #define LRFDDBELL_MIS2_PBE15_SET 0x00008000U 5857 #define LRFDDBELL_MIS2_PBE15_CLR 0x00000000U 5858 5859 // Field: [14] PBE14 5860 // 5861 // PBE14 event 5862 // ENUMs: 5863 // SET Interrupt occurred 5864 // CLR Interrupt did not occur 5865 #define LRFDDBELL_MIS2_PBE14 0x00004000U 5866 #define LRFDDBELL_MIS2_PBE14_M 0x00004000U 5867 #define LRFDDBELL_MIS2_PBE14_S 14U 5868 #define LRFDDBELL_MIS2_PBE14_SET 0x00004000U 5869 #define LRFDDBELL_MIS2_PBE14_CLR 0x00000000U 5870 5871 // Field: [13] PBE13 5872 // 5873 // PBE13 event 5874 // ENUMs: 5875 // SET Interrupt occurred 5876 // CLR Interrupt did not occur 5877 #define LRFDDBELL_MIS2_PBE13 0x00002000U 5878 #define LRFDDBELL_MIS2_PBE13_M 0x00002000U 5879 #define LRFDDBELL_MIS2_PBE13_S 13U 5880 #define LRFDDBELL_MIS2_PBE13_SET 0x00002000U 5881 #define LRFDDBELL_MIS2_PBE13_CLR 0x00000000U 5882 5883 // Field: [12] PBE12 5884 // 5885 // PBE12 event 5886 // ENUMs: 5887 // SET Interrupt occurred 5888 // CLR Interrupt did not occur 5889 #define LRFDDBELL_MIS2_PBE12 0x00001000U 5890 #define LRFDDBELL_MIS2_PBE12_M 0x00001000U 5891 #define LRFDDBELL_MIS2_PBE12_S 12U 5892 #define LRFDDBELL_MIS2_PBE12_SET 0x00001000U 5893 #define LRFDDBELL_MIS2_PBE12_CLR 0x00000000U 5894 5895 // Field: [11] PBE11 5896 // 5897 // PBE11 event 5898 // ENUMs: 5899 // SET Interrupt occurred 5900 // CLR Interrupt did not occur 5901 #define LRFDDBELL_MIS2_PBE11 0x00000800U 5902 #define LRFDDBELL_MIS2_PBE11_M 0x00000800U 5903 #define LRFDDBELL_MIS2_PBE11_S 11U 5904 #define LRFDDBELL_MIS2_PBE11_SET 0x00000800U 5905 #define LRFDDBELL_MIS2_PBE11_CLR 0x00000000U 5906 5907 // Field: [10] PBE10 5908 // 5909 // PBE10 event 5910 // ENUMs: 5911 // SET Interrupt occurred 5912 // CLR Interrupt did not occur 5913 #define LRFDDBELL_MIS2_PBE10 0x00000400U 5914 #define LRFDDBELL_MIS2_PBE10_M 0x00000400U 5915 #define LRFDDBELL_MIS2_PBE10_S 10U 5916 #define LRFDDBELL_MIS2_PBE10_SET 0x00000400U 5917 #define LRFDDBELL_MIS2_PBE10_CLR 0x00000000U 5918 5919 // Field: [9] PBE9 5920 // 5921 // PBE9 event 5922 // ENUMs: 5923 // SET Interrupt occurred 5924 // CLR Interrupt did not occur 5925 #define LRFDDBELL_MIS2_PBE9 0x00000200U 5926 #define LRFDDBELL_MIS2_PBE9_M 0x00000200U 5927 #define LRFDDBELL_MIS2_PBE9_S 9U 5928 #define LRFDDBELL_MIS2_PBE9_SET 0x00000200U 5929 #define LRFDDBELL_MIS2_PBE9_CLR 0x00000000U 5930 5931 // Field: [8] PBE8 5932 // 5933 // PBE8 event 5934 // ENUMs: 5935 // SET Interrupt occurred 5936 // CLR Interrupt did not occur 5937 #define LRFDDBELL_MIS2_PBE8 0x00000100U 5938 #define LRFDDBELL_MIS2_PBE8_M 0x00000100U 5939 #define LRFDDBELL_MIS2_PBE8_S 8U 5940 #define LRFDDBELL_MIS2_PBE8_SET 0x00000100U 5941 #define LRFDDBELL_MIS2_PBE8_CLR 0x00000000U 5942 5943 // Field: [7] PBE7 5944 // 5945 // PBE7 event 5946 // ENUMs: 5947 // SET Interrupt occurred 5948 // CLR Interrupt did not occur 5949 #define LRFDDBELL_MIS2_PBE7 0x00000080U 5950 #define LRFDDBELL_MIS2_PBE7_M 0x00000080U 5951 #define LRFDDBELL_MIS2_PBE7_S 7U 5952 #define LRFDDBELL_MIS2_PBE7_SET 0x00000080U 5953 #define LRFDDBELL_MIS2_PBE7_CLR 0x00000000U 5954 5955 // Field: [6] PBE6 5956 // 5957 // PBE6 event 5958 // ENUMs: 5959 // SET Interrupt occurred 5960 // CLR Interrupt did not occur 5961 #define LRFDDBELL_MIS2_PBE6 0x00000040U 5962 #define LRFDDBELL_MIS2_PBE6_M 0x00000040U 5963 #define LRFDDBELL_MIS2_PBE6_S 6U 5964 #define LRFDDBELL_MIS2_PBE6_SET 0x00000040U 5965 #define LRFDDBELL_MIS2_PBE6_CLR 0x00000000U 5966 5967 // Field: [5] PBE5 5968 // 5969 // PBE5 event 5970 // ENUMs: 5971 // SET Interrupt occurred 5972 // CLR Interrupt did not occur 5973 #define LRFDDBELL_MIS2_PBE5 0x00000020U 5974 #define LRFDDBELL_MIS2_PBE5_M 0x00000020U 5975 #define LRFDDBELL_MIS2_PBE5_S 5U 5976 #define LRFDDBELL_MIS2_PBE5_SET 0x00000020U 5977 #define LRFDDBELL_MIS2_PBE5_CLR 0x00000000U 5978 5979 // Field: [4] PBE4 5980 // 5981 // PBE4 event 5982 // ENUMs: 5983 // SET Interrupt occurred 5984 // CLR Interrupt did not occur 5985 #define LRFDDBELL_MIS2_PBE4 0x00000010U 5986 #define LRFDDBELL_MIS2_PBE4_M 0x00000010U 5987 #define LRFDDBELL_MIS2_PBE4_S 4U 5988 #define LRFDDBELL_MIS2_PBE4_SET 0x00000010U 5989 #define LRFDDBELL_MIS2_PBE4_CLR 0x00000000U 5990 5991 // Field: [3] PBE3 5992 // 5993 // PBE3 event 5994 // ENUMs: 5995 // SET Interrupt occurred 5996 // CLR Interrupt did not occur 5997 #define LRFDDBELL_MIS2_PBE3 0x00000008U 5998 #define LRFDDBELL_MIS2_PBE3_M 0x00000008U 5999 #define LRFDDBELL_MIS2_PBE3_S 3U 6000 #define LRFDDBELL_MIS2_PBE3_SET 0x00000008U 6001 #define LRFDDBELL_MIS2_PBE3_CLR 0x00000000U 6002 6003 // Field: [2] PBE2 6004 // 6005 // PBE2 event 6006 // ENUMs: 6007 // SET Interrupt occurred 6008 // CLR Interrupt did not occur 6009 #define LRFDDBELL_MIS2_PBE2 0x00000004U 6010 #define LRFDDBELL_MIS2_PBE2_M 0x00000004U 6011 #define LRFDDBELL_MIS2_PBE2_S 2U 6012 #define LRFDDBELL_MIS2_PBE2_SET 0x00000004U 6013 #define LRFDDBELL_MIS2_PBE2_CLR 0x00000000U 6014 6015 // Field: [1] PBE1 6016 // 6017 // PBE1 event 6018 // ENUMs: 6019 // SET Interrupt occurred 6020 // CLR Interrupt did not occur 6021 #define LRFDDBELL_MIS2_PBE1 0x00000002U 6022 #define LRFDDBELL_MIS2_PBE1_M 0x00000002U 6023 #define LRFDDBELL_MIS2_PBE1_S 1U 6024 #define LRFDDBELL_MIS2_PBE1_SET 0x00000002U 6025 #define LRFDDBELL_MIS2_PBE1_CLR 0x00000000U 6026 6027 // Field: [0] PBE0 6028 // 6029 // PBE0 event 6030 // ENUMs: 6031 // SET Interrupt occurred 6032 // CLR Interrupt did not occur 6033 #define LRFDDBELL_MIS2_PBE0 0x00000001U 6034 #define LRFDDBELL_MIS2_PBE0_M 0x00000001U 6035 #define LRFDDBELL_MIS2_PBE0_S 0U 6036 #define LRFDDBELL_MIS2_PBE0_SET 0x00000001U 6037 #define LRFDDBELL_MIS2_PBE0_CLR 0x00000000U 6038 6039 //***************************************************************************** 6040 // 6041 // Register: LRFDDBELL_O_ISET2 6042 // 6043 //***************************************************************************** 6044 // Field: [31] SYSTIM2 6045 // 6046 // SYSTIM2 event 6047 // ENUMs: 6048 // SET Set Interrupt 6049 // NOEFF Writing 0 has no effect 6050 #define LRFDDBELL_ISET2_SYSTIM2 0x80000000U 6051 #define LRFDDBELL_ISET2_SYSTIM2_M 0x80000000U 6052 #define LRFDDBELL_ISET2_SYSTIM2_S 31U 6053 #define LRFDDBELL_ISET2_SYSTIM2_SET 0x80000000U 6054 #define LRFDDBELL_ISET2_SYSTIM2_NOEFF 0x00000000U 6055 6056 // Field: [30] SYSTIM1 6057 // 6058 // SYSTIM1 event 6059 // ENUMs: 6060 // SET Set Interrupt 6061 // NOEFF Writing 0 has no effect 6062 #define LRFDDBELL_ISET2_SYSTIM1 0x40000000U 6063 #define LRFDDBELL_ISET2_SYSTIM1_M 0x40000000U 6064 #define LRFDDBELL_ISET2_SYSTIM1_S 30U 6065 #define LRFDDBELL_ISET2_SYSTIM1_SET 0x40000000U 6066 #define LRFDDBELL_ISET2_SYSTIM1_NOEFF 0x00000000U 6067 6068 // Field: [29] SYSTIM0 6069 // 6070 // SYSTIM0 event 6071 // ENUMs: 6072 // SET Set Interrupt 6073 // NOEFF Writing 0 has no effect 6074 #define LRFDDBELL_ISET2_SYSTIM0 0x20000000U 6075 #define LRFDDBELL_ISET2_SYSTIM0_M 0x20000000U 6076 #define LRFDDBELL_ISET2_SYSTIM0_S 29U 6077 #define LRFDDBELL_ISET2_SYSTIM0_SET 0x20000000U 6078 #define LRFDDBELL_ISET2_SYSTIM0_NOEFF 0x00000000U 6079 6080 // Field: [28] MDMDONE 6081 // 6082 // MDMDONE event 6083 // ENUMs: 6084 // SET Set Interrupt 6085 // NOEFF Writing 0 has no effect 6086 #define LRFDDBELL_ISET2_MDMDONE 0x10000000U 6087 #define LRFDDBELL_ISET2_MDMDONE_M 0x10000000U 6088 #define LRFDDBELL_ISET2_MDMDONE_S 28U 6089 #define LRFDDBELL_ISET2_MDMDONE_SET 0x10000000U 6090 #define LRFDDBELL_ISET2_MDMDONE_NOEFF 0x00000000U 6091 6092 // Field: [27] MDMIN 6093 // 6094 // MDMIN event 6095 // ENUMs: 6096 // SET Set Interrupt 6097 // NOEFF Writing 0 has no effect 6098 #define LRFDDBELL_ISET2_MDMIN 0x08000000U 6099 #define LRFDDBELL_ISET2_MDMIN_M 0x08000000U 6100 #define LRFDDBELL_ISET2_MDMIN_S 27U 6101 #define LRFDDBELL_ISET2_MDMIN_SET 0x08000000U 6102 #define LRFDDBELL_ISET2_MDMIN_NOEFF 0x00000000U 6103 6104 // Field: [26] MDMOUT 6105 // 6106 // MDMOUT event 6107 // ENUMs: 6108 // SET Set Interrupt 6109 // NOEFF Writing 0 has no effect 6110 #define LRFDDBELL_ISET2_MDMOUT 0x04000000U 6111 #define LRFDDBELL_ISET2_MDMOUT_M 0x04000000U 6112 #define LRFDDBELL_ISET2_MDMOUT_S 26U 6113 #define LRFDDBELL_ISET2_MDMOUT_SET 0x04000000U 6114 #define LRFDDBELL_ISET2_MDMOUT_NOEFF 0x00000000U 6115 6116 // Field: [25] MDMSOFT2 6117 // 6118 // MDMSOFT event 6119 // ENUMs: 6120 // SET Set Interrupt 6121 // NOEFF Writing 0 has no effect 6122 #define LRFDDBELL_ISET2_MDMSOFT2 0x02000000U 6123 #define LRFDDBELL_ISET2_MDMSOFT2_M 0x02000000U 6124 #define LRFDDBELL_ISET2_MDMSOFT2_S 25U 6125 #define LRFDDBELL_ISET2_MDMSOFT2_SET 0x02000000U 6126 #define LRFDDBELL_ISET2_MDMSOFT2_NOEFF 0x00000000U 6127 6128 // Field: [24] MDMSOFT1 6129 // 6130 // MDMSOFT1 event 6131 // ENUMs: 6132 // SET Set Interrupt 6133 // NOEFF Writing 0 has no effect 6134 #define LRFDDBELL_ISET2_MDMSOFT1 0x01000000U 6135 #define LRFDDBELL_ISET2_MDMSOFT1_M 0x01000000U 6136 #define LRFDDBELL_ISET2_MDMSOFT1_S 24U 6137 #define LRFDDBELL_ISET2_MDMSOFT1_SET 0x01000000U 6138 #define LRFDDBELL_ISET2_MDMSOFT1_NOEFF 0x00000000U 6139 6140 // Field: [23] MDMSOFT0 6141 // 6142 // MDMSOFT event 6143 // ENUMs: 6144 // SET Set Interrupt 6145 // NOEFF Writing 0 has no effect 6146 #define LRFDDBELL_ISET2_MDMSOFT0 0x00800000U 6147 #define LRFDDBELL_ISET2_MDMSOFT0_M 0x00800000U 6148 #define LRFDDBELL_ISET2_MDMSOFT0_S 23U 6149 #define LRFDDBELL_ISET2_MDMSOFT0_SET 0x00800000U 6150 #define LRFDDBELL_ISET2_MDMSOFT0_NOEFF 0x00000000U 6151 6152 // Field: [22] RFEDONE 6153 // 6154 // RFEDONE event 6155 // ENUMs: 6156 // SET Set Interrupt 6157 // NOEFF Writing 0 has no effect 6158 #define LRFDDBELL_ISET2_RFEDONE 0x00400000U 6159 #define LRFDDBELL_ISET2_RFEDONE_M 0x00400000U 6160 #define LRFDDBELL_ISET2_RFEDONE_S 22U 6161 #define LRFDDBELL_ISET2_RFEDONE_SET 0x00400000U 6162 #define LRFDDBELL_ISET2_RFEDONE_NOEFF 0x00000000U 6163 6164 // Field: [21] RFESOFT1 6165 // 6166 // RFESOFT1 event 6167 // ENUMs: 6168 // SET Set Interrupt 6169 // NOEFF Writing 0 has no effect 6170 #define LRFDDBELL_ISET2_RFESOFT1 0x00200000U 6171 #define LRFDDBELL_ISET2_RFESOFT1_M 0x00200000U 6172 #define LRFDDBELL_ISET2_RFESOFT1_S 21U 6173 #define LRFDDBELL_ISET2_RFESOFT1_SET 0x00200000U 6174 #define LRFDDBELL_ISET2_RFESOFT1_NOEFF 0x00000000U 6175 6176 // Field: [20] RFESOFT0 6177 // 6178 // RFESOFT0 event 6179 // ENUMs: 6180 // SET Set Interrupt 6181 // NOEFF Writing 0 has no effect 6182 #define LRFDDBELL_ISET2_RFESOFT0 0x00100000U 6183 #define LRFDDBELL_ISET2_RFESOFT0_M 0x00100000U 6184 #define LRFDDBELL_ISET2_RFESOFT0_S 20U 6185 #define LRFDDBELL_ISET2_RFESOFT0_SET 0x00100000U 6186 #define LRFDDBELL_ISET2_RFESOFT0_NOEFF 0x00000000U 6187 6188 // Field: [19] LOCK 6189 // 6190 // LOCK event 6191 // ENUMs: 6192 // SET Set Interrupt 6193 // NOEFF Writing 0 has no effect 6194 #define LRFDDBELL_ISET2_LOCK 0x00080000U 6195 #define LRFDDBELL_ISET2_LOCK_M 0x00080000U 6196 #define LRFDDBELL_ISET2_LOCK_S 19U 6197 #define LRFDDBELL_ISET2_LOCK_SET 0x00080000U 6198 #define LRFDDBELL_ISET2_LOCK_NOEFF 0x00000000U 6199 6200 // Field: [18] LOL 6201 // 6202 // LOSS_OF_LOCK event 6203 // ENUMs: 6204 // SET Set Interrupt 6205 // NOEFF Writing 0 has no effect 6206 #define LRFDDBELL_ISET2_LOL 0x00040000U 6207 #define LRFDDBELL_ISET2_LOL_M 0x00040000U 6208 #define LRFDDBELL_ISET2_LOL_S 18U 6209 #define LRFDDBELL_ISET2_LOL_SET 0x00040000U 6210 #define LRFDDBELL_ISET2_LOL_NOEFF 0x00000000U 6211 6212 // Field: [17] TXFIFO 6213 // 6214 // TXFIFO event 6215 // ENUMs: 6216 // SET Set Interrupt 6217 // NOEFF Writing 0 has no effect 6218 #define LRFDDBELL_ISET2_TXFIFO 0x00020000U 6219 #define LRFDDBELL_ISET2_TXFIFO_M 0x00020000U 6220 #define LRFDDBELL_ISET2_TXFIFO_S 17U 6221 #define LRFDDBELL_ISET2_TXFIFO_SET 0x00020000U 6222 #define LRFDDBELL_ISET2_TXFIFO_NOEFF 0x00000000U 6223 6224 // Field: [16] RXFIFO 6225 // 6226 // RXFIFO event 6227 // ENUMs: 6228 // SET Set Interrupt 6229 // NOEFF Writing 0 has no effect 6230 #define LRFDDBELL_ISET2_RXFIFO 0x00010000U 6231 #define LRFDDBELL_ISET2_RXFIFO_M 0x00010000U 6232 #define LRFDDBELL_ISET2_RXFIFO_S 16U 6233 #define LRFDDBELL_ISET2_RXFIFO_SET 0x00010000U 6234 #define LRFDDBELL_ISET2_RXFIFO_NOEFF 0x00000000U 6235 6236 // Field: [15] PBE15 6237 // 6238 // PBE15 event 6239 // ENUMs: 6240 // SET Set Interrupt 6241 // NOEFF Writing 0 has no effect 6242 #define LRFDDBELL_ISET2_PBE15 0x00008000U 6243 #define LRFDDBELL_ISET2_PBE15_M 0x00008000U 6244 #define LRFDDBELL_ISET2_PBE15_S 15U 6245 #define LRFDDBELL_ISET2_PBE15_SET 0x00008000U 6246 #define LRFDDBELL_ISET2_PBE15_NOEFF 0x00000000U 6247 6248 // Field: [14] PBE14 6249 // 6250 // PBE14 event 6251 // ENUMs: 6252 // SET Set Interrupt 6253 // NOEFF Writing 0 has no effect 6254 #define LRFDDBELL_ISET2_PBE14 0x00004000U 6255 #define LRFDDBELL_ISET2_PBE14_M 0x00004000U 6256 #define LRFDDBELL_ISET2_PBE14_S 14U 6257 #define LRFDDBELL_ISET2_PBE14_SET 0x00004000U 6258 #define LRFDDBELL_ISET2_PBE14_NOEFF 0x00000000U 6259 6260 // Field: [13] PBE13 6261 // 6262 // PBE13 event 6263 // ENUMs: 6264 // SET Set Interrupt 6265 // NOEFF Writing 0 has no effect 6266 #define LRFDDBELL_ISET2_PBE13 0x00002000U 6267 #define LRFDDBELL_ISET2_PBE13_M 0x00002000U 6268 #define LRFDDBELL_ISET2_PBE13_S 13U 6269 #define LRFDDBELL_ISET2_PBE13_SET 0x00002000U 6270 #define LRFDDBELL_ISET2_PBE13_NOEFF 0x00000000U 6271 6272 // Field: [12] PBE12 6273 // 6274 // PBE12 event 6275 // ENUMs: 6276 // SET Set Interrupt 6277 // NOEFF Writing 0 has no effect 6278 #define LRFDDBELL_ISET2_PBE12 0x00001000U 6279 #define LRFDDBELL_ISET2_PBE12_M 0x00001000U 6280 #define LRFDDBELL_ISET2_PBE12_S 12U 6281 #define LRFDDBELL_ISET2_PBE12_SET 0x00001000U 6282 #define LRFDDBELL_ISET2_PBE12_NOEFF 0x00000000U 6283 6284 // Field: [11] PBE11 6285 // 6286 // PBE11 event 6287 // ENUMs: 6288 // SET Set Interrupt 6289 // NOEFF Writing 0 has no effect 6290 #define LRFDDBELL_ISET2_PBE11 0x00000800U 6291 #define LRFDDBELL_ISET2_PBE11_M 0x00000800U 6292 #define LRFDDBELL_ISET2_PBE11_S 11U 6293 #define LRFDDBELL_ISET2_PBE11_SET 0x00000800U 6294 #define LRFDDBELL_ISET2_PBE11_NOEFF 0x00000000U 6295 6296 // Field: [10] PBE10 6297 // 6298 // PBE10 event 6299 // ENUMs: 6300 // SET Set Interrupt 6301 // NOEFF Writing 0 has no effect 6302 #define LRFDDBELL_ISET2_PBE10 0x00000400U 6303 #define LRFDDBELL_ISET2_PBE10_M 0x00000400U 6304 #define LRFDDBELL_ISET2_PBE10_S 10U 6305 #define LRFDDBELL_ISET2_PBE10_SET 0x00000400U 6306 #define LRFDDBELL_ISET2_PBE10_NOEFF 0x00000000U 6307 6308 // Field: [9] PBE9 6309 // 6310 // PBE9 event 6311 // ENUMs: 6312 // SET Set Interrupt 6313 // NOEFF Writing 0 has no effect 6314 #define LRFDDBELL_ISET2_PBE9 0x00000200U 6315 #define LRFDDBELL_ISET2_PBE9_M 0x00000200U 6316 #define LRFDDBELL_ISET2_PBE9_S 9U 6317 #define LRFDDBELL_ISET2_PBE9_SET 0x00000200U 6318 #define LRFDDBELL_ISET2_PBE9_NOEFF 0x00000000U 6319 6320 // Field: [8] PBE8 6321 // 6322 // PBE8 event 6323 // ENUMs: 6324 // SET Set Interrupt 6325 // NOEFF Writing 0 has no effect 6326 #define LRFDDBELL_ISET2_PBE8 0x00000100U 6327 #define LRFDDBELL_ISET2_PBE8_M 0x00000100U 6328 #define LRFDDBELL_ISET2_PBE8_S 8U 6329 #define LRFDDBELL_ISET2_PBE8_SET 0x00000100U 6330 #define LRFDDBELL_ISET2_PBE8_NOEFF 0x00000000U 6331 6332 // Field: [7] PBE7 6333 // 6334 // PBE7 event 6335 // ENUMs: 6336 // SET Set Interrupt 6337 // NOEFF Writing 0 has no effect 6338 #define LRFDDBELL_ISET2_PBE7 0x00000080U 6339 #define LRFDDBELL_ISET2_PBE7_M 0x00000080U 6340 #define LRFDDBELL_ISET2_PBE7_S 7U 6341 #define LRFDDBELL_ISET2_PBE7_SET 0x00000080U 6342 #define LRFDDBELL_ISET2_PBE7_NOEFF 0x00000000U 6343 6344 // Field: [6] PBE6 6345 // 6346 // PBE6 event 6347 // ENUMs: 6348 // SET Set Interrupt 6349 // NOEFF Writing 0 has no effect 6350 #define LRFDDBELL_ISET2_PBE6 0x00000040U 6351 #define LRFDDBELL_ISET2_PBE6_M 0x00000040U 6352 #define LRFDDBELL_ISET2_PBE6_S 6U 6353 #define LRFDDBELL_ISET2_PBE6_SET 0x00000040U 6354 #define LRFDDBELL_ISET2_PBE6_NOEFF 0x00000000U 6355 6356 // Field: [5] PBE5 6357 // 6358 // PBE5 event 6359 // ENUMs: 6360 // SET Set Interrupt 6361 // NOEFF Writing 0 has no effect 6362 #define LRFDDBELL_ISET2_PBE5 0x00000020U 6363 #define LRFDDBELL_ISET2_PBE5_M 0x00000020U 6364 #define LRFDDBELL_ISET2_PBE5_S 5U 6365 #define LRFDDBELL_ISET2_PBE5_SET 0x00000020U 6366 #define LRFDDBELL_ISET2_PBE5_NOEFF 0x00000000U 6367 6368 // Field: [4] PBE4 6369 // 6370 // PBE4 event 6371 // ENUMs: 6372 // SET Set Interrupt 6373 // NOEFF Writing 0 has no effect 6374 #define LRFDDBELL_ISET2_PBE4 0x00000010U 6375 #define LRFDDBELL_ISET2_PBE4_M 0x00000010U 6376 #define LRFDDBELL_ISET2_PBE4_S 4U 6377 #define LRFDDBELL_ISET2_PBE4_SET 0x00000010U 6378 #define LRFDDBELL_ISET2_PBE4_NOEFF 0x00000000U 6379 6380 // Field: [3] PBE3 6381 // 6382 // PBE3 event 6383 // ENUMs: 6384 // SET Set Interrupt 6385 // NOEFF Writing 0 has no effect 6386 #define LRFDDBELL_ISET2_PBE3 0x00000008U 6387 #define LRFDDBELL_ISET2_PBE3_M 0x00000008U 6388 #define LRFDDBELL_ISET2_PBE3_S 3U 6389 #define LRFDDBELL_ISET2_PBE3_SET 0x00000008U 6390 #define LRFDDBELL_ISET2_PBE3_NOEFF 0x00000000U 6391 6392 // Field: [2] PBE2 6393 // 6394 // PBE2 event 6395 // ENUMs: 6396 // SET Set Interrupt 6397 // NOEFF Writing 0 has no effect 6398 #define LRFDDBELL_ISET2_PBE2 0x00000004U 6399 #define LRFDDBELL_ISET2_PBE2_M 0x00000004U 6400 #define LRFDDBELL_ISET2_PBE2_S 2U 6401 #define LRFDDBELL_ISET2_PBE2_SET 0x00000004U 6402 #define LRFDDBELL_ISET2_PBE2_NOEFF 0x00000000U 6403 6404 // Field: [1] PBE1 6405 // 6406 // PBE1 event 6407 // ENUMs: 6408 // SET Set Interrupt 6409 // NOEFF Writing 0 has no effect 6410 #define LRFDDBELL_ISET2_PBE1 0x00000002U 6411 #define LRFDDBELL_ISET2_PBE1_M 0x00000002U 6412 #define LRFDDBELL_ISET2_PBE1_S 1U 6413 #define LRFDDBELL_ISET2_PBE1_SET 0x00000002U 6414 #define LRFDDBELL_ISET2_PBE1_NOEFF 0x00000000U 6415 6416 // Field: [0] PBE0 6417 // 6418 // PBE0 event 6419 // ENUMs: 6420 // SET Set Interrupt 6421 // NOEFF Writing 0 has no effect 6422 #define LRFDDBELL_ISET2_PBE0 0x00000001U 6423 #define LRFDDBELL_ISET2_PBE0_M 0x00000001U 6424 #define LRFDDBELL_ISET2_PBE0_S 0U 6425 #define LRFDDBELL_ISET2_PBE0_SET 0x00000001U 6426 #define LRFDDBELL_ISET2_PBE0_NOEFF 0x00000000U 6427 6428 //***************************************************************************** 6429 // 6430 // Register: LRFDDBELL_O_ICLR2 6431 // 6432 //***************************************************************************** 6433 // Field: [31] SYSTIM2 6434 // 6435 // SYSTIM2 event 6436 // ENUMs: 6437 // CLR Clear Interrupt 6438 // NOEFF Writing 0 has no effect 6439 #define LRFDDBELL_ICLR2_SYSTIM2 0x80000000U 6440 #define LRFDDBELL_ICLR2_SYSTIM2_M 0x80000000U 6441 #define LRFDDBELL_ICLR2_SYSTIM2_S 31U 6442 #define LRFDDBELL_ICLR2_SYSTIM2_CLR 0x80000000U 6443 #define LRFDDBELL_ICLR2_SYSTIM2_NOEFF 0x00000000U 6444 6445 // Field: [30] SYSTIM1 6446 // 6447 // SYSTIM1 event 6448 // ENUMs: 6449 // CLR Clear Interrupt 6450 // NOEFF Writing 0 has no effect 6451 #define LRFDDBELL_ICLR2_SYSTIM1 0x40000000U 6452 #define LRFDDBELL_ICLR2_SYSTIM1_M 0x40000000U 6453 #define LRFDDBELL_ICLR2_SYSTIM1_S 30U 6454 #define LRFDDBELL_ICLR2_SYSTIM1_CLR 0x40000000U 6455 #define LRFDDBELL_ICLR2_SYSTIM1_NOEFF 0x00000000U 6456 6457 // Field: [29] SYSTIM0 6458 // 6459 // SYSTIM0 event 6460 // ENUMs: 6461 // CLR Clear Interrupt 6462 // NOEFF Writing 0 has no effect 6463 #define LRFDDBELL_ICLR2_SYSTIM0 0x20000000U 6464 #define LRFDDBELL_ICLR2_SYSTIM0_M 0x20000000U 6465 #define LRFDDBELL_ICLR2_SYSTIM0_S 29U 6466 #define LRFDDBELL_ICLR2_SYSTIM0_CLR 0x20000000U 6467 #define LRFDDBELL_ICLR2_SYSTIM0_NOEFF 0x00000000U 6468 6469 // Field: [28] MDMDONE 6470 // 6471 // MDMDONE event 6472 // ENUMs: 6473 // CLR Clear Interrupt 6474 // NOEFF Writing 0 has no effect 6475 #define LRFDDBELL_ICLR2_MDMDONE 0x10000000U 6476 #define LRFDDBELL_ICLR2_MDMDONE_M 0x10000000U 6477 #define LRFDDBELL_ICLR2_MDMDONE_S 28U 6478 #define LRFDDBELL_ICLR2_MDMDONE_CLR 0x10000000U 6479 #define LRFDDBELL_ICLR2_MDMDONE_NOEFF 0x00000000U 6480 6481 // Field: [27] MDMIN 6482 // 6483 // MDMIN event 6484 // ENUMs: 6485 // CLR Clear Interrupt 6486 // NOEFF Writing 0 has no effect 6487 #define LRFDDBELL_ICLR2_MDMIN 0x08000000U 6488 #define LRFDDBELL_ICLR2_MDMIN_M 0x08000000U 6489 #define LRFDDBELL_ICLR2_MDMIN_S 27U 6490 #define LRFDDBELL_ICLR2_MDMIN_CLR 0x08000000U 6491 #define LRFDDBELL_ICLR2_MDMIN_NOEFF 0x00000000U 6492 6493 // Field: [26] MDMOUT 6494 // 6495 // MDMOUT event 6496 // ENUMs: 6497 // CLR Clear Interrupt 6498 // NOEFF Writing 0 has no effect 6499 #define LRFDDBELL_ICLR2_MDMOUT 0x04000000U 6500 #define LRFDDBELL_ICLR2_MDMOUT_M 0x04000000U 6501 #define LRFDDBELL_ICLR2_MDMOUT_S 26U 6502 #define LRFDDBELL_ICLR2_MDMOUT_CLR 0x04000000U 6503 #define LRFDDBELL_ICLR2_MDMOUT_NOEFF 0x00000000U 6504 6505 // Field: [25] MDMSOFT2 6506 // 6507 // MDMSOFT event 6508 // ENUMs: 6509 // CLR Clear Interrupt 6510 // NOEFF Writing 0 has no effect 6511 #define LRFDDBELL_ICLR2_MDMSOFT2 0x02000000U 6512 #define LRFDDBELL_ICLR2_MDMSOFT2_M 0x02000000U 6513 #define LRFDDBELL_ICLR2_MDMSOFT2_S 25U 6514 #define LRFDDBELL_ICLR2_MDMSOFT2_CLR 0x02000000U 6515 #define LRFDDBELL_ICLR2_MDMSOFT2_NOEFF 0x00000000U 6516 6517 // Field: [24] MDMSOFT1 6518 // 6519 // MDMSOFT1 event 6520 // ENUMs: 6521 // CLR Clear Interrupt 6522 // NOEFF Writing 0 has no effect 6523 #define LRFDDBELL_ICLR2_MDMSOFT1 0x01000000U 6524 #define LRFDDBELL_ICLR2_MDMSOFT1_M 0x01000000U 6525 #define LRFDDBELL_ICLR2_MDMSOFT1_S 24U 6526 #define LRFDDBELL_ICLR2_MDMSOFT1_CLR 0x01000000U 6527 #define LRFDDBELL_ICLR2_MDMSOFT1_NOEFF 0x00000000U 6528 6529 // Field: [23] MDMSOFT0 6530 // 6531 // MDMSOFT event 6532 // ENUMs: 6533 // CLR Clear Interrupt 6534 // NOEFF Writing 0 has no effect 6535 #define LRFDDBELL_ICLR2_MDMSOFT0 0x00800000U 6536 #define LRFDDBELL_ICLR2_MDMSOFT0_M 0x00800000U 6537 #define LRFDDBELL_ICLR2_MDMSOFT0_S 23U 6538 #define LRFDDBELL_ICLR2_MDMSOFT0_CLR 0x00800000U 6539 #define LRFDDBELL_ICLR2_MDMSOFT0_NOEFF 0x00000000U 6540 6541 // Field: [22] RFEDONE 6542 // 6543 // RFEDONE event 6544 // ENUMs: 6545 // CLR Clear Interrupt 6546 // NOEFF Writing 0 has no effect 6547 #define LRFDDBELL_ICLR2_RFEDONE 0x00400000U 6548 #define LRFDDBELL_ICLR2_RFEDONE_M 0x00400000U 6549 #define LRFDDBELL_ICLR2_RFEDONE_S 22U 6550 #define LRFDDBELL_ICLR2_RFEDONE_CLR 0x00400000U 6551 #define LRFDDBELL_ICLR2_RFEDONE_NOEFF 0x00000000U 6552 6553 // Field: [21] RFESOFT1 6554 // 6555 // RFESOFT1 event 6556 // ENUMs: 6557 // CLR Clear Interrupt 6558 // NOEFF Writing 0 has no effect 6559 #define LRFDDBELL_ICLR2_RFESOFT1 0x00200000U 6560 #define LRFDDBELL_ICLR2_RFESOFT1_M 0x00200000U 6561 #define LRFDDBELL_ICLR2_RFESOFT1_S 21U 6562 #define LRFDDBELL_ICLR2_RFESOFT1_CLR 0x00200000U 6563 #define LRFDDBELL_ICLR2_RFESOFT1_NOEFF 0x00000000U 6564 6565 // Field: [20] RFESOFT0 6566 // 6567 // RFESOFT0 event 6568 // ENUMs: 6569 // CLR Clear Interrupt 6570 // NOEFF Writing 0 has no effect 6571 #define LRFDDBELL_ICLR2_RFESOFT0 0x00100000U 6572 #define LRFDDBELL_ICLR2_RFESOFT0_M 0x00100000U 6573 #define LRFDDBELL_ICLR2_RFESOFT0_S 20U 6574 #define LRFDDBELL_ICLR2_RFESOFT0_CLR 0x00100000U 6575 #define LRFDDBELL_ICLR2_RFESOFT0_NOEFF 0x00000000U 6576 6577 // Field: [19] LOCK 6578 // 6579 // LOCK event 6580 // ENUMs: 6581 // CLR Clear Interrupt 6582 // NOEFF Writing 0 has no effect 6583 #define LRFDDBELL_ICLR2_LOCK 0x00080000U 6584 #define LRFDDBELL_ICLR2_LOCK_M 0x00080000U 6585 #define LRFDDBELL_ICLR2_LOCK_S 19U 6586 #define LRFDDBELL_ICLR2_LOCK_CLR 0x00080000U 6587 #define LRFDDBELL_ICLR2_LOCK_NOEFF 0x00000000U 6588 6589 // Field: [18] LOL 6590 // 6591 // LOSS_OF_LOCK event 6592 // ENUMs: 6593 // CLR Clear Interrupt 6594 // NOEFF Writing 0 has no effect 6595 #define LRFDDBELL_ICLR2_LOL 0x00040000U 6596 #define LRFDDBELL_ICLR2_LOL_M 0x00040000U 6597 #define LRFDDBELL_ICLR2_LOL_S 18U 6598 #define LRFDDBELL_ICLR2_LOL_CLR 0x00040000U 6599 #define LRFDDBELL_ICLR2_LOL_NOEFF 0x00000000U 6600 6601 // Field: [17] TXFIFO 6602 // 6603 // TXFIFO event 6604 // ENUMs: 6605 // CLR Clear Interrupt 6606 // NOEFF Writing 0 has no effect 6607 #define LRFDDBELL_ICLR2_TXFIFO 0x00020000U 6608 #define LRFDDBELL_ICLR2_TXFIFO_M 0x00020000U 6609 #define LRFDDBELL_ICLR2_TXFIFO_S 17U 6610 #define LRFDDBELL_ICLR2_TXFIFO_CLR 0x00020000U 6611 #define LRFDDBELL_ICLR2_TXFIFO_NOEFF 0x00000000U 6612 6613 // Field: [16] RXFIFO 6614 // 6615 // RXFIFO event 6616 // ENUMs: 6617 // CLR Clear Interrupt 6618 // NOEFF Writing 0 has no effect 6619 #define LRFDDBELL_ICLR2_RXFIFO 0x00010000U 6620 #define LRFDDBELL_ICLR2_RXFIFO_M 0x00010000U 6621 #define LRFDDBELL_ICLR2_RXFIFO_S 16U 6622 #define LRFDDBELL_ICLR2_RXFIFO_CLR 0x00010000U 6623 #define LRFDDBELL_ICLR2_RXFIFO_NOEFF 0x00000000U 6624 6625 // Field: [15] PBE15 6626 // 6627 // PBE15 event 6628 // ENUMs: 6629 // CLR Clear Interrupt 6630 // NOEFF Writing 0 has no effect 6631 #define LRFDDBELL_ICLR2_PBE15 0x00008000U 6632 #define LRFDDBELL_ICLR2_PBE15_M 0x00008000U 6633 #define LRFDDBELL_ICLR2_PBE15_S 15U 6634 #define LRFDDBELL_ICLR2_PBE15_CLR 0x00008000U 6635 #define LRFDDBELL_ICLR2_PBE15_NOEFF 0x00000000U 6636 6637 // Field: [14] PBE14 6638 // 6639 // PBE14 event 6640 // ENUMs: 6641 // CLR Clear Interrupt 6642 // NOEFF Writing 0 has no effect 6643 #define LRFDDBELL_ICLR2_PBE14 0x00004000U 6644 #define LRFDDBELL_ICLR2_PBE14_M 0x00004000U 6645 #define LRFDDBELL_ICLR2_PBE14_S 14U 6646 #define LRFDDBELL_ICLR2_PBE14_CLR 0x00004000U 6647 #define LRFDDBELL_ICLR2_PBE14_NOEFF 0x00000000U 6648 6649 // Field: [13] PBE13 6650 // 6651 // PBE13 event 6652 // ENUMs: 6653 // CLR Clear Interrupt 6654 // NOEFF Writing 0 has no effect 6655 #define LRFDDBELL_ICLR2_PBE13 0x00002000U 6656 #define LRFDDBELL_ICLR2_PBE13_M 0x00002000U 6657 #define LRFDDBELL_ICLR2_PBE13_S 13U 6658 #define LRFDDBELL_ICLR2_PBE13_CLR 0x00002000U 6659 #define LRFDDBELL_ICLR2_PBE13_NOEFF 0x00000000U 6660 6661 // Field: [12] PBE12 6662 // 6663 // PBE12 event 6664 // ENUMs: 6665 // CLR Clear Interrupt 6666 // NOEFF Writing 0 has no effect 6667 #define LRFDDBELL_ICLR2_PBE12 0x00001000U 6668 #define LRFDDBELL_ICLR2_PBE12_M 0x00001000U 6669 #define LRFDDBELL_ICLR2_PBE12_S 12U 6670 #define LRFDDBELL_ICLR2_PBE12_CLR 0x00001000U 6671 #define LRFDDBELL_ICLR2_PBE12_NOEFF 0x00000000U 6672 6673 // Field: [11] PBE11 6674 // 6675 // PBE11 event 6676 // ENUMs: 6677 // CLR Clear Interrupt 6678 // NOEFF Writing 0 has no effect 6679 #define LRFDDBELL_ICLR2_PBE11 0x00000800U 6680 #define LRFDDBELL_ICLR2_PBE11_M 0x00000800U 6681 #define LRFDDBELL_ICLR2_PBE11_S 11U 6682 #define LRFDDBELL_ICLR2_PBE11_CLR 0x00000800U 6683 #define LRFDDBELL_ICLR2_PBE11_NOEFF 0x00000000U 6684 6685 // Field: [10] PBE10 6686 // 6687 // PBE10 event 6688 // ENUMs: 6689 // CLR Clear Interrupt 6690 // NOEFF Writing 0 has no effect 6691 #define LRFDDBELL_ICLR2_PBE10 0x00000400U 6692 #define LRFDDBELL_ICLR2_PBE10_M 0x00000400U 6693 #define LRFDDBELL_ICLR2_PBE10_S 10U 6694 #define LRFDDBELL_ICLR2_PBE10_CLR 0x00000400U 6695 #define LRFDDBELL_ICLR2_PBE10_NOEFF 0x00000000U 6696 6697 // Field: [9] PBE9 6698 // 6699 // PBE9 event 6700 // ENUMs: 6701 // CLR Clear Interrupt 6702 // NOEFF Writing 0 has no effect 6703 #define LRFDDBELL_ICLR2_PBE9 0x00000200U 6704 #define LRFDDBELL_ICLR2_PBE9_M 0x00000200U 6705 #define LRFDDBELL_ICLR2_PBE9_S 9U 6706 #define LRFDDBELL_ICLR2_PBE9_CLR 0x00000200U 6707 #define LRFDDBELL_ICLR2_PBE9_NOEFF 0x00000000U 6708 6709 // Field: [8] PBE8 6710 // 6711 // PBE8 event 6712 // ENUMs: 6713 // CLR Clear Interrupt 6714 // NOEFF Writing 0 has no effect 6715 #define LRFDDBELL_ICLR2_PBE8 0x00000100U 6716 #define LRFDDBELL_ICLR2_PBE8_M 0x00000100U 6717 #define LRFDDBELL_ICLR2_PBE8_S 8U 6718 #define LRFDDBELL_ICLR2_PBE8_CLR 0x00000100U 6719 #define LRFDDBELL_ICLR2_PBE8_NOEFF 0x00000000U 6720 6721 // Field: [7] PBE7 6722 // 6723 // PBE7 event 6724 // ENUMs: 6725 // CLR Clear Interrupt 6726 // NOEFF Writing 0 has no effect 6727 #define LRFDDBELL_ICLR2_PBE7 0x00000080U 6728 #define LRFDDBELL_ICLR2_PBE7_M 0x00000080U 6729 #define LRFDDBELL_ICLR2_PBE7_S 7U 6730 #define LRFDDBELL_ICLR2_PBE7_CLR 0x00000080U 6731 #define LRFDDBELL_ICLR2_PBE7_NOEFF 0x00000000U 6732 6733 // Field: [6] PBE6 6734 // 6735 // PBE6 event 6736 // ENUMs: 6737 // CLR Clear Interrupt 6738 // NOEFF Writing 0 has no effect 6739 #define LRFDDBELL_ICLR2_PBE6 0x00000040U 6740 #define LRFDDBELL_ICLR2_PBE6_M 0x00000040U 6741 #define LRFDDBELL_ICLR2_PBE6_S 6U 6742 #define LRFDDBELL_ICLR2_PBE6_CLR 0x00000040U 6743 #define LRFDDBELL_ICLR2_PBE6_NOEFF 0x00000000U 6744 6745 // Field: [5] PBE5 6746 // 6747 // PBE5 event 6748 // ENUMs: 6749 // CLR Clear Interrupt 6750 // NOEFF Writing 0 has no effect 6751 #define LRFDDBELL_ICLR2_PBE5 0x00000020U 6752 #define LRFDDBELL_ICLR2_PBE5_M 0x00000020U 6753 #define LRFDDBELL_ICLR2_PBE5_S 5U 6754 #define LRFDDBELL_ICLR2_PBE5_CLR 0x00000020U 6755 #define LRFDDBELL_ICLR2_PBE5_NOEFF 0x00000000U 6756 6757 // Field: [4] PBE4 6758 // 6759 // PBE4 event 6760 // ENUMs: 6761 // CLR Clear Interrupt 6762 // NOEFF Writing 0 has no effect 6763 #define LRFDDBELL_ICLR2_PBE4 0x00000010U 6764 #define LRFDDBELL_ICLR2_PBE4_M 0x00000010U 6765 #define LRFDDBELL_ICLR2_PBE4_S 4U 6766 #define LRFDDBELL_ICLR2_PBE4_CLR 0x00000010U 6767 #define LRFDDBELL_ICLR2_PBE4_NOEFF 0x00000000U 6768 6769 // Field: [3] PBE3 6770 // 6771 // PBE3 event 6772 // ENUMs: 6773 // CLR Clear Interrupt 6774 // NOEFF Writing 0 has no effect 6775 #define LRFDDBELL_ICLR2_PBE3 0x00000008U 6776 #define LRFDDBELL_ICLR2_PBE3_M 0x00000008U 6777 #define LRFDDBELL_ICLR2_PBE3_S 3U 6778 #define LRFDDBELL_ICLR2_PBE3_CLR 0x00000008U 6779 #define LRFDDBELL_ICLR2_PBE3_NOEFF 0x00000000U 6780 6781 // Field: [2] PBE2 6782 // 6783 // PBE2 event 6784 // ENUMs: 6785 // CLR Clear Interrupt 6786 // NOEFF Writing 0 has no effect 6787 #define LRFDDBELL_ICLR2_PBE2 0x00000004U 6788 #define LRFDDBELL_ICLR2_PBE2_M 0x00000004U 6789 #define LRFDDBELL_ICLR2_PBE2_S 2U 6790 #define LRFDDBELL_ICLR2_PBE2_CLR 0x00000004U 6791 #define LRFDDBELL_ICLR2_PBE2_NOEFF 0x00000000U 6792 6793 // Field: [1] PBE1 6794 // 6795 // PBE1 event 6796 // ENUMs: 6797 // CLR Clear Interrupt 6798 // NOEFF Writing 0 has no effect 6799 #define LRFDDBELL_ICLR2_PBE1 0x00000002U 6800 #define LRFDDBELL_ICLR2_PBE1_M 0x00000002U 6801 #define LRFDDBELL_ICLR2_PBE1_S 1U 6802 #define LRFDDBELL_ICLR2_PBE1_CLR 0x00000002U 6803 #define LRFDDBELL_ICLR2_PBE1_NOEFF 0x00000000U 6804 6805 // Field: [0] PBE0 6806 // 6807 // PBE0 event 6808 // ENUMs: 6809 // CLR Clear Interrupt 6810 // NOEFF Writing 0 has no effect 6811 #define LRFDDBELL_ICLR2_PBE0 0x00000001U 6812 #define LRFDDBELL_ICLR2_PBE0_M 0x00000001U 6813 #define LRFDDBELL_ICLR2_PBE0_S 0U 6814 #define LRFDDBELL_ICLR2_PBE0_CLR 0x00000001U 6815 #define LRFDDBELL_ICLR2_PBE0_NOEFF 0x00000000U 6816 6817 6818 #endif // __LRFDDBELL__ 6819
