1 /****************************************************************************** 2 * Filename: hw_lgpt_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_LGPT_H__ 34 #define __HW_LGPT_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // LGPT component 40 // 41 //***************************************************************************** 42 // Description Register. 43 #define LGPT_O_DESC 0x00000000U 44 45 // Description Extended 46 #define LGPT_O_DESCEX 0x00000004U 47 48 // Start Configuration 49 #define LGPT_O_STARTCFG 0x00000008U 50 51 // Timer Control 52 #define LGPT_O_CTL 0x0000000CU 53 54 // Output Control 55 #define LGPT_O_OUTCTL 0x00000010U 56 57 // Counter 58 #define LGPT_O_CNTR 0x00000014U 59 60 // Clock Prescaler Configuration 61 #define LGPT_O_PRECFG 0x00000018U 62 63 // Prescaler Event 64 #define LGPT_O_PREEVENT 0x0000001CU 65 66 // Channel Input Filter 67 #define LGPT_O_CHFILT 0x00000020U 68 69 // Quadrature Decoder Status 70 #define LGPT_O_QDECSTAT 0x00000034U 71 72 // IR Generation 73 #define LGPT_O_IRGEN 0x00000038U 74 75 // Direct Memory Accsess 76 #define LGPT_O_DMA 0x0000003CU 77 78 // Direct Memory Access 79 #define LGPT_O_DMARW 0x00000040U 80 81 // ADC Trigger 82 #define LGPT_O_ADCTRG 0x00000044U 83 84 // IO Controller 85 #define LGPT_O_IOCTL 0x00000048U 86 87 // Interrupt mask. 88 #define LGPT_O_IMASK 0x00000068U 89 90 // Raw interrupt status. 91 #define LGPT_O_RIS 0x0000006CU 92 93 // Masked interrupt status. 94 #define LGPT_O_MIS 0x00000070U 95 96 // Interrupt set register. 97 #define LGPT_O_ISET 0x00000074U 98 99 // Interrupt clear register. 100 #define LGPT_O_ICLR 0x00000078U 101 102 // Interrupt mask set register. 103 #define LGPT_O_IMSET 0x0000007CU 104 105 // Interrupt mask clear register. 106 #define LGPT_O_IMCLR 0x00000080U 107 108 // Debug control 109 #define LGPT_O_EMU 0x00000084U 110 111 // Channel 0 Configuration 112 #define LGPT_O_C0CFG 0x000000C0U 113 114 // Channel 1 Configuration 115 #define LGPT_O_C1CFG 0x000000C4U 116 117 // Channel 2 Configuration 118 #define LGPT_O_C2CFG 0x000000C8U 119 120 // Pipeline Target 121 #define LGPT_O_PTGT 0x000000FCU 122 123 // Pipeline Channel 0 Capture Compare 124 #define LGPT_O_PC0CC 0x00000100U 125 126 // Pipeline Channel 1 Capture Compare 127 #define LGPT_O_PC1CC 0x00000104U 128 129 // Pipeline Channel 2 Capture Compare 130 #define LGPT_O_PC2CC 0x00000108U 131 132 // Target 133 #define LGPT_O_TGT 0x0000013CU 134 135 // Channel 0 Capture Compare 136 #define LGPT_O_C0CC 0x00000140U 137 138 // Channel 1 Capture Compare 139 #define LGPT_O_C1CC 0x00000144U 140 141 // Channel 2 Capture Compare 142 #define LGPT_O_C2CC 0x00000148U 143 144 // Pipeline Target No Clear 145 #define LGPT_O_PTGTNC 0x0000017CU 146 147 // Pipeline Channel 0 Capture Compare No Clear 148 #define LGPT_O_PC0CCNC 0x00000180U 149 150 // Pipeline Channel 1 Capture Compare No Clear 151 #define LGPT_O_PC1CCNC 0x00000184U 152 153 // Pipeline Channel 2 Capture Compare No Clear 154 #define LGPT_O_PC2CCNC 0x00000188U 155 156 // Target No Clear 157 #define LGPT_O_TGTNC 0x000001BCU 158 159 // Channel 0 Capture Compare No Clear 160 #define LGPT_O_C0CCNC 0x000001C0U 161 162 // Channel 1 Capture Compare No Clear 163 #define LGPT_O_C1CCNC 0x000001C4U 164 165 // Channel 2 Capture Compare No Clear 166 #define LGPT_O_C2CCNC 0x000001C8U 167 168 //***************************************************************************** 169 // 170 // Register: LGPT_O_DESC 171 // 172 //***************************************************************************** 173 // Field: [31:16] MODID 174 // 175 // Module identifier used to uniquely identify this IP. 176 #define LGPT_DESC_MODID_W 16U 177 #define LGPT_DESC_MODID_M 0xFFFF0000U 178 #define LGPT_DESC_MODID_S 16U 179 180 // Field: [15:12] STDIPOFF 181 // 182 // Standard IP MMR block offset. Standard IP MMRs are the set of from 183 // aggregated IRQ registers till DTB. 184 // 185 // 0: Standard IP MMRs do not exist 186 // 187 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 188 // address) 189 #define LGPT_DESC_STDIPOFF_W 4U 190 #define LGPT_DESC_STDIPOFF_M 0x0000F000U 191 #define LGPT_DESC_STDIPOFF_S 12U 192 193 // Field: [11:8] INSTIDX 194 // 195 // IP Instance ID number. If multiple instances of IP exist in the device, this 196 // field can identify the instance number. 197 #define LGPT_DESC_INSTIDX_W 4U 198 #define LGPT_DESC_INSTIDX_M 0x00000F00U 199 #define LGPT_DESC_INSTIDX_S 8U 200 201 // Field: [7:4] MAJREV 202 // 203 // Major revision of IP. 204 #define LGPT_DESC_MAJREV_W 4U 205 #define LGPT_DESC_MAJREV_M 0x000000F0U 206 #define LGPT_DESC_MAJREV_S 4U 207 208 // Field: [3:0] MINREV 209 // 210 // Minor revision of IP. 211 #define LGPT_DESC_MINREV_W 4U 212 #define LGPT_DESC_MINREV_M 0x0000000FU 213 #define LGPT_DESC_MINREV_S 0U 214 215 //***************************************************************************** 216 // 217 // Register: LGPT_O_DESCEX 218 // 219 //***************************************************************************** 220 // Field: [19] HIR 221 // 222 // Has IR logic. 223 #define LGPT_DESCEX_HIR 0x00080000U 224 #define LGPT_DESCEX_HIR_M 0x00080000U 225 #define LGPT_DESCEX_HIR_S 19U 226 227 // Field: [18] HDBF 228 // 229 // Has Dead-Band, Fault, and Park logic. 230 #define LGPT_DESCEX_HDBF 0x00040000U 231 #define LGPT_DESCEX_HDBF_M 0x00040000U 232 #define LGPT_DESCEX_HDBF_S 18U 233 234 // Field: [17:14] PREW 235 // 236 // Prescale width. The prescaler can maximum be configured to 2^PREW-1. 237 #define LGPT_DESCEX_PREW_W 4U 238 #define LGPT_DESCEX_PREW_M 0x0003C000U 239 #define LGPT_DESCEX_PREW_S 14U 240 241 // Field: [13] HQDEC 242 // 243 // Has Quadrature Decoder. 244 #define LGPT_DESCEX_HQDEC 0x00002000U 245 #define LGPT_DESCEX_HQDEC_M 0x00002000U 246 #define LGPT_DESCEX_HQDEC_S 13U 247 248 // Field: [12] HCIF 249 // 250 // Has channel input filter. 251 #define LGPT_DESCEX_HCIF 0x00001000U 252 #define LGPT_DESCEX_HCIF_M 0x00001000U 253 #define LGPT_DESCEX_HCIF_S 12U 254 255 // Field: [11:8] CIFS 256 // 257 // Channel input filter size. The prevailing state filter can maximum be 258 // configured to 2^CIFS-1. 259 #define LGPT_DESCEX_CIFS_W 4U 260 #define LGPT_DESCEX_CIFS_M 0x00000F00U 261 #define LGPT_DESCEX_CIFS_S 8U 262 263 // Field: [7] HDMA 264 // 265 // Has uDMA output and logic. 266 #define LGPT_DESCEX_HDMA 0x00000080U 267 #define LGPT_DESCEX_HDMA_M 0x00000080U 268 #define LGPT_DESCEX_HDMA_S 7U 269 270 // Field: [6] HINT 271 // 272 // Has interrupt output and logic. 273 #define LGPT_DESCEX_HINT 0x00000040U 274 #define LGPT_DESCEX_HINT_M 0x00000040U 275 #define LGPT_DESCEX_HINT_S 6U 276 277 // Field: [5:4] CNTRW 278 // 279 // Counter bit-width. 280 // The maximum counter value is equal to 2^CNTRW-1. 281 // ENUMs: 282 // RESERVED RESERVED 283 // CNTR32 32-bit counter. 284 // CNTR24 24-bit counter. 285 // CNTR16 16-bit counter. 286 #define LGPT_DESCEX_CNTRW_W 2U 287 #define LGPT_DESCEX_CNTRW_M 0x00000030U 288 #define LGPT_DESCEX_CNTRW_S 4U 289 #define LGPT_DESCEX_CNTRW_RESERVED 0x00000030U 290 #define LGPT_DESCEX_CNTRW_CNTR32 0x00000020U 291 #define LGPT_DESCEX_CNTRW_CNTR24 0x00000010U 292 #define LGPT_DESCEX_CNTRW_CNTR16 0x00000000U 293 294 // Field: [3:0] NCH 295 // 296 // Number of channels. 297 #define LGPT_DESCEX_NCH_W 4U 298 #define LGPT_DESCEX_NCH_M 0x0000000FU 299 #define LGPT_DESCEX_NCH_S 0U 300 301 //***************************************************************************** 302 // 303 // Register: LGPT_O_STARTCFG 304 // 305 //***************************************************************************** 306 // Field: [1:0] LGPT 307 // 308 // LGPT start 309 // ENUMs: 310 // EV_SYNC LGPT starts when synchronized event input is high. 311 // Configured here EVTSVT.LGPTSYNCSEL. 312 #define LGPT_STARTCFG_LGPT_W 2U 313 #define LGPT_STARTCFG_LGPT_M 0x00000003U 314 #define LGPT_STARTCFG_LGPT_S 0U 315 #define LGPT_STARTCFG_LGPT_EV_SYNC 0x00000000U 316 317 //***************************************************************************** 318 // 319 // Register: LGPT_O_CTL 320 // 321 //***************************************************************************** 322 // Field: [10] C2RST 323 // 324 // Channel 2 reset. 325 // ENUMs: 326 // RST Reset C2CC, PC2CC, and C2CFG. 327 // NOEFF No effect. 328 #define LGPT_CTL_C2RST 0x00000400U 329 #define LGPT_CTL_C2RST_M 0x00000400U 330 #define LGPT_CTL_C2RST_S 10U 331 #define LGPT_CTL_C2RST_RST 0x00000400U 332 #define LGPT_CTL_C2RST_NOEFF 0x00000000U 333 334 // Field: [9] C1RST 335 // 336 // Channel 1 reset. 337 // ENUMs: 338 // RST Reset C1CC, PC1CC, and C1CFG. 339 // NOEFF No effect. 340 #define LGPT_CTL_C1RST 0x00000200U 341 #define LGPT_CTL_C1RST_M 0x00000200U 342 #define LGPT_CTL_C1RST_S 9U 343 #define LGPT_CTL_C1RST_RST 0x00000200U 344 #define LGPT_CTL_C1RST_NOEFF 0x00000000U 345 346 // Field: [8] C0RST 347 // 348 // Channel 0 reset. 349 // ENUMs: 350 // RST Reset C0CC, PC0CC, and C0CFG. 351 // NOEFF No effect. 352 #define LGPT_CTL_C0RST 0x00000100U 353 #define LGPT_CTL_C0RST_M 0x00000100U 354 #define LGPT_CTL_C0RST_S 8U 355 #define LGPT_CTL_C0RST_RST 0x00000100U 356 #define LGPT_CTL_C0RST_NOEFF 0x00000000U 357 358 // Field: [5] INTP 359 // 360 // Interrupt Phase. 361 // This bit field controls when the RIS.TGT and RIS.ZERO interrupts are set. 362 // ENUMs: 363 // LATE RIS.TGT and RIS.ZERO are set one timer clock cycle 364 // after CNTR = TARGET/ZERO. 365 // EARLY RIS.TGT and RIS.ZERO are set one system clock 366 // cycle after CNTR = TARGET/ZERO. 367 #define LGPT_CTL_INTP 0x00000020U 368 #define LGPT_CTL_INTP_M 0x00000020U 369 #define LGPT_CTL_INTP_S 5U 370 #define LGPT_CTL_INTP_LATE 0x00000020U 371 #define LGPT_CTL_INTP_EARLY 0x00000000U 372 373 // Field: [4:3] CMPDIR 374 // 375 // Compare direction. 376 // 377 // This bit field controls the direction the counter must have in order to set 378 // the [RIS.CnCC] channel interrupts. This bitfield is only relevant if 379 // [CnCFG.CCACT] is configured to a compare action. 380 // ENUMs: 381 // RESERVED RESERVED 382 // DOWN Compare RIS fields are only set on down count. 383 // UP Compare RIS fields are only set on up count. 384 // BOTH Compare RIS fields are set on up count and down 385 // count. 386 #define LGPT_CTL_CMPDIR_W 2U 387 #define LGPT_CTL_CMPDIR_M 0x00000018U 388 #define LGPT_CTL_CMPDIR_S 3U 389 #define LGPT_CTL_CMPDIR_RESERVED 0x00000018U 390 #define LGPT_CTL_CMPDIR_DOWN 0x00000010U 391 #define LGPT_CTL_CMPDIR_UP 0x00000008U 392 #define LGPT_CTL_CMPDIR_BOTH 0x00000000U 393 394 // Field: [2:0] MODE 395 // 396 // Timer mode control 397 // 398 // The CNTR restarts from 0 when MODE is written to UP_ONCE, UP_PER, UPDWN_PER, 399 // QDEC, SYNC_UP_ONCE, SYNC_UP_PER or SYNC_UPDWN_PER. 400 // 401 // When writing MODE all internally queued updates to the channels and TGT is 402 // cleared. 403 // 404 // When configuring the timer, MODE should be the last thing to configure. If 405 // changing timer configuration after MODE has been set is necessary, 406 // instructions, if any, given in the configuration registers should be 407 // followed. See for example C0CFG. 408 // ENUMs: 409 // SYNC_UPDWN_PER Start counting up and down periodically 410 // synchronous to another LGPT, selected within 411 // STARTCFG. The timer is started by setting 412 // CTL.MODE = UPDWN_PER automatically. 413 // It then operates as a 414 // normal timer in CTL.MODE = UPDWN_PER, counting 415 // from 0 to target value and back to 0, 416 // repeatedly. 417 // 418 // Period = (target value * 419 // 2) * timer clock period 420 // SYNC_UP_PER Start counting up periodically synchronous to 421 // another LGPT, selected within STARTCFG. The 422 // timer is started by setting CTL.MODE = UP_PER 423 // automatically. 424 // It then operates as a 425 // normal timer in CTL.MODE = UP_PER, incrementing 426 // from 0 to target value, repeatedly. 427 // 428 // Period = (target value * 429 // 2) * timer clock period 430 // SYNC_UP_ONCE Start counting up once synchronous to another 431 // LGPT, selected within STARTCFG. The timer is 432 // started by setting CTL.MODE = UP_ONCE 433 // automatically. 434 // It then functions as a 435 // normal timer in CTL.MODE = UP_ONCE, 436 // incrementing from 0 to target value, then 437 // stops and sets MODE to DIS. 438 // QDEC The timer functions as a quadrature decoder. IOC 439 // input 0, IOC input 1 and IOC input 2 are used 440 // respectivly as PHA, PHB and IDX inputs. IDX can 441 // be turned off by setting C2CFG.EDGE = NONE. 442 // The timer clock frequency 443 // sets the sample rate of the QDEC logic. This 444 // frequency can be configured in PRECFG. 445 // UPDWN_PER Count up and down periodically. The timer counts 446 // from 0 to target value and back to 0, 447 // repeatedly. 448 // 449 // Period = (target value * 450 // 2) * timer clock period 451 // UP_PER Count up periodically. The timer increments from 0 452 // to target value, repeatedly. 453 // 454 // Period = (target value + 455 // 1) * timer clock period 456 // UP_ONCE Count up once. The timer increments from 0 to 457 // target value, then stops and sets MODE to DIS. 458 // DIS Disable timer. Updates to counter, channels, and 459 // events stop. 460 #define LGPT_CTL_MODE_W 3U 461 #define LGPT_CTL_MODE_M 0x00000007U 462 #define LGPT_CTL_MODE_S 0U 463 #define LGPT_CTL_MODE_SYNC_UPDWN_PER 0x00000007U 464 #define LGPT_CTL_MODE_SYNC_UP_PER 0x00000006U 465 #define LGPT_CTL_MODE_SYNC_UP_ONCE 0x00000005U 466 #define LGPT_CTL_MODE_QDEC 0x00000004U 467 #define LGPT_CTL_MODE_UPDWN_PER 0x00000003U 468 #define LGPT_CTL_MODE_UP_PER 0x00000002U 469 #define LGPT_CTL_MODE_UP_ONCE 0x00000001U 470 #define LGPT_CTL_MODE_DIS 0x00000000U 471 472 //***************************************************************************** 473 // 474 // Register: LGPT_O_OUTCTL 475 // 476 //***************************************************************************** 477 // Field: [5] SETOUT2 478 // 479 // Set output 2. 480 // 481 // Write 1 to set output 2. 482 #define LGPT_OUTCTL_SETOUT2 0x00000020U 483 #define LGPT_OUTCTL_SETOUT2_M 0x00000020U 484 #define LGPT_OUTCTL_SETOUT2_S 5U 485 486 // Field: [4] CLROUT2 487 // 488 // Clear output 2. 489 // 490 // Write 1 to clear output 2. 491 #define LGPT_OUTCTL_CLROUT2 0x00000010U 492 #define LGPT_OUTCTL_CLROUT2_M 0x00000010U 493 #define LGPT_OUTCTL_CLROUT2_S 4U 494 495 // Field: [3] SETOUT1 496 // 497 // Set output 1. 498 // 499 // Write 1 to set output 1. 500 #define LGPT_OUTCTL_SETOUT1 0x00000008U 501 #define LGPT_OUTCTL_SETOUT1_M 0x00000008U 502 #define LGPT_OUTCTL_SETOUT1_S 3U 503 504 // Field: [2] CLROUT1 505 // 506 // Clear output 1. 507 // 508 // Write 1 to clear output 1. 509 #define LGPT_OUTCTL_CLROUT1 0x00000004U 510 #define LGPT_OUTCTL_CLROUT1_M 0x00000004U 511 #define LGPT_OUTCTL_CLROUT1_S 2U 512 513 // Field: [1] SETOUT0 514 // 515 // Set output 0. 516 // 517 // Write 1 to set output 0. 518 #define LGPT_OUTCTL_SETOUT0 0x00000002U 519 #define LGPT_OUTCTL_SETOUT0_M 0x00000002U 520 #define LGPT_OUTCTL_SETOUT0_S 1U 521 522 // Field: [0] CLROUT0 523 // 524 // Clear output 0. 525 // 526 // Write 1 to clear output 0. 527 #define LGPT_OUTCTL_CLROUT0 0x00000001U 528 #define LGPT_OUTCTL_CLROUT0_M 0x00000001U 529 #define LGPT_OUTCTL_CLROUT0_S 0U 530 531 //***************************************************************************** 532 // 533 // Register: LGPT_O_CNTR 534 // 535 //***************************************************************************** 536 // Field: [15:0] VAL 537 // 538 // Current counter value. 539 // If CTL.MODE = QDEC this can be used to set the initial counter value during 540 // QDEC. Writing to CNTR in other modes than QDEC is possible, but may result 541 // in unpredictable behavior. 542 #define LGPT_CNTR_VAL_W 16U 543 #define LGPT_CNTR_VAL_M 0x0000FFFFU 544 #define LGPT_CNTR_VAL_S 0U 545 546 //***************************************************************************** 547 // 548 // Register: LGPT_O_PRECFG 549 // 550 //***************************************************************************** 551 // Field: [15:8] TICKDIV 552 // 553 // Tick division. 554 // 555 // TICKDIV determines the timer clock frequency for the counter, and timer 556 // output updates. The timer clock frequency is the clock selected by TICKSRC 557 // divided by (TICKDIV + 1). This inverse is the timer clock period. 558 // 559 // 0x00: Divide by 1. 560 // 0x01: Divide by 2. 561 // ... 562 // 0xFF: Divide by 256. 563 #define LGPT_PRECFG_TICKDIV_W 8U 564 #define LGPT_PRECFG_TICKDIV_M 0x0000FF00U 565 #define LGPT_PRECFG_TICKDIV_S 8U 566 567 // Field: [1:0] TICKSRC 568 // 569 // Prescaler tick source. 570 // 571 // TICKSRC determines the source which decrements the prescaler. 572 // ENUMs: 573 // BOTH_TICK Prescaler is updated at both edges of TICKEN. 574 // FALL_TICK Prescaler is updated at the falling edge of 575 // TICKEN. 576 // RISE_TICK Prescaler is updated at the rising edge of TICKEN. 577 // CLK Prescaler is updated at the system clock. 578 #define LGPT_PRECFG_TICKSRC_W 2U 579 #define LGPT_PRECFG_TICKSRC_M 0x00000003U 580 #define LGPT_PRECFG_TICKSRC_S 0U 581 #define LGPT_PRECFG_TICKSRC_BOTH_TICK 0x00000003U 582 #define LGPT_PRECFG_TICKSRC_FALL_TICK 0x00000002U 583 #define LGPT_PRECFG_TICKSRC_RISE_TICK 0x00000001U 584 #define LGPT_PRECFG_TICKSRC_CLK 0x00000000U 585 586 //***************************************************************************** 587 // 588 // Register: LGPT_O_PREEVENT 589 // 590 //***************************************************************************** 591 // Field: [7:0] VAL 592 // 593 // Sets the HIGH time of the prescaler event output. 594 // 595 // Event goes high when the prescaler counter equals VAL. Event goes low when 596 // prescaler counter is 0. 597 // 598 // Note: 599 // - Can be used to precharge or turn an external component on for a short time 600 // before sampling, like in QDEC. 601 // - If there is a requirement to create such events that have very short 602 // periods compared to timer clock period, use two timers. One timer acts as 603 // prescaler and event generator for another timer. 604 #define LGPT_PREEVENT_VAL_W 8U 605 #define LGPT_PREEVENT_VAL_M 0x000000FFU 606 #define LGPT_PREEVENT_VAL_S 0U 607 608 //***************************************************************************** 609 // 610 // Register: LGPT_O_CHFILT 611 // 612 //***************************************************************************** 613 // Field: [15:8] LOAD 614 // 615 // The input of the channel filter is passed to the edge detection logic after 616 // LOAD + 1 consecutive equal samples. 617 #define LGPT_CHFILT_LOAD_W 8U 618 #define LGPT_CHFILT_LOAD_M 0x0000FF00U 619 #define LGPT_CHFILT_LOAD_S 8U 620 621 // Field: [1:0] MODE 622 // 623 // Channel filter mode 624 // ENUMs: 625 // TIMERCLK Filter is clocked by timer clock. 626 // TICKSRC Filter is clocked by PRECFG.TICKSRC. 627 // CLK Filter is clocked by system clock. 628 // BYPASS Filter is bypassed. No Filter is used. 629 #define LGPT_CHFILT_MODE_W 2U 630 #define LGPT_CHFILT_MODE_M 0x00000003U 631 #define LGPT_CHFILT_MODE_S 0U 632 #define LGPT_CHFILT_MODE_TIMERCLK 0x00000003U 633 #define LGPT_CHFILT_MODE_TICKSRC 0x00000002U 634 #define LGPT_CHFILT_MODE_CLK 0x00000001U 635 #define LGPT_CHFILT_MODE_BYPASS 0x00000000U 636 637 //***************************************************************************** 638 // 639 // Register: LGPT_O_QDECSTAT 640 // 641 //***************************************************************************** 642 // Field: [1] DBLTRANS 643 // 644 // Double transition 645 // ENUMs: 646 // DBL Double transition on phase inputs. 647 // NONE Single or no transition on phase inputs. 648 #define LGPT_QDECSTAT_DBLTRANS 0x00000002U 649 #define LGPT_QDECSTAT_DBLTRANS_M 0x00000002U 650 #define LGPT_QDECSTAT_DBLTRANS_S 1U 651 #define LGPT_QDECSTAT_DBLTRANS_DBL 0x00000002U 652 #define LGPT_QDECSTAT_DBLTRANS_NONE 0x00000000U 653 654 // Field: [0] QDIR 655 // 656 // Direction of count during QDEC mode. 657 // ENUMs: 658 // DOWN Down (PHB leads PHA) 659 // UP Up (PHA leads PHB) 660 #define LGPT_QDECSTAT_QDIR 0x00000001U 661 #define LGPT_QDECSTAT_QDIR_M 0x00000001U 662 #define LGPT_QDECSTAT_QDIR_S 0U 663 #define LGPT_QDECSTAT_QDIR_DOWN 0x00000001U 664 #define LGPT_QDECSTAT_QDIR_UP 0x00000000U 665 666 //***************************************************************************** 667 // 668 // Register: LGPT_O_IRGEN 669 // 670 //***************************************************************************** 671 // Field: [0] CTL 672 // 673 // Control 674 // ENUMs: 675 // EN Enable. 676 // DIS Disable. 677 #define LGPT_IRGEN_CTL 0x00000001U 678 #define LGPT_IRGEN_CTL_M 0x00000001U 679 #define LGPT_IRGEN_CTL_S 0U 680 #define LGPT_IRGEN_CTL_EN 0x00000001U 681 #define LGPT_IRGEN_CTL_DIS 0x00000000U 682 683 //***************************************************************************** 684 // 685 // Register: LGPT_O_DMA 686 // 687 //***************************************************************************** 688 // Field: [19:16] RWCNTR 689 // 690 // The read/write counter. RWCNTR+1 is the number of times the DMA can access 691 // (read/write) the DMARW register. For each DMA access to DMARW an internal 692 // counter is incremented, writing to the next address field. RWADDR + 4*RWCNTR 693 // is the final register address which can be accessed by the DMA. 694 #define LGPT_DMA_RWCNTR_W 4U 695 #define LGPT_DMA_RWCNTR_M 0x000F0000U 696 #define LGPT_DMA_RWCNTR_S 16U 697 698 // Field: [14:8] RWADDR 699 // 700 // The base address which the DMA access when reading/writing DMARW. The base 701 // address is set by taking the 9 LSB of the physical address and divide by 4. 702 // For example, if you wanted the RWADDR to point to the PTGT register you 703 // should set RWADDR = 0x0FC/4. 704 #define LGPT_DMA_RWADDR_W 7U 705 #define LGPT_DMA_RWADDR_M 0x00007F00U 706 #define LGPT_DMA_RWADDR_S 8U 707 708 // Field: [3:0] REQ 709 // 710 // ENUMs: 711 // C11CC Setting of RIS.C11CC generates a DMA request. 712 // C10CC Setting of RIS.C10CC generates a DMA request. 713 // C9CC Setting of RIS.C9CC generates a DMA request. 714 // C8CC Setting of RIS.C8CC generates a DMA request. 715 // C7CC Setting of RIS.C7CC generates a DMA request. 716 // C6CC Setting of RIS.C6CC generates a DMA request. 717 // C5CC Setting of RIS.C5CC generates a DMA request. 718 // C4CC Setting of RIS.C4CC generates a DMA request. 719 // C3CC Setting of RIS.C3CC generates a DMA request. 720 // C2CC Setting of RIS.C2CC generates a DMA request. 721 // C1CC Setting of RIS.C1CC generates a DMA request. 722 // C0CC Setting of RIS.C0CC generates a DMA request. 723 // FAULT Setting of RIS.FAULT generates a DMA request. 724 // ZERO Setting of RIS.ZERO generates a DMA request. 725 // TGT Setting of RIS.TGT generates a DMA request. 726 // DIS Disabled 727 #define LGPT_DMA_REQ_W 4U 728 #define LGPT_DMA_REQ_M 0x0000000FU 729 #define LGPT_DMA_REQ_S 0U 730 #define LGPT_DMA_REQ_C11CC 0x0000000FU 731 #define LGPT_DMA_REQ_C10CC 0x0000000EU 732 #define LGPT_DMA_REQ_C9CC 0x0000000DU 733 #define LGPT_DMA_REQ_C8CC 0x0000000CU 734 #define LGPT_DMA_REQ_C7CC 0x0000000BU 735 #define LGPT_DMA_REQ_C6CC 0x0000000AU 736 #define LGPT_DMA_REQ_C5CC 0x00000009U 737 #define LGPT_DMA_REQ_C4CC 0x00000008U 738 #define LGPT_DMA_REQ_C3CC 0x00000007U 739 #define LGPT_DMA_REQ_C2CC 0x00000006U 740 #define LGPT_DMA_REQ_C1CC 0x00000005U 741 #define LGPT_DMA_REQ_C0CC 0x00000004U 742 #define LGPT_DMA_REQ_FAULT 0x00000003U 743 #define LGPT_DMA_REQ_ZERO 0x00000002U 744 #define LGPT_DMA_REQ_TGT 0x00000001U 745 #define LGPT_DMA_REQ_DIS 0x00000000U 746 747 //***************************************************************************** 748 // 749 // Register: LGPT_O_DMARW 750 // 751 //***************************************************************************** 752 // Field: [15:0] VAL 753 // 754 // DMA read write value. 755 // 756 // The value that is read/written from/to the registers. 757 #define LGPT_DMARW_VAL_W 16U 758 #define LGPT_DMARW_VAL_M 0x0000FFFFU 759 #define LGPT_DMARW_VAL_S 0U 760 761 //***************************************************************************** 762 // 763 // Register: LGPT_O_ADCTRG 764 // 765 //***************************************************************************** 766 // Field: [3:0] SRC 767 // 768 // ENUMs: 769 // C11CC Setting of RIS.C11CC generates an ADC trigger. 770 // C10CC Setting of RIS.C10CC generates an ADC trigger. 771 // C9CC Setting of RIS.C9CC generates an ADC trigger. 772 // C8CC Setting of RIS.C8CC generates an ADC trigger. 773 // C7CC Setting of RIS.C7CC generates an ADC trigger. 774 // C6CC Setting of RIS.C6CC generates an ADC trigger. 775 // C5CC Setting of RIS.C5CC generates an ADC trigger. 776 // C4CC Setting of RIS.C4CC generates an ADC trigger. 777 // C3CC Setting of RIS.C3CC generates an ADC trigger. 778 // C2CC Setting of RIS.C2CC generates an ADC trigger. 779 // C1CC Setting of RIS.C1CC generates an ADC trigger. 780 // C0CC Setting of RIS.C0CC generates an ADC trigger. 781 // FAULT Setting of RIS.FAULT generates an ADC trigger. 782 // ZERO Setting of RIS.ZERO generates an ADC trigger. 783 // TGT Setting of RIS.TGT generates an ADC trigger. 784 // DIS Disabled 785 #define LGPT_ADCTRG_SRC_W 4U 786 #define LGPT_ADCTRG_SRC_M 0x0000000FU 787 #define LGPT_ADCTRG_SRC_S 0U 788 #define LGPT_ADCTRG_SRC_C11CC 0x0000000FU 789 #define LGPT_ADCTRG_SRC_C10CC 0x0000000EU 790 #define LGPT_ADCTRG_SRC_C9CC 0x0000000DU 791 #define LGPT_ADCTRG_SRC_C8CC 0x0000000CU 792 #define LGPT_ADCTRG_SRC_C7CC 0x0000000BU 793 #define LGPT_ADCTRG_SRC_C6CC 0x0000000AU 794 #define LGPT_ADCTRG_SRC_C5CC 0x00000009U 795 #define LGPT_ADCTRG_SRC_C4CC 0x00000008U 796 #define LGPT_ADCTRG_SRC_C3CC 0x00000007U 797 #define LGPT_ADCTRG_SRC_C2CC 0x00000006U 798 #define LGPT_ADCTRG_SRC_C1CC 0x00000005U 799 #define LGPT_ADCTRG_SRC_C0CC 0x00000004U 800 #define LGPT_ADCTRG_SRC_FAULT 0x00000003U 801 #define LGPT_ADCTRG_SRC_ZERO 0x00000002U 802 #define LGPT_ADCTRG_SRC_TGT 0x00000001U 803 #define LGPT_ADCTRG_SRC_DIS 0x00000000U 804 805 //***************************************************************************** 806 // 807 // Register: LGPT_O_IOCTL 808 // 809 //***************************************************************************** 810 // Field: [11:10] COUT2 811 // 812 // IO complementary output 2 control 813 // 814 // This bit field controls IO complementary output 2. 815 // ENUMs: 816 // INV Inverted value. The IO complementary output is 817 // inverted. 818 // HIGH Driven high. The IO complementary output is driven 819 // high. 820 // LOW Driven low. The IO complementary output is driven 821 // low. 822 // NRM Normal output. The IO complementary output is not 823 // changed. 824 #define LGPT_IOCTL_COUT2_W 2U 825 #define LGPT_IOCTL_COUT2_M 0x00000C00U 826 #define LGPT_IOCTL_COUT2_S 10U 827 #define LGPT_IOCTL_COUT2_INV 0x00000C00U 828 #define LGPT_IOCTL_COUT2_HIGH 0x00000800U 829 #define LGPT_IOCTL_COUT2_LOW 0x00000400U 830 #define LGPT_IOCTL_COUT2_NRM 0x00000000U 831 832 // Field: [9:8] OUT2 833 // 834 // IO output 2 control 835 // 836 // This bit field controls IO output 2. 837 // ENUMs: 838 // INV Inverted value. The IO output is inverted. 839 // HIGH Driven high. The IO output is driven high. 840 // LOW Driven low. The IO output is driven low. 841 // NRM Normal output. The IO output is not changed. 842 #define LGPT_IOCTL_OUT2_W 2U 843 #define LGPT_IOCTL_OUT2_M 0x00000300U 844 #define LGPT_IOCTL_OUT2_S 8U 845 #define LGPT_IOCTL_OUT2_INV 0x00000300U 846 #define LGPT_IOCTL_OUT2_HIGH 0x00000200U 847 #define LGPT_IOCTL_OUT2_LOW 0x00000100U 848 #define LGPT_IOCTL_OUT2_NRM 0x00000000U 849 850 // Field: [7:6] COUT1 851 // 852 // IO complementary output 1 control 853 // 854 // This bit field controls IO complementary output 1. 855 // ENUMs: 856 // INV Inverted value. The IO complementary output is 857 // inverted. 858 // HIGH Driven high. The IO complementary output is driven 859 // high. 860 // LOW Driven low. The IO complementary output is driven 861 // low. 862 // NRM Normal output. The IO complementary output is not 863 // changed. 864 #define LGPT_IOCTL_COUT1_W 2U 865 #define LGPT_IOCTL_COUT1_M 0x000000C0U 866 #define LGPT_IOCTL_COUT1_S 6U 867 #define LGPT_IOCTL_COUT1_INV 0x000000C0U 868 #define LGPT_IOCTL_COUT1_HIGH 0x00000080U 869 #define LGPT_IOCTL_COUT1_LOW 0x00000040U 870 #define LGPT_IOCTL_COUT1_NRM 0x00000000U 871 872 // Field: [5:4] OUT1 873 // 874 // IO output 1 control 875 // 876 // This bit field controls IO output 1. 877 // ENUMs: 878 // INV Inverted value. The IO output is inverted. 879 // HIGH Driven high. The IO output is driven high. 880 // LOW Driven low. The IO output is driven low. 881 // NRM Normal output. The IO output is not changed. 882 #define LGPT_IOCTL_OUT1_W 2U 883 #define LGPT_IOCTL_OUT1_M 0x00000030U 884 #define LGPT_IOCTL_OUT1_S 4U 885 #define LGPT_IOCTL_OUT1_INV 0x00000030U 886 #define LGPT_IOCTL_OUT1_HIGH 0x00000020U 887 #define LGPT_IOCTL_OUT1_LOW 0x00000010U 888 #define LGPT_IOCTL_OUT1_NRM 0x00000000U 889 890 // Field: [3:2] COUT0 891 // 892 // IO complementary output 0 control 893 // 894 // This bit field controls IO complementary output 0. 895 // ENUMs: 896 // INV Inverted value. The IO complementary output is 897 // inverted. 898 // HIGH Driven high. The IO complementary output is driven 899 // high. 900 // LOW Driven low. The IO complementary output is driven 901 // low. 902 // NRM Normal output. The IO complementary output is not 903 // changed. 904 #define LGPT_IOCTL_COUT0_W 2U 905 #define LGPT_IOCTL_COUT0_M 0x0000000CU 906 #define LGPT_IOCTL_COUT0_S 2U 907 #define LGPT_IOCTL_COUT0_INV 0x0000000CU 908 #define LGPT_IOCTL_COUT0_HIGH 0x00000008U 909 #define LGPT_IOCTL_COUT0_LOW 0x00000004U 910 #define LGPT_IOCTL_COUT0_NRM 0x00000000U 911 912 // Field: [1:0] OUT0 913 // 914 // IO output 0 control 915 // 916 // This bit field controls IO output 0. 917 // ENUMs: 918 // INV Inverted value. The IO output is inverted. 919 // HIGH Driven high. The IO output is driven high. 920 // LOW Driven low. The IO output is driven low. 921 // NRM Normal output. The IO output is not changed. 922 #define LGPT_IOCTL_OUT0_W 2U 923 #define LGPT_IOCTL_OUT0_M 0x00000003U 924 #define LGPT_IOCTL_OUT0_S 0U 925 #define LGPT_IOCTL_OUT0_INV 0x00000003U 926 #define LGPT_IOCTL_OUT0_HIGH 0x00000002U 927 #define LGPT_IOCTL_OUT0_LOW 0x00000001U 928 #define LGPT_IOCTL_OUT0_NRM 0x00000000U 929 930 //***************************************************************************** 931 // 932 // Register: LGPT_O_IMASK 933 // 934 //***************************************************************************** 935 // Field: [10] C2CC 936 // 937 // Enable RIS.C2CC interrupt. 938 // ENUMs: 939 // EN Enable 940 // DIS Disable 941 #define LGPT_IMASK_C2CC 0x00000400U 942 #define LGPT_IMASK_C2CC_M 0x00000400U 943 #define LGPT_IMASK_C2CC_S 10U 944 #define LGPT_IMASK_C2CC_EN 0x00000400U 945 #define LGPT_IMASK_C2CC_DIS 0x00000000U 946 947 // Field: [9] C1CC 948 // 949 // Enable RIS.C1CC interrupt. 950 // ENUMs: 951 // EN Enable 952 // DIS Disable 953 #define LGPT_IMASK_C1CC 0x00000200U 954 #define LGPT_IMASK_C1CC_M 0x00000200U 955 #define LGPT_IMASK_C1CC_S 9U 956 #define LGPT_IMASK_C1CC_EN 0x00000200U 957 #define LGPT_IMASK_C1CC_DIS 0x00000000U 958 959 // Field: [8] C0CC 960 // 961 // Enable RIS.C0CC interrupt. 962 // ENUMs: 963 // EN Enable 964 // DIS Disable 965 #define LGPT_IMASK_C0CC 0x00000100U 966 #define LGPT_IMASK_C0CC_M 0x00000100U 967 #define LGPT_IMASK_C0CC_S 8U 968 #define LGPT_IMASK_C0CC_EN 0x00000100U 969 #define LGPT_IMASK_C0CC_DIS 0x00000000U 970 971 // Field: [6] FAULT 972 // 973 // Enable RIS.FAULT interrupt. 974 // ENUMs: 975 // EN Enable 976 // DIS Disable 977 #define LGPT_IMASK_FAULT 0x00000040U 978 #define LGPT_IMASK_FAULT_M 0x00000040U 979 #define LGPT_IMASK_FAULT_S 6U 980 #define LGPT_IMASK_FAULT_EN 0x00000040U 981 #define LGPT_IMASK_FAULT_DIS 0x00000000U 982 983 // Field: [5] IDX 984 // 985 // Enable RIS.IDX interrupt. 986 // ENUMs: 987 // EN Enable 988 // DIS Disable 989 #define LGPT_IMASK_IDX 0x00000020U 990 #define LGPT_IMASK_IDX_M 0x00000020U 991 #define LGPT_IMASK_IDX_S 5U 992 #define LGPT_IMASK_IDX_EN 0x00000020U 993 #define LGPT_IMASK_IDX_DIS 0x00000000U 994 995 // Field: [4] DIRCHNG 996 // 997 // Enable RIS.DIRCHNG interrupt. 998 // ENUMs: 999 // EN Enable 1000 // DIS Disable 1001 #define LGPT_IMASK_DIRCHNG 0x00000010U 1002 #define LGPT_IMASK_DIRCHNG_M 0x00000010U 1003 #define LGPT_IMASK_DIRCHNG_S 4U 1004 #define LGPT_IMASK_DIRCHNG_EN 0x00000010U 1005 #define LGPT_IMASK_DIRCHNG_DIS 0x00000000U 1006 1007 // Field: [3] CNTRCHNG 1008 // 1009 // Enable RIS.CNTRCHNG interrupt. 1010 // ENUMs: 1011 // EN Enable 1012 // DIS Disable 1013 #define LGPT_IMASK_CNTRCHNG 0x00000008U 1014 #define LGPT_IMASK_CNTRCHNG_M 0x00000008U 1015 #define LGPT_IMASK_CNTRCHNG_S 3U 1016 #define LGPT_IMASK_CNTRCHNG_EN 0x00000008U 1017 #define LGPT_IMASK_CNTRCHNG_DIS 0x00000000U 1018 1019 // Field: [2] DBLTRANS 1020 // 1021 // Enable RIS.DBLTRANS interrupt. 1022 // ENUMs: 1023 // EN Enable 1024 // DIS Disable 1025 #define LGPT_IMASK_DBLTRANS 0x00000004U 1026 #define LGPT_IMASK_DBLTRANS_M 0x00000004U 1027 #define LGPT_IMASK_DBLTRANS_S 2U 1028 #define LGPT_IMASK_DBLTRANS_EN 0x00000004U 1029 #define LGPT_IMASK_DBLTRANS_DIS 0x00000000U 1030 1031 // Field: [1] ZERO 1032 // 1033 // Enable RIS.ZERO interrupt. 1034 // ENUMs: 1035 // EN Enable 1036 // DIS Disable 1037 #define LGPT_IMASK_ZERO 0x00000002U 1038 #define LGPT_IMASK_ZERO_M 0x00000002U 1039 #define LGPT_IMASK_ZERO_S 1U 1040 #define LGPT_IMASK_ZERO_EN 0x00000002U 1041 #define LGPT_IMASK_ZERO_DIS 0x00000000U 1042 1043 // Field: [0] TGT 1044 // 1045 // Enable RIS.TGT interrupt. 1046 // ENUMs: 1047 // EN Enable 1048 // DIS Disable 1049 #define LGPT_IMASK_TGT 0x00000001U 1050 #define LGPT_IMASK_TGT_M 0x00000001U 1051 #define LGPT_IMASK_TGT_S 0U 1052 #define LGPT_IMASK_TGT_EN 0x00000001U 1053 #define LGPT_IMASK_TGT_DIS 0x00000000U 1054 1055 //***************************************************************************** 1056 // 1057 // Register: LGPT_O_RIS 1058 // 1059 //***************************************************************************** 1060 // Field: [10] C2CC 1061 // 1062 // Status of the C2CC interrupt. The interrupt is set when C2CC has capture or 1063 // compare event. 1064 // ENUMs: 1065 // SET 1066 // CLR Cleared 1067 #define LGPT_RIS_C2CC 0x00000400U 1068 #define LGPT_RIS_C2CC_M 0x00000400U 1069 #define LGPT_RIS_C2CC_S 10U 1070 #define LGPT_RIS_C2CC_SET 0x00000400U 1071 #define LGPT_RIS_C2CC_CLR 0x00000000U 1072 1073 // Field: [9] C1CC 1074 // 1075 // Status of the C1CC interrupt. The interrupt is set when C1CC has capture or 1076 // compare event. 1077 // ENUMs: 1078 // SET 1079 // CLR Cleared 1080 #define LGPT_RIS_C1CC 0x00000200U 1081 #define LGPT_RIS_C1CC_M 0x00000200U 1082 #define LGPT_RIS_C1CC_S 9U 1083 #define LGPT_RIS_C1CC_SET 0x00000200U 1084 #define LGPT_RIS_C1CC_CLR 0x00000000U 1085 1086 // Field: [8] C0CC 1087 // 1088 // Status of the C0CC interrupt. The interrupt is set when C0CC has capture or 1089 // compare event. 1090 // ENUMs: 1091 // SET 1092 // CLR Cleared 1093 #define LGPT_RIS_C0CC 0x00000100U 1094 #define LGPT_RIS_C0CC_M 0x00000100U 1095 #define LGPT_RIS_C0CC_S 8U 1096 #define LGPT_RIS_C0CC_SET 0x00000100U 1097 #define LGPT_RIS_C0CC_CLR 0x00000000U 1098 1099 // Field: [6] FAULT 1100 // 1101 // Status of the FAULT interrupt. The interrupt is set immediately on active 1102 // fault input. 1103 // ENUMs: 1104 // SET 1105 // CLR Cleared 1106 #define LGPT_RIS_FAULT 0x00000040U 1107 #define LGPT_RIS_FAULT_M 0x00000040U 1108 #define LGPT_RIS_FAULT_S 6U 1109 #define LGPT_RIS_FAULT_SET 0x00000040U 1110 #define LGPT_RIS_FAULT_CLR 0x00000000U 1111 1112 // Field: [5] IDX 1113 // 1114 // Status of the IDX interrupt. The interrupt is set when IDX is active. 1115 // ENUMs: 1116 // SET 1117 // CLR Cleared 1118 #define LGPT_RIS_IDX 0x00000020U 1119 #define LGPT_RIS_IDX_M 0x00000020U 1120 #define LGPT_RIS_IDX_S 5U 1121 #define LGPT_RIS_IDX_SET 0x00000020U 1122 #define LGPT_RIS_IDX_CLR 0x00000000U 1123 1124 // Field: [4] DIRCHNG 1125 // 1126 // Status of the DIRCHNG interrupt. The interrupt is set when the direction of 1127 // the counter changes. 1128 // ENUMs: 1129 // SET 1130 // CLR Cleared 1131 #define LGPT_RIS_DIRCHNG 0x00000010U 1132 #define LGPT_RIS_DIRCHNG_M 0x00000010U 1133 #define LGPT_RIS_DIRCHNG_S 4U 1134 #define LGPT_RIS_DIRCHNG_SET 0x00000010U 1135 #define LGPT_RIS_DIRCHNG_CLR 0x00000000U 1136 1137 // Field: [3] CNTRCHNG 1138 // 1139 // Status of the CNTRCHNG interrupt. The interrupt is set when the counter 1140 // increments or decrements. 1141 // ENUMs: 1142 // SET 1143 // CLR Cleared 1144 #define LGPT_RIS_CNTRCHNG 0x00000008U 1145 #define LGPT_RIS_CNTRCHNG_M 0x00000008U 1146 #define LGPT_RIS_CNTRCHNG_S 3U 1147 #define LGPT_RIS_CNTRCHNG_SET 0x00000008U 1148 #define LGPT_RIS_CNTRCHNG_CLR 0x00000000U 1149 1150 // Field: [2] DBLTRANS 1151 // 1152 // Status of the DBLTRANS interrupt. The interrupt is set when a double 1153 // transition has happened during QDEC mode. 1154 // ENUMs: 1155 // SET 1156 // CLR Cleared 1157 #define LGPT_RIS_DBLTRANS 0x00000004U 1158 #define LGPT_RIS_DBLTRANS_M 0x00000004U 1159 #define LGPT_RIS_DBLTRANS_S 2U 1160 #define LGPT_RIS_DBLTRANS_SET 0x00000004U 1161 #define LGPT_RIS_DBLTRANS_CLR 0x00000000U 1162 1163 // Field: [1] ZERO 1164 // 1165 // Status of the ZERO interrupt. The interrupt is set when CNTR = 0. 1166 // ENUMs: 1167 // SET 1168 // CLR Cleared 1169 #define LGPT_RIS_ZERO 0x00000002U 1170 #define LGPT_RIS_ZERO_M 0x00000002U 1171 #define LGPT_RIS_ZERO_S 1U 1172 #define LGPT_RIS_ZERO_SET 0x00000002U 1173 #define LGPT_RIS_ZERO_CLR 0x00000000U 1174 1175 // Field: [0] TGT 1176 // 1177 // Status of the TGT interrupt. The interrupt is set when CNTR = TGT. 1178 // ENUMs: 1179 // SET 1180 // CLR Cleared 1181 #define LGPT_RIS_TGT 0x00000001U 1182 #define LGPT_RIS_TGT_M 0x00000001U 1183 #define LGPT_RIS_TGT_S 0U 1184 #define LGPT_RIS_TGT_SET 0x00000001U 1185 #define LGPT_RIS_TGT_CLR 0x00000000U 1186 1187 //***************************************************************************** 1188 // 1189 // Register: LGPT_O_MIS 1190 // 1191 //***************************************************************************** 1192 // Field: [10] C2CC 1193 // 1194 // Masked status of the RIS.C2CC interrupt. 1195 // ENUMs: 1196 // SET 1197 // CLR Cleared 1198 #define LGPT_MIS_C2CC 0x00000400U 1199 #define LGPT_MIS_C2CC_M 0x00000400U 1200 #define LGPT_MIS_C2CC_S 10U 1201 #define LGPT_MIS_C2CC_SET 0x00000400U 1202 #define LGPT_MIS_C2CC_CLR 0x00000000U 1203 1204 // Field: [9] C1CC 1205 // 1206 // Masked status of the RIS.C1CC interrupt. 1207 // ENUMs: 1208 // SET 1209 // CLR Cleared 1210 #define LGPT_MIS_C1CC 0x00000200U 1211 #define LGPT_MIS_C1CC_M 0x00000200U 1212 #define LGPT_MIS_C1CC_S 9U 1213 #define LGPT_MIS_C1CC_SET 0x00000200U 1214 #define LGPT_MIS_C1CC_CLR 0x00000000U 1215 1216 // Field: [8] C0CC 1217 // 1218 // Masked status of the RIS.C0CC interrupt. 1219 // ENUMs: 1220 // SET 1221 // CLR Cleared 1222 #define LGPT_MIS_C0CC 0x00000100U 1223 #define LGPT_MIS_C0CC_M 0x00000100U 1224 #define LGPT_MIS_C0CC_S 8U 1225 #define LGPT_MIS_C0CC_SET 0x00000100U 1226 #define LGPT_MIS_C0CC_CLR 0x00000000U 1227 1228 // Field: [6] FAULT 1229 // 1230 // Masked status of the RIS.FAULT interrupt. 1231 // ENUMs: 1232 // SET 1233 // CLR Cleared 1234 #define LGPT_MIS_FAULT 0x00000040U 1235 #define LGPT_MIS_FAULT_M 0x00000040U 1236 #define LGPT_MIS_FAULT_S 6U 1237 #define LGPT_MIS_FAULT_SET 0x00000040U 1238 #define LGPT_MIS_FAULT_CLR 0x00000000U 1239 1240 // Field: [5] IDX 1241 // 1242 // Masked status of the RIS.IDX interrupt. 1243 // ENUMs: 1244 // SET 1245 // CLR Cleared 1246 #define LGPT_MIS_IDX 0x00000020U 1247 #define LGPT_MIS_IDX_M 0x00000020U 1248 #define LGPT_MIS_IDX_S 5U 1249 #define LGPT_MIS_IDX_SET 0x00000020U 1250 #define LGPT_MIS_IDX_CLR 0x00000000U 1251 1252 // Field: [4] DIRCHNG 1253 // 1254 // Masked status of the RIS.DIRCHNG interrupt. 1255 // ENUMs: 1256 // SET 1257 // CLR Cleared 1258 #define LGPT_MIS_DIRCHNG 0x00000010U 1259 #define LGPT_MIS_DIRCHNG_M 0x00000010U 1260 #define LGPT_MIS_DIRCHNG_S 4U 1261 #define LGPT_MIS_DIRCHNG_SET 0x00000010U 1262 #define LGPT_MIS_DIRCHNG_CLR 0x00000000U 1263 1264 // Field: [3] CNTRCHNG 1265 // 1266 // Masked status of the RIS.CNTRCHNG interrupt. 1267 // ENUMs: 1268 // SET 1269 // CLR Cleared 1270 #define LGPT_MIS_CNTRCHNG 0x00000008U 1271 #define LGPT_MIS_CNTRCHNG_M 0x00000008U 1272 #define LGPT_MIS_CNTRCHNG_S 3U 1273 #define LGPT_MIS_CNTRCHNG_SET 0x00000008U 1274 #define LGPT_MIS_CNTRCHNG_CLR 0x00000000U 1275 1276 // Field: [2] DBLTRANS 1277 // 1278 // Masked status of the RIS.DBLTRANS interrupt. 1279 // ENUMs: 1280 // SET 1281 // CLR Cleared 1282 #define LGPT_MIS_DBLTRANS 0x00000004U 1283 #define LGPT_MIS_DBLTRANS_M 0x00000004U 1284 #define LGPT_MIS_DBLTRANS_S 2U 1285 #define LGPT_MIS_DBLTRANS_SET 0x00000004U 1286 #define LGPT_MIS_DBLTRANS_CLR 0x00000000U 1287 1288 // Field: [1] ZERO 1289 // 1290 // Masked status of the RIS.ZERO interrupt. 1291 // ENUMs: 1292 // SET 1293 // CLR Cleared 1294 #define LGPT_MIS_ZERO 0x00000002U 1295 #define LGPT_MIS_ZERO_M 0x00000002U 1296 #define LGPT_MIS_ZERO_S 1U 1297 #define LGPT_MIS_ZERO_SET 0x00000002U 1298 #define LGPT_MIS_ZERO_CLR 0x00000000U 1299 1300 // Field: [0] TGT 1301 // 1302 // Masked status of the RIS.TGT interrupt. 1303 // ENUMs: 1304 // SET 1305 // CLR Cleared 1306 #define LGPT_MIS_TGT 0x00000001U 1307 #define LGPT_MIS_TGT_M 0x00000001U 1308 #define LGPT_MIS_TGT_S 0U 1309 #define LGPT_MIS_TGT_SET 0x00000001U 1310 #define LGPT_MIS_TGT_CLR 0x00000000U 1311 1312 //***************************************************************************** 1313 // 1314 // Register: LGPT_O_ISET 1315 // 1316 //***************************************************************************** 1317 // Field: [10] C2CC 1318 // 1319 // Set the RIS.C2CC interrupt. 1320 // ENUMs: 1321 // SET 1322 // NO_EFFECT No effect 1323 #define LGPT_ISET_C2CC 0x00000400U 1324 #define LGPT_ISET_C2CC_M 0x00000400U 1325 #define LGPT_ISET_C2CC_S 10U 1326 #define LGPT_ISET_C2CC_SET 0x00000400U 1327 #define LGPT_ISET_C2CC_NO_EFFECT 0x00000000U 1328 1329 // Field: [9] C1CC 1330 // 1331 // Set the RIS.C1CC interrupt. 1332 // ENUMs: 1333 // SET 1334 // NO_EFFECT No effect 1335 #define LGPT_ISET_C1CC 0x00000200U 1336 #define LGPT_ISET_C1CC_M 0x00000200U 1337 #define LGPT_ISET_C1CC_S 9U 1338 #define LGPT_ISET_C1CC_SET 0x00000200U 1339 #define LGPT_ISET_C1CC_NO_EFFECT 0x00000000U 1340 1341 // Field: [8] C0CC 1342 // 1343 // Set the RIS.C0CC interrupt. 1344 // ENUMs: 1345 // SET 1346 // NO_EFFECT No effect 1347 #define LGPT_ISET_C0CC 0x00000100U 1348 #define LGPT_ISET_C0CC_M 0x00000100U 1349 #define LGPT_ISET_C0CC_S 8U 1350 #define LGPT_ISET_C0CC_SET 0x00000100U 1351 #define LGPT_ISET_C0CC_NO_EFFECT 0x00000000U 1352 1353 // Field: [6] FAULT 1354 // 1355 // Set the RIS.FAULT interrupt. 1356 // ENUMs: 1357 // SET 1358 // NO_EFFECT No effect 1359 #define LGPT_ISET_FAULT 0x00000040U 1360 #define LGPT_ISET_FAULT_M 0x00000040U 1361 #define LGPT_ISET_FAULT_S 6U 1362 #define LGPT_ISET_FAULT_SET 0x00000040U 1363 #define LGPT_ISET_FAULT_NO_EFFECT 0x00000000U 1364 1365 // Field: [5] IDX 1366 // 1367 // Set the RIS.IDX interrupt. 1368 // ENUMs: 1369 // SET 1370 // NO_EFFECT No effect 1371 #define LGPT_ISET_IDX 0x00000020U 1372 #define LGPT_ISET_IDX_M 0x00000020U 1373 #define LGPT_ISET_IDX_S 5U 1374 #define LGPT_ISET_IDX_SET 0x00000020U 1375 #define LGPT_ISET_IDX_NO_EFFECT 0x00000000U 1376 1377 // Field: [4] DIRCHNG 1378 // 1379 // Set the RIS.DIRCHNG interrupt. 1380 // ENUMs: 1381 // SET 1382 // NO_EFFECT No effect 1383 #define LGPT_ISET_DIRCHNG 0x00000010U 1384 #define LGPT_ISET_DIRCHNG_M 0x00000010U 1385 #define LGPT_ISET_DIRCHNG_S 4U 1386 #define LGPT_ISET_DIRCHNG_SET 0x00000010U 1387 #define LGPT_ISET_DIRCHNG_NO_EFFECT 0x00000000U 1388 1389 // Field: [3] CNTRCHNG 1390 // 1391 // Set the RIS.CNTRCHNG interrupt. 1392 // ENUMs: 1393 // SET 1394 // NO_EFFECT No effect 1395 #define LGPT_ISET_CNTRCHNG 0x00000008U 1396 #define LGPT_ISET_CNTRCHNG_M 0x00000008U 1397 #define LGPT_ISET_CNTRCHNG_S 3U 1398 #define LGPT_ISET_CNTRCHNG_SET 0x00000008U 1399 #define LGPT_ISET_CNTRCHNG_NO_EFFECT 0x00000000U 1400 1401 // Field: [2] DBLTRANS 1402 // 1403 // Set the RIS.DBLTRANS interrupt. 1404 // ENUMs: 1405 // SET 1406 // NO_EFFECT No effect 1407 #define LGPT_ISET_DBLTRANS 0x00000004U 1408 #define LGPT_ISET_DBLTRANS_M 0x00000004U 1409 #define LGPT_ISET_DBLTRANS_S 2U 1410 #define LGPT_ISET_DBLTRANS_SET 0x00000004U 1411 #define LGPT_ISET_DBLTRANS_NO_EFFECT 0x00000000U 1412 1413 // Field: [1] ZERO 1414 // 1415 // Set the RIS.ZERO interrupt. 1416 // ENUMs: 1417 // SET 1418 // NO_EFFECT No effect 1419 #define LGPT_ISET_ZERO 0x00000002U 1420 #define LGPT_ISET_ZERO_M 0x00000002U 1421 #define LGPT_ISET_ZERO_S 1U 1422 #define LGPT_ISET_ZERO_SET 0x00000002U 1423 #define LGPT_ISET_ZERO_NO_EFFECT 0x00000000U 1424 1425 // Field: [0] TGT 1426 // 1427 // Set the RIS.TGT interrupt. 1428 // ENUMs: 1429 // SET 1430 // NO_EFFECT No effect 1431 #define LGPT_ISET_TGT 0x00000001U 1432 #define LGPT_ISET_TGT_M 0x00000001U 1433 #define LGPT_ISET_TGT_S 0U 1434 #define LGPT_ISET_TGT_SET 0x00000001U 1435 #define LGPT_ISET_TGT_NO_EFFECT 0x00000000U 1436 1437 //***************************************************************************** 1438 // 1439 // Register: LGPT_O_ICLR 1440 // 1441 //***************************************************************************** 1442 // Field: [10] C2CC 1443 // 1444 // Clear the RIS.C2CC interrupt. 1445 // ENUMs: 1446 // CLR Clear 1447 // NO_EFFECT No effect 1448 #define LGPT_ICLR_C2CC 0x00000400U 1449 #define LGPT_ICLR_C2CC_M 0x00000400U 1450 #define LGPT_ICLR_C2CC_S 10U 1451 #define LGPT_ICLR_C2CC_CLR 0x00000400U 1452 #define LGPT_ICLR_C2CC_NO_EFFECT 0x00000000U 1453 1454 // Field: [9] C1CC 1455 // 1456 // Clear the RIS.C1CC interrupt. 1457 // ENUMs: 1458 // CLR Clear 1459 // NO_EFFECT No effect 1460 #define LGPT_ICLR_C1CC 0x00000200U 1461 #define LGPT_ICLR_C1CC_M 0x00000200U 1462 #define LGPT_ICLR_C1CC_S 9U 1463 #define LGPT_ICLR_C1CC_CLR 0x00000200U 1464 #define LGPT_ICLR_C1CC_NO_EFFECT 0x00000000U 1465 1466 // Field: [8] C0CC 1467 // 1468 // Clear the RIS.C0CC interrupt. 1469 // ENUMs: 1470 // CLR Clear 1471 // NO_EFFECT No effect 1472 #define LGPT_ICLR_C0CC 0x00000100U 1473 #define LGPT_ICLR_C0CC_M 0x00000100U 1474 #define LGPT_ICLR_C0CC_S 8U 1475 #define LGPT_ICLR_C0CC_CLR 0x00000100U 1476 #define LGPT_ICLR_C0CC_NO_EFFECT 0x00000000U 1477 1478 // Field: [6] FAULT 1479 // 1480 // Clear the RIS.FAULT interrupt. 1481 // ENUMs: 1482 // CLR Clear 1483 // NO_EFFECT No effect 1484 #define LGPT_ICLR_FAULT 0x00000040U 1485 #define LGPT_ICLR_FAULT_M 0x00000040U 1486 #define LGPT_ICLR_FAULT_S 6U 1487 #define LGPT_ICLR_FAULT_CLR 0x00000040U 1488 #define LGPT_ICLR_FAULT_NO_EFFECT 0x00000000U 1489 1490 // Field: [5] IDX 1491 // 1492 // Clear the RIS.IDX interrupt. 1493 // ENUMs: 1494 // CLR Clear 1495 // NO_EFFECT No effect 1496 #define LGPT_ICLR_IDX 0x00000020U 1497 #define LGPT_ICLR_IDX_M 0x00000020U 1498 #define LGPT_ICLR_IDX_S 5U 1499 #define LGPT_ICLR_IDX_CLR 0x00000020U 1500 #define LGPT_ICLR_IDX_NO_EFFECT 0x00000000U 1501 1502 // Field: [4] DIRCHNG 1503 // 1504 // Clear the RIS.DIRCHNG interrupt. 1505 // ENUMs: 1506 // CLR Clear 1507 // NO_EFFECT No effect 1508 #define LGPT_ICLR_DIRCHNG 0x00000010U 1509 #define LGPT_ICLR_DIRCHNG_M 0x00000010U 1510 #define LGPT_ICLR_DIRCHNG_S 4U 1511 #define LGPT_ICLR_DIRCHNG_CLR 0x00000010U 1512 #define LGPT_ICLR_DIRCHNG_NO_EFFECT 0x00000000U 1513 1514 // Field: [3] CNTRCHNG 1515 // 1516 // Clear the RIS.CNTRCHNG interrupt. 1517 // ENUMs: 1518 // CLR Clear 1519 // NO_EFFECT No effect 1520 #define LGPT_ICLR_CNTRCHNG 0x00000008U 1521 #define LGPT_ICLR_CNTRCHNG_M 0x00000008U 1522 #define LGPT_ICLR_CNTRCHNG_S 3U 1523 #define LGPT_ICLR_CNTRCHNG_CLR 0x00000008U 1524 #define LGPT_ICLR_CNTRCHNG_NO_EFFECT 0x00000000U 1525 1526 // Field: [2] DBLTRANS 1527 // 1528 // Clear the RIS.DBLTRANS interrupt. 1529 // ENUMs: 1530 // CLR Clear 1531 // NO_EFFECT No effect 1532 #define LGPT_ICLR_DBLTRANS 0x00000004U 1533 #define LGPT_ICLR_DBLTRANS_M 0x00000004U 1534 #define LGPT_ICLR_DBLTRANS_S 2U 1535 #define LGPT_ICLR_DBLTRANS_CLR 0x00000004U 1536 #define LGPT_ICLR_DBLTRANS_NO_EFFECT 0x00000000U 1537 1538 // Field: [1] ZERO 1539 // 1540 // Clear the RIS.ZERO interrupt. 1541 // ENUMs: 1542 // CLR Clear 1543 // NO_EFFECT No effect 1544 #define LGPT_ICLR_ZERO 0x00000002U 1545 #define LGPT_ICLR_ZERO_M 0x00000002U 1546 #define LGPT_ICLR_ZERO_S 1U 1547 #define LGPT_ICLR_ZERO_CLR 0x00000002U 1548 #define LGPT_ICLR_ZERO_NO_EFFECT 0x00000000U 1549 1550 // Field: [0] TGT 1551 // 1552 // Clear the RIS.TGT interrupt. 1553 // ENUMs: 1554 // CLR Clear 1555 // NO_EFFECT No effect 1556 #define LGPT_ICLR_TGT 0x00000001U 1557 #define LGPT_ICLR_TGT_M 0x00000001U 1558 #define LGPT_ICLR_TGT_S 0U 1559 #define LGPT_ICLR_TGT_CLR 0x00000001U 1560 #define LGPT_ICLR_TGT_NO_EFFECT 0x00000000U 1561 1562 //***************************************************************************** 1563 // 1564 // Register: LGPT_O_IMSET 1565 // 1566 //***************************************************************************** 1567 // Field: [10] C2CC 1568 // 1569 // Set the MIS.C2CC mask. 1570 // ENUMs: 1571 // SET 1572 // NO_EFFECT No effect 1573 #define LGPT_IMSET_C2CC 0x00000400U 1574 #define LGPT_IMSET_C2CC_M 0x00000400U 1575 #define LGPT_IMSET_C2CC_S 10U 1576 #define LGPT_IMSET_C2CC_SET 0x00000400U 1577 #define LGPT_IMSET_C2CC_NO_EFFECT 0x00000000U 1578 1579 // Field: [9] C1CC 1580 // 1581 // Set the MIS.C1CC mask. 1582 // ENUMs: 1583 // SET 1584 // NO_EFFECT No effect 1585 #define LGPT_IMSET_C1CC 0x00000200U 1586 #define LGPT_IMSET_C1CC_M 0x00000200U 1587 #define LGPT_IMSET_C1CC_S 9U 1588 #define LGPT_IMSET_C1CC_SET 0x00000200U 1589 #define LGPT_IMSET_C1CC_NO_EFFECT 0x00000000U 1590 1591 // Field: [8] C0CC 1592 // 1593 // Set the MIS.C0CC mask. 1594 // ENUMs: 1595 // SET 1596 // NO_EFFECT No effect 1597 #define LGPT_IMSET_C0CC 0x00000100U 1598 #define LGPT_IMSET_C0CC_M 0x00000100U 1599 #define LGPT_IMSET_C0CC_S 8U 1600 #define LGPT_IMSET_C0CC_SET 0x00000100U 1601 #define LGPT_IMSET_C0CC_NO_EFFECT 0x00000000U 1602 1603 // Field: [6] FAULT 1604 // 1605 // Set the MIS.FAULT mask. 1606 // ENUMs: 1607 // SET 1608 // NO_EFFECT No effect 1609 #define LGPT_IMSET_FAULT 0x00000040U 1610 #define LGPT_IMSET_FAULT_M 0x00000040U 1611 #define LGPT_IMSET_FAULT_S 6U 1612 #define LGPT_IMSET_FAULT_SET 0x00000040U 1613 #define LGPT_IMSET_FAULT_NO_EFFECT 0x00000000U 1614 1615 // Field: [5] IDX 1616 // 1617 // Set the MIS.IDX mask. 1618 // ENUMs: 1619 // SET 1620 // NO_EFFECT No effect 1621 #define LGPT_IMSET_IDX 0x00000020U 1622 #define LGPT_IMSET_IDX_M 0x00000020U 1623 #define LGPT_IMSET_IDX_S 5U 1624 #define LGPT_IMSET_IDX_SET 0x00000020U 1625 #define LGPT_IMSET_IDX_NO_EFFECT 0x00000000U 1626 1627 // Field: [4] DIRCHNG 1628 // 1629 // Set the MIS.DIRCHNG mask. 1630 // ENUMs: 1631 // SET 1632 // NO_EFFECT No effect 1633 #define LGPT_IMSET_DIRCHNG 0x00000010U 1634 #define LGPT_IMSET_DIRCHNG_M 0x00000010U 1635 #define LGPT_IMSET_DIRCHNG_S 4U 1636 #define LGPT_IMSET_DIRCHNG_SET 0x00000010U 1637 #define LGPT_IMSET_DIRCHNG_NO_EFFECT 0x00000000U 1638 1639 // Field: [3] CNTRCHNG 1640 // 1641 // Set the MIS.CNTRCHNG mask. 1642 // ENUMs: 1643 // SET 1644 // NO_EFFECT No effect 1645 #define LGPT_IMSET_CNTRCHNG 0x00000008U 1646 #define LGPT_IMSET_CNTRCHNG_M 0x00000008U 1647 #define LGPT_IMSET_CNTRCHNG_S 3U 1648 #define LGPT_IMSET_CNTRCHNG_SET 0x00000008U 1649 #define LGPT_IMSET_CNTRCHNG_NO_EFFECT 0x00000000U 1650 1651 // Field: [2] DBLTRANS 1652 // 1653 // Set the MIS.DBLTRANS mask. 1654 // ENUMs: 1655 // SET 1656 // NO_EFFECT No effect 1657 #define LGPT_IMSET_DBLTRANS 0x00000004U 1658 #define LGPT_IMSET_DBLTRANS_M 0x00000004U 1659 #define LGPT_IMSET_DBLTRANS_S 2U 1660 #define LGPT_IMSET_DBLTRANS_SET 0x00000004U 1661 #define LGPT_IMSET_DBLTRANS_NO_EFFECT 0x00000000U 1662 1663 // Field: [1] ZERO 1664 // 1665 // Set the MIS.ZERO mask. 1666 // ENUMs: 1667 // SET 1668 // NO_EFFECT No effect 1669 #define LGPT_IMSET_ZERO 0x00000002U 1670 #define LGPT_IMSET_ZERO_M 0x00000002U 1671 #define LGPT_IMSET_ZERO_S 1U 1672 #define LGPT_IMSET_ZERO_SET 0x00000002U 1673 #define LGPT_IMSET_ZERO_NO_EFFECT 0x00000000U 1674 1675 // Field: [0] TGT 1676 // 1677 // Set the MIS.TGT mask. 1678 // ENUMs: 1679 // SET 1680 // NO_EFFECT No effect 1681 #define LGPT_IMSET_TGT 0x00000001U 1682 #define LGPT_IMSET_TGT_M 0x00000001U 1683 #define LGPT_IMSET_TGT_S 0U 1684 #define LGPT_IMSET_TGT_SET 0x00000001U 1685 #define LGPT_IMSET_TGT_NO_EFFECT 0x00000000U 1686 1687 //***************************************************************************** 1688 // 1689 // Register: LGPT_O_IMCLR 1690 // 1691 //***************************************************************************** 1692 // Field: [10] C2CC 1693 // 1694 // Clear the MIS.C2CC mask. 1695 // ENUMs: 1696 // CLR Clear 1697 // NO_EFFECT No effect 1698 #define LGPT_IMCLR_C2CC 0x00000400U 1699 #define LGPT_IMCLR_C2CC_M 0x00000400U 1700 #define LGPT_IMCLR_C2CC_S 10U 1701 #define LGPT_IMCLR_C2CC_CLR 0x00000400U 1702 #define LGPT_IMCLR_C2CC_NO_EFFECT 0x00000000U 1703 1704 // Field: [9] C1CC 1705 // 1706 // Clear the MIS.C1CC mask. 1707 // ENUMs: 1708 // CLR Clear 1709 // NO_EFFECT No effect 1710 #define LGPT_IMCLR_C1CC 0x00000200U 1711 #define LGPT_IMCLR_C1CC_M 0x00000200U 1712 #define LGPT_IMCLR_C1CC_S 9U 1713 #define LGPT_IMCLR_C1CC_CLR 0x00000200U 1714 #define LGPT_IMCLR_C1CC_NO_EFFECT 0x00000000U 1715 1716 // Field: [8] C0CC 1717 // 1718 // Clear the MIS.C0CC mask. 1719 // ENUMs: 1720 // CLR Clear 1721 // NO_EFFECT No effect 1722 #define LGPT_IMCLR_C0CC 0x00000100U 1723 #define LGPT_IMCLR_C0CC_M 0x00000100U 1724 #define LGPT_IMCLR_C0CC_S 8U 1725 #define LGPT_IMCLR_C0CC_CLR 0x00000100U 1726 #define LGPT_IMCLR_C0CC_NO_EFFECT 0x00000000U 1727 1728 // Field: [6] FAULT 1729 // 1730 // Clear the MIS.FAULT mask. 1731 // ENUMs: 1732 // CLR Clear 1733 // NO_EFFECT No effect 1734 #define LGPT_IMCLR_FAULT 0x00000040U 1735 #define LGPT_IMCLR_FAULT_M 0x00000040U 1736 #define LGPT_IMCLR_FAULT_S 6U 1737 #define LGPT_IMCLR_FAULT_CLR 0x00000040U 1738 #define LGPT_IMCLR_FAULT_NO_EFFECT 0x00000000U 1739 1740 // Field: [5] IDX 1741 // 1742 // Clear the MIS.IDX mask. 1743 // ENUMs: 1744 // CLR Clear 1745 // NO_EFFECT No effect 1746 #define LGPT_IMCLR_IDX 0x00000020U 1747 #define LGPT_IMCLR_IDX_M 0x00000020U 1748 #define LGPT_IMCLR_IDX_S 5U 1749 #define LGPT_IMCLR_IDX_CLR 0x00000020U 1750 #define LGPT_IMCLR_IDX_NO_EFFECT 0x00000000U 1751 1752 // Field: [4] DIRCHNG 1753 // 1754 // Clear the MIS.DIRCHNG mask. 1755 // ENUMs: 1756 // CLR Clear 1757 // NO_EFFECT No effect 1758 #define LGPT_IMCLR_DIRCHNG 0x00000010U 1759 #define LGPT_IMCLR_DIRCHNG_M 0x00000010U 1760 #define LGPT_IMCLR_DIRCHNG_S 4U 1761 #define LGPT_IMCLR_DIRCHNG_CLR 0x00000010U 1762 #define LGPT_IMCLR_DIRCHNG_NO_EFFECT 0x00000000U 1763 1764 // Field: [3] CNTRCHNG 1765 // 1766 // Clear the MIS.CNTRCHNG mask. 1767 // ENUMs: 1768 // CLR Clear 1769 // NO_EFFECT No effect 1770 #define LGPT_IMCLR_CNTRCHNG 0x00000008U 1771 #define LGPT_IMCLR_CNTRCHNG_M 0x00000008U 1772 #define LGPT_IMCLR_CNTRCHNG_S 3U 1773 #define LGPT_IMCLR_CNTRCHNG_CLR 0x00000008U 1774 #define LGPT_IMCLR_CNTRCHNG_NO_EFFECT 0x00000000U 1775 1776 // Field: [2] DBLTRANS 1777 // 1778 // Clear the MIS.DBLTRANS mask. 1779 // ENUMs: 1780 // CLR Clear 1781 // NO_EFFECT No effect 1782 #define LGPT_IMCLR_DBLTRANS 0x00000004U 1783 #define LGPT_IMCLR_DBLTRANS_M 0x00000004U 1784 #define LGPT_IMCLR_DBLTRANS_S 2U 1785 #define LGPT_IMCLR_DBLTRANS_CLR 0x00000004U 1786 #define LGPT_IMCLR_DBLTRANS_NO_EFFECT 0x00000000U 1787 1788 // Field: [1] ZERO 1789 // 1790 // Clear the MIS.ZERO mask. 1791 // ENUMs: 1792 // CLR Clear 1793 // NO_EFFECT No effect 1794 #define LGPT_IMCLR_ZERO 0x00000002U 1795 #define LGPT_IMCLR_ZERO_M 0x00000002U 1796 #define LGPT_IMCLR_ZERO_S 1U 1797 #define LGPT_IMCLR_ZERO_CLR 0x00000002U 1798 #define LGPT_IMCLR_ZERO_NO_EFFECT 0x00000000U 1799 1800 // Field: [0] TGT 1801 // 1802 // Clear the MIS.TGT mask. 1803 // ENUMs: 1804 // CLR Clear 1805 // NO_EFFECT No effect 1806 #define LGPT_IMCLR_TGT 0x00000001U 1807 #define LGPT_IMCLR_TGT_M 0x00000001U 1808 #define LGPT_IMCLR_TGT_S 0U 1809 #define LGPT_IMCLR_TGT_CLR 0x00000001U 1810 #define LGPT_IMCLR_TGT_NO_EFFECT 0x00000000U 1811 1812 //***************************************************************************** 1813 // 1814 // Register: LGPT_O_EMU 1815 // 1816 //***************************************************************************** 1817 // Field: [1] CTL 1818 // 1819 // Halt control. 1820 // 1821 // Configure when the counter shall stop upon CPU halt. This bitfield only 1822 // applies if HALT = 1. 1823 // ENUMs: 1824 // ZERCOND Zero condition. The counter stops when CNTR = 0. 1825 // IMMEDIATE Immediate reaction. The counter stops immediately 1826 // on debug halt. 1827 #define LGPT_EMU_CTL 0x00000002U 1828 #define LGPT_EMU_CTL_M 0x00000002U 1829 #define LGPT_EMU_CTL_S 1U 1830 #define LGPT_EMU_CTL_ZERCOND 0x00000002U 1831 #define LGPT_EMU_CTL_IMMEDIATE 0x00000000U 1832 1833 // Field: [0] HALT 1834 // 1835 // Halt LGPT when CPU is halted in debug. 1836 // ENUMs: 1837 // EN Enable. 1838 // DIS Disable. 1839 #define LGPT_EMU_HALT 0x00000001U 1840 #define LGPT_EMU_HALT_M 0x00000001U 1841 #define LGPT_EMU_HALT_S 0U 1842 #define LGPT_EMU_HALT_EN 0x00000001U 1843 #define LGPT_EMU_HALT_DIS 0x00000000U 1844 1845 //***************************************************************************** 1846 // 1847 // Register: LGPT_O_C0CFG 1848 // 1849 //***************************************************************************** 1850 // Field: [10] OUT2 1851 // 1852 // Output 2 enable. 1853 // 1854 // When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event. 1855 // ENUMs: 1856 // EN Channel 0 controls output 2. 1857 // DIS Channel 0 does not control output 2. 1858 #define LGPT_C0CFG_OUT2 0x00000400U 1859 #define LGPT_C0CFG_OUT2_M 0x00000400U 1860 #define LGPT_C0CFG_OUT2_S 10U 1861 #define LGPT_C0CFG_OUT2_EN 0x00000400U 1862 #define LGPT_C0CFG_OUT2_DIS 0x00000000U 1863 1864 // Field: [9] OUT1 1865 // 1866 // Output 1 enable. 1867 // 1868 // When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event. 1869 // ENUMs: 1870 // EN Channel 0 controls output 1. 1871 // DIS Channel 0 does not control output 1. 1872 #define LGPT_C0CFG_OUT1 0x00000200U 1873 #define LGPT_C0CFG_OUT1_M 0x00000200U 1874 #define LGPT_C0CFG_OUT1_S 9U 1875 #define LGPT_C0CFG_OUT1_EN 0x00000200U 1876 #define LGPT_C0CFG_OUT1_DIS 0x00000000U 1877 1878 // Field: [8] OUT0 1879 // 1880 // Output 0 enable. 1881 // 1882 // When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event. 1883 // ENUMs: 1884 // EN Channel 0 controls output 0. 1885 // DIS Channel 0 does not control output 0. 1886 #define LGPT_C0CFG_OUT0 0x00000100U 1887 #define LGPT_C0CFG_OUT0_M 0x00000100U 1888 #define LGPT_C0CFG_OUT0_S 8U 1889 #define LGPT_C0CFG_OUT0_EN 0x00000100U 1890 #define LGPT_C0CFG_OUT0_DIS 0x00000000U 1891 1892 // Field: [6] INPUT 1893 // 1894 // Select channel input. 1895 // ENUMs: 1896 // IO IO controller 1897 // EV Event fabric 1898 #define LGPT_C0CFG_INPUT 0x00000040U 1899 #define LGPT_C0CFG_INPUT_M 0x00000040U 1900 #define LGPT_C0CFG_INPUT_S 6U 1901 #define LGPT_C0CFG_INPUT_IO 0x00000040U 1902 #define LGPT_C0CFG_INPUT_EV 0x00000000U 1903 1904 // Field: [5:4] EDGE 1905 // 1906 // Determines the edge that triggers the channel input event. This happens post 1907 // filter. 1908 // ENUMs: 1909 // BOTH Input event is triggered at both edges. 1910 // FALL Input event is triggered at falling edge. 1911 // RISE Input event is triggered at rising edge. 1912 // NONE Input is turned off. 1913 #define LGPT_C0CFG_EDGE_W 2U 1914 #define LGPT_C0CFG_EDGE_M 0x00000030U 1915 #define LGPT_C0CFG_EDGE_S 4U 1916 #define LGPT_C0CFG_EDGE_BOTH 0x00000030U 1917 #define LGPT_C0CFG_EDGE_FALL 0x00000020U 1918 #define LGPT_C0CFG_EDGE_RISE 0x00000010U 1919 #define LGPT_C0CFG_EDGE_NONE 0x00000000U 1920 1921 // Field: [3:0] CCACT 1922 // 1923 // Capture-Compare action. 1924 // 1925 // Capture-Compare action defines 15 different channel functions that utilize 1926 // capture, compare, and zero events. In every compare event the timer looks at 1927 // the current value of CNTR. The corresponding output event will be set 1 1928 // timer period after CNTR = C0CC. 1929 // ENUMs: 1930 // PULSE_ON_CMP Pulse on compare repeatedly. 1931 // 1932 // Channel function 1933 // sequence: 1934 // - Pulse enabled outputs 1935 // when C0CC.VAL = CNTR.VAL. 1936 // 1937 // The output is high for 1938 // two timer clock periods. 1939 // TGL_ON_CMP Toggle on compare repeatedly. 1940 // 1941 // Channel function 1942 // sequence: 1943 // - Toggle enabled outputs 1944 // when C0CC.VAL = CNTR.VAL. 1945 // SET_ON_CMP Set on compare repeatedly. 1946 // 1947 // Channel function 1948 // sequence: 1949 // - Set enabled outputs 1950 // when C0CC.VAL = CNTR.VAL. 1951 // CLR_ON_CMP Clear on compare repeatedly. 1952 // 1953 // Channel function 1954 // sequence: 1955 // - Clear enabled outputs 1956 // when C0CC.VAL = CNTR.VAL. 1957 // SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. 1958 // 1959 // Channel function 1960 // sequence: 1961 // - Set enabled outputs 1962 // when CNTR.VAL = 0. 1963 // - Toggle enabled outputs 1964 // when C0CC.VAL = CNTR.VAL. 1965 // 1966 // Set CTL.MODE to UP_PER 1967 // for edge-aligned PWM generation. Duty cycle is 1968 // given by: 1969 // 1970 // When C0CC.VAL <= TGT.VAL: 1971 // Duty cycle = C0CC.VAL 1972 // / ( TGT.VAL + 1 ). 1973 // 1974 // When C0CC.VAL > TGT.VAL: 1975 // Duty cycle = 1. 1976 // 1977 // Enabled outputs are 1978 // cleared when C0CC.VAL = 0 and CNTR.VAL = 0. 1979 // CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. 1980 // 1981 // Channel function 1982 // sequence: 1983 // - Clear enabled outputs 1984 // when CNTR.VAL = 0. 1985 // - Toggle enabled outputs 1986 // when C0CC.VAL = CNTR.VAL. 1987 // 1988 // Set CTL.MODE to UPDWN_PER 1989 // for center-aligned PWM generation. Duty cycle 1990 // is given by: 1991 // 1992 // When C0CC.VAL <= TGT.VAL: 1993 // Duty cycle = 1 - ( 1994 // C0CC.VAL / TGT.VAL ). 1995 // 1996 // When C0CC.VAL > TGT.VAL: 1997 // Duty cycle = 0. 1998 // 1999 // Enabled outputs are set 2000 // when C0CC.VAL = 0 and CNTR.VAL = 0. 2001 // SET_ON_CAPT Set on capture repeatedly. 2002 // 2003 // Channel function 2004 // sequence: 2005 // - Set enabled outputs on 2006 // capture event and copy CNTR.VAL to C0CC.VAL. 2007 // PER_PULSE_WIDTH_MEAS Period and pulse width measurement. 2008 // 2009 // Continuously capture 2010 // period and pulse width of the signal selected 2011 // by INPUT relative to the signal edge given by 2012 // EDGE. 2013 // 2014 // Set enabled outputs and 2015 // RIS.C0CC when C0CC.VAL contains signal period 2016 // and PC0CC.VAL contains signal pulse width. 2017 // 2018 // Notes: 2019 // - Make sure to configure 2020 // INPUT and CCACT when CTL.MODE equals DIS, then 2021 // set CTL.MODE to UP_ONCE or UP_PER. 2022 // - The counter restarts in 2023 // the selected timer mode when C0CC.VAL contains 2024 // the signal period. 2025 // - If more than one 2026 // channel uses this function, the channels will 2027 // perform this function one at a time. The 2028 // channel with lowest number has priority and 2029 // performs the function first. Next measurement 2030 // starts when current measurement completes 2031 // successfully or times out. A timeout occurs 2032 // when counter equals target. 2033 // - To observe a timeout 2034 // event the RIS.TGT interrupt can be used, or 2035 // another channel can be configured to SET_ON_CMP 2036 // with compare value equal TGT. 2037 // 2038 // Signal property 2039 // requirements: 2040 // - Signal Period >= 2 * ( 2041 // 1 + PRECFG.TICKDIV ) * timer clock period. 2042 // - Signal Period <= 2043 // MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock 2044 // period. 2045 // - Signal low and high 2046 // phase >= (1 + PRECFG.TICKDIV ) * timer clock 2047 // period. 2048 // PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. 2049 // 2050 // Channel function 2051 // sequence: 2052 // - Pulse enabled outputs 2053 // when C0CC.VAL = CNTR.VAL. 2054 // - Disable channel. 2055 // 2056 // The output is high for 2057 // two timer clock periods. 2058 // TGL_ON_CMP_DIS Toggle on compare, and then disable channel. 2059 // 2060 // Channel function 2061 // sequence: 2062 // - Toggle enabled outputs 2063 // when C0CC.VAL = CNTR.VAL. 2064 // - Disable channel. 2065 // SET_ON_CMP_DIS Set on compare, and then disable channel. 2066 // 2067 // Channel function 2068 // sequence: 2069 // - Set enabled outputs 2070 // when C0CC.VAL = CNTR.VAL. 2071 // - Disable channel. 2072 // CLR_ON_CMP_DIS Clear on compare, and then disable channel. 2073 // 2074 // Channel function 2075 // sequence: 2076 // - Clear enabled outputs 2077 // when C0CC.VAL = CNTR.VAL. 2078 // - Disable channel. 2079 // SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable 2080 // channel. 2081 // 2082 // Channel function 2083 // sequence: 2084 // - Set enabled outputs 2085 // when CNTR.VAL = 0. 2086 // - Toggle enabled outputs 2087 // when C0CC.VAL = CNTR.VAL. 2088 // - Disable channel. 2089 // 2090 // Enabled outputs are 2091 // cleared when C0CC.VAL = 0 and CNTR.VAL = 0. 2092 // CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable 2093 // channel. 2094 // 2095 // Channel function 2096 // sequence: 2097 // - Clear enabled outputs 2098 // when CNTR.VAL = 0. 2099 // - Toggle enabled outputs 2100 // when C0CC.VAL = CNTR.VAL. 2101 // - Disable channel. 2102 // 2103 // Enabled outputs are set 2104 // when C0CC.VAL = 0 and CNTR.VAL = 0. 2105 // SET_ON_CAPT_DIS Set on capture, and then disable channel. 2106 // 2107 // Channel function 2108 // sequence: 2109 // - Set enabled outputs on 2110 // capture event and copy CNTR.VAL to C0CC.VAL. 2111 // - Disable channel. 2112 // 2113 // Primary use scenario is 2114 // to select this function before starting the 2115 // timer. 2116 // Follow these steps to 2117 // select this function while CTL.MODE is 2118 // different from DIS: 2119 // - Set CCACT to 2120 // SET_ON_CAPT with no output enable. 2121 // - Configure INPUT 2122 // (optional). 2123 // - Wait for three timer 2124 // clock periods as defined in PRECFG before 2125 // setting CCACT to SET_ON_CAPT_DIS. Output enable 2126 // is optional. 2127 // 2128 // These steps prevent 2129 // capture events caused by expired signal values 2130 // in edge-detection circuit. 2131 // DIS Disable channel. 2132 #define LGPT_C0CFG_CCACT_W 4U 2133 #define LGPT_C0CFG_CCACT_M 0x0000000FU 2134 #define LGPT_C0CFG_CCACT_S 0U 2135 #define LGPT_C0CFG_CCACT_PULSE_ON_CMP 0x0000000FU 2136 #define LGPT_C0CFG_CCACT_TGL_ON_CMP 0x0000000EU 2137 #define LGPT_C0CFG_CCACT_SET_ON_CMP 0x0000000DU 2138 #define LGPT_C0CFG_CCACT_CLR_ON_CMP 0x0000000CU 2139 #define LGPT_C0CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU 2140 #define LGPT_C0CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU 2141 #define LGPT_C0CFG_CCACT_SET_ON_CAPT 0x00000009U 2142 #define LGPT_C0CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U 2143 #define LGPT_C0CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U 2144 #define LGPT_C0CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U 2145 #define LGPT_C0CFG_CCACT_SET_ON_CMP_DIS 0x00000005U 2146 #define LGPT_C0CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U 2147 #define LGPT_C0CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U 2148 #define LGPT_C0CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U 2149 #define LGPT_C0CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U 2150 #define LGPT_C0CFG_CCACT_DIS 0x00000000U 2151 2152 //***************************************************************************** 2153 // 2154 // Register: LGPT_O_C1CFG 2155 // 2156 //***************************************************************************** 2157 // Field: [10] OUT2 2158 // 2159 // Output 2 enable. 2160 // 2161 // When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event. 2162 // ENUMs: 2163 // EN Channel 1 controls output 2. 2164 // DIS Channel 1 does not control output 2. 2165 #define LGPT_C1CFG_OUT2 0x00000400U 2166 #define LGPT_C1CFG_OUT2_M 0x00000400U 2167 #define LGPT_C1CFG_OUT2_S 10U 2168 #define LGPT_C1CFG_OUT2_EN 0x00000400U 2169 #define LGPT_C1CFG_OUT2_DIS 0x00000000U 2170 2171 // Field: [9] OUT1 2172 // 2173 // Output 1 enable. 2174 // 2175 // When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event. 2176 // ENUMs: 2177 // EN Channel 1 controls output 1. 2178 // DIS Channel 1 does not control output 1. 2179 #define LGPT_C1CFG_OUT1 0x00000200U 2180 #define LGPT_C1CFG_OUT1_M 0x00000200U 2181 #define LGPT_C1CFG_OUT1_S 9U 2182 #define LGPT_C1CFG_OUT1_EN 0x00000200U 2183 #define LGPT_C1CFG_OUT1_DIS 0x00000000U 2184 2185 // Field: [8] OUT0 2186 // 2187 // Output 0 enable. 2188 // When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event. 2189 // ENUMs: 2190 // EN Channel 1 controls output 0. 2191 // DIS Channel 1 does not control output 0. 2192 #define LGPT_C1CFG_OUT0 0x00000100U 2193 #define LGPT_C1CFG_OUT0_M 0x00000100U 2194 #define LGPT_C1CFG_OUT0_S 8U 2195 #define LGPT_C1CFG_OUT0_EN 0x00000100U 2196 #define LGPT_C1CFG_OUT0_DIS 0x00000000U 2197 2198 // Field: [6] INPUT 2199 // 2200 // Select channel input. 2201 // ENUMs: 2202 // IO IO controller 2203 // EV Event fabric 2204 #define LGPT_C1CFG_INPUT 0x00000040U 2205 #define LGPT_C1CFG_INPUT_M 0x00000040U 2206 #define LGPT_C1CFG_INPUT_S 6U 2207 #define LGPT_C1CFG_INPUT_IO 0x00000040U 2208 #define LGPT_C1CFG_INPUT_EV 0x00000000U 2209 2210 // Field: [5:4] EDGE 2211 // 2212 // Determines the edge that triggers the channel input event. This happens post 2213 // filter. 2214 // ENUMs: 2215 // BOTH Input event is triggered at both edges. 2216 // FALL Input event is triggered at falling edge. 2217 // RISE Input event is triggered at rising edge. 2218 // NONE Input is turned off. 2219 #define LGPT_C1CFG_EDGE_W 2U 2220 #define LGPT_C1CFG_EDGE_M 0x00000030U 2221 #define LGPT_C1CFG_EDGE_S 4U 2222 #define LGPT_C1CFG_EDGE_BOTH 0x00000030U 2223 #define LGPT_C1CFG_EDGE_FALL 0x00000020U 2224 #define LGPT_C1CFG_EDGE_RISE 0x00000010U 2225 #define LGPT_C1CFG_EDGE_NONE 0x00000000U 2226 2227 // Field: [3:0] CCACT 2228 // 2229 // Capture-Compare action. 2230 // 2231 // Capture-Compare action defines 15 different channel functions that utilize 2232 // capture, compare, and zero events. In every compare event the timer looks at 2233 // the current value of CNTR. The corresponding output event will be set 1 2234 // timer period after CNTR = C1CC. 2235 // ENUMs: 2236 // PULSE_ON_CMP Pulse on compare repeatedly. 2237 // 2238 // Channel function 2239 // sequence: 2240 // - Pulse enabled outputs 2241 // when C1CC.VAL = CNTR.VAL. 2242 // 2243 // The output is high for 2244 // two timer clock periods. 2245 // TGL_ON_CMP Toggle on compare repeatedly. 2246 // 2247 // Channel function 2248 // sequence: 2249 // - Toggle enabled outputs 2250 // when C1CC.VAL = CNTR.VAL. 2251 // SET_ON_CMP Set on compare repeatedly. 2252 // 2253 // Channel function 2254 // sequence: 2255 // - Set enabled outputs 2256 // when C1CC.VAL = CNTR.VAL. 2257 // CLR_ON_CMP Clear on compare repeatedly. 2258 // 2259 // Channel function 2260 // sequence: 2261 // - Clear enabled outputs 2262 // when C1CC.VAL = CNTR.VAL. 2263 // SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. 2264 // 2265 // Channel function 2266 // sequence: 2267 // - Set enabled outputs 2268 // when CNTR.VAL = 0. 2269 // - Toggle enabled outputs 2270 // when C1CC.VAL = CNTR.VAL. 2271 // 2272 // Set CTL.MODE to UP_PER 2273 // for edge-aligned PWM generation. Duty cycle is 2274 // given by: 2275 // 2276 // When C1CC.VAL <= TGT.VAL: 2277 // Duty cycle = C1CC.VAL 2278 // / ( TGT.VAL + 1 ). 2279 // 2280 // When C1CC.VAL > TGT.VAL: 2281 // Duty cycle = 1. 2282 // 2283 // Enabled outputs are 2284 // cleared when C1CC.VAL = 0 and CNTR.VAL = 0. 2285 // CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. 2286 // 2287 // Channel function 2288 // sequence: 2289 // - Clear enabled outputs 2290 // when CNTR.VAL = 0. 2291 // - Toggle enabled outputs 2292 // when C1CC.VAL = CNTR.VAL. 2293 // 2294 // Set CTL.MODE to UPDWN_PER 2295 // for center-aligned PWM generation. Duty cycle 2296 // is given by: 2297 // 2298 // When C1CC.VAL <= TGT.VAL: 2299 // Duty cycle = 1 - ( 2300 // C1CC.VAL / TGT.VAL ). 2301 // 2302 // When C1CC.VAL > TGT.VAL: 2303 // Duty cycle = 0. 2304 // 2305 // Enabled outputs are set 2306 // when C1CC.VAL = 0 and CNTR.VAL = 0. 2307 // SET_ON_CAPT Set on capture repeatedly. 2308 // 2309 // Channel function 2310 // sequence: 2311 // - Set enabled outputs on 2312 // capture event and copy CNTR.VAL to C1CC.VAL. 2313 // PER_PULSE_WIDTH_MEAS Period and pulse width measurement. 2314 // 2315 // Continuously capture 2316 // period and pulse width of the signal selected 2317 // by INPUT relative to the signal edge given by 2318 // EDGE. 2319 // 2320 // Set enabled outputs and 2321 // RIS.C1CC when C1CC.VAL contains signal period 2322 // and PC1CC.VAL contains signal pulse width. 2323 // 2324 // Notes: 2325 // - Make sure to configure 2326 // INPUT and CCACT when CTL.MODE equals DIS, then 2327 // set CTL.MODE to UP_ONCE or UP_PER. 2328 // - The counter restarts in 2329 // the selected timer mode when C1CC.VAL contains 2330 // the signal period. 2331 // - If more than one 2332 // channel uses this function, the channels will 2333 // perform this function one at a time. The 2334 // channel with lowest number has priority and 2335 // performs the function first. Next measurement 2336 // starts when current measurement completes 2337 // successfully or times out. A timeout occurs 2338 // when counter equals target. 2339 // - To observe a timeout 2340 // event the RIS.TGT interrupt can be used, or 2341 // another channel can be configured to SET_ON_CMP 2342 // with compare value equal TGT. 2343 // 2344 // Signal property 2345 // requirements: 2346 // - Signal Period >= 2 * ( 2347 // 1 + PRECFG.TICKDIV ) * timer clock period. 2348 // - Signal Period <= 2349 // MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock 2350 // period. 2351 // - Signal low and high 2352 // phase >= (1 + PRECFG.TICKDIV ) * timer clock 2353 // period. 2354 // PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. 2355 // 2356 // Channel function 2357 // sequence: 2358 // - Pulse enabled outputs 2359 // when C1CC.VAL = CNTR.VAL. 2360 // - Disable channel. 2361 // 2362 // The output is high for 2363 // two timer clock periods. 2364 // TGL_ON_CMP_DIS Toggle on compare, and then disable channel. 2365 // 2366 // Channel function 2367 // sequence: 2368 // - Toggle enabled outputs 2369 // when C1CC.VAL = CNTR.VAL. 2370 // - Disable channel. 2371 // SET_ON_CMP_DIS Set on compare, and then disable channel. 2372 // 2373 // Channel function 2374 // sequence: 2375 // - Set enabled outputs 2376 // when C1CC.VAL = CNTR.VAL. 2377 // - Disable channel. 2378 // CLR_ON_CMP_DIS Clear on compare, and then disable channel. 2379 // 2380 // Channel function 2381 // sequence: 2382 // - Clear enabled outputs 2383 // when C1CC.VAL = CNTR.VAL. 2384 // - Disable channel. 2385 // SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable 2386 // channel. 2387 // 2388 // Channel function 2389 // sequence: 2390 // - Set enabled outputs 2391 // when CNTR.VAL = 0. 2392 // - Toggle enabled outputs 2393 // when C1CC.VAL = CNTR.VAL. 2394 // - Disable channel. 2395 // 2396 // Enabled outputs are 2397 // cleared when C1CC.VAL = 0 and CNTR.VAL = 0. 2398 // CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable 2399 // channel. 2400 // 2401 // Channel function 2402 // sequence: 2403 // - Clear enabled outputs 2404 // when CNTR.VAL = 0. 2405 // - Toggle enabled outputs 2406 // when C1CC.VAL = CNTR.VAL. 2407 // - Disable channel. 2408 // 2409 // Enabled outputs are set 2410 // when C1CC.VAL = 0 and CNTR.VAL = 0. 2411 // SET_ON_CAPT_DIS Set on capture, and then disable channel. 2412 // 2413 // Channel function 2414 // sequence: 2415 // - Set enabled outputs on 2416 // capture event and copy CNTR.VAL to C1CC.VAL. 2417 // - Disable channel. 2418 // 2419 // Primary use scenario is 2420 // to select this function before starting the 2421 // timer. 2422 // Follow these steps to 2423 // select this function while CTL.MODE is 2424 // different from DIS: 2425 // - Set CCACT to 2426 // SET_ON_CAPT with no output enable. 2427 // - Configure INPUT 2428 // (optional). 2429 // - Wait for three timer 2430 // clock periods as defined in PRECFG before 2431 // setting CCACT to SET_ON_CAPT_DIS. Output enable 2432 // is optional. 2433 // 2434 // These steps prevent 2435 // capture events caused by expired signal values 2436 // in edge-detection circuit. 2437 // DIS Disable channel. 2438 #define LGPT_C1CFG_CCACT_W 4U 2439 #define LGPT_C1CFG_CCACT_M 0x0000000FU 2440 #define LGPT_C1CFG_CCACT_S 0U 2441 #define LGPT_C1CFG_CCACT_PULSE_ON_CMP 0x0000000FU 2442 #define LGPT_C1CFG_CCACT_TGL_ON_CMP 0x0000000EU 2443 #define LGPT_C1CFG_CCACT_SET_ON_CMP 0x0000000DU 2444 #define LGPT_C1CFG_CCACT_CLR_ON_CMP 0x0000000CU 2445 #define LGPT_C1CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU 2446 #define LGPT_C1CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU 2447 #define LGPT_C1CFG_CCACT_SET_ON_CAPT 0x00000009U 2448 #define LGPT_C1CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U 2449 #define LGPT_C1CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U 2450 #define LGPT_C1CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U 2451 #define LGPT_C1CFG_CCACT_SET_ON_CMP_DIS 0x00000005U 2452 #define LGPT_C1CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U 2453 #define LGPT_C1CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U 2454 #define LGPT_C1CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U 2455 #define LGPT_C1CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U 2456 #define LGPT_C1CFG_CCACT_DIS 0x00000000U 2457 2458 //***************************************************************************** 2459 // 2460 // Register: LGPT_O_C2CFG 2461 // 2462 //***************************************************************************** 2463 // Field: [10] OUT2 2464 // 2465 // Output 2 enable. 2466 // 2467 // When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event. 2468 // ENUMs: 2469 // EN Channel 2 controls output 2. 2470 // DIS Channel 2 does not control output 2. 2471 #define LGPT_C2CFG_OUT2 0x00000400U 2472 #define LGPT_C2CFG_OUT2_M 0x00000400U 2473 #define LGPT_C2CFG_OUT2_S 10U 2474 #define LGPT_C2CFG_OUT2_EN 0x00000400U 2475 #define LGPT_C2CFG_OUT2_DIS 0x00000000U 2476 2477 // Field: [9] OUT1 2478 // 2479 // Output 1 enable. 2480 // 2481 // When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event. 2482 // ENUMs: 2483 // EN Channel 2 controls output 1. 2484 // DIS Channel 2 does not control output 1. 2485 #define LGPT_C2CFG_OUT1 0x00000200U 2486 #define LGPT_C2CFG_OUT1_M 0x00000200U 2487 #define LGPT_C2CFG_OUT1_S 9U 2488 #define LGPT_C2CFG_OUT1_EN 0x00000200U 2489 #define LGPT_C2CFG_OUT1_DIS 0x00000000U 2490 2491 // Field: [8] OUT0 2492 // 2493 // Output 0 enable. 2494 // 2495 // When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event. 2496 // ENUMs: 2497 // EN Channel 2 controls output 0. 2498 // DIS Channel 2 does not control output 0. 2499 #define LGPT_C2CFG_OUT0 0x00000100U 2500 #define LGPT_C2CFG_OUT0_M 0x00000100U 2501 #define LGPT_C2CFG_OUT0_S 8U 2502 #define LGPT_C2CFG_OUT0_EN 0x00000100U 2503 #define LGPT_C2CFG_OUT0_DIS 0x00000000U 2504 2505 // Field: [6] INPUT 2506 // 2507 // Select channel input. 2508 // ENUMs: 2509 // IO IO controller 2510 // EV Event fabric 2511 #define LGPT_C2CFG_INPUT 0x00000040U 2512 #define LGPT_C2CFG_INPUT_M 0x00000040U 2513 #define LGPT_C2CFG_INPUT_S 6U 2514 #define LGPT_C2CFG_INPUT_IO 0x00000040U 2515 #define LGPT_C2CFG_INPUT_EV 0x00000000U 2516 2517 // Field: [5:4] EDGE 2518 // 2519 // Determines the edge that triggers the channel input event. This happens post 2520 // filter. 2521 // ENUMs: 2522 // BOTH Input event is triggered at both edges. 2523 // FALL Input event is triggered at falling edge. 2524 // RISE Input event is triggered at rising edge. 2525 // NONE Input is turned off. 2526 #define LGPT_C2CFG_EDGE_W 2U 2527 #define LGPT_C2CFG_EDGE_M 0x00000030U 2528 #define LGPT_C2CFG_EDGE_S 4U 2529 #define LGPT_C2CFG_EDGE_BOTH 0x00000030U 2530 #define LGPT_C2CFG_EDGE_FALL 0x00000020U 2531 #define LGPT_C2CFG_EDGE_RISE 0x00000010U 2532 #define LGPT_C2CFG_EDGE_NONE 0x00000000U 2533 2534 // Field: [3:0] CCACT 2535 // 2536 // Capture-Compare action. 2537 // 2538 // Capture-Compare action defines 15 different channel functions that utilize 2539 // capture, compare, and zero events. In every compare event the timer looks at 2540 // the current value of CNTR. The corresponding output event will be set 1 2541 // timer period after CNTR = C2CC. 2542 // ENUMs: 2543 // PULSE_ON_CMP Pulse on compare repeatedly. 2544 // 2545 // Channel function 2546 // sequence: 2547 // - Pulse enabled outputs 2548 // when C2CC.VAL = CNTR.VAL. 2549 // 2550 // The output is high for 2551 // two timer clock periods. 2552 // TGL_ON_CMP Toggle on compare repeatedly. 2553 // 2554 // Channel function 2555 // sequence: 2556 // - Toggle enabled outputs 2557 // when C2CC.VAL = CNTR.VAL. 2558 // SET_ON_CMP Set on compare repeatedly. 2559 // 2560 // Channel function 2561 // sequence: 2562 // - Set enabled outputs 2563 // when C2CC.VAL = CNTR.VAL. 2564 // CLR_ON_CMP Clear on compare repeatedly. 2565 // 2566 // Channel function 2567 // sequence: 2568 // - Clear enabled outputs 2569 // when C2CC.VAL = CNTR.VAL. 2570 // SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. 2571 // 2572 // Channel function 2573 // sequence: 2574 // - Set enabled outputs 2575 // when CNTR.VAL = 0. 2576 // - Toggle enabled outputs 2577 // when C2CC.VAL = CNTR.VAL. 2578 // 2579 // Set CTL.MODE to UP_PER 2580 // for edge-aligned PWM generation. Duty cycle is 2581 // given by: 2582 // 2583 // When C2CC.VAL <= TGT.VAL: 2584 // Duty cycle = C2CC.VAL 2585 // / ( TGT.VAL + 1 ). 2586 // 2587 // When C2CC.VAL > TGT.VAL: 2588 // Duty cycle = 1. 2589 // 2590 // Enabled outputs are 2591 // cleared when C2CC.VAL = 0 and CNTR.VAL = 0. 2592 // CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. 2593 // 2594 // Channel function 2595 // sequence: 2596 // - Clear enabled outputs 2597 // when CNTR.VAL = 0. 2598 // - Toggle enabled outputs 2599 // when C2CC.VAL = CNTR.VAL. 2600 // 2601 // Set CTL.MODE to UPDWN_PER 2602 // for center-aligned PWM generation. Duty cycle 2603 // is given by: 2604 // 2605 // When C2CC.VAL <= TGT.VAL: 2606 // Duty cycle = 1 - ( 2607 // C2CC.VAL / TGT.VAL ). 2608 // 2609 // When C2CC.VAL > TGT.VAL: 2610 // Duty cycle = 0. 2611 // 2612 // Enabled outputs are set 2613 // when C2CC.VAL = 0 and CNTR.VAL = 0. 2614 // SET_ON_CAPT Set on capture repeatedly. 2615 // 2616 // Channel function 2617 // sequence: 2618 // - Set enabled outputs on 2619 // capture event and copy CNTR.VAL to C2CC.VAL. 2620 // PER_PULSE_WIDTH_MEAS Period and pulse width measurement. 2621 // 2622 // Continuously capture 2623 // period and pulse width of the signal selected 2624 // by INPUT relative to the signal edge given by 2625 // EDGE. 2626 // 2627 // Set enabled outputs and 2628 // RIS.C2CC when C2CC.VAL contains signal period 2629 // and PC2CC.VAL contains signal pulse width. 2630 // 2631 // Notes: 2632 // - Make sure to configure 2633 // INPUT and CCACT when CTL.MODE equals DIS, then 2634 // set CTL.MODE to UP_ONCE or UP_PER. 2635 // - The counter restarts in 2636 // the selected timer mode when C2CC.VAL contains 2637 // the signal period. 2638 // - If more than one 2639 // channel uses this function, the channels will 2640 // perform this function one at a time. The 2641 // channel with lowest number has priority and 2642 // performs the function first. Next measurement 2643 // starts when current measurement completes 2644 // successfully or times out. A timeout occurs 2645 // when counter equals target. 2646 // - To observe a timeout 2647 // event the RIS.TGT interrupt can be used, or 2648 // another channel can be configured to SET_ON_CMP 2649 // with compare value equal TGT. 2650 // 2651 // Signal property 2652 // requirements: 2653 // - Signal Period >= 2 * ( 2654 // 1 + PRECFG.TICKDIV ) * timer clock period. 2655 // - Signal Period <= 2656 // MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock 2657 // period. 2658 // - Signal low and high 2659 // phase >= (1 + PRECFG.TICKDIV ) * timer clock 2660 // period. 2661 // PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. 2662 // 2663 // Channel function 2664 // sequence: 2665 // - Pulse enabled outputs 2666 // when C2CC.VAL = CNTR.VAL. 2667 // - Disable channel. 2668 // 2669 // The output is high for 2670 // two timer clock periods. 2671 // TGL_ON_CMP_DIS Toggle on compare, and then disable channel. 2672 // 2673 // Channel function 2674 // sequence: 2675 // - Toggle enabled outputs 2676 // when C2CC.VAL = CNTR.VAL. 2677 // - Disable channel. 2678 // SET_ON_CMP_DIS Set on compare, and then disable channel. 2679 // 2680 // Channel function 2681 // sequence: 2682 // - Set enabled outputs 2683 // when C2CC.VAL = CNTR.VAL. 2684 // - Disable channel. 2685 // CLR_ON_CMP_DIS Clear on compare, and then disable channel. 2686 // 2687 // Channel function 2688 // sequence: 2689 // - Clear enabled outputs 2690 // when C2CC.VAL = CNTR.VAL. 2691 // - Disable channel. 2692 // SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable 2693 // channel. 2694 // 2695 // Channel function 2696 // sequence: 2697 // - Set enabled outputs 2698 // when CNTR.VAL = 0. 2699 // - Toggle enabled outputs 2700 // when C2CC.VAL = CNTR.VAL. 2701 // - Disable channel. 2702 // 2703 // Enabled outputs are 2704 // cleared when C2CC.VAL = 0 and CNTR.VAL = 0. 2705 // CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable 2706 // channel. 2707 // 2708 // Channel function 2709 // sequence: 2710 // - Clear enabled outputs 2711 // when CNTR.VAL = 0. 2712 // - Toggle enabled outputs 2713 // when C2CC.VAL = CNTR.VAL. 2714 // - Disable channel. 2715 // 2716 // Enabled outputs are set 2717 // when C2CC.VAL = 0 and CNTR.VAL = 0. 2718 // SET_ON_CAPT_DIS Set on capture, and then disable channel. 2719 // 2720 // Channel function 2721 // sequence: 2722 // - Set enabled outputs on 2723 // capture event and copy CNTR.VAL to C2CC.VAL. 2724 // - Disable channel. 2725 // 2726 // Primary use scenario is 2727 // to select this function before starting the 2728 // timer. 2729 // Follow these steps to 2730 // select this function while CTL.MODE is 2731 // different from DIS: 2732 // - Set CCACT to 2733 // SET_ON_CAPT with no output enable. 2734 // - Configure INPUT 2735 // (optional). 2736 // - Wait for three timer 2737 // clock periods as defined in PRECFG before 2738 // setting CCACT to SET_ON_CAPT_DIS. Output enable 2739 // is optional. 2740 // 2741 // These steps prevent 2742 // capture events caused by expired signal values 2743 // in edge-detection circuit. 2744 // DIS Disable channel. 2745 #define LGPT_C2CFG_CCACT_W 4U 2746 #define LGPT_C2CFG_CCACT_M 0x0000000FU 2747 #define LGPT_C2CFG_CCACT_S 0U 2748 #define LGPT_C2CFG_CCACT_PULSE_ON_CMP 0x0000000FU 2749 #define LGPT_C2CFG_CCACT_TGL_ON_CMP 0x0000000EU 2750 #define LGPT_C2CFG_CCACT_SET_ON_CMP 0x0000000DU 2751 #define LGPT_C2CFG_CCACT_CLR_ON_CMP 0x0000000CU 2752 #define LGPT_C2CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU 2753 #define LGPT_C2CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU 2754 #define LGPT_C2CFG_CCACT_SET_ON_CAPT 0x00000009U 2755 #define LGPT_C2CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U 2756 #define LGPT_C2CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U 2757 #define LGPT_C2CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U 2758 #define LGPT_C2CFG_CCACT_SET_ON_CMP_DIS 0x00000005U 2759 #define LGPT_C2CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U 2760 #define LGPT_C2CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U 2761 #define LGPT_C2CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U 2762 #define LGPT_C2CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U 2763 #define LGPT_C2CFG_CCACT_DIS 0x00000000U 2764 2765 //***************************************************************************** 2766 // 2767 // Register: LGPT_O_PTGT 2768 // 2769 //***************************************************************************** 2770 // Field: [15:0] VAL 2771 // 2772 // The pipleline target value. 2773 #define LGPT_PTGT_VAL_W 16U 2774 #define LGPT_PTGT_VAL_M 0x0000FFFFU 2775 #define LGPT_PTGT_VAL_S 0U 2776 2777 //***************************************************************************** 2778 // 2779 // Register: LGPT_O_PC0CC 2780 // 2781 //***************************************************************************** 2782 // Field: [15:0] VAL 2783 // 2784 // Pipeline Capture Compare value. 2785 // 2786 // User defined pipeline compare value or channel-updated capture value. 2787 // 2788 // A read or write to this register will clear the RIS.C0CC interrupt. 2789 // 2790 // Compare mode: 2791 // An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is 2792 // zero and CTL.MODE is different from DIS. This is useful for PWM generation 2793 // and prevents jitter on the edges of the generated signal. 2794 // 2795 // Capture mode: 2796 // When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of 2797 // the low or high phase of the selected signal. This is specified by 2798 // C0CFG.EDGE. 2799 #define LGPT_PC0CC_VAL_W 16U 2800 #define LGPT_PC0CC_VAL_M 0x0000FFFFU 2801 #define LGPT_PC0CC_VAL_S 0U 2802 2803 //***************************************************************************** 2804 // 2805 // Register: LGPT_O_PC1CC 2806 // 2807 //***************************************************************************** 2808 // Field: [15:0] VAL 2809 // 2810 // Pipeline Capture Compare value. 2811 // 2812 // User defined pipeline compare value or channel-updated capture value. 2813 // 2814 // A read or write to this register will clear the RIS.C1CC interrupt. 2815 // 2816 // Compare mode: 2817 // An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is 2818 // zero and CTL.MODE is different from DIS. This is useful for PWM generation 2819 // and prevents jitter on the edges of the generated signal. 2820 // 2821 // Capture mode: 2822 // When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of 2823 // the low or high phase of the selected signal. This is specified by 2824 // C1CFG.EDGE. 2825 #define LGPT_PC1CC_VAL_W 16U 2826 #define LGPT_PC1CC_VAL_M 0x0000FFFFU 2827 #define LGPT_PC1CC_VAL_S 0U 2828 2829 //***************************************************************************** 2830 // 2831 // Register: LGPT_O_PC2CC 2832 // 2833 //***************************************************************************** 2834 // Field: [15:0] VAL 2835 // 2836 // Pipeline Capture Compare value. 2837 // 2838 // User defined pipeline compare value or channel-updated capture value. 2839 // 2840 // A read or write to this register will clear the RIS.C2CC interrupt. 2841 // 2842 // Compare mode: 2843 // An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is 2844 // zero and CTL.MODE is different from DIS. This is useful for PWM generation 2845 // and prevents jitter on the edges of the generated signal. 2846 // 2847 // Capture mode: 2848 // When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of 2849 // the low or high phase of the selected signal. This is specified by 2850 // C2CFG.EDGE. 2851 #define LGPT_PC2CC_VAL_W 16U 2852 #define LGPT_PC2CC_VAL_M 0x0000FFFFU 2853 #define LGPT_PC2CC_VAL_S 0U 2854 2855 //***************************************************************************** 2856 // 2857 // Register: LGPT_O_TGT 2858 // 2859 //***************************************************************************** 2860 // Field: [15:0] VAL 2861 // 2862 // User defined counter target value. 2863 #define LGPT_TGT_VAL_W 16U 2864 #define LGPT_TGT_VAL_M 0x0000FFFFU 2865 #define LGPT_TGT_VAL_S 0U 2866 2867 //***************************************************************************** 2868 // 2869 // Register: LGPT_O_C0CC 2870 // 2871 //***************************************************************************** 2872 // Field: [15:0] VAL 2873 // 2874 // Capture Compare value. 2875 // 2876 // User defined compare value or channel-updated capture value. 2877 // 2878 // A read or write to this register will clear the RIS.C0CC interrupt. 2879 // 2880 // Compare mode: 2881 // VAL is compared against CNTR.VAL and an event is generated as specified by 2882 // C0CFG.CCACT when these are equal. 2883 // 2884 // Capture mode: 2885 // The current counter value is stored in VAL when a capture event occurs. 2886 // C0CFG.CCACT determines if VAL is a signal period or a regular capture value. 2887 #define LGPT_C0CC_VAL_W 16U 2888 #define LGPT_C0CC_VAL_M 0x0000FFFFU 2889 #define LGPT_C0CC_VAL_S 0U 2890 2891 //***************************************************************************** 2892 // 2893 // Register: LGPT_O_C1CC 2894 // 2895 //***************************************************************************** 2896 // Field: [15:0] VAL 2897 // 2898 // Capture Compare value. 2899 // 2900 // User defined compare value or channel-updated capture value. 2901 // 2902 // A read or write to this register will clear the RIS.C1CC interrupt. 2903 // 2904 // Compare mode: 2905 // VAL is compared against CNTR.VAL and an event is generated as specified by 2906 // C1CFG.CCACT when these are equal. 2907 // 2908 // Capture mode: 2909 // The current counter value is stored in VAL when a capture event occurs. 2910 // C1CFG.CCACT determines if VAL is a signal period or a regular capture value. 2911 #define LGPT_C1CC_VAL_W 16U 2912 #define LGPT_C1CC_VAL_M 0x0000FFFFU 2913 #define LGPT_C1CC_VAL_S 0U 2914 2915 //***************************************************************************** 2916 // 2917 // Register: LGPT_O_C2CC 2918 // 2919 //***************************************************************************** 2920 // Field: [15:0] VAL 2921 // 2922 // Capture Compare value. 2923 // 2924 // User defined compare value or channel-updated capture value. 2925 // 2926 // A read or write to this register will clear the RIS.C2CC interrupt. 2927 // 2928 // Compare mode: 2929 // VAL is compared against CNTR.VAL and an event is generated as specified by 2930 // C2CFG.CCACT when these are equal. 2931 // 2932 // Capture mode: 2933 // The current counter value is stored in VAL when a capture event occurs. 2934 // C2CFG.CCACT determines if VAL is a signal period or a regular capture value. 2935 #define LGPT_C2CC_VAL_W 16U 2936 #define LGPT_C2CC_VAL_M 0x0000FFFFU 2937 #define LGPT_C2CC_VAL_S 0U 2938 2939 //***************************************************************************** 2940 // 2941 // Register: LGPT_O_PTGTNC 2942 // 2943 //***************************************************************************** 2944 // Field: [15:0] VAL 2945 // 2946 // A read or write to this register will not clear the RIS.TGT interrupt. 2947 // 2948 // If CTL.MODE != QDEC. 2949 // Target value for next counter period. 2950 // The timer copies VAL to TGT.VAL when CNTR.VAL becomes 0. The copy does not 2951 // happen when restarting the timer. 2952 // This is useful to avoid period jitter in PWM applications with time-varying 2953 // period, sometimes referenced as phase corrected PWM. 2954 // 2955 // If CTL.MODE = QDEC. 2956 // The CNTR.VAL is updated with VAL on IDX. VAL is not loaded into TGT.VAL when 2957 // CNTR.VAL becomes 0. 2958 #define LGPT_PTGTNC_VAL_W 16U 2959 #define LGPT_PTGTNC_VAL_M 0x0000FFFFU 2960 #define LGPT_PTGTNC_VAL_S 0U 2961 2962 //***************************************************************************** 2963 // 2964 // Register: LGPT_O_PC0CCNC 2965 // 2966 //***************************************************************************** 2967 // Field: [15:0] VAL 2968 // 2969 // Pipeline Capture Compare value. 2970 // 2971 // User defined pipeline compare value or channel-updated capture value. 2972 // 2973 // A read or write to this register will not clear the RIS.C0CC interrupt. 2974 // 2975 // Compare mode: 2976 // An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is 2977 // zero and CTL.MODE is different from DIS. This is useful for PWM generation 2978 // and prevents jitter on the edges of the generated signal. 2979 // 2980 // Capture mode: 2981 // When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of 2982 // the low or high phase of the selected signal. This is specified by 2983 // C0CFG.EDGE. 2984 #define LGPT_PC0CCNC_VAL_W 16U 2985 #define LGPT_PC0CCNC_VAL_M 0x0000FFFFU 2986 #define LGPT_PC0CCNC_VAL_S 0U 2987 2988 //***************************************************************************** 2989 // 2990 // Register: LGPT_O_PC1CCNC 2991 // 2992 //***************************************************************************** 2993 // Field: [15:0] VAL 2994 // 2995 // Pipeline Capture Compare value. 2996 // 2997 // User defined pipeline compare value or channel-updated capture value. 2998 // 2999 // A read or write to this register will not clear the RIS.C1CC interrupt. 3000 // 3001 // Compare mode: 3002 // An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is 3003 // zero and CTL.MODE is different from DIS. This is useful for PWM generation 3004 // and prevents jitter on the edges of the generated signal. 3005 // 3006 // Capture mode: 3007 // When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of 3008 // the low or high phase of the selected signal. This is specified by 3009 // C1CFG.EDGE. 3010 #define LGPT_PC1CCNC_VAL_W 16U 3011 #define LGPT_PC1CCNC_VAL_M 0x0000FFFFU 3012 #define LGPT_PC1CCNC_VAL_S 0U 3013 3014 //***************************************************************************** 3015 // 3016 // Register: LGPT_O_PC2CCNC 3017 // 3018 //***************************************************************************** 3019 // Field: [15:0] VAL 3020 // 3021 // Pipeline Capture Compare value. 3022 // 3023 // User defined pipeline compare value or channel-updated capture value. 3024 // 3025 // A read or write to this register will not clear the RIS.C2CC interrupt. 3026 // 3027 // Compare mode: 3028 // An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is 3029 // zero and CTL.MODE is different from DIS. This is useful for PWM generation 3030 // and prevents jitter on the edges of the generated signal. 3031 // 3032 // Capture mode: 3033 // When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of 3034 // the low or high phase of the selected signal. This is specified by 3035 // C2CFG.EDGE. 3036 #define LGPT_PC2CCNC_VAL_W 16U 3037 #define LGPT_PC2CCNC_VAL_M 0x0000FFFFU 3038 #define LGPT_PC2CCNC_VAL_S 0U 3039 3040 //***************************************************************************** 3041 // 3042 // Register: LGPT_O_TGTNC 3043 // 3044 //***************************************************************************** 3045 // Field: [15:0] VAL 3046 // 3047 // User defined counter target value. 3048 #define LGPT_TGTNC_VAL_W 16U 3049 #define LGPT_TGTNC_VAL_M 0x0000FFFFU 3050 #define LGPT_TGTNC_VAL_S 0U 3051 3052 //***************************************************************************** 3053 // 3054 // Register: LGPT_O_C0CCNC 3055 // 3056 //***************************************************************************** 3057 // Field: [15:0] VAL 3058 // 3059 // Capture Compare value. 3060 // 3061 // User defined compare value or channel-updated capture value. 3062 // 3063 // A read or write to this register will not clear the RIS.C0CC interrupt. 3064 // 3065 // Compare mode: 3066 // VAL is compared against CNTR.VAL and an event is generated as specified by 3067 // C0CFG.CCACT when these are equal. 3068 // 3069 // Capture mode: 3070 // The current counter value is stored in VAL when a capture event occurs. 3071 // C0CFG.CCACT determines if VAL is a signal period or a regular capture value. 3072 #define LGPT_C0CCNC_VAL_W 16U 3073 #define LGPT_C0CCNC_VAL_M 0x0000FFFFU 3074 #define LGPT_C0CCNC_VAL_S 0U 3075 3076 //***************************************************************************** 3077 // 3078 // Register: LGPT_O_C1CCNC 3079 // 3080 //***************************************************************************** 3081 // Field: [15:0] VAL 3082 // 3083 // Capture Compare value. 3084 // 3085 // User defined compare value or channel-updated capture value. 3086 // 3087 // A read or write to this register will not clear the RIS.C1CC interrupt. 3088 // 3089 // Compare mode: 3090 // VAL is compared against CNTR.VAL and an event is generated as specified by 3091 // C1CFG.CCACT when these are equal. 3092 // 3093 // Capture mode: 3094 // The current counter value is stored in VAL when a capture event occurs. 3095 // C1CFG.CCACT determines if VAL is a signal period or a regular capture value. 3096 #define LGPT_C1CCNC_VAL_W 16U 3097 #define LGPT_C1CCNC_VAL_M 0x0000FFFFU 3098 #define LGPT_C1CCNC_VAL_S 0U 3099 3100 //***************************************************************************** 3101 // 3102 // Register: LGPT_O_C2CCNC 3103 // 3104 //***************************************************************************** 3105 // Field: [15:0] VAL 3106 // 3107 // Capture Compare value. 3108 // 3109 // User defined compare value or channel-updated capture value. 3110 // 3111 // A read or write to this register will not clear the RIS.C2CC interrupt. 3112 // 3113 // Compare mode: 3114 // VAL is compared against CNTR.VAL and an event is generated as specified by 3115 // C2CFG.CCACT when these are equal. 3116 // 3117 // Capture mode: 3118 // The current counter value is stored in VAL when a capture event occurs. 3119 // C2CFG.CCACT determines if VAL is a signal period or a regular capture value. 3120 #define LGPT_C2CCNC_VAL_W 16U 3121 #define LGPT_C2CCNC_VAL_M 0x0000FFFFU 3122 #define LGPT_C2CCNC_VAL_S 0U 3123 3124 3125 #endif // __LGPT__ 3126
