1 /****************************************************************************** 2 * Filename: hw_ioc_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_IOC_H__ 34 #define __HW_IOC_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // IOC component 40 // 41 //***************************************************************************** 42 // Module Description 43 #define IOC_O_DESC 0x00000000U 44 45 // Extended Module Description 46 #define IOC_O_DESCEX 0x00000004U 47 48 // Configuration 49 #define IOC_O_IOC0 0x00000100U 50 51 // Configuration 52 #define IOC_O_IOC1 0x00000104U 53 54 // Configuration 55 #define IOC_O_IOC2 0x00000108U 56 57 // Configuration 58 #define IOC_O_IOC3 0x0000010CU 59 60 // Configuration 61 #define IOC_O_IOC4 0x00000110U 62 63 // Configuration 64 #define IOC_O_IOC5 0x00000114U 65 66 // Configuration 67 #define IOC_O_IOC6 0x00000118U 68 69 // Configuration 70 #define IOC_O_IOC7 0x0000011CU 71 72 // Configuration 73 #define IOC_O_IOC8 0x00000120U 74 75 // Configuration 76 #define IOC_O_IOC9 0x00000124U 77 78 // Configuration 79 #define IOC_O_IOC10 0x00000128U 80 81 // Configuration 82 #define IOC_O_IOC11 0x0000012CU 83 84 // Configuration 85 #define IOC_O_IOC12 0x00000130U 86 87 // Configuration 88 #define IOC_O_IOC13 0x00000134U 89 90 // Configuration 91 #define IOC_O_IOC14 0x00000138U 92 93 // Configuration 94 #define IOC_O_IOC15 0x0000013CU 95 96 // Configuration 97 #define IOC_O_IOC16 0x00000140U 98 99 // Configuration 100 #define IOC_O_IOC17 0x00000144U 101 102 // Configuration 103 #define IOC_O_IOC18 0x00000148U 104 105 // Configuration 106 #define IOC_O_IOC19 0x0000014CU 107 108 // Configuration 109 #define IOC_O_IOC20 0x00000150U 110 111 // Configuration 112 #define IOC_O_IOC21 0x00000154U 113 114 // Configuration 115 #define IOC_O_IOC22 0x00000158U 116 117 // Configuration 118 #define IOC_O_IOC23 0x0000015CU 119 120 // Configuration 121 #define IOC_O_IOC24 0x00000160U 122 123 // Configuration 124 #define IOC_O_IOC25 0x00000164U 125 126 // DTB configuration 127 #define IOC_O_DTBCFG 0x00000C00U 128 129 // DTB output enable 130 #define IOC_O_DTBOE 0x00000C04U 131 132 // Event configuration 133 #define IOC_O_EVTCFG 0x00000C08U 134 135 // Test 136 #define IOC_O_TEST 0x00000C0CU 137 138 // DTB status 139 #define IOC_O_DTBSTAT 0x00000C10U 140 141 //***************************************************************************** 142 // 143 // Register: IOC_O_DESC 144 // 145 //***************************************************************************** 146 // Field: [31:16] MODID 147 // 148 // Module identifier used to uniquely identify this IP. 149 #define IOC_DESC_MODID_W 16U 150 #define IOC_DESC_MODID_M 0xFFFF0000U 151 #define IOC_DESC_MODID_S 16U 152 153 // Field: [15:12] STDIPOFF 154 // 155 // Standard IP MMR block offset. Standard IP MMRs are the set of from 156 // aggregated IRQ registers till DTB. 157 // 158 // 0: Standard IP MMRs do not exist 159 // 160 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 161 // address) 162 #define IOC_DESC_STDIPOFF_W 4U 163 #define IOC_DESC_STDIPOFF_M 0x0000F000U 164 #define IOC_DESC_STDIPOFF_S 12U 165 166 // Field: [11:8] INSTIDX 167 // 168 // IP Instance ID number. If multiple instances of IP exist in the device, this 169 // field can identify the instance number (0-15). 170 #define IOC_DESC_INSTIDX_W 4U 171 #define IOC_DESC_INSTIDX_M 0x00000F00U 172 #define IOC_DESC_INSTIDX_S 8U 173 174 // Field: [7:4] MAJREV 175 // 176 // Major revision of IP (0-15). 177 #define IOC_DESC_MAJREV_W 4U 178 #define IOC_DESC_MAJREV_M 0x000000F0U 179 #define IOC_DESC_MAJREV_S 4U 180 181 // Field: [3:0] MINREV 182 // 183 // Minor revision of IP (0-15). 184 #define IOC_DESC_MINREV_W 4U 185 #define IOC_DESC_MINREV_M 0x0000000FU 186 #define IOC_DESC_MINREV_S 0U 187 188 //***************************************************************************** 189 // 190 // Register: IOC_O_DESCEX 191 // 192 //***************************************************************************** 193 // Field: [15:12] NUMDTBIO 194 // 195 // Number of DTB IOs supported. Total DTB IOs supported is NUMDTBIO value +1. 196 // ENUMs: 197 // MAXIMUM Highest possible value 198 // MINIMUM Smallest value 199 #define IOC_DESCEX_NUMDTBIO_W 4U 200 #define IOC_DESCEX_NUMDTBIO_M 0x0000F000U 201 #define IOC_DESCEX_NUMDTBIO_S 12U 202 #define IOC_DESCEX_NUMDTBIO_MAXIMUM 0x0000F000U 203 #define IOC_DESCEX_NUMDTBIO_MINIMUM 0x00000000U 204 205 // Field: [11:7] NUMHDIO 206 // 207 // Number of high drive IOs supported. Total high drive IOs supported is 208 // NUMHDIO value +1. 209 // ENUMs: 210 // MAXIMUM Highest possible value 211 // MINIMUM Smallest value 212 #define IOC_DESCEX_NUMHDIO_W 5U 213 #define IOC_DESCEX_NUMHDIO_M 0x00000F80U 214 #define IOC_DESCEX_NUMHDIO_S 7U 215 #define IOC_DESCEX_NUMHDIO_MAXIMUM 0x00000F80U 216 #define IOC_DESCEX_NUMHDIO_MINIMUM 0x00000000U 217 218 // Field: [6] HDIO 219 // 220 // High drive IO supported by IOC. 221 // ENUMs: 222 // PRESENT HD IO supported by IOC 223 // ABSENT HD IO not supported by IOC 224 #define IOC_DESCEX_HDIO 0x00000040U 225 #define IOC_DESCEX_HDIO_M 0x00000040U 226 #define IOC_DESCEX_HDIO_S 6U 227 #define IOC_DESCEX_HDIO_PRESENT 0x00000040U 228 #define IOC_DESCEX_HDIO_ABSENT 0x00000000U 229 230 // Field: [5:0] NUMDIO 231 // 232 // Number of DIOs supported. Total DIOs supported is NUMDIO value +1. 233 // ENUMs: 234 // MAXIMUM Highest possible value 235 // MINIMUM Smallest value 236 #define IOC_DESCEX_NUMDIO_W 6U 237 #define IOC_DESCEX_NUMDIO_M 0x0000003FU 238 #define IOC_DESCEX_NUMDIO_S 0U 239 #define IOC_DESCEX_NUMDIO_MAXIMUM 0x0000003FU 240 #define IOC_DESCEX_NUMDIO_MINIMUM 0x00000000U 241 242 //***************************************************************************** 243 // 244 // Register: IOC_O_IOC0 245 // 246 //***************************************************************************** 247 // Field: [30] HYSTEN 248 // 249 // This field controls input hysteresis 250 // ENUMs: 251 // EN Input hysteresis enabled 252 // DIS Input hysteresis disabled 253 #define IOC_IOC0_HYSTEN 0x40000000U 254 #define IOC_IOC0_HYSTEN_M 0x40000000U 255 #define IOC_IOC0_HYSTEN_S 30U 256 #define IOC_IOC0_HYSTEN_EN 0x40000000U 257 #define IOC_IOC0_HYSTEN_DIS 0x00000000U 258 259 // Field: [29] INPEN 260 // 261 // This field controls the input capability of DIO 262 // ENUMs: 263 // EN Input enabled 264 // DIS Input disabled 265 #define IOC_IOC0_INPEN 0x20000000U 266 #define IOC_IOC0_INPEN_M 0x20000000U 267 #define IOC_IOC0_INPEN_S 29U 268 #define IOC_IOC0_INPEN_EN 0x20000000U 269 #define IOC_IOC0_INPEN_DIS 0x00000000U 270 271 // Field: [26:24] IOMODE 272 // 273 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 274 // behavior. 275 // ENUMs: 276 // OPENS_INV Open Source, inverted IO 277 // OPENS Open Source, normal IO 278 // OPEND_INV Open Drain, inverted IO 279 // OPEND Open Drain, normal IO 280 // INVERTED Inverted IO 281 // NORMAL Normal IO 282 #define IOC_IOC0_IOMODE_W 3U 283 #define IOC_IOC0_IOMODE_M 0x07000000U 284 #define IOC_IOC0_IOMODE_S 24U 285 #define IOC_IOC0_IOMODE_OPENS_INV 0x05000000U 286 #define IOC_IOC0_IOMODE_OPENS 0x04000000U 287 #define IOC_IOC0_IOMODE_OPEND_INV 0x03000000U 288 #define IOC_IOC0_IOMODE_OPEND 0x02000000U 289 #define IOC_IOC0_IOMODE_INVERTED 0x01000000U 290 #define IOC_IOC0_IOMODE_NORMAL 0x00000000U 291 292 // Field: [21:20] WUCFGSD 293 // 294 // Wakeup configuration from shutdown 295 // ENUMs: 296 // WAKE_HIGH Wakeup triggered when pad level is high 297 // WAKE_LOW Wakeup triggered when pad level is low 298 // DIS_1 Wakeup disabled 299 // DIS_0 Wakeup disabled 300 #define IOC_IOC0_WUCFGSD_W 2U 301 #define IOC_IOC0_WUCFGSD_M 0x00300000U 302 #define IOC_IOC0_WUCFGSD_S 20U 303 #define IOC_IOC0_WUCFGSD_WAKE_HIGH 0x00300000U 304 #define IOC_IOC0_WUCFGSD_WAKE_LOW 0x00200000U 305 #define IOC_IOC0_WUCFGSD_DIS_1 0x00100000U 306 #define IOC_IOC0_WUCFGSD_DIS_0 0x00000000U 307 308 // Field: [18] WUENSB 309 // 310 // Wakeup enable from standby 311 // ENUMs: 312 // EN Wakeup enabled (effective only if EDGEDET is 313 // enabled) 314 // DIS Wakeup disabled 315 #define IOC_IOC0_WUENSB 0x00040000U 316 #define IOC_IOC0_WUENSB_M 0x00040000U 317 #define IOC_IOC0_WUENSB_S 18U 318 #define IOC_IOC0_WUENSB_EN 0x00040000U 319 #define IOC_IOC0_WUENSB_DIS 0x00000000U 320 321 // Field: [17:16] EDGEDET 322 // 323 // Edge detect configuration 324 // ENUMs: 325 // EDGE_BOTH Positive and negative edge detection 326 // EDGE_POS Positive edge detection 327 // EDGE_NEG Negative edge detection 328 // EDGE_DIS No edge detection 329 #define IOC_IOC0_EDGEDET_W 2U 330 #define IOC_IOC0_EDGEDET_M 0x00030000U 331 #define IOC_IOC0_EDGEDET_S 16U 332 #define IOC_IOC0_EDGEDET_EDGE_BOTH 0x00030000U 333 #define IOC_IOC0_EDGEDET_EDGE_POS 0x00020000U 334 #define IOC_IOC0_EDGEDET_EDGE_NEG 0x00010000U 335 #define IOC_IOC0_EDGEDET_EDGE_DIS 0x00000000U 336 337 // Field: [14:13] PULLCTL 338 // 339 // Pull control. Setting this to value 0x3 disables pull. 340 // ENUMs: 341 // PULL_UP Pull up enabled 342 // PULL_DOWN Pull down enabled 343 // PULL_DIS No pull 344 #define IOC_IOC0_PULLCTL_W 2U 345 #define IOC_IOC0_PULLCTL_M 0x00006000U 346 #define IOC_IOC0_PULLCTL_S 13U 347 #define IOC_IOC0_PULLCTL_PULL_UP 0x00004000U 348 #define IOC_IOC0_PULLCTL_PULL_DOWN 0x00002000U 349 #define IOC_IOC0_PULLCTL_PULL_DIS 0x00000000U 350 351 // Field: [2:0] PORTCFG 352 // 353 // Selects usage of DIO0 354 // ENUMs: 355 // DTB Digital Test Bus function 356 // ANA Analog function 357 // PFUNC5 Digital peripheral function-5 358 // PFUNC4 Digital peripheral function-4 359 // PFUNC3 Digital peripheral function-3 360 // PFUNC2 Digital peripheral function-2 361 // PFUNC1 Digital peripheral function-1 362 // BASE Base function 363 #define IOC_IOC0_PORTCFG_W 3U 364 #define IOC_IOC0_PORTCFG_M 0x00000007U 365 #define IOC_IOC0_PORTCFG_S 0U 366 #define IOC_IOC0_PORTCFG_DTB 0x00000007U 367 #define IOC_IOC0_PORTCFG_ANA 0x00000006U 368 #define IOC_IOC0_PORTCFG_PFUNC5 0x00000005U 369 #define IOC_IOC0_PORTCFG_PFUNC4 0x00000004U 370 #define IOC_IOC0_PORTCFG_PFUNC3 0x00000003U 371 #define IOC_IOC0_PORTCFG_PFUNC2 0x00000002U 372 #define IOC_IOC0_PORTCFG_PFUNC1 0x00000001U 373 #define IOC_IOC0_PORTCFG_BASE 0x00000000U 374 375 //***************************************************************************** 376 // 377 // Register: IOC_O_IOC1 378 // 379 //***************************************************************************** 380 // Field: [30] HYSTEN 381 // 382 // This field controls input hysteresis 383 // ENUMs: 384 // EN Input hysteresis enabled 385 // DIS Input hysteresis disabled 386 #define IOC_IOC1_HYSTEN 0x40000000U 387 #define IOC_IOC1_HYSTEN_M 0x40000000U 388 #define IOC_IOC1_HYSTEN_S 30U 389 #define IOC_IOC1_HYSTEN_EN 0x40000000U 390 #define IOC_IOC1_HYSTEN_DIS 0x00000000U 391 392 // Field: [29] INPEN 393 // 394 // This field controls the input capability of DIO 395 // ENUMs: 396 // EN Input enabled 397 // DIS Input disabled 398 #define IOC_IOC1_INPEN 0x20000000U 399 #define IOC_IOC1_INPEN_M 0x20000000U 400 #define IOC_IOC1_INPEN_S 29U 401 #define IOC_IOC1_INPEN_EN 0x20000000U 402 #define IOC_IOC1_INPEN_DIS 0x00000000U 403 404 // Field: [26:24] IOMODE 405 // 406 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 407 // behavior. 408 // ENUMs: 409 // OPENS_INV Open Source, inverted IO 410 // OPENS Open Source, normal IO 411 // OPEND_INV Open Drain, inverted IO 412 // OPEND Open Drain, normal IO 413 // INVERTED Inverted IO 414 // NORMAL Normal IO 415 #define IOC_IOC1_IOMODE_W 3U 416 #define IOC_IOC1_IOMODE_M 0x07000000U 417 #define IOC_IOC1_IOMODE_S 24U 418 #define IOC_IOC1_IOMODE_OPENS_INV 0x05000000U 419 #define IOC_IOC1_IOMODE_OPENS 0x04000000U 420 #define IOC_IOC1_IOMODE_OPEND_INV 0x03000000U 421 #define IOC_IOC1_IOMODE_OPEND 0x02000000U 422 #define IOC_IOC1_IOMODE_INVERTED 0x01000000U 423 #define IOC_IOC1_IOMODE_NORMAL 0x00000000U 424 425 // Field: [21:20] WUCFGSD 426 // 427 // Wakeup configuration from shutdown 428 // ENUMs: 429 // WAKE_HIGH Wakeup triggered when pad level is high 430 // WAKE_LOW Wakeup triggered when pad level is low 431 // DIS_1 Wakeup disabled 432 // DIS_0 Wakeup disabled 433 #define IOC_IOC1_WUCFGSD_W 2U 434 #define IOC_IOC1_WUCFGSD_M 0x00300000U 435 #define IOC_IOC1_WUCFGSD_S 20U 436 #define IOC_IOC1_WUCFGSD_WAKE_HIGH 0x00300000U 437 #define IOC_IOC1_WUCFGSD_WAKE_LOW 0x00200000U 438 #define IOC_IOC1_WUCFGSD_DIS_1 0x00100000U 439 #define IOC_IOC1_WUCFGSD_DIS_0 0x00000000U 440 441 // Field: [18] WUENSB 442 // 443 // Wakeup enable from standby 444 // ENUMs: 445 // EN Wakeup enabled (effective only if EDGEDET is 446 // enabled) 447 // DIS Wakeup disabled 448 #define IOC_IOC1_WUENSB 0x00040000U 449 #define IOC_IOC1_WUENSB_M 0x00040000U 450 #define IOC_IOC1_WUENSB_S 18U 451 #define IOC_IOC1_WUENSB_EN 0x00040000U 452 #define IOC_IOC1_WUENSB_DIS 0x00000000U 453 454 // Field: [17:16] EDGEDET 455 // 456 // Edge detect configuration 457 // ENUMs: 458 // EDGE_BOTH Positive and negative edge detection 459 // EDGE_POS Positive edge detection 460 // EDGE_NEG Negative edge detection 461 // EDGE_DIS No edge detection 462 #define IOC_IOC1_EDGEDET_W 2U 463 #define IOC_IOC1_EDGEDET_M 0x00030000U 464 #define IOC_IOC1_EDGEDET_S 16U 465 #define IOC_IOC1_EDGEDET_EDGE_BOTH 0x00030000U 466 #define IOC_IOC1_EDGEDET_EDGE_POS 0x00020000U 467 #define IOC_IOC1_EDGEDET_EDGE_NEG 0x00010000U 468 #define IOC_IOC1_EDGEDET_EDGE_DIS 0x00000000U 469 470 // Field: [14:13] PULLCTL 471 // 472 // Pull control. Setting this to value 0x3 disables pull. 473 // ENUMs: 474 // PULL_UP Pull up enabled 475 // PULL_DOWN Pull down enabled 476 // PULL_DIS No pull 477 #define IOC_IOC1_PULLCTL_W 2U 478 #define IOC_IOC1_PULLCTL_M 0x00006000U 479 #define IOC_IOC1_PULLCTL_S 13U 480 #define IOC_IOC1_PULLCTL_PULL_UP 0x00004000U 481 #define IOC_IOC1_PULLCTL_PULL_DOWN 0x00002000U 482 #define IOC_IOC1_PULLCTL_PULL_DIS 0x00000000U 483 484 // Field: [2:0] PORTCFG 485 // 486 // Selects usage of DIO1 487 // ENUMs: 488 // DTB Digital Test Bus function 489 // ANA Analog function 490 // PFUNC5 Digital peripheral function-5 491 // PFUNC4 Digital peripheral function-4 492 // PFUNC3 Digital peripheral function-3 493 // PFUNC2 Digital peripheral function-2 494 // PFUNC1 Digital peripheral function-1 495 // BASE Base function 496 #define IOC_IOC1_PORTCFG_W 3U 497 #define IOC_IOC1_PORTCFG_M 0x00000007U 498 #define IOC_IOC1_PORTCFG_S 0U 499 #define IOC_IOC1_PORTCFG_DTB 0x00000007U 500 #define IOC_IOC1_PORTCFG_ANA 0x00000006U 501 #define IOC_IOC1_PORTCFG_PFUNC5 0x00000005U 502 #define IOC_IOC1_PORTCFG_PFUNC4 0x00000004U 503 #define IOC_IOC1_PORTCFG_PFUNC3 0x00000003U 504 #define IOC_IOC1_PORTCFG_PFUNC2 0x00000002U 505 #define IOC_IOC1_PORTCFG_PFUNC1 0x00000001U 506 #define IOC_IOC1_PORTCFG_BASE 0x00000000U 507 508 //***************************************************************************** 509 // 510 // Register: IOC_O_IOC2 511 // 512 //***************************************************************************** 513 // Field: [30] HYSTEN 514 // 515 // This field controls input hysteresis 516 // ENUMs: 517 // EN Input hysteresis enabled 518 // DIS Input hysteresis disabled 519 #define IOC_IOC2_HYSTEN 0x40000000U 520 #define IOC_IOC2_HYSTEN_M 0x40000000U 521 #define IOC_IOC2_HYSTEN_S 30U 522 #define IOC_IOC2_HYSTEN_EN 0x40000000U 523 #define IOC_IOC2_HYSTEN_DIS 0x00000000U 524 525 // Field: [29] INPEN 526 // 527 // This field controls the input capability of DIO 528 // ENUMs: 529 // EN Input enabled 530 // DIS Input disabled 531 #define IOC_IOC2_INPEN 0x20000000U 532 #define IOC_IOC2_INPEN_M 0x20000000U 533 #define IOC_IOC2_INPEN_S 29U 534 #define IOC_IOC2_INPEN_EN 0x20000000U 535 #define IOC_IOC2_INPEN_DIS 0x00000000U 536 537 // Field: [26:24] IOMODE 538 // 539 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 540 // behavior. 541 // ENUMs: 542 // OPENS_INV Open Source, inverted IO 543 // OPENS Open Source, normal IO 544 // OPEND_INV Open Drain, inverted IO 545 // OPEND Open Drain, normal IO 546 // INVERTED Inverted IO 547 // NORMAL Normal IO 548 #define IOC_IOC2_IOMODE_W 3U 549 #define IOC_IOC2_IOMODE_M 0x07000000U 550 #define IOC_IOC2_IOMODE_S 24U 551 #define IOC_IOC2_IOMODE_OPENS_INV 0x05000000U 552 #define IOC_IOC2_IOMODE_OPENS 0x04000000U 553 #define IOC_IOC2_IOMODE_OPEND_INV 0x03000000U 554 #define IOC_IOC2_IOMODE_OPEND 0x02000000U 555 #define IOC_IOC2_IOMODE_INVERTED 0x01000000U 556 #define IOC_IOC2_IOMODE_NORMAL 0x00000000U 557 558 // Field: [21:20] WUCFGSD 559 // 560 // Wakeup configuration from shutdown 561 // ENUMs: 562 // WAKE_HIGH Wakeup triggered when pad level is high 563 // WAKE_LOW Wakeup triggered when pad level is low 564 // DIS_1 Wakeup disabled 565 // DIS_0 Wakeup disabled 566 #define IOC_IOC2_WUCFGSD_W 2U 567 #define IOC_IOC2_WUCFGSD_M 0x00300000U 568 #define IOC_IOC2_WUCFGSD_S 20U 569 #define IOC_IOC2_WUCFGSD_WAKE_HIGH 0x00300000U 570 #define IOC_IOC2_WUCFGSD_WAKE_LOW 0x00200000U 571 #define IOC_IOC2_WUCFGSD_DIS_1 0x00100000U 572 #define IOC_IOC2_WUCFGSD_DIS_0 0x00000000U 573 574 // Field: [18] WUENSB 575 // 576 // Wakeup enable from standby 577 // ENUMs: 578 // EN Wakeup enabled (effective only if EDGEDET is 579 // enabled) 580 // DIS Wakeup disabled 581 #define IOC_IOC2_WUENSB 0x00040000U 582 #define IOC_IOC2_WUENSB_M 0x00040000U 583 #define IOC_IOC2_WUENSB_S 18U 584 #define IOC_IOC2_WUENSB_EN 0x00040000U 585 #define IOC_IOC2_WUENSB_DIS 0x00000000U 586 587 // Field: [17:16] EDGEDET 588 // 589 // Edge detect configuration 590 // ENUMs: 591 // EDGE_BOTH Positive and negative edge detection 592 // EDGE_POS Positive edge detection 593 // EDGE_NEG Negative edge detection 594 // EDGE_DIS No edge detection 595 #define IOC_IOC2_EDGEDET_W 2U 596 #define IOC_IOC2_EDGEDET_M 0x00030000U 597 #define IOC_IOC2_EDGEDET_S 16U 598 #define IOC_IOC2_EDGEDET_EDGE_BOTH 0x00030000U 599 #define IOC_IOC2_EDGEDET_EDGE_POS 0x00020000U 600 #define IOC_IOC2_EDGEDET_EDGE_NEG 0x00010000U 601 #define IOC_IOC2_EDGEDET_EDGE_DIS 0x00000000U 602 603 // Field: [14:13] PULLCTL 604 // 605 // Pull control. Setting this to value 0x3 disables pull. 606 // ENUMs: 607 // PULL_UP Pull up enabled 608 // PULL_DOWN Pull down enabled 609 // PULL_DIS No pull 610 #define IOC_IOC2_PULLCTL_W 2U 611 #define IOC_IOC2_PULLCTL_M 0x00006000U 612 #define IOC_IOC2_PULLCTL_S 13U 613 #define IOC_IOC2_PULLCTL_PULL_UP 0x00004000U 614 #define IOC_IOC2_PULLCTL_PULL_DOWN 0x00002000U 615 #define IOC_IOC2_PULLCTL_PULL_DIS 0x00000000U 616 617 // Field: [2:0] PORTCFG 618 // 619 // Selects usage of DIO2 620 // ENUMs: 621 // DTB Digital Test Bus function 622 // ANA Analog function 623 // PFUNC5 Digital peripheral function-5 624 // PFUNC4 Digital peripheral function-4 625 // PFUNC3 Digital peripheral function-3 626 // PFUNC2 Digital peripheral function-2 627 // PFUNC1 Digital peripheral function-1 628 // BASE Base function 629 #define IOC_IOC2_PORTCFG_W 3U 630 #define IOC_IOC2_PORTCFG_M 0x00000007U 631 #define IOC_IOC2_PORTCFG_S 0U 632 #define IOC_IOC2_PORTCFG_DTB 0x00000007U 633 #define IOC_IOC2_PORTCFG_ANA 0x00000006U 634 #define IOC_IOC2_PORTCFG_PFUNC5 0x00000005U 635 #define IOC_IOC2_PORTCFG_PFUNC4 0x00000004U 636 #define IOC_IOC2_PORTCFG_PFUNC3 0x00000003U 637 #define IOC_IOC2_PORTCFG_PFUNC2 0x00000002U 638 #define IOC_IOC2_PORTCFG_PFUNC1 0x00000001U 639 #define IOC_IOC2_PORTCFG_BASE 0x00000000U 640 641 //***************************************************************************** 642 // 643 // Register: IOC_O_IOC3 644 // 645 //***************************************************************************** 646 // Field: [30] HYSTEN 647 // 648 // This field controls input hysteresis 649 // ENUMs: 650 // EN Input hysteresis enabled 651 // DIS Input hysteresis disabled 652 #define IOC_IOC3_HYSTEN 0x40000000U 653 #define IOC_IOC3_HYSTEN_M 0x40000000U 654 #define IOC_IOC3_HYSTEN_S 30U 655 #define IOC_IOC3_HYSTEN_EN 0x40000000U 656 #define IOC_IOC3_HYSTEN_DIS 0x00000000U 657 658 // Field: [29] INPEN 659 // 660 // This field controls the input capability of DIO 661 // ENUMs: 662 // EN Input enabled 663 // DIS Input disabled 664 #define IOC_IOC3_INPEN 0x20000000U 665 #define IOC_IOC3_INPEN_M 0x20000000U 666 #define IOC_IOC3_INPEN_S 29U 667 #define IOC_IOC3_INPEN_EN 0x20000000U 668 #define IOC_IOC3_INPEN_DIS 0x00000000U 669 670 // Field: [26:24] IOMODE 671 // 672 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 673 // behavior. 674 // ENUMs: 675 // OPENS_INV Open Source, inverted IO 676 // OPENS Open Source, normal IO 677 // OPEND_INV Open Drain, inverted IO 678 // OPEND Open Drain, normal IO 679 // INVERTED Inverted IO 680 // NORMAL Normal IO 681 #define IOC_IOC3_IOMODE_W 3U 682 #define IOC_IOC3_IOMODE_M 0x07000000U 683 #define IOC_IOC3_IOMODE_S 24U 684 #define IOC_IOC3_IOMODE_OPENS_INV 0x05000000U 685 #define IOC_IOC3_IOMODE_OPENS 0x04000000U 686 #define IOC_IOC3_IOMODE_OPEND_INV 0x03000000U 687 #define IOC_IOC3_IOMODE_OPEND 0x02000000U 688 #define IOC_IOC3_IOMODE_INVERTED 0x01000000U 689 #define IOC_IOC3_IOMODE_NORMAL 0x00000000U 690 691 // Field: [21:20] WUCFGSD 692 // 693 // Wakeup configuration from shutdown 694 // ENUMs: 695 // WAKE_HIGH Wakeup triggered when pad level is high 696 // WAKE_LOW Wakeup triggered when pad level is low 697 // DIS_1 Wakeup disabled 698 // DIS_0 Wakeup disabled 699 #define IOC_IOC3_WUCFGSD_W 2U 700 #define IOC_IOC3_WUCFGSD_M 0x00300000U 701 #define IOC_IOC3_WUCFGSD_S 20U 702 #define IOC_IOC3_WUCFGSD_WAKE_HIGH 0x00300000U 703 #define IOC_IOC3_WUCFGSD_WAKE_LOW 0x00200000U 704 #define IOC_IOC3_WUCFGSD_DIS_1 0x00100000U 705 #define IOC_IOC3_WUCFGSD_DIS_0 0x00000000U 706 707 // Field: [18] WUENSB 708 // 709 // Wakeup enable from standby 710 // ENUMs: 711 // EN Wakeup enabled (effective only if EDGEDET is 712 // enabled) 713 // DIS Wakeup disabled 714 #define IOC_IOC3_WUENSB 0x00040000U 715 #define IOC_IOC3_WUENSB_M 0x00040000U 716 #define IOC_IOC3_WUENSB_S 18U 717 #define IOC_IOC3_WUENSB_EN 0x00040000U 718 #define IOC_IOC3_WUENSB_DIS 0x00000000U 719 720 // Field: [17:16] EDGEDET 721 // 722 // Edge detect configuration 723 // ENUMs: 724 // EDGE_BOTH Positive and negative edge detection 725 // EDGE_POS Positive edge detection 726 // EDGE_NEG Negative edge detection 727 // EDGE_DIS No edge detection 728 #define IOC_IOC3_EDGEDET_W 2U 729 #define IOC_IOC3_EDGEDET_M 0x00030000U 730 #define IOC_IOC3_EDGEDET_S 16U 731 #define IOC_IOC3_EDGEDET_EDGE_BOTH 0x00030000U 732 #define IOC_IOC3_EDGEDET_EDGE_POS 0x00020000U 733 #define IOC_IOC3_EDGEDET_EDGE_NEG 0x00010000U 734 #define IOC_IOC3_EDGEDET_EDGE_DIS 0x00000000U 735 736 // Field: [14:13] PULLCTL 737 // 738 // Pull control. Setting this to value 0x3 disables pull. 739 // ENUMs: 740 // PULL_UP Pull up enabled 741 // PULL_DOWN Pull down enabled 742 // PULL_DIS No pull 743 #define IOC_IOC3_PULLCTL_W 2U 744 #define IOC_IOC3_PULLCTL_M 0x00006000U 745 #define IOC_IOC3_PULLCTL_S 13U 746 #define IOC_IOC3_PULLCTL_PULL_UP 0x00004000U 747 #define IOC_IOC3_PULLCTL_PULL_DOWN 0x00002000U 748 #define IOC_IOC3_PULLCTL_PULL_DIS 0x00000000U 749 750 // Field: [2:0] PORTCFG 751 // 752 // Selects usage of DIO3 753 // ENUMs: 754 // DTB Digital Test Bus function 755 // ANA Analog function 756 // PFUNC5 Digital peripheral function-5 757 // PFUNC4 Digital peripheral function-4 758 // PFUNC3 Digital peripheral function-3 759 // PFUNC2 Digital peripheral function-2 760 // PFUNC1 Digital peripheral function-1 761 // BASE Base function 762 #define IOC_IOC3_PORTCFG_W 3U 763 #define IOC_IOC3_PORTCFG_M 0x00000007U 764 #define IOC_IOC3_PORTCFG_S 0U 765 #define IOC_IOC3_PORTCFG_DTB 0x00000007U 766 #define IOC_IOC3_PORTCFG_ANA 0x00000006U 767 #define IOC_IOC3_PORTCFG_PFUNC5 0x00000005U 768 #define IOC_IOC3_PORTCFG_PFUNC4 0x00000004U 769 #define IOC_IOC3_PORTCFG_PFUNC3 0x00000003U 770 #define IOC_IOC3_PORTCFG_PFUNC2 0x00000002U 771 #define IOC_IOC3_PORTCFG_PFUNC1 0x00000001U 772 #define IOC_IOC3_PORTCFG_BASE 0x00000000U 773 774 //***************************************************************************** 775 // 776 // Register: IOC_O_IOC4 777 // 778 //***************************************************************************** 779 // Field: [30] HYSTEN 780 // 781 // This field controls input hysteresis 782 // ENUMs: 783 // EN Input hysteresis enabled 784 // DIS Input hysteresis disabled 785 #define IOC_IOC4_HYSTEN 0x40000000U 786 #define IOC_IOC4_HYSTEN_M 0x40000000U 787 #define IOC_IOC4_HYSTEN_S 30U 788 #define IOC_IOC4_HYSTEN_EN 0x40000000U 789 #define IOC_IOC4_HYSTEN_DIS 0x00000000U 790 791 // Field: [29] INPEN 792 // 793 // This field controls the input capability of DIO 794 // ENUMs: 795 // EN Input enabled 796 // DIS Input disabled 797 #define IOC_IOC4_INPEN 0x20000000U 798 #define IOC_IOC4_INPEN_M 0x20000000U 799 #define IOC_IOC4_INPEN_S 29U 800 #define IOC_IOC4_INPEN_EN 0x20000000U 801 #define IOC_IOC4_INPEN_DIS 0x00000000U 802 803 // Field: [26:24] IOMODE 804 // 805 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 806 // behavior. 807 // ENUMs: 808 // OPENS_INV Open Source, inverted IO 809 // OPENS Open Source, normal IO 810 // OPEND_INV Open Drain, inverted IO 811 // OPEND Open Drain, normal IO 812 // INVERTED Inverted IO 813 // NORMAL Normal IO 814 #define IOC_IOC4_IOMODE_W 3U 815 #define IOC_IOC4_IOMODE_M 0x07000000U 816 #define IOC_IOC4_IOMODE_S 24U 817 #define IOC_IOC4_IOMODE_OPENS_INV 0x05000000U 818 #define IOC_IOC4_IOMODE_OPENS 0x04000000U 819 #define IOC_IOC4_IOMODE_OPEND_INV 0x03000000U 820 #define IOC_IOC4_IOMODE_OPEND 0x02000000U 821 #define IOC_IOC4_IOMODE_INVERTED 0x01000000U 822 #define IOC_IOC4_IOMODE_NORMAL 0x00000000U 823 824 // Field: [21:20] WUCFGSD 825 // 826 // Wakeup configuration from shutdown 827 // ENUMs: 828 // WAKE_HIGH Wakeup triggered when pad level is high 829 // WAKE_LOW Wakeup triggered when pad level is low 830 // DIS_1 Wakeup disabled 831 // DIS_0 Wakeup disabled 832 #define IOC_IOC4_WUCFGSD_W 2U 833 #define IOC_IOC4_WUCFGSD_M 0x00300000U 834 #define IOC_IOC4_WUCFGSD_S 20U 835 #define IOC_IOC4_WUCFGSD_WAKE_HIGH 0x00300000U 836 #define IOC_IOC4_WUCFGSD_WAKE_LOW 0x00200000U 837 #define IOC_IOC4_WUCFGSD_DIS_1 0x00100000U 838 #define IOC_IOC4_WUCFGSD_DIS_0 0x00000000U 839 840 // Field: [18] WUENSB 841 // 842 // Wakeup enable from standby 843 // ENUMs: 844 // EN Wakeup enabled (effective only if EDGEDET is 845 // enabled) 846 // DIS Wakeup disabled 847 #define IOC_IOC4_WUENSB 0x00040000U 848 #define IOC_IOC4_WUENSB_M 0x00040000U 849 #define IOC_IOC4_WUENSB_S 18U 850 #define IOC_IOC4_WUENSB_EN 0x00040000U 851 #define IOC_IOC4_WUENSB_DIS 0x00000000U 852 853 // Field: [17:16] EDGEDET 854 // 855 // Edge detect configuration 856 // ENUMs: 857 // EDGE_BOTH Positive and negative edge detection 858 // EDGE_POS Positive edge detection 859 // EDGE_NEG Negative edge detection 860 // EDGE_DIS No edge detection 861 #define IOC_IOC4_EDGEDET_W 2U 862 #define IOC_IOC4_EDGEDET_M 0x00030000U 863 #define IOC_IOC4_EDGEDET_S 16U 864 #define IOC_IOC4_EDGEDET_EDGE_BOTH 0x00030000U 865 #define IOC_IOC4_EDGEDET_EDGE_POS 0x00020000U 866 #define IOC_IOC4_EDGEDET_EDGE_NEG 0x00010000U 867 #define IOC_IOC4_EDGEDET_EDGE_DIS 0x00000000U 868 869 // Field: [14:13] PULLCTL 870 // 871 // Pull control. Setting this to value 0x3 disables pull. 872 // ENUMs: 873 // PULL_UP Pull up enabled 874 // PULL_DOWN Pull down enabled 875 // PULL_DIS No pull 876 #define IOC_IOC4_PULLCTL_W 2U 877 #define IOC_IOC4_PULLCTL_M 0x00006000U 878 #define IOC_IOC4_PULLCTL_S 13U 879 #define IOC_IOC4_PULLCTL_PULL_UP 0x00004000U 880 #define IOC_IOC4_PULLCTL_PULL_DOWN 0x00002000U 881 #define IOC_IOC4_PULLCTL_PULL_DIS 0x00000000U 882 883 // Field: [2:0] PORTCFG 884 // 885 // Selects usage of DIO4 886 // ENUMs: 887 // DTB Digital Test Bus function 888 // ANA Analog function 889 // PFUNC5 Digital peripheral function-5 890 // PFUNC4 Digital peripheral function-4 891 // PFUNC3 Digital peripheral function-3 892 // PFUNC2 Digital peripheral function-2 893 // PFUNC1 Digital peripheral function-1 894 // BASE Base function 895 #define IOC_IOC4_PORTCFG_W 3U 896 #define IOC_IOC4_PORTCFG_M 0x00000007U 897 #define IOC_IOC4_PORTCFG_S 0U 898 #define IOC_IOC4_PORTCFG_DTB 0x00000007U 899 #define IOC_IOC4_PORTCFG_ANA 0x00000006U 900 #define IOC_IOC4_PORTCFG_PFUNC5 0x00000005U 901 #define IOC_IOC4_PORTCFG_PFUNC4 0x00000004U 902 #define IOC_IOC4_PORTCFG_PFUNC3 0x00000003U 903 #define IOC_IOC4_PORTCFG_PFUNC2 0x00000002U 904 #define IOC_IOC4_PORTCFG_PFUNC1 0x00000001U 905 #define IOC_IOC4_PORTCFG_BASE 0x00000000U 906 907 //***************************************************************************** 908 // 909 // Register: IOC_O_IOC5 910 // 911 //***************************************************************************** 912 // Field: [30] HYSTEN 913 // 914 // This field controls input hysteresis 915 // ENUMs: 916 // EN Input hysteresis enabled 917 // DIS Input hysteresis disabled 918 #define IOC_IOC5_HYSTEN 0x40000000U 919 #define IOC_IOC5_HYSTEN_M 0x40000000U 920 #define IOC_IOC5_HYSTEN_S 30U 921 #define IOC_IOC5_HYSTEN_EN 0x40000000U 922 #define IOC_IOC5_HYSTEN_DIS 0x00000000U 923 924 // Field: [29] INPEN 925 // 926 // This field controls the input capability of DIO 927 // ENUMs: 928 // EN Input enabled 929 // DIS Input disabled 930 #define IOC_IOC5_INPEN 0x20000000U 931 #define IOC_IOC5_INPEN_M 0x20000000U 932 #define IOC_IOC5_INPEN_S 29U 933 #define IOC_IOC5_INPEN_EN 0x20000000U 934 #define IOC_IOC5_INPEN_DIS 0x00000000U 935 936 // Field: [26:24] IOMODE 937 // 938 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 939 // behavior. 940 // ENUMs: 941 // OPENS_INV Open Source, inverted IO 942 // OPENS Open Source, normal IO 943 // OPEND_INV Open Drain, inverted IO 944 // OPEND Open Drain, normal IO 945 // INVERTED Inverted IO 946 // NORMAL Normal IO 947 #define IOC_IOC5_IOMODE_W 3U 948 #define IOC_IOC5_IOMODE_M 0x07000000U 949 #define IOC_IOC5_IOMODE_S 24U 950 #define IOC_IOC5_IOMODE_OPENS_INV 0x05000000U 951 #define IOC_IOC5_IOMODE_OPENS 0x04000000U 952 #define IOC_IOC5_IOMODE_OPEND_INV 0x03000000U 953 #define IOC_IOC5_IOMODE_OPEND 0x02000000U 954 #define IOC_IOC5_IOMODE_INVERTED 0x01000000U 955 #define IOC_IOC5_IOMODE_NORMAL 0x00000000U 956 957 // Field: [21:20] WUCFGSD 958 // 959 // Wakeup configuration from shutdown 960 // ENUMs: 961 // WAKE_HIGH Wakeup triggered when pad level is high 962 // WAKE_LOW Wakeup triggered when pad level is low 963 // DIS_1 Wakeup disabled 964 // DIS_0 Wakeup disabled 965 #define IOC_IOC5_WUCFGSD_W 2U 966 #define IOC_IOC5_WUCFGSD_M 0x00300000U 967 #define IOC_IOC5_WUCFGSD_S 20U 968 #define IOC_IOC5_WUCFGSD_WAKE_HIGH 0x00300000U 969 #define IOC_IOC5_WUCFGSD_WAKE_LOW 0x00200000U 970 #define IOC_IOC5_WUCFGSD_DIS_1 0x00100000U 971 #define IOC_IOC5_WUCFGSD_DIS_0 0x00000000U 972 973 // Field: [18] WUENSB 974 // 975 // Wakeup enable from standby 976 // ENUMs: 977 // EN Wakeup enabled (effective only if EDGEDET is 978 // enabled) 979 // DIS Wakeup disabled 980 #define IOC_IOC5_WUENSB 0x00040000U 981 #define IOC_IOC5_WUENSB_M 0x00040000U 982 #define IOC_IOC5_WUENSB_S 18U 983 #define IOC_IOC5_WUENSB_EN 0x00040000U 984 #define IOC_IOC5_WUENSB_DIS 0x00000000U 985 986 // Field: [17:16] EDGEDET 987 // 988 // Edge detect configuration 989 // ENUMs: 990 // EDGE_BOTH Positive and negative edge detection 991 // EDGE_POS Positive edge detection 992 // EDGE_NEG Negative edge detection 993 // EDGE_DIS No edge detection 994 #define IOC_IOC5_EDGEDET_W 2U 995 #define IOC_IOC5_EDGEDET_M 0x00030000U 996 #define IOC_IOC5_EDGEDET_S 16U 997 #define IOC_IOC5_EDGEDET_EDGE_BOTH 0x00030000U 998 #define IOC_IOC5_EDGEDET_EDGE_POS 0x00020000U 999 #define IOC_IOC5_EDGEDET_EDGE_NEG 0x00010000U 1000 #define IOC_IOC5_EDGEDET_EDGE_DIS 0x00000000U 1001 1002 // Field: [14:13] PULLCTL 1003 // 1004 // Pull control. Setting this to value 0x3 disables pull. 1005 // ENUMs: 1006 // PULL_UP Pull up enabled 1007 // PULL_DOWN Pull down enabled 1008 // PULL_DIS No pull 1009 #define IOC_IOC5_PULLCTL_W 2U 1010 #define IOC_IOC5_PULLCTL_M 0x00006000U 1011 #define IOC_IOC5_PULLCTL_S 13U 1012 #define IOC_IOC5_PULLCTL_PULL_UP 0x00004000U 1013 #define IOC_IOC5_PULLCTL_PULL_DOWN 0x00002000U 1014 #define IOC_IOC5_PULLCTL_PULL_DIS 0x00000000U 1015 1016 // Field: [2:0] PORTCFG 1017 // 1018 // Selects usage of DIO5 1019 // ENUMs: 1020 // DTB Digital Test Bus function 1021 // ANA Analog function 1022 // PFUNC5 Digital peripheral function-5 1023 // PFUNC4 Digital peripheral function-4 1024 // PFUNC3 Digital peripheral function-3 1025 // PFUNC2 Digital peripheral function-2 1026 // PFUNC1 Digital peripheral function-1 1027 // BASE Base function 1028 #define IOC_IOC5_PORTCFG_W 3U 1029 #define IOC_IOC5_PORTCFG_M 0x00000007U 1030 #define IOC_IOC5_PORTCFG_S 0U 1031 #define IOC_IOC5_PORTCFG_DTB 0x00000007U 1032 #define IOC_IOC5_PORTCFG_ANA 0x00000006U 1033 #define IOC_IOC5_PORTCFG_PFUNC5 0x00000005U 1034 #define IOC_IOC5_PORTCFG_PFUNC4 0x00000004U 1035 #define IOC_IOC5_PORTCFG_PFUNC3 0x00000003U 1036 #define IOC_IOC5_PORTCFG_PFUNC2 0x00000002U 1037 #define IOC_IOC5_PORTCFG_PFUNC1 0x00000001U 1038 #define IOC_IOC5_PORTCFG_BASE 0x00000000U 1039 1040 //***************************************************************************** 1041 // 1042 // Register: IOC_O_IOC6 1043 // 1044 //***************************************************************************** 1045 // Field: [30] HYSTEN 1046 // 1047 // This field controls input hysteresis 1048 // ENUMs: 1049 // EN Input hysteresis enabled 1050 // DIS Input hysteresis disabled 1051 #define IOC_IOC6_HYSTEN 0x40000000U 1052 #define IOC_IOC6_HYSTEN_M 0x40000000U 1053 #define IOC_IOC6_HYSTEN_S 30U 1054 #define IOC_IOC6_HYSTEN_EN 0x40000000U 1055 #define IOC_IOC6_HYSTEN_DIS 0x00000000U 1056 1057 // Field: [29] INPEN 1058 // 1059 // This field controls the input capability of DIO 1060 // ENUMs: 1061 // EN Input enabled 1062 // DIS Input disabled 1063 #define IOC_IOC6_INPEN 0x20000000U 1064 #define IOC_IOC6_INPEN_M 0x20000000U 1065 #define IOC_IOC6_INPEN_S 29U 1066 #define IOC_IOC6_INPEN_EN 0x20000000U 1067 #define IOC_IOC6_INPEN_DIS 0x00000000U 1068 1069 // Field: [26:24] IOMODE 1070 // 1071 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 1072 // behavior. 1073 // ENUMs: 1074 // OPENS_INV Open Source, inverted IO 1075 // OPENS Open Source, normal IO 1076 // OPEND_INV Open Drain, inverted IO 1077 // OPEND Open Drain, normal IO 1078 // INVERTED Inverted IO 1079 // NORMAL Normal IO 1080 #define IOC_IOC6_IOMODE_W 3U 1081 #define IOC_IOC6_IOMODE_M 0x07000000U 1082 #define IOC_IOC6_IOMODE_S 24U 1083 #define IOC_IOC6_IOMODE_OPENS_INV 0x05000000U 1084 #define IOC_IOC6_IOMODE_OPENS 0x04000000U 1085 #define IOC_IOC6_IOMODE_OPEND_INV 0x03000000U 1086 #define IOC_IOC6_IOMODE_OPEND 0x02000000U 1087 #define IOC_IOC6_IOMODE_INVERTED 0x01000000U 1088 #define IOC_IOC6_IOMODE_NORMAL 0x00000000U 1089 1090 // Field: [21:20] WUCFGSD 1091 // 1092 // Wakeup configuration from shutdown 1093 // ENUMs: 1094 // WAKE_HIGH Wakeup triggered when pad level is high 1095 // WAKE_LOW Wakeup triggered when pad level is low 1096 // DIS_1 Wakeup disabled 1097 // DIS_0 Wakeup disabled 1098 #define IOC_IOC6_WUCFGSD_W 2U 1099 #define IOC_IOC6_WUCFGSD_M 0x00300000U 1100 #define IOC_IOC6_WUCFGSD_S 20U 1101 #define IOC_IOC6_WUCFGSD_WAKE_HIGH 0x00300000U 1102 #define IOC_IOC6_WUCFGSD_WAKE_LOW 0x00200000U 1103 #define IOC_IOC6_WUCFGSD_DIS_1 0x00100000U 1104 #define IOC_IOC6_WUCFGSD_DIS_0 0x00000000U 1105 1106 // Field: [18] WUENSB 1107 // 1108 // Wakeup enable from standby 1109 // ENUMs: 1110 // EN Wakeup enabled (effective only if EDGEDET is 1111 // enabled) 1112 // DIS Wakeup disabled 1113 #define IOC_IOC6_WUENSB 0x00040000U 1114 #define IOC_IOC6_WUENSB_M 0x00040000U 1115 #define IOC_IOC6_WUENSB_S 18U 1116 #define IOC_IOC6_WUENSB_EN 0x00040000U 1117 #define IOC_IOC6_WUENSB_DIS 0x00000000U 1118 1119 // Field: [17:16] EDGEDET 1120 // 1121 // Edge detect configuration 1122 // ENUMs: 1123 // EDGE_BOTH Positive and negative edge detection 1124 // EDGE_POS Positive edge detection 1125 // EDGE_NEG Negative edge detection 1126 // EDGE_DIS No edge detection 1127 #define IOC_IOC6_EDGEDET_W 2U 1128 #define IOC_IOC6_EDGEDET_M 0x00030000U 1129 #define IOC_IOC6_EDGEDET_S 16U 1130 #define IOC_IOC6_EDGEDET_EDGE_BOTH 0x00030000U 1131 #define IOC_IOC6_EDGEDET_EDGE_POS 0x00020000U 1132 #define IOC_IOC6_EDGEDET_EDGE_NEG 0x00010000U 1133 #define IOC_IOC6_EDGEDET_EDGE_DIS 0x00000000U 1134 1135 // Field: [14:13] PULLCTL 1136 // 1137 // Pull control. Setting this to value 0x3 disables pull. 1138 // ENUMs: 1139 // PULL_UP Pull up enabled 1140 // PULL_DOWN Pull down enabled 1141 // PULL_DIS No pull 1142 #define IOC_IOC6_PULLCTL_W 2U 1143 #define IOC_IOC6_PULLCTL_M 0x00006000U 1144 #define IOC_IOC6_PULLCTL_S 13U 1145 #define IOC_IOC6_PULLCTL_PULL_UP 0x00004000U 1146 #define IOC_IOC6_PULLCTL_PULL_DOWN 0x00002000U 1147 #define IOC_IOC6_PULLCTL_PULL_DIS 0x00000000U 1148 1149 // Field: [2:0] PORTCFG 1150 // 1151 // Selects usage of DIO6 1152 // ENUMs: 1153 // DTB Digital Test Bus function 1154 // ANA Analog function 1155 // PFUNC5 Digital peripheral function-5 1156 // PFUNC4 Digital peripheral function-4 1157 // PFUNC3 Digital peripheral function-3 1158 // PFUNC2 Digital peripheral function-2 1159 // PFUNC1 Digital peripheral function-1 1160 // BASE Base function 1161 #define IOC_IOC6_PORTCFG_W 3U 1162 #define IOC_IOC6_PORTCFG_M 0x00000007U 1163 #define IOC_IOC6_PORTCFG_S 0U 1164 #define IOC_IOC6_PORTCFG_DTB 0x00000007U 1165 #define IOC_IOC6_PORTCFG_ANA 0x00000006U 1166 #define IOC_IOC6_PORTCFG_PFUNC5 0x00000005U 1167 #define IOC_IOC6_PORTCFG_PFUNC4 0x00000004U 1168 #define IOC_IOC6_PORTCFG_PFUNC3 0x00000003U 1169 #define IOC_IOC6_PORTCFG_PFUNC2 0x00000002U 1170 #define IOC_IOC6_PORTCFG_PFUNC1 0x00000001U 1171 #define IOC_IOC6_PORTCFG_BASE 0x00000000U 1172 1173 //***************************************************************************** 1174 // 1175 // Register: IOC_O_IOC7 1176 // 1177 //***************************************************************************** 1178 // Field: [30] HYSTEN 1179 // 1180 // This field controls input hysteresis 1181 // ENUMs: 1182 // EN Input hysteresis enabled 1183 // DIS Input hysteresis disabled 1184 #define IOC_IOC7_HYSTEN 0x40000000U 1185 #define IOC_IOC7_HYSTEN_M 0x40000000U 1186 #define IOC_IOC7_HYSTEN_S 30U 1187 #define IOC_IOC7_HYSTEN_EN 0x40000000U 1188 #define IOC_IOC7_HYSTEN_DIS 0x00000000U 1189 1190 // Field: [29] INPEN 1191 // 1192 // This field controls the input capability of DIO 1193 // ENUMs: 1194 // EN Input enabled 1195 // DIS Input disabled 1196 #define IOC_IOC7_INPEN 0x20000000U 1197 #define IOC_IOC7_INPEN_M 0x20000000U 1198 #define IOC_IOC7_INPEN_S 29U 1199 #define IOC_IOC7_INPEN_EN 0x20000000U 1200 #define IOC_IOC7_INPEN_DIS 0x00000000U 1201 1202 // Field: [26:24] IOMODE 1203 // 1204 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 1205 // behavior. 1206 // ENUMs: 1207 // OPENS_INV Open Source, inverted IO 1208 // OPENS Open Source, normal IO 1209 // OPEND_INV Open Drain, inverted IO 1210 // OPEND Open Drain, normal IO 1211 // INVERTED Inverted IO 1212 // NORMAL Normal IO 1213 #define IOC_IOC7_IOMODE_W 3U 1214 #define IOC_IOC7_IOMODE_M 0x07000000U 1215 #define IOC_IOC7_IOMODE_S 24U 1216 #define IOC_IOC7_IOMODE_OPENS_INV 0x05000000U 1217 #define IOC_IOC7_IOMODE_OPENS 0x04000000U 1218 #define IOC_IOC7_IOMODE_OPEND_INV 0x03000000U 1219 #define IOC_IOC7_IOMODE_OPEND 0x02000000U 1220 #define IOC_IOC7_IOMODE_INVERTED 0x01000000U 1221 #define IOC_IOC7_IOMODE_NORMAL 0x00000000U 1222 1223 // Field: [21:20] WUCFGSD 1224 // 1225 // Wakeup configuration from shutdown 1226 // ENUMs: 1227 // WAKE_HIGH Wakeup triggered when pad level is high 1228 // WAKE_LOW Wakeup triggered when pad level is low 1229 // DIS_1 Wakeup disabled 1230 // DIS_0 Wakeup disabled 1231 #define IOC_IOC7_WUCFGSD_W 2U 1232 #define IOC_IOC7_WUCFGSD_M 0x00300000U 1233 #define IOC_IOC7_WUCFGSD_S 20U 1234 #define IOC_IOC7_WUCFGSD_WAKE_HIGH 0x00300000U 1235 #define IOC_IOC7_WUCFGSD_WAKE_LOW 0x00200000U 1236 #define IOC_IOC7_WUCFGSD_DIS_1 0x00100000U 1237 #define IOC_IOC7_WUCFGSD_DIS_0 0x00000000U 1238 1239 // Field: [18] WUENSB 1240 // 1241 // Wakeup enable from standby 1242 // ENUMs: 1243 // EN Wakeup enabled (effective only if EDGEDET is 1244 // enabled) 1245 // DIS Wakeup disabled 1246 #define IOC_IOC7_WUENSB 0x00040000U 1247 #define IOC_IOC7_WUENSB_M 0x00040000U 1248 #define IOC_IOC7_WUENSB_S 18U 1249 #define IOC_IOC7_WUENSB_EN 0x00040000U 1250 #define IOC_IOC7_WUENSB_DIS 0x00000000U 1251 1252 // Field: [17:16] EDGEDET 1253 // 1254 // Edge detect configuration 1255 // ENUMs: 1256 // EDGE_BOTH Positive and negative edge detection 1257 // EDGE_POS Positive edge detection 1258 // EDGE_NEG Negative edge detection 1259 // EDGE_DIS No edge detection 1260 #define IOC_IOC7_EDGEDET_W 2U 1261 #define IOC_IOC7_EDGEDET_M 0x00030000U 1262 #define IOC_IOC7_EDGEDET_S 16U 1263 #define IOC_IOC7_EDGEDET_EDGE_BOTH 0x00030000U 1264 #define IOC_IOC7_EDGEDET_EDGE_POS 0x00020000U 1265 #define IOC_IOC7_EDGEDET_EDGE_NEG 0x00010000U 1266 #define IOC_IOC7_EDGEDET_EDGE_DIS 0x00000000U 1267 1268 // Field: [14:13] PULLCTL 1269 // 1270 // Pull control. Setting this to value 0x3 disables pull. 1271 // ENUMs: 1272 // PULL_UP Pull up enabled 1273 // PULL_DOWN Pull down enabled 1274 // PULL_DIS No pull 1275 #define IOC_IOC7_PULLCTL_W 2U 1276 #define IOC_IOC7_PULLCTL_M 0x00006000U 1277 #define IOC_IOC7_PULLCTL_S 13U 1278 #define IOC_IOC7_PULLCTL_PULL_UP 0x00004000U 1279 #define IOC_IOC7_PULLCTL_PULL_DOWN 0x00002000U 1280 #define IOC_IOC7_PULLCTL_PULL_DIS 0x00000000U 1281 1282 // Field: [2:0] PORTCFG 1283 // 1284 // Selects usage of DIO7 1285 // ENUMs: 1286 // DTB Digital Test Bus function 1287 // ANA Analog function 1288 // PFUNC5 Digital peripheral function-5 1289 // PFUNC4 Digital peripheral function-4 1290 // PFUNC3 Digital peripheral function-3 1291 // PFUNC2 Digital peripheral function-2 1292 // PFUNC1 Digital peripheral function-1 1293 // BASE Base function 1294 #define IOC_IOC7_PORTCFG_W 3U 1295 #define IOC_IOC7_PORTCFG_M 0x00000007U 1296 #define IOC_IOC7_PORTCFG_S 0U 1297 #define IOC_IOC7_PORTCFG_DTB 0x00000007U 1298 #define IOC_IOC7_PORTCFG_ANA 0x00000006U 1299 #define IOC_IOC7_PORTCFG_PFUNC5 0x00000005U 1300 #define IOC_IOC7_PORTCFG_PFUNC4 0x00000004U 1301 #define IOC_IOC7_PORTCFG_PFUNC3 0x00000003U 1302 #define IOC_IOC7_PORTCFG_PFUNC2 0x00000002U 1303 #define IOC_IOC7_PORTCFG_PFUNC1 0x00000001U 1304 #define IOC_IOC7_PORTCFG_BASE 0x00000000U 1305 1306 //***************************************************************************** 1307 // 1308 // Register: IOC_O_IOC8 1309 // 1310 //***************************************************************************** 1311 // Field: [30] HYSTEN 1312 // 1313 // This field controls input hysteresis 1314 // ENUMs: 1315 // EN Input hysteresis enabled 1316 // DIS Input hysteresis disabled 1317 #define IOC_IOC8_HYSTEN 0x40000000U 1318 #define IOC_IOC8_HYSTEN_M 0x40000000U 1319 #define IOC_IOC8_HYSTEN_S 30U 1320 #define IOC_IOC8_HYSTEN_EN 0x40000000U 1321 #define IOC_IOC8_HYSTEN_DIS 0x00000000U 1322 1323 // Field: [29] INPEN 1324 // 1325 // This field controls the input capability of DIO 1326 // ENUMs: 1327 // EN Input enabled 1328 // DIS Input disabled 1329 #define IOC_IOC8_INPEN 0x20000000U 1330 #define IOC_IOC8_INPEN_M 0x20000000U 1331 #define IOC_IOC8_INPEN_S 29U 1332 #define IOC_IOC8_INPEN_EN 0x20000000U 1333 #define IOC_IOC8_INPEN_DIS 0x00000000U 1334 1335 // Field: [26:24] IOMODE 1336 // 1337 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 1338 // behavior. 1339 // ENUMs: 1340 // OPENS_INV Open Source, inverted IO 1341 // OPENS Open Source, normal IO 1342 // OPEND_INV Open Drain, inverted IO 1343 // OPEND Open Drain, normal IO 1344 // INVERTED Inverted IO 1345 // NORMAL Normal IO 1346 #define IOC_IOC8_IOMODE_W 3U 1347 #define IOC_IOC8_IOMODE_M 0x07000000U 1348 #define IOC_IOC8_IOMODE_S 24U 1349 #define IOC_IOC8_IOMODE_OPENS_INV 0x05000000U 1350 #define IOC_IOC8_IOMODE_OPENS 0x04000000U 1351 #define IOC_IOC8_IOMODE_OPEND_INV 0x03000000U 1352 #define IOC_IOC8_IOMODE_OPEND 0x02000000U 1353 #define IOC_IOC8_IOMODE_INVERTED 0x01000000U 1354 #define IOC_IOC8_IOMODE_NORMAL 0x00000000U 1355 1356 // Field: [21:20] WUCFGSD 1357 // 1358 // Wakeup configuration from shutdown 1359 // ENUMs: 1360 // WAKE_HIGH Wakeup triggered when pad level is high 1361 // WAKE_LOW Wakeup triggered when pad level is low 1362 // DIS_1 Wakeup disabled 1363 // DIS_0 Wakeup disabled 1364 #define IOC_IOC8_WUCFGSD_W 2U 1365 #define IOC_IOC8_WUCFGSD_M 0x00300000U 1366 #define IOC_IOC8_WUCFGSD_S 20U 1367 #define IOC_IOC8_WUCFGSD_WAKE_HIGH 0x00300000U 1368 #define IOC_IOC8_WUCFGSD_WAKE_LOW 0x00200000U 1369 #define IOC_IOC8_WUCFGSD_DIS_1 0x00100000U 1370 #define IOC_IOC8_WUCFGSD_DIS_0 0x00000000U 1371 1372 // Field: [18] WUENSB 1373 // 1374 // Wakeup enable from standby 1375 // ENUMs: 1376 // EN Wakeup enabled (effective only if EDGEDET is 1377 // enabled) 1378 // DIS Wakeup disabled 1379 #define IOC_IOC8_WUENSB 0x00040000U 1380 #define IOC_IOC8_WUENSB_M 0x00040000U 1381 #define IOC_IOC8_WUENSB_S 18U 1382 #define IOC_IOC8_WUENSB_EN 0x00040000U 1383 #define IOC_IOC8_WUENSB_DIS 0x00000000U 1384 1385 // Field: [17:16] EDGEDET 1386 // 1387 // Edge detect configuration 1388 // ENUMs: 1389 // EDGE_BOTH Positive and negative edge detection 1390 // EDGE_POS Positive edge detection 1391 // EDGE_NEG Negative edge detection 1392 // EDGE_DIS No edge detection 1393 #define IOC_IOC8_EDGEDET_W 2U 1394 #define IOC_IOC8_EDGEDET_M 0x00030000U 1395 #define IOC_IOC8_EDGEDET_S 16U 1396 #define IOC_IOC8_EDGEDET_EDGE_BOTH 0x00030000U 1397 #define IOC_IOC8_EDGEDET_EDGE_POS 0x00020000U 1398 #define IOC_IOC8_EDGEDET_EDGE_NEG 0x00010000U 1399 #define IOC_IOC8_EDGEDET_EDGE_DIS 0x00000000U 1400 1401 // Field: [14:13] PULLCTL 1402 // 1403 // Pull control. Setting this to value 0x3 disables pull. 1404 // ENUMs: 1405 // PULL_UP Pull up enabled 1406 // PULL_DOWN Pull down enabled 1407 // PULL_DIS No pull 1408 #define IOC_IOC8_PULLCTL_W 2U 1409 #define IOC_IOC8_PULLCTL_M 0x00006000U 1410 #define IOC_IOC8_PULLCTL_S 13U 1411 #define IOC_IOC8_PULLCTL_PULL_UP 0x00004000U 1412 #define IOC_IOC8_PULLCTL_PULL_DOWN 0x00002000U 1413 #define IOC_IOC8_PULLCTL_PULL_DIS 0x00000000U 1414 1415 // Field: [2:0] PORTCFG 1416 // 1417 // Selects usage of DIO8 1418 // ENUMs: 1419 // DTB Digital Test Bus function 1420 // ANA Analog function 1421 // PFUNC5 Digital peripheral function-5 1422 // PFUNC4 Digital peripheral function-4 1423 // PFUNC3 Digital peripheral function-3 1424 // PFUNC2 Digital peripheral function-2 1425 // PFUNC1 Digital peripheral function-1 1426 // BASE Base function 1427 #define IOC_IOC8_PORTCFG_W 3U 1428 #define IOC_IOC8_PORTCFG_M 0x00000007U 1429 #define IOC_IOC8_PORTCFG_S 0U 1430 #define IOC_IOC8_PORTCFG_DTB 0x00000007U 1431 #define IOC_IOC8_PORTCFG_ANA 0x00000006U 1432 #define IOC_IOC8_PORTCFG_PFUNC5 0x00000005U 1433 #define IOC_IOC8_PORTCFG_PFUNC4 0x00000004U 1434 #define IOC_IOC8_PORTCFG_PFUNC3 0x00000003U 1435 #define IOC_IOC8_PORTCFG_PFUNC2 0x00000002U 1436 #define IOC_IOC8_PORTCFG_PFUNC1 0x00000001U 1437 #define IOC_IOC8_PORTCFG_BASE 0x00000000U 1438 1439 //***************************************************************************** 1440 // 1441 // Register: IOC_O_IOC9 1442 // 1443 //***************************************************************************** 1444 // Field: [30] HYSTEN 1445 // 1446 // This field controls input hysteresis 1447 // ENUMs: 1448 // EN Input hysteresis enabled 1449 // DIS Input hysteresis disabled 1450 #define IOC_IOC9_HYSTEN 0x40000000U 1451 #define IOC_IOC9_HYSTEN_M 0x40000000U 1452 #define IOC_IOC9_HYSTEN_S 30U 1453 #define IOC_IOC9_HYSTEN_EN 0x40000000U 1454 #define IOC_IOC9_HYSTEN_DIS 0x00000000U 1455 1456 // Field: [29] INPEN 1457 // 1458 // This field controls the input capability of DIO 1459 // ENUMs: 1460 // EN Input enabled 1461 // DIS Input disabled 1462 #define IOC_IOC9_INPEN 0x20000000U 1463 #define IOC_IOC9_INPEN_M 0x20000000U 1464 #define IOC_IOC9_INPEN_S 29U 1465 #define IOC_IOC9_INPEN_EN 0x20000000U 1466 #define IOC_IOC9_INPEN_DIS 0x00000000U 1467 1468 // Field: [26:24] IOMODE 1469 // 1470 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 1471 // behavior. 1472 // ENUMs: 1473 // OPENS_INV Open Source, inverted IO 1474 // OPENS Open Source, normal IO 1475 // OPEND_INV Open Drain, inverted IO 1476 // OPEND Open Drain, normal IO 1477 // INVERTED Inverted IO 1478 // NORMAL Normal IO 1479 #define IOC_IOC9_IOMODE_W 3U 1480 #define IOC_IOC9_IOMODE_M 0x07000000U 1481 #define IOC_IOC9_IOMODE_S 24U 1482 #define IOC_IOC9_IOMODE_OPENS_INV 0x05000000U 1483 #define IOC_IOC9_IOMODE_OPENS 0x04000000U 1484 #define IOC_IOC9_IOMODE_OPEND_INV 0x03000000U 1485 #define IOC_IOC9_IOMODE_OPEND 0x02000000U 1486 #define IOC_IOC9_IOMODE_INVERTED 0x01000000U 1487 #define IOC_IOC9_IOMODE_NORMAL 0x00000000U 1488 1489 // Field: [21:20] WUCFGSD 1490 // 1491 // Wakeup configuration from shutdown 1492 // ENUMs: 1493 // WAKE_HIGH Wakeup triggered when pad level is high 1494 // WAKE_LOW Wakeup triggered when pad level is low 1495 // DIS_1 Wakeup disabled 1496 // DIS_0 Wakeup disabled 1497 #define IOC_IOC9_WUCFGSD_W 2U 1498 #define IOC_IOC9_WUCFGSD_M 0x00300000U 1499 #define IOC_IOC9_WUCFGSD_S 20U 1500 #define IOC_IOC9_WUCFGSD_WAKE_HIGH 0x00300000U 1501 #define IOC_IOC9_WUCFGSD_WAKE_LOW 0x00200000U 1502 #define IOC_IOC9_WUCFGSD_DIS_1 0x00100000U 1503 #define IOC_IOC9_WUCFGSD_DIS_0 0x00000000U 1504 1505 // Field: [18] WUENSB 1506 // 1507 // Wakeup enable from standby 1508 // ENUMs: 1509 // EN Wakeup enabled (effective only if EDGEDET is 1510 // enabled) 1511 // DIS Wakeup disabled 1512 #define IOC_IOC9_WUENSB 0x00040000U 1513 #define IOC_IOC9_WUENSB_M 0x00040000U 1514 #define IOC_IOC9_WUENSB_S 18U 1515 #define IOC_IOC9_WUENSB_EN 0x00040000U 1516 #define IOC_IOC9_WUENSB_DIS 0x00000000U 1517 1518 // Field: [17:16] EDGEDET 1519 // 1520 // Edge detect configuration 1521 // ENUMs: 1522 // EDGE_BOTH Positive and negative edge detection 1523 // EDGE_POS Positive edge detection 1524 // EDGE_NEG Negative edge detection 1525 // EDGE_DIS No edge detection 1526 #define IOC_IOC9_EDGEDET_W 2U 1527 #define IOC_IOC9_EDGEDET_M 0x00030000U 1528 #define IOC_IOC9_EDGEDET_S 16U 1529 #define IOC_IOC9_EDGEDET_EDGE_BOTH 0x00030000U 1530 #define IOC_IOC9_EDGEDET_EDGE_POS 0x00020000U 1531 #define IOC_IOC9_EDGEDET_EDGE_NEG 0x00010000U 1532 #define IOC_IOC9_EDGEDET_EDGE_DIS 0x00000000U 1533 1534 // Field: [14:13] PULLCTL 1535 // 1536 // Pull control. Setting this to value 0x3 disables pull. 1537 // ENUMs: 1538 // PULL_UP Pull up enabled 1539 // PULL_DOWN Pull down enabled 1540 // PULL_DIS No pull 1541 #define IOC_IOC9_PULLCTL_W 2U 1542 #define IOC_IOC9_PULLCTL_M 0x00006000U 1543 #define IOC_IOC9_PULLCTL_S 13U 1544 #define IOC_IOC9_PULLCTL_PULL_UP 0x00004000U 1545 #define IOC_IOC9_PULLCTL_PULL_DOWN 0x00002000U 1546 #define IOC_IOC9_PULLCTL_PULL_DIS 0x00000000U 1547 1548 // Field: [2:0] PORTCFG 1549 // 1550 // Selects usage of DIO9 1551 // ENUMs: 1552 // DTB Digital Test Bus function 1553 // ANA Analog function 1554 // PFUNC5 Digital peripheral function-5 1555 // PFUNC4 Digital peripheral function-4 1556 // PFUNC3 Digital peripheral function-3 1557 // PFUNC2 Digital peripheral function-2 1558 // PFUNC1 Digital peripheral function-1 1559 // BASE Base function 1560 #define IOC_IOC9_PORTCFG_W 3U 1561 #define IOC_IOC9_PORTCFG_M 0x00000007U 1562 #define IOC_IOC9_PORTCFG_S 0U 1563 #define IOC_IOC9_PORTCFG_DTB 0x00000007U 1564 #define IOC_IOC9_PORTCFG_ANA 0x00000006U 1565 #define IOC_IOC9_PORTCFG_PFUNC5 0x00000005U 1566 #define IOC_IOC9_PORTCFG_PFUNC4 0x00000004U 1567 #define IOC_IOC9_PORTCFG_PFUNC3 0x00000003U 1568 #define IOC_IOC9_PORTCFG_PFUNC2 0x00000002U 1569 #define IOC_IOC9_PORTCFG_PFUNC1 0x00000001U 1570 #define IOC_IOC9_PORTCFG_BASE 0x00000000U 1571 1572 //***************************************************************************** 1573 // 1574 // Register: IOC_O_IOC10 1575 // 1576 //***************************************************************************** 1577 // Field: [30] HYSTEN 1578 // 1579 // This field controls input hysteresis 1580 // ENUMs: 1581 // EN Input hysteresis enabled 1582 // DIS Input hysteresis disabled 1583 #define IOC_IOC10_HYSTEN 0x40000000U 1584 #define IOC_IOC10_HYSTEN_M 0x40000000U 1585 #define IOC_IOC10_HYSTEN_S 30U 1586 #define IOC_IOC10_HYSTEN_EN 0x40000000U 1587 #define IOC_IOC10_HYSTEN_DIS 0x00000000U 1588 1589 // Field: [29] INPEN 1590 // 1591 // This field controls the input capability of DIO 1592 // ENUMs: 1593 // EN Input enabled 1594 // DIS Input disabled 1595 #define IOC_IOC10_INPEN 0x20000000U 1596 #define IOC_IOC10_INPEN_M 0x20000000U 1597 #define IOC_IOC10_INPEN_S 29U 1598 #define IOC_IOC10_INPEN_EN 0x20000000U 1599 #define IOC_IOC10_INPEN_DIS 0x00000000U 1600 1601 // Field: [26:24] IOMODE 1602 // 1603 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 1604 // behavior. 1605 // ENUMs: 1606 // OPENS_INV Open Source, inverted IO 1607 // OPENS Open Source, normal IO 1608 // OPEND_INV Open Drain, inverted IO 1609 // OPEND Open Drain, normal IO 1610 // INVERTED Inverted IO 1611 // NORMAL Normal IO 1612 #define IOC_IOC10_IOMODE_W 3U 1613 #define IOC_IOC10_IOMODE_M 0x07000000U 1614 #define IOC_IOC10_IOMODE_S 24U 1615 #define IOC_IOC10_IOMODE_OPENS_INV 0x05000000U 1616 #define IOC_IOC10_IOMODE_OPENS 0x04000000U 1617 #define IOC_IOC10_IOMODE_OPEND_INV 0x03000000U 1618 #define IOC_IOC10_IOMODE_OPEND 0x02000000U 1619 #define IOC_IOC10_IOMODE_INVERTED 0x01000000U 1620 #define IOC_IOC10_IOMODE_NORMAL 0x00000000U 1621 1622 // Field: [21:20] WUCFGSD 1623 // 1624 // Wakeup configuration from shutdown 1625 // ENUMs: 1626 // WAKE_HIGH Wakeup triggered when pad level is high 1627 // WAKE_LOW Wakeup triggered when pad level is low 1628 // DIS_1 Wakeup disabled 1629 // DIS_0 Wakeup disabled 1630 #define IOC_IOC10_WUCFGSD_W 2U 1631 #define IOC_IOC10_WUCFGSD_M 0x00300000U 1632 #define IOC_IOC10_WUCFGSD_S 20U 1633 #define IOC_IOC10_WUCFGSD_WAKE_HIGH 0x00300000U 1634 #define IOC_IOC10_WUCFGSD_WAKE_LOW 0x00200000U 1635 #define IOC_IOC10_WUCFGSD_DIS_1 0x00100000U 1636 #define IOC_IOC10_WUCFGSD_DIS_0 0x00000000U 1637 1638 // Field: [18] WUENSB 1639 // 1640 // Wakeup enable from standby 1641 // ENUMs: 1642 // EN Wakeup enabled (effective only if EDGEDET is 1643 // enabled) 1644 // DIS Wakeup disabled 1645 #define IOC_IOC10_WUENSB 0x00040000U 1646 #define IOC_IOC10_WUENSB_M 0x00040000U 1647 #define IOC_IOC10_WUENSB_S 18U 1648 #define IOC_IOC10_WUENSB_EN 0x00040000U 1649 #define IOC_IOC10_WUENSB_DIS 0x00000000U 1650 1651 // Field: [17:16] EDGEDET 1652 // 1653 // Edge detect configuration 1654 // ENUMs: 1655 // EDGE_BOTH Positive and negative edge detection 1656 // EDGE_POS Positive edge detection 1657 // EDGE_NEG Negative edge detection 1658 // EDGE_DIS No edge detection 1659 #define IOC_IOC10_EDGEDET_W 2U 1660 #define IOC_IOC10_EDGEDET_M 0x00030000U 1661 #define IOC_IOC10_EDGEDET_S 16U 1662 #define IOC_IOC10_EDGEDET_EDGE_BOTH 0x00030000U 1663 #define IOC_IOC10_EDGEDET_EDGE_POS 0x00020000U 1664 #define IOC_IOC10_EDGEDET_EDGE_NEG 0x00010000U 1665 #define IOC_IOC10_EDGEDET_EDGE_DIS 0x00000000U 1666 1667 // Field: [14:13] PULLCTL 1668 // 1669 // Pull control. Setting this to value 0x3 disables pull. 1670 // ENUMs: 1671 // PULL_UP Pull up enabled 1672 // PULL_DOWN Pull down enabled 1673 // PULL_DIS No pull 1674 #define IOC_IOC10_PULLCTL_W 2U 1675 #define IOC_IOC10_PULLCTL_M 0x00006000U 1676 #define IOC_IOC10_PULLCTL_S 13U 1677 #define IOC_IOC10_PULLCTL_PULL_UP 0x00004000U 1678 #define IOC_IOC10_PULLCTL_PULL_DOWN 0x00002000U 1679 #define IOC_IOC10_PULLCTL_PULL_DIS 0x00000000U 1680 1681 // Field: [2:0] PORTCFG 1682 // 1683 // Selects usage of DIO10 1684 // ENUMs: 1685 // DTB Digital Test Bus function 1686 // ANA Analog function 1687 // PFUNC5 Digital peripheral function-5 1688 // PFUNC4 Digital peripheral function-4 1689 // PFUNC3 Digital peripheral function-3 1690 // PFUNC2 Digital peripheral function-2 1691 // PFUNC1 Digital peripheral function-1 1692 // BASE Base function 1693 #define IOC_IOC10_PORTCFG_W 3U 1694 #define IOC_IOC10_PORTCFG_M 0x00000007U 1695 #define IOC_IOC10_PORTCFG_S 0U 1696 #define IOC_IOC10_PORTCFG_DTB 0x00000007U 1697 #define IOC_IOC10_PORTCFG_ANA 0x00000006U 1698 #define IOC_IOC10_PORTCFG_PFUNC5 0x00000005U 1699 #define IOC_IOC10_PORTCFG_PFUNC4 0x00000004U 1700 #define IOC_IOC10_PORTCFG_PFUNC3 0x00000003U 1701 #define IOC_IOC10_PORTCFG_PFUNC2 0x00000002U 1702 #define IOC_IOC10_PORTCFG_PFUNC1 0x00000001U 1703 #define IOC_IOC10_PORTCFG_BASE 0x00000000U 1704 1705 //***************************************************************************** 1706 // 1707 // Register: IOC_O_IOC11 1708 // 1709 //***************************************************************************** 1710 // Field: [30] HYSTEN 1711 // 1712 // This field controls input hysteresis 1713 // ENUMs: 1714 // EN Input hysteresis enabled 1715 // DIS Input hysteresis disabled 1716 #define IOC_IOC11_HYSTEN 0x40000000U 1717 #define IOC_IOC11_HYSTEN_M 0x40000000U 1718 #define IOC_IOC11_HYSTEN_S 30U 1719 #define IOC_IOC11_HYSTEN_EN 0x40000000U 1720 #define IOC_IOC11_HYSTEN_DIS 0x00000000U 1721 1722 // Field: [29] INPEN 1723 // 1724 // This field controls the input capability of DIO 1725 // ENUMs: 1726 // EN Input enabled 1727 // DIS Input disabled 1728 #define IOC_IOC11_INPEN 0x20000000U 1729 #define IOC_IOC11_INPEN_M 0x20000000U 1730 #define IOC_IOC11_INPEN_S 29U 1731 #define IOC_IOC11_INPEN_EN 0x20000000U 1732 #define IOC_IOC11_INPEN_DIS 0x00000000U 1733 1734 // Field: [26:24] IOMODE 1735 // 1736 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 1737 // behavior. 1738 // ENUMs: 1739 // OPENS_INV Open Source, inverted IO 1740 // OPENS Open Source, normal IO 1741 // OPEND_INV Open Drain, inverted IO 1742 // OPEND Open Drain, normal IO 1743 // INVERTED Inverted IO 1744 // NORMAL Normal IO 1745 #define IOC_IOC11_IOMODE_W 3U 1746 #define IOC_IOC11_IOMODE_M 0x07000000U 1747 #define IOC_IOC11_IOMODE_S 24U 1748 #define IOC_IOC11_IOMODE_OPENS_INV 0x05000000U 1749 #define IOC_IOC11_IOMODE_OPENS 0x04000000U 1750 #define IOC_IOC11_IOMODE_OPEND_INV 0x03000000U 1751 #define IOC_IOC11_IOMODE_OPEND 0x02000000U 1752 #define IOC_IOC11_IOMODE_INVERTED 0x01000000U 1753 #define IOC_IOC11_IOMODE_NORMAL 0x00000000U 1754 1755 // Field: [21:20] WUCFGSD 1756 // 1757 // Wakeup configuration from shutdown 1758 // ENUMs: 1759 // WAKE_HIGH Wakeup triggered when pad level is high 1760 // WAKE_LOW Wakeup triggered when pad level is low 1761 // DIS_1 Wakeup disabled 1762 // DIS_0 Wakeup disabled 1763 #define IOC_IOC11_WUCFGSD_W 2U 1764 #define IOC_IOC11_WUCFGSD_M 0x00300000U 1765 #define IOC_IOC11_WUCFGSD_S 20U 1766 #define IOC_IOC11_WUCFGSD_WAKE_HIGH 0x00300000U 1767 #define IOC_IOC11_WUCFGSD_WAKE_LOW 0x00200000U 1768 #define IOC_IOC11_WUCFGSD_DIS_1 0x00100000U 1769 #define IOC_IOC11_WUCFGSD_DIS_0 0x00000000U 1770 1771 // Field: [18] WUENSB 1772 // 1773 // Wakeup enable from standby 1774 // ENUMs: 1775 // EN Wakeup enabled (effective only if EDGEDET is 1776 // enabled) 1777 // DIS Wakeup disabled 1778 #define IOC_IOC11_WUENSB 0x00040000U 1779 #define IOC_IOC11_WUENSB_M 0x00040000U 1780 #define IOC_IOC11_WUENSB_S 18U 1781 #define IOC_IOC11_WUENSB_EN 0x00040000U 1782 #define IOC_IOC11_WUENSB_DIS 0x00000000U 1783 1784 // Field: [17:16] EDGEDET 1785 // 1786 // Edge detect configuration 1787 // ENUMs: 1788 // EDGE_BOTH Positive and negative edge detection 1789 // EDGE_POS Positive edge detection 1790 // EDGE_NEG Negative edge detection 1791 // EDGE_DIS No edge detection 1792 #define IOC_IOC11_EDGEDET_W 2U 1793 #define IOC_IOC11_EDGEDET_M 0x00030000U 1794 #define IOC_IOC11_EDGEDET_S 16U 1795 #define IOC_IOC11_EDGEDET_EDGE_BOTH 0x00030000U 1796 #define IOC_IOC11_EDGEDET_EDGE_POS 0x00020000U 1797 #define IOC_IOC11_EDGEDET_EDGE_NEG 0x00010000U 1798 #define IOC_IOC11_EDGEDET_EDGE_DIS 0x00000000U 1799 1800 // Field: [14:13] PULLCTL 1801 // 1802 // Pull control. Setting this to value 0x3 disables pull. 1803 // ENUMs: 1804 // PULL_UP Pull up enabled 1805 // PULL_DOWN Pull down enabled 1806 // PULL_DIS No pull 1807 #define IOC_IOC11_PULLCTL_W 2U 1808 #define IOC_IOC11_PULLCTL_M 0x00006000U 1809 #define IOC_IOC11_PULLCTL_S 13U 1810 #define IOC_IOC11_PULLCTL_PULL_UP 0x00004000U 1811 #define IOC_IOC11_PULLCTL_PULL_DOWN 0x00002000U 1812 #define IOC_IOC11_PULLCTL_PULL_DIS 0x00000000U 1813 1814 // Field: [2:0] PORTCFG 1815 // 1816 // Selects usage of DIO11 1817 // ENUMs: 1818 // DTB Digital Test Bus function 1819 // ANA Analog function 1820 // PFUNC5 Digital peripheral function-5 1821 // PFUNC4 Digital peripheral function-4 1822 // PFUNC3 Digital peripheral function-3 1823 // PFUNC2 Digital peripheral function-2 1824 // PFUNC1 Digital peripheral function-1 1825 // BASE Base function 1826 #define IOC_IOC11_PORTCFG_W 3U 1827 #define IOC_IOC11_PORTCFG_M 0x00000007U 1828 #define IOC_IOC11_PORTCFG_S 0U 1829 #define IOC_IOC11_PORTCFG_DTB 0x00000007U 1830 #define IOC_IOC11_PORTCFG_ANA 0x00000006U 1831 #define IOC_IOC11_PORTCFG_PFUNC5 0x00000005U 1832 #define IOC_IOC11_PORTCFG_PFUNC4 0x00000004U 1833 #define IOC_IOC11_PORTCFG_PFUNC3 0x00000003U 1834 #define IOC_IOC11_PORTCFG_PFUNC2 0x00000002U 1835 #define IOC_IOC11_PORTCFG_PFUNC1 0x00000001U 1836 #define IOC_IOC11_PORTCFG_BASE 0x00000000U 1837 1838 //***************************************************************************** 1839 // 1840 // Register: IOC_O_IOC12 1841 // 1842 //***************************************************************************** 1843 // Field: [30] HYSTEN 1844 // 1845 // This field controls input hysteresis 1846 // ENUMs: 1847 // EN Input hysteresis enabled 1848 // DIS Input hysteresis disabled 1849 #define IOC_IOC12_HYSTEN 0x40000000U 1850 #define IOC_IOC12_HYSTEN_M 0x40000000U 1851 #define IOC_IOC12_HYSTEN_S 30U 1852 #define IOC_IOC12_HYSTEN_EN 0x40000000U 1853 #define IOC_IOC12_HYSTEN_DIS 0x00000000U 1854 1855 // Field: [29] INPEN 1856 // 1857 // This field controls the input capability of DIO 1858 // ENUMs: 1859 // EN Input enabled 1860 // DIS Input disabled 1861 #define IOC_IOC12_INPEN 0x20000000U 1862 #define IOC_IOC12_INPEN_M 0x20000000U 1863 #define IOC_IOC12_INPEN_S 29U 1864 #define IOC_IOC12_INPEN_EN 0x20000000U 1865 #define IOC_IOC12_INPEN_DIS 0x00000000U 1866 1867 // Field: [26:24] IOMODE 1868 // 1869 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 1870 // behavior. 1871 // ENUMs: 1872 // OPENS_INV Open Source, inverted IO 1873 // OPENS Open Source, normal IO 1874 // OPEND_INV Open Drain, inverted IO 1875 // OPEND Open Drain, normal IO 1876 // INVERTED Inverted IO 1877 // NORMAL Normal IO 1878 #define IOC_IOC12_IOMODE_W 3U 1879 #define IOC_IOC12_IOMODE_M 0x07000000U 1880 #define IOC_IOC12_IOMODE_S 24U 1881 #define IOC_IOC12_IOMODE_OPENS_INV 0x05000000U 1882 #define IOC_IOC12_IOMODE_OPENS 0x04000000U 1883 #define IOC_IOC12_IOMODE_OPEND_INV 0x03000000U 1884 #define IOC_IOC12_IOMODE_OPEND 0x02000000U 1885 #define IOC_IOC12_IOMODE_INVERTED 0x01000000U 1886 #define IOC_IOC12_IOMODE_NORMAL 0x00000000U 1887 1888 // Field: [21:20] WUCFGSD 1889 // 1890 // Wakeup configuration from shutdown 1891 // ENUMs: 1892 // WAKE_HIGH Wakeup triggered when pad level is high 1893 // WAKE_LOW Wakeup triggered when pad level is low 1894 // DIS_1 Wakeup disabled 1895 // DIS_0 Wakeup disabled 1896 #define IOC_IOC12_WUCFGSD_W 2U 1897 #define IOC_IOC12_WUCFGSD_M 0x00300000U 1898 #define IOC_IOC12_WUCFGSD_S 20U 1899 #define IOC_IOC12_WUCFGSD_WAKE_HIGH 0x00300000U 1900 #define IOC_IOC12_WUCFGSD_WAKE_LOW 0x00200000U 1901 #define IOC_IOC12_WUCFGSD_DIS_1 0x00100000U 1902 #define IOC_IOC12_WUCFGSD_DIS_0 0x00000000U 1903 1904 // Field: [18] WUENSB 1905 // 1906 // Wakeup enable from standby 1907 // ENUMs: 1908 // EN Wakeup enabled (effective only if EDGEDET is 1909 // enabled) 1910 // DIS Wakeup disabled 1911 #define IOC_IOC12_WUENSB 0x00040000U 1912 #define IOC_IOC12_WUENSB_M 0x00040000U 1913 #define IOC_IOC12_WUENSB_S 18U 1914 #define IOC_IOC12_WUENSB_EN 0x00040000U 1915 #define IOC_IOC12_WUENSB_DIS 0x00000000U 1916 1917 // Field: [17:16] EDGEDET 1918 // 1919 // Edge detect configuration 1920 // ENUMs: 1921 // EDGE_BOTH Positive and negative edge detection 1922 // EDGE_POS Positive edge detection 1923 // EDGE_NEG Negative edge detection 1924 // EDGE_DIS No edge detection 1925 #define IOC_IOC12_EDGEDET_W 2U 1926 #define IOC_IOC12_EDGEDET_M 0x00030000U 1927 #define IOC_IOC12_EDGEDET_S 16U 1928 #define IOC_IOC12_EDGEDET_EDGE_BOTH 0x00030000U 1929 #define IOC_IOC12_EDGEDET_EDGE_POS 0x00020000U 1930 #define IOC_IOC12_EDGEDET_EDGE_NEG 0x00010000U 1931 #define IOC_IOC12_EDGEDET_EDGE_DIS 0x00000000U 1932 1933 // Field: [14:13] PULLCTL 1934 // 1935 // Pull control. Setting this to value 0x3 disables pull. 1936 // ENUMs: 1937 // PULL_UP Pull up enabled 1938 // PULL_DOWN Pull down enabled 1939 // PULL_DIS No pull 1940 #define IOC_IOC12_PULLCTL_W 2U 1941 #define IOC_IOC12_PULLCTL_M 0x00006000U 1942 #define IOC_IOC12_PULLCTL_S 13U 1943 #define IOC_IOC12_PULLCTL_PULL_UP 0x00004000U 1944 #define IOC_IOC12_PULLCTL_PULL_DOWN 0x00002000U 1945 #define IOC_IOC12_PULLCTL_PULL_DIS 0x00000000U 1946 1947 // Field: [12] SLEWRED 1948 // 1949 // Slew rate configuration 1950 // ENUMs: 1951 // REDUCED Reduced slew rate 1952 // NORMAL Normal slew rate 1953 #define IOC_IOC12_SLEWRED 0x00001000U 1954 #define IOC_IOC12_SLEWRED_M 0x00001000U 1955 #define IOC_IOC12_SLEWRED_S 12U 1956 #define IOC_IOC12_SLEWRED_REDUCED 0x00001000U 1957 #define IOC_IOC12_SLEWRED_NORMAL 0x00000000U 1958 1959 // Field: [11:10] IOCURR 1960 // 1961 // Output current configuration. Writing value 0x3 defaults to 2mA current 1962 // setting. 1963 // ENUMs: 1964 // CUR_8MA 1965 // CUR_4MA 1966 // CUR_2MA 1967 #define IOC_IOC12_IOCURR_W 2U 1968 #define IOC_IOC12_IOCURR_M 0x00000C00U 1969 #define IOC_IOC12_IOCURR_S 10U 1970 #define IOC_IOC12_IOCURR_CUR_8MA 0x00000800U 1971 #define IOC_IOC12_IOCURR_CUR_4MA 0x00000400U 1972 #define IOC_IOC12_IOCURR_CUR_2MA 0x00000000U 1973 1974 // Field: [9:8] IOSTR 1975 // 1976 // Drive strength configuration 1977 // ENUMs: 1978 // MAX Maximum drive strength 1979 // MEDIUM Medium drive strength 1980 // MIN Minimum drive stregnth 1981 // AUTO Automatic drive strength adjustment 1982 #define IOC_IOC12_IOSTR_W 2U 1983 #define IOC_IOC12_IOSTR_M 0x00000300U 1984 #define IOC_IOC12_IOSTR_S 8U 1985 #define IOC_IOC12_IOSTR_MAX 0x00000300U 1986 #define IOC_IOC12_IOSTR_MEDIUM 0x00000200U 1987 #define IOC_IOC12_IOSTR_MIN 0x00000100U 1988 #define IOC_IOC12_IOSTR_AUTO 0x00000000U 1989 1990 // Field: [2:0] PORTCFG 1991 // 1992 // Selects usage of DIO12 1993 // ENUMs: 1994 // DTB Digital Test Bus function 1995 // ANA Analog function 1996 // PFUNC5 Digital peripheral function-5 1997 // PFUNC4 Digital peripheral function-4 1998 // PFUNC3 Digital peripheral function-3 1999 // PFUNC2 Digital peripheral function-2 2000 // PFUNC1 Digital peripheral function-1 2001 // BASE Base function 2002 #define IOC_IOC12_PORTCFG_W 3U 2003 #define IOC_IOC12_PORTCFG_M 0x00000007U 2004 #define IOC_IOC12_PORTCFG_S 0U 2005 #define IOC_IOC12_PORTCFG_DTB 0x00000007U 2006 #define IOC_IOC12_PORTCFG_ANA 0x00000006U 2007 #define IOC_IOC12_PORTCFG_PFUNC5 0x00000005U 2008 #define IOC_IOC12_PORTCFG_PFUNC4 0x00000004U 2009 #define IOC_IOC12_PORTCFG_PFUNC3 0x00000003U 2010 #define IOC_IOC12_PORTCFG_PFUNC2 0x00000002U 2011 #define IOC_IOC12_PORTCFG_PFUNC1 0x00000001U 2012 #define IOC_IOC12_PORTCFG_BASE 0x00000000U 2013 2014 //***************************************************************************** 2015 // 2016 // Register: IOC_O_IOC13 2017 // 2018 //***************************************************************************** 2019 // Field: [30] HYSTEN 2020 // 2021 // This field controls input hysteresis 2022 // ENUMs: 2023 // EN Input hysteresis enabled 2024 // DIS Input hysteresis disabled 2025 #define IOC_IOC13_HYSTEN 0x40000000U 2026 #define IOC_IOC13_HYSTEN_M 0x40000000U 2027 #define IOC_IOC13_HYSTEN_S 30U 2028 #define IOC_IOC13_HYSTEN_EN 0x40000000U 2029 #define IOC_IOC13_HYSTEN_DIS 0x00000000U 2030 2031 // Field: [29] INPEN 2032 // 2033 // This field controls the input capability of DIO 2034 // ENUMs: 2035 // EN Input enabled 2036 // DIS Input disabled 2037 #define IOC_IOC13_INPEN 0x20000000U 2038 #define IOC_IOC13_INPEN_M 0x20000000U 2039 #define IOC_IOC13_INPEN_S 29U 2040 #define IOC_IOC13_INPEN_EN 0x20000000U 2041 #define IOC_IOC13_INPEN_DIS 0x00000000U 2042 2043 // Field: [26:24] IOMODE 2044 // 2045 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 2046 // behavior. 2047 // ENUMs: 2048 // OPENS_INV Open Source, inverted IO 2049 // OPENS Open Source, normal IO 2050 // OPEND_INV Open Drain, inverted IO 2051 // OPEND Open Drain, normal IO 2052 // INVERTED Inverted IO 2053 // NORMAL Normal IO 2054 #define IOC_IOC13_IOMODE_W 3U 2055 #define IOC_IOC13_IOMODE_M 0x07000000U 2056 #define IOC_IOC13_IOMODE_S 24U 2057 #define IOC_IOC13_IOMODE_OPENS_INV 0x05000000U 2058 #define IOC_IOC13_IOMODE_OPENS 0x04000000U 2059 #define IOC_IOC13_IOMODE_OPEND_INV 0x03000000U 2060 #define IOC_IOC13_IOMODE_OPEND 0x02000000U 2061 #define IOC_IOC13_IOMODE_INVERTED 0x01000000U 2062 #define IOC_IOC13_IOMODE_NORMAL 0x00000000U 2063 2064 // Field: [21:20] WUCFGSD 2065 // 2066 // Wakeup configuration from shutdown 2067 // ENUMs: 2068 // WAKE_HIGH Wakeup triggered when pad level is high 2069 // WAKE_LOW Wakeup triggered when pad level is low 2070 // DIS_1 Wakeup disabled 2071 // DIS_0 Wakeup disabled 2072 #define IOC_IOC13_WUCFGSD_W 2U 2073 #define IOC_IOC13_WUCFGSD_M 0x00300000U 2074 #define IOC_IOC13_WUCFGSD_S 20U 2075 #define IOC_IOC13_WUCFGSD_WAKE_HIGH 0x00300000U 2076 #define IOC_IOC13_WUCFGSD_WAKE_LOW 0x00200000U 2077 #define IOC_IOC13_WUCFGSD_DIS_1 0x00100000U 2078 #define IOC_IOC13_WUCFGSD_DIS_0 0x00000000U 2079 2080 // Field: [18] WUENSB 2081 // 2082 // Wakeup enable from standby 2083 // ENUMs: 2084 // EN Wakeup enabled (effective only if EDGEDET is 2085 // enabled) 2086 // DIS Wakeup disabled 2087 #define IOC_IOC13_WUENSB 0x00040000U 2088 #define IOC_IOC13_WUENSB_M 0x00040000U 2089 #define IOC_IOC13_WUENSB_S 18U 2090 #define IOC_IOC13_WUENSB_EN 0x00040000U 2091 #define IOC_IOC13_WUENSB_DIS 0x00000000U 2092 2093 // Field: [17:16] EDGEDET 2094 // 2095 // Edge detect configuration 2096 // ENUMs: 2097 // EDGE_BOTH Positive and negative edge detection 2098 // EDGE_POS Positive edge detection 2099 // EDGE_NEG Negative edge detection 2100 // EDGE_DIS No edge detection 2101 #define IOC_IOC13_EDGEDET_W 2U 2102 #define IOC_IOC13_EDGEDET_M 0x00030000U 2103 #define IOC_IOC13_EDGEDET_S 16U 2104 #define IOC_IOC13_EDGEDET_EDGE_BOTH 0x00030000U 2105 #define IOC_IOC13_EDGEDET_EDGE_POS 0x00020000U 2106 #define IOC_IOC13_EDGEDET_EDGE_NEG 0x00010000U 2107 #define IOC_IOC13_EDGEDET_EDGE_DIS 0x00000000U 2108 2109 // Field: [14:13] PULLCTL 2110 // 2111 // Pull control. Setting this to value 0x3 disables pull. 2112 // ENUMs: 2113 // PULL_UP Pull up enabled 2114 // PULL_DOWN Pull down enabled 2115 // PULL_DIS No pull 2116 #define IOC_IOC13_PULLCTL_W 2U 2117 #define IOC_IOC13_PULLCTL_M 0x00006000U 2118 #define IOC_IOC13_PULLCTL_S 13U 2119 #define IOC_IOC13_PULLCTL_PULL_UP 0x00004000U 2120 #define IOC_IOC13_PULLCTL_PULL_DOWN 0x00002000U 2121 #define IOC_IOC13_PULLCTL_PULL_DIS 0x00000000U 2122 2123 // Field: [2:0] PORTCFG 2124 // 2125 // Selects usage of DIO13 2126 // ENUMs: 2127 // DTB Digital Test Bus function 2128 // ANA Analog function 2129 // PFUNC5 Digital peripheral function-5 2130 // PFUNC4 Digital peripheral function-4 2131 // PFUNC3 Digital peripheral function-3 2132 // PFUNC2 Digital peripheral function-2 2133 // PFUNC1 Digital peripheral function-1 2134 // BASE Base function 2135 #define IOC_IOC13_PORTCFG_W 3U 2136 #define IOC_IOC13_PORTCFG_M 0x00000007U 2137 #define IOC_IOC13_PORTCFG_S 0U 2138 #define IOC_IOC13_PORTCFG_DTB 0x00000007U 2139 #define IOC_IOC13_PORTCFG_ANA 0x00000006U 2140 #define IOC_IOC13_PORTCFG_PFUNC5 0x00000005U 2141 #define IOC_IOC13_PORTCFG_PFUNC4 0x00000004U 2142 #define IOC_IOC13_PORTCFG_PFUNC3 0x00000003U 2143 #define IOC_IOC13_PORTCFG_PFUNC2 0x00000002U 2144 #define IOC_IOC13_PORTCFG_PFUNC1 0x00000001U 2145 #define IOC_IOC13_PORTCFG_BASE 0x00000000U 2146 2147 //***************************************************************************** 2148 // 2149 // Register: IOC_O_IOC14 2150 // 2151 //***************************************************************************** 2152 // Field: [30] HYSTEN 2153 // 2154 // This field controls input hysteresis 2155 // ENUMs: 2156 // EN Input hysteresis enabled 2157 // DIS Input hysteresis disabled 2158 #define IOC_IOC14_HYSTEN 0x40000000U 2159 #define IOC_IOC14_HYSTEN_M 0x40000000U 2160 #define IOC_IOC14_HYSTEN_S 30U 2161 #define IOC_IOC14_HYSTEN_EN 0x40000000U 2162 #define IOC_IOC14_HYSTEN_DIS 0x00000000U 2163 2164 // Field: [29] INPEN 2165 // 2166 // This field controls the input capability of DIO 2167 // ENUMs: 2168 // EN Input enabled 2169 // DIS Input disabled 2170 #define IOC_IOC14_INPEN 0x20000000U 2171 #define IOC_IOC14_INPEN_M 0x20000000U 2172 #define IOC_IOC14_INPEN_S 29U 2173 #define IOC_IOC14_INPEN_EN 0x20000000U 2174 #define IOC_IOC14_INPEN_DIS 0x00000000U 2175 2176 // Field: [26:24] IOMODE 2177 // 2178 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 2179 // behavior. 2180 // ENUMs: 2181 // OPENS_INV Open Source, inverted IO 2182 // OPENS Open Source, normal IO 2183 // OPEND_INV Open Drain, inverted IO 2184 // OPEND Open Drain, normal IO 2185 // INVERTED Inverted IO 2186 // NORMAL Normal IO 2187 #define IOC_IOC14_IOMODE_W 3U 2188 #define IOC_IOC14_IOMODE_M 0x07000000U 2189 #define IOC_IOC14_IOMODE_S 24U 2190 #define IOC_IOC14_IOMODE_OPENS_INV 0x05000000U 2191 #define IOC_IOC14_IOMODE_OPENS 0x04000000U 2192 #define IOC_IOC14_IOMODE_OPEND_INV 0x03000000U 2193 #define IOC_IOC14_IOMODE_OPEND 0x02000000U 2194 #define IOC_IOC14_IOMODE_INVERTED 0x01000000U 2195 #define IOC_IOC14_IOMODE_NORMAL 0x00000000U 2196 2197 // Field: [21:20] WUCFGSD 2198 // 2199 // Wakeup configuration from shutdown 2200 // ENUMs: 2201 // WAKE_HIGH Wakeup triggered when pad level is high 2202 // WAKE_LOW Wakeup triggered when pad level is low 2203 // DIS_1 Wakeup disabled 2204 // DIS_0 Wakeup disabled 2205 #define IOC_IOC14_WUCFGSD_W 2U 2206 #define IOC_IOC14_WUCFGSD_M 0x00300000U 2207 #define IOC_IOC14_WUCFGSD_S 20U 2208 #define IOC_IOC14_WUCFGSD_WAKE_HIGH 0x00300000U 2209 #define IOC_IOC14_WUCFGSD_WAKE_LOW 0x00200000U 2210 #define IOC_IOC14_WUCFGSD_DIS_1 0x00100000U 2211 #define IOC_IOC14_WUCFGSD_DIS_0 0x00000000U 2212 2213 // Field: [18] WUENSB 2214 // 2215 // Wakeup enable from standby 2216 // ENUMs: 2217 // EN Wakeup enabled (effective only if EDGEDET is 2218 // enabled) 2219 // DIS Wakeup disabled 2220 #define IOC_IOC14_WUENSB 0x00040000U 2221 #define IOC_IOC14_WUENSB_M 0x00040000U 2222 #define IOC_IOC14_WUENSB_S 18U 2223 #define IOC_IOC14_WUENSB_EN 0x00040000U 2224 #define IOC_IOC14_WUENSB_DIS 0x00000000U 2225 2226 // Field: [17:16] EDGEDET 2227 // 2228 // Edge detect configuration 2229 // ENUMs: 2230 // EDGE_BOTH Positive and negative edge detection 2231 // EDGE_POS Positive edge detection 2232 // EDGE_NEG Negative edge detection 2233 // EDGE_DIS No edge detection 2234 #define IOC_IOC14_EDGEDET_W 2U 2235 #define IOC_IOC14_EDGEDET_M 0x00030000U 2236 #define IOC_IOC14_EDGEDET_S 16U 2237 #define IOC_IOC14_EDGEDET_EDGE_BOTH 0x00030000U 2238 #define IOC_IOC14_EDGEDET_EDGE_POS 0x00020000U 2239 #define IOC_IOC14_EDGEDET_EDGE_NEG 0x00010000U 2240 #define IOC_IOC14_EDGEDET_EDGE_DIS 0x00000000U 2241 2242 // Field: [14:13] PULLCTL 2243 // 2244 // Pull control. Setting this to value 0x3 disables pull. 2245 // ENUMs: 2246 // PULL_UP Pull up enabled 2247 // PULL_DOWN Pull down enabled 2248 // PULL_DIS No pull 2249 #define IOC_IOC14_PULLCTL_W 2U 2250 #define IOC_IOC14_PULLCTL_M 0x00006000U 2251 #define IOC_IOC14_PULLCTL_S 13U 2252 #define IOC_IOC14_PULLCTL_PULL_UP 0x00004000U 2253 #define IOC_IOC14_PULLCTL_PULL_DOWN 0x00002000U 2254 #define IOC_IOC14_PULLCTL_PULL_DIS 0x00000000U 2255 2256 // Field: [2:0] PORTCFG 2257 // 2258 // Selects usage of DIO14 2259 // ENUMs: 2260 // DTB Digital Test Bus function 2261 // ANA Analog function 2262 // PFUNC5 Digital peripheral function-5 2263 // PFUNC4 Digital peripheral function-4 2264 // PFUNC3 Digital peripheral function-3 2265 // PFUNC2 Digital peripheral function-2 2266 // PFUNC1 Digital peripheral function-1 2267 // BASE Base function 2268 #define IOC_IOC14_PORTCFG_W 3U 2269 #define IOC_IOC14_PORTCFG_M 0x00000007U 2270 #define IOC_IOC14_PORTCFG_S 0U 2271 #define IOC_IOC14_PORTCFG_DTB 0x00000007U 2272 #define IOC_IOC14_PORTCFG_ANA 0x00000006U 2273 #define IOC_IOC14_PORTCFG_PFUNC5 0x00000005U 2274 #define IOC_IOC14_PORTCFG_PFUNC4 0x00000004U 2275 #define IOC_IOC14_PORTCFG_PFUNC3 0x00000003U 2276 #define IOC_IOC14_PORTCFG_PFUNC2 0x00000002U 2277 #define IOC_IOC14_PORTCFG_PFUNC1 0x00000001U 2278 #define IOC_IOC14_PORTCFG_BASE 0x00000000U 2279 2280 //***************************************************************************** 2281 // 2282 // Register: IOC_O_IOC15 2283 // 2284 //***************************************************************************** 2285 // Field: [30] HYSTEN 2286 // 2287 // This field controls input hysteresis 2288 // ENUMs: 2289 // EN Input hysteresis enabled 2290 // DIS Input hysteresis disabled 2291 #define IOC_IOC15_HYSTEN 0x40000000U 2292 #define IOC_IOC15_HYSTEN_M 0x40000000U 2293 #define IOC_IOC15_HYSTEN_S 30U 2294 #define IOC_IOC15_HYSTEN_EN 0x40000000U 2295 #define IOC_IOC15_HYSTEN_DIS 0x00000000U 2296 2297 // Field: [29] INPEN 2298 // 2299 // This field controls the input capability of DIO 2300 // ENUMs: 2301 // EN Input enabled 2302 // DIS Input disabled 2303 #define IOC_IOC15_INPEN 0x20000000U 2304 #define IOC_IOC15_INPEN_M 0x20000000U 2305 #define IOC_IOC15_INPEN_S 29U 2306 #define IOC_IOC15_INPEN_EN 0x20000000U 2307 #define IOC_IOC15_INPEN_DIS 0x00000000U 2308 2309 // Field: [26:24] IOMODE 2310 // 2311 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 2312 // behavior. 2313 // ENUMs: 2314 // OPENS_INV Open Source, inverted IO 2315 // OPENS Open Source, normal IO 2316 // OPEND_INV Open Drain, inverted IO 2317 // OPEND Open Drain, normal IO 2318 // INVERTED Inverted IO 2319 // NORMAL Normal IO 2320 #define IOC_IOC15_IOMODE_W 3U 2321 #define IOC_IOC15_IOMODE_M 0x07000000U 2322 #define IOC_IOC15_IOMODE_S 24U 2323 #define IOC_IOC15_IOMODE_OPENS_INV 0x05000000U 2324 #define IOC_IOC15_IOMODE_OPENS 0x04000000U 2325 #define IOC_IOC15_IOMODE_OPEND_INV 0x03000000U 2326 #define IOC_IOC15_IOMODE_OPEND 0x02000000U 2327 #define IOC_IOC15_IOMODE_INVERTED 0x01000000U 2328 #define IOC_IOC15_IOMODE_NORMAL 0x00000000U 2329 2330 // Field: [21:20] WUCFGSD 2331 // 2332 // Wakeup configuration from shutdown 2333 // ENUMs: 2334 // WAKE_HIGH Wakeup triggered when pad level is high 2335 // WAKE_LOW Wakeup triggered when pad level is low 2336 // DIS_1 Wakeup disabled 2337 // DIS_0 Wakeup disabled 2338 #define IOC_IOC15_WUCFGSD_W 2U 2339 #define IOC_IOC15_WUCFGSD_M 0x00300000U 2340 #define IOC_IOC15_WUCFGSD_S 20U 2341 #define IOC_IOC15_WUCFGSD_WAKE_HIGH 0x00300000U 2342 #define IOC_IOC15_WUCFGSD_WAKE_LOW 0x00200000U 2343 #define IOC_IOC15_WUCFGSD_DIS_1 0x00100000U 2344 #define IOC_IOC15_WUCFGSD_DIS_0 0x00000000U 2345 2346 // Field: [18] WUENSB 2347 // 2348 // Wakeup enable from standby 2349 // ENUMs: 2350 // EN Wakeup enabled (effective only if EDGEDET is 2351 // enabled) 2352 // DIS Wakeup disabled 2353 #define IOC_IOC15_WUENSB 0x00040000U 2354 #define IOC_IOC15_WUENSB_M 0x00040000U 2355 #define IOC_IOC15_WUENSB_S 18U 2356 #define IOC_IOC15_WUENSB_EN 0x00040000U 2357 #define IOC_IOC15_WUENSB_DIS 0x00000000U 2358 2359 // Field: [17:16] EDGEDET 2360 // 2361 // Edge detect configuration 2362 // ENUMs: 2363 // EDGE_BOTH Positive and negative edge detection 2364 // EDGE_POS Positive edge detection 2365 // EDGE_NEG Negative edge detection 2366 // EDGE_DIS No edge detection 2367 #define IOC_IOC15_EDGEDET_W 2U 2368 #define IOC_IOC15_EDGEDET_M 0x00030000U 2369 #define IOC_IOC15_EDGEDET_S 16U 2370 #define IOC_IOC15_EDGEDET_EDGE_BOTH 0x00030000U 2371 #define IOC_IOC15_EDGEDET_EDGE_POS 0x00020000U 2372 #define IOC_IOC15_EDGEDET_EDGE_NEG 0x00010000U 2373 #define IOC_IOC15_EDGEDET_EDGE_DIS 0x00000000U 2374 2375 // Field: [14:13] PULLCTL 2376 // 2377 // Pull control. Setting this to value 0x3 disables pull. 2378 // ENUMs: 2379 // PULL_UP Pull up enabled 2380 // PULL_DOWN Pull down enabled 2381 // PULL_DIS No pull 2382 #define IOC_IOC15_PULLCTL_W 2U 2383 #define IOC_IOC15_PULLCTL_M 0x00006000U 2384 #define IOC_IOC15_PULLCTL_S 13U 2385 #define IOC_IOC15_PULLCTL_PULL_UP 0x00004000U 2386 #define IOC_IOC15_PULLCTL_PULL_DOWN 0x00002000U 2387 #define IOC_IOC15_PULLCTL_PULL_DIS 0x00000000U 2388 2389 // Field: [2:0] PORTCFG 2390 // 2391 // Selects usage of DIO15 2392 // ENUMs: 2393 // DTB Digital Test Bus function 2394 // ANA Analog function 2395 // PFUNC5 Digital peripheral function-5 2396 // PFUNC4 Digital peripheral function-4 2397 // PFUNC3 Digital peripheral function-3 2398 // PFUNC2 Digital peripheral function-2 2399 // PFUNC1 Digital peripheral function-1 2400 // BASE Base function 2401 #define IOC_IOC15_PORTCFG_W 3U 2402 #define IOC_IOC15_PORTCFG_M 0x00000007U 2403 #define IOC_IOC15_PORTCFG_S 0U 2404 #define IOC_IOC15_PORTCFG_DTB 0x00000007U 2405 #define IOC_IOC15_PORTCFG_ANA 0x00000006U 2406 #define IOC_IOC15_PORTCFG_PFUNC5 0x00000005U 2407 #define IOC_IOC15_PORTCFG_PFUNC4 0x00000004U 2408 #define IOC_IOC15_PORTCFG_PFUNC3 0x00000003U 2409 #define IOC_IOC15_PORTCFG_PFUNC2 0x00000002U 2410 #define IOC_IOC15_PORTCFG_PFUNC1 0x00000001U 2411 #define IOC_IOC15_PORTCFG_BASE 0x00000000U 2412 2413 //***************************************************************************** 2414 // 2415 // Register: IOC_O_IOC16 2416 // 2417 //***************************************************************************** 2418 // Field: [30] HYSTEN 2419 // 2420 // This field controls input hysteresis 2421 // ENUMs: 2422 // EN Input hysteresis enabled 2423 // DIS Input hysteresis disabled 2424 #define IOC_IOC16_HYSTEN 0x40000000U 2425 #define IOC_IOC16_HYSTEN_M 0x40000000U 2426 #define IOC_IOC16_HYSTEN_S 30U 2427 #define IOC_IOC16_HYSTEN_EN 0x40000000U 2428 #define IOC_IOC16_HYSTEN_DIS 0x00000000U 2429 2430 // Field: [29] INPEN 2431 // 2432 // This field controls the input capability of DIO 2433 // ENUMs: 2434 // EN Input enabled 2435 // DIS Input disabled 2436 #define IOC_IOC16_INPEN 0x20000000U 2437 #define IOC_IOC16_INPEN_M 0x20000000U 2438 #define IOC_IOC16_INPEN_S 29U 2439 #define IOC_IOC16_INPEN_EN 0x20000000U 2440 #define IOC_IOC16_INPEN_DIS 0x00000000U 2441 2442 // Field: [26:24] IOMODE 2443 // 2444 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 2445 // behavior. 2446 // ENUMs: 2447 // OPENS_INV Open Source, inverted IO 2448 // OPENS Open Source, normal IO 2449 // OPEND_INV Open Drain, inverted IO 2450 // OPEND Open Drain, normal IO 2451 // INVERTED Inverted IO 2452 // NORMAL Normal IO 2453 #define IOC_IOC16_IOMODE_W 3U 2454 #define IOC_IOC16_IOMODE_M 0x07000000U 2455 #define IOC_IOC16_IOMODE_S 24U 2456 #define IOC_IOC16_IOMODE_OPENS_INV 0x05000000U 2457 #define IOC_IOC16_IOMODE_OPENS 0x04000000U 2458 #define IOC_IOC16_IOMODE_OPEND_INV 0x03000000U 2459 #define IOC_IOC16_IOMODE_OPEND 0x02000000U 2460 #define IOC_IOC16_IOMODE_INVERTED 0x01000000U 2461 #define IOC_IOC16_IOMODE_NORMAL 0x00000000U 2462 2463 // Field: [21:20] WUCFGSD 2464 // 2465 // Wakeup configuration from shutdown 2466 // ENUMs: 2467 // WAKE_HIGH Wakeup triggered when pad level is high 2468 // WAKE_LOW Wakeup triggered when pad level is low 2469 // DIS_1 Wakeup disabled 2470 // DIS_0 Wakeup disabled 2471 #define IOC_IOC16_WUCFGSD_W 2U 2472 #define IOC_IOC16_WUCFGSD_M 0x00300000U 2473 #define IOC_IOC16_WUCFGSD_S 20U 2474 #define IOC_IOC16_WUCFGSD_WAKE_HIGH 0x00300000U 2475 #define IOC_IOC16_WUCFGSD_WAKE_LOW 0x00200000U 2476 #define IOC_IOC16_WUCFGSD_DIS_1 0x00100000U 2477 #define IOC_IOC16_WUCFGSD_DIS_0 0x00000000U 2478 2479 // Field: [18] WUENSB 2480 // 2481 // Wakeup enable from standby 2482 // ENUMs: 2483 // EN Wakeup enabled (effective only if EDGEDET is 2484 // enabled) 2485 // DIS Wakeup disabled 2486 #define IOC_IOC16_WUENSB 0x00040000U 2487 #define IOC_IOC16_WUENSB_M 0x00040000U 2488 #define IOC_IOC16_WUENSB_S 18U 2489 #define IOC_IOC16_WUENSB_EN 0x00040000U 2490 #define IOC_IOC16_WUENSB_DIS 0x00000000U 2491 2492 // Field: [17:16] EDGEDET 2493 // 2494 // Edge detect configuration 2495 // ENUMs: 2496 // EDGE_BOTH Positive and negative edge detection 2497 // EDGE_POS Positive edge detection 2498 // EDGE_NEG Negative edge detection 2499 // EDGE_DIS No edge detection 2500 #define IOC_IOC16_EDGEDET_W 2U 2501 #define IOC_IOC16_EDGEDET_M 0x00030000U 2502 #define IOC_IOC16_EDGEDET_S 16U 2503 #define IOC_IOC16_EDGEDET_EDGE_BOTH 0x00030000U 2504 #define IOC_IOC16_EDGEDET_EDGE_POS 0x00020000U 2505 #define IOC_IOC16_EDGEDET_EDGE_NEG 0x00010000U 2506 #define IOC_IOC16_EDGEDET_EDGE_DIS 0x00000000U 2507 2508 // Field: [14:13] PULLCTL 2509 // 2510 // Pull control. Setting this to value 0x3 disables pull. 2511 // ENUMs: 2512 // PULL_UP Pull up enabled 2513 // PULL_DOWN Pull down enabled 2514 // PULL_DIS No pull 2515 #define IOC_IOC16_PULLCTL_W 2U 2516 #define IOC_IOC16_PULLCTL_M 0x00006000U 2517 #define IOC_IOC16_PULLCTL_S 13U 2518 #define IOC_IOC16_PULLCTL_PULL_UP 0x00004000U 2519 #define IOC_IOC16_PULLCTL_PULL_DOWN 0x00002000U 2520 #define IOC_IOC16_PULLCTL_PULL_DIS 0x00000000U 2521 2522 // Field: [12] SLEWRED 2523 // 2524 // Slew rate configuration 2525 // ENUMs: 2526 // REDUCED Reduced slew rate 2527 // NORMAL Normal slew rate 2528 #define IOC_IOC16_SLEWRED 0x00001000U 2529 #define IOC_IOC16_SLEWRED_M 0x00001000U 2530 #define IOC_IOC16_SLEWRED_S 12U 2531 #define IOC_IOC16_SLEWRED_REDUCED 0x00001000U 2532 #define IOC_IOC16_SLEWRED_NORMAL 0x00000000U 2533 2534 // Field: [11:10] IOCURR 2535 // 2536 // Output current configuration. Writing value 0x3 defaults to 2mA current 2537 // setting. 2538 // ENUMs: 2539 // CUR_8MA 2540 // CUR_4MA 2541 // CUR_2MA 2542 #define IOC_IOC16_IOCURR_W 2U 2543 #define IOC_IOC16_IOCURR_M 0x00000C00U 2544 #define IOC_IOC16_IOCURR_S 10U 2545 #define IOC_IOC16_IOCURR_CUR_8MA 0x00000800U 2546 #define IOC_IOC16_IOCURR_CUR_4MA 0x00000400U 2547 #define IOC_IOC16_IOCURR_CUR_2MA 0x00000000U 2548 2549 // Field: [9:8] IOSTR 2550 // 2551 // Drive strength configuration 2552 // ENUMs: 2553 // MAX Maximum drive strength 2554 // MEDIUM Medium drive strength 2555 // MIN Minimum drive stregnth 2556 // AUTO Automatic drive strength adjustment 2557 #define IOC_IOC16_IOSTR_W 2U 2558 #define IOC_IOC16_IOSTR_M 0x00000300U 2559 #define IOC_IOC16_IOSTR_S 8U 2560 #define IOC_IOC16_IOSTR_MAX 0x00000300U 2561 #define IOC_IOC16_IOSTR_MEDIUM 0x00000200U 2562 #define IOC_IOC16_IOSTR_MIN 0x00000100U 2563 #define IOC_IOC16_IOSTR_AUTO 0x00000000U 2564 2565 // Field: [2:0] PORTCFG 2566 // 2567 // Selects usage of DIO16 2568 // ENUMs: 2569 // DTB Digital Test Bus function 2570 // ANA Analog function 2571 // PFUNC5 Digital peripheral function-5 2572 // PFUNC4 Digital peripheral function-4 2573 // PFUNC3 Digital peripheral function-3 2574 // PFUNC2 Digital peripheral function-2 2575 // PFUNC1 Digital peripheral function-1 2576 // BASE Base function 2577 #define IOC_IOC16_PORTCFG_W 3U 2578 #define IOC_IOC16_PORTCFG_M 0x00000007U 2579 #define IOC_IOC16_PORTCFG_S 0U 2580 #define IOC_IOC16_PORTCFG_DTB 0x00000007U 2581 #define IOC_IOC16_PORTCFG_ANA 0x00000006U 2582 #define IOC_IOC16_PORTCFG_PFUNC5 0x00000005U 2583 #define IOC_IOC16_PORTCFG_PFUNC4 0x00000004U 2584 #define IOC_IOC16_PORTCFG_PFUNC3 0x00000003U 2585 #define IOC_IOC16_PORTCFG_PFUNC2 0x00000002U 2586 #define IOC_IOC16_PORTCFG_PFUNC1 0x00000001U 2587 #define IOC_IOC16_PORTCFG_BASE 0x00000000U 2588 2589 //***************************************************************************** 2590 // 2591 // Register: IOC_O_IOC17 2592 // 2593 //***************************************************************************** 2594 // Field: [30] HYSTEN 2595 // 2596 // This field controls input hysteresis 2597 // ENUMs: 2598 // EN Input hysteresis enabled 2599 // DIS Input hysteresis disabled 2600 #define IOC_IOC17_HYSTEN 0x40000000U 2601 #define IOC_IOC17_HYSTEN_M 0x40000000U 2602 #define IOC_IOC17_HYSTEN_S 30U 2603 #define IOC_IOC17_HYSTEN_EN 0x40000000U 2604 #define IOC_IOC17_HYSTEN_DIS 0x00000000U 2605 2606 // Field: [29] INPEN 2607 // 2608 // This field controls the input capability of DIO 2609 // ENUMs: 2610 // EN Input enabled 2611 // DIS Input disabled 2612 #define IOC_IOC17_INPEN 0x20000000U 2613 #define IOC_IOC17_INPEN_M 0x20000000U 2614 #define IOC_IOC17_INPEN_S 29U 2615 #define IOC_IOC17_INPEN_EN 0x20000000U 2616 #define IOC_IOC17_INPEN_DIS 0x00000000U 2617 2618 // Field: [26:24] IOMODE 2619 // 2620 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 2621 // behavior. 2622 // ENUMs: 2623 // OPENS_INV Open Source, inverted IO 2624 // OPENS Open Source, normal IO 2625 // OPEND_INV Open Drain, inverted IO 2626 // OPEND Open Drain, normal IO 2627 // INVERTED Inverted IO 2628 // NORMAL Normal IO 2629 #define IOC_IOC17_IOMODE_W 3U 2630 #define IOC_IOC17_IOMODE_M 0x07000000U 2631 #define IOC_IOC17_IOMODE_S 24U 2632 #define IOC_IOC17_IOMODE_OPENS_INV 0x05000000U 2633 #define IOC_IOC17_IOMODE_OPENS 0x04000000U 2634 #define IOC_IOC17_IOMODE_OPEND_INV 0x03000000U 2635 #define IOC_IOC17_IOMODE_OPEND 0x02000000U 2636 #define IOC_IOC17_IOMODE_INVERTED 0x01000000U 2637 #define IOC_IOC17_IOMODE_NORMAL 0x00000000U 2638 2639 // Field: [21:20] WUCFGSD 2640 // 2641 // Wakeup configuration from shutdown 2642 // ENUMs: 2643 // WAKE_HIGH Wakeup triggered when pad level is high 2644 // WAKE_LOW Wakeup triggered when pad level is low 2645 // DIS_1 Wakeup disabled 2646 // DIS_0 Wakeup disabled 2647 #define IOC_IOC17_WUCFGSD_W 2U 2648 #define IOC_IOC17_WUCFGSD_M 0x00300000U 2649 #define IOC_IOC17_WUCFGSD_S 20U 2650 #define IOC_IOC17_WUCFGSD_WAKE_HIGH 0x00300000U 2651 #define IOC_IOC17_WUCFGSD_WAKE_LOW 0x00200000U 2652 #define IOC_IOC17_WUCFGSD_DIS_1 0x00100000U 2653 #define IOC_IOC17_WUCFGSD_DIS_0 0x00000000U 2654 2655 // Field: [18] WUENSB 2656 // 2657 // Wakeup enable from standby 2658 // ENUMs: 2659 // EN Wakeup enabled (effective only if EDGEDET is 2660 // enabled) 2661 // DIS Wakeup disabled 2662 #define IOC_IOC17_WUENSB 0x00040000U 2663 #define IOC_IOC17_WUENSB_M 0x00040000U 2664 #define IOC_IOC17_WUENSB_S 18U 2665 #define IOC_IOC17_WUENSB_EN 0x00040000U 2666 #define IOC_IOC17_WUENSB_DIS 0x00000000U 2667 2668 // Field: [17:16] EDGEDET 2669 // 2670 // Edge detect configuration 2671 // ENUMs: 2672 // EDGE_BOTH Positive and negative edge detection 2673 // EDGE_POS Positive edge detection 2674 // EDGE_NEG Negative edge detection 2675 // EDGE_DIS No edge detection 2676 #define IOC_IOC17_EDGEDET_W 2U 2677 #define IOC_IOC17_EDGEDET_M 0x00030000U 2678 #define IOC_IOC17_EDGEDET_S 16U 2679 #define IOC_IOC17_EDGEDET_EDGE_BOTH 0x00030000U 2680 #define IOC_IOC17_EDGEDET_EDGE_POS 0x00020000U 2681 #define IOC_IOC17_EDGEDET_EDGE_NEG 0x00010000U 2682 #define IOC_IOC17_EDGEDET_EDGE_DIS 0x00000000U 2683 2684 // Field: [14:13] PULLCTL 2685 // 2686 // Pull control. Setting this to value 0x3 disables pull. 2687 // ENUMs: 2688 // PULL_UP Pull up enabled 2689 // PULL_DOWN Pull down enabled 2690 // PULL_DIS No pull 2691 #define IOC_IOC17_PULLCTL_W 2U 2692 #define IOC_IOC17_PULLCTL_M 0x00006000U 2693 #define IOC_IOC17_PULLCTL_S 13U 2694 #define IOC_IOC17_PULLCTL_PULL_UP 0x00004000U 2695 #define IOC_IOC17_PULLCTL_PULL_DOWN 0x00002000U 2696 #define IOC_IOC17_PULLCTL_PULL_DIS 0x00000000U 2697 2698 // Field: [12] SLEWRED 2699 // 2700 // Slew rate configuration 2701 // ENUMs: 2702 // REDUCED Reduced slew rate 2703 // NORMAL Normal slew rate 2704 #define IOC_IOC17_SLEWRED 0x00001000U 2705 #define IOC_IOC17_SLEWRED_M 0x00001000U 2706 #define IOC_IOC17_SLEWRED_S 12U 2707 #define IOC_IOC17_SLEWRED_REDUCED 0x00001000U 2708 #define IOC_IOC17_SLEWRED_NORMAL 0x00000000U 2709 2710 // Field: [11:10] IOCURR 2711 // 2712 // Output current configuration. Writing value 0x3 defaults to 2mA current 2713 // setting. 2714 // ENUMs: 2715 // CUR_8MA 2716 // CUR_4MA 2717 // CUR_2MA 2718 #define IOC_IOC17_IOCURR_W 2U 2719 #define IOC_IOC17_IOCURR_M 0x00000C00U 2720 #define IOC_IOC17_IOCURR_S 10U 2721 #define IOC_IOC17_IOCURR_CUR_8MA 0x00000800U 2722 #define IOC_IOC17_IOCURR_CUR_4MA 0x00000400U 2723 #define IOC_IOC17_IOCURR_CUR_2MA 0x00000000U 2724 2725 // Field: [9:8] IOSTR 2726 // 2727 // Drive strength configuration 2728 // ENUMs: 2729 // MAX Maximum drive strength 2730 // MEDIUM Medium drive strength 2731 // MIN Minimum drive stregnth 2732 // AUTO Automatic drive strength adjustment 2733 #define IOC_IOC17_IOSTR_W 2U 2734 #define IOC_IOC17_IOSTR_M 0x00000300U 2735 #define IOC_IOC17_IOSTR_S 8U 2736 #define IOC_IOC17_IOSTR_MAX 0x00000300U 2737 #define IOC_IOC17_IOSTR_MEDIUM 0x00000200U 2738 #define IOC_IOC17_IOSTR_MIN 0x00000100U 2739 #define IOC_IOC17_IOSTR_AUTO 0x00000000U 2740 2741 // Field: [2:0] PORTCFG 2742 // 2743 // Selects usage of DIO17 2744 // ENUMs: 2745 // DTB Digital Test Bus function 2746 // ANA Analog function 2747 // PFUNC5 Digital peripheral function-5 2748 // PFUNC4 Digital peripheral function-4 2749 // PFUNC3 Digital peripheral function-3 2750 // PFUNC2 Digital peripheral function-2 2751 // PFUNC1 Digital peripheral function-1 2752 // BASE Base function 2753 #define IOC_IOC17_PORTCFG_W 3U 2754 #define IOC_IOC17_PORTCFG_M 0x00000007U 2755 #define IOC_IOC17_PORTCFG_S 0U 2756 #define IOC_IOC17_PORTCFG_DTB 0x00000007U 2757 #define IOC_IOC17_PORTCFG_ANA 0x00000006U 2758 #define IOC_IOC17_PORTCFG_PFUNC5 0x00000005U 2759 #define IOC_IOC17_PORTCFG_PFUNC4 0x00000004U 2760 #define IOC_IOC17_PORTCFG_PFUNC3 0x00000003U 2761 #define IOC_IOC17_PORTCFG_PFUNC2 0x00000002U 2762 #define IOC_IOC17_PORTCFG_PFUNC1 0x00000001U 2763 #define IOC_IOC17_PORTCFG_BASE 0x00000000U 2764 2765 //***************************************************************************** 2766 // 2767 // Register: IOC_O_IOC18 2768 // 2769 //***************************************************************************** 2770 // Field: [30] HYSTEN 2771 // 2772 // This field controls input hysteresis 2773 // ENUMs: 2774 // EN Input hysteresis enabled 2775 // DIS Input hysteresis disabled 2776 #define IOC_IOC18_HYSTEN 0x40000000U 2777 #define IOC_IOC18_HYSTEN_M 0x40000000U 2778 #define IOC_IOC18_HYSTEN_S 30U 2779 #define IOC_IOC18_HYSTEN_EN 0x40000000U 2780 #define IOC_IOC18_HYSTEN_DIS 0x00000000U 2781 2782 // Field: [29] INPEN 2783 // 2784 // This field controls the input capability of DIO 2785 // ENUMs: 2786 // EN Input enabled 2787 // DIS Input disabled 2788 #define IOC_IOC18_INPEN 0x20000000U 2789 #define IOC_IOC18_INPEN_M 0x20000000U 2790 #define IOC_IOC18_INPEN_S 29U 2791 #define IOC_IOC18_INPEN_EN 0x20000000U 2792 #define IOC_IOC18_INPEN_DIS 0x00000000U 2793 2794 // Field: [26:24] IOMODE 2795 // 2796 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 2797 // behavior. 2798 // ENUMs: 2799 // OPENS_INV Open Source, inverted IO 2800 // OPENS Open Source, normal IO 2801 // OPEND_INV Open Drain, inverted IO 2802 // OPEND Open Drain, normal IO 2803 // INVERTED Inverted IO 2804 // NORMAL Normal IO 2805 #define IOC_IOC18_IOMODE_W 3U 2806 #define IOC_IOC18_IOMODE_M 0x07000000U 2807 #define IOC_IOC18_IOMODE_S 24U 2808 #define IOC_IOC18_IOMODE_OPENS_INV 0x05000000U 2809 #define IOC_IOC18_IOMODE_OPENS 0x04000000U 2810 #define IOC_IOC18_IOMODE_OPEND_INV 0x03000000U 2811 #define IOC_IOC18_IOMODE_OPEND 0x02000000U 2812 #define IOC_IOC18_IOMODE_INVERTED 0x01000000U 2813 #define IOC_IOC18_IOMODE_NORMAL 0x00000000U 2814 2815 // Field: [21:20] WUCFGSD 2816 // 2817 // Wakeup configuration from shutdown 2818 // ENUMs: 2819 // WAKE_HIGH Wakeup triggered when pad level is high 2820 // WAKE_LOW Wakeup triggered when pad level is low 2821 // DIS_1 Wakeup disabled 2822 // DIS_0 Wakeup disabled 2823 #define IOC_IOC18_WUCFGSD_W 2U 2824 #define IOC_IOC18_WUCFGSD_M 0x00300000U 2825 #define IOC_IOC18_WUCFGSD_S 20U 2826 #define IOC_IOC18_WUCFGSD_WAKE_HIGH 0x00300000U 2827 #define IOC_IOC18_WUCFGSD_WAKE_LOW 0x00200000U 2828 #define IOC_IOC18_WUCFGSD_DIS_1 0x00100000U 2829 #define IOC_IOC18_WUCFGSD_DIS_0 0x00000000U 2830 2831 // Field: [18] WUENSB 2832 // 2833 // Wakeup enable from standby 2834 // ENUMs: 2835 // EN Wakeup enabled (effective only if EDGEDET is 2836 // enabled) 2837 // DIS Wakeup disabled 2838 #define IOC_IOC18_WUENSB 0x00040000U 2839 #define IOC_IOC18_WUENSB_M 0x00040000U 2840 #define IOC_IOC18_WUENSB_S 18U 2841 #define IOC_IOC18_WUENSB_EN 0x00040000U 2842 #define IOC_IOC18_WUENSB_DIS 0x00000000U 2843 2844 // Field: [17:16] EDGEDET 2845 // 2846 // Edge detect configuration 2847 // ENUMs: 2848 // EDGE_BOTH Positive and negative edge detection 2849 // EDGE_POS Positive edge detection 2850 // EDGE_NEG Negative edge detection 2851 // EDGE_DIS No edge detection 2852 #define IOC_IOC18_EDGEDET_W 2U 2853 #define IOC_IOC18_EDGEDET_M 0x00030000U 2854 #define IOC_IOC18_EDGEDET_S 16U 2855 #define IOC_IOC18_EDGEDET_EDGE_BOTH 0x00030000U 2856 #define IOC_IOC18_EDGEDET_EDGE_POS 0x00020000U 2857 #define IOC_IOC18_EDGEDET_EDGE_NEG 0x00010000U 2858 #define IOC_IOC18_EDGEDET_EDGE_DIS 0x00000000U 2859 2860 // Field: [14:13] PULLCTL 2861 // 2862 // Pull control. Setting this to value 0x3 disables pull. 2863 // ENUMs: 2864 // PULL_UP Pull up enabled 2865 // PULL_DOWN Pull down enabled 2866 // PULL_DIS No pull 2867 #define IOC_IOC18_PULLCTL_W 2U 2868 #define IOC_IOC18_PULLCTL_M 0x00006000U 2869 #define IOC_IOC18_PULLCTL_S 13U 2870 #define IOC_IOC18_PULLCTL_PULL_UP 0x00004000U 2871 #define IOC_IOC18_PULLCTL_PULL_DOWN 0x00002000U 2872 #define IOC_IOC18_PULLCTL_PULL_DIS 0x00000000U 2873 2874 // Field: [12] SLEWRED 2875 // 2876 // Slew rate configuration 2877 // ENUMs: 2878 // REDUCED Reduced slew rate 2879 // NORMAL Normal slew rate 2880 #define IOC_IOC18_SLEWRED 0x00001000U 2881 #define IOC_IOC18_SLEWRED_M 0x00001000U 2882 #define IOC_IOC18_SLEWRED_S 12U 2883 #define IOC_IOC18_SLEWRED_REDUCED 0x00001000U 2884 #define IOC_IOC18_SLEWRED_NORMAL 0x00000000U 2885 2886 // Field: [11:10] IOCURR 2887 // 2888 // Output current configuration. Writing value 0x3 defaults to 2mA current 2889 // setting. 2890 // ENUMs: 2891 // CUR_8MA 2892 // CUR_4MA 2893 // CUR_2MA 2894 #define IOC_IOC18_IOCURR_W 2U 2895 #define IOC_IOC18_IOCURR_M 0x00000C00U 2896 #define IOC_IOC18_IOCURR_S 10U 2897 #define IOC_IOC18_IOCURR_CUR_8MA 0x00000800U 2898 #define IOC_IOC18_IOCURR_CUR_4MA 0x00000400U 2899 #define IOC_IOC18_IOCURR_CUR_2MA 0x00000000U 2900 2901 // Field: [9:8] IOSTR 2902 // 2903 // Drive strength configuration 2904 // ENUMs: 2905 // MAX Maximum drive strength 2906 // MEDIUM Medium drive strength 2907 // MIN Minimum drive stregnth 2908 // AUTO Automatic drive strength adjustment 2909 #define IOC_IOC18_IOSTR_W 2U 2910 #define IOC_IOC18_IOSTR_M 0x00000300U 2911 #define IOC_IOC18_IOSTR_S 8U 2912 #define IOC_IOC18_IOSTR_MAX 0x00000300U 2913 #define IOC_IOC18_IOSTR_MEDIUM 0x00000200U 2914 #define IOC_IOC18_IOSTR_MIN 0x00000100U 2915 #define IOC_IOC18_IOSTR_AUTO 0x00000000U 2916 2917 // Field: [2:0] PORTCFG 2918 // 2919 // Selects usage of DIO18 2920 // ENUMs: 2921 // DTB Digital Test Bus function 2922 // ANA Analog function 2923 // PFUNC5 Digital peripheral function-5 2924 // PFUNC4 Digital peripheral function-4 2925 // PFUNC3 Digital peripheral function-3 2926 // PFUNC2 Digital peripheral function-2 2927 // PFUNC1 Digital peripheral function-1 2928 // BASE Base function 2929 #define IOC_IOC18_PORTCFG_W 3U 2930 #define IOC_IOC18_PORTCFG_M 0x00000007U 2931 #define IOC_IOC18_PORTCFG_S 0U 2932 #define IOC_IOC18_PORTCFG_DTB 0x00000007U 2933 #define IOC_IOC18_PORTCFG_ANA 0x00000006U 2934 #define IOC_IOC18_PORTCFG_PFUNC5 0x00000005U 2935 #define IOC_IOC18_PORTCFG_PFUNC4 0x00000004U 2936 #define IOC_IOC18_PORTCFG_PFUNC3 0x00000003U 2937 #define IOC_IOC18_PORTCFG_PFUNC2 0x00000002U 2938 #define IOC_IOC18_PORTCFG_PFUNC1 0x00000001U 2939 #define IOC_IOC18_PORTCFG_BASE 0x00000000U 2940 2941 //***************************************************************************** 2942 // 2943 // Register: IOC_O_IOC19 2944 // 2945 //***************************************************************************** 2946 // Field: [30] HYSTEN 2947 // 2948 // This field controls input hysteresis 2949 // ENUMs: 2950 // EN Input hysteresis enabled 2951 // DIS Input hysteresis disabled 2952 #define IOC_IOC19_HYSTEN 0x40000000U 2953 #define IOC_IOC19_HYSTEN_M 0x40000000U 2954 #define IOC_IOC19_HYSTEN_S 30U 2955 #define IOC_IOC19_HYSTEN_EN 0x40000000U 2956 #define IOC_IOC19_HYSTEN_DIS 0x00000000U 2957 2958 // Field: [29] INPEN 2959 // 2960 // This field controls the input capability of DIO 2961 // ENUMs: 2962 // EN Input enabled 2963 // DIS Input disabled 2964 #define IOC_IOC19_INPEN 0x20000000U 2965 #define IOC_IOC19_INPEN_M 0x20000000U 2966 #define IOC_IOC19_INPEN_S 29U 2967 #define IOC_IOC19_INPEN_EN 0x20000000U 2968 #define IOC_IOC19_INPEN_DIS 0x00000000U 2969 2970 // Field: [26:24] IOMODE 2971 // 2972 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 2973 // behavior. 2974 // ENUMs: 2975 // OPENS_INV Open Source, inverted IO 2976 // OPENS Open Source, normal IO 2977 // OPEND_INV Open Drain, inverted IO 2978 // OPEND Open Drain, normal IO 2979 // INVERTED Inverted IO 2980 // NORMAL Normal IO 2981 #define IOC_IOC19_IOMODE_W 3U 2982 #define IOC_IOC19_IOMODE_M 0x07000000U 2983 #define IOC_IOC19_IOMODE_S 24U 2984 #define IOC_IOC19_IOMODE_OPENS_INV 0x05000000U 2985 #define IOC_IOC19_IOMODE_OPENS 0x04000000U 2986 #define IOC_IOC19_IOMODE_OPEND_INV 0x03000000U 2987 #define IOC_IOC19_IOMODE_OPEND 0x02000000U 2988 #define IOC_IOC19_IOMODE_INVERTED 0x01000000U 2989 #define IOC_IOC19_IOMODE_NORMAL 0x00000000U 2990 2991 // Field: [21:20] WUCFGSD 2992 // 2993 // Wakeup configuration from shutdown 2994 // ENUMs: 2995 // WAKE_HIGH Wakeup triggered when pad level is high 2996 // WAKE_LOW Wakeup triggered when pad level is low 2997 // DIS_1 Wakeup disabled 2998 // DIS_0 Wakeup disabled 2999 #define IOC_IOC19_WUCFGSD_W 2U 3000 #define IOC_IOC19_WUCFGSD_M 0x00300000U 3001 #define IOC_IOC19_WUCFGSD_S 20U 3002 #define IOC_IOC19_WUCFGSD_WAKE_HIGH 0x00300000U 3003 #define IOC_IOC19_WUCFGSD_WAKE_LOW 0x00200000U 3004 #define IOC_IOC19_WUCFGSD_DIS_1 0x00100000U 3005 #define IOC_IOC19_WUCFGSD_DIS_0 0x00000000U 3006 3007 // Field: [18] WUENSB 3008 // 3009 // Wakeup enable from standby 3010 // ENUMs: 3011 // EN Wakeup enabled (effective only if EDGEDET is 3012 // enabled) 3013 // DIS Wakeup disabled 3014 #define IOC_IOC19_WUENSB 0x00040000U 3015 #define IOC_IOC19_WUENSB_M 0x00040000U 3016 #define IOC_IOC19_WUENSB_S 18U 3017 #define IOC_IOC19_WUENSB_EN 0x00040000U 3018 #define IOC_IOC19_WUENSB_DIS 0x00000000U 3019 3020 // Field: [17:16] EDGEDET 3021 // 3022 // Edge detect configuration 3023 // ENUMs: 3024 // EDGE_BOTH Positive and negative edge detection 3025 // EDGE_POS Positive edge detection 3026 // EDGE_NEG Negative edge detection 3027 // EDGE_DIS No edge detection 3028 #define IOC_IOC19_EDGEDET_W 2U 3029 #define IOC_IOC19_EDGEDET_M 0x00030000U 3030 #define IOC_IOC19_EDGEDET_S 16U 3031 #define IOC_IOC19_EDGEDET_EDGE_BOTH 0x00030000U 3032 #define IOC_IOC19_EDGEDET_EDGE_POS 0x00020000U 3033 #define IOC_IOC19_EDGEDET_EDGE_NEG 0x00010000U 3034 #define IOC_IOC19_EDGEDET_EDGE_DIS 0x00000000U 3035 3036 // Field: [14:13] PULLCTL 3037 // 3038 // Pull control. Setting this to value 0x3 disables pull. 3039 // ENUMs: 3040 // PULL_UP Pull up enabled 3041 // PULL_DOWN Pull down enabled 3042 // PULL_DIS No pull 3043 #define IOC_IOC19_PULLCTL_W 2U 3044 #define IOC_IOC19_PULLCTL_M 0x00006000U 3045 #define IOC_IOC19_PULLCTL_S 13U 3046 #define IOC_IOC19_PULLCTL_PULL_UP 0x00004000U 3047 #define IOC_IOC19_PULLCTL_PULL_DOWN 0x00002000U 3048 #define IOC_IOC19_PULLCTL_PULL_DIS 0x00000000U 3049 3050 // Field: [12] SLEWRED 3051 // 3052 // Slew rate configuration 3053 // ENUMs: 3054 // REDUCED Reduced slew rate 3055 // NORMAL Normal slew rate 3056 #define IOC_IOC19_SLEWRED 0x00001000U 3057 #define IOC_IOC19_SLEWRED_M 0x00001000U 3058 #define IOC_IOC19_SLEWRED_S 12U 3059 #define IOC_IOC19_SLEWRED_REDUCED 0x00001000U 3060 #define IOC_IOC19_SLEWRED_NORMAL 0x00000000U 3061 3062 // Field: [11:10] IOCURR 3063 // 3064 // Output current configuration. Writing value 0x3 defaults to 2mA current 3065 // setting. 3066 // ENUMs: 3067 // CUR_8MA 3068 // CUR_4MA 3069 // CUR_2MA 3070 #define IOC_IOC19_IOCURR_W 2U 3071 #define IOC_IOC19_IOCURR_M 0x00000C00U 3072 #define IOC_IOC19_IOCURR_S 10U 3073 #define IOC_IOC19_IOCURR_CUR_8MA 0x00000800U 3074 #define IOC_IOC19_IOCURR_CUR_4MA 0x00000400U 3075 #define IOC_IOC19_IOCURR_CUR_2MA 0x00000000U 3076 3077 // Field: [9:8] IOSTR 3078 // 3079 // Drive strength configuration 3080 // ENUMs: 3081 // MAX Maximum drive strength 3082 // MEDIUM Medium drive strength 3083 // MIN Minimum drive stregnth 3084 // AUTO Automatic drive strength adjustment 3085 #define IOC_IOC19_IOSTR_W 2U 3086 #define IOC_IOC19_IOSTR_M 0x00000300U 3087 #define IOC_IOC19_IOSTR_S 8U 3088 #define IOC_IOC19_IOSTR_MAX 0x00000300U 3089 #define IOC_IOC19_IOSTR_MEDIUM 0x00000200U 3090 #define IOC_IOC19_IOSTR_MIN 0x00000100U 3091 #define IOC_IOC19_IOSTR_AUTO 0x00000000U 3092 3093 // Field: [2:0] PORTCFG 3094 // 3095 // Selects usage of DIO19 3096 // ENUMs: 3097 // DTB Digital Test Bus function 3098 // ANA Analog function 3099 // PFUNC5 Digital peripheral function-5 3100 // PFUNC4 Digital peripheral function-4 3101 // PFUNC3 Digital peripheral function-3 3102 // PFUNC2 Digital peripheral function-2 3103 // PFUNC1 Digital peripheral function-1 3104 // BASE Base function 3105 #define IOC_IOC19_PORTCFG_W 3U 3106 #define IOC_IOC19_PORTCFG_M 0x00000007U 3107 #define IOC_IOC19_PORTCFG_S 0U 3108 #define IOC_IOC19_PORTCFG_DTB 0x00000007U 3109 #define IOC_IOC19_PORTCFG_ANA 0x00000006U 3110 #define IOC_IOC19_PORTCFG_PFUNC5 0x00000005U 3111 #define IOC_IOC19_PORTCFG_PFUNC4 0x00000004U 3112 #define IOC_IOC19_PORTCFG_PFUNC3 0x00000003U 3113 #define IOC_IOC19_PORTCFG_PFUNC2 0x00000002U 3114 #define IOC_IOC19_PORTCFG_PFUNC1 0x00000001U 3115 #define IOC_IOC19_PORTCFG_BASE 0x00000000U 3116 3117 //***************************************************************************** 3118 // 3119 // Register: IOC_O_IOC20 3120 // 3121 //***************************************************************************** 3122 // Field: [30] HYSTEN 3123 // 3124 // This field controls input hysteresis 3125 // ENUMs: 3126 // EN Input hysteresis enabled 3127 // DIS Input hysteresis disabled 3128 #define IOC_IOC20_HYSTEN 0x40000000U 3129 #define IOC_IOC20_HYSTEN_M 0x40000000U 3130 #define IOC_IOC20_HYSTEN_S 30U 3131 #define IOC_IOC20_HYSTEN_EN 0x40000000U 3132 #define IOC_IOC20_HYSTEN_DIS 0x00000000U 3133 3134 // Field: [29] INPEN 3135 // 3136 // This field controls the input capability of DIO 3137 // ENUMs: 3138 // EN Input enabled 3139 // DIS Input disabled 3140 #define IOC_IOC20_INPEN 0x20000000U 3141 #define IOC_IOC20_INPEN_M 0x20000000U 3142 #define IOC_IOC20_INPEN_S 29U 3143 #define IOC_IOC20_INPEN_EN 0x20000000U 3144 #define IOC_IOC20_INPEN_DIS 0x00000000U 3145 3146 // Field: [26:24] IOMODE 3147 // 3148 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 3149 // behavior. 3150 // ENUMs: 3151 // OPENS_INV Open Source, inverted IO 3152 // OPENS Open Source, normal IO 3153 // OPEND_INV Open Drain, inverted IO 3154 // OPEND Open Drain, normal IO 3155 // INVERTED Inverted IO 3156 // NORMAL Normal IO 3157 #define IOC_IOC20_IOMODE_W 3U 3158 #define IOC_IOC20_IOMODE_M 0x07000000U 3159 #define IOC_IOC20_IOMODE_S 24U 3160 #define IOC_IOC20_IOMODE_OPENS_INV 0x05000000U 3161 #define IOC_IOC20_IOMODE_OPENS 0x04000000U 3162 #define IOC_IOC20_IOMODE_OPEND_INV 0x03000000U 3163 #define IOC_IOC20_IOMODE_OPEND 0x02000000U 3164 #define IOC_IOC20_IOMODE_INVERTED 0x01000000U 3165 #define IOC_IOC20_IOMODE_NORMAL 0x00000000U 3166 3167 // Field: [21:20] WUCFGSD 3168 // 3169 // Wakeup configuration from shutdown 3170 // ENUMs: 3171 // WAKE_HIGH Wakeup triggered when pad level is high 3172 // WAKE_LOW Wakeup triggered when pad level is low 3173 // DIS_1 Wakeup disabled 3174 // DIS_0 Wakeup disabled 3175 #define IOC_IOC20_WUCFGSD_W 2U 3176 #define IOC_IOC20_WUCFGSD_M 0x00300000U 3177 #define IOC_IOC20_WUCFGSD_S 20U 3178 #define IOC_IOC20_WUCFGSD_WAKE_HIGH 0x00300000U 3179 #define IOC_IOC20_WUCFGSD_WAKE_LOW 0x00200000U 3180 #define IOC_IOC20_WUCFGSD_DIS_1 0x00100000U 3181 #define IOC_IOC20_WUCFGSD_DIS_0 0x00000000U 3182 3183 // Field: [18] WUENSB 3184 // 3185 // Wakeup enable from standby 3186 // ENUMs: 3187 // EN Wakeup enabled (effective only if EDGEDET is 3188 // enabled) 3189 // DIS Wakeup disabled 3190 #define IOC_IOC20_WUENSB 0x00040000U 3191 #define IOC_IOC20_WUENSB_M 0x00040000U 3192 #define IOC_IOC20_WUENSB_S 18U 3193 #define IOC_IOC20_WUENSB_EN 0x00040000U 3194 #define IOC_IOC20_WUENSB_DIS 0x00000000U 3195 3196 // Field: [17:16] EDGEDET 3197 // 3198 // Edge detect configuration 3199 // ENUMs: 3200 // EDGE_BOTH Positive and negative edge detection 3201 // EDGE_POS Positive edge detection 3202 // EDGE_NEG Negative edge detection 3203 // EDGE_DIS No edge detection 3204 #define IOC_IOC20_EDGEDET_W 2U 3205 #define IOC_IOC20_EDGEDET_M 0x00030000U 3206 #define IOC_IOC20_EDGEDET_S 16U 3207 #define IOC_IOC20_EDGEDET_EDGE_BOTH 0x00030000U 3208 #define IOC_IOC20_EDGEDET_EDGE_POS 0x00020000U 3209 #define IOC_IOC20_EDGEDET_EDGE_NEG 0x00010000U 3210 #define IOC_IOC20_EDGEDET_EDGE_DIS 0x00000000U 3211 3212 // Field: [14:13] PULLCTL 3213 // 3214 // Pull control. Setting this to value 0x3 disables pull. 3215 // ENUMs: 3216 // PULL_UP Pull up enabled 3217 // PULL_DOWN Pull down enabled 3218 // PULL_DIS No pull 3219 #define IOC_IOC20_PULLCTL_W 2U 3220 #define IOC_IOC20_PULLCTL_M 0x00006000U 3221 #define IOC_IOC20_PULLCTL_S 13U 3222 #define IOC_IOC20_PULLCTL_PULL_UP 0x00004000U 3223 #define IOC_IOC20_PULLCTL_PULL_DOWN 0x00002000U 3224 #define IOC_IOC20_PULLCTL_PULL_DIS 0x00000000U 3225 3226 // Field: [2:0] PORTCFG 3227 // 3228 // Selects usage of DIO20 3229 // ENUMs: 3230 // DTB Digital Test Bus function 3231 // ANA Analog function 3232 // PFUNC5 Digital peripheral function-5 3233 // PFUNC4 Digital peripheral function-4 3234 // PFUNC3 Digital peripheral function-3 3235 // PFUNC2 Digital peripheral function-2 3236 // PFUNC1 Digital peripheral function-1 3237 // BASE Base function 3238 #define IOC_IOC20_PORTCFG_W 3U 3239 #define IOC_IOC20_PORTCFG_M 0x00000007U 3240 #define IOC_IOC20_PORTCFG_S 0U 3241 #define IOC_IOC20_PORTCFG_DTB 0x00000007U 3242 #define IOC_IOC20_PORTCFG_ANA 0x00000006U 3243 #define IOC_IOC20_PORTCFG_PFUNC5 0x00000005U 3244 #define IOC_IOC20_PORTCFG_PFUNC4 0x00000004U 3245 #define IOC_IOC20_PORTCFG_PFUNC3 0x00000003U 3246 #define IOC_IOC20_PORTCFG_PFUNC2 0x00000002U 3247 #define IOC_IOC20_PORTCFG_PFUNC1 0x00000001U 3248 #define IOC_IOC20_PORTCFG_BASE 0x00000000U 3249 3250 //***************************************************************************** 3251 // 3252 // Register: IOC_O_IOC21 3253 // 3254 //***************************************************************************** 3255 // Field: [30] HYSTEN 3256 // 3257 // This field controls input hysteresis 3258 // ENUMs: 3259 // EN Input hysteresis enabled 3260 // DIS Input hysteresis disabled 3261 #define IOC_IOC21_HYSTEN 0x40000000U 3262 #define IOC_IOC21_HYSTEN_M 0x40000000U 3263 #define IOC_IOC21_HYSTEN_S 30U 3264 #define IOC_IOC21_HYSTEN_EN 0x40000000U 3265 #define IOC_IOC21_HYSTEN_DIS 0x00000000U 3266 3267 // Field: [29] INPEN 3268 // 3269 // This field controls the input capability of DIO 3270 // ENUMs: 3271 // EN Input enabled 3272 // DIS Input disabled 3273 #define IOC_IOC21_INPEN 0x20000000U 3274 #define IOC_IOC21_INPEN_M 0x20000000U 3275 #define IOC_IOC21_INPEN_S 29U 3276 #define IOC_IOC21_INPEN_EN 0x20000000U 3277 #define IOC_IOC21_INPEN_DIS 0x00000000U 3278 3279 // Field: [26:24] IOMODE 3280 // 3281 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 3282 // behavior. 3283 // ENUMs: 3284 // OPENS_INV Open Source, inverted IO 3285 // OPENS Open Source, normal IO 3286 // OPEND_INV Open Drain, inverted IO 3287 // OPEND Open Drain, normal IO 3288 // INVERTED Inverted IO 3289 // NORMAL Normal IO 3290 #define IOC_IOC21_IOMODE_W 3U 3291 #define IOC_IOC21_IOMODE_M 0x07000000U 3292 #define IOC_IOC21_IOMODE_S 24U 3293 #define IOC_IOC21_IOMODE_OPENS_INV 0x05000000U 3294 #define IOC_IOC21_IOMODE_OPENS 0x04000000U 3295 #define IOC_IOC21_IOMODE_OPEND_INV 0x03000000U 3296 #define IOC_IOC21_IOMODE_OPEND 0x02000000U 3297 #define IOC_IOC21_IOMODE_INVERTED 0x01000000U 3298 #define IOC_IOC21_IOMODE_NORMAL 0x00000000U 3299 3300 // Field: [21:20] WUCFGSD 3301 // 3302 // Wakeup configuration from shutdown 3303 // ENUMs: 3304 // WAKE_HIGH Wakeup triggered when pad level is high 3305 // WAKE_LOW Wakeup triggered when pad level is low 3306 // DIS_1 Wakeup disabled 3307 // DIS_0 Wakeup disabled 3308 #define IOC_IOC21_WUCFGSD_W 2U 3309 #define IOC_IOC21_WUCFGSD_M 0x00300000U 3310 #define IOC_IOC21_WUCFGSD_S 20U 3311 #define IOC_IOC21_WUCFGSD_WAKE_HIGH 0x00300000U 3312 #define IOC_IOC21_WUCFGSD_WAKE_LOW 0x00200000U 3313 #define IOC_IOC21_WUCFGSD_DIS_1 0x00100000U 3314 #define IOC_IOC21_WUCFGSD_DIS_0 0x00000000U 3315 3316 // Field: [18] WUENSB 3317 // 3318 // Wakeup enable from standby 3319 // ENUMs: 3320 // EN Wakeup enabled (effective only if EDGEDET is 3321 // enabled) 3322 // DIS Wakeup disabled 3323 #define IOC_IOC21_WUENSB 0x00040000U 3324 #define IOC_IOC21_WUENSB_M 0x00040000U 3325 #define IOC_IOC21_WUENSB_S 18U 3326 #define IOC_IOC21_WUENSB_EN 0x00040000U 3327 #define IOC_IOC21_WUENSB_DIS 0x00000000U 3328 3329 // Field: [17:16] EDGEDET 3330 // 3331 // Edge detect configuration 3332 // ENUMs: 3333 // EDGE_BOTH Positive and negative edge detection 3334 // EDGE_POS Positive edge detection 3335 // EDGE_NEG Negative edge detection 3336 // EDGE_DIS No edge detection 3337 #define IOC_IOC21_EDGEDET_W 2U 3338 #define IOC_IOC21_EDGEDET_M 0x00030000U 3339 #define IOC_IOC21_EDGEDET_S 16U 3340 #define IOC_IOC21_EDGEDET_EDGE_BOTH 0x00030000U 3341 #define IOC_IOC21_EDGEDET_EDGE_POS 0x00020000U 3342 #define IOC_IOC21_EDGEDET_EDGE_NEG 0x00010000U 3343 #define IOC_IOC21_EDGEDET_EDGE_DIS 0x00000000U 3344 3345 // Field: [14:13] PULLCTL 3346 // 3347 // Pull control. Setting this to value 0x3 disables pull. 3348 // ENUMs: 3349 // PULL_UP Pull up enabled 3350 // PULL_DOWN Pull down enabled 3351 // PULL_DIS No pull 3352 #define IOC_IOC21_PULLCTL_W 2U 3353 #define IOC_IOC21_PULLCTL_M 0x00006000U 3354 #define IOC_IOC21_PULLCTL_S 13U 3355 #define IOC_IOC21_PULLCTL_PULL_UP 0x00004000U 3356 #define IOC_IOC21_PULLCTL_PULL_DOWN 0x00002000U 3357 #define IOC_IOC21_PULLCTL_PULL_DIS 0x00000000U 3358 3359 // Field: [2:0] PORTCFG 3360 // 3361 // Selects usage of DIO21 3362 // ENUMs: 3363 // DTB Digital Test Bus function 3364 // ANA Analog function 3365 // PFUNC5 Digital peripheral function-5 3366 // PFUNC4 Digital peripheral function-4 3367 // PFUNC3 Digital peripheral function-3 3368 // PFUNC2 Digital peripheral function-2 3369 // PFUNC1 Digital peripheral function-1 3370 // BASE Base function 3371 #define IOC_IOC21_PORTCFG_W 3U 3372 #define IOC_IOC21_PORTCFG_M 0x00000007U 3373 #define IOC_IOC21_PORTCFG_S 0U 3374 #define IOC_IOC21_PORTCFG_DTB 0x00000007U 3375 #define IOC_IOC21_PORTCFG_ANA 0x00000006U 3376 #define IOC_IOC21_PORTCFG_PFUNC5 0x00000005U 3377 #define IOC_IOC21_PORTCFG_PFUNC4 0x00000004U 3378 #define IOC_IOC21_PORTCFG_PFUNC3 0x00000003U 3379 #define IOC_IOC21_PORTCFG_PFUNC2 0x00000002U 3380 #define IOC_IOC21_PORTCFG_PFUNC1 0x00000001U 3381 #define IOC_IOC21_PORTCFG_BASE 0x00000000U 3382 3383 //***************************************************************************** 3384 // 3385 // Register: IOC_O_IOC22 3386 // 3387 //***************************************************************************** 3388 // Field: [30] HYSTEN 3389 // 3390 // This field controls input hysteresis 3391 // ENUMs: 3392 // EN Input hysteresis enabled 3393 // DIS Input hysteresis disabled 3394 #define IOC_IOC22_HYSTEN 0x40000000U 3395 #define IOC_IOC22_HYSTEN_M 0x40000000U 3396 #define IOC_IOC22_HYSTEN_S 30U 3397 #define IOC_IOC22_HYSTEN_EN 0x40000000U 3398 #define IOC_IOC22_HYSTEN_DIS 0x00000000U 3399 3400 // Field: [29] INPEN 3401 // 3402 // This field controls the input capability of DIO 3403 // ENUMs: 3404 // EN Input enabled 3405 // DIS Input disabled 3406 #define IOC_IOC22_INPEN 0x20000000U 3407 #define IOC_IOC22_INPEN_M 0x20000000U 3408 #define IOC_IOC22_INPEN_S 29U 3409 #define IOC_IOC22_INPEN_EN 0x20000000U 3410 #define IOC_IOC22_INPEN_DIS 0x00000000U 3411 3412 // Field: [26:24] IOMODE 3413 // 3414 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 3415 // behavior. 3416 // ENUMs: 3417 // OPENS_INV Open Source, inverted IO 3418 // OPENS Open Source, normal IO 3419 // OPEND_INV Open Drain, inverted IO 3420 // OPEND Open Drain, normal IO 3421 // INVERTED Inverted IO 3422 // NORMAL Normal IO 3423 #define IOC_IOC22_IOMODE_W 3U 3424 #define IOC_IOC22_IOMODE_M 0x07000000U 3425 #define IOC_IOC22_IOMODE_S 24U 3426 #define IOC_IOC22_IOMODE_OPENS_INV 0x05000000U 3427 #define IOC_IOC22_IOMODE_OPENS 0x04000000U 3428 #define IOC_IOC22_IOMODE_OPEND_INV 0x03000000U 3429 #define IOC_IOC22_IOMODE_OPEND 0x02000000U 3430 #define IOC_IOC22_IOMODE_INVERTED 0x01000000U 3431 #define IOC_IOC22_IOMODE_NORMAL 0x00000000U 3432 3433 // Field: [21:20] WUCFGSD 3434 // 3435 // Wakeup configuration from shutdown 3436 // ENUMs: 3437 // WAKE_HIGH Wakeup triggered when pad level is high 3438 // WAKE_LOW Wakeup triggered when pad level is low 3439 // DIS_1 Wakeup disabled 3440 // DIS_0 Wakeup disabled 3441 #define IOC_IOC22_WUCFGSD_W 2U 3442 #define IOC_IOC22_WUCFGSD_M 0x00300000U 3443 #define IOC_IOC22_WUCFGSD_S 20U 3444 #define IOC_IOC22_WUCFGSD_WAKE_HIGH 0x00300000U 3445 #define IOC_IOC22_WUCFGSD_WAKE_LOW 0x00200000U 3446 #define IOC_IOC22_WUCFGSD_DIS_1 0x00100000U 3447 #define IOC_IOC22_WUCFGSD_DIS_0 0x00000000U 3448 3449 // Field: [18] WUENSB 3450 // 3451 // Wakeup enable from standby 3452 // ENUMs: 3453 // EN Wakeup enabled (effective only if EDGEDET is 3454 // enabled) 3455 // DIS Wakeup disabled 3456 #define IOC_IOC22_WUENSB 0x00040000U 3457 #define IOC_IOC22_WUENSB_M 0x00040000U 3458 #define IOC_IOC22_WUENSB_S 18U 3459 #define IOC_IOC22_WUENSB_EN 0x00040000U 3460 #define IOC_IOC22_WUENSB_DIS 0x00000000U 3461 3462 // Field: [17:16] EDGEDET 3463 // 3464 // Edge detect configuration 3465 // ENUMs: 3466 // EDGE_BOTH Positive and negative edge detection 3467 // EDGE_POS Positive edge detection 3468 // EDGE_NEG Negative edge detection 3469 // EDGE_DIS No edge detection 3470 #define IOC_IOC22_EDGEDET_W 2U 3471 #define IOC_IOC22_EDGEDET_M 0x00030000U 3472 #define IOC_IOC22_EDGEDET_S 16U 3473 #define IOC_IOC22_EDGEDET_EDGE_BOTH 0x00030000U 3474 #define IOC_IOC22_EDGEDET_EDGE_POS 0x00020000U 3475 #define IOC_IOC22_EDGEDET_EDGE_NEG 0x00010000U 3476 #define IOC_IOC22_EDGEDET_EDGE_DIS 0x00000000U 3477 3478 // Field: [14:13] PULLCTL 3479 // 3480 // Pull control. Setting this to value 0x3 disables pull. 3481 // ENUMs: 3482 // PULL_UP Pull up enabled 3483 // PULL_DOWN Pull down enabled 3484 // PULL_DIS No pull 3485 #define IOC_IOC22_PULLCTL_W 2U 3486 #define IOC_IOC22_PULLCTL_M 0x00006000U 3487 #define IOC_IOC22_PULLCTL_S 13U 3488 #define IOC_IOC22_PULLCTL_PULL_UP 0x00004000U 3489 #define IOC_IOC22_PULLCTL_PULL_DOWN 0x00002000U 3490 #define IOC_IOC22_PULLCTL_PULL_DIS 0x00000000U 3491 3492 // Field: [2:0] PORTCFG 3493 // 3494 // Selects usage of DIO22 3495 // ENUMs: 3496 // DTB Digital Test Bus function 3497 // ANA Analog function 3498 // PFUNC5 Digital peripheral function-5 3499 // PFUNC4 Digital peripheral function-4 3500 // PFUNC3 Digital peripheral function-3 3501 // PFUNC2 Digital peripheral function-2 3502 // PFUNC1 Digital peripheral function-1 3503 // BASE Base function 3504 #define IOC_IOC22_PORTCFG_W 3U 3505 #define IOC_IOC22_PORTCFG_M 0x00000007U 3506 #define IOC_IOC22_PORTCFG_S 0U 3507 #define IOC_IOC22_PORTCFG_DTB 0x00000007U 3508 #define IOC_IOC22_PORTCFG_ANA 0x00000006U 3509 #define IOC_IOC22_PORTCFG_PFUNC5 0x00000005U 3510 #define IOC_IOC22_PORTCFG_PFUNC4 0x00000004U 3511 #define IOC_IOC22_PORTCFG_PFUNC3 0x00000003U 3512 #define IOC_IOC22_PORTCFG_PFUNC2 0x00000002U 3513 #define IOC_IOC22_PORTCFG_PFUNC1 0x00000001U 3514 #define IOC_IOC22_PORTCFG_BASE 0x00000000U 3515 3516 //***************************************************************************** 3517 // 3518 // Register: IOC_O_IOC23 3519 // 3520 //***************************************************************************** 3521 // Field: [30] HYSTEN 3522 // 3523 // This field controls input hysteresis 3524 // ENUMs: 3525 // EN Input hysteresis enabled 3526 // DIS Input hysteresis disabled 3527 #define IOC_IOC23_HYSTEN 0x40000000U 3528 #define IOC_IOC23_HYSTEN_M 0x40000000U 3529 #define IOC_IOC23_HYSTEN_S 30U 3530 #define IOC_IOC23_HYSTEN_EN 0x40000000U 3531 #define IOC_IOC23_HYSTEN_DIS 0x00000000U 3532 3533 // Field: [29] INPEN 3534 // 3535 // This field controls the input capability of DIO 3536 // ENUMs: 3537 // EN Input enabled 3538 // DIS Input disabled 3539 #define IOC_IOC23_INPEN 0x20000000U 3540 #define IOC_IOC23_INPEN_M 0x20000000U 3541 #define IOC_IOC23_INPEN_S 29U 3542 #define IOC_IOC23_INPEN_EN 0x20000000U 3543 #define IOC_IOC23_INPEN_DIS 0x00000000U 3544 3545 // Field: [26:24] IOMODE 3546 // 3547 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 3548 // behavior. 3549 // ENUMs: 3550 // OPENS_INV Open Source, inverted IO 3551 // OPENS Open Source, normal IO 3552 // OPEND_INV Open Drain, inverted IO 3553 // OPEND Open Drain, normal IO 3554 // INVERTED Inverted IO 3555 // NORMAL Normal IO 3556 #define IOC_IOC23_IOMODE_W 3U 3557 #define IOC_IOC23_IOMODE_M 0x07000000U 3558 #define IOC_IOC23_IOMODE_S 24U 3559 #define IOC_IOC23_IOMODE_OPENS_INV 0x05000000U 3560 #define IOC_IOC23_IOMODE_OPENS 0x04000000U 3561 #define IOC_IOC23_IOMODE_OPEND_INV 0x03000000U 3562 #define IOC_IOC23_IOMODE_OPEND 0x02000000U 3563 #define IOC_IOC23_IOMODE_INVERTED 0x01000000U 3564 #define IOC_IOC23_IOMODE_NORMAL 0x00000000U 3565 3566 // Field: [21:20] WUCFGSD 3567 // 3568 // Wakeup configuration from shutdown 3569 // ENUMs: 3570 // WAKE_HIGH Wakeup triggered when pad level is high 3571 // WAKE_LOW Wakeup triggered when pad level is low 3572 // DIS_1 Wakeup disabled 3573 // DIS_0 Wakeup disabled 3574 #define IOC_IOC23_WUCFGSD_W 2U 3575 #define IOC_IOC23_WUCFGSD_M 0x00300000U 3576 #define IOC_IOC23_WUCFGSD_S 20U 3577 #define IOC_IOC23_WUCFGSD_WAKE_HIGH 0x00300000U 3578 #define IOC_IOC23_WUCFGSD_WAKE_LOW 0x00200000U 3579 #define IOC_IOC23_WUCFGSD_DIS_1 0x00100000U 3580 #define IOC_IOC23_WUCFGSD_DIS_0 0x00000000U 3581 3582 // Field: [18] WUENSB 3583 // 3584 // Wakeup enable from standby 3585 // ENUMs: 3586 // EN Wakeup enabled (effective only if EDGEDET is 3587 // enabled) 3588 // DIS Wakeup disabled 3589 #define IOC_IOC23_WUENSB 0x00040000U 3590 #define IOC_IOC23_WUENSB_M 0x00040000U 3591 #define IOC_IOC23_WUENSB_S 18U 3592 #define IOC_IOC23_WUENSB_EN 0x00040000U 3593 #define IOC_IOC23_WUENSB_DIS 0x00000000U 3594 3595 // Field: [17:16] EDGEDET 3596 // 3597 // Edge detect configuration 3598 // ENUMs: 3599 // EDGE_BOTH Positive and negative edge detection 3600 // EDGE_POS Positive edge detection 3601 // EDGE_NEG Negative edge detection 3602 // EDGE_DIS No edge detection 3603 #define IOC_IOC23_EDGEDET_W 2U 3604 #define IOC_IOC23_EDGEDET_M 0x00030000U 3605 #define IOC_IOC23_EDGEDET_S 16U 3606 #define IOC_IOC23_EDGEDET_EDGE_BOTH 0x00030000U 3607 #define IOC_IOC23_EDGEDET_EDGE_POS 0x00020000U 3608 #define IOC_IOC23_EDGEDET_EDGE_NEG 0x00010000U 3609 #define IOC_IOC23_EDGEDET_EDGE_DIS 0x00000000U 3610 3611 // Field: [14:13] PULLCTL 3612 // 3613 // Pull control. Setting this to value 0x3 disables pull. 3614 // ENUMs: 3615 // PULL_UP Pull up enabled 3616 // PULL_DOWN Pull down enabled 3617 // PULL_DIS No pull 3618 #define IOC_IOC23_PULLCTL_W 2U 3619 #define IOC_IOC23_PULLCTL_M 0x00006000U 3620 #define IOC_IOC23_PULLCTL_S 13U 3621 #define IOC_IOC23_PULLCTL_PULL_UP 0x00004000U 3622 #define IOC_IOC23_PULLCTL_PULL_DOWN 0x00002000U 3623 #define IOC_IOC23_PULLCTL_PULL_DIS 0x00000000U 3624 3625 // Field: [2:0] PORTCFG 3626 // 3627 // Selects usage of DIO23 3628 // ENUMs: 3629 // DTB Digital Test Bus function 3630 // ANA Analog function 3631 // PFUNC5 Digital peripheral function-5 3632 // PFUNC4 Digital peripheral function-4 3633 // PFUNC3 Digital peripheral function-3 3634 // PFUNC2 Digital peripheral function-2 3635 // PFUNC1 Digital peripheral function-1 3636 // BASE Base function 3637 #define IOC_IOC23_PORTCFG_W 3U 3638 #define IOC_IOC23_PORTCFG_M 0x00000007U 3639 #define IOC_IOC23_PORTCFG_S 0U 3640 #define IOC_IOC23_PORTCFG_DTB 0x00000007U 3641 #define IOC_IOC23_PORTCFG_ANA 0x00000006U 3642 #define IOC_IOC23_PORTCFG_PFUNC5 0x00000005U 3643 #define IOC_IOC23_PORTCFG_PFUNC4 0x00000004U 3644 #define IOC_IOC23_PORTCFG_PFUNC3 0x00000003U 3645 #define IOC_IOC23_PORTCFG_PFUNC2 0x00000002U 3646 #define IOC_IOC23_PORTCFG_PFUNC1 0x00000001U 3647 #define IOC_IOC23_PORTCFG_BASE 0x00000000U 3648 3649 //***************************************************************************** 3650 // 3651 // Register: IOC_O_IOC24 3652 // 3653 //***************************************************************************** 3654 // Field: [30] HYSTEN 3655 // 3656 // This field controls input hysteresis 3657 // ENUMs: 3658 // EN Input hysteresis enabled 3659 // DIS Input hysteresis disabled 3660 #define IOC_IOC24_HYSTEN 0x40000000U 3661 #define IOC_IOC24_HYSTEN_M 0x40000000U 3662 #define IOC_IOC24_HYSTEN_S 30U 3663 #define IOC_IOC24_HYSTEN_EN 0x40000000U 3664 #define IOC_IOC24_HYSTEN_DIS 0x00000000U 3665 3666 // Field: [29] INPEN 3667 // 3668 // This field controls the input capability of DIO 3669 // ENUMs: 3670 // EN Input enabled 3671 // DIS Input disabled 3672 #define IOC_IOC24_INPEN 0x20000000U 3673 #define IOC_IOC24_INPEN_M 0x20000000U 3674 #define IOC_IOC24_INPEN_S 29U 3675 #define IOC_IOC24_INPEN_EN 0x20000000U 3676 #define IOC_IOC24_INPEN_DIS 0x00000000U 3677 3678 // Field: [26:24] IOMODE 3679 // 3680 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 3681 // behavior. 3682 // ENUMs: 3683 // OPENS_INV Open Source, inverted IO 3684 // OPENS Open Source, normal IO 3685 // OPEND_INV Open Drain, inverted IO 3686 // OPEND Open Drain, normal IO 3687 // INVERTED Inverted IO 3688 // NORMAL Normal IO 3689 #define IOC_IOC24_IOMODE_W 3U 3690 #define IOC_IOC24_IOMODE_M 0x07000000U 3691 #define IOC_IOC24_IOMODE_S 24U 3692 #define IOC_IOC24_IOMODE_OPENS_INV 0x05000000U 3693 #define IOC_IOC24_IOMODE_OPENS 0x04000000U 3694 #define IOC_IOC24_IOMODE_OPEND_INV 0x03000000U 3695 #define IOC_IOC24_IOMODE_OPEND 0x02000000U 3696 #define IOC_IOC24_IOMODE_INVERTED 0x01000000U 3697 #define IOC_IOC24_IOMODE_NORMAL 0x00000000U 3698 3699 // Field: [21:20] WUCFGSD 3700 // 3701 // Wakeup configuration from shutdown 3702 // ENUMs: 3703 // WAKE_HIGH Wakeup triggered when pad level is high 3704 // WAKE_LOW Wakeup triggered when pad level is low 3705 // DIS_1 Wakeup disabled 3706 // DIS_0 Wakeup disabled 3707 #define IOC_IOC24_WUCFGSD_W 2U 3708 #define IOC_IOC24_WUCFGSD_M 0x00300000U 3709 #define IOC_IOC24_WUCFGSD_S 20U 3710 #define IOC_IOC24_WUCFGSD_WAKE_HIGH 0x00300000U 3711 #define IOC_IOC24_WUCFGSD_WAKE_LOW 0x00200000U 3712 #define IOC_IOC24_WUCFGSD_DIS_1 0x00100000U 3713 #define IOC_IOC24_WUCFGSD_DIS_0 0x00000000U 3714 3715 // Field: [18] WUENSB 3716 // 3717 // Wakeup enable from standby 3718 // ENUMs: 3719 // EN Wakeup enabled (effective only if EDGEDET is 3720 // enabled) 3721 // DIS Wakeup disabled 3722 #define IOC_IOC24_WUENSB 0x00040000U 3723 #define IOC_IOC24_WUENSB_M 0x00040000U 3724 #define IOC_IOC24_WUENSB_S 18U 3725 #define IOC_IOC24_WUENSB_EN 0x00040000U 3726 #define IOC_IOC24_WUENSB_DIS 0x00000000U 3727 3728 // Field: [17:16] EDGEDET 3729 // 3730 // Edge detect configuration 3731 // ENUMs: 3732 // EDGE_BOTH Positive and negative edge detection 3733 // EDGE_POS Positive edge detection 3734 // EDGE_NEG Negative edge detection 3735 // EDGE_DIS No edge detection 3736 #define IOC_IOC24_EDGEDET_W 2U 3737 #define IOC_IOC24_EDGEDET_M 0x00030000U 3738 #define IOC_IOC24_EDGEDET_S 16U 3739 #define IOC_IOC24_EDGEDET_EDGE_BOTH 0x00030000U 3740 #define IOC_IOC24_EDGEDET_EDGE_POS 0x00020000U 3741 #define IOC_IOC24_EDGEDET_EDGE_NEG 0x00010000U 3742 #define IOC_IOC24_EDGEDET_EDGE_DIS 0x00000000U 3743 3744 // Field: [14:13] PULLCTL 3745 // 3746 // Pull control. Setting this to value 0x3 disables pull. 3747 // ENUMs: 3748 // PULL_UP Pull up enabled 3749 // PULL_DOWN Pull down enabled 3750 // PULL_DIS No pull 3751 #define IOC_IOC24_PULLCTL_W 2U 3752 #define IOC_IOC24_PULLCTL_M 0x00006000U 3753 #define IOC_IOC24_PULLCTL_S 13U 3754 #define IOC_IOC24_PULLCTL_PULL_UP 0x00004000U 3755 #define IOC_IOC24_PULLCTL_PULL_DOWN 0x00002000U 3756 #define IOC_IOC24_PULLCTL_PULL_DIS 0x00000000U 3757 3758 // Field: [12] SLEWRED 3759 // 3760 // Slew rate configuration 3761 // ENUMs: 3762 // REDUCED Reduced slew rate 3763 // NORMAL Normal slew rate 3764 #define IOC_IOC24_SLEWRED 0x00001000U 3765 #define IOC_IOC24_SLEWRED_M 0x00001000U 3766 #define IOC_IOC24_SLEWRED_S 12U 3767 #define IOC_IOC24_SLEWRED_REDUCED 0x00001000U 3768 #define IOC_IOC24_SLEWRED_NORMAL 0x00000000U 3769 3770 // Field: [11:10] IOCURR 3771 // 3772 // Output current configuration. Writing value 0x3 defaults to 2mA current 3773 // setting. 3774 // ENUMs: 3775 // CUR_8MA 3776 // CUR_4MA 3777 // CUR_2MA 3778 #define IOC_IOC24_IOCURR_W 2U 3779 #define IOC_IOC24_IOCURR_M 0x00000C00U 3780 #define IOC_IOC24_IOCURR_S 10U 3781 #define IOC_IOC24_IOCURR_CUR_8MA 0x00000800U 3782 #define IOC_IOC24_IOCURR_CUR_4MA 0x00000400U 3783 #define IOC_IOC24_IOCURR_CUR_2MA 0x00000000U 3784 3785 // Field: [9:8] IOSTR 3786 // 3787 // Drive strength configuration 3788 // ENUMs: 3789 // MAX Maximum drive strength 3790 // MEDIUM Medium drive strength 3791 // MIN Minimum drive stregnth 3792 // AUTO Automatic drive strength adjustment 3793 #define IOC_IOC24_IOSTR_W 2U 3794 #define IOC_IOC24_IOSTR_M 0x00000300U 3795 #define IOC_IOC24_IOSTR_S 8U 3796 #define IOC_IOC24_IOSTR_MAX 0x00000300U 3797 #define IOC_IOC24_IOSTR_MEDIUM 0x00000200U 3798 #define IOC_IOC24_IOSTR_MIN 0x00000100U 3799 #define IOC_IOC24_IOSTR_AUTO 0x00000000U 3800 3801 // Field: [2:0] PORTCFG 3802 // 3803 // Selects usage of DIO24 3804 // ENUMs: 3805 // DTB Digital Test Bus function 3806 // ANA Analog function 3807 // PFUNC5 Digital peripheral function-5 3808 // PFUNC4 Digital peripheral function-4 3809 // PFUNC3 Digital peripheral function-3 3810 // PFUNC2 Digital peripheral function-2 3811 // PFUNC1 Digital peripheral function-1 3812 // BASE Base function 3813 #define IOC_IOC24_PORTCFG_W 3U 3814 #define IOC_IOC24_PORTCFG_M 0x00000007U 3815 #define IOC_IOC24_PORTCFG_S 0U 3816 #define IOC_IOC24_PORTCFG_DTB 0x00000007U 3817 #define IOC_IOC24_PORTCFG_ANA 0x00000006U 3818 #define IOC_IOC24_PORTCFG_PFUNC5 0x00000005U 3819 #define IOC_IOC24_PORTCFG_PFUNC4 0x00000004U 3820 #define IOC_IOC24_PORTCFG_PFUNC3 0x00000003U 3821 #define IOC_IOC24_PORTCFG_PFUNC2 0x00000002U 3822 #define IOC_IOC24_PORTCFG_PFUNC1 0x00000001U 3823 #define IOC_IOC24_PORTCFG_BASE 0x00000000U 3824 3825 //***************************************************************************** 3826 // 3827 // Register: IOC_O_IOC25 3828 // 3829 //***************************************************************************** 3830 // Field: [30] HYSTEN 3831 // 3832 // This field controls input hysteresis 3833 // ENUMs: 3834 // EN Input hysteresis enabled 3835 // DIS Input hysteresis disabled 3836 #define IOC_IOC25_HYSTEN 0x40000000U 3837 #define IOC_IOC25_HYSTEN_M 0x40000000U 3838 #define IOC_IOC25_HYSTEN_S 30U 3839 #define IOC_IOC25_HYSTEN_EN 0x40000000U 3840 #define IOC_IOC25_HYSTEN_DIS 0x00000000U 3841 3842 // Field: [29] INPEN 3843 // 3844 // This field controls the input capability of DIO 3845 // ENUMs: 3846 // EN Input enabled 3847 // DIS Input disabled 3848 #define IOC_IOC25_INPEN 0x20000000U 3849 #define IOC_IOC25_INPEN_M 0x20000000U 3850 #define IOC_IOC25_INPEN_S 29U 3851 #define IOC_IOC25_INPEN_EN 0x20000000U 3852 #define IOC_IOC25_INPEN_DIS 0x00000000U 3853 3854 // Field: [26:24] IOMODE 3855 // 3856 // IO Mode. Setting this to value 0x6 or 0x7 will default to normal IO 3857 // behavior. 3858 // ENUMs: 3859 // OPENS_INV Open Source, inverted IO 3860 // OPENS Open Source, normal IO 3861 // OPEND_INV Open Drain, inverted IO 3862 // OPEND Open Drain, normal IO 3863 // INVERTED Inverted IO 3864 // NORMAL Normal IO 3865 #define IOC_IOC25_IOMODE_W 3U 3866 #define IOC_IOC25_IOMODE_M 0x07000000U 3867 #define IOC_IOC25_IOMODE_S 24U 3868 #define IOC_IOC25_IOMODE_OPENS_INV 0x05000000U 3869 #define IOC_IOC25_IOMODE_OPENS 0x04000000U 3870 #define IOC_IOC25_IOMODE_OPEND_INV 0x03000000U 3871 #define IOC_IOC25_IOMODE_OPEND 0x02000000U 3872 #define IOC_IOC25_IOMODE_INVERTED 0x01000000U 3873 #define IOC_IOC25_IOMODE_NORMAL 0x00000000U 3874 3875 // Field: [21:20] WUCFGSD 3876 // 3877 // Wakeup configuration from shutdown 3878 // ENUMs: 3879 // WAKE_HIGH Wakeup triggered when pad level is high 3880 // WAKE_LOW Wakeup triggered when pad level is low 3881 // DIS_1 Wakeup disabled 3882 // DIS_0 Wakeup disabled 3883 #define IOC_IOC25_WUCFGSD_W 2U 3884 #define IOC_IOC25_WUCFGSD_M 0x00300000U 3885 #define IOC_IOC25_WUCFGSD_S 20U 3886 #define IOC_IOC25_WUCFGSD_WAKE_HIGH 0x00300000U 3887 #define IOC_IOC25_WUCFGSD_WAKE_LOW 0x00200000U 3888 #define IOC_IOC25_WUCFGSD_DIS_1 0x00100000U 3889 #define IOC_IOC25_WUCFGSD_DIS_0 0x00000000U 3890 3891 // Field: [18] WUENSB 3892 // 3893 // Wakeup enable from standby 3894 // ENUMs: 3895 // EN Wakeup enabled (effective only if EDGEDET is 3896 // enabled) 3897 // DIS Wakeup disabled 3898 #define IOC_IOC25_WUENSB 0x00040000U 3899 #define IOC_IOC25_WUENSB_M 0x00040000U 3900 #define IOC_IOC25_WUENSB_S 18U 3901 #define IOC_IOC25_WUENSB_EN 0x00040000U 3902 #define IOC_IOC25_WUENSB_DIS 0x00000000U 3903 3904 // Field: [17:16] EDGEDET 3905 // 3906 // Edge detect configuration 3907 // ENUMs: 3908 // EDGE_BOTH Positive and negative edge detection 3909 // EDGE_POS Positive edge detection 3910 // EDGE_NEG Negative edge detection 3911 // EDGE_DIS No edge detection 3912 #define IOC_IOC25_EDGEDET_W 2U 3913 #define IOC_IOC25_EDGEDET_M 0x00030000U 3914 #define IOC_IOC25_EDGEDET_S 16U 3915 #define IOC_IOC25_EDGEDET_EDGE_BOTH 0x00030000U 3916 #define IOC_IOC25_EDGEDET_EDGE_POS 0x00020000U 3917 #define IOC_IOC25_EDGEDET_EDGE_NEG 0x00010000U 3918 #define IOC_IOC25_EDGEDET_EDGE_DIS 0x00000000U 3919 3920 // Field: [14:13] PULLCTL 3921 // 3922 // Pull control. Setting this to value 0x3 disables pull. 3923 // ENUMs: 3924 // PULL_UP Pull up enabled 3925 // PULL_DOWN Pull down enabled 3926 // PULL_DIS No pull 3927 #define IOC_IOC25_PULLCTL_W 2U 3928 #define IOC_IOC25_PULLCTL_M 0x00006000U 3929 #define IOC_IOC25_PULLCTL_S 13U 3930 #define IOC_IOC25_PULLCTL_PULL_UP 0x00004000U 3931 #define IOC_IOC25_PULLCTL_PULL_DOWN 0x00002000U 3932 #define IOC_IOC25_PULLCTL_PULL_DIS 0x00000000U 3933 3934 // Field: [2:0] PORTCFG 3935 // 3936 // Selects usage of DIO25 3937 // ENUMs: 3938 // DTB Digital Test Bus function 3939 // ANA Analog function 3940 // PFUNC5 Digital peripheral function-5 3941 // PFUNC4 Digital peripheral function-4 3942 // PFUNC3 Digital peripheral function-3 3943 // PFUNC2 Digital peripheral function-2 3944 // PFUNC1 Digital peripheral function-1 3945 // BASE Base function 3946 #define IOC_IOC25_PORTCFG_W 3U 3947 #define IOC_IOC25_PORTCFG_M 0x00000007U 3948 #define IOC_IOC25_PORTCFG_S 0U 3949 #define IOC_IOC25_PORTCFG_DTB 0x00000007U 3950 #define IOC_IOC25_PORTCFG_ANA 0x00000006U 3951 #define IOC_IOC25_PORTCFG_PFUNC5 0x00000005U 3952 #define IOC_IOC25_PORTCFG_PFUNC4 0x00000004U 3953 #define IOC_IOC25_PORTCFG_PFUNC3 0x00000003U 3954 #define IOC_IOC25_PORTCFG_PFUNC2 0x00000002U 3955 #define IOC_IOC25_PORTCFG_PFUNC1 0x00000001U 3956 #define IOC_IOC25_PORTCFG_BASE 0x00000000U 3957 3958 //***************************************************************************** 3959 // 3960 // Register: IOC_O_DTBCFG 3961 // 3962 //***************************************************************************** 3963 // Field: [23] DTB0DIV 3964 // 3965 // This bit is used to divide DTB[0] output by 8. 3966 // ENUMs: 3967 // EN Divide DTB[0] output by 8 3968 // DIS No divide 3969 #define IOC_DTBCFG_DTB0DIV 0x00800000U 3970 #define IOC_DTBCFG_DTB0DIV_M 0x00800000U 3971 #define IOC_DTBCFG_DTB0DIV_S 23U 3972 #define IOC_DTBCFG_DTB0DIV_EN 0x00800000U 3973 #define IOC_DTBCFG_DTB0DIV_DIS 0x00000000U 3974 3975 // Field: [18:16] PADSEL 3976 // 3977 // Selects which 3 DTB lines out of total 16 are routed to DTB pins 15 to 13. 3978 // ENUMs: 3979 // DTB2TO0 DTB[2:0] selected 3980 // DTB5TO3 DTB[5:3] selected 3981 // DTB8TO6 DTB[8:6] selected 3982 // DTB11TO9 DTB[11:9] selected 3983 // DTB14TO12 DTB[14:12] selected 3984 // DTB15TO13 DTB[15:13] selected 3985 #define IOC_DTBCFG_PADSEL_W 3U 3986 #define IOC_DTBCFG_PADSEL_M 0x00070000U 3987 #define IOC_DTBCFG_PADSEL_S 16U 3988 #define IOC_DTBCFG_PADSEL_DTB2TO0 0x00050000U 3989 #define IOC_DTBCFG_PADSEL_DTB5TO3 0x00040000U 3990 #define IOC_DTBCFG_PADSEL_DTB8TO6 0x00030000U 3991 #define IOC_DTBCFG_PADSEL_DTB11TO9 0x00020000U 3992 #define IOC_DTBCFG_PADSEL_DTB14TO12 0x00010000U 3993 #define IOC_DTBCFG_PADSEL_DTB15TO13 0x00000000U 3994 3995 // Field: [12:8] ULLSEL 3996 // 3997 // ULL DTB Mux selection 3998 #define IOC_DTBCFG_ULLSEL_W 5U 3999 #define IOC_DTBCFG_ULLSEL_M 0x00001F00U 4000 #define IOC_DTBCFG_ULLSEL_S 8U 4001 4002 // Field: [4:0] SVTSEL 4003 // 4004 // SVT DTB Mux selection 4005 #define IOC_DTBCFG_SVTSEL_W 5U 4006 #define IOC_DTBCFG_SVTSEL_M 0x0000001FU 4007 #define IOC_DTBCFG_SVTSEL_S 0U 4008 4009 //***************************************************************************** 4010 // 4011 // Register: IOC_O_DTBOE 4012 // 4013 //***************************************************************************** 4014 // Field: [15] EN15 4015 // 4016 // Enables DTB output 15 4017 // ENUMs: 4018 // EN DTB output enabled 4019 // DIS DTB output disabled 4020 #define IOC_DTBOE_EN15 0x00008000U 4021 #define IOC_DTBOE_EN15_M 0x00008000U 4022 #define IOC_DTBOE_EN15_S 15U 4023 #define IOC_DTBOE_EN15_EN 0x00008000U 4024 #define IOC_DTBOE_EN15_DIS 0x00000000U 4025 4026 // Field: [14] EN14 4027 // 4028 // Enables DTB output 14 4029 // ENUMs: 4030 // EN DTB output enabled 4031 // DIS DTB output disabled 4032 #define IOC_DTBOE_EN14 0x00004000U 4033 #define IOC_DTBOE_EN14_M 0x00004000U 4034 #define IOC_DTBOE_EN14_S 14U 4035 #define IOC_DTBOE_EN14_EN 0x00004000U 4036 #define IOC_DTBOE_EN14_DIS 0x00000000U 4037 4038 // Field: [13] EN13 4039 // 4040 // Enables DTB output 13 4041 // ENUMs: 4042 // EN DTB output enabled 4043 // DIS DTB output disabled 4044 #define IOC_DTBOE_EN13 0x00002000U 4045 #define IOC_DTBOE_EN13_M 0x00002000U 4046 #define IOC_DTBOE_EN13_S 13U 4047 #define IOC_DTBOE_EN13_EN 0x00002000U 4048 #define IOC_DTBOE_EN13_DIS 0x00000000U 4049 4050 // Field: [12] EN12 4051 // 4052 // Enables DTB output 12 4053 // ENUMs: 4054 // EN DTB output enabled 4055 // DIS DTB output disabled 4056 #define IOC_DTBOE_EN12 0x00001000U 4057 #define IOC_DTBOE_EN12_M 0x00001000U 4058 #define IOC_DTBOE_EN12_S 12U 4059 #define IOC_DTBOE_EN12_EN 0x00001000U 4060 #define IOC_DTBOE_EN12_DIS 0x00000000U 4061 4062 // Field: [11] EN11 4063 // 4064 // Enables DTB output 11 4065 // ENUMs: 4066 // EN DTB output enabled 4067 // DIS DTB output disabled 4068 #define IOC_DTBOE_EN11 0x00000800U 4069 #define IOC_DTBOE_EN11_M 0x00000800U 4070 #define IOC_DTBOE_EN11_S 11U 4071 #define IOC_DTBOE_EN11_EN 0x00000800U 4072 #define IOC_DTBOE_EN11_DIS 0x00000000U 4073 4074 // Field: [10] EN10 4075 // 4076 // Enables DTB output 10 4077 // ENUMs: 4078 // EN DTB output enabled 4079 // DIS DTB output disabled 4080 #define IOC_DTBOE_EN10 0x00000400U 4081 #define IOC_DTBOE_EN10_M 0x00000400U 4082 #define IOC_DTBOE_EN10_S 10U 4083 #define IOC_DTBOE_EN10_EN 0x00000400U 4084 #define IOC_DTBOE_EN10_DIS 0x00000000U 4085 4086 // Field: [9] EN9 4087 // 4088 // Enables DTB output 9 4089 // ENUMs: 4090 // EN DTB output enabled 4091 // DIS DTB output disabled 4092 #define IOC_DTBOE_EN9 0x00000200U 4093 #define IOC_DTBOE_EN9_M 0x00000200U 4094 #define IOC_DTBOE_EN9_S 9U 4095 #define IOC_DTBOE_EN9_EN 0x00000200U 4096 #define IOC_DTBOE_EN9_DIS 0x00000000U 4097 4098 // Field: [8] EN8 4099 // 4100 // Enables DTB output 8 4101 // ENUMs: 4102 // EN DTB output enabled 4103 // DIS DTB output disabled 4104 #define IOC_DTBOE_EN8 0x00000100U 4105 #define IOC_DTBOE_EN8_M 0x00000100U 4106 #define IOC_DTBOE_EN8_S 8U 4107 #define IOC_DTBOE_EN8_EN 0x00000100U 4108 #define IOC_DTBOE_EN8_DIS 0x00000000U 4109 4110 // Field: [7] EN7 4111 // 4112 // Enables DTB output 7 4113 // ENUMs: 4114 // EN DTB output enabled 4115 // DIS DTB output disabled 4116 #define IOC_DTBOE_EN7 0x00000080U 4117 #define IOC_DTBOE_EN7_M 0x00000080U 4118 #define IOC_DTBOE_EN7_S 7U 4119 #define IOC_DTBOE_EN7_EN 0x00000080U 4120 #define IOC_DTBOE_EN7_DIS 0x00000000U 4121 4122 // Field: [6] EN6 4123 // 4124 // Enables DTB output 6 4125 // ENUMs: 4126 // EN DTB output enabled 4127 // DIS DTB output disabled 4128 #define IOC_DTBOE_EN6 0x00000040U 4129 #define IOC_DTBOE_EN6_M 0x00000040U 4130 #define IOC_DTBOE_EN6_S 6U 4131 #define IOC_DTBOE_EN6_EN 0x00000040U 4132 #define IOC_DTBOE_EN6_DIS 0x00000000U 4133 4134 // Field: [5] EN5 4135 // 4136 // Enables DTB output 5 4137 // ENUMs: 4138 // EN DTB output enabled 4139 // DIS DTB output disabled 4140 #define IOC_DTBOE_EN5 0x00000020U 4141 #define IOC_DTBOE_EN5_M 0x00000020U 4142 #define IOC_DTBOE_EN5_S 5U 4143 #define IOC_DTBOE_EN5_EN 0x00000020U 4144 #define IOC_DTBOE_EN5_DIS 0x00000000U 4145 4146 // Field: [4] EN4 4147 // 4148 // Enables DTB output 4 4149 // ENUMs: 4150 // EN DTB output enabled 4151 // DIS DTB output disabled 4152 #define IOC_DTBOE_EN4 0x00000010U 4153 #define IOC_DTBOE_EN4_M 0x00000010U 4154 #define IOC_DTBOE_EN4_S 4U 4155 #define IOC_DTBOE_EN4_EN 0x00000010U 4156 #define IOC_DTBOE_EN4_DIS 0x00000000U 4157 4158 // Field: [3] EN3 4159 // 4160 // Enables DTB output 3 4161 // ENUMs: 4162 // EN DTB output enabled 4163 // DIS DTB output disabled 4164 #define IOC_DTBOE_EN3 0x00000008U 4165 #define IOC_DTBOE_EN3_M 0x00000008U 4166 #define IOC_DTBOE_EN3_S 3U 4167 #define IOC_DTBOE_EN3_EN 0x00000008U 4168 #define IOC_DTBOE_EN3_DIS 0x00000000U 4169 4170 // Field: [2] EN2 4171 // 4172 // Enables DTB output 2 4173 // ENUMs: 4174 // EN DTB output enabled 4175 // DIS DTB output disabled 4176 #define IOC_DTBOE_EN2 0x00000004U 4177 #define IOC_DTBOE_EN2_M 0x00000004U 4178 #define IOC_DTBOE_EN2_S 2U 4179 #define IOC_DTBOE_EN2_EN 0x00000004U 4180 #define IOC_DTBOE_EN2_DIS 0x00000000U 4181 4182 // Field: [1] EN1 4183 // 4184 // Enables DTB output 1 4185 // ENUMs: 4186 // EN DTB output enabled 4187 // DIS DTB output disabled 4188 #define IOC_DTBOE_EN1 0x00000002U 4189 #define IOC_DTBOE_EN1_M 0x00000002U 4190 #define IOC_DTBOE_EN1_S 1U 4191 #define IOC_DTBOE_EN1_EN 0x00000002U 4192 #define IOC_DTBOE_EN1_DIS 0x00000000U 4193 4194 // Field: [0] EN0 4195 // 4196 // Enables DTB output 0 4197 // ENUMs: 4198 // EN DTB output enabled 4199 // DIS DTB output disabled 4200 #define IOC_DTBOE_EN0 0x00000001U 4201 #define IOC_DTBOE_EN0_M 0x00000001U 4202 #define IOC_DTBOE_EN0_S 0U 4203 #define IOC_DTBOE_EN0_EN 0x00000001U 4204 #define IOC_DTBOE_EN0_DIS 0x00000000U 4205 4206 //***************************************************************************** 4207 // 4208 // Register: IOC_O_EVTCFG 4209 // 4210 //***************************************************************************** 4211 // Field: [8] EVTIFG 4212 // 4213 // Event flag. It is set when edge is detected on selected DIO. 4214 // Note: The edge detector flop is cleared for the selected DIO when EVTIFG is 4215 // cleared by software. 4216 // ENUMs: 4217 // SET Set ULL event 4218 // CLR Clear ULL event 4219 #define IOC_EVTCFG_EVTIFG 0x00000100U 4220 #define IOC_EVTCFG_EVTIFG_M 0x00000100U 4221 #define IOC_EVTCFG_EVTIFG_S 8U 4222 #define IOC_EVTCFG_EVTIFG_SET 0x00000100U 4223 #define IOC_EVTCFG_EVTIFG_CLR 0x00000000U 4224 4225 // Field: [7] EVTEN 4226 // 4227 // Enables IOC to publish event on AON event fabric when EVTIFG is set. 4228 // ENUMs: 4229 // EN Enable 4230 // DIS Disable 4231 #define IOC_EVTCFG_EVTEN 0x00000080U 4232 #define IOC_EVTCFG_EVTEN_M 0x00000080U 4233 #define IOC_EVTCFG_EVTEN_S 7U 4234 #define IOC_EVTCFG_EVTEN_EN 0x00000080U 4235 #define IOC_EVTCFG_EVTEN_DIS 0x00000000U 4236 4237 // Field: [5:0] DIOSEL 4238 // 4239 // This is used to select DIO for event generation. For example, DIOSEL = 0x0 4240 // selects DIO0 and DIOSEL = 0x8 selects DIO8. 4241 #define IOC_EVTCFG_DIOSEL_W 6U 4242 #define IOC_EVTCFG_DIOSEL_M 0x0000003FU 4243 #define IOC_EVTCFG_DIOSEL_S 0U 4244 4245 //***************************************************************************** 4246 // 4247 // Register: IOC_O_TEST 4248 // 4249 //***************************************************************************** 4250 // Field: [0] SEL 4251 // 4252 // This is used to drive SWDIO (Serial Wire DIO) output data and output enable 4253 // from debug sub-system onto DIO12 (Test Data Output) pad. 4254 // ENUMs: 4255 // HI Output data and output enable driven based on 4256 // debug sub-system inputs 4257 // LO Output data and output enable managed by IOC 4258 #define IOC_TEST_SEL 0x00000001U 4259 #define IOC_TEST_SEL_M 0x00000001U 4260 #define IOC_TEST_SEL_S 0U 4261 #define IOC_TEST_SEL_HI 0x00000001U 4262 #define IOC_TEST_SEL_LO 0x00000000U 4263 4264 //***************************************************************************** 4265 // 4266 // Register: IOC_O_DTBSTAT 4267 // 4268 //***************************************************************************** 4269 // Field: [15:0] VAL 4270 // 4271 // This bit field captures the final 16-bit value of DTB signals provided from 4272 // IOC to device pins. 4273 #define IOC_DTBSTAT_VAL_W 16U 4274 #define IOC_DTBSTAT_VAL_M 0x0000FFFFU 4275 #define IOC_DTBSTAT_VAL_S 0U 4276 4277 4278 #endif // __IOC__ 4279
