1 /****************************************************************************** 2 * Filename: hw_ints_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_INTS_H__ 34 #define __HW_INTS_H__ 35 36 //***************************************************************************** 37 // 38 // The following are defines for the interrupt assignments. 39 // 40 //***************************************************************************** 41 #define INT_NMI_FAULT 2 // NMI Fault 42 #define INT_HARD_FAULT 3 // Hard Fault 43 #define INT_SVCALL 11 // Supervisor Call (SVCall) 44 #define INT_PENDSV 14 // Pending Service Call (PendSV) 45 #define INT_SYSTICK 15 // SysTick Interrupt from the System Timer 46 // in NVIC. 47 #define INT_CPUIRQ0 16 // IRQ0: Configurable source controlled by 48 // EVTSVT.CPUIRQ0SEL 49 #define INT_CPUIRQ1 17 // IRQ1: Configurable source controlled by 50 // EVTSVT.CPUIRQ1SEL 51 #define INT_CPUIRQ2 18 // IRQ2: Configurable source controlled by 52 // EVTSVT.CPUIRQ2SEL 53 #define INT_CPUIRQ3 19 // IRQ3: Configurable source controlled by 54 // EVTSVT.CPUIRQ3SEL 55 #define INT_CPUIRQ4 20 // IRQ4: Configurable source controlled by 56 // EVTSVT.CPUIRQ4SEL 57 #define INT_GPIO_COMB 21 // GPIO combined wake up interrupt, 58 // interrupt flags can be found here 59 // GPIO:MIS 60 #define INT_LRFD_IRQ0 22 // LRFD combined event, interrupt flags can 61 // be found here LRFDDBELL:MIS0 62 #define INT_LRFD_IRQ1 23 // LRFD combined event, interrupt flags can 63 // be found here LRFDDBELL:MIS1 64 #define INT_DMA_DONE_COMB 24 // DMA combined done interrupt, 65 // corresponding flags can be found here 66 // DMA:REQDONE 67 #define INT_AES_COMB 25 // AES accelerator combined interrupt 68 // request, interrupt flags can be found 69 // here AES:MIS 70 #define INT_SPI0_COMB 26 // SPI0 combined interrupt request, 71 // interrupt flags can be found here 72 // SPI0:MIS 73 #define INT_UART0_COMB 27 // UART0 combined interrupt, interrupt 74 // flags are found here UART0:MIS 75 #define INT_I2C0_IRQ 28 // Interrupt event from I2C0, interrupt 76 // flags can be found here I2C0:MIS 77 #define INT_LGPT0_COMB 29 // LGPT0 combined interrupt, interrupt 78 // flags are found here LGPT0:MIS 79 #define INT_LGPT1_COMB 30 // LGPT1 combined interrupt, interrupt 80 // flags are found here LGPT1:MIS 81 #define INT_ADC_COMB 31 // ADC combined interrupt request, 82 // interrupt flags can be found here 83 // ADC:MIS0 84 #define INT_CPUIRQ16 32 // IRQ16: Configurable source controlled by 85 // EVTSVT.CPUIRQ16SEL 86 #define INT_LGPT2_COMB 33 // LGPT2 combined interrupt, interrupt 87 // flags are found here LGPT2:MIS 88 #define INT_LGPT3_COMB 34 // LGPT3 combined interrupt, interrupt 89 // flags are found here LGPT3:MIS 90 91 //***************************************************************************** 92 // 93 // The following are defines for number of interrupts and priority levels. 94 // 95 //***************************************************************************** 96 #define INT_PRI_LEVEL0 0x00000000 // Priority level 0 value 97 #define INT_PRI_LEVEL1 0x00000040 // Priority level 1 value 98 #define INT_PRI_LEVEL2 0x00000080 // Priority level 2 value 99 #define INT_PRI_LEVEL3 0x000000C0 // Priority level 3 value 100 #define INT_PRIORITY_MASK 0x000000C0 // Priority level mask 101 #define NUM_INTERRUPTS 35 // Number of exceptions 102 #define NUM_PRIORITY 4 // Number of exception priority levels 103 #define NUM_PRIORITY_BITS 2 // Number of exception priority bits 104 105 #endif // __HW_INTS__ 106
