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Searched refs:I2C0_BASE (Results 1 – 7 of 7) sorted by relevance

/hal_ti-latest/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/
Di2c.h172 return(ui32Base == I2C0_BASE); in I2CBaseValid()
240 HWREG(I2C0_BASE + I2C_O_MCTRL) = ui32Cmd; in I2CMasterControl()
275 HWREG(I2C0_BASE + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; in I2CMasterSlaveAddrSet()
296 HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 1; in I2CMasterEnable()
299 HWREG(I2C0_BASE + I2C_O_MCTRL) = I2C_MCTRL_RUN; in I2CMasterEnable()
320 HWREG(I2C0_BASE + I2C_O_MCTRL) = 0; in I2CMasterDisable()
323 HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 0; in I2CMasterDisable()
347 if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSY) in I2CMasterBusy()
379 if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSBSY) in I2CMasterBusBusy()
408 return(HWREG(I2C0_BASE + I2C_O_MDR)); in I2CMasterDataGet()
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Di2c.c74 I2CMasterEnable(I2C0_BASE); in I2CMasterInitExpClk()
91 HWREG(I2C0_BASE + I2C_O_MTPR) = ui32TPR; in I2CMasterInitExpClk()
108 ui32Err = HWREG(I2C0_BASE + I2C_O_MSTAT); in I2CMasterErr()
/hal_ti-latest/simplelink_lpf3/source/ti/devices/cc23x0r5/inc/
Dhw_memmap.h65 #define I2C0_BASE 0x40038000 // I2C macro
/hal_ti-latest/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/inc/
Dhw_memmap.h54 #define I2C0_BASE 0x40002000 // I2C macro
/hal_ti-latest/simplelink/source/ti/devices/cc13x2_cc26x2/inc/
Dhw_memmap.h54 #define I2C0_BASE 0x40002000 // I2C macro
/hal_ti-latest/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/
Di2c.h143 return (base == I2C0_BASE); in I2CBaseValid()
/hal_ti-latest/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/
Di2c.h170 return(ui32Base == I2C0_BASE); in I2CBaseValid()