1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_GPIO_H__ 35 #define __HW_GPIO_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the GPIO register offsets. 40 // 41 //***************************************************************************** 42 #define GPIO_O_GPIO_DATA 0x00000000 // 0x4000 5000 0x4000 6000 0x4000 43 // 7000 0x4002 4000 GPIO Data 44 // (GPIODATA)@@ offset 0x000 The 45 // GPIODATA register is the data 46 // register. In software control 47 // mode@@ values written in the 48 // GPIODATA register are transferred 49 // onto the GPIO port pins if the 50 // respective pins have been 51 // configured as outputs through the 52 // GPIO Direction (GPIODIR) register 53 // (see page 653). In order to write 54 // to GPIODATA@@ the corresponding 55 // bits in the mask@@ resulting from 56 // the address bus bits [9:2]@@ must 57 // be set. Otherwise@@ the bit 58 // values remain unchanged by the 59 // write. Similarly@@ the values 60 // read from this register are 61 // determined for each bit by the 62 // mask bit derived from the address 63 // used to access the data 64 // register@@ bits [9:2]. Bits that 65 // are set in the address mask cause 66 // the corresponding bits in 67 // GPIODATA to be read@@ and bits 68 // that are clear in the address 69 // mask cause the corresponding bits 70 // in GPIODATA to be read as 0@@ 71 // regardless of their value. A read 72 // from GPIODATA returns the last 73 // bit value written if the 74 // respective pins are configured as 75 // outputs@@ or it returns the value 76 // on the corresponding input pin 77 // when these are configured as 78 // inputs. All bits are cleared by a 79 // reset. 80 #define GPIO_O_GPIO_DIR 0x00000400 // 0x4000 5400 0x4000 6400 0x4000 81 // 7400 0x4002 4400 GPIO Direction 82 // (GPIODIR)@@ offset 0x400 The 83 // GPIODIR register is the data 84 // direction register. Setting a bit 85 // in the GPIODIR register 86 // configures the corresponding pin 87 // to be an output@@ while clearing 88 // a bit configures the 89 // corresponding pin to be an input. 90 // All bits are cleared by a reset@@ 91 // meaning all GPIO pins are inputs 92 // by default. 93 #define GPIO_O_GPIO_IS 0x00000404 // 0x4000 5404 0x4000 6404 0x4000 94 // 7404 0x4002 4404 GPIO Interrupt 95 // Sense (GPIOIS)@@ offset 0x404 The 96 // GPIOIS register is the interrupt 97 // sense register. Setting a bit in 98 // the GPIOIS register configures 99 // the corresponding pin to detect 100 // levels@@ while clearing a bit 101 // configures the corresponding pin 102 // to detect edges. All bits are 103 // cleared by a reset. 104 #define GPIO_O_GPIO_IBE 0x00000408 // 0x4000 5408 0x4000 6408 0x4000 105 // 7408 0x4002 4408 GPIO Interrupt 106 // Both Edges (GPIOIBE)@@ offset 107 // 0x408 The GPIOIBE register allows 108 // both edges to cause interrupts. 109 // When the corresponding bit in the 110 // GPIO Interrupt Sense (GPIOIS) 111 // register is set to detect edges@@ 112 // setting a bit in the GPIOIBE 113 // register configures the 114 // corresponding pin to detect both 115 // rising and falling edges@@ 116 // regardless of the corresponding 117 // bit in the GPIO Interrupt Event 118 // (GPIOIEV) register . Clearing a 119 // bit configures the pin to be 120 // controlled by the GPIOIEV 121 // register. All bits are cleared by 122 // a reset. 123 #define GPIO_O_GPIO_IEV 0x0000040C // 0x4000 540C 0x4000 640C 0x4000 124 // 740C 0x4002 440C GPIO Interrupt 125 // Event (GPIOIEV)@@ offset 0x40C 126 // The GPIOIEV register is the 127 // interrupt event register. Setting 128 // a bit in the GPIOIEV register 129 // configures the corresponding pin 130 // to detect rising edges or high 131 // levels@@ depending on the 132 // corresponding bit value in the 133 // GPIO Interrupt Sense (GPIOIS) 134 // register . Clearing a bit 135 // configures the pin to detect 136 // falling edges or low levels@@ 137 // depending on the corresponding 138 // bit value in the GPIOIS register. 139 // All bits are cleared by a reset. 140 #define GPIO_O_GPIO_IM 0x00000410 // 0x4000 5410 0x4000 6410 0x4000 141 // 7410 0x4002 4410 GPIO Interrupt 142 // Mask (GPIOIM)@@ offset 0x410 The 143 // GPIOIM register is the interrupt 144 // mask register. Setting a bit in 145 // the GPIOIM register allows 146 // interrupts that are generated by 147 // the corresponding pin to be sent 148 // to the interrupt controller on 149 // the combined interrupt signal. 150 // Clearing a bit prevents an 151 // interrupt on the corresponding 152 // pin from being sent to the 153 // interrupt controller. All bits 154 // are cleared by a reset. 155 #define GPIO_O_GPIO_RIS 0x00000414 // 0x4000 5414 0x4000 6414 0x4000 156 // 7414 0x4002 4414 GPIO Raw 157 // Interrupt Status (GPIORIS)@@ 158 // offset 0x414 The GPIORIS register 159 // is the raw interrupt status 160 // register. A bit in this register 161 // is set when an interrupt 162 // condition occurs on the 163 // corresponding GPIO pin. If the 164 // corresponding bit in the GPIO 165 // Interrupt Mask (GPIOIM) register 166 // is set@@ the interrupt is sent to 167 // the interrupt controller. Bits 168 // read as zero indicate that 169 // corresponding input pins have not 170 // initiated an interrupt. A bit in 171 // this register can be cleared by 172 // writing a 1 to the corresponding 173 // bit in the GPIO Interrupt Clear 174 // (GPIOICR) register. 175 #define GPIO_O_GPIO_MIS 0x00000418 // 0x4000 5418 0x4000 6418 0x4000 176 // 7418 0x4002 4418 GPIO Masked 177 // Interrupt Status (GPIOMIS)@@ 178 // offset 0x418 The GPIOMIS register 179 // is the masked interrupt status 180 // register. If a bit is set in this 181 // register@@ the corresponding 182 // interrupt has triggered an 183 // interrupt to the interrupt 184 // controller. If a bit is clear@@ 185 // either no interrupt has been 186 // generated@@ or the interrupt is 187 // masked. If no port pin@@ other 188 // than the one that is being used 189 // as an ADC trigger@@ is being used 190 // to generate interrupts@@ the 191 // appropriate Interrupt Set Enable 192 // (ENn) register can disable the 193 // interrupts for the port@@ and the 194 // ADC interrupt can be used to read 195 // back the converted data. 196 // Otherwise@@ the port interrupt 197 // handler must ignore and clear 198 // interrupts on the port pin and 199 // wait for the ADC interrupt@@ or 200 // the ADC interrupt must be 201 // disabled in the EN0 register and 202 // the port interrupt handler must 203 // poll the ADC registers until the 204 // conversion is completed. If no 205 // port pin@@ other than the one 206 // that is being used as an ADC 207 // trigger@@ is being used to 208 // generate interrupts@@ the 209 // appropriate Interrupt Set Enable 210 // (ENn) register can disable the 211 // interrupts for the port@@ and the 212 // ADC interrupt can be used to read 213 // back the converted data. 214 // Otherwise@@ the port interrupt 215 // handler must ignore and clear 216 // interrupts on the port pin and 217 // wait for the ADC interrupt@@ or 218 // the ADC interrupt must be 219 // disabled in the EN0 register and 220 // the port interrupt handler must 221 // poll the ADC registers until the 222 // conversion is completed. Note 223 // that if the Port B GPIOADCCTL 224 // register is cleared@@ PB4 can 225 // still be used as an external 226 // trigger for the ADC. This is a 227 // legacy mode which allows code 228 // written for previous Stellaris 229 // devices to operate on this 230 // microcontroller. GPIOMIS is the 231 // state of the interrupt after 232 // masking. 233 #define GPIO_O_GPIO_ICR 0x0000041C // 0x4000 541C 0x4000 641C 0x4000 234 // 741C 0x4002 441C GPIO Interrupt 235 // Clear (GPIOICR)@@ offset 0x41C 236 // The GPIOICR register is the 237 // interrupt clear register. Writing 238 // a 1 to a bit in this register 239 // clears the corresponding 240 // interrupt bit in the GPIORIS and 241 // GPIOMIS registers. Writing a 0 242 // has no effect. 243 #define GPIO_O_GPIO_AFSEL 0x00000420 // 0x4000 5420 0x4000 6420 0x4000 244 // 7420 0x4002 4420 GPIO Alternate 245 // Function Select (GPIOAFSEL)@@ 246 // offset 0x420 The GPIOAFSEL 247 // register is the mode control 248 // select register. If a bit is 249 // clear@@ the pin is used as a GPIO 250 // and is controlled by the GPIO 251 // registers. Setting a bit in this 252 // register configures the 253 // corresponding GPIO line to be 254 // controlled by an associated 255 // peripheral. Several possible 256 // peripheral functions are 257 // multiplexed on each GPIO. The 258 // GPIO Port Control (GPIOPCTL) 259 // register is used to select one of 260 // the possible functions. 261 #define GPIO_O_GPIO_DR2R 0x00000500 // 0x4000 5500 0x4000 6500 0x4000 262 // 7500 0x4002 4500 GPIO 2-mA Drive 263 // Select (GPIODR2R)@@ offset 0x500 264 // The GPIODR2R register is the 2-mA 265 // drive control register. Each GPIO 266 // signal in the port can be 267 // individually configured without 268 // affecting the other pads. When 269 // setting the DRV2 bit for a GPIO 270 // signal@@ the corresponding DRV4 271 // bit in the GPIODR4R register and 272 // DRV8 bit in the GPIODR8R register 273 // are automatically cleared by 274 // hardware. By default@@ all GPIO 275 // pins have 2-mA drive. 276 #define GPIO_O_GPIO_DR4R 0x00000504 // 0x4000 5504 0x4000 6504 0x4000 277 // 7504 0x4002 4504 GPIO 4-mA Drive 278 // Select (GPIODR4R)@@ offset 0x504 279 // The GPIODR4R register is the 4-mA 280 // drive control register. Each GPIO 281 // signal in the port can be 282 // individually configured without 283 // affecting the other pads. When 284 // setting the DRV4 bit for a GPIO 285 // signal@@ the corresponding DRV2 286 // bit in the GPIODR2R register and 287 // DRV8 bit in the GPIODR8R register 288 // are automatically cleared by 289 // hardware. 290 #define GPIO_O_GPIO_DR8R 0x00000508 // 0x4000 5508 0x4000 6508 0x4000 291 // 7508 0x4002 4508 GPIO 8-mA Drive 292 // Select (GPIODR8R)@@ offset 0x508 293 // The GPIODR8R register is the 8-mA 294 // drive control register. Each GPIO 295 // signal in the port can be 296 // individually configured without 297 // affecting the other pads. When 298 // setting the DRV8 bit for a GPIO 299 // signal@@ the corresponding DRV2 300 // bit in the GPIODR2R register and 301 // DRV4 bit in the GPIODR4R register 302 // are automatically cleared by 303 // hardware. The 8-mA setting is 304 // also used for high-current 305 // operation. Note: There is no 306 // configuration difference between 307 // 8-mA and high-current operation. 308 // The additional current capacity 309 // results from a shift in the 310 // VOH/VOL levels. 311 #define GPIO_O_GPIO_ODR 0x0000050C // 0x4000 550C 0x4000 650C 0x4000 312 // 750C 0x4002 450C GPIO Open Drain 313 // Select (GPIOODR)@@ offset 0x50C 314 // The GPIOODR register is the open 315 // drain control register. Setting a 316 // bit in this register enables the 317 // open-drain configuration of the 318 // corresponding GPIO pad. When 319 // open-drain mode is enabled@@ the 320 // corresponding bit should also be 321 // set in the GPIO Digital Input 322 // Enable (GPIODEN) register . 323 // Corresponding bits in the drive 324 // strength and slew rate control 325 // registers (GPIODR2R@@ GPIODR4R@@ 326 // GPIODR8R@@ and GPIOSLR) can be 327 // set to achieve the desired rise 328 // and fall times. The GPIO acts as 329 // an open-drain input if the 330 // corresponding bit in the GPIODIR 331 // register is cleared. If open 332 // drain is selected while the GPIO 333 // is configured as an input@@ the 334 // GPIO will remain an input and the 335 // open-drain selection has no 336 // effect until the GPIO is changed 337 // to an output. When using the I2C 338 // module@@ in addition to 339 // configuring the pin to open 340 // drain@@ the GPIO Alternate 341 // Function Select (GPIOAFSEL) 342 // register bits for the I2C clock 343 // and data pins should be set 344 #define GPIO_O_GPIO_PUR 0x00000510 // 0x4000 5510 0x4000 6510 0x4000 345 // 7510 0x4002 4510 GPIO Pull-Up 346 // Select (GPIOPUR)@@ offset 0x510 347 // The GPIOPUR register is the 348 // pull-up control register. When a 349 // bit is set@@ a weak pull-up 350 // resistor on the corresponding 351 // GPIO signal is enabled. Setting a 352 // bit in GPIOPUR automatically 353 // clears the corresponding bit in 354 // the GPIO Pull-Down Select 355 // (GPIOPDR) register . Write access 356 // to this register is protected 357 // with the GPIOCR register. Bits in 358 // GPIOCR that are cleared prevent 359 // writes to the equivalent bit in 360 // this register. 361 #define GPIO_O_GPIO_PDR 0x00000514 // 0x4000 5514 0x4000 6514 0x4000 362 // 7514 0x4002 4514 GPIO Pull-Down 363 // Select (GPIOPDR)@@ offset 0x514 364 // The GPIOPDR register is the 365 // pull-down control register. When 366 // a bit is set@@ a weak pull-down 367 // resistor on the corresponding 368 // GPIO signal is enabled. Setting a 369 // bit in GPIOPDR automatically 370 // clears the corresponding bit in 371 // the GPIO Pull-Up Select (GPIOPUR) 372 // register 373 #define GPIO_O_GPIO_SLR 0x00000518 // 0x4000 5518 0x4000 6518 0x4000 374 // 7518 0x4002 4518 The GPIOSLR 375 // register is the slew rate control 376 // register. Slew rate control is 377 // only available when using the 378 // 8-mA drive strength option via 379 // the GPIO 8-mA Drive Select 380 // (GPIODR8R) register 381 #define GPIO_O_GPIO_DEN 0x0000051C // 0x4000 551C 0x4000 651C 0x4000 382 // 751C 0x4002 451C GPIO Digital 383 // Enable (GPIODEN)@@ offset 0x51C 384 // Note: Pins configured as digital 385 // inputs are Schmitt-triggered. The 386 // GPIODEN register is the digital 387 // enable register. By default@@ all 388 // GPIO signals except those listed 389 // below are configured out of reset 390 // to be undriven (tristate). Their 391 // digital function is disabled; 392 // they do not drive a logic value 393 // on the pin and they do not allow 394 // the pin voltage into the GPIO 395 // receiver. To use the pin as a 396 // digital input or output (either 397 // GPIO or alternate function)@@ the 398 // corresponding GPIODEN bit must be 399 // set. 400 #define GPIO_O_GPIO_LOCK 0x00000520 // 0x4000 5520 0x4000 6520 0x4000 401 // 7520 0x4002 4520 GPIO Lock 402 // (GPIOLOCK)@@ offset 0x520 The 403 // GPIOLOCK register enables write 404 // access to the GPIOCR register . 405 // Writing 0x4C4F.434B to the 406 // GPIOLOCK register unlocks the 407 // GPIOCR register. Writing any 408 // other value to the GPIOLOCK 409 // register re-enables the locked 410 // state. Reading the GPIOLOCK 411 // register returns the lock status 412 // rather than the 32-bit value that 413 // was previously written. 414 // Therefore@@ when write accesses 415 // are disabled@@ or locked@@ 416 // reading the GPIOLOCK register 417 // returns 0x0000.0001. When write 418 // accesses are enabled@@ or 419 // unlocked@@ reading the GPIOLOCK 420 // register returns 0x0000.0000. 421 #define GPIO_O_GPIO_CR 0x00000524 // 0x4000 5524 0x4000 6524 0x4000 422 // 7524 0x4002 4524 GPIO Commit 423 // (GPIOCR)@@ offset 0x524 The 424 // GPIOCR register is the commit 425 // register. The value of the GPIOCR 426 // register determines which bits of 427 // the GPIOAFSEL@@ GPIOPUR@@ 428 // GPIOPDR@@ and GPIODEN registers 429 // are committed when a write to 430 // these registers is performed. If 431 // a bit in the GPIOCR register is 432 // cleared@@ the data being written 433 // to the corresponding bit in the 434 // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ 435 // or GPIODEN registers cannot be 436 // committed and retains its 437 // previous value. If a bit in the 438 // GPIOCR register is set@@ the data 439 // being written to the 440 // corresponding bit of the 441 // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ 442 // or GPIODEN registers is committed 443 // to the register and reflects the 444 // new value. The contents of the 445 // GPIOCR register can only be 446 // modified if the status in the 447 // GPIOLOCK register is unlocked. 448 // Writes to the GPIOCR register are 449 // ignored if the status in the 450 // GPIOLOCK register is locked. 451 #define GPIO_O_GPIO_AMSEL 0x00000528 // 0x4000 5528 0x4000 6528 0x4000 452 // 7528 0x4002 4528 The GPIOAMSEL 453 // register controls isolation 454 // circuits to the analog side of a 455 // unified I/O pad. Because the 456 // GPIOs may be driven by a 5-V 457 // source and affect analog 458 // operation@@ analog circuitry 459 // requires isolation from the pins 460 // when they are not used in their 461 // analog function. Each bit of this 462 // register controls the isolation 463 // circuitry for the corresponding 464 // GPIO signal. 465 #define GPIO_O_GPIO_PCTL 0x0000052C // This register is not used in 466 // cc3xx. equivalant register exsist 467 // outside GPIO IP (refer 468 // PAD*_config register in the 469 // shared comn space) 0x4000 552C 470 // 0x4000 652C 0x4000 752C 0x4002 471 // 452C GPIO Port Control 472 // (GPIOPCTL)@@ offset 0x52C The 473 // GPIOPCTL register is used in 474 // conjunction with the GPIOAFSEL 475 // register and selects the specific 476 // peripheral signal for each GPIO 477 // pin when using the alternate 478 // function mode. Most bits in the 479 // GPIOAFSEL register are cleared on 480 // reset@@ therefore most GPIO pins 481 // are configured as GPIOs by 482 // default. When a bit is set in the 483 // GPIOAFSEL register@@ the 484 // corresponding GPIO signal is 485 // controlled by an associated 486 // peripheral. The GPIOPCTL register 487 // selects one out of a set of 488 // peripheral functions for each 489 // GPIO@@ providing additional 490 // flexibility in signal definition. 491 #define GPIO_O_GPIO_ADCCTL 0x00000530 // This register is not used in 492 // cc3xx. ADC trigger via GPIO is 493 // not supported. 0x4000 5530 0x4000 494 // 6530 0x4000 7530 0x4002 4530 GPIO 495 // ADC Control (GPIOADCCTL)@@ offset 496 // 0x530 This register is used to 497 // configure a GPIO pin as a source 498 // for the ADC trigger. Note that if 499 // the Port B GPIOADCCTL register is 500 // cleared@@ PB4 can still be used 501 // as an external trigger for the 502 // ADC. This is a legacy mode which 503 // allows code written for previous 504 // Stellaris devices to operate on 505 // this microcontroller. 506 #define GPIO_O_GPIO_DMACTL 0x00000534 // 0x4000 5534 0x4000 6534 0x4000 507 // 7534 0x4002 4534 GPIO DMA Control 508 // (GPIODMACTL)@@ offset 0x534 This 509 // register is used to configure a 510 // GPIO pin as a source for the ?DMA 511 // trigger. 512 #define GPIO_O_GPIO_SI 0x00000538 // 0x4000 5538 0x4000 6538 0x4000 513 // 7538 0x4002 4538 GPIO Select 514 // Interrupt (GPIOSI)@@ offset 0x538 515 // This register is used to enable 516 // individual interrupts for each 517 // pin. Note: This register is only 518 // available on Port P and Port Q. 519 #define GPIO_O_GPIO_PERIPHID4 0x00000FD0 // 0x4000 5FD0 0x4000 6FD0 0x4000 520 // 7FD0 0x4002 4FD0 GPIO Peripheral 521 // Identification 4 522 // (GPIOPeriphID4)@@ offset 0xFD0 523 // The GPIOPeriphID4@@ 524 // GPIOPeriphID5@@ GPIOPeriphID6@@ 525 // and GPIOPeriphID7 registers can 526 // conceptually be treated as one 527 // 32-bit register; each register 528 // contains eight bits of the 32-bit 529 // register@@ used by software to 530 // identify the peripheral. 531 #define GPIO_O_GPIO_PERIPHID5 0x00000FD4 // 0x4000 5FD4 0x4000 6FD4 0x4000 532 // 7FD4 0x4002 4FD4 GPIO Peripheral 533 // Identification 5 534 // (GPIOPeriphID5)@@ offset 0xFD4 535 // The GPIOPeriphID4@@ 536 // GPIOPeriphID5@@ GPIOPeriphID6@@ 537 // and GPIOPeriphID7 registers can 538 // conceptually be treated as one 539 // 32-bit register; each register 540 // contains eight bits of the 32-bit 541 // register@@ used by software to 542 // identify the peripheral. 543 #define GPIO_O_GPIO_PERIPHID6 0x00000FD8 // 0x4000 5FD8 0x4000 6FD8 0x4000 544 // 7FD8 0x4002 4FD8 GPIO Peripheral 545 // Identification 6 546 // (GPIOPeriphID6)@@ offset 0xFD8 547 // The GPIOPeriphID4@@ 548 // GPIOPeriphID5@@ GPIOPeriphID6@@ 549 // and GPIOPeriphID7 registers can 550 // conceptually be treated as one 551 // 32-bit register; each register 552 // contains eight bits of the 32-bit 553 // register@@ used by software to 554 // identify the peripheral. 555 #define GPIO_O_GPIO_PERIPHID7 0x00000FDC // 0x4000 5FDC 0x4000 6FDC 0x4000 556 // 7FDC 0x4002 4FDC GPIO Peripheral 557 // Identification 7 558 // (GPIOPeriphID7)@@ offset 0xFDC 559 // The GPIOPeriphID4@@ 560 // GPIOPeriphID5@@ GPIOPeriphID6@@ 561 // and GPIOPeriphID7 registers can 562 // conceptually be treated as one 563 // 32-bit register; each register 564 // contains eight bits of the 32-bit 565 // register@@ used by software to 566 // identify the peripheral. 567 #define GPIO_O_GPIO_PERIPHID0 0x00000FE0 // 0x4000 5FE0 0x4000 6FE0 0x4000 568 // 7FE0 0x4002 4FE0 GPIO Peripheral 569 // Identification 0 570 // (GPIOPeriphID0)@@ offset 0xFE0 571 // The GPIOPeriphID0@@ 572 // GPIOPeriphID1@@ GPIOPeriphID2@@ 573 // and GPIOPeriphID3 registers can 574 // conceptually be treated as one 575 // 32-bit register; each register 576 // contains eight bits of the 32-bit 577 // register@@ used by software to 578 // identify the peripheral. 579 #define GPIO_O_GPIO_PERIPHID1 0x00000FE4 // 0x4000 5FE4 0x4000 6FE4 0x4000 580 // 7FE4 0x4002 4FE4 GPIO Peripheral 581 // Identification 1 582 // (GPIOPeriphID1)@@ offset 0xFE4 583 // The GPIOPeriphID0@@ 584 // GPIOPeriphID1@@ GPIOPeriphID2@@ 585 // and GPIOPeriphID3 registers can 586 // conceptually be treated as one 587 // 32-bit register; each register 588 // contains eight bits of the 32-bit 589 // register@@ used by software to 590 // identify the peripheral. 591 #define GPIO_O_GPIO_PERIPHID2 0x00000FE8 // 0x4000 5FE8 0x4000 6FE8 0x4000 592 // 7FE8 0x4002 4FE8 GPIO Peripheral 593 // Identification 2 594 // (GPIOPeriphID2)@@ offset 0xFE8 595 // The GPIOPeriphID0@@ 596 // GPIOPeriphID1@@ GPIOPeriphID2@@ 597 // and GPIOPeriphID3 registers can 598 // conceptually be treated as one 599 // 32-bit register; each register 600 // contains eight bits of the 32-bit 601 // register@@ used by software to 602 // identify the peripheral. 603 #define GPIO_O_GPIO_PERIPHID3 0x00000FEC // 0x4000 5FEC 0x4000 6FEC 0x4000 604 // 7FEC 0x4002 4FEC GPIO Peripheral 605 // Identification 3 606 // (GPIOPeriphID3)@@ offset 0xFEC 607 // The GPIOPeriphID0@@ 608 // GPIOPeriphID1@@ GPIOPeriphID2@@ 609 // and GPIOPeriphID3 registers can 610 // conceptually be treated as one 611 // 32-bit register; each register 612 // contains eight bits of the 32-bit 613 // register@@ used by software to 614 // identify the peripheral. 615 #define GPIO_O_GPIO_PCELLID0 0x00000FF0 // 0x4000 5FF0 0x4000 6FF0 0x4000 616 // 7FF0 0x4002 4FF0 GPIO PrimeCell 617 // Identification 0 (GPIOPCellID0)@@ 618 // offset 0xFF0 The GPIOPCellID0@@ 619 // GPIOPCellID1@@ GPIOPCellID2@@ and 620 // GPIOPCellID3 registers are four 621 // 8-bit wide registers@@ that can 622 // conceptually be treated as one 623 // 32-bit register. The register is 624 // used as a standard 625 // cross-peripheral identification 626 // system. 627 #define GPIO_O_GPIO_PCELLID1 0x00000FF4 // 0x4000 5FF4 0x4000 6FF4 0x4000 628 // 7FF4 0x4002 4FF4 GPIO PrimeCell 629 // Identification 1 (GPIOPCellID1)@@ 630 // offset 0xFF4 The GPIOPCellID0@@ 631 // GPIOPCellID1@@ GPIOPCellID2@@ and 632 // GPIOPCellID3 registers are four 633 // 8-bit wide registers@@ that can 634 // conceptually be treated as one 635 // 32-bit register. The register is 636 // used as a standard 637 // cross-peripheral identification 638 // system. 639 #define GPIO_O_GPIO_PCELLID2 0x00000FF8 // 0x4000 5FF8 0x4000 6FF8 0x4000 640 // 7FF8 0x4002 4FF8 GPIO PrimeCell 641 // Identification 2 (GPIOPCellID2)@@ 642 // offset 0xFF8 The GPIOPCellID0@@ 643 // GPIOPCellID1@@ GPIOPCellID2@@ and 644 // GPIOPCellID3 registers are four 645 // 8-bit wide registers@@ that can 646 // conceptually be treated as one 647 // 32-bit register. The register is 648 // used as a standard 649 // cross-peripheral identification 650 // system. 651 #define GPIO_O_GPIO_PCELLID3 0x00000FFC // 0x4000 5FFC 0x4000 6FFC 0x4000 652 // 7FFC 0x4002 4FFC GPIO PrimeCell 653 // Identification 3 (GPIOPCellID3)@@ 654 // offset 0xFFC The GPIOPCellID0@@ 655 // GPIOPCellID1@@ GPIOPCellID2@@ and 656 // GPIOPCellID3 registers are four 657 // 8-bit wide registers@@ that can 658 // conceptually be treated as one 659 // 32-bit register. The register is 660 // used as a standard 661 // cross-peripheral identification 662 // system.0xb1 663 664 665 666 //****************************************************************************** 667 // 668 // The following are defines for the bit fields in the GPIO_O_GPIO_DATA register. 669 // 670 //****************************************************************************** 671 #define GPIO_GPIO_DATA_DATA_M 0x000000FF // GPIO Data This register is 672 // virtually mapped to 256 locations 673 // in the address space. To 674 // facilitate the reading and 675 // writing of data to these 676 // registers by independent 677 // drivers@@ the data read from and 678 // written to the registers are 679 // masked by the eight address lines 680 // [9:2]. Reads from this register 681 // return its current state. Writes 682 // to this register only affect bits 683 // that are not masked by ADDR[9:2] 684 // and are configured as outputs. 685 #define GPIO_GPIO_DATA_DATA_S 0 686 //****************************************************************************** 687 // 688 // The following are defines for the bit fields in the GPIO_O_GPIO_DIR register. 689 // 690 //****************************************************************************** 691 #define GPIO_GPIO_DIR_DIR_M 0x000000FF // GPIO Data Direction Value 692 // Description 0 Corresponding pin 693 // is an input. 1 Corresponding pins 694 // is an output. 695 #define GPIO_GPIO_DIR_DIR_S 0 696 //****************************************************************************** 697 // 698 // The following are defines for the bit fields in the GPIO_O_GPIO_IS register. 699 // 700 //****************************************************************************** 701 #define GPIO_GPIO_IS_IS_M 0x000000FF // GPIO Interrupt Sense Value 702 // Description 0 The edge on the 703 // corresponding pin is detected 704 // (edge-sensitive). 1 The level on 705 // the corresponding pin is detected 706 // (level-sensitive). 707 #define GPIO_GPIO_IS_IS_S 0 708 //****************************************************************************** 709 // 710 // The following are defines for the bit fields in the GPIO_O_GPIO_IBE register. 711 // 712 //****************************************************************************** 713 #define GPIO_GPIO_IBE_IBE_M 0x000000FF // GPIO Interrupt Both Edges Value 714 // Description 0 Interrupt 715 // generation is controlled by the 716 // GPIO Interrupt Event (GPIOIEV) 717 // register. 1 Both edges on the 718 // corresponding pin trigger an 719 // interrupt. 720 #define GPIO_GPIO_IBE_IBE_S 0 721 //****************************************************************************** 722 // 723 // The following are defines for the bit fields in the GPIO_O_GPIO_IEV register. 724 // 725 //****************************************************************************** 726 #define GPIO_GPIO_IEV_IEV_M 0x000000FF // GPIO Interrupt Event Value 727 // Description 1 A falling edge or a 728 // Low level on the corresponding 729 // pin triggers an interrupt. 0 A 730 // rising edge or a High level on 731 // the corresponding pin triggers an 732 // interrupt. 733 #define GPIO_GPIO_IEV_IEV_S 0 734 //****************************************************************************** 735 // 736 // The following are defines for the bit fields in the GPIO_O_GPIO_IM register. 737 // 738 //****************************************************************************** 739 #define GPIO_GPIO_IM_IME_M 0x000000FF // GPIO Interrupt Mask Enable Value 740 // Description 0 The interrupt from 741 // the corresponding pin is masked. 742 // 1 The interrupt from the 743 // corresponding pin is sent to the 744 // interrupt controller. 745 #define GPIO_GPIO_IM_IME_S 0 746 //****************************************************************************** 747 // 748 // The following are defines for the bit fields in the GPIO_O_GPIO_RIS register. 749 // 750 //****************************************************************************** 751 #define GPIO_GPIO_RIS_RIS_M 0x000000FF // GPIO Interrupt Raw Status Value 752 // Description 1 An interrupt 753 // condition has occurred on the 754 // corresponding pin. 0 interrupt 755 // condition has not occurred on the 756 // corresponding pin. A bit is 757 // cleared by writing a 1 to the 758 // corresponding bit in the GPIOICR 759 // register. 760 #define GPIO_GPIO_RIS_RIS_S 0 761 //****************************************************************************** 762 // 763 // The following are defines for the bit fields in the GPIO_O_GPIO_MIS register. 764 // 765 //****************************************************************************** 766 #define GPIO_GPIO_MIS_MIS_M 0x000000FF // GPIO Masked Interrupt Status 767 // Value Description 1 An interrupt 768 // condition on the corresponding 769 // pin has triggered an interrupt to 770 // the interrupt controller. 0 An 771 // interrupt condition on the 772 // corresponding pin is masked or 773 // has not occurred. A bit is 774 // cleared by writing a 1 to the 775 // corresponding bit in the GPIOICR 776 // register. 777 #define GPIO_GPIO_MIS_MIS_S 0 778 //****************************************************************************** 779 // 780 // The following are defines for the bit fields in the GPIO_O_GPIO_ICR register. 781 // 782 //****************************************************************************** 783 #define GPIO_GPIO_ICR_IC_M 0x000000FF // GPIO Interrupt Clear Value 784 // Description 1 The corresponding 785 // interrupt is cleared. 0 The 786 // corresponding interrupt is 787 // unaffected. 788 #define GPIO_GPIO_ICR_IC_S 0 789 //****************************************************************************** 790 // 791 // The following are defines for the bit fields in the GPIO_O_GPIO_AFSEL register. 792 // 793 //****************************************************************************** 794 //****************************************************************************** 795 // 796 // The following are defines for the bit fields in the GPIO_O_GPIO_DR2R register. 797 // 798 //****************************************************************************** 799 #define GPIO_GPIO_DR2R_DRV2_M 0x000000FF // This register is not used in 800 // cc3xx. equivalant register exsist 801 // outside GPIO IP (refer 802 // PAD*_config register in the 803 // shared comn space) Output Pad 804 // 2-mA Drive Enable Value 805 // Description 1 The corresponding 806 // GPIO pin has 2-mA drive. The 807 // drive for the corresponding GPIO 808 // pin is controlled by the GPIODR4R 809 // or GPIODR8R register. 0 Setting a 810 // bit in either the GPIODR4 811 // register or the GPIODR8 register 812 // clears the corresponding 2-mA 813 // enable bit. The change is 814 // effective on the second clock 815 // cycle after the write if 816 // accessing GPIO via the APB memory 817 // aperture. If using AHB access@@ 818 // the change is effective on the 819 // next clock cycle. 820 #define GPIO_GPIO_DR2R_DRV2_S 0 821 //****************************************************************************** 822 // 823 // The following are defines for the bit fields in the GPIO_O_GPIO_DR4R register. 824 // 825 //****************************************************************************** 826 #define GPIO_GPIO_DR4R_DRV4_M 0x000000FF // This register is not used in 827 // cc3xx. equivalant register exsist 828 // outside GPIO IP (refer 829 // PAD*_config register in the 830 // shared comn space) Output Pad 831 // 4-mA Drive Enable Value 832 // Description 1 The corresponding 833 // GPIO pin has 4-mA drive. The 834 // drive for the corresponding GPIO 835 // pin is controlled by the GPIODR2R 836 // or GPIODR8R register. 0 Setting a 837 // bit in either the GPIODR2 838 // register or the GPIODR8 register 839 // clears the corresponding 4-mA 840 // enable bit. The change is 841 // effective on the second clock 842 // cycle after the write if 843 // accessing GPIO via the APB memory 844 // aperture. If using AHB access@@ 845 // the change is effective on the 846 // next clock cycle. 847 #define GPIO_GPIO_DR4R_DRV4_S 0 848 //****************************************************************************** 849 // 850 // The following are defines for the bit fields in the GPIO_O_GPIO_DR8R register. 851 // 852 //****************************************************************************** 853 #define GPIO_GPIO_DR8R_DRV8_M 0x000000FF // This register is not used in 854 // cc3xx. equivalant register exsist 855 // outside GPIO IP (refer 856 // PAD*_config register in the 857 // shared comn space) Output Pad 858 // 8-mA Drive Enable Value 859 // Description 1 The corresponding 860 // GPIO pin has 8-mA drive. The 861 // drive for the corresponding GPIO 862 // pin is controlled by the GPIODR2R 863 // or GPIODR4R register. 0 Setting a 864 // bit in either the GPIODR2 865 // register or the GPIODR4 register 866 // clears the corresponding 8-mA 867 // enable bit. The change is 868 // effective on the second clock 869 // cycle after the write if 870 // accessing GPIO via the APB memory 871 // aperture. If using AHB access@@ 872 // the change is effective on the 873 // next clock cycle. 874 #define GPIO_GPIO_DR8R_DRV8_S 0 875 //****************************************************************************** 876 // 877 // The following are defines for the bit fields in the GPIO_O_GPIO_ODR register. 878 // 879 //****************************************************************************** 880 #define GPIO_GPIO_ODR_ODE_M 0x000000FF // This register is not used in 881 // cc3xx. equivalant register exsist 882 // outside GPIO IP (refer 883 // PAD*_config register in the 884 // shared comn space) Output Pad 885 // Open Drain Enable Value 886 // Description 1 The corresponding 887 // pin is configured as open drain. 888 // 0 The corresponding pin is not 889 // configured as open drain. 890 #define GPIO_GPIO_ODR_ODE_S 0 891 //****************************************************************************** 892 // 893 // The following are defines for the bit fields in the GPIO_O_GPIO_PUR register. 894 // 895 //****************************************************************************** 896 #define GPIO_GPIO_PUR_PUE_M 0x000000FF // This register is not used in 897 // cc3xx. equivalant register exsist 898 // outside GPIO IP (refer 899 // PAD*_config register in the 900 // shared comn space) Pad Weak 901 // Pull-Up Enable Value Description 902 // 1 The corresponding pin has a 903 // weak pull-up resistor. 0 The 904 // corresponding pin is not 905 // affected. Setting a bit in the 906 // GPIOPDR register clears the 907 // corresponding bit in the GPIOPUR 908 // register. The change is effective 909 // on the second clock cycle after 910 // the write if accessing GPIO via 911 // the APB memory aperture. If using 912 // AHB access@@ the change is 913 // effective on the next clock 914 // cycle. 915 #define GPIO_GPIO_PUR_PUE_S 0 916 //****************************************************************************** 917 // 918 // The following are defines for the bit fields in the GPIO_O_GPIO_PDR register. 919 // 920 //****************************************************************************** 921 #define GPIO_GPIO_PDR_PDE_M 0x000000FF // This register is not used in 922 // cc3xx. equivalant register exsist 923 // outside GPIO IP (refer 924 // PAD*_config register in the 925 // shared comn space) Pad Weak 926 // Pull-Down Enable Value 927 // Description 1 The corresponding 928 // pin has a weak pull-down 929 // resistor. 0 The corresponding pin 930 // is not affected. Setting a bit in 931 // the GPIOPUR register clears the 932 // corresponding bit in the GPIOPDR 933 // register. The change is effective 934 // on the second clock cycle after 935 // the write if accessing GPIO via 936 // the APB memory aperture. If using 937 // AHB access@@ the change is 938 // effective on the next clock 939 // cycle. 940 #define GPIO_GPIO_PDR_PDE_S 0 941 //****************************************************************************** 942 // 943 // The following are defines for the bit fields in the GPIO_O_GPIO_SLR register. 944 // 945 //****************************************************************************** 946 #define GPIO_GPIO_SLR_SRL_M 0x000000FF // This register is not used in 947 // cc3xx. equivalant register exsist 948 // outside GPIO IP (refer 949 // PAD*_config register in the 950 // shared comn space) Slew Rate 951 // Limit Enable (8-mA drive only) 952 // Value Description 1 Slew rate 953 // control is enabled for the 954 // corresponding pin. 0 Slew rate 955 // control is disabled for the 956 // corresponding pin. 957 #define GPIO_GPIO_SLR_SRL_S 0 958 //****************************************************************************** 959 // 960 // The following are defines for the bit fields in the GPIO_O_GPIO_DEN register. 961 // 962 //****************************************************************************** 963 #define GPIO_GPIO_DEN_DEN_M 0x000000FF // This register is not used in 964 // cc3xx. equivalant register exsist 965 // outside GPIO IP (refer 966 // PAD*_config register in the 967 // shared comn space) Digital Enable 968 // Value Description 0 The digital 969 // functions for the corresponding 970 // pin are disabled. 1 The digital 971 // functions for the corresponding 972 // pin are enabled. 973 #define GPIO_GPIO_DEN_DEN_S 0 974 //****************************************************************************** 975 // 976 // The following are defines for the bit fields in the GPIO_O_GPIO_LOCK register. 977 // 978 //****************************************************************************** 979 #define GPIO_GPIO_LOCK_LOCK_M 0xFFFFFFFF // This register is not used in 980 // cc3xx. GPIO Lock A write of the 981 // value 0x4C4F.434B unlocks the 982 // GPIO Commit (GPIOCR) register for 983 // write access.A write of any other 984 // value or a write to the GPIOCR 985 // register reapplies the lock@@ 986 // preventing any register updates. 987 // A read of this register returns 988 // the following values: Value 989 // Description 0x1 The GPIOCR 990 // register is locked and may not be 991 // modified. 0x0 The GPIOCR register 992 // is unlocked and may be modified. 993 #define GPIO_GPIO_LOCK_LOCK_S 0 994 //****************************************************************************** 995 // 996 // The following are defines for the bit fields in the GPIO_O_GPIO_CR register. 997 // 998 //****************************************************************************** 999 #define GPIO_GPIO_CR_CR_M 0x000000FF // This register is not used in 1000 // cc3xx. equivalant register exsist 1001 // outside GPIO IP (refer 1002 // PAD*_config register in the 1003 // shared comn space) GPIO Commit 1004 // Value Description The 1005 // corresponding GPIOAFSEL@@ 1006 // GPIOPUR@@ GPIOPDR@@ or GPIODEN 1007 // bits can be written. 1 The 1008 // corresponding GPIOAFSEL@@ 1009 // GPIOPUR@@ GPIOPDR@@ or GPIODEN 1010 // bits cannot be written. 0 Note: 1011 // The default register type for the 1012 // GPIOCR register is RO for all 1013 // GPIO pins with the exception of 1014 // the NMI pin and the four JTAG/SWD 1015 // pins (PD7@@ PF0@@ and PC[3:0]). 1016 // These six pins are the only GPIOs 1017 // that are protected by the GPIOCR 1018 // register. Because of this@@ the 1019 // register type for GPIO Port D7@@ 1020 // GPIO Port F0@@ and GPIO Port 1021 // C[3:0] is R/W. The default reset 1022 // value for the GPIOCR register is 1023 // 0x0000.00FF for all GPIO pins@@ 1024 // with the exception of the NMI pin 1025 // and the four JTAG/SWD pins (PD7@@ 1026 // PF0@@ and PC[3:0]). To ensure 1027 // that the JTAG port is not 1028 // accidentally programmed as GPIO 1029 // pins@@ the PC[3:0] pins default 1030 // to non-committable. Similarly@@ 1031 // to ensure that the NMI pin is not 1032 // accidentally programmed as a GPIO 1033 // pin@@ the PD7 and PF0 pins 1034 // default to non-committable. 1035 // Because of this@@ the default 1036 // reset value of GPIOCR for GPIO 1037 // Port C is 0x0000.00F0@@ for GPIO 1038 // Port D is 0x0000.007F@@ and for 1039 // GPIO Port F is 0x0000.00FE. 1040 #define GPIO_GPIO_CR_CR_S 0 1041 //****************************************************************************** 1042 // 1043 // The following are defines for the bit fields in the GPIO_O_GPIO_AMSEL register. 1044 // 1045 //****************************************************************************** 1046 #define GPIO_GPIO_AMSEL_GPIO_AMSEL_M \ 1047 0x000000FF // This register is not used in 1048 // cc3xx. equivalant register exsist 1049 // outside GPIO IP (refer 1050 // PAD*_config register in the 1051 // shared comn space) GPIO Analog 1052 // Mode Select Value Description 1 1053 // The analog function of the pin is 1054 // enabled@@ the isolation is 1055 // disabled@@ and the pin is capable 1056 // of analog functions. 0 The analog 1057 // function of the pin is disabled@@ 1058 // the isolation is enabled@@ and 1059 // the pin is capable of digital 1060 // functions as specified by the 1061 // other GPIO configuration 1062 // registers. Note: This register 1063 // and bits are only valid for GPIO 1064 // signals that share analog 1065 // function through a unified I/O 1066 // pad. The reset state of this 1067 // register is 0 for all signals. 1068 1069 #define GPIO_GPIO_AMSEL_GPIO_AMSEL_S 0 1070 //****************************************************************************** 1071 // 1072 // The following are defines for the bit fields in the GPIO_O_GPIO_PCTL register. 1073 // 1074 //****************************************************************************** 1075 #define GPIO_GPIO_PCTL_PMC7_M 0xF0000000 // This register is not used in 1076 // cc3xx. equivalant register exsist 1077 // outside GPIO IP (refer 1078 // PAD*_config register in the 1079 // shared comn space) Port Mux 1080 // Control 7 This field controls the 1081 // configuration for GPIO pin 7. 1082 #define GPIO_GPIO_PCTL_PMC7_S 28 1083 #define GPIO_GPIO_PCTL_PMC6_M 0x0F000000 // This register is not used in 1084 // cc3xx. equivalant register exsist 1085 // outside GPIO IP (refer 1086 // PAD*_config register in the 1087 // shared comn space) Port Mux 1088 // Control 6 This field controls the 1089 // configuration for GPIO pin 6. 1090 #define GPIO_GPIO_PCTL_PMC6_S 24 1091 #define GPIO_GPIO_PCTL_PMC5_M 0x00F00000 // This register is not used in 1092 // cc3xx. equivalant register exsist 1093 // outside GPIO IP (refer 1094 // PAD*_config register in the 1095 // shared comn space) Port Mux 1096 // Control 5 This field controls the 1097 // configuration for GPIO pin 5. 1098 #define GPIO_GPIO_PCTL_PMC5_S 20 1099 #define GPIO_GPIO_PCTL_PMC4_M 0x000F0000 // This register is not used in 1100 // cc3xx. equivalant register exsist 1101 // outside GPIO IP (refer 1102 // PAD*_config register in the 1103 // shared comn space) Port Mux 1104 // Control 4 This field controls the 1105 // configuration for GPIO pin 4. 1106 #define GPIO_GPIO_PCTL_PMC4_S 16 1107 #define GPIO_GPIO_PCTL_PMC3_M 0x0000F000 // This register is not used in 1108 // cc3xx. equivalant register exsist 1109 // outside GPIO IP (refer 1110 // PAD*_config register in the 1111 // shared comn space) Port Mux 1112 // Control 43 This field controls 1113 // the configuration for GPIO pin 3. 1114 #define GPIO_GPIO_PCTL_PMC3_S 12 1115 #define GPIO_GPIO_PCTL_PMC1_M 0x00000F00 // This register is not used in 1116 // cc3xx. equivalant register exsist 1117 // outside GPIO IP (refer 1118 // PAD*_config register in the 1119 // shared comn space) Port Mux 1120 // Control 1 This field controls the 1121 // configuration for GPIO pin 1. 1122 #define GPIO_GPIO_PCTL_PMC1_S 8 1123 #define GPIO_GPIO_PCTL_PMC2_M 0x000000F0 // This register is not used in 1124 // cc3xx. equivalant register exsist 1125 // outside GPIO IP (refer 1126 // PAD*_config register in the 1127 // shared comn space) Port Mux 1128 // Control 2 This field controls the 1129 // configuration for GPIO pin 2. 1130 #define GPIO_GPIO_PCTL_PMC2_S 4 1131 #define GPIO_GPIO_PCTL_PMC0_M 0x0000000F // This register is not used in 1132 // cc3xx. equivalant register exsist 1133 // outside GPIO IP (refer 1134 // PAD*_config register in the 1135 // shared comn space) Port Mux 1136 // Control 0 This field controls the 1137 // configuration for GPIO pin 0. 1138 #define GPIO_GPIO_PCTL_PMC0_S 0 1139 //****************************************************************************** 1140 // 1141 // The following are defines for the bit fields in the 1142 // GPIO_O_GPIO_ADCCTL register. 1143 // 1144 //****************************************************************************** 1145 #define GPIO_GPIO_ADCCTL_ADCEN_M \ 1146 0x000000FF // This register is not used in 1147 // cc3xx. ADC trigger via GPIO is 1148 // not supported. ADC Trigger Enable 1149 // Value Description 1 The 1150 // corresponding pin is used to 1151 // trigger the ADC. 0 The 1152 // corresponding pin is not used to 1153 // trigger the ADC. 1154 1155 #define GPIO_GPIO_ADCCTL_ADCEN_S 0 1156 //****************************************************************************** 1157 // 1158 // The following are defines for the bit fields in the 1159 // GPIO_O_GPIO_DMACTL register. 1160 // 1161 //****************************************************************************** 1162 #define GPIO_GPIO_DMACTL_DMAEN_M \ 1163 0x000000FF // This register is not used in the 1164 // cc3xx. Alternate register to 1165 // support this feature is coded in 1166 // the APPS_NWP_CMN space. refer 1167 // register as offset 0x400F70D8 1168 // ?DMA Trigger Enable Value 1169 // Description 1 The corresponding 1170 // pin is used to trigger the ?DMA. 1171 // 0 The corresponding pin is not 1172 // used to trigger the ?DMA. 1173 1174 #define GPIO_GPIO_DMACTL_DMAEN_S 0 1175 //****************************************************************************** 1176 // 1177 // The following are defines for the bit fields in the GPIO_O_GPIO_SI register. 1178 // 1179 //****************************************************************************** 1180 #define GPIO_GPIO_SI_SUM 0x00000001 // Summary Interrupt Value 1181 // Description 1 Each pin has its 1182 // own interrupt vector. 0 All port 1183 // pin interrupts are OR'ed together 1184 // to produce a summary interrupt. 1185 //****************************************************************************** 1186 // 1187 // The following are defines for the bit fields in the 1188 // GPIO_O_GPIO_PERIPHID4 register. 1189 // 1190 //****************************************************************************** 1191 #define GPIO_GPIO_PERIPHID4_PID4_M \ 1192 0x000000FF // This register is not used in 1193 // CC3XX. GPIO Peripheral ID 1194 // Register [7:0] 1195 1196 #define GPIO_GPIO_PERIPHID4_PID4_S 0 1197 //****************************************************************************** 1198 // 1199 // The following are defines for the bit fields in the 1200 // GPIO_O_GPIO_PERIPHID5 register. 1201 // 1202 //****************************************************************************** 1203 #define GPIO_GPIO_PERIPHID5_PID5_M \ 1204 0x000000FF // This register is not used in 1205 // CC3XX. GPIO Peripheral ID 1206 // Register [15:8] 1207 1208 #define GPIO_GPIO_PERIPHID5_PID5_S 0 1209 //****************************************************************************** 1210 // 1211 // The following are defines for the bit fields in the 1212 // GPIO_O_GPIO_PERIPHID6 register. 1213 // 1214 //****************************************************************************** 1215 #define GPIO_GPIO_PERIPHID6_PID6_M \ 1216 0x000000FF // This register is not used in 1217 // CC3XX. GPIO Peripheral ID 1218 // Register [23:16] 1219 1220 #define GPIO_GPIO_PERIPHID6_PID6_S 0 1221 //****************************************************************************** 1222 // 1223 // The following are defines for the bit fields in the 1224 // GPIO_O_GPIO_PERIPHID7 register. 1225 // 1226 //****************************************************************************** 1227 #define GPIO_GPIO_PERIPHID7_PID7_M \ 1228 0x000000FF // This register is not used in 1229 // CC3XX. GPIO Peripheral ID 1230 // Register [31:24] 1231 1232 #define GPIO_GPIO_PERIPHID7_PID7_S 0 1233 //****************************************************************************** 1234 // 1235 // The following are defines for the bit fields in the 1236 // GPIO_O_GPIO_PERIPHID0 register. 1237 // 1238 //****************************************************************************** 1239 #define GPIO_GPIO_PERIPHID0_PID0_M \ 1240 0x000000FF // This register is not used in 1241 // CC3XX. GPIO Peripheral ID 1242 // Register [7:0] Can be used by 1243 // software to identify the presence 1244 // of this peripheral. 1245 1246 #define GPIO_GPIO_PERIPHID0_PID0_S 0 1247 //****************************************************************************** 1248 // 1249 // The following are defines for the bit fields in the 1250 // GPIO_O_GPIO_PERIPHID1 register. 1251 // 1252 //****************************************************************************** 1253 #define GPIO_GPIO_PERIPHID1_PID1_M \ 1254 0x000000FF // GPIO Peripheral ID Register 1255 // [15:8] Can be used by software to 1256 // identify the presence of this 1257 // peripheral. 1258 1259 #define GPIO_GPIO_PERIPHID1_PID1_S 0 1260 //****************************************************************************** 1261 // 1262 // The following are defines for the bit fields in the 1263 // GPIO_O_GPIO_PERIPHID2 register. 1264 // 1265 //****************************************************************************** 1266 #define GPIO_GPIO_PERIPHID2_PID2_M \ 1267 0x000000FF // This register is not used in 1268 // CC3XX.v GPIO Peripheral ID 1269 // Register [23:16] Can be used by 1270 // software to identify the presence 1271 // of this peripheral. 1272 1273 #define GPIO_GPIO_PERIPHID2_PID2_S 0 1274 //****************************************************************************** 1275 // 1276 // The following are defines for the bit fields in the 1277 // GPIO_O_GPIO_PERIPHID3 register. 1278 // 1279 //****************************************************************************** 1280 #define GPIO_GPIO_PERIPHID3_PID3_M \ 1281 0x000000FF // This register is not used in 1282 // CC3XX. GPIO Peripheral ID 1283 // Register [31:24] Can be used by 1284 // software to identify the presence 1285 // of this peripheral. 1286 1287 #define GPIO_GPIO_PERIPHID3_PID3_S 0 1288 //****************************************************************************** 1289 // 1290 // The following are defines for the bit fields in the 1291 // GPIO_O_GPIO_PCELLID0 register. 1292 // 1293 //****************************************************************************** 1294 #define GPIO_GPIO_PCELLID0_CID0_M \ 1295 0x000000FF // This register is not used in 1296 // CC3XX. GPIO PrimeCell ID Register 1297 // [7:0] Provides software a 1298 // standard cross-peripheral 1299 // identification system. 1300 1301 #define GPIO_GPIO_PCELLID0_CID0_S 0 1302 //****************************************************************************** 1303 // 1304 // The following are defines for the bit fields in the 1305 // GPIO_O_GPIO_PCELLID1 register. 1306 // 1307 //****************************************************************************** 1308 #define GPIO_GPIO_PCELLID1_CID1_M \ 1309 0x000000FF // This register is not used in 1310 // CC3XX. GPIO PrimeCell ID Register 1311 // [15:8] Provides software a 1312 // standard cross-peripheral 1313 // identification system. 1314 1315 #define GPIO_GPIO_PCELLID1_CID1_S 0 1316 //****************************************************************************** 1317 // 1318 // The following are defines for the bit fields in the 1319 // GPIO_O_GPIO_PCELLID2 register. 1320 // 1321 //****************************************************************************** 1322 #define GPIO_GPIO_PCELLID2_CID2_M \ 1323 0x000000FF // This register is not used in 1324 // CC3XX. GPIO PrimeCell ID Register 1325 // [23:16] Provides software a 1326 // standard cross-peripheral 1327 // identification system. 1328 1329 #define GPIO_GPIO_PCELLID2_CID2_S 0 1330 //****************************************************************************** 1331 // 1332 // The following are defines for the bit fields in the 1333 // GPIO_O_GPIO_PCELLID3 register. 1334 // 1335 //****************************************************************************** 1336 #define GPIO_GPIO_PCELLID3_CID3_M \ 1337 0x000000FF // This register is not used in 1338 // CC3XX. GPIO PrimeCell ID Register 1339 // [31:24] Provides software a 1340 // standard cross-peripheral 1341 // identification system. 1342 1343 #define GPIO_GPIO_PCELLID3_CID3_S 0 1344 1345 1346 1347 #endif // __HW_GPIO_H__ 1348
