1 /****************************************************************************** 2 * Filename: hw_gpio_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_GPIO_H__ 34 #define __HW_GPIO_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // GPIO component 40 // 41 //***************************************************************************** 42 // Module Description 43 #define GPIO_O_DESC 0x00000000U 44 45 // Module Description Extended 46 #define GPIO_O_DESCEX 0x00000004U 47 48 // Interrupt Mask 49 #define GPIO_O_IMASK 0x00000044U 50 51 // Raw interrupt status 52 #define GPIO_O_RIS 0x0000004CU 53 54 // Masked interrupt status 55 #define GPIO_O_MIS 0x00000054U 56 57 // Interrupt set 58 #define GPIO_O_ISET 0x0000005CU 59 60 // Interrupt clear 61 #define GPIO_O_ICLR 0x00000064U 62 63 // Interrupt mask set 64 #define GPIO_O_IMSET 0x0000006CU 65 66 // Interrupt mask clear 67 #define GPIO_O_IMCLR 0x00000074U 68 69 // Alias for Data out 3 to 0 70 #define GPIO_O_DOUT3_0 0x00000100U 71 72 // Alias for Data out 7 to 4 73 #define GPIO_O_DOUT7_4 0x00000104U 74 75 // Alias for Data out 11 to 8 76 #define GPIO_O_DOUT11_8 0x00000108U 77 78 // Alias for Data out 15 to 12 79 #define GPIO_O_DOUT15_12 0x0000010CU 80 81 // Alias for Data out 19 to 16 82 #define GPIO_O_DOUT19_16 0x00000110U 83 84 // Alias for Data out 23 to 20 85 #define GPIO_O_DOUT23_20 0x00000114U 86 87 // Alias for Data out 27 to 24 88 #define GPIO_O_DOUT27_24 0x00000118U 89 90 // Data out 31 to 0 91 #define GPIO_O_DOUT31_0 0x00000200U 92 93 // Data out set 31 to 0 94 #define GPIO_O_DOUTSET31_0 0x00000210U 95 96 // Data out clear 31 to 0 97 #define GPIO_O_DOUTCLR31_0 0x00000220U 98 99 // Data out toggle 31 to 0 100 #define GPIO_O_DOUTTGL31_0 0x00000230U 101 102 // Alias for Data out toggle 3 to 0 103 #define GPIO_O_DOUTTGL3_0 0x00000300U 104 105 // Alias for Data out toggle 7 to 4 106 #define GPIO_O_DOUTTGL7_4 0x00000304U 107 108 // Alias for Data out toggle 11 to 8 109 #define GPIO_O_DOUTTGL11_8 0x00000308U 110 111 // Alias for Data out toggle 15 to 12 112 #define GPIO_O_DOUTTGL15_12 0x0000030CU 113 114 // Alias for Data out toggle 19 to 16 115 #define GPIO_O_DOUTTGL19_16 0x00000310U 116 117 // Alias for Data out toggle 23 to 20 118 #define GPIO_O_DOUTTGL23_20 0x00000314U 119 120 // Alias for Data out toggle 27 to 24 121 #define GPIO_O_DOUTTGL27_24 0x00000318U 122 123 // Alias for Data out enable 3 to 0 124 #define GPIO_O_DOE3_0 0x00000400U 125 126 // Alias for Data out enable 7 to 4 127 #define GPIO_O_DOE7_4 0x00000404U 128 129 // Alias for Data out enable 11 to 8 130 #define GPIO_O_DOE11_8 0x00000408U 131 132 // Alias for Data out enable 15 to 12 133 #define GPIO_O_DOE15_12 0x0000040CU 134 135 // Alias for Data out enable 19 to 16 136 #define GPIO_O_DOE19_16 0x00000410U 137 138 // Alias for Data out enable 23 to 20 139 #define GPIO_O_DOE23_20 0x00000414U 140 141 // Alias for Data out enable 27 to 24 142 #define GPIO_O_DOE27_24 0x00000418U 143 144 // Data out enable 31 to 0 145 #define GPIO_O_DOE31_0 0x00000500U 146 147 // Data out enable set 31 to 0 148 #define GPIO_O_DOESET31_0 0x00000510U 149 150 // Data out enable clear 31 to 0 151 #define GPIO_O_DOECLR31_0 0x00000520U 152 153 // Data out enable toggle 31 to 0 154 #define GPIO_O_DOETGL31_0 0x00000530U 155 156 // Alias for Data input 3 to 0 157 #define GPIO_O_DIN3_0 0x00000600U 158 159 // Alias for Data input 7 to 4 160 #define GPIO_O_DIN7_4 0x00000604U 161 162 // Alias for Data input 11 to 8 163 #define GPIO_O_DIN11_8 0x00000608U 164 165 // Alias for Data input 15 to 12 166 #define GPIO_O_DIN15_12 0x0000060CU 167 168 // Alias for Data input 19 to 16 169 #define GPIO_O_DIN19_16 0x00000610U 170 171 // Alias for Data input 23 to 20 172 #define GPIO_O_DIN23_20 0x00000614U 173 174 // Alias for Data input 27 to 24 175 #define GPIO_O_DIN27_24 0x00000618U 176 177 // Data input 31 to 0 178 #define GPIO_O_DIN31_0 0x00000700U 179 180 // Event configuration 181 #define GPIO_O_EVTCFG 0x00000800U 182 183 //***************************************************************************** 184 // 185 // Register: GPIO_O_DESC 186 // 187 //***************************************************************************** 188 // Field: [31:16] MODID 189 // 190 // Module identifier used to uniquely identify this IP. 191 #define GPIO_DESC_MODID_W 16U 192 #define GPIO_DESC_MODID_M 0xFFFF0000U 193 #define GPIO_DESC_MODID_S 16U 194 195 // Field: [15:12] STDIPOFF 196 // 197 // Standard IP MMR block offset. Standard IP MMRs are the set from aggregated 198 // IRQ registers till DTB. 199 // 200 // 0: Standard IP MMRs do not exist 201 // 202 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 203 // address) 204 #define GPIO_DESC_STDIPOFF_W 4U 205 #define GPIO_DESC_STDIPOFF_M 0x0000F000U 206 #define GPIO_DESC_STDIPOFF_S 12U 207 208 // Field: [11:8] INSTIDX 209 // 210 // IP Instance ID number. If multiple instances of IP exist in the device, this 211 // field can identify the instance number (0-15). 212 #define GPIO_DESC_INSTIDX_W 4U 213 #define GPIO_DESC_INSTIDX_M 0x00000F00U 214 #define GPIO_DESC_INSTIDX_S 8U 215 216 // Field: [7:4] MAJREV 217 // 218 // Major revision of IP (0-15). 219 #define GPIO_DESC_MAJREV_W 4U 220 #define GPIO_DESC_MAJREV_M 0x000000F0U 221 #define GPIO_DESC_MAJREV_S 4U 222 223 // Field: [3:0] MINREV 224 // 225 // Minor revision of IP (0-15). 226 #define GPIO_DESC_MINREV_W 4U 227 #define GPIO_DESC_MINREV_M 0x0000000FU 228 #define GPIO_DESC_MINREV_S 0U 229 230 //***************************************************************************** 231 // 232 // Register: GPIO_O_DESCEX 233 // 234 //***************************************************************************** 235 // Field: [5:0] NUMDIO 236 // 237 // This provides the total number of DIOs supported by GPIO. The number of DIOs 238 // supprted is NUMDIO + 1 239 #define GPIO_DESCEX_NUMDIO_W 6U 240 #define GPIO_DESCEX_NUMDIO_M 0x0000003FU 241 #define GPIO_DESCEX_NUMDIO_S 0U 242 243 //***************************************************************************** 244 // 245 // Register: GPIO_O_IMASK 246 // 247 //***************************************************************************** 248 // Field: [25] DIO25 249 // 250 // Interrupt mask for DIO25 251 // ENUMs: 252 // SET Set Interrrupt Mask 253 // CLR Clear Interrupt Mask 254 #define GPIO_IMASK_DIO25 0x02000000U 255 #define GPIO_IMASK_DIO25_M 0x02000000U 256 #define GPIO_IMASK_DIO25_S 25U 257 #define GPIO_IMASK_DIO25_SET 0x02000000U 258 #define GPIO_IMASK_DIO25_CLR 0x00000000U 259 260 // Field: [24] DIO24 261 // 262 // Interrupt mask for DIO24 263 // ENUMs: 264 // SET Set Interrrupt Mask 265 // CLR Clear Interrupt Mask 266 #define GPIO_IMASK_DIO24 0x01000000U 267 #define GPIO_IMASK_DIO24_M 0x01000000U 268 #define GPIO_IMASK_DIO24_S 24U 269 #define GPIO_IMASK_DIO24_SET 0x01000000U 270 #define GPIO_IMASK_DIO24_CLR 0x00000000U 271 272 // Field: [23] DIO23 273 // 274 // Interrupt mask for DIO23 275 // ENUMs: 276 // SET Set Interrrupt Mask 277 // CLR Clear Interrupt Mask 278 #define GPIO_IMASK_DIO23 0x00800000U 279 #define GPIO_IMASK_DIO23_M 0x00800000U 280 #define GPIO_IMASK_DIO23_S 23U 281 #define GPIO_IMASK_DIO23_SET 0x00800000U 282 #define GPIO_IMASK_DIO23_CLR 0x00000000U 283 284 // Field: [22] DIO22 285 // 286 // Interrupt mask for DIO22 287 // ENUMs: 288 // SET Set Interrrupt Mask 289 // CLR Clear Interrupt Mask 290 #define GPIO_IMASK_DIO22 0x00400000U 291 #define GPIO_IMASK_DIO22_M 0x00400000U 292 #define GPIO_IMASK_DIO22_S 22U 293 #define GPIO_IMASK_DIO22_SET 0x00400000U 294 #define GPIO_IMASK_DIO22_CLR 0x00000000U 295 296 // Field: [21] DIO21 297 // 298 // Interrupt mask for DIO21 299 // ENUMs: 300 // SET Set Interrrupt Mask 301 // CLR Clear Interrupt Mask 302 #define GPIO_IMASK_DIO21 0x00200000U 303 #define GPIO_IMASK_DIO21_M 0x00200000U 304 #define GPIO_IMASK_DIO21_S 21U 305 #define GPIO_IMASK_DIO21_SET 0x00200000U 306 #define GPIO_IMASK_DIO21_CLR 0x00000000U 307 308 // Field: [20] DIO20 309 // 310 // Interrupt mask for DIO20 311 // ENUMs: 312 // SET Set Interrrupt Mask 313 // CLR Clear Interrupt Mask 314 #define GPIO_IMASK_DIO20 0x00100000U 315 #define GPIO_IMASK_DIO20_M 0x00100000U 316 #define GPIO_IMASK_DIO20_S 20U 317 #define GPIO_IMASK_DIO20_SET 0x00100000U 318 #define GPIO_IMASK_DIO20_CLR 0x00000000U 319 320 // Field: [19] DIO19 321 // 322 // Interrupt mask for DIO19 323 // ENUMs: 324 // SET Set Interrrupt Mask 325 // CLR Clear Interrupt Mask 326 #define GPIO_IMASK_DIO19 0x00080000U 327 #define GPIO_IMASK_DIO19_M 0x00080000U 328 #define GPIO_IMASK_DIO19_S 19U 329 #define GPIO_IMASK_DIO19_SET 0x00080000U 330 #define GPIO_IMASK_DIO19_CLR 0x00000000U 331 332 // Field: [18] DIO18 333 // 334 // Interrupt mask for DIO18 335 // ENUMs: 336 // SET Set Interrrupt Mask 337 // CLR Clear Interrupt Mask 338 #define GPIO_IMASK_DIO18 0x00040000U 339 #define GPIO_IMASK_DIO18_M 0x00040000U 340 #define GPIO_IMASK_DIO18_S 18U 341 #define GPIO_IMASK_DIO18_SET 0x00040000U 342 #define GPIO_IMASK_DIO18_CLR 0x00000000U 343 344 // Field: [17] DIO17 345 // 346 // Interrupt mask for DIO17 347 // ENUMs: 348 // SET Set Interrrupt Mask 349 // CLR Clear Interrupt Mask 350 #define GPIO_IMASK_DIO17 0x00020000U 351 #define GPIO_IMASK_DIO17_M 0x00020000U 352 #define GPIO_IMASK_DIO17_S 17U 353 #define GPIO_IMASK_DIO17_SET 0x00020000U 354 #define GPIO_IMASK_DIO17_CLR 0x00000000U 355 356 // Field: [16] DIO16 357 // 358 // Interrupt mask for DIO16 359 // ENUMs: 360 // SET Set Interrrupt Mask 361 // CLR Clear Interrupt Mask 362 #define GPIO_IMASK_DIO16 0x00010000U 363 #define GPIO_IMASK_DIO16_M 0x00010000U 364 #define GPIO_IMASK_DIO16_S 16U 365 #define GPIO_IMASK_DIO16_SET 0x00010000U 366 #define GPIO_IMASK_DIO16_CLR 0x00000000U 367 368 // Field: [15] DIO15 369 // 370 // Interrupt mask for DIO15 371 // ENUMs: 372 // SET Set Interrrupt Mask 373 // CLR Clear Interrupt Mask 374 #define GPIO_IMASK_DIO15 0x00008000U 375 #define GPIO_IMASK_DIO15_M 0x00008000U 376 #define GPIO_IMASK_DIO15_S 15U 377 #define GPIO_IMASK_DIO15_SET 0x00008000U 378 #define GPIO_IMASK_DIO15_CLR 0x00000000U 379 380 // Field: [14] DIO14 381 // 382 // Interrupt mask for DIO14 383 // ENUMs: 384 // SET Set Interrrupt Mask 385 // CLR Clear Interrupt Mask 386 #define GPIO_IMASK_DIO14 0x00004000U 387 #define GPIO_IMASK_DIO14_M 0x00004000U 388 #define GPIO_IMASK_DIO14_S 14U 389 #define GPIO_IMASK_DIO14_SET 0x00004000U 390 #define GPIO_IMASK_DIO14_CLR 0x00000000U 391 392 // Field: [13] DIO13 393 // 394 // Interrupt mask for DIO13 395 // ENUMs: 396 // SET Set Interrrupt Mask 397 // CLR Clear Interrupt Mask 398 #define GPIO_IMASK_DIO13 0x00002000U 399 #define GPIO_IMASK_DIO13_M 0x00002000U 400 #define GPIO_IMASK_DIO13_S 13U 401 #define GPIO_IMASK_DIO13_SET 0x00002000U 402 #define GPIO_IMASK_DIO13_CLR 0x00000000U 403 404 // Field: [12] DIO12 405 // 406 // Interrupt mask for DIO12 407 // ENUMs: 408 // SET Set Interrrupt Mask 409 // CLR Clear Interrupt Mask 410 #define GPIO_IMASK_DIO12 0x00001000U 411 #define GPIO_IMASK_DIO12_M 0x00001000U 412 #define GPIO_IMASK_DIO12_S 12U 413 #define GPIO_IMASK_DIO12_SET 0x00001000U 414 #define GPIO_IMASK_DIO12_CLR 0x00000000U 415 416 // Field: [11] DIO11 417 // 418 // Interrupt mask for DIO11 419 // ENUMs: 420 // SET Set Interrrupt Mask 421 // CLR Clear Interrupt Mask 422 #define GPIO_IMASK_DIO11 0x00000800U 423 #define GPIO_IMASK_DIO11_M 0x00000800U 424 #define GPIO_IMASK_DIO11_S 11U 425 #define GPIO_IMASK_DIO11_SET 0x00000800U 426 #define GPIO_IMASK_DIO11_CLR 0x00000000U 427 428 // Field: [10] DIO10 429 // 430 // Interrupt mask for DIO10 431 // ENUMs: 432 // SET Set Interrrupt Mask 433 // CLR Clear Interrupt Mask 434 #define GPIO_IMASK_DIO10 0x00000400U 435 #define GPIO_IMASK_DIO10_M 0x00000400U 436 #define GPIO_IMASK_DIO10_S 10U 437 #define GPIO_IMASK_DIO10_SET 0x00000400U 438 #define GPIO_IMASK_DIO10_CLR 0x00000000U 439 440 // Field: [9] DIO9 441 // 442 // Interrupt mask for DIO9 443 // ENUMs: 444 // SET Set Interrrupt Mask 445 // CLR Clear Interrupt Mask 446 #define GPIO_IMASK_DIO9 0x00000200U 447 #define GPIO_IMASK_DIO9_M 0x00000200U 448 #define GPIO_IMASK_DIO9_S 9U 449 #define GPIO_IMASK_DIO9_SET 0x00000200U 450 #define GPIO_IMASK_DIO9_CLR 0x00000000U 451 452 // Field: [8] DIO8 453 // 454 // Interrupt mask for DIO8 455 // ENUMs: 456 // SET Set Interrrupt Mask 457 // CLR Clear Interrupt Mask 458 #define GPIO_IMASK_DIO8 0x00000100U 459 #define GPIO_IMASK_DIO8_M 0x00000100U 460 #define GPIO_IMASK_DIO8_S 8U 461 #define GPIO_IMASK_DIO8_SET 0x00000100U 462 #define GPIO_IMASK_DIO8_CLR 0x00000000U 463 464 // Field: [7] DIO7 465 // 466 // Interrupt mask for DIO7 467 // ENUMs: 468 // SET Set Interrrupt Mask 469 // CLR Clear Interrupt Mask 470 #define GPIO_IMASK_DIO7 0x00000080U 471 #define GPIO_IMASK_DIO7_M 0x00000080U 472 #define GPIO_IMASK_DIO7_S 7U 473 #define GPIO_IMASK_DIO7_SET 0x00000080U 474 #define GPIO_IMASK_DIO7_CLR 0x00000000U 475 476 // Field: [6] DIO6 477 // 478 // Interrupt mask for DIO6 479 // ENUMs: 480 // SET Set Interrrupt Mask 481 // CLR Clear Interrupt Mask 482 #define GPIO_IMASK_DIO6 0x00000040U 483 #define GPIO_IMASK_DIO6_M 0x00000040U 484 #define GPIO_IMASK_DIO6_S 6U 485 #define GPIO_IMASK_DIO6_SET 0x00000040U 486 #define GPIO_IMASK_DIO6_CLR 0x00000000U 487 488 // Field: [5] DIO5 489 // 490 // Interrupt mask for DIO5 491 // ENUMs: 492 // SET Set Interrrupt Mask 493 // CLR Clear Interrupt Mask 494 #define GPIO_IMASK_DIO5 0x00000020U 495 #define GPIO_IMASK_DIO5_M 0x00000020U 496 #define GPIO_IMASK_DIO5_S 5U 497 #define GPIO_IMASK_DIO5_SET 0x00000020U 498 #define GPIO_IMASK_DIO5_CLR 0x00000000U 499 500 // Field: [4] DIO4 501 // 502 // Interrupt mask for DIO4 503 // ENUMs: 504 // SET Set Interrrupt Mask 505 // CLR Clear Interrupt Mask 506 #define GPIO_IMASK_DIO4 0x00000010U 507 #define GPIO_IMASK_DIO4_M 0x00000010U 508 #define GPIO_IMASK_DIO4_S 4U 509 #define GPIO_IMASK_DIO4_SET 0x00000010U 510 #define GPIO_IMASK_DIO4_CLR 0x00000000U 511 512 // Field: [3] DIO3 513 // 514 // Interrupt mask for DIO3 515 // ENUMs: 516 // SET Set Interrrupt Mask 517 // CLR Clear Interrupt Mask 518 #define GPIO_IMASK_DIO3 0x00000008U 519 #define GPIO_IMASK_DIO3_M 0x00000008U 520 #define GPIO_IMASK_DIO3_S 3U 521 #define GPIO_IMASK_DIO3_SET 0x00000008U 522 #define GPIO_IMASK_DIO3_CLR 0x00000000U 523 524 // Field: [2] DIO2 525 // 526 // Interrupt mask for DIO2 527 // ENUMs: 528 // SET Set Interrrupt Mask 529 // CLR Clear Interrupt Mask 530 #define GPIO_IMASK_DIO2 0x00000004U 531 #define GPIO_IMASK_DIO2_M 0x00000004U 532 #define GPIO_IMASK_DIO2_S 2U 533 #define GPIO_IMASK_DIO2_SET 0x00000004U 534 #define GPIO_IMASK_DIO2_CLR 0x00000000U 535 536 // Field: [1] DIO1 537 // 538 // Interrupt mask for DIO1 539 // ENUMs: 540 // SET Set Interrrupt Mask 541 // CLR Clear Interrupt Mask 542 #define GPIO_IMASK_DIO1 0x00000002U 543 #define GPIO_IMASK_DIO1_M 0x00000002U 544 #define GPIO_IMASK_DIO1_S 1U 545 #define GPIO_IMASK_DIO1_SET 0x00000002U 546 #define GPIO_IMASK_DIO1_CLR 0x00000000U 547 548 // Field: [0] DIO0 549 // 550 // Interrupt mask for DIO0 551 // ENUMs: 552 // SET Set Interrrupt Mask 553 // CLR Clear Interrupt Mask 554 #define GPIO_IMASK_DIO0 0x00000001U 555 #define GPIO_IMASK_DIO0_M 0x00000001U 556 #define GPIO_IMASK_DIO0_S 0U 557 #define GPIO_IMASK_DIO0_SET 0x00000001U 558 #define GPIO_IMASK_DIO0_CLR 0x00000000U 559 560 //***************************************************************************** 561 // 562 // Register: GPIO_O_RIS 563 // 564 //***************************************************************************** 565 // Field: [25] DIO25 566 // 567 // Raw interrupt flag for DIO25 568 // ENUMs: 569 // SET Interrupt occured 570 // CLR Interrupt did not occur 571 #define GPIO_RIS_DIO25 0x02000000U 572 #define GPIO_RIS_DIO25_M 0x02000000U 573 #define GPIO_RIS_DIO25_S 25U 574 #define GPIO_RIS_DIO25_SET 0x02000000U 575 #define GPIO_RIS_DIO25_CLR 0x00000000U 576 577 // Field: [24] DIO24 578 // 579 // Raw interrupt flag for DIO24 580 // ENUMs: 581 // SET Interrupt occured 582 // CLR Interrupt did not occur 583 #define GPIO_RIS_DIO24 0x01000000U 584 #define GPIO_RIS_DIO24_M 0x01000000U 585 #define GPIO_RIS_DIO24_S 24U 586 #define GPIO_RIS_DIO24_SET 0x01000000U 587 #define GPIO_RIS_DIO24_CLR 0x00000000U 588 589 // Field: [23] DIO23 590 // 591 // Raw interrupt flag for DIO23 592 // ENUMs: 593 // SET Interrupt occured 594 // CLR Interrupt did not occur 595 #define GPIO_RIS_DIO23 0x00800000U 596 #define GPIO_RIS_DIO23_M 0x00800000U 597 #define GPIO_RIS_DIO23_S 23U 598 #define GPIO_RIS_DIO23_SET 0x00800000U 599 #define GPIO_RIS_DIO23_CLR 0x00000000U 600 601 // Field: [22] DIO22 602 // 603 // Raw interrupt flag for DIO22 604 // ENUMs: 605 // SET Interrupt occured 606 // CLR Interrupt did not occur 607 #define GPIO_RIS_DIO22 0x00400000U 608 #define GPIO_RIS_DIO22_M 0x00400000U 609 #define GPIO_RIS_DIO22_S 22U 610 #define GPIO_RIS_DIO22_SET 0x00400000U 611 #define GPIO_RIS_DIO22_CLR 0x00000000U 612 613 // Field: [21] DIO21 614 // 615 // Raw interrupt flag for DIO21 616 // ENUMs: 617 // SET Interrupt occured 618 // CLR Interrupt did not occur 619 #define GPIO_RIS_DIO21 0x00200000U 620 #define GPIO_RIS_DIO21_M 0x00200000U 621 #define GPIO_RIS_DIO21_S 21U 622 #define GPIO_RIS_DIO21_SET 0x00200000U 623 #define GPIO_RIS_DIO21_CLR 0x00000000U 624 625 // Field: [20] DIO20 626 // 627 // Raw interrupt flag for DIO20 628 // ENUMs: 629 // SET Interrupt occured 630 // CLR Interrupt did not occur 631 #define GPIO_RIS_DIO20 0x00100000U 632 #define GPIO_RIS_DIO20_M 0x00100000U 633 #define GPIO_RIS_DIO20_S 20U 634 #define GPIO_RIS_DIO20_SET 0x00100000U 635 #define GPIO_RIS_DIO20_CLR 0x00000000U 636 637 // Field: [19] DIO19 638 // 639 // Raw interrupt flag for DIO19 640 // ENUMs: 641 // SET Interrupt occured 642 // CLR Interrupt did not occur 643 #define GPIO_RIS_DIO19 0x00080000U 644 #define GPIO_RIS_DIO19_M 0x00080000U 645 #define GPIO_RIS_DIO19_S 19U 646 #define GPIO_RIS_DIO19_SET 0x00080000U 647 #define GPIO_RIS_DIO19_CLR 0x00000000U 648 649 // Field: [18] DIO18 650 // 651 // Raw interrupt flag for DIO18 652 // ENUMs: 653 // SET Interrupt occured 654 // CLR Interrupt did not occur 655 #define GPIO_RIS_DIO18 0x00040000U 656 #define GPIO_RIS_DIO18_M 0x00040000U 657 #define GPIO_RIS_DIO18_S 18U 658 #define GPIO_RIS_DIO18_SET 0x00040000U 659 #define GPIO_RIS_DIO18_CLR 0x00000000U 660 661 // Field: [17] DIO17 662 // 663 // Raw interrupt flag for DIO17 664 // ENUMs: 665 // SET Interrupt occured 666 // CLR Interrupt did not occur 667 #define GPIO_RIS_DIO17 0x00020000U 668 #define GPIO_RIS_DIO17_M 0x00020000U 669 #define GPIO_RIS_DIO17_S 17U 670 #define GPIO_RIS_DIO17_SET 0x00020000U 671 #define GPIO_RIS_DIO17_CLR 0x00000000U 672 673 // Field: [16] DIO16 674 // 675 // Raw interrupt flag for DIO16 676 // ENUMs: 677 // SET Interrupt occured 678 // CLR Interrupt did not occur 679 #define GPIO_RIS_DIO16 0x00010000U 680 #define GPIO_RIS_DIO16_M 0x00010000U 681 #define GPIO_RIS_DIO16_S 16U 682 #define GPIO_RIS_DIO16_SET 0x00010000U 683 #define GPIO_RIS_DIO16_CLR 0x00000000U 684 685 // Field: [15] DIO15 686 // 687 // Raw interrupt flag for DIO15 688 // ENUMs: 689 // SET Interrupt occured 690 // CLR Interrupt did not occur 691 #define GPIO_RIS_DIO15 0x00008000U 692 #define GPIO_RIS_DIO15_M 0x00008000U 693 #define GPIO_RIS_DIO15_S 15U 694 #define GPIO_RIS_DIO15_SET 0x00008000U 695 #define GPIO_RIS_DIO15_CLR 0x00000000U 696 697 // Field: [14] DIO14 698 // 699 // Raw interrupt flag for DIO14 700 // ENUMs: 701 // SET Interrupt occured 702 // CLR Interrupt did not occur 703 #define GPIO_RIS_DIO14 0x00004000U 704 #define GPIO_RIS_DIO14_M 0x00004000U 705 #define GPIO_RIS_DIO14_S 14U 706 #define GPIO_RIS_DIO14_SET 0x00004000U 707 #define GPIO_RIS_DIO14_CLR 0x00000000U 708 709 // Field: [13] DIO13 710 // 711 // Raw interrupt flag for DIO13 712 // ENUMs: 713 // SET Interrupt occured 714 // CLR Interrupt did not occur 715 #define GPIO_RIS_DIO13 0x00002000U 716 #define GPIO_RIS_DIO13_M 0x00002000U 717 #define GPIO_RIS_DIO13_S 13U 718 #define GPIO_RIS_DIO13_SET 0x00002000U 719 #define GPIO_RIS_DIO13_CLR 0x00000000U 720 721 // Field: [12] DIO12 722 // 723 // Raw interrupt flag for DIO12 724 // ENUMs: 725 // SET Interrupt occured 726 // CLR Interrupt did not occur 727 #define GPIO_RIS_DIO12 0x00001000U 728 #define GPIO_RIS_DIO12_M 0x00001000U 729 #define GPIO_RIS_DIO12_S 12U 730 #define GPIO_RIS_DIO12_SET 0x00001000U 731 #define GPIO_RIS_DIO12_CLR 0x00000000U 732 733 // Field: [11] DIO11 734 // 735 // Raw interrupt flag for DIO11 736 // ENUMs: 737 // SET Interrupt occured 738 // CLR Interrupt did not occur 739 #define GPIO_RIS_DIO11 0x00000800U 740 #define GPIO_RIS_DIO11_M 0x00000800U 741 #define GPIO_RIS_DIO11_S 11U 742 #define GPIO_RIS_DIO11_SET 0x00000800U 743 #define GPIO_RIS_DIO11_CLR 0x00000000U 744 745 // Field: [10] DIO10 746 // 747 // Raw interrupt flag for DIO10 748 // ENUMs: 749 // SET Interrupt occured 750 // CLR Interrupt did not occur 751 #define GPIO_RIS_DIO10 0x00000400U 752 #define GPIO_RIS_DIO10_M 0x00000400U 753 #define GPIO_RIS_DIO10_S 10U 754 #define GPIO_RIS_DIO10_SET 0x00000400U 755 #define GPIO_RIS_DIO10_CLR 0x00000000U 756 757 // Field: [9] DIO9 758 // 759 // Raw interrupt flag for DIO9 760 // ENUMs: 761 // SET Interrupt occured 762 // CLR Interrupt did not occur 763 #define GPIO_RIS_DIO9 0x00000200U 764 #define GPIO_RIS_DIO9_M 0x00000200U 765 #define GPIO_RIS_DIO9_S 9U 766 #define GPIO_RIS_DIO9_SET 0x00000200U 767 #define GPIO_RIS_DIO9_CLR 0x00000000U 768 769 // Field: [8] DIO8 770 // 771 // Raw interrupt flag for DIO8 772 // ENUMs: 773 // SET Interrupt occured 774 // CLR Interrupt did not occur 775 #define GPIO_RIS_DIO8 0x00000100U 776 #define GPIO_RIS_DIO8_M 0x00000100U 777 #define GPIO_RIS_DIO8_S 8U 778 #define GPIO_RIS_DIO8_SET 0x00000100U 779 #define GPIO_RIS_DIO8_CLR 0x00000000U 780 781 // Field: [7] DIO7 782 // 783 // Raw interrupt flag for DIO7 784 // ENUMs: 785 // SET Interrupt occured 786 // CLR Interrupt did not occur 787 #define GPIO_RIS_DIO7 0x00000080U 788 #define GPIO_RIS_DIO7_M 0x00000080U 789 #define GPIO_RIS_DIO7_S 7U 790 #define GPIO_RIS_DIO7_SET 0x00000080U 791 #define GPIO_RIS_DIO7_CLR 0x00000000U 792 793 // Field: [6] DIO6 794 // 795 // Raw interrupt flag for DIO6 796 // ENUMs: 797 // SET Interrupt occured 798 // CLR Interrupt did not occur 799 #define GPIO_RIS_DIO6 0x00000040U 800 #define GPIO_RIS_DIO6_M 0x00000040U 801 #define GPIO_RIS_DIO6_S 6U 802 #define GPIO_RIS_DIO6_SET 0x00000040U 803 #define GPIO_RIS_DIO6_CLR 0x00000000U 804 805 // Field: [5] DIO5 806 // 807 // Raw interrupt flag for DIO5 808 // ENUMs: 809 // SET Interrupt occured 810 // CLR Interrupt did not occur 811 #define GPIO_RIS_DIO5 0x00000020U 812 #define GPIO_RIS_DIO5_M 0x00000020U 813 #define GPIO_RIS_DIO5_S 5U 814 #define GPIO_RIS_DIO5_SET 0x00000020U 815 #define GPIO_RIS_DIO5_CLR 0x00000000U 816 817 // Field: [4] DIO4 818 // 819 // Raw interrupt flag for DIO4 820 // ENUMs: 821 // SET Interrupt occured 822 // CLR Interrupt did not occur 823 #define GPIO_RIS_DIO4 0x00000010U 824 #define GPIO_RIS_DIO4_M 0x00000010U 825 #define GPIO_RIS_DIO4_S 4U 826 #define GPIO_RIS_DIO4_SET 0x00000010U 827 #define GPIO_RIS_DIO4_CLR 0x00000000U 828 829 // Field: [3] DIO3 830 // 831 // Raw interrupt flag for DIO3 832 // ENUMs: 833 // SET Interrupt occured 834 // CLR Interrupt did not occur 835 #define GPIO_RIS_DIO3 0x00000008U 836 #define GPIO_RIS_DIO3_M 0x00000008U 837 #define GPIO_RIS_DIO3_S 3U 838 #define GPIO_RIS_DIO3_SET 0x00000008U 839 #define GPIO_RIS_DIO3_CLR 0x00000000U 840 841 // Field: [2] DIO2 842 // 843 // Raw interrupt flag for DIO2 844 // ENUMs: 845 // SET Interrupt occured 846 // CLR Interrupt did not occur 847 #define GPIO_RIS_DIO2 0x00000004U 848 #define GPIO_RIS_DIO2_M 0x00000004U 849 #define GPIO_RIS_DIO2_S 2U 850 #define GPIO_RIS_DIO2_SET 0x00000004U 851 #define GPIO_RIS_DIO2_CLR 0x00000000U 852 853 // Field: [1] DIO1 854 // 855 // Raw interrupt flag for DIO1 856 // ENUMs: 857 // SET Interrupt occured 858 // CLR Interrupt did not occur 859 #define GPIO_RIS_DIO1 0x00000002U 860 #define GPIO_RIS_DIO1_M 0x00000002U 861 #define GPIO_RIS_DIO1_S 1U 862 #define GPIO_RIS_DIO1_SET 0x00000002U 863 #define GPIO_RIS_DIO1_CLR 0x00000000U 864 865 // Field: [0] DIO0 866 // 867 // Raw interrupt flag for DIO0 868 // ENUMs: 869 // SET Interrupt occured 870 // CLR Interrupt did not occur 871 #define GPIO_RIS_DIO0 0x00000001U 872 #define GPIO_RIS_DIO0_M 0x00000001U 873 #define GPIO_RIS_DIO0_S 0U 874 #define GPIO_RIS_DIO0_SET 0x00000001U 875 #define GPIO_RIS_DIO0_CLR 0x00000000U 876 877 //***************************************************************************** 878 // 879 // Register: GPIO_O_MIS 880 // 881 //***************************************************************************** 882 // Field: [25] DIO25 883 // 884 // Masked interrupt flag for DIO25 885 // ENUMs: 886 // SET Interrupt occured 887 // CLR Interrupt did not occur 888 #define GPIO_MIS_DIO25 0x02000000U 889 #define GPIO_MIS_DIO25_M 0x02000000U 890 #define GPIO_MIS_DIO25_S 25U 891 #define GPIO_MIS_DIO25_SET 0x02000000U 892 #define GPIO_MIS_DIO25_CLR 0x00000000U 893 894 // Field: [24] DIO24 895 // 896 // Masked interrupt flag for DIO24 897 // ENUMs: 898 // SET Interrupt occured 899 // CLR Interrupt did not occur 900 #define GPIO_MIS_DIO24 0x01000000U 901 #define GPIO_MIS_DIO24_M 0x01000000U 902 #define GPIO_MIS_DIO24_S 24U 903 #define GPIO_MIS_DIO24_SET 0x01000000U 904 #define GPIO_MIS_DIO24_CLR 0x00000000U 905 906 // Field: [23] DIO23 907 // 908 // Masked interrupt flag for DIO23 909 // ENUMs: 910 // SET Interrupt occured 911 // CLR Interrupt did not occur 912 #define GPIO_MIS_DIO23 0x00800000U 913 #define GPIO_MIS_DIO23_M 0x00800000U 914 #define GPIO_MIS_DIO23_S 23U 915 #define GPIO_MIS_DIO23_SET 0x00800000U 916 #define GPIO_MIS_DIO23_CLR 0x00000000U 917 918 // Field: [22] DIO22 919 // 920 // Masked interrupt flag for DIO22 921 // ENUMs: 922 // SET Interrupt occured 923 // CLR Interrupt did not occur 924 #define GPIO_MIS_DIO22 0x00400000U 925 #define GPIO_MIS_DIO22_M 0x00400000U 926 #define GPIO_MIS_DIO22_S 22U 927 #define GPIO_MIS_DIO22_SET 0x00400000U 928 #define GPIO_MIS_DIO22_CLR 0x00000000U 929 930 // Field: [21] DIO21 931 // 932 // Masked interrupt flag for DIO21 933 // ENUMs: 934 // SET Interrupt occured 935 // CLR Interrupt did not occur 936 #define GPIO_MIS_DIO21 0x00200000U 937 #define GPIO_MIS_DIO21_M 0x00200000U 938 #define GPIO_MIS_DIO21_S 21U 939 #define GPIO_MIS_DIO21_SET 0x00200000U 940 #define GPIO_MIS_DIO21_CLR 0x00000000U 941 942 // Field: [20] DIO20 943 // 944 // Masked interrupt flag for DIO20 945 // ENUMs: 946 // SET Interrupt occured 947 // CLR Interrupt did not occur 948 #define GPIO_MIS_DIO20 0x00100000U 949 #define GPIO_MIS_DIO20_M 0x00100000U 950 #define GPIO_MIS_DIO20_S 20U 951 #define GPIO_MIS_DIO20_SET 0x00100000U 952 #define GPIO_MIS_DIO20_CLR 0x00000000U 953 954 // Field: [19] DIO19 955 // 956 // Masked interrupt flag for DIO19 957 // ENUMs: 958 // SET Interrupt occured 959 // CLR Interrupt did not occur 960 #define GPIO_MIS_DIO19 0x00080000U 961 #define GPIO_MIS_DIO19_M 0x00080000U 962 #define GPIO_MIS_DIO19_S 19U 963 #define GPIO_MIS_DIO19_SET 0x00080000U 964 #define GPIO_MIS_DIO19_CLR 0x00000000U 965 966 // Field: [18] DIO18 967 // 968 // Masked interrupt flag for DIO18 969 // ENUMs: 970 // SET Interrupt occured 971 // CLR Interrupt did not occur 972 #define GPIO_MIS_DIO18 0x00040000U 973 #define GPIO_MIS_DIO18_M 0x00040000U 974 #define GPIO_MIS_DIO18_S 18U 975 #define GPIO_MIS_DIO18_SET 0x00040000U 976 #define GPIO_MIS_DIO18_CLR 0x00000000U 977 978 // Field: [17] DIO17 979 // 980 // Masked interrupt flag for DIO17 981 // ENUMs: 982 // SET Interrupt occured 983 // CLR Interrupt did not occur 984 #define GPIO_MIS_DIO17 0x00020000U 985 #define GPIO_MIS_DIO17_M 0x00020000U 986 #define GPIO_MIS_DIO17_S 17U 987 #define GPIO_MIS_DIO17_SET 0x00020000U 988 #define GPIO_MIS_DIO17_CLR 0x00000000U 989 990 // Field: [16] DIO16 991 // 992 // Masked interrupt flag for DIO16 993 // ENUMs: 994 // SET Interrupt occured 995 // CLR Interrupt did not occur 996 #define GPIO_MIS_DIO16 0x00010000U 997 #define GPIO_MIS_DIO16_M 0x00010000U 998 #define GPIO_MIS_DIO16_S 16U 999 #define GPIO_MIS_DIO16_SET 0x00010000U 1000 #define GPIO_MIS_DIO16_CLR 0x00000000U 1001 1002 // Field: [15] DIO15 1003 // 1004 // Masked interrupt flag for DIO15 1005 // ENUMs: 1006 // SET Interrupt occured 1007 // CLR Interrupt did not occur 1008 #define GPIO_MIS_DIO15 0x00008000U 1009 #define GPIO_MIS_DIO15_M 0x00008000U 1010 #define GPIO_MIS_DIO15_S 15U 1011 #define GPIO_MIS_DIO15_SET 0x00008000U 1012 #define GPIO_MIS_DIO15_CLR 0x00000000U 1013 1014 // Field: [14] DIO14 1015 // 1016 // Masked interrupt flag for DIO14 1017 // ENUMs: 1018 // SET Interrupt occured 1019 // CLR Interrupt did not occur 1020 #define GPIO_MIS_DIO14 0x00004000U 1021 #define GPIO_MIS_DIO14_M 0x00004000U 1022 #define GPIO_MIS_DIO14_S 14U 1023 #define GPIO_MIS_DIO14_SET 0x00004000U 1024 #define GPIO_MIS_DIO14_CLR 0x00000000U 1025 1026 // Field: [13] DIO13 1027 // 1028 // Masked interrupt flag for DIO13 1029 // ENUMs: 1030 // SET Interrupt occured 1031 // CLR Interrupt did not occur 1032 #define GPIO_MIS_DIO13 0x00002000U 1033 #define GPIO_MIS_DIO13_M 0x00002000U 1034 #define GPIO_MIS_DIO13_S 13U 1035 #define GPIO_MIS_DIO13_SET 0x00002000U 1036 #define GPIO_MIS_DIO13_CLR 0x00000000U 1037 1038 // Field: [12] DIO12 1039 // 1040 // Masked interrupt flag for DIO12 1041 // ENUMs: 1042 // SET Interrupt occured 1043 // CLR Interrupt did not occur 1044 #define GPIO_MIS_DIO12 0x00001000U 1045 #define GPIO_MIS_DIO12_M 0x00001000U 1046 #define GPIO_MIS_DIO12_S 12U 1047 #define GPIO_MIS_DIO12_SET 0x00001000U 1048 #define GPIO_MIS_DIO12_CLR 0x00000000U 1049 1050 // Field: [11] DIO11 1051 // 1052 // Masked interrupt flag for DIO11 1053 // ENUMs: 1054 // SET Interrupt occured 1055 // CLR Interrupt did not occur 1056 #define GPIO_MIS_DIO11 0x00000800U 1057 #define GPIO_MIS_DIO11_M 0x00000800U 1058 #define GPIO_MIS_DIO11_S 11U 1059 #define GPIO_MIS_DIO11_SET 0x00000800U 1060 #define GPIO_MIS_DIO11_CLR 0x00000000U 1061 1062 // Field: [10] DIO10 1063 // 1064 // Masked interrupt flag for DIO10 1065 // ENUMs: 1066 // SET Interrupt occured 1067 // CLR Interrupt did not occur 1068 #define GPIO_MIS_DIO10 0x00000400U 1069 #define GPIO_MIS_DIO10_M 0x00000400U 1070 #define GPIO_MIS_DIO10_S 10U 1071 #define GPIO_MIS_DIO10_SET 0x00000400U 1072 #define GPIO_MIS_DIO10_CLR 0x00000000U 1073 1074 // Field: [9] DIO9 1075 // 1076 // Masked interrupt flag for DIO9 1077 // ENUMs: 1078 // SET Interrupt occured 1079 // CLR Interrupt did not occur 1080 #define GPIO_MIS_DIO9 0x00000200U 1081 #define GPIO_MIS_DIO9_M 0x00000200U 1082 #define GPIO_MIS_DIO9_S 9U 1083 #define GPIO_MIS_DIO9_SET 0x00000200U 1084 #define GPIO_MIS_DIO9_CLR 0x00000000U 1085 1086 // Field: [8] DIO8 1087 // 1088 // Masked interrupt flag for DIO8 1089 // ENUMs: 1090 // SET Interrupt occured 1091 // CLR Interrupt did not occur 1092 #define GPIO_MIS_DIO8 0x00000100U 1093 #define GPIO_MIS_DIO8_M 0x00000100U 1094 #define GPIO_MIS_DIO8_S 8U 1095 #define GPIO_MIS_DIO8_SET 0x00000100U 1096 #define GPIO_MIS_DIO8_CLR 0x00000000U 1097 1098 // Field: [7] DIO7 1099 // 1100 // Masked interrupt flag for DIO7 1101 // ENUMs: 1102 // SET Interrupt occured 1103 // CLR Interrupt did not occur 1104 #define GPIO_MIS_DIO7 0x00000080U 1105 #define GPIO_MIS_DIO7_M 0x00000080U 1106 #define GPIO_MIS_DIO7_S 7U 1107 #define GPIO_MIS_DIO7_SET 0x00000080U 1108 #define GPIO_MIS_DIO7_CLR 0x00000000U 1109 1110 // Field: [6] DIO6 1111 // 1112 // Masked interrupt flag for DIO6 1113 // ENUMs: 1114 // SET Interrupt occured 1115 // CLR Interrupt did not occur 1116 #define GPIO_MIS_DIO6 0x00000040U 1117 #define GPIO_MIS_DIO6_M 0x00000040U 1118 #define GPIO_MIS_DIO6_S 6U 1119 #define GPIO_MIS_DIO6_SET 0x00000040U 1120 #define GPIO_MIS_DIO6_CLR 0x00000000U 1121 1122 // Field: [5] DIO5 1123 // 1124 // Masked interrupt flag for DIO5 1125 // ENUMs: 1126 // SET Interrupt occured 1127 // CLR Interrupt did not occur 1128 #define GPIO_MIS_DIO5 0x00000020U 1129 #define GPIO_MIS_DIO5_M 0x00000020U 1130 #define GPIO_MIS_DIO5_S 5U 1131 #define GPIO_MIS_DIO5_SET 0x00000020U 1132 #define GPIO_MIS_DIO5_CLR 0x00000000U 1133 1134 // Field: [4] DIO4 1135 // 1136 // Masked interrupt flag for DIO4 1137 // ENUMs: 1138 // SET Interrupt occured 1139 // CLR Interrupt did not occur 1140 #define GPIO_MIS_DIO4 0x00000010U 1141 #define GPIO_MIS_DIO4_M 0x00000010U 1142 #define GPIO_MIS_DIO4_S 4U 1143 #define GPIO_MIS_DIO4_SET 0x00000010U 1144 #define GPIO_MIS_DIO4_CLR 0x00000000U 1145 1146 // Field: [3] DIO3 1147 // 1148 // Masked interrupt flag for DIO3 1149 // ENUMs: 1150 // SET Interrupt occured 1151 // CLR Interrupt did not occur 1152 #define GPIO_MIS_DIO3 0x00000008U 1153 #define GPIO_MIS_DIO3_M 0x00000008U 1154 #define GPIO_MIS_DIO3_S 3U 1155 #define GPIO_MIS_DIO3_SET 0x00000008U 1156 #define GPIO_MIS_DIO3_CLR 0x00000000U 1157 1158 // Field: [2] DIO2 1159 // 1160 // Masked interrupt flag for DIO2 1161 // ENUMs: 1162 // SET Interrupt occured 1163 // CLR Interrupt did not occur 1164 #define GPIO_MIS_DIO2 0x00000004U 1165 #define GPIO_MIS_DIO2_M 0x00000004U 1166 #define GPIO_MIS_DIO2_S 2U 1167 #define GPIO_MIS_DIO2_SET 0x00000004U 1168 #define GPIO_MIS_DIO2_CLR 0x00000000U 1169 1170 // Field: [1] DIO1 1171 // 1172 // Masked interrupt flag for DIO1 1173 // ENUMs: 1174 // SET Interrupt occured 1175 // CLR Interrupt did not occur 1176 #define GPIO_MIS_DIO1 0x00000002U 1177 #define GPIO_MIS_DIO1_M 0x00000002U 1178 #define GPIO_MIS_DIO1_S 1U 1179 #define GPIO_MIS_DIO1_SET 0x00000002U 1180 #define GPIO_MIS_DIO1_CLR 0x00000000U 1181 1182 // Field: [0] DIO0 1183 // 1184 // Masked interrupt flag for DIO0 1185 // ENUMs: 1186 // SET Interrupt occured 1187 // CLR Interrupt did not occur 1188 #define GPIO_MIS_DIO0 0x00000001U 1189 #define GPIO_MIS_DIO0_M 0x00000001U 1190 #define GPIO_MIS_DIO0_S 0U 1191 #define GPIO_MIS_DIO0_SET 0x00000001U 1192 #define GPIO_MIS_DIO0_CLR 0x00000000U 1193 1194 //***************************************************************************** 1195 // 1196 // Register: GPIO_O_ISET 1197 // 1198 //***************************************************************************** 1199 // Field: [25] DIO25 1200 // 1201 // Set DIO25 in RIS 1202 // ENUMs: 1203 // SET Set Interrupt 1204 // NOEFF Writing 0 has no effect 1205 #define GPIO_ISET_DIO25 0x02000000U 1206 #define GPIO_ISET_DIO25_M 0x02000000U 1207 #define GPIO_ISET_DIO25_S 25U 1208 #define GPIO_ISET_DIO25_SET 0x02000000U 1209 #define GPIO_ISET_DIO25_NOEFF 0x00000000U 1210 1211 // Field: [24] DIO24 1212 // 1213 // Set DIO24 in RIS 1214 // ENUMs: 1215 // SET Set Interrupt 1216 // NOEFF Writing 0 has no effect 1217 #define GPIO_ISET_DIO24 0x01000000U 1218 #define GPIO_ISET_DIO24_M 0x01000000U 1219 #define GPIO_ISET_DIO24_S 24U 1220 #define GPIO_ISET_DIO24_SET 0x01000000U 1221 #define GPIO_ISET_DIO24_NOEFF 0x00000000U 1222 1223 // Field: [23] DIO23 1224 // 1225 // Set DIO23 in RIS 1226 // ENUMs: 1227 // SET Set Interrupt 1228 // NOEFF Writing 0 has no effect 1229 #define GPIO_ISET_DIO23 0x00800000U 1230 #define GPIO_ISET_DIO23_M 0x00800000U 1231 #define GPIO_ISET_DIO23_S 23U 1232 #define GPIO_ISET_DIO23_SET 0x00800000U 1233 #define GPIO_ISET_DIO23_NOEFF 0x00000000U 1234 1235 // Field: [22] DIO22 1236 // 1237 // Set DIO22 in RIS 1238 // ENUMs: 1239 // SET Set Interrupt 1240 // NOEFF Writing 0 has no effect 1241 #define GPIO_ISET_DIO22 0x00400000U 1242 #define GPIO_ISET_DIO22_M 0x00400000U 1243 #define GPIO_ISET_DIO22_S 22U 1244 #define GPIO_ISET_DIO22_SET 0x00400000U 1245 #define GPIO_ISET_DIO22_NOEFF 0x00000000U 1246 1247 // Field: [21] DIO21 1248 // 1249 // Set DIO21 in RIS 1250 // ENUMs: 1251 // SET Set Interrupt 1252 // NOEFF Writing 0 has no effect 1253 #define GPIO_ISET_DIO21 0x00200000U 1254 #define GPIO_ISET_DIO21_M 0x00200000U 1255 #define GPIO_ISET_DIO21_S 21U 1256 #define GPIO_ISET_DIO21_SET 0x00200000U 1257 #define GPIO_ISET_DIO21_NOEFF 0x00000000U 1258 1259 // Field: [20] DIO20 1260 // 1261 // Set DIO20 in RIS 1262 // ENUMs: 1263 // SET Set Interrupt 1264 // NOEFF Writing 0 has no effect 1265 #define GPIO_ISET_DIO20 0x00100000U 1266 #define GPIO_ISET_DIO20_M 0x00100000U 1267 #define GPIO_ISET_DIO20_S 20U 1268 #define GPIO_ISET_DIO20_SET 0x00100000U 1269 #define GPIO_ISET_DIO20_NOEFF 0x00000000U 1270 1271 // Field: [19] DIO19 1272 // 1273 // Set DIO19 in RIS 1274 // ENUMs: 1275 // SET Set Interrupt 1276 // NOEFF Writing 0 has no effect 1277 #define GPIO_ISET_DIO19 0x00080000U 1278 #define GPIO_ISET_DIO19_M 0x00080000U 1279 #define GPIO_ISET_DIO19_S 19U 1280 #define GPIO_ISET_DIO19_SET 0x00080000U 1281 #define GPIO_ISET_DIO19_NOEFF 0x00000000U 1282 1283 // Field: [18] DIO18 1284 // 1285 // Set DIO18 in RIS 1286 // ENUMs: 1287 // SET Set Interrupt 1288 // NOEFF Writing 0 has no effect 1289 #define GPIO_ISET_DIO18 0x00040000U 1290 #define GPIO_ISET_DIO18_M 0x00040000U 1291 #define GPIO_ISET_DIO18_S 18U 1292 #define GPIO_ISET_DIO18_SET 0x00040000U 1293 #define GPIO_ISET_DIO18_NOEFF 0x00000000U 1294 1295 // Field: [17] DIO17 1296 // 1297 // Set DIO17 in RIS 1298 // ENUMs: 1299 // SET Set Interrupt 1300 // NOEFF Writing 0 has no effect 1301 #define GPIO_ISET_DIO17 0x00020000U 1302 #define GPIO_ISET_DIO17_M 0x00020000U 1303 #define GPIO_ISET_DIO17_S 17U 1304 #define GPIO_ISET_DIO17_SET 0x00020000U 1305 #define GPIO_ISET_DIO17_NOEFF 0x00000000U 1306 1307 // Field: [16] DIO16 1308 // 1309 // Set DIO16 in RIS 1310 // ENUMs: 1311 // SET Set Interrupt 1312 // NOEFF Writing 0 has no effect 1313 #define GPIO_ISET_DIO16 0x00010000U 1314 #define GPIO_ISET_DIO16_M 0x00010000U 1315 #define GPIO_ISET_DIO16_S 16U 1316 #define GPIO_ISET_DIO16_SET 0x00010000U 1317 #define GPIO_ISET_DIO16_NOEFF 0x00000000U 1318 1319 // Field: [15] DIO15 1320 // 1321 // Set DIO15 in RIS 1322 // ENUMs: 1323 // SET Set Interrupt 1324 // NOEFF Writing 0 has no effect 1325 #define GPIO_ISET_DIO15 0x00008000U 1326 #define GPIO_ISET_DIO15_M 0x00008000U 1327 #define GPIO_ISET_DIO15_S 15U 1328 #define GPIO_ISET_DIO15_SET 0x00008000U 1329 #define GPIO_ISET_DIO15_NOEFF 0x00000000U 1330 1331 // Field: [14] DIO14 1332 // 1333 // Set DIO14 in RIS 1334 // ENUMs: 1335 // SET Set Interrupt 1336 // NOEFF Writing 0 has no effect 1337 #define GPIO_ISET_DIO14 0x00004000U 1338 #define GPIO_ISET_DIO14_M 0x00004000U 1339 #define GPIO_ISET_DIO14_S 14U 1340 #define GPIO_ISET_DIO14_SET 0x00004000U 1341 #define GPIO_ISET_DIO14_NOEFF 0x00000000U 1342 1343 // Field: [13] DIO13 1344 // 1345 // Set DIO13 in RIS 1346 // ENUMs: 1347 // SET Set Interrupt 1348 // NOEFF Writing 0 has no effect 1349 #define GPIO_ISET_DIO13 0x00002000U 1350 #define GPIO_ISET_DIO13_M 0x00002000U 1351 #define GPIO_ISET_DIO13_S 13U 1352 #define GPIO_ISET_DIO13_SET 0x00002000U 1353 #define GPIO_ISET_DIO13_NOEFF 0x00000000U 1354 1355 // Field: [12] DIO12 1356 // 1357 // Set DIO12 in RIS 1358 // ENUMs: 1359 // SET Set Interrupt 1360 // NOEFF Writing 0 has no effect 1361 #define GPIO_ISET_DIO12 0x00001000U 1362 #define GPIO_ISET_DIO12_M 0x00001000U 1363 #define GPIO_ISET_DIO12_S 12U 1364 #define GPIO_ISET_DIO12_SET 0x00001000U 1365 #define GPIO_ISET_DIO12_NOEFF 0x00000000U 1366 1367 // Field: [11] DIO11 1368 // 1369 // Set DIO11 in RIS 1370 // ENUMs: 1371 // SET Set Interrupt 1372 // NOEFF Writing 0 has no effect 1373 #define GPIO_ISET_DIO11 0x00000800U 1374 #define GPIO_ISET_DIO11_M 0x00000800U 1375 #define GPIO_ISET_DIO11_S 11U 1376 #define GPIO_ISET_DIO11_SET 0x00000800U 1377 #define GPIO_ISET_DIO11_NOEFF 0x00000000U 1378 1379 // Field: [10] DIO10 1380 // 1381 // Set DIO10 in RIS 1382 // ENUMs: 1383 // SET Set Interrupt 1384 // NOEFF Writing 0 has no effect 1385 #define GPIO_ISET_DIO10 0x00000400U 1386 #define GPIO_ISET_DIO10_M 0x00000400U 1387 #define GPIO_ISET_DIO10_S 10U 1388 #define GPIO_ISET_DIO10_SET 0x00000400U 1389 #define GPIO_ISET_DIO10_NOEFF 0x00000000U 1390 1391 // Field: [9] DIO9 1392 // 1393 // Set DIO9 in RIS 1394 // ENUMs: 1395 // SET Set Interrupt 1396 // NOEFF Writing 0 has no effect 1397 #define GPIO_ISET_DIO9 0x00000200U 1398 #define GPIO_ISET_DIO9_M 0x00000200U 1399 #define GPIO_ISET_DIO9_S 9U 1400 #define GPIO_ISET_DIO9_SET 0x00000200U 1401 #define GPIO_ISET_DIO9_NOEFF 0x00000000U 1402 1403 // Field: [8] DIO8 1404 // 1405 // Set DIO8 in RIS 1406 // ENUMs: 1407 // SET Set Interrupt 1408 // NOEFF Writing 0 has no effect 1409 #define GPIO_ISET_DIO8 0x00000100U 1410 #define GPIO_ISET_DIO8_M 0x00000100U 1411 #define GPIO_ISET_DIO8_S 8U 1412 #define GPIO_ISET_DIO8_SET 0x00000100U 1413 #define GPIO_ISET_DIO8_NOEFF 0x00000000U 1414 1415 // Field: [7] DIO7 1416 // 1417 // Set DIO7 in RIS 1418 // ENUMs: 1419 // SET Set Interrupt 1420 // NOEFF Writing 0 has no effect 1421 #define GPIO_ISET_DIO7 0x00000080U 1422 #define GPIO_ISET_DIO7_M 0x00000080U 1423 #define GPIO_ISET_DIO7_S 7U 1424 #define GPIO_ISET_DIO7_SET 0x00000080U 1425 #define GPIO_ISET_DIO7_NOEFF 0x00000000U 1426 1427 // Field: [6] DIO6 1428 // 1429 // Set DIO6 in RIS 1430 // ENUMs: 1431 // SET Set Interrupt 1432 // NOEFF Writing 0 has no effect 1433 #define GPIO_ISET_DIO6 0x00000040U 1434 #define GPIO_ISET_DIO6_M 0x00000040U 1435 #define GPIO_ISET_DIO6_S 6U 1436 #define GPIO_ISET_DIO6_SET 0x00000040U 1437 #define GPIO_ISET_DIO6_NOEFF 0x00000000U 1438 1439 // Field: [5] DIO5 1440 // 1441 // Set DIO5 in RIS 1442 // ENUMs: 1443 // SET Set Interrupt 1444 // NOEFF Writing 0 has no effect 1445 #define GPIO_ISET_DIO5 0x00000020U 1446 #define GPIO_ISET_DIO5_M 0x00000020U 1447 #define GPIO_ISET_DIO5_S 5U 1448 #define GPIO_ISET_DIO5_SET 0x00000020U 1449 #define GPIO_ISET_DIO5_NOEFF 0x00000000U 1450 1451 // Field: [4] DIO4 1452 // 1453 // Set DIO4 in RIS 1454 // ENUMs: 1455 // SET Set Interrupt 1456 // NOEFF Writing 0 has no effect 1457 #define GPIO_ISET_DIO4 0x00000010U 1458 #define GPIO_ISET_DIO4_M 0x00000010U 1459 #define GPIO_ISET_DIO4_S 4U 1460 #define GPIO_ISET_DIO4_SET 0x00000010U 1461 #define GPIO_ISET_DIO4_NOEFF 0x00000000U 1462 1463 // Field: [3] DIO3 1464 // 1465 // Set DIO3 in RIS 1466 // ENUMs: 1467 // SET Set Interrupt 1468 // NOEFF Writing 0 has no effect 1469 #define GPIO_ISET_DIO3 0x00000008U 1470 #define GPIO_ISET_DIO3_M 0x00000008U 1471 #define GPIO_ISET_DIO3_S 3U 1472 #define GPIO_ISET_DIO3_SET 0x00000008U 1473 #define GPIO_ISET_DIO3_NOEFF 0x00000000U 1474 1475 // Field: [2] DIO2 1476 // 1477 // Set DIO2 in RIS 1478 // ENUMs: 1479 // SET Set Interrupt 1480 // NOEFF Writing 0 has no effect 1481 #define GPIO_ISET_DIO2 0x00000004U 1482 #define GPIO_ISET_DIO2_M 0x00000004U 1483 #define GPIO_ISET_DIO2_S 2U 1484 #define GPIO_ISET_DIO2_SET 0x00000004U 1485 #define GPIO_ISET_DIO2_NOEFF 0x00000000U 1486 1487 // Field: [1] DIO1 1488 // 1489 // Set DIO1 in RIS 1490 // ENUMs: 1491 // SET Set Interrupt 1492 // NOEFF Writing 0 has no effect 1493 #define GPIO_ISET_DIO1 0x00000002U 1494 #define GPIO_ISET_DIO1_M 0x00000002U 1495 #define GPIO_ISET_DIO1_S 1U 1496 #define GPIO_ISET_DIO1_SET 0x00000002U 1497 #define GPIO_ISET_DIO1_NOEFF 0x00000000U 1498 1499 // Field: [0] DIO0 1500 // 1501 // Set DIO0 in RIS 1502 // ENUMs: 1503 // SET Set Interrupt 1504 // NOEFF Writing 0 has no effect 1505 #define GPIO_ISET_DIO0 0x00000001U 1506 #define GPIO_ISET_DIO0_M 0x00000001U 1507 #define GPIO_ISET_DIO0_S 0U 1508 #define GPIO_ISET_DIO0_SET 0x00000001U 1509 #define GPIO_ISET_DIO0_NOEFF 0x00000000U 1510 1511 //***************************************************************************** 1512 // 1513 // Register: GPIO_O_ICLR 1514 // 1515 //***************************************************************************** 1516 // Field: [25] DIO25 1517 // 1518 // Clears DIO25 in RIS 1519 // ENUMs: 1520 // CLR Clear Interrupt 1521 // NOEFF Writing 0 has no effect 1522 #define GPIO_ICLR_DIO25 0x02000000U 1523 #define GPIO_ICLR_DIO25_M 0x02000000U 1524 #define GPIO_ICLR_DIO25_S 25U 1525 #define GPIO_ICLR_DIO25_CLR 0x02000000U 1526 #define GPIO_ICLR_DIO25_NOEFF 0x00000000U 1527 1528 // Field: [24] DIO24 1529 // 1530 // Clears DIO24 in RIS 1531 // ENUMs: 1532 // CLR Clear Interrupt 1533 // NOEFF Writing 0 has no effect 1534 #define GPIO_ICLR_DIO24 0x01000000U 1535 #define GPIO_ICLR_DIO24_M 0x01000000U 1536 #define GPIO_ICLR_DIO24_S 24U 1537 #define GPIO_ICLR_DIO24_CLR 0x01000000U 1538 #define GPIO_ICLR_DIO24_NOEFF 0x00000000U 1539 1540 // Field: [23] DIO23 1541 // 1542 // Clears DIO23 in RIS 1543 // ENUMs: 1544 // CLR Clear Interrupt 1545 // NOEFF Writing 0 has no effect 1546 #define GPIO_ICLR_DIO23 0x00800000U 1547 #define GPIO_ICLR_DIO23_M 0x00800000U 1548 #define GPIO_ICLR_DIO23_S 23U 1549 #define GPIO_ICLR_DIO23_CLR 0x00800000U 1550 #define GPIO_ICLR_DIO23_NOEFF 0x00000000U 1551 1552 // Field: [22] DIO22 1553 // 1554 // Clears DIO22 in RIS 1555 // ENUMs: 1556 // CLR Clear Interrupt 1557 // NOEFF Writing 0 has no effect 1558 #define GPIO_ICLR_DIO22 0x00400000U 1559 #define GPIO_ICLR_DIO22_M 0x00400000U 1560 #define GPIO_ICLR_DIO22_S 22U 1561 #define GPIO_ICLR_DIO22_CLR 0x00400000U 1562 #define GPIO_ICLR_DIO22_NOEFF 0x00000000U 1563 1564 // Field: [21] DIO21 1565 // 1566 // Clears DIO21 in RIS 1567 // ENUMs: 1568 // CLR Clear Interrupt 1569 // NOEFF Writing 0 has no effect 1570 #define GPIO_ICLR_DIO21 0x00200000U 1571 #define GPIO_ICLR_DIO21_M 0x00200000U 1572 #define GPIO_ICLR_DIO21_S 21U 1573 #define GPIO_ICLR_DIO21_CLR 0x00200000U 1574 #define GPIO_ICLR_DIO21_NOEFF 0x00000000U 1575 1576 // Field: [20] DIO20 1577 // 1578 // Clears DIO20 in RIS 1579 // ENUMs: 1580 // CLR Clear Interrupt 1581 // NOEFF Writing 0 has no effect 1582 #define GPIO_ICLR_DIO20 0x00100000U 1583 #define GPIO_ICLR_DIO20_M 0x00100000U 1584 #define GPIO_ICLR_DIO20_S 20U 1585 #define GPIO_ICLR_DIO20_CLR 0x00100000U 1586 #define GPIO_ICLR_DIO20_NOEFF 0x00000000U 1587 1588 // Field: [19] DIO19 1589 // 1590 // Clears DIO19 in RIS 1591 // ENUMs: 1592 // CLR Clear Interrupt 1593 // NOEFF Writing 0 has no effect 1594 #define GPIO_ICLR_DIO19 0x00080000U 1595 #define GPIO_ICLR_DIO19_M 0x00080000U 1596 #define GPIO_ICLR_DIO19_S 19U 1597 #define GPIO_ICLR_DIO19_CLR 0x00080000U 1598 #define GPIO_ICLR_DIO19_NOEFF 0x00000000U 1599 1600 // Field: [18] DIO18 1601 // 1602 // Clears DIO18 in RIS 1603 // ENUMs: 1604 // CLR Clear Interrupt 1605 // NOEFF Writing 0 has no effect 1606 #define GPIO_ICLR_DIO18 0x00040000U 1607 #define GPIO_ICLR_DIO18_M 0x00040000U 1608 #define GPIO_ICLR_DIO18_S 18U 1609 #define GPIO_ICLR_DIO18_CLR 0x00040000U 1610 #define GPIO_ICLR_DIO18_NOEFF 0x00000000U 1611 1612 // Field: [17] DIO17 1613 // 1614 // Clears DIO17 in RIS 1615 // ENUMs: 1616 // CLR Clear Interrupt 1617 // NOEFF Writing 0 has no effect 1618 #define GPIO_ICLR_DIO17 0x00020000U 1619 #define GPIO_ICLR_DIO17_M 0x00020000U 1620 #define GPIO_ICLR_DIO17_S 17U 1621 #define GPIO_ICLR_DIO17_CLR 0x00020000U 1622 #define GPIO_ICLR_DIO17_NOEFF 0x00000000U 1623 1624 // Field: [16] DIO16 1625 // 1626 // Clears DIO16 in RIS 1627 // ENUMs: 1628 // CLR Clear Interrupt 1629 // NOEFF Writing 0 has no effect 1630 #define GPIO_ICLR_DIO16 0x00010000U 1631 #define GPIO_ICLR_DIO16_M 0x00010000U 1632 #define GPIO_ICLR_DIO16_S 16U 1633 #define GPIO_ICLR_DIO16_CLR 0x00010000U 1634 #define GPIO_ICLR_DIO16_NOEFF 0x00000000U 1635 1636 // Field: [15] DIO15 1637 // 1638 // Clears DIO15 in RIS 1639 // ENUMs: 1640 // CLR Clear Interrupt 1641 // NOEFF Writing 0 has no effect 1642 #define GPIO_ICLR_DIO15 0x00008000U 1643 #define GPIO_ICLR_DIO15_M 0x00008000U 1644 #define GPIO_ICLR_DIO15_S 15U 1645 #define GPIO_ICLR_DIO15_CLR 0x00008000U 1646 #define GPIO_ICLR_DIO15_NOEFF 0x00000000U 1647 1648 // Field: [14] DIO14 1649 // 1650 // Clears DIO14 in RIS 1651 // ENUMs: 1652 // CLR Clear Interrupt 1653 // NOEFF Writing 0 has no effect 1654 #define GPIO_ICLR_DIO14 0x00004000U 1655 #define GPIO_ICLR_DIO14_M 0x00004000U 1656 #define GPIO_ICLR_DIO14_S 14U 1657 #define GPIO_ICLR_DIO14_CLR 0x00004000U 1658 #define GPIO_ICLR_DIO14_NOEFF 0x00000000U 1659 1660 // Field: [13] DIO13 1661 // 1662 // Clears DIO13 in RIS 1663 // ENUMs: 1664 // CLR Clear Interrupt 1665 // NOEFF Writing 0 has no effect 1666 #define GPIO_ICLR_DIO13 0x00002000U 1667 #define GPIO_ICLR_DIO13_M 0x00002000U 1668 #define GPIO_ICLR_DIO13_S 13U 1669 #define GPIO_ICLR_DIO13_CLR 0x00002000U 1670 #define GPIO_ICLR_DIO13_NOEFF 0x00000000U 1671 1672 // Field: [12] DIO12 1673 // 1674 // Clears DIO12 in RIS 1675 // ENUMs: 1676 // CLR Clear Interrupt 1677 // NOEFF Writing 0 has no effect 1678 #define GPIO_ICLR_DIO12 0x00001000U 1679 #define GPIO_ICLR_DIO12_M 0x00001000U 1680 #define GPIO_ICLR_DIO12_S 12U 1681 #define GPIO_ICLR_DIO12_CLR 0x00001000U 1682 #define GPIO_ICLR_DIO12_NOEFF 0x00000000U 1683 1684 // Field: [11] DIO11 1685 // 1686 // Clears DIO11 in RIS 1687 // ENUMs: 1688 // CLR Clear Interrupt 1689 // NOEFF Writing 0 has no effect 1690 #define GPIO_ICLR_DIO11 0x00000800U 1691 #define GPIO_ICLR_DIO11_M 0x00000800U 1692 #define GPIO_ICLR_DIO11_S 11U 1693 #define GPIO_ICLR_DIO11_CLR 0x00000800U 1694 #define GPIO_ICLR_DIO11_NOEFF 0x00000000U 1695 1696 // Field: [10] DIO10 1697 // 1698 // Clears DIO10 in RIS 1699 // ENUMs: 1700 // CLR Clear Interrupt 1701 // NOEFF Writing 0 has no effect 1702 #define GPIO_ICLR_DIO10 0x00000400U 1703 #define GPIO_ICLR_DIO10_M 0x00000400U 1704 #define GPIO_ICLR_DIO10_S 10U 1705 #define GPIO_ICLR_DIO10_CLR 0x00000400U 1706 #define GPIO_ICLR_DIO10_NOEFF 0x00000000U 1707 1708 // Field: [9] DIO9 1709 // 1710 // Clears DIO9 in RIS 1711 // ENUMs: 1712 // CLR Clear Interrupt 1713 // NOEFF Writing 0 has no effect 1714 #define GPIO_ICLR_DIO9 0x00000200U 1715 #define GPIO_ICLR_DIO9_M 0x00000200U 1716 #define GPIO_ICLR_DIO9_S 9U 1717 #define GPIO_ICLR_DIO9_CLR 0x00000200U 1718 #define GPIO_ICLR_DIO9_NOEFF 0x00000000U 1719 1720 // Field: [8] DIO8 1721 // 1722 // Clears DIO8 in RIS 1723 // ENUMs: 1724 // CLR Clear Interrupt 1725 // NOEFF Writing 0 has no effect 1726 #define GPIO_ICLR_DIO8 0x00000100U 1727 #define GPIO_ICLR_DIO8_M 0x00000100U 1728 #define GPIO_ICLR_DIO8_S 8U 1729 #define GPIO_ICLR_DIO8_CLR 0x00000100U 1730 #define GPIO_ICLR_DIO8_NOEFF 0x00000000U 1731 1732 // Field: [7] DIO7 1733 // 1734 // Clears DIO7 in RIS 1735 // ENUMs: 1736 // CLR Clear Interrupt 1737 // NOEFF Writing 0 has no effect 1738 #define GPIO_ICLR_DIO7 0x00000080U 1739 #define GPIO_ICLR_DIO7_M 0x00000080U 1740 #define GPIO_ICLR_DIO7_S 7U 1741 #define GPIO_ICLR_DIO7_CLR 0x00000080U 1742 #define GPIO_ICLR_DIO7_NOEFF 0x00000000U 1743 1744 // Field: [6] DIO6 1745 // 1746 // Clears DIO6 in RIS 1747 // ENUMs: 1748 // CLR Clear Interrupt 1749 // NOEFF Writing 0 has no effect 1750 #define GPIO_ICLR_DIO6 0x00000040U 1751 #define GPIO_ICLR_DIO6_M 0x00000040U 1752 #define GPIO_ICLR_DIO6_S 6U 1753 #define GPIO_ICLR_DIO6_CLR 0x00000040U 1754 #define GPIO_ICLR_DIO6_NOEFF 0x00000000U 1755 1756 // Field: [5] DIO5 1757 // 1758 // Clears DIO5 in RIS 1759 // ENUMs: 1760 // CLR Clear Interrupt 1761 // NOEFF Writing 0 has no effect 1762 #define GPIO_ICLR_DIO5 0x00000020U 1763 #define GPIO_ICLR_DIO5_M 0x00000020U 1764 #define GPIO_ICLR_DIO5_S 5U 1765 #define GPIO_ICLR_DIO5_CLR 0x00000020U 1766 #define GPIO_ICLR_DIO5_NOEFF 0x00000000U 1767 1768 // Field: [4] DIO4 1769 // 1770 // Clears DIO4 in RIS 1771 // ENUMs: 1772 // CLR Clear Interrupt 1773 // NOEFF Writing 0 has no effect 1774 #define GPIO_ICLR_DIO4 0x00000010U 1775 #define GPIO_ICLR_DIO4_M 0x00000010U 1776 #define GPIO_ICLR_DIO4_S 4U 1777 #define GPIO_ICLR_DIO4_CLR 0x00000010U 1778 #define GPIO_ICLR_DIO4_NOEFF 0x00000000U 1779 1780 // Field: [3] DIO3 1781 // 1782 // Clears DIO3 in RIS 1783 // ENUMs: 1784 // CLR Clear Interrupt 1785 // NOEFF Writing 0 has no effect 1786 #define GPIO_ICLR_DIO3 0x00000008U 1787 #define GPIO_ICLR_DIO3_M 0x00000008U 1788 #define GPIO_ICLR_DIO3_S 3U 1789 #define GPIO_ICLR_DIO3_CLR 0x00000008U 1790 #define GPIO_ICLR_DIO3_NOEFF 0x00000000U 1791 1792 // Field: [2] DIO2 1793 // 1794 // Clears DIO2 in RIS 1795 // ENUMs: 1796 // CLR Clear Interrupt 1797 // NOEFF Writing 0 has no effect 1798 #define GPIO_ICLR_DIO2 0x00000004U 1799 #define GPIO_ICLR_DIO2_M 0x00000004U 1800 #define GPIO_ICLR_DIO2_S 2U 1801 #define GPIO_ICLR_DIO2_CLR 0x00000004U 1802 #define GPIO_ICLR_DIO2_NOEFF 0x00000000U 1803 1804 // Field: [1] DIO1 1805 // 1806 // Clears DIO1 in RIS 1807 // ENUMs: 1808 // CLR Clear Interrupt 1809 // NOEFF Writing 0 has no effect 1810 #define GPIO_ICLR_DIO1 0x00000002U 1811 #define GPIO_ICLR_DIO1_M 0x00000002U 1812 #define GPIO_ICLR_DIO1_S 1U 1813 #define GPIO_ICLR_DIO1_CLR 0x00000002U 1814 #define GPIO_ICLR_DIO1_NOEFF 0x00000000U 1815 1816 // Field: [0] DIO0 1817 // 1818 // Clears DIO0 in RIS 1819 // ENUMs: 1820 // CLR Clear Interrupt 1821 // NOEFF Writing 0 has no effect 1822 #define GPIO_ICLR_DIO0 0x00000001U 1823 #define GPIO_ICLR_DIO0_M 0x00000001U 1824 #define GPIO_ICLR_DIO0_S 0U 1825 #define GPIO_ICLR_DIO0_CLR 0x00000001U 1826 #define GPIO_ICLR_DIO0_NOEFF 0x00000000U 1827 1828 //***************************************************************************** 1829 // 1830 // Register: GPIO_O_IMSET 1831 // 1832 //***************************************************************************** 1833 // Field: [25] DIO25 1834 // 1835 // Sets DIO25 in IMASK 1836 // ENUMs: 1837 // SET Set interrupt mask 1838 // NOEFF Writing 0 has no effect 1839 #define GPIO_IMSET_DIO25 0x02000000U 1840 #define GPIO_IMSET_DIO25_M 0x02000000U 1841 #define GPIO_IMSET_DIO25_S 25U 1842 #define GPIO_IMSET_DIO25_SET 0x02000000U 1843 #define GPIO_IMSET_DIO25_NOEFF 0x00000000U 1844 1845 // Field: [24] DIO24 1846 // 1847 // Sets DIO24 in IMASK 1848 // ENUMs: 1849 // SET Set interrupt mask 1850 // NOEFF Writing 0 has no effect 1851 #define GPIO_IMSET_DIO24 0x01000000U 1852 #define GPIO_IMSET_DIO24_M 0x01000000U 1853 #define GPIO_IMSET_DIO24_S 24U 1854 #define GPIO_IMSET_DIO24_SET 0x01000000U 1855 #define GPIO_IMSET_DIO24_NOEFF 0x00000000U 1856 1857 // Field: [23] DIO23 1858 // 1859 // Sets DIO23 in IMASK 1860 // ENUMs: 1861 // SET Set interrupt mask 1862 // NOEFF Writing 0 has no effect 1863 #define GPIO_IMSET_DIO23 0x00800000U 1864 #define GPIO_IMSET_DIO23_M 0x00800000U 1865 #define GPIO_IMSET_DIO23_S 23U 1866 #define GPIO_IMSET_DIO23_SET 0x00800000U 1867 #define GPIO_IMSET_DIO23_NOEFF 0x00000000U 1868 1869 // Field: [22] DIO22 1870 // 1871 // Sets DIO22 in IMASK 1872 // ENUMs: 1873 // SET Set interrupt mask 1874 // NOEFF Writing 0 has no effect 1875 #define GPIO_IMSET_DIO22 0x00400000U 1876 #define GPIO_IMSET_DIO22_M 0x00400000U 1877 #define GPIO_IMSET_DIO22_S 22U 1878 #define GPIO_IMSET_DIO22_SET 0x00400000U 1879 #define GPIO_IMSET_DIO22_NOEFF 0x00000000U 1880 1881 // Field: [21] DIO21 1882 // 1883 // Sets DIO21 in IMASK 1884 // ENUMs: 1885 // SET Set interrupt mask 1886 // NOEFF Writing 0 has no effect 1887 #define GPIO_IMSET_DIO21 0x00200000U 1888 #define GPIO_IMSET_DIO21_M 0x00200000U 1889 #define GPIO_IMSET_DIO21_S 21U 1890 #define GPIO_IMSET_DIO21_SET 0x00200000U 1891 #define GPIO_IMSET_DIO21_NOEFF 0x00000000U 1892 1893 // Field: [20] DIO20 1894 // 1895 // Sets DIO20 in IMASK 1896 // ENUMs: 1897 // SET Set interrupt mask 1898 // NOEFF Writing 0 has no effect 1899 #define GPIO_IMSET_DIO20 0x00100000U 1900 #define GPIO_IMSET_DIO20_M 0x00100000U 1901 #define GPIO_IMSET_DIO20_S 20U 1902 #define GPIO_IMSET_DIO20_SET 0x00100000U 1903 #define GPIO_IMSET_DIO20_NOEFF 0x00000000U 1904 1905 // Field: [19] DIO19 1906 // 1907 // Sets DIO19 in IMASK 1908 // ENUMs: 1909 // SET Set interrupt mask 1910 // NOEFF Writing 0 has no effect 1911 #define GPIO_IMSET_DIO19 0x00080000U 1912 #define GPIO_IMSET_DIO19_M 0x00080000U 1913 #define GPIO_IMSET_DIO19_S 19U 1914 #define GPIO_IMSET_DIO19_SET 0x00080000U 1915 #define GPIO_IMSET_DIO19_NOEFF 0x00000000U 1916 1917 // Field: [18] DIO18 1918 // 1919 // Sets DIO18 in IMASK 1920 // ENUMs: 1921 // SET Set interrupt mask 1922 // NOEFF Writing 0 has no effect 1923 #define GPIO_IMSET_DIO18 0x00040000U 1924 #define GPIO_IMSET_DIO18_M 0x00040000U 1925 #define GPIO_IMSET_DIO18_S 18U 1926 #define GPIO_IMSET_DIO18_SET 0x00040000U 1927 #define GPIO_IMSET_DIO18_NOEFF 0x00000000U 1928 1929 // Field: [17] DIO17 1930 // 1931 // Sets DIO17 in IMASK 1932 // ENUMs: 1933 // SET Set interrupt mask 1934 // NOEFF Writing 0 has no effect 1935 #define GPIO_IMSET_DIO17 0x00020000U 1936 #define GPIO_IMSET_DIO17_M 0x00020000U 1937 #define GPIO_IMSET_DIO17_S 17U 1938 #define GPIO_IMSET_DIO17_SET 0x00020000U 1939 #define GPIO_IMSET_DIO17_NOEFF 0x00000000U 1940 1941 // Field: [16] DIO16 1942 // 1943 // Sets DIO16 in IMASK 1944 // ENUMs: 1945 // SET Set interrupt mask 1946 // NOEFF Writing 0 has no effect 1947 #define GPIO_IMSET_DIO16 0x00010000U 1948 #define GPIO_IMSET_DIO16_M 0x00010000U 1949 #define GPIO_IMSET_DIO16_S 16U 1950 #define GPIO_IMSET_DIO16_SET 0x00010000U 1951 #define GPIO_IMSET_DIO16_NOEFF 0x00000000U 1952 1953 // Field: [15] DIO15 1954 // 1955 // Sets DIO15 in IMASK 1956 // ENUMs: 1957 // SET Set interrupt mask 1958 // NOEFF Writing 0 has no effect 1959 #define GPIO_IMSET_DIO15 0x00008000U 1960 #define GPIO_IMSET_DIO15_M 0x00008000U 1961 #define GPIO_IMSET_DIO15_S 15U 1962 #define GPIO_IMSET_DIO15_SET 0x00008000U 1963 #define GPIO_IMSET_DIO15_NOEFF 0x00000000U 1964 1965 // Field: [14] DIO14 1966 // 1967 // Sets DIO14 in IMASK 1968 // ENUMs: 1969 // SET Set interrupt mask 1970 // NOEFF Writing 0 has no effect 1971 #define GPIO_IMSET_DIO14 0x00004000U 1972 #define GPIO_IMSET_DIO14_M 0x00004000U 1973 #define GPIO_IMSET_DIO14_S 14U 1974 #define GPIO_IMSET_DIO14_SET 0x00004000U 1975 #define GPIO_IMSET_DIO14_NOEFF 0x00000000U 1976 1977 // Field: [13] DIO13 1978 // 1979 // Sets DIO13 in IMASK 1980 // ENUMs: 1981 // SET Set interrupt mask 1982 // NOEFF Writing 0 has no effect 1983 #define GPIO_IMSET_DIO13 0x00002000U 1984 #define GPIO_IMSET_DIO13_M 0x00002000U 1985 #define GPIO_IMSET_DIO13_S 13U 1986 #define GPIO_IMSET_DIO13_SET 0x00002000U 1987 #define GPIO_IMSET_DIO13_NOEFF 0x00000000U 1988 1989 // Field: [12] DIO12 1990 // 1991 // Sets DIO12 in IMASK 1992 // ENUMs: 1993 // SET Set interrupt mask 1994 // NOEFF Writing 0 has no effect 1995 #define GPIO_IMSET_DIO12 0x00001000U 1996 #define GPIO_IMSET_DIO12_M 0x00001000U 1997 #define GPIO_IMSET_DIO12_S 12U 1998 #define GPIO_IMSET_DIO12_SET 0x00001000U 1999 #define GPIO_IMSET_DIO12_NOEFF 0x00000000U 2000 2001 // Field: [11] DIO11 2002 // 2003 // Sets DIO11 in IMASK 2004 // ENUMs: 2005 // SET Set interrupt mask 2006 // NOEFF Writing 0 has no effect 2007 #define GPIO_IMSET_DIO11 0x00000800U 2008 #define GPIO_IMSET_DIO11_M 0x00000800U 2009 #define GPIO_IMSET_DIO11_S 11U 2010 #define GPIO_IMSET_DIO11_SET 0x00000800U 2011 #define GPIO_IMSET_DIO11_NOEFF 0x00000000U 2012 2013 // Field: [10] DIO10 2014 // 2015 // Sets DIO10 in IMASK 2016 // ENUMs: 2017 // SET Set interrupt mask 2018 // NOEFF Writing 0 has no effect 2019 #define GPIO_IMSET_DIO10 0x00000400U 2020 #define GPIO_IMSET_DIO10_M 0x00000400U 2021 #define GPIO_IMSET_DIO10_S 10U 2022 #define GPIO_IMSET_DIO10_SET 0x00000400U 2023 #define GPIO_IMSET_DIO10_NOEFF 0x00000000U 2024 2025 // Field: [9] DIO9 2026 // 2027 // Sets DIO9 in IMASK 2028 // ENUMs: 2029 // SET Set interrupt mask 2030 // NOEFF Writing 0 has no effect 2031 #define GPIO_IMSET_DIO9 0x00000200U 2032 #define GPIO_IMSET_DIO9_M 0x00000200U 2033 #define GPIO_IMSET_DIO9_S 9U 2034 #define GPIO_IMSET_DIO9_SET 0x00000200U 2035 #define GPIO_IMSET_DIO9_NOEFF 0x00000000U 2036 2037 // Field: [8] DIO8 2038 // 2039 // Sets DIO8 in IMASK 2040 // ENUMs: 2041 // SET Set interrupt mask 2042 // NOEFF Writing 0 has no effect 2043 #define GPIO_IMSET_DIO8 0x00000100U 2044 #define GPIO_IMSET_DIO8_M 0x00000100U 2045 #define GPIO_IMSET_DIO8_S 8U 2046 #define GPIO_IMSET_DIO8_SET 0x00000100U 2047 #define GPIO_IMSET_DIO8_NOEFF 0x00000000U 2048 2049 // Field: [7] DIO7 2050 // 2051 // Sets DIO7 in IMASK 2052 // ENUMs: 2053 // SET Set interrupt mask 2054 // NOEFF Writing 0 has no effect 2055 #define GPIO_IMSET_DIO7 0x00000080U 2056 #define GPIO_IMSET_DIO7_M 0x00000080U 2057 #define GPIO_IMSET_DIO7_S 7U 2058 #define GPIO_IMSET_DIO7_SET 0x00000080U 2059 #define GPIO_IMSET_DIO7_NOEFF 0x00000000U 2060 2061 // Field: [6] DIO6 2062 // 2063 // Sets DIO6 in IMASK 2064 // ENUMs: 2065 // SET Set interrupt mask 2066 // NOEFF Writing 0 has no effect 2067 #define GPIO_IMSET_DIO6 0x00000040U 2068 #define GPIO_IMSET_DIO6_M 0x00000040U 2069 #define GPIO_IMSET_DIO6_S 6U 2070 #define GPIO_IMSET_DIO6_SET 0x00000040U 2071 #define GPIO_IMSET_DIO6_NOEFF 0x00000000U 2072 2073 // Field: [5] DIO5 2074 // 2075 // Sets DIO5 in IMASK 2076 // ENUMs: 2077 // SET Set interrupt mask 2078 // NOEFF Writing 0 has no effect 2079 #define GPIO_IMSET_DIO5 0x00000020U 2080 #define GPIO_IMSET_DIO5_M 0x00000020U 2081 #define GPIO_IMSET_DIO5_S 5U 2082 #define GPIO_IMSET_DIO5_SET 0x00000020U 2083 #define GPIO_IMSET_DIO5_NOEFF 0x00000000U 2084 2085 // Field: [4] DIO4 2086 // 2087 // Sets DIO4 in IMASK 2088 // ENUMs: 2089 // SET Set interrupt mask 2090 // NOEFF Writing 0 has no effect 2091 #define GPIO_IMSET_DIO4 0x00000010U 2092 #define GPIO_IMSET_DIO4_M 0x00000010U 2093 #define GPIO_IMSET_DIO4_S 4U 2094 #define GPIO_IMSET_DIO4_SET 0x00000010U 2095 #define GPIO_IMSET_DIO4_NOEFF 0x00000000U 2096 2097 // Field: [3] DIO3 2098 // 2099 // Sets DIO3 in IMASK 2100 // ENUMs: 2101 // SET Set interrupt mask 2102 // NOEFF Writing 0 has no effect 2103 #define GPIO_IMSET_DIO3 0x00000008U 2104 #define GPIO_IMSET_DIO3_M 0x00000008U 2105 #define GPIO_IMSET_DIO3_S 3U 2106 #define GPIO_IMSET_DIO3_SET 0x00000008U 2107 #define GPIO_IMSET_DIO3_NOEFF 0x00000000U 2108 2109 // Field: [2] DIO2 2110 // 2111 // Sets DIO2 in IMASK 2112 // ENUMs: 2113 // SET Set interrupt mask 2114 // NOEFF Writing 0 has no effect 2115 #define GPIO_IMSET_DIO2 0x00000004U 2116 #define GPIO_IMSET_DIO2_M 0x00000004U 2117 #define GPIO_IMSET_DIO2_S 2U 2118 #define GPIO_IMSET_DIO2_SET 0x00000004U 2119 #define GPIO_IMSET_DIO2_NOEFF 0x00000000U 2120 2121 // Field: [1] DIO1 2122 // 2123 // Sets DIO1 in IMASK 2124 // ENUMs: 2125 // SET Set interrupt mask 2126 // NOEFF Writing 0 has no effect 2127 #define GPIO_IMSET_DIO1 0x00000002U 2128 #define GPIO_IMSET_DIO1_M 0x00000002U 2129 #define GPIO_IMSET_DIO1_S 1U 2130 #define GPIO_IMSET_DIO1_SET 0x00000002U 2131 #define GPIO_IMSET_DIO1_NOEFF 0x00000000U 2132 2133 // Field: [0] DIO0 2134 // 2135 // Sets DIO0 in IMASK 2136 // ENUMs: 2137 // SET Set interrupt mask 2138 // NOEFF Writing 0 has no effect 2139 #define GPIO_IMSET_DIO0 0x00000001U 2140 #define GPIO_IMSET_DIO0_M 0x00000001U 2141 #define GPIO_IMSET_DIO0_S 0U 2142 #define GPIO_IMSET_DIO0_SET 0x00000001U 2143 #define GPIO_IMSET_DIO0_NOEFF 0x00000000U 2144 2145 //***************************************************************************** 2146 // 2147 // Register: GPIO_O_IMCLR 2148 // 2149 //***************************************************************************** 2150 // Field: [25] DIO25 2151 // 2152 // Clears DIO25 in IMASK 2153 // ENUMs: 2154 // CLR Clear interrupt mask 2155 // NOEFF Writing 0 has no effect 2156 #define GPIO_IMCLR_DIO25 0x02000000U 2157 #define GPIO_IMCLR_DIO25_M 0x02000000U 2158 #define GPIO_IMCLR_DIO25_S 25U 2159 #define GPIO_IMCLR_DIO25_CLR 0x02000000U 2160 #define GPIO_IMCLR_DIO25_NOEFF 0x00000000U 2161 2162 // Field: [24] DIO24 2163 // 2164 // Clears DIO24 in IMASK 2165 // ENUMs: 2166 // CLR Clear interrupt mask 2167 // NOEFF Writing 0 has no effect 2168 #define GPIO_IMCLR_DIO24 0x01000000U 2169 #define GPIO_IMCLR_DIO24_M 0x01000000U 2170 #define GPIO_IMCLR_DIO24_S 24U 2171 #define GPIO_IMCLR_DIO24_CLR 0x01000000U 2172 #define GPIO_IMCLR_DIO24_NOEFF 0x00000000U 2173 2174 // Field: [23] DIO23 2175 // 2176 // Clears DIO23 in IMASK 2177 // ENUMs: 2178 // CLR Clear interrupt mask 2179 // NOEFF Writing 0 has no effect 2180 #define GPIO_IMCLR_DIO23 0x00800000U 2181 #define GPIO_IMCLR_DIO23_M 0x00800000U 2182 #define GPIO_IMCLR_DIO23_S 23U 2183 #define GPIO_IMCLR_DIO23_CLR 0x00800000U 2184 #define GPIO_IMCLR_DIO23_NOEFF 0x00000000U 2185 2186 // Field: [22] DIO22 2187 // 2188 // Clears DIO22 in IMASK 2189 // ENUMs: 2190 // CLR Clear interrupt mask 2191 // NOEFF Writing 0 has no effect 2192 #define GPIO_IMCLR_DIO22 0x00400000U 2193 #define GPIO_IMCLR_DIO22_M 0x00400000U 2194 #define GPIO_IMCLR_DIO22_S 22U 2195 #define GPIO_IMCLR_DIO22_CLR 0x00400000U 2196 #define GPIO_IMCLR_DIO22_NOEFF 0x00000000U 2197 2198 // Field: [21] DIO21 2199 // 2200 // Clears DIO21 in IMASK 2201 // ENUMs: 2202 // CLR Clear interrupt mask 2203 // NOEFF Writing 0 has no effect 2204 #define GPIO_IMCLR_DIO21 0x00200000U 2205 #define GPIO_IMCLR_DIO21_M 0x00200000U 2206 #define GPIO_IMCLR_DIO21_S 21U 2207 #define GPIO_IMCLR_DIO21_CLR 0x00200000U 2208 #define GPIO_IMCLR_DIO21_NOEFF 0x00000000U 2209 2210 // Field: [20] DIO20 2211 // 2212 // Clears DIO20 in IMASK 2213 // ENUMs: 2214 // CLR Clear interrupt mask 2215 // NOEFF Writing 0 has no effect 2216 #define GPIO_IMCLR_DIO20 0x00100000U 2217 #define GPIO_IMCLR_DIO20_M 0x00100000U 2218 #define GPIO_IMCLR_DIO20_S 20U 2219 #define GPIO_IMCLR_DIO20_CLR 0x00100000U 2220 #define GPIO_IMCLR_DIO20_NOEFF 0x00000000U 2221 2222 // Field: [19] DIO19 2223 // 2224 // Clears DIO19 in IMASK 2225 // ENUMs: 2226 // CLR Clear interrupt mask 2227 // NOEFF Writing 0 has no effect 2228 #define GPIO_IMCLR_DIO19 0x00080000U 2229 #define GPIO_IMCLR_DIO19_M 0x00080000U 2230 #define GPIO_IMCLR_DIO19_S 19U 2231 #define GPIO_IMCLR_DIO19_CLR 0x00080000U 2232 #define GPIO_IMCLR_DIO19_NOEFF 0x00000000U 2233 2234 // Field: [18] DIO18 2235 // 2236 // Clears DIO18 in IMASK 2237 // ENUMs: 2238 // CLR Clear interrupt mask 2239 // NOEFF Writing 0 has no effect 2240 #define GPIO_IMCLR_DIO18 0x00040000U 2241 #define GPIO_IMCLR_DIO18_M 0x00040000U 2242 #define GPIO_IMCLR_DIO18_S 18U 2243 #define GPIO_IMCLR_DIO18_CLR 0x00040000U 2244 #define GPIO_IMCLR_DIO18_NOEFF 0x00000000U 2245 2246 // Field: [17] DIO17 2247 // 2248 // Clears DIO17 in IMASK 2249 // ENUMs: 2250 // CLR Clear interrupt mask 2251 // NOEFF Writing 0 has no effect 2252 #define GPIO_IMCLR_DIO17 0x00020000U 2253 #define GPIO_IMCLR_DIO17_M 0x00020000U 2254 #define GPIO_IMCLR_DIO17_S 17U 2255 #define GPIO_IMCLR_DIO17_CLR 0x00020000U 2256 #define GPIO_IMCLR_DIO17_NOEFF 0x00000000U 2257 2258 // Field: [16] DIO16 2259 // 2260 // Clears DIO16 in IMASK 2261 // ENUMs: 2262 // CLR Clear interrupt mask 2263 // NOEFF Writing 0 has no effect 2264 #define GPIO_IMCLR_DIO16 0x00010000U 2265 #define GPIO_IMCLR_DIO16_M 0x00010000U 2266 #define GPIO_IMCLR_DIO16_S 16U 2267 #define GPIO_IMCLR_DIO16_CLR 0x00010000U 2268 #define GPIO_IMCLR_DIO16_NOEFF 0x00000000U 2269 2270 // Field: [15] DIO15 2271 // 2272 // Clears DIO15 in IMASK 2273 // ENUMs: 2274 // CLR Clear interrupt mask 2275 // NOEFF Writing 0 has no effect 2276 #define GPIO_IMCLR_DIO15 0x00008000U 2277 #define GPIO_IMCLR_DIO15_M 0x00008000U 2278 #define GPIO_IMCLR_DIO15_S 15U 2279 #define GPIO_IMCLR_DIO15_CLR 0x00008000U 2280 #define GPIO_IMCLR_DIO15_NOEFF 0x00000000U 2281 2282 // Field: [14] DIO14 2283 // 2284 // Clears DIO14 in IMASK 2285 // ENUMs: 2286 // CLR Clear interrupt mask 2287 // NOEFF Writing 0 has no effect 2288 #define GPIO_IMCLR_DIO14 0x00004000U 2289 #define GPIO_IMCLR_DIO14_M 0x00004000U 2290 #define GPIO_IMCLR_DIO14_S 14U 2291 #define GPIO_IMCLR_DIO14_CLR 0x00004000U 2292 #define GPIO_IMCLR_DIO14_NOEFF 0x00000000U 2293 2294 // Field: [13] DIO13 2295 // 2296 // Clears DIO13 in IMASK 2297 // ENUMs: 2298 // CLR Clear interrupt mask 2299 // NOEFF Writing 0 has no effect 2300 #define GPIO_IMCLR_DIO13 0x00002000U 2301 #define GPIO_IMCLR_DIO13_M 0x00002000U 2302 #define GPIO_IMCLR_DIO13_S 13U 2303 #define GPIO_IMCLR_DIO13_CLR 0x00002000U 2304 #define GPIO_IMCLR_DIO13_NOEFF 0x00000000U 2305 2306 // Field: [12] DIO12 2307 // 2308 // Clears DIO12 in IMASK 2309 // ENUMs: 2310 // CLR Clear interrupt mask 2311 // NOEFF Writing 0 has no effect 2312 #define GPIO_IMCLR_DIO12 0x00001000U 2313 #define GPIO_IMCLR_DIO12_M 0x00001000U 2314 #define GPIO_IMCLR_DIO12_S 12U 2315 #define GPIO_IMCLR_DIO12_CLR 0x00001000U 2316 #define GPIO_IMCLR_DIO12_NOEFF 0x00000000U 2317 2318 // Field: [11] DIO11 2319 // 2320 // Clears DIO11 in IMASK 2321 // ENUMs: 2322 // CLR Clear interrupt mask 2323 // NOEFF Writing 0 has no effect 2324 #define GPIO_IMCLR_DIO11 0x00000800U 2325 #define GPIO_IMCLR_DIO11_M 0x00000800U 2326 #define GPIO_IMCLR_DIO11_S 11U 2327 #define GPIO_IMCLR_DIO11_CLR 0x00000800U 2328 #define GPIO_IMCLR_DIO11_NOEFF 0x00000000U 2329 2330 // Field: [10] DIO10 2331 // 2332 // Clears DIO10 in IMASK 2333 // ENUMs: 2334 // CLR Clear interrupt mask 2335 // NOEFF Writing 0 has no effect 2336 #define GPIO_IMCLR_DIO10 0x00000400U 2337 #define GPIO_IMCLR_DIO10_M 0x00000400U 2338 #define GPIO_IMCLR_DIO10_S 10U 2339 #define GPIO_IMCLR_DIO10_CLR 0x00000400U 2340 #define GPIO_IMCLR_DIO10_NOEFF 0x00000000U 2341 2342 // Field: [9] DIO9 2343 // 2344 // Clears DIO9 in IMASK 2345 // ENUMs: 2346 // CLR Clear interrupt mask 2347 // NOEFF Writing 0 has no effect 2348 #define GPIO_IMCLR_DIO9 0x00000200U 2349 #define GPIO_IMCLR_DIO9_M 0x00000200U 2350 #define GPIO_IMCLR_DIO9_S 9U 2351 #define GPIO_IMCLR_DIO9_CLR 0x00000200U 2352 #define GPIO_IMCLR_DIO9_NOEFF 0x00000000U 2353 2354 // Field: [8] DIO8 2355 // 2356 // Clears DIO8 in IMASK 2357 // ENUMs: 2358 // CLR Clear interrupt mask 2359 // NOEFF Writing 0 has no effect 2360 #define GPIO_IMCLR_DIO8 0x00000100U 2361 #define GPIO_IMCLR_DIO8_M 0x00000100U 2362 #define GPIO_IMCLR_DIO8_S 8U 2363 #define GPIO_IMCLR_DIO8_CLR 0x00000100U 2364 #define GPIO_IMCLR_DIO8_NOEFF 0x00000000U 2365 2366 // Field: [7] DIO7 2367 // 2368 // Clears DIO7 in IMASK 2369 // ENUMs: 2370 // CLR Clear interrupt mask 2371 // NOEFF Writing 0 has no effect 2372 #define GPIO_IMCLR_DIO7 0x00000080U 2373 #define GPIO_IMCLR_DIO7_M 0x00000080U 2374 #define GPIO_IMCLR_DIO7_S 7U 2375 #define GPIO_IMCLR_DIO7_CLR 0x00000080U 2376 #define GPIO_IMCLR_DIO7_NOEFF 0x00000000U 2377 2378 // Field: [6] DIO6 2379 // 2380 // Clears DIO6 in IMASK 2381 // ENUMs: 2382 // CLR Clear interrupt mask 2383 // NOEFF Writing 0 has no effect 2384 #define GPIO_IMCLR_DIO6 0x00000040U 2385 #define GPIO_IMCLR_DIO6_M 0x00000040U 2386 #define GPIO_IMCLR_DIO6_S 6U 2387 #define GPIO_IMCLR_DIO6_CLR 0x00000040U 2388 #define GPIO_IMCLR_DIO6_NOEFF 0x00000000U 2389 2390 // Field: [5] DIO5 2391 // 2392 // Clears DIO5 in IMASK 2393 // ENUMs: 2394 // CLR Clear interrupt mask 2395 // NOEFF Writing 0 has no effect 2396 #define GPIO_IMCLR_DIO5 0x00000020U 2397 #define GPIO_IMCLR_DIO5_M 0x00000020U 2398 #define GPIO_IMCLR_DIO5_S 5U 2399 #define GPIO_IMCLR_DIO5_CLR 0x00000020U 2400 #define GPIO_IMCLR_DIO5_NOEFF 0x00000000U 2401 2402 // Field: [4] DIO4 2403 // 2404 // Clears DIO4 in IMASK 2405 // ENUMs: 2406 // CLR Clear interrupt mask 2407 // NOEFF Writing 0 has no effect 2408 #define GPIO_IMCLR_DIO4 0x00000010U 2409 #define GPIO_IMCLR_DIO4_M 0x00000010U 2410 #define GPIO_IMCLR_DIO4_S 4U 2411 #define GPIO_IMCLR_DIO4_CLR 0x00000010U 2412 #define GPIO_IMCLR_DIO4_NOEFF 0x00000000U 2413 2414 // Field: [3] DIO3 2415 // 2416 // Clears DIO3 in IMASK 2417 // ENUMs: 2418 // CLR Clear interrupt mask 2419 // NOEFF Writing 0 has no effect 2420 #define GPIO_IMCLR_DIO3 0x00000008U 2421 #define GPIO_IMCLR_DIO3_M 0x00000008U 2422 #define GPIO_IMCLR_DIO3_S 3U 2423 #define GPIO_IMCLR_DIO3_CLR 0x00000008U 2424 #define GPIO_IMCLR_DIO3_NOEFF 0x00000000U 2425 2426 // Field: [2] DIO2 2427 // 2428 // Clears DIO2 in IMASK 2429 // ENUMs: 2430 // CLR Clear interrupt mask 2431 // NOEFF Writing 0 has no effect 2432 #define GPIO_IMCLR_DIO2 0x00000004U 2433 #define GPIO_IMCLR_DIO2_M 0x00000004U 2434 #define GPIO_IMCLR_DIO2_S 2U 2435 #define GPIO_IMCLR_DIO2_CLR 0x00000004U 2436 #define GPIO_IMCLR_DIO2_NOEFF 0x00000000U 2437 2438 // Field: [1] DIO1 2439 // 2440 // Clears DIO1 in IMASK 2441 // ENUMs: 2442 // CLR Clear interrupt mask 2443 // NOEFF Writing 0 has no effect 2444 #define GPIO_IMCLR_DIO1 0x00000002U 2445 #define GPIO_IMCLR_DIO1_M 0x00000002U 2446 #define GPIO_IMCLR_DIO1_S 1U 2447 #define GPIO_IMCLR_DIO1_CLR 0x00000002U 2448 #define GPIO_IMCLR_DIO1_NOEFF 0x00000000U 2449 2450 // Field: [0] DIO0 2451 // 2452 // Clears DIO0 in IMASK 2453 // ENUMs: 2454 // CLR Clear interrupt mask 2455 // NOEFF Writing 0 has no effect 2456 #define GPIO_IMCLR_DIO0 0x00000001U 2457 #define GPIO_IMCLR_DIO0_M 0x00000001U 2458 #define GPIO_IMCLR_DIO0_S 0U 2459 #define GPIO_IMCLR_DIO0_CLR 0x00000001U 2460 #define GPIO_IMCLR_DIO0_NOEFF 0x00000000U 2461 2462 //***************************************************************************** 2463 // 2464 // Register: GPIO_O_DOUT3_0 2465 // 2466 //***************************************************************************** 2467 // Field: [24] DIO3 2468 // 2469 // Data output for DIO3 2470 // ENUMs: 2471 // ONE Output is set to 1 2472 // ZERO Output is set to 0 2473 #define GPIO_DOUT3_0_DIO3 0x01000000U 2474 #define GPIO_DOUT3_0_DIO3_M 0x01000000U 2475 #define GPIO_DOUT3_0_DIO3_S 24U 2476 #define GPIO_DOUT3_0_DIO3_ONE 0x01000000U 2477 #define GPIO_DOUT3_0_DIO3_ZERO 0x00000000U 2478 2479 // Field: [16] DIO2 2480 // 2481 // Data output for DIO2 2482 // ENUMs: 2483 // ONE Output is set to 1 2484 // ZERO Output is set to 0 2485 #define GPIO_DOUT3_0_DIO2 0x00010000U 2486 #define GPIO_DOUT3_0_DIO2_M 0x00010000U 2487 #define GPIO_DOUT3_0_DIO2_S 16U 2488 #define GPIO_DOUT3_0_DIO2_ONE 0x00010000U 2489 #define GPIO_DOUT3_0_DIO2_ZERO 0x00000000U 2490 2491 // Field: [8] DIO1 2492 // 2493 // Data output for DIO1 2494 // ENUMs: 2495 // ONE Output is set to 1 2496 // ZERO Output is set to 0 2497 #define GPIO_DOUT3_0_DIO1 0x00000100U 2498 #define GPIO_DOUT3_0_DIO1_M 0x00000100U 2499 #define GPIO_DOUT3_0_DIO1_S 8U 2500 #define GPIO_DOUT3_0_DIO1_ONE 0x00000100U 2501 #define GPIO_DOUT3_0_DIO1_ZERO 0x00000000U 2502 2503 // Field: [0] DIO0 2504 // 2505 // Data output for DIO0 2506 // ENUMs: 2507 // ONE Output is set to 1 2508 // ZERO Output is set to 0 2509 #define GPIO_DOUT3_0_DIO0 0x00000001U 2510 #define GPIO_DOUT3_0_DIO0_M 0x00000001U 2511 #define GPIO_DOUT3_0_DIO0_S 0U 2512 #define GPIO_DOUT3_0_DIO0_ONE 0x00000001U 2513 #define GPIO_DOUT3_0_DIO0_ZERO 0x00000000U 2514 2515 //***************************************************************************** 2516 // 2517 // Register: GPIO_O_DOUT7_4 2518 // 2519 //***************************************************************************** 2520 // Field: [24] DIO7 2521 // 2522 // Data output for DIO7 2523 // ENUMs: 2524 // ONE Output is set to 1 2525 // ZERO Output is set to 0 2526 #define GPIO_DOUT7_4_DIO7 0x01000000U 2527 #define GPIO_DOUT7_4_DIO7_M 0x01000000U 2528 #define GPIO_DOUT7_4_DIO7_S 24U 2529 #define GPIO_DOUT7_4_DIO7_ONE 0x01000000U 2530 #define GPIO_DOUT7_4_DIO7_ZERO 0x00000000U 2531 2532 // Field: [16] DIO6 2533 // 2534 // Data output for DIO6 2535 // ENUMs: 2536 // ONE Output is set to 1 2537 // ZERO Output is set to 0 2538 #define GPIO_DOUT7_4_DIO6 0x00010000U 2539 #define GPIO_DOUT7_4_DIO6_M 0x00010000U 2540 #define GPIO_DOUT7_4_DIO6_S 16U 2541 #define GPIO_DOUT7_4_DIO6_ONE 0x00010000U 2542 #define GPIO_DOUT7_4_DIO6_ZERO 0x00000000U 2543 2544 // Field: [8] DIO5 2545 // 2546 // Data output for DIO5 2547 // ENUMs: 2548 // ONE Output is set to 1 2549 // ZERO Output is set to 0 2550 #define GPIO_DOUT7_4_DIO5 0x00000100U 2551 #define GPIO_DOUT7_4_DIO5_M 0x00000100U 2552 #define GPIO_DOUT7_4_DIO5_S 8U 2553 #define GPIO_DOUT7_4_DIO5_ONE 0x00000100U 2554 #define GPIO_DOUT7_4_DIO5_ZERO 0x00000000U 2555 2556 // Field: [0] DIO4 2557 // 2558 // Data output for DIO4 2559 // ENUMs: 2560 // ONE Output is set to 1 2561 // ZERO Output is set to 0 2562 #define GPIO_DOUT7_4_DIO4 0x00000001U 2563 #define GPIO_DOUT7_4_DIO4_M 0x00000001U 2564 #define GPIO_DOUT7_4_DIO4_S 0U 2565 #define GPIO_DOUT7_4_DIO4_ONE 0x00000001U 2566 #define GPIO_DOUT7_4_DIO4_ZERO 0x00000000U 2567 2568 //***************************************************************************** 2569 // 2570 // Register: GPIO_O_DOUT11_8 2571 // 2572 //***************************************************************************** 2573 // Field: [24] DIO11 2574 // 2575 // Data output for DIO11 2576 // ENUMs: 2577 // ONE Output is set to 1 2578 // ZERO Output is set to 0 2579 #define GPIO_DOUT11_8_DIO11 0x01000000U 2580 #define GPIO_DOUT11_8_DIO11_M 0x01000000U 2581 #define GPIO_DOUT11_8_DIO11_S 24U 2582 #define GPIO_DOUT11_8_DIO11_ONE 0x01000000U 2583 #define GPIO_DOUT11_8_DIO11_ZERO 0x00000000U 2584 2585 // Field: [16] DIO10 2586 // 2587 // Data output for DIO10 2588 // ENUMs: 2589 // ONE Output is set to 1 2590 // ZERO Output is set to 0 2591 #define GPIO_DOUT11_8_DIO10 0x00010000U 2592 #define GPIO_DOUT11_8_DIO10_M 0x00010000U 2593 #define GPIO_DOUT11_8_DIO10_S 16U 2594 #define GPIO_DOUT11_8_DIO10_ONE 0x00010000U 2595 #define GPIO_DOUT11_8_DIO10_ZERO 0x00000000U 2596 2597 // Field: [8] DIO9 2598 // 2599 // Data output for DIO9 2600 // ENUMs: 2601 // ONE Output is set to 1 2602 // ZERO Output is set to 0 2603 #define GPIO_DOUT11_8_DIO9 0x00000100U 2604 #define GPIO_DOUT11_8_DIO9_M 0x00000100U 2605 #define GPIO_DOUT11_8_DIO9_S 8U 2606 #define GPIO_DOUT11_8_DIO9_ONE 0x00000100U 2607 #define GPIO_DOUT11_8_DIO9_ZERO 0x00000000U 2608 2609 // Field: [0] DIO8 2610 // 2611 // Data output for DIO8 2612 // ENUMs: 2613 // ONE Output is set to 1 2614 // ZERO Output is set to 0 2615 #define GPIO_DOUT11_8_DIO8 0x00000001U 2616 #define GPIO_DOUT11_8_DIO8_M 0x00000001U 2617 #define GPIO_DOUT11_8_DIO8_S 0U 2618 #define GPIO_DOUT11_8_DIO8_ONE 0x00000001U 2619 #define GPIO_DOUT11_8_DIO8_ZERO 0x00000000U 2620 2621 //***************************************************************************** 2622 // 2623 // Register: GPIO_O_DOUT15_12 2624 // 2625 //***************************************************************************** 2626 // Field: [24] DIO15 2627 // 2628 // Data output for DIO15 2629 // ENUMs: 2630 // ONE Output is set to 1 2631 // ZERO Output is set to 0 2632 #define GPIO_DOUT15_12_DIO15 0x01000000U 2633 #define GPIO_DOUT15_12_DIO15_M 0x01000000U 2634 #define GPIO_DOUT15_12_DIO15_S 24U 2635 #define GPIO_DOUT15_12_DIO15_ONE 0x01000000U 2636 #define GPIO_DOUT15_12_DIO15_ZERO 0x00000000U 2637 2638 // Field: [16] DIO14 2639 // 2640 // Data output for DIO14 2641 // ENUMs: 2642 // ONE Output is set to 1 2643 // ZERO Output is set to 0 2644 #define GPIO_DOUT15_12_DIO14 0x00010000U 2645 #define GPIO_DOUT15_12_DIO14_M 0x00010000U 2646 #define GPIO_DOUT15_12_DIO14_S 16U 2647 #define GPIO_DOUT15_12_DIO14_ONE 0x00010000U 2648 #define GPIO_DOUT15_12_DIO14_ZERO 0x00000000U 2649 2650 // Field: [8] DIO13 2651 // 2652 // Data output for DIO13 2653 // ENUMs: 2654 // ONE Output is set to 1 2655 // ZERO Output is set to 0 2656 #define GPIO_DOUT15_12_DIO13 0x00000100U 2657 #define GPIO_DOUT15_12_DIO13_M 0x00000100U 2658 #define GPIO_DOUT15_12_DIO13_S 8U 2659 #define GPIO_DOUT15_12_DIO13_ONE 0x00000100U 2660 #define GPIO_DOUT15_12_DIO13_ZERO 0x00000000U 2661 2662 // Field: [0] DIO12 2663 // 2664 // Data output for DIO12 2665 // ENUMs: 2666 // ONE Output is set to 1 2667 // ZERO Output is set to 0 2668 #define GPIO_DOUT15_12_DIO12 0x00000001U 2669 #define GPIO_DOUT15_12_DIO12_M 0x00000001U 2670 #define GPIO_DOUT15_12_DIO12_S 0U 2671 #define GPIO_DOUT15_12_DIO12_ONE 0x00000001U 2672 #define GPIO_DOUT15_12_DIO12_ZERO 0x00000000U 2673 2674 //***************************************************************************** 2675 // 2676 // Register: GPIO_O_DOUT19_16 2677 // 2678 //***************************************************************************** 2679 // Field: [24] DIO19 2680 // 2681 // Data output for DIO19 2682 // ENUMs: 2683 // ONE Output is set to 1 2684 // ZERO Output is set to 0 2685 #define GPIO_DOUT19_16_DIO19 0x01000000U 2686 #define GPIO_DOUT19_16_DIO19_M 0x01000000U 2687 #define GPIO_DOUT19_16_DIO19_S 24U 2688 #define GPIO_DOUT19_16_DIO19_ONE 0x01000000U 2689 #define GPIO_DOUT19_16_DIO19_ZERO 0x00000000U 2690 2691 // Field: [16] DIO18 2692 // 2693 // Data output for DIO18 2694 // ENUMs: 2695 // ONE Output is set to 1 2696 // ZERO Output is set to 0 2697 #define GPIO_DOUT19_16_DIO18 0x00010000U 2698 #define GPIO_DOUT19_16_DIO18_M 0x00010000U 2699 #define GPIO_DOUT19_16_DIO18_S 16U 2700 #define GPIO_DOUT19_16_DIO18_ONE 0x00010000U 2701 #define GPIO_DOUT19_16_DIO18_ZERO 0x00000000U 2702 2703 // Field: [8] DIO17 2704 // 2705 // Data output for DIO17 2706 // ENUMs: 2707 // ONE Output is set to 1 2708 // ZERO Output is set to 0 2709 #define GPIO_DOUT19_16_DIO17 0x00000100U 2710 #define GPIO_DOUT19_16_DIO17_M 0x00000100U 2711 #define GPIO_DOUT19_16_DIO17_S 8U 2712 #define GPIO_DOUT19_16_DIO17_ONE 0x00000100U 2713 #define GPIO_DOUT19_16_DIO17_ZERO 0x00000000U 2714 2715 // Field: [0] DIO16 2716 // 2717 // Data output for DIO16 2718 // ENUMs: 2719 // ONE Output is set to 1 2720 // ZERO Output is set to 0 2721 #define GPIO_DOUT19_16_DIO16 0x00000001U 2722 #define GPIO_DOUT19_16_DIO16_M 0x00000001U 2723 #define GPIO_DOUT19_16_DIO16_S 0U 2724 #define GPIO_DOUT19_16_DIO16_ONE 0x00000001U 2725 #define GPIO_DOUT19_16_DIO16_ZERO 0x00000000U 2726 2727 //***************************************************************************** 2728 // 2729 // Register: GPIO_O_DOUT23_20 2730 // 2731 //***************************************************************************** 2732 // Field: [24] DIO23 2733 // 2734 // Data output for DIO23 2735 // ENUMs: 2736 // ONE Output is set to 1 2737 // ZERO Output is set to 0 2738 #define GPIO_DOUT23_20_DIO23 0x01000000U 2739 #define GPIO_DOUT23_20_DIO23_M 0x01000000U 2740 #define GPIO_DOUT23_20_DIO23_S 24U 2741 #define GPIO_DOUT23_20_DIO23_ONE 0x01000000U 2742 #define GPIO_DOUT23_20_DIO23_ZERO 0x00000000U 2743 2744 // Field: [16] DIO22 2745 // 2746 // Data output for DIO22 2747 // ENUMs: 2748 // ONE Output is set to 1 2749 // ZERO Output is set to 0 2750 #define GPIO_DOUT23_20_DIO22 0x00010000U 2751 #define GPIO_DOUT23_20_DIO22_M 0x00010000U 2752 #define GPIO_DOUT23_20_DIO22_S 16U 2753 #define GPIO_DOUT23_20_DIO22_ONE 0x00010000U 2754 #define GPIO_DOUT23_20_DIO22_ZERO 0x00000000U 2755 2756 // Field: [8] DIO21 2757 // 2758 // Data output for DIO21 2759 // ENUMs: 2760 // ONE Output is set to 1 2761 // ZERO Output is set to 0 2762 #define GPIO_DOUT23_20_DIO21 0x00000100U 2763 #define GPIO_DOUT23_20_DIO21_M 0x00000100U 2764 #define GPIO_DOUT23_20_DIO21_S 8U 2765 #define GPIO_DOUT23_20_DIO21_ONE 0x00000100U 2766 #define GPIO_DOUT23_20_DIO21_ZERO 0x00000000U 2767 2768 // Field: [0] DIO20 2769 // 2770 // Data output for DIO20 2771 // ENUMs: 2772 // ONE Output is set to 1 2773 // ZERO Output is set to 0 2774 #define GPIO_DOUT23_20_DIO20 0x00000001U 2775 #define GPIO_DOUT23_20_DIO20_M 0x00000001U 2776 #define GPIO_DOUT23_20_DIO20_S 0U 2777 #define GPIO_DOUT23_20_DIO20_ONE 0x00000001U 2778 #define GPIO_DOUT23_20_DIO20_ZERO 0x00000000U 2779 2780 //***************************************************************************** 2781 // 2782 // Register: GPIO_O_DOUT27_24 2783 // 2784 //***************************************************************************** 2785 // Field: [8] DIO25 2786 // 2787 // Data output for DIO25 2788 // ENUMs: 2789 // ONE Output is set to 1 2790 // ZERO Output is set to 0 2791 #define GPIO_DOUT27_24_DIO25 0x00000100U 2792 #define GPIO_DOUT27_24_DIO25_M 0x00000100U 2793 #define GPIO_DOUT27_24_DIO25_S 8U 2794 #define GPIO_DOUT27_24_DIO25_ONE 0x00000100U 2795 #define GPIO_DOUT27_24_DIO25_ZERO 0x00000000U 2796 2797 // Field: [0] DIO24 2798 // 2799 // Data output for DIO24 2800 // ENUMs: 2801 // ONE Output is set to 1 2802 // ZERO Output is set to 0 2803 #define GPIO_DOUT27_24_DIO24 0x00000001U 2804 #define GPIO_DOUT27_24_DIO24_M 0x00000001U 2805 #define GPIO_DOUT27_24_DIO24_S 0U 2806 #define GPIO_DOUT27_24_DIO24_ONE 0x00000001U 2807 #define GPIO_DOUT27_24_DIO24_ZERO 0x00000000U 2808 2809 //***************************************************************************** 2810 // 2811 // Register: GPIO_O_DOUT31_0 2812 // 2813 //***************************************************************************** 2814 // Field: [25] DIO25 2815 // 2816 // Data output for DIO25 2817 // ENUMs: 2818 // ONE Output is set to 1 2819 // ZERO Output is set to 0 2820 #define GPIO_DOUT31_0_DIO25 0x02000000U 2821 #define GPIO_DOUT31_0_DIO25_M 0x02000000U 2822 #define GPIO_DOUT31_0_DIO25_S 25U 2823 #define GPIO_DOUT31_0_DIO25_ONE 0x02000000U 2824 #define GPIO_DOUT31_0_DIO25_ZERO 0x00000000U 2825 2826 // Field: [24] DIO24 2827 // 2828 // Data output for DIO24 2829 // ENUMs: 2830 // ONE Output is set to 1 2831 // ZERO Output is set to 0 2832 #define GPIO_DOUT31_0_DIO24 0x01000000U 2833 #define GPIO_DOUT31_0_DIO24_M 0x01000000U 2834 #define GPIO_DOUT31_0_DIO24_S 24U 2835 #define GPIO_DOUT31_0_DIO24_ONE 0x01000000U 2836 #define GPIO_DOUT31_0_DIO24_ZERO 0x00000000U 2837 2838 // Field: [23] DIO23 2839 // 2840 // Data output for DIO23 2841 // ENUMs: 2842 // ONE Output is set to 1 2843 // ZERO Output is set to 0 2844 #define GPIO_DOUT31_0_DIO23 0x00800000U 2845 #define GPIO_DOUT31_0_DIO23_M 0x00800000U 2846 #define GPIO_DOUT31_0_DIO23_S 23U 2847 #define GPIO_DOUT31_0_DIO23_ONE 0x00800000U 2848 #define GPIO_DOUT31_0_DIO23_ZERO 0x00000000U 2849 2850 // Field: [22] DIO22 2851 // 2852 // Data output for DIO22 2853 // ENUMs: 2854 // ONE Output is set to 1 2855 // ZERO Output is set to 0 2856 #define GPIO_DOUT31_0_DIO22 0x00400000U 2857 #define GPIO_DOUT31_0_DIO22_M 0x00400000U 2858 #define GPIO_DOUT31_0_DIO22_S 22U 2859 #define GPIO_DOUT31_0_DIO22_ONE 0x00400000U 2860 #define GPIO_DOUT31_0_DIO22_ZERO 0x00000000U 2861 2862 // Field: [21] DIO21 2863 // 2864 // Data output for DIO21 2865 // ENUMs: 2866 // ONE Output is set to 1 2867 // ZERO Output is set to 0 2868 #define GPIO_DOUT31_0_DIO21 0x00200000U 2869 #define GPIO_DOUT31_0_DIO21_M 0x00200000U 2870 #define GPIO_DOUT31_0_DIO21_S 21U 2871 #define GPIO_DOUT31_0_DIO21_ONE 0x00200000U 2872 #define GPIO_DOUT31_0_DIO21_ZERO 0x00000000U 2873 2874 // Field: [20] DIO20 2875 // 2876 // Data output for DIO20 2877 // ENUMs: 2878 // ONE Output is set to 1 2879 // ZERO Output is set to 0 2880 #define GPIO_DOUT31_0_DIO20 0x00100000U 2881 #define GPIO_DOUT31_0_DIO20_M 0x00100000U 2882 #define GPIO_DOUT31_0_DIO20_S 20U 2883 #define GPIO_DOUT31_0_DIO20_ONE 0x00100000U 2884 #define GPIO_DOUT31_0_DIO20_ZERO 0x00000000U 2885 2886 // Field: [19] DIO19 2887 // 2888 // Data output for DIO19 2889 // ENUMs: 2890 // ONE Output is set to 1 2891 // ZERO Output is set to 0 2892 #define GPIO_DOUT31_0_DIO19 0x00080000U 2893 #define GPIO_DOUT31_0_DIO19_M 0x00080000U 2894 #define GPIO_DOUT31_0_DIO19_S 19U 2895 #define GPIO_DOUT31_0_DIO19_ONE 0x00080000U 2896 #define GPIO_DOUT31_0_DIO19_ZERO 0x00000000U 2897 2898 // Field: [18] DIO18 2899 // 2900 // Data output for DIO18 2901 // ENUMs: 2902 // ONE Output is set to 1 2903 // ZERO Output is set to 0 2904 #define GPIO_DOUT31_0_DIO18 0x00040000U 2905 #define GPIO_DOUT31_0_DIO18_M 0x00040000U 2906 #define GPIO_DOUT31_0_DIO18_S 18U 2907 #define GPIO_DOUT31_0_DIO18_ONE 0x00040000U 2908 #define GPIO_DOUT31_0_DIO18_ZERO 0x00000000U 2909 2910 // Field: [17] DIO17 2911 // 2912 // Data output for DIO17 2913 // ENUMs: 2914 // ONE Output is set to 1 2915 // ZERO Output is set to 0 2916 #define GPIO_DOUT31_0_DIO17 0x00020000U 2917 #define GPIO_DOUT31_0_DIO17_M 0x00020000U 2918 #define GPIO_DOUT31_0_DIO17_S 17U 2919 #define GPIO_DOUT31_0_DIO17_ONE 0x00020000U 2920 #define GPIO_DOUT31_0_DIO17_ZERO 0x00000000U 2921 2922 // Field: [16] DIO16 2923 // 2924 // Data output for DIO16 2925 // ENUMs: 2926 // ONE Output is set to 1 2927 // ZERO Output is set to 0 2928 #define GPIO_DOUT31_0_DIO16 0x00010000U 2929 #define GPIO_DOUT31_0_DIO16_M 0x00010000U 2930 #define GPIO_DOUT31_0_DIO16_S 16U 2931 #define GPIO_DOUT31_0_DIO16_ONE 0x00010000U 2932 #define GPIO_DOUT31_0_DIO16_ZERO 0x00000000U 2933 2934 // Field: [15] DIO15 2935 // 2936 // Data output for DIO15 2937 // ENUMs: 2938 // ONE Output is set to 1 2939 // ZERO Output is set to 0 2940 #define GPIO_DOUT31_0_DIO15 0x00008000U 2941 #define GPIO_DOUT31_0_DIO15_M 0x00008000U 2942 #define GPIO_DOUT31_0_DIO15_S 15U 2943 #define GPIO_DOUT31_0_DIO15_ONE 0x00008000U 2944 #define GPIO_DOUT31_0_DIO15_ZERO 0x00000000U 2945 2946 // Field: [14] DIO14 2947 // 2948 // Data output for DIO14 2949 // ENUMs: 2950 // ONE Output is set to 1 2951 // ZERO Output is set to 0 2952 #define GPIO_DOUT31_0_DIO14 0x00004000U 2953 #define GPIO_DOUT31_0_DIO14_M 0x00004000U 2954 #define GPIO_DOUT31_0_DIO14_S 14U 2955 #define GPIO_DOUT31_0_DIO14_ONE 0x00004000U 2956 #define GPIO_DOUT31_0_DIO14_ZERO 0x00000000U 2957 2958 // Field: [13] DIO13 2959 // 2960 // Data output for DIO13 2961 // ENUMs: 2962 // ONE Output is set to 1 2963 // ZERO Output is set to 0 2964 #define GPIO_DOUT31_0_DIO13 0x00002000U 2965 #define GPIO_DOUT31_0_DIO13_M 0x00002000U 2966 #define GPIO_DOUT31_0_DIO13_S 13U 2967 #define GPIO_DOUT31_0_DIO13_ONE 0x00002000U 2968 #define GPIO_DOUT31_0_DIO13_ZERO 0x00000000U 2969 2970 // Field: [12] DIO12 2971 // 2972 // Data output for DIO12 2973 // ENUMs: 2974 // ONE Output is set to 1 2975 // ZERO Output is set to 0 2976 #define GPIO_DOUT31_0_DIO12 0x00001000U 2977 #define GPIO_DOUT31_0_DIO12_M 0x00001000U 2978 #define GPIO_DOUT31_0_DIO12_S 12U 2979 #define GPIO_DOUT31_0_DIO12_ONE 0x00001000U 2980 #define GPIO_DOUT31_0_DIO12_ZERO 0x00000000U 2981 2982 // Field: [11] DIO11 2983 // 2984 // Data output for DIO11 2985 // ENUMs: 2986 // ONE Output is set to 1 2987 // ZERO Output is set to 0 2988 #define GPIO_DOUT31_0_DIO11 0x00000800U 2989 #define GPIO_DOUT31_0_DIO11_M 0x00000800U 2990 #define GPIO_DOUT31_0_DIO11_S 11U 2991 #define GPIO_DOUT31_0_DIO11_ONE 0x00000800U 2992 #define GPIO_DOUT31_0_DIO11_ZERO 0x00000000U 2993 2994 // Field: [10] DIO10 2995 // 2996 // Data output for DIO10 2997 // ENUMs: 2998 // ONE Output is set to 1 2999 // ZERO Output is set to 0 3000 #define GPIO_DOUT31_0_DIO10 0x00000400U 3001 #define GPIO_DOUT31_0_DIO10_M 0x00000400U 3002 #define GPIO_DOUT31_0_DIO10_S 10U 3003 #define GPIO_DOUT31_0_DIO10_ONE 0x00000400U 3004 #define GPIO_DOUT31_0_DIO10_ZERO 0x00000000U 3005 3006 // Field: [9] DIO9 3007 // 3008 // Data output for DIO9 3009 // ENUMs: 3010 // ONE Output is set to 1 3011 // ZERO Output is set to 0 3012 #define GPIO_DOUT31_0_DIO9 0x00000200U 3013 #define GPIO_DOUT31_0_DIO9_M 0x00000200U 3014 #define GPIO_DOUT31_0_DIO9_S 9U 3015 #define GPIO_DOUT31_0_DIO9_ONE 0x00000200U 3016 #define GPIO_DOUT31_0_DIO9_ZERO 0x00000000U 3017 3018 // Field: [8] DIO8 3019 // 3020 // Data output for DIO8 3021 // ENUMs: 3022 // ONE Output is set to 1 3023 // ZERO Output is set to 0 3024 #define GPIO_DOUT31_0_DIO8 0x00000100U 3025 #define GPIO_DOUT31_0_DIO8_M 0x00000100U 3026 #define GPIO_DOUT31_0_DIO8_S 8U 3027 #define GPIO_DOUT31_0_DIO8_ONE 0x00000100U 3028 #define GPIO_DOUT31_0_DIO8_ZERO 0x00000000U 3029 3030 // Field: [7] DIO7 3031 // 3032 // Data output for DIO7 3033 // ENUMs: 3034 // ONE Output is set to 1 3035 // ZERO Output is set to 0 3036 #define GPIO_DOUT31_0_DIO7 0x00000080U 3037 #define GPIO_DOUT31_0_DIO7_M 0x00000080U 3038 #define GPIO_DOUT31_0_DIO7_S 7U 3039 #define GPIO_DOUT31_0_DIO7_ONE 0x00000080U 3040 #define GPIO_DOUT31_0_DIO7_ZERO 0x00000000U 3041 3042 // Field: [6] DIO6 3043 // 3044 // Data output for DIO6 3045 // ENUMs: 3046 // ONE Output is set to 1 3047 // ZERO Output is set to 0 3048 #define GPIO_DOUT31_0_DIO6 0x00000040U 3049 #define GPIO_DOUT31_0_DIO6_M 0x00000040U 3050 #define GPIO_DOUT31_0_DIO6_S 6U 3051 #define GPIO_DOUT31_0_DIO6_ONE 0x00000040U 3052 #define GPIO_DOUT31_0_DIO6_ZERO 0x00000000U 3053 3054 // Field: [5] DIO5 3055 // 3056 // Data output for DIO5 3057 // ENUMs: 3058 // ONE Output is set to 1 3059 // ZERO Output is set to 0 3060 #define GPIO_DOUT31_0_DIO5 0x00000020U 3061 #define GPIO_DOUT31_0_DIO5_M 0x00000020U 3062 #define GPIO_DOUT31_0_DIO5_S 5U 3063 #define GPIO_DOUT31_0_DIO5_ONE 0x00000020U 3064 #define GPIO_DOUT31_0_DIO5_ZERO 0x00000000U 3065 3066 // Field: [4] DIO4 3067 // 3068 // Data output for DIO4 3069 // ENUMs: 3070 // ONE Output is set to 1 3071 // ZERO Output is set to 0 3072 #define GPIO_DOUT31_0_DIO4 0x00000010U 3073 #define GPIO_DOUT31_0_DIO4_M 0x00000010U 3074 #define GPIO_DOUT31_0_DIO4_S 4U 3075 #define GPIO_DOUT31_0_DIO4_ONE 0x00000010U 3076 #define GPIO_DOUT31_0_DIO4_ZERO 0x00000000U 3077 3078 // Field: [3] DIO3 3079 // 3080 // Data output for DIO3 3081 // ENUMs: 3082 // ONE Output is set to 1 3083 // ZERO Output is set to 0 3084 #define GPIO_DOUT31_0_DIO3 0x00000008U 3085 #define GPIO_DOUT31_0_DIO3_M 0x00000008U 3086 #define GPIO_DOUT31_0_DIO3_S 3U 3087 #define GPIO_DOUT31_0_DIO3_ONE 0x00000008U 3088 #define GPIO_DOUT31_0_DIO3_ZERO 0x00000000U 3089 3090 // Field: [2] DIO2 3091 // 3092 // Data output for DIO2 3093 // ENUMs: 3094 // ONE Output is set to 1 3095 // ZERO Output is set to 0 3096 #define GPIO_DOUT31_0_DIO2 0x00000004U 3097 #define GPIO_DOUT31_0_DIO2_M 0x00000004U 3098 #define GPIO_DOUT31_0_DIO2_S 2U 3099 #define GPIO_DOUT31_0_DIO2_ONE 0x00000004U 3100 #define GPIO_DOUT31_0_DIO2_ZERO 0x00000000U 3101 3102 // Field: [1] DIO1 3103 // 3104 // Data output for DIO1 3105 // ENUMs: 3106 // ONE Output is set to 1 3107 // ZERO Output is set to 0 3108 #define GPIO_DOUT31_0_DIO1 0x00000002U 3109 #define GPIO_DOUT31_0_DIO1_M 0x00000002U 3110 #define GPIO_DOUT31_0_DIO1_S 1U 3111 #define GPIO_DOUT31_0_DIO1_ONE 0x00000002U 3112 #define GPIO_DOUT31_0_DIO1_ZERO 0x00000000U 3113 3114 // Field: [0] DIO0 3115 // 3116 // Data output for DIO0 3117 // ENUMs: 3118 // ONE Output is set to 1 3119 // ZERO Output is set to 0 3120 #define GPIO_DOUT31_0_DIO0 0x00000001U 3121 #define GPIO_DOUT31_0_DIO0_M 0x00000001U 3122 #define GPIO_DOUT31_0_DIO0_S 0U 3123 #define GPIO_DOUT31_0_DIO0_ONE 0x00000001U 3124 #define GPIO_DOUT31_0_DIO0_ZERO 0x00000000U 3125 3126 //***************************************************************************** 3127 // 3128 // Register: GPIO_O_DOUTSET31_0 3129 // 3130 //***************************************************************************** 3131 // Field: [25] DIO25 3132 // 3133 // Set bit DOUT31_0.DIO25 3134 // ENUMs: 3135 // SET 3136 // NOEFF No effect 3137 #define GPIO_DOUTSET31_0_DIO25 0x02000000U 3138 #define GPIO_DOUTSET31_0_DIO25_M 0x02000000U 3139 #define GPIO_DOUTSET31_0_DIO25_S 25U 3140 #define GPIO_DOUTSET31_0_DIO25_SET 0x02000000U 3141 #define GPIO_DOUTSET31_0_DIO25_NOEFF 0x00000000U 3142 3143 // Field: [24] DIO24 3144 // 3145 // Set bit DOUT31_0.DIO24 3146 // ENUMs: 3147 // SET 3148 // NOEFF No effect 3149 #define GPIO_DOUTSET31_0_DIO24 0x01000000U 3150 #define GPIO_DOUTSET31_0_DIO24_M 0x01000000U 3151 #define GPIO_DOUTSET31_0_DIO24_S 24U 3152 #define GPIO_DOUTSET31_0_DIO24_SET 0x01000000U 3153 #define GPIO_DOUTSET31_0_DIO24_NOEFF 0x00000000U 3154 3155 // Field: [23] DIO23 3156 // 3157 // Set bit DOUT31_0.DIO23 3158 // ENUMs: 3159 // SET 3160 // NOEFF No effect 3161 #define GPIO_DOUTSET31_0_DIO23 0x00800000U 3162 #define GPIO_DOUTSET31_0_DIO23_M 0x00800000U 3163 #define GPIO_DOUTSET31_0_DIO23_S 23U 3164 #define GPIO_DOUTSET31_0_DIO23_SET 0x00800000U 3165 #define GPIO_DOUTSET31_0_DIO23_NOEFF 0x00000000U 3166 3167 // Field: [22] DIO22 3168 // 3169 // Set bit DOUT31_0.DIO22 3170 // ENUMs: 3171 // SET 3172 // NOEFF No effect 3173 #define GPIO_DOUTSET31_0_DIO22 0x00400000U 3174 #define GPIO_DOUTSET31_0_DIO22_M 0x00400000U 3175 #define GPIO_DOUTSET31_0_DIO22_S 22U 3176 #define GPIO_DOUTSET31_0_DIO22_SET 0x00400000U 3177 #define GPIO_DOUTSET31_0_DIO22_NOEFF 0x00000000U 3178 3179 // Field: [21] DIO21 3180 // 3181 // Set bit DOUT31_0.DIO21 3182 // ENUMs: 3183 // SET 3184 // NOEFF No effect 3185 #define GPIO_DOUTSET31_0_DIO21 0x00200000U 3186 #define GPIO_DOUTSET31_0_DIO21_M 0x00200000U 3187 #define GPIO_DOUTSET31_0_DIO21_S 21U 3188 #define GPIO_DOUTSET31_0_DIO21_SET 0x00200000U 3189 #define GPIO_DOUTSET31_0_DIO21_NOEFF 0x00000000U 3190 3191 // Field: [20] DIO20 3192 // 3193 // Set bit DOUT31_0.DIO20 3194 // ENUMs: 3195 // SET 3196 // NOEFF No effect 3197 #define GPIO_DOUTSET31_0_DIO20 0x00100000U 3198 #define GPIO_DOUTSET31_0_DIO20_M 0x00100000U 3199 #define GPIO_DOUTSET31_0_DIO20_S 20U 3200 #define GPIO_DOUTSET31_0_DIO20_SET 0x00100000U 3201 #define GPIO_DOUTSET31_0_DIO20_NOEFF 0x00000000U 3202 3203 // Field: [19] DIO19 3204 // 3205 // Set bit DOUT31_0.DIO19 3206 // ENUMs: 3207 // SET 3208 // NOEFF No effect 3209 #define GPIO_DOUTSET31_0_DIO19 0x00080000U 3210 #define GPIO_DOUTSET31_0_DIO19_M 0x00080000U 3211 #define GPIO_DOUTSET31_0_DIO19_S 19U 3212 #define GPIO_DOUTSET31_0_DIO19_SET 0x00080000U 3213 #define GPIO_DOUTSET31_0_DIO19_NOEFF 0x00000000U 3214 3215 // Field: [18] DIO18 3216 // 3217 // Set bit DOUT31_0.DIO18 3218 // ENUMs: 3219 // SET 3220 // NOEFF No effect 3221 #define GPIO_DOUTSET31_0_DIO18 0x00040000U 3222 #define GPIO_DOUTSET31_0_DIO18_M 0x00040000U 3223 #define GPIO_DOUTSET31_0_DIO18_S 18U 3224 #define GPIO_DOUTSET31_0_DIO18_SET 0x00040000U 3225 #define GPIO_DOUTSET31_0_DIO18_NOEFF 0x00000000U 3226 3227 // Field: [17] DIO17 3228 // 3229 // Set bit DOUT31_0.DIO17 3230 // ENUMs: 3231 // SET 3232 // NOEFF No effect 3233 #define GPIO_DOUTSET31_0_DIO17 0x00020000U 3234 #define GPIO_DOUTSET31_0_DIO17_M 0x00020000U 3235 #define GPIO_DOUTSET31_0_DIO17_S 17U 3236 #define GPIO_DOUTSET31_0_DIO17_SET 0x00020000U 3237 #define GPIO_DOUTSET31_0_DIO17_NOEFF 0x00000000U 3238 3239 // Field: [16] DIO16 3240 // 3241 // Set bit DOUT31_0.DIO16 3242 // ENUMs: 3243 // SET 3244 // NOEFF No effect 3245 #define GPIO_DOUTSET31_0_DIO16 0x00010000U 3246 #define GPIO_DOUTSET31_0_DIO16_M 0x00010000U 3247 #define GPIO_DOUTSET31_0_DIO16_S 16U 3248 #define GPIO_DOUTSET31_0_DIO16_SET 0x00010000U 3249 #define GPIO_DOUTSET31_0_DIO16_NOEFF 0x00000000U 3250 3251 // Field: [15] DIO15 3252 // 3253 // Set bit DOUT31_0.DIO15 3254 // ENUMs: 3255 // SET 3256 // NOEFF No effect 3257 #define GPIO_DOUTSET31_0_DIO15 0x00008000U 3258 #define GPIO_DOUTSET31_0_DIO15_M 0x00008000U 3259 #define GPIO_DOUTSET31_0_DIO15_S 15U 3260 #define GPIO_DOUTSET31_0_DIO15_SET 0x00008000U 3261 #define GPIO_DOUTSET31_0_DIO15_NOEFF 0x00000000U 3262 3263 // Field: [14] DIO14 3264 // 3265 // Set bit DOUT31_0.DIO14 3266 // ENUMs: 3267 // SET 3268 // NOEFF No effect 3269 #define GPIO_DOUTSET31_0_DIO14 0x00004000U 3270 #define GPIO_DOUTSET31_0_DIO14_M 0x00004000U 3271 #define GPIO_DOUTSET31_0_DIO14_S 14U 3272 #define GPIO_DOUTSET31_0_DIO14_SET 0x00004000U 3273 #define GPIO_DOUTSET31_0_DIO14_NOEFF 0x00000000U 3274 3275 // Field: [13] DIO13 3276 // 3277 // Set bit DOUT31_0.DIO13 3278 // ENUMs: 3279 // SET 3280 // NOEFF No effect 3281 #define GPIO_DOUTSET31_0_DIO13 0x00002000U 3282 #define GPIO_DOUTSET31_0_DIO13_M 0x00002000U 3283 #define GPIO_DOUTSET31_0_DIO13_S 13U 3284 #define GPIO_DOUTSET31_0_DIO13_SET 0x00002000U 3285 #define GPIO_DOUTSET31_0_DIO13_NOEFF 0x00000000U 3286 3287 // Field: [12] DIO12 3288 // 3289 // Set bit DOUT31_0.DIO12 3290 // ENUMs: 3291 // SET 3292 // NOEFF No effect 3293 #define GPIO_DOUTSET31_0_DIO12 0x00001000U 3294 #define GPIO_DOUTSET31_0_DIO12_M 0x00001000U 3295 #define GPIO_DOUTSET31_0_DIO12_S 12U 3296 #define GPIO_DOUTSET31_0_DIO12_SET 0x00001000U 3297 #define GPIO_DOUTSET31_0_DIO12_NOEFF 0x00000000U 3298 3299 // Field: [11] DIO11 3300 // 3301 // Set bit DOUT31_0.DIO11 3302 // ENUMs: 3303 // SET 3304 // NOEFF No effect 3305 #define GPIO_DOUTSET31_0_DIO11 0x00000800U 3306 #define GPIO_DOUTSET31_0_DIO11_M 0x00000800U 3307 #define GPIO_DOUTSET31_0_DIO11_S 11U 3308 #define GPIO_DOUTSET31_0_DIO11_SET 0x00000800U 3309 #define GPIO_DOUTSET31_0_DIO11_NOEFF 0x00000000U 3310 3311 // Field: [10] DIO10 3312 // 3313 // Set bit DOUT31_0.DIO10 3314 // ENUMs: 3315 // SET 3316 // NOEFF No effect 3317 #define GPIO_DOUTSET31_0_DIO10 0x00000400U 3318 #define GPIO_DOUTSET31_0_DIO10_M 0x00000400U 3319 #define GPIO_DOUTSET31_0_DIO10_S 10U 3320 #define GPIO_DOUTSET31_0_DIO10_SET 0x00000400U 3321 #define GPIO_DOUTSET31_0_DIO10_NOEFF 0x00000000U 3322 3323 // Field: [9] DIO9 3324 // 3325 // Set bit DOUT31_0.DIO9 3326 // ENUMs: 3327 // SET 3328 // NOEFF No effect 3329 #define GPIO_DOUTSET31_0_DIO9 0x00000200U 3330 #define GPIO_DOUTSET31_0_DIO9_M 0x00000200U 3331 #define GPIO_DOUTSET31_0_DIO9_S 9U 3332 #define GPIO_DOUTSET31_0_DIO9_SET 0x00000200U 3333 #define GPIO_DOUTSET31_0_DIO9_NOEFF 0x00000000U 3334 3335 // Field: [8] DIO8 3336 // 3337 // Set bit DOUT31_0.DIO8 3338 // ENUMs: 3339 // SET 3340 // NOEFF No effect 3341 #define GPIO_DOUTSET31_0_DIO8 0x00000100U 3342 #define GPIO_DOUTSET31_0_DIO8_M 0x00000100U 3343 #define GPIO_DOUTSET31_0_DIO8_S 8U 3344 #define GPIO_DOUTSET31_0_DIO8_SET 0x00000100U 3345 #define GPIO_DOUTSET31_0_DIO8_NOEFF 0x00000000U 3346 3347 // Field: [7] DIO7 3348 // 3349 // Set bit DOUT31_0.DIO7 3350 // ENUMs: 3351 // SET 3352 // NOEFF No effect 3353 #define GPIO_DOUTSET31_0_DIO7 0x00000080U 3354 #define GPIO_DOUTSET31_0_DIO7_M 0x00000080U 3355 #define GPIO_DOUTSET31_0_DIO7_S 7U 3356 #define GPIO_DOUTSET31_0_DIO7_SET 0x00000080U 3357 #define GPIO_DOUTSET31_0_DIO7_NOEFF 0x00000000U 3358 3359 // Field: [6] DIO6 3360 // 3361 // Set bit DOUT31_0.DIO6 3362 // ENUMs: 3363 // SET 3364 // NOEFF No effect 3365 #define GPIO_DOUTSET31_0_DIO6 0x00000040U 3366 #define GPIO_DOUTSET31_0_DIO6_M 0x00000040U 3367 #define GPIO_DOUTSET31_0_DIO6_S 6U 3368 #define GPIO_DOUTSET31_0_DIO6_SET 0x00000040U 3369 #define GPIO_DOUTSET31_0_DIO6_NOEFF 0x00000000U 3370 3371 // Field: [5] DIO5 3372 // 3373 // Set bit DOUT31_0.DIO5 3374 // ENUMs: 3375 // SET 3376 // NOEFF No effect 3377 #define GPIO_DOUTSET31_0_DIO5 0x00000020U 3378 #define GPIO_DOUTSET31_0_DIO5_M 0x00000020U 3379 #define GPIO_DOUTSET31_0_DIO5_S 5U 3380 #define GPIO_DOUTSET31_0_DIO5_SET 0x00000020U 3381 #define GPIO_DOUTSET31_0_DIO5_NOEFF 0x00000000U 3382 3383 // Field: [4] DIO4 3384 // 3385 // Set bit DOUT31_0.DIO4 3386 // ENUMs: 3387 // SET 3388 // NOEFF No effect 3389 #define GPIO_DOUTSET31_0_DIO4 0x00000010U 3390 #define GPIO_DOUTSET31_0_DIO4_M 0x00000010U 3391 #define GPIO_DOUTSET31_0_DIO4_S 4U 3392 #define GPIO_DOUTSET31_0_DIO4_SET 0x00000010U 3393 #define GPIO_DOUTSET31_0_DIO4_NOEFF 0x00000000U 3394 3395 // Field: [3] DIO3 3396 // 3397 // Set bit DOUT31_0.DIO3 3398 // ENUMs: 3399 // SET 3400 // NOEFF No effect 3401 #define GPIO_DOUTSET31_0_DIO3 0x00000008U 3402 #define GPIO_DOUTSET31_0_DIO3_M 0x00000008U 3403 #define GPIO_DOUTSET31_0_DIO3_S 3U 3404 #define GPIO_DOUTSET31_0_DIO3_SET 0x00000008U 3405 #define GPIO_DOUTSET31_0_DIO3_NOEFF 0x00000000U 3406 3407 // Field: [2] DIO2 3408 // 3409 // Set bit DOUT31_0.DIO2 3410 // ENUMs: 3411 // SET 3412 // NOEFF No effect 3413 #define GPIO_DOUTSET31_0_DIO2 0x00000004U 3414 #define GPIO_DOUTSET31_0_DIO2_M 0x00000004U 3415 #define GPIO_DOUTSET31_0_DIO2_S 2U 3416 #define GPIO_DOUTSET31_0_DIO2_SET 0x00000004U 3417 #define GPIO_DOUTSET31_0_DIO2_NOEFF 0x00000000U 3418 3419 // Field: [1] DIO1 3420 // 3421 // Set bit DOUT31_0.DIO1 3422 // ENUMs: 3423 // SET 3424 // NOEFF No effect 3425 #define GPIO_DOUTSET31_0_DIO1 0x00000002U 3426 #define GPIO_DOUTSET31_0_DIO1_M 0x00000002U 3427 #define GPIO_DOUTSET31_0_DIO1_S 1U 3428 #define GPIO_DOUTSET31_0_DIO1_SET 0x00000002U 3429 #define GPIO_DOUTSET31_0_DIO1_NOEFF 0x00000000U 3430 3431 // Field: [0] DIO0 3432 // 3433 // Set bit DOUT31_0.DIO0 3434 // ENUMs: 3435 // SET 3436 // NOEFF No effect 3437 #define GPIO_DOUTSET31_0_DIO0 0x00000001U 3438 #define GPIO_DOUTSET31_0_DIO0_M 0x00000001U 3439 #define GPIO_DOUTSET31_0_DIO0_S 0U 3440 #define GPIO_DOUTSET31_0_DIO0_SET 0x00000001U 3441 #define GPIO_DOUTSET31_0_DIO0_NOEFF 0x00000000U 3442 3443 //***************************************************************************** 3444 // 3445 // Register: GPIO_O_DOUTCLR31_0 3446 // 3447 //***************************************************************************** 3448 // Field: [25] DIO25 3449 // 3450 // Clear bit DOUT31_0.DIO25 3451 // ENUMs: 3452 // CLR Clear 3453 // NOEFF No effect 3454 #define GPIO_DOUTCLR31_0_DIO25 0x02000000U 3455 #define GPIO_DOUTCLR31_0_DIO25_M 0x02000000U 3456 #define GPIO_DOUTCLR31_0_DIO25_S 25U 3457 #define GPIO_DOUTCLR31_0_DIO25_CLR 0x02000000U 3458 #define GPIO_DOUTCLR31_0_DIO25_NOEFF 0x00000000U 3459 3460 // Field: [24] DIO24 3461 // 3462 // Clear bit DOUT31_0.DIO24 3463 // ENUMs: 3464 // CLR Clear 3465 // NOEFF No effect 3466 #define GPIO_DOUTCLR31_0_DIO24 0x01000000U 3467 #define GPIO_DOUTCLR31_0_DIO24_M 0x01000000U 3468 #define GPIO_DOUTCLR31_0_DIO24_S 24U 3469 #define GPIO_DOUTCLR31_0_DIO24_CLR 0x01000000U 3470 #define GPIO_DOUTCLR31_0_DIO24_NOEFF 0x00000000U 3471 3472 // Field: [23] DIO23 3473 // 3474 // Clear bit DOUT31_0.DIO23 3475 // ENUMs: 3476 // CLR Clear 3477 // NOEFF No effect 3478 #define GPIO_DOUTCLR31_0_DIO23 0x00800000U 3479 #define GPIO_DOUTCLR31_0_DIO23_M 0x00800000U 3480 #define GPIO_DOUTCLR31_0_DIO23_S 23U 3481 #define GPIO_DOUTCLR31_0_DIO23_CLR 0x00800000U 3482 #define GPIO_DOUTCLR31_0_DIO23_NOEFF 0x00000000U 3483 3484 // Field: [22] DIO22 3485 // 3486 // Clear bit DOUT31_0.DIO22 3487 // ENUMs: 3488 // CLR Clear 3489 // NOEFF No effect 3490 #define GPIO_DOUTCLR31_0_DIO22 0x00400000U 3491 #define GPIO_DOUTCLR31_0_DIO22_M 0x00400000U 3492 #define GPIO_DOUTCLR31_0_DIO22_S 22U 3493 #define GPIO_DOUTCLR31_0_DIO22_CLR 0x00400000U 3494 #define GPIO_DOUTCLR31_0_DIO22_NOEFF 0x00000000U 3495 3496 // Field: [21] DIO21 3497 // 3498 // Clear bit DOUT31_0.DIO21 3499 // ENUMs: 3500 // CLR Clear 3501 // NOEFF No effect 3502 #define GPIO_DOUTCLR31_0_DIO21 0x00200000U 3503 #define GPIO_DOUTCLR31_0_DIO21_M 0x00200000U 3504 #define GPIO_DOUTCLR31_0_DIO21_S 21U 3505 #define GPIO_DOUTCLR31_0_DIO21_CLR 0x00200000U 3506 #define GPIO_DOUTCLR31_0_DIO21_NOEFF 0x00000000U 3507 3508 // Field: [20] DIO20 3509 // 3510 // Clear bit DOUT31_0.DIO20 3511 // ENUMs: 3512 // CLR Clear 3513 // NOEFF No effect 3514 #define GPIO_DOUTCLR31_0_DIO20 0x00100000U 3515 #define GPIO_DOUTCLR31_0_DIO20_M 0x00100000U 3516 #define GPIO_DOUTCLR31_0_DIO20_S 20U 3517 #define GPIO_DOUTCLR31_0_DIO20_CLR 0x00100000U 3518 #define GPIO_DOUTCLR31_0_DIO20_NOEFF 0x00000000U 3519 3520 // Field: [19] DIO19 3521 // 3522 // Clear bit DOUT31_0.DIO19 3523 // ENUMs: 3524 // CLR Clear 3525 // NOEFF No effect 3526 #define GPIO_DOUTCLR31_0_DIO19 0x00080000U 3527 #define GPIO_DOUTCLR31_0_DIO19_M 0x00080000U 3528 #define GPIO_DOUTCLR31_0_DIO19_S 19U 3529 #define GPIO_DOUTCLR31_0_DIO19_CLR 0x00080000U 3530 #define GPIO_DOUTCLR31_0_DIO19_NOEFF 0x00000000U 3531 3532 // Field: [18] DIO18 3533 // 3534 // Clear bit DOUT31_0.DIO18 3535 // ENUMs: 3536 // CLR Clear 3537 // NOEFF No effect 3538 #define GPIO_DOUTCLR31_0_DIO18 0x00040000U 3539 #define GPIO_DOUTCLR31_0_DIO18_M 0x00040000U 3540 #define GPIO_DOUTCLR31_0_DIO18_S 18U 3541 #define GPIO_DOUTCLR31_0_DIO18_CLR 0x00040000U 3542 #define GPIO_DOUTCLR31_0_DIO18_NOEFF 0x00000000U 3543 3544 // Field: [17] DIO17 3545 // 3546 // Clear bit DOUT31_0.DIO17 3547 // ENUMs: 3548 // CLR Clear 3549 // NOEFF No effect 3550 #define GPIO_DOUTCLR31_0_DIO17 0x00020000U 3551 #define GPIO_DOUTCLR31_0_DIO17_M 0x00020000U 3552 #define GPIO_DOUTCLR31_0_DIO17_S 17U 3553 #define GPIO_DOUTCLR31_0_DIO17_CLR 0x00020000U 3554 #define GPIO_DOUTCLR31_0_DIO17_NOEFF 0x00000000U 3555 3556 // Field: [16] DIO16 3557 // 3558 // Clear bit DOUT31_0.DIO16 3559 // ENUMs: 3560 // CLR Clear 3561 // NOEFF No effect 3562 #define GPIO_DOUTCLR31_0_DIO16 0x00010000U 3563 #define GPIO_DOUTCLR31_0_DIO16_M 0x00010000U 3564 #define GPIO_DOUTCLR31_0_DIO16_S 16U 3565 #define GPIO_DOUTCLR31_0_DIO16_CLR 0x00010000U 3566 #define GPIO_DOUTCLR31_0_DIO16_NOEFF 0x00000000U 3567 3568 // Field: [15] DIO15 3569 // 3570 // Clear bit DOUT31_0.DIO15 3571 // ENUMs: 3572 // CLR Clear 3573 // NOEFF No effect 3574 #define GPIO_DOUTCLR31_0_DIO15 0x00008000U 3575 #define GPIO_DOUTCLR31_0_DIO15_M 0x00008000U 3576 #define GPIO_DOUTCLR31_0_DIO15_S 15U 3577 #define GPIO_DOUTCLR31_0_DIO15_CLR 0x00008000U 3578 #define GPIO_DOUTCLR31_0_DIO15_NOEFF 0x00000000U 3579 3580 // Field: [14] DIO14 3581 // 3582 // Clear bit DOUT31_0.DIO14 3583 // ENUMs: 3584 // CLR Clear 3585 // NOEFF No effect 3586 #define GPIO_DOUTCLR31_0_DIO14 0x00004000U 3587 #define GPIO_DOUTCLR31_0_DIO14_M 0x00004000U 3588 #define GPIO_DOUTCLR31_0_DIO14_S 14U 3589 #define GPIO_DOUTCLR31_0_DIO14_CLR 0x00004000U 3590 #define GPIO_DOUTCLR31_0_DIO14_NOEFF 0x00000000U 3591 3592 // Field: [13] DIO13 3593 // 3594 // Clear bit DOUT31_0.DIO13 3595 // ENUMs: 3596 // CLR Clear 3597 // NOEFF No effect 3598 #define GPIO_DOUTCLR31_0_DIO13 0x00002000U 3599 #define GPIO_DOUTCLR31_0_DIO13_M 0x00002000U 3600 #define GPIO_DOUTCLR31_0_DIO13_S 13U 3601 #define GPIO_DOUTCLR31_0_DIO13_CLR 0x00002000U 3602 #define GPIO_DOUTCLR31_0_DIO13_NOEFF 0x00000000U 3603 3604 // Field: [12] DIO12 3605 // 3606 // Clear bit DOUT31_0.DIO12 3607 // ENUMs: 3608 // CLR Clear 3609 // NOEFF No effect 3610 #define GPIO_DOUTCLR31_0_DIO12 0x00001000U 3611 #define GPIO_DOUTCLR31_0_DIO12_M 0x00001000U 3612 #define GPIO_DOUTCLR31_0_DIO12_S 12U 3613 #define GPIO_DOUTCLR31_0_DIO12_CLR 0x00001000U 3614 #define GPIO_DOUTCLR31_0_DIO12_NOEFF 0x00000000U 3615 3616 // Field: [11] DIO11 3617 // 3618 // Clear bit DOUT31_0.DIO11 3619 // ENUMs: 3620 // CLR Clear 3621 // NOEFF No effect 3622 #define GPIO_DOUTCLR31_0_DIO11 0x00000800U 3623 #define GPIO_DOUTCLR31_0_DIO11_M 0x00000800U 3624 #define GPIO_DOUTCLR31_0_DIO11_S 11U 3625 #define GPIO_DOUTCLR31_0_DIO11_CLR 0x00000800U 3626 #define GPIO_DOUTCLR31_0_DIO11_NOEFF 0x00000000U 3627 3628 // Field: [10] DIO10 3629 // 3630 // Clear bit DOUT31_0.DIO10 3631 // ENUMs: 3632 // CLR Clear 3633 // NOEFF No effect 3634 #define GPIO_DOUTCLR31_0_DIO10 0x00000400U 3635 #define GPIO_DOUTCLR31_0_DIO10_M 0x00000400U 3636 #define GPIO_DOUTCLR31_0_DIO10_S 10U 3637 #define GPIO_DOUTCLR31_0_DIO10_CLR 0x00000400U 3638 #define GPIO_DOUTCLR31_0_DIO10_NOEFF 0x00000000U 3639 3640 // Field: [9] DIO9 3641 // 3642 // Clear bit DOUT31_0.DIO9 3643 // ENUMs: 3644 // CLR Clear 3645 // NOEFF No effect 3646 #define GPIO_DOUTCLR31_0_DIO9 0x00000200U 3647 #define GPIO_DOUTCLR31_0_DIO9_M 0x00000200U 3648 #define GPIO_DOUTCLR31_0_DIO9_S 9U 3649 #define GPIO_DOUTCLR31_0_DIO9_CLR 0x00000200U 3650 #define GPIO_DOUTCLR31_0_DIO9_NOEFF 0x00000000U 3651 3652 // Field: [8] DIO8 3653 // 3654 // Clear bit DOUT31_0.DIO8 3655 // ENUMs: 3656 // CLR Clear 3657 // NOEFF No effect 3658 #define GPIO_DOUTCLR31_0_DIO8 0x00000100U 3659 #define GPIO_DOUTCLR31_0_DIO8_M 0x00000100U 3660 #define GPIO_DOUTCLR31_0_DIO8_S 8U 3661 #define GPIO_DOUTCLR31_0_DIO8_CLR 0x00000100U 3662 #define GPIO_DOUTCLR31_0_DIO8_NOEFF 0x00000000U 3663 3664 // Field: [7] DIO7 3665 // 3666 // Clear bit DOUT31_0.DIO7 3667 // ENUMs: 3668 // CLR Clear 3669 // NOEFF No effect 3670 #define GPIO_DOUTCLR31_0_DIO7 0x00000080U 3671 #define GPIO_DOUTCLR31_0_DIO7_M 0x00000080U 3672 #define GPIO_DOUTCLR31_0_DIO7_S 7U 3673 #define GPIO_DOUTCLR31_0_DIO7_CLR 0x00000080U 3674 #define GPIO_DOUTCLR31_0_DIO7_NOEFF 0x00000000U 3675 3676 // Field: [6] DIO6 3677 // 3678 // Clear bit DOUT31_0.DIO6 3679 // ENUMs: 3680 // CLR Clear 3681 // NOEFF No effect 3682 #define GPIO_DOUTCLR31_0_DIO6 0x00000040U 3683 #define GPIO_DOUTCLR31_0_DIO6_M 0x00000040U 3684 #define GPIO_DOUTCLR31_0_DIO6_S 6U 3685 #define GPIO_DOUTCLR31_0_DIO6_CLR 0x00000040U 3686 #define GPIO_DOUTCLR31_0_DIO6_NOEFF 0x00000000U 3687 3688 // Field: [5] DIO5 3689 // 3690 // Clear bit DOUT31_0.DIO5 3691 // ENUMs: 3692 // CLR Clear 3693 // NOEFF No effect 3694 #define GPIO_DOUTCLR31_0_DIO5 0x00000020U 3695 #define GPIO_DOUTCLR31_0_DIO5_M 0x00000020U 3696 #define GPIO_DOUTCLR31_0_DIO5_S 5U 3697 #define GPIO_DOUTCLR31_0_DIO5_CLR 0x00000020U 3698 #define GPIO_DOUTCLR31_0_DIO5_NOEFF 0x00000000U 3699 3700 // Field: [4] DIO4 3701 // 3702 // Clear bit DOUT31_0.DIO4 3703 // ENUMs: 3704 // CLR Clear 3705 // NOEFF No effect 3706 #define GPIO_DOUTCLR31_0_DIO4 0x00000010U 3707 #define GPIO_DOUTCLR31_0_DIO4_M 0x00000010U 3708 #define GPIO_DOUTCLR31_0_DIO4_S 4U 3709 #define GPIO_DOUTCLR31_0_DIO4_CLR 0x00000010U 3710 #define GPIO_DOUTCLR31_0_DIO4_NOEFF 0x00000000U 3711 3712 // Field: [3] DIO3 3713 // 3714 // Clear bit DOUT31_0.DIO3 3715 // ENUMs: 3716 // CLR Clear 3717 // NOEFF No effect 3718 #define GPIO_DOUTCLR31_0_DIO3 0x00000008U 3719 #define GPIO_DOUTCLR31_0_DIO3_M 0x00000008U 3720 #define GPIO_DOUTCLR31_0_DIO3_S 3U 3721 #define GPIO_DOUTCLR31_0_DIO3_CLR 0x00000008U 3722 #define GPIO_DOUTCLR31_0_DIO3_NOEFF 0x00000000U 3723 3724 // Field: [2] DIO2 3725 // 3726 // Clear bit DOUT31_0.DIO2 3727 // ENUMs: 3728 // CLR Clear 3729 // NOEFF No effect 3730 #define GPIO_DOUTCLR31_0_DIO2 0x00000004U 3731 #define GPIO_DOUTCLR31_0_DIO2_M 0x00000004U 3732 #define GPIO_DOUTCLR31_0_DIO2_S 2U 3733 #define GPIO_DOUTCLR31_0_DIO2_CLR 0x00000004U 3734 #define GPIO_DOUTCLR31_0_DIO2_NOEFF 0x00000000U 3735 3736 // Field: [1] DIO1 3737 // 3738 // Clear bit DOUT31_0.DIO1 3739 // ENUMs: 3740 // CLR Clear 3741 // NOEFF No effect 3742 #define GPIO_DOUTCLR31_0_DIO1 0x00000002U 3743 #define GPIO_DOUTCLR31_0_DIO1_M 0x00000002U 3744 #define GPIO_DOUTCLR31_0_DIO1_S 1U 3745 #define GPIO_DOUTCLR31_0_DIO1_CLR 0x00000002U 3746 #define GPIO_DOUTCLR31_0_DIO1_NOEFF 0x00000000U 3747 3748 // Field: [0] DIO0 3749 // 3750 // Clear bit DOUT31_0.DIO0 3751 // ENUMs: 3752 // CLR Clear 3753 // NOEFF No effect 3754 #define GPIO_DOUTCLR31_0_DIO0 0x00000001U 3755 #define GPIO_DOUTCLR31_0_DIO0_M 0x00000001U 3756 #define GPIO_DOUTCLR31_0_DIO0_S 0U 3757 #define GPIO_DOUTCLR31_0_DIO0_CLR 0x00000001U 3758 #define GPIO_DOUTCLR31_0_DIO0_NOEFF 0x00000000U 3759 3760 //***************************************************************************** 3761 // 3762 // Register: GPIO_O_DOUTTGL31_0 3763 // 3764 //***************************************************************************** 3765 // Field: [25] DIO25 3766 // 3767 // Toggles bit DOUT31_0.DIO25 3768 // ENUMs: 3769 // TOGGLE Toggle 3770 // NOEFF No effect 3771 #define GPIO_DOUTTGL31_0_DIO25 0x02000000U 3772 #define GPIO_DOUTTGL31_0_DIO25_M 0x02000000U 3773 #define GPIO_DOUTTGL31_0_DIO25_S 25U 3774 #define GPIO_DOUTTGL31_0_DIO25_TOGGLE 0x02000000U 3775 #define GPIO_DOUTTGL31_0_DIO25_NOEFF 0x00000000U 3776 3777 // Field: [24] DIO24 3778 // 3779 // Toggles bit DOUT31_0.DIO24 3780 // ENUMs: 3781 // TOGGLE Toggle 3782 // NOEFF No effect 3783 #define GPIO_DOUTTGL31_0_DIO24 0x01000000U 3784 #define GPIO_DOUTTGL31_0_DIO24_M 0x01000000U 3785 #define GPIO_DOUTTGL31_0_DIO24_S 24U 3786 #define GPIO_DOUTTGL31_0_DIO24_TOGGLE 0x01000000U 3787 #define GPIO_DOUTTGL31_0_DIO24_NOEFF 0x00000000U 3788 3789 // Field: [23] DIO23 3790 // 3791 // Toggles bit DOUT31_0.DIO23 3792 // ENUMs: 3793 // TOGGLE Toggle 3794 // NOEFF No effect 3795 #define GPIO_DOUTTGL31_0_DIO23 0x00800000U 3796 #define GPIO_DOUTTGL31_0_DIO23_M 0x00800000U 3797 #define GPIO_DOUTTGL31_0_DIO23_S 23U 3798 #define GPIO_DOUTTGL31_0_DIO23_TOGGLE 0x00800000U 3799 #define GPIO_DOUTTGL31_0_DIO23_NOEFF 0x00000000U 3800 3801 // Field: [22] DIO22 3802 // 3803 // Toggles bit DOUT31_0.DIO22 3804 // ENUMs: 3805 // TOGGLE Toggle 3806 // NOEFF No effect 3807 #define GPIO_DOUTTGL31_0_DIO22 0x00400000U 3808 #define GPIO_DOUTTGL31_0_DIO22_M 0x00400000U 3809 #define GPIO_DOUTTGL31_0_DIO22_S 22U 3810 #define GPIO_DOUTTGL31_0_DIO22_TOGGLE 0x00400000U 3811 #define GPIO_DOUTTGL31_0_DIO22_NOEFF 0x00000000U 3812 3813 // Field: [21] DIO21 3814 // 3815 // Toggles bit DOUT31_0.DIO21 3816 // ENUMs: 3817 // TOGGLE Toggle 3818 // NOEFF No effect 3819 #define GPIO_DOUTTGL31_0_DIO21 0x00200000U 3820 #define GPIO_DOUTTGL31_0_DIO21_M 0x00200000U 3821 #define GPIO_DOUTTGL31_0_DIO21_S 21U 3822 #define GPIO_DOUTTGL31_0_DIO21_TOGGLE 0x00200000U 3823 #define GPIO_DOUTTGL31_0_DIO21_NOEFF 0x00000000U 3824 3825 // Field: [20] DIO20 3826 // 3827 // Toggles bit DOUT31_0.DIO20 3828 // ENUMs: 3829 // TOGGLE Toggle 3830 // NOEFF No effect 3831 #define GPIO_DOUTTGL31_0_DIO20 0x00100000U 3832 #define GPIO_DOUTTGL31_0_DIO20_M 0x00100000U 3833 #define GPIO_DOUTTGL31_0_DIO20_S 20U 3834 #define GPIO_DOUTTGL31_0_DIO20_TOGGLE 0x00100000U 3835 #define GPIO_DOUTTGL31_0_DIO20_NOEFF 0x00000000U 3836 3837 // Field: [19] DIO19 3838 // 3839 // Toggles bit DOUT31_0.DIO19 3840 // ENUMs: 3841 // TOGGLE Toggle 3842 // NOEFF No effect 3843 #define GPIO_DOUTTGL31_0_DIO19 0x00080000U 3844 #define GPIO_DOUTTGL31_0_DIO19_M 0x00080000U 3845 #define GPIO_DOUTTGL31_0_DIO19_S 19U 3846 #define GPIO_DOUTTGL31_0_DIO19_TOGGLE 0x00080000U 3847 #define GPIO_DOUTTGL31_0_DIO19_NOEFF 0x00000000U 3848 3849 // Field: [18] DIO18 3850 // 3851 // Toggles bit DOUT31_0.DIO18 3852 // ENUMs: 3853 // TOGGLE Toggle 3854 // NOEFF No effect 3855 #define GPIO_DOUTTGL31_0_DIO18 0x00040000U 3856 #define GPIO_DOUTTGL31_0_DIO18_M 0x00040000U 3857 #define GPIO_DOUTTGL31_0_DIO18_S 18U 3858 #define GPIO_DOUTTGL31_0_DIO18_TOGGLE 0x00040000U 3859 #define GPIO_DOUTTGL31_0_DIO18_NOEFF 0x00000000U 3860 3861 // Field: [17] DIO17 3862 // 3863 // Toggles bit DOUT31_0.DIO17 3864 // ENUMs: 3865 // TOGGLE Toggle 3866 // NOEFF No effect 3867 #define GPIO_DOUTTGL31_0_DIO17 0x00020000U 3868 #define GPIO_DOUTTGL31_0_DIO17_M 0x00020000U 3869 #define GPIO_DOUTTGL31_0_DIO17_S 17U 3870 #define GPIO_DOUTTGL31_0_DIO17_TOGGLE 0x00020000U 3871 #define GPIO_DOUTTGL31_0_DIO17_NOEFF 0x00000000U 3872 3873 // Field: [16] DIO16 3874 // 3875 // Toggles bit DOUT31_0.DIO16 3876 // ENUMs: 3877 // TOGGLE Toggle 3878 // NOEFF No effect 3879 #define GPIO_DOUTTGL31_0_DIO16 0x00010000U 3880 #define GPIO_DOUTTGL31_0_DIO16_M 0x00010000U 3881 #define GPIO_DOUTTGL31_0_DIO16_S 16U 3882 #define GPIO_DOUTTGL31_0_DIO16_TOGGLE 0x00010000U 3883 #define GPIO_DOUTTGL31_0_DIO16_NOEFF 0x00000000U 3884 3885 // Field: [15] DIO15 3886 // 3887 // Toggles bit DOUT31_0.DIO15 3888 // ENUMs: 3889 // TOGGLE Toggle 3890 // NOEFF No effect 3891 #define GPIO_DOUTTGL31_0_DIO15 0x00008000U 3892 #define GPIO_DOUTTGL31_0_DIO15_M 0x00008000U 3893 #define GPIO_DOUTTGL31_0_DIO15_S 15U 3894 #define GPIO_DOUTTGL31_0_DIO15_TOGGLE 0x00008000U 3895 #define GPIO_DOUTTGL31_0_DIO15_NOEFF 0x00000000U 3896 3897 // Field: [14] DIO14 3898 // 3899 // Toggles bit DOUT31_0.DIO14 3900 // ENUMs: 3901 // TOGGLE Toggle 3902 // NOEFF No effect 3903 #define GPIO_DOUTTGL31_0_DIO14 0x00004000U 3904 #define GPIO_DOUTTGL31_0_DIO14_M 0x00004000U 3905 #define GPIO_DOUTTGL31_0_DIO14_S 14U 3906 #define GPIO_DOUTTGL31_0_DIO14_TOGGLE 0x00004000U 3907 #define GPIO_DOUTTGL31_0_DIO14_NOEFF 0x00000000U 3908 3909 // Field: [13] DIO13 3910 // 3911 // Toggles bit DOUT31_0.DIO13 3912 // ENUMs: 3913 // TOGGLE Toggle 3914 // NOEFF No effect 3915 #define GPIO_DOUTTGL31_0_DIO13 0x00002000U 3916 #define GPIO_DOUTTGL31_0_DIO13_M 0x00002000U 3917 #define GPIO_DOUTTGL31_0_DIO13_S 13U 3918 #define GPIO_DOUTTGL31_0_DIO13_TOGGLE 0x00002000U 3919 #define GPIO_DOUTTGL31_0_DIO13_NOEFF 0x00000000U 3920 3921 // Field: [12] DIO12 3922 // 3923 // Toggles bit DOUT31_0.DIO12 3924 // ENUMs: 3925 // TOGGLE Toggle 3926 // NOEFF No effect 3927 #define GPIO_DOUTTGL31_0_DIO12 0x00001000U 3928 #define GPIO_DOUTTGL31_0_DIO12_M 0x00001000U 3929 #define GPIO_DOUTTGL31_0_DIO12_S 12U 3930 #define GPIO_DOUTTGL31_0_DIO12_TOGGLE 0x00001000U 3931 #define GPIO_DOUTTGL31_0_DIO12_NOEFF 0x00000000U 3932 3933 // Field: [11] DIO11 3934 // 3935 // Toggles bit DOUT31_0.DIO11 3936 // ENUMs: 3937 // TOGGLE Toggle 3938 // NOEFF No effect 3939 #define GPIO_DOUTTGL31_0_DIO11 0x00000800U 3940 #define GPIO_DOUTTGL31_0_DIO11_M 0x00000800U 3941 #define GPIO_DOUTTGL31_0_DIO11_S 11U 3942 #define GPIO_DOUTTGL31_0_DIO11_TOGGLE 0x00000800U 3943 #define GPIO_DOUTTGL31_0_DIO11_NOEFF 0x00000000U 3944 3945 // Field: [10] DIO10 3946 // 3947 // Toggles bit DOUT31_0.DIO10 3948 // ENUMs: 3949 // TOGGLE Toggle 3950 // NOEFF No effect 3951 #define GPIO_DOUTTGL31_0_DIO10 0x00000400U 3952 #define GPIO_DOUTTGL31_0_DIO10_M 0x00000400U 3953 #define GPIO_DOUTTGL31_0_DIO10_S 10U 3954 #define GPIO_DOUTTGL31_0_DIO10_TOGGLE 0x00000400U 3955 #define GPIO_DOUTTGL31_0_DIO10_NOEFF 0x00000000U 3956 3957 // Field: [9] DIO9 3958 // 3959 // Toggles bit DOUT31_0.DIO9 3960 // ENUMs: 3961 // TOGGLE Toggle 3962 // NOEFF No effect 3963 #define GPIO_DOUTTGL31_0_DIO9 0x00000200U 3964 #define GPIO_DOUTTGL31_0_DIO9_M 0x00000200U 3965 #define GPIO_DOUTTGL31_0_DIO9_S 9U 3966 #define GPIO_DOUTTGL31_0_DIO9_TOGGLE 0x00000200U 3967 #define GPIO_DOUTTGL31_0_DIO9_NOEFF 0x00000000U 3968 3969 // Field: [8] DIO8 3970 // 3971 // Toggles bit DOUT31_0.DIO8 3972 // ENUMs: 3973 // TOGGLE Toggle 3974 // NOEFF No effect 3975 #define GPIO_DOUTTGL31_0_DIO8 0x00000100U 3976 #define GPIO_DOUTTGL31_0_DIO8_M 0x00000100U 3977 #define GPIO_DOUTTGL31_0_DIO8_S 8U 3978 #define GPIO_DOUTTGL31_0_DIO8_TOGGLE 0x00000100U 3979 #define GPIO_DOUTTGL31_0_DIO8_NOEFF 0x00000000U 3980 3981 // Field: [7] DIO7 3982 // 3983 // Toggles bit DOUT31_0.DIO7 3984 // ENUMs: 3985 // TOGGLE Toggle 3986 // NOEFF No effect 3987 #define GPIO_DOUTTGL31_0_DIO7 0x00000080U 3988 #define GPIO_DOUTTGL31_0_DIO7_M 0x00000080U 3989 #define GPIO_DOUTTGL31_0_DIO7_S 7U 3990 #define GPIO_DOUTTGL31_0_DIO7_TOGGLE 0x00000080U 3991 #define GPIO_DOUTTGL31_0_DIO7_NOEFF 0x00000000U 3992 3993 // Field: [6] DIO6 3994 // 3995 // Toggles bit DOUT31_0.DIO6 3996 // ENUMs: 3997 // TOGGLE Toggle 3998 // NOEFF No effect 3999 #define GPIO_DOUTTGL31_0_DIO6 0x00000040U 4000 #define GPIO_DOUTTGL31_0_DIO6_M 0x00000040U 4001 #define GPIO_DOUTTGL31_0_DIO6_S 6U 4002 #define GPIO_DOUTTGL31_0_DIO6_TOGGLE 0x00000040U 4003 #define GPIO_DOUTTGL31_0_DIO6_NOEFF 0x00000000U 4004 4005 // Field: [5] DIO5 4006 // 4007 // Toggles bit DOUT31_0.DIO5 4008 // ENUMs: 4009 // TOGGLE Toggle 4010 // NOEFF No effect 4011 #define GPIO_DOUTTGL31_0_DIO5 0x00000020U 4012 #define GPIO_DOUTTGL31_0_DIO5_M 0x00000020U 4013 #define GPIO_DOUTTGL31_0_DIO5_S 5U 4014 #define GPIO_DOUTTGL31_0_DIO5_TOGGLE 0x00000020U 4015 #define GPIO_DOUTTGL31_0_DIO5_NOEFF 0x00000000U 4016 4017 // Field: [4] DIO4 4018 // 4019 // Toggles bit DOUT31_0.DIO4 4020 // ENUMs: 4021 // TOGGLE Toggle 4022 // NOEFF No effect 4023 #define GPIO_DOUTTGL31_0_DIO4 0x00000010U 4024 #define GPIO_DOUTTGL31_0_DIO4_M 0x00000010U 4025 #define GPIO_DOUTTGL31_0_DIO4_S 4U 4026 #define GPIO_DOUTTGL31_0_DIO4_TOGGLE 0x00000010U 4027 #define GPIO_DOUTTGL31_0_DIO4_NOEFF 0x00000000U 4028 4029 // Field: [3] DIO3 4030 // 4031 // Toggles bit DOUT31_0.DIO3 4032 // ENUMs: 4033 // TOGGLE Toggle 4034 // NOEFF No effect 4035 #define GPIO_DOUTTGL31_0_DIO3 0x00000008U 4036 #define GPIO_DOUTTGL31_0_DIO3_M 0x00000008U 4037 #define GPIO_DOUTTGL31_0_DIO3_S 3U 4038 #define GPIO_DOUTTGL31_0_DIO3_TOGGLE 0x00000008U 4039 #define GPIO_DOUTTGL31_0_DIO3_NOEFF 0x00000000U 4040 4041 // Field: [2] DIO2 4042 // 4043 // Toggles bit DOUT31_0.DIO2 4044 // ENUMs: 4045 // TOGGLE Toggle 4046 // NOEFF No effect 4047 #define GPIO_DOUTTGL31_0_DIO2 0x00000004U 4048 #define GPIO_DOUTTGL31_0_DIO2_M 0x00000004U 4049 #define GPIO_DOUTTGL31_0_DIO2_S 2U 4050 #define GPIO_DOUTTGL31_0_DIO2_TOGGLE 0x00000004U 4051 #define GPIO_DOUTTGL31_0_DIO2_NOEFF 0x00000000U 4052 4053 // Field: [1] DIO1 4054 // 4055 // Toggles bit DOUT31_0.DIO1 4056 // ENUMs: 4057 // TOGGLE Toggle 4058 // NOEFF No effect 4059 #define GPIO_DOUTTGL31_0_DIO1 0x00000002U 4060 #define GPIO_DOUTTGL31_0_DIO1_M 0x00000002U 4061 #define GPIO_DOUTTGL31_0_DIO1_S 1U 4062 #define GPIO_DOUTTGL31_0_DIO1_TOGGLE 0x00000002U 4063 #define GPIO_DOUTTGL31_0_DIO1_NOEFF 0x00000000U 4064 4065 // Field: [0] DIO0 4066 // 4067 // Toggles bit DOUT31_0.DIO0 4068 // ENUMs: 4069 // TOGGLE Toggle 4070 // NOEFF No effect 4071 #define GPIO_DOUTTGL31_0_DIO0 0x00000001U 4072 #define GPIO_DOUTTGL31_0_DIO0_M 0x00000001U 4073 #define GPIO_DOUTTGL31_0_DIO0_S 0U 4074 #define GPIO_DOUTTGL31_0_DIO0_TOGGLE 0x00000001U 4075 #define GPIO_DOUTTGL31_0_DIO0_NOEFF 0x00000000U 4076 4077 //***************************************************************************** 4078 // 4079 // Register: GPIO_O_DOUTTGL3_0 4080 // 4081 //***************************************************************************** 4082 // Field: [24] DIO3 4083 // 4084 // Toggles bit DOUT31_0.DIO3 4085 // ENUMs: 4086 // TOGGLE Toggle 4087 // NOEFF No effect 4088 #define GPIO_DOUTTGL3_0_DIO3 0x01000000U 4089 #define GPIO_DOUTTGL3_0_DIO3_M 0x01000000U 4090 #define GPIO_DOUTTGL3_0_DIO3_S 24U 4091 #define GPIO_DOUTTGL3_0_DIO3_TOGGLE 0x01000000U 4092 #define GPIO_DOUTTGL3_0_DIO3_NOEFF 0x00000000U 4093 4094 // Field: [16] DIO2 4095 // 4096 // Toggles bit DOUT31_0.DIO2 4097 // ENUMs: 4098 // TOGGLE Toggle 4099 // NOEFF No effect 4100 #define GPIO_DOUTTGL3_0_DIO2 0x00010000U 4101 #define GPIO_DOUTTGL3_0_DIO2_M 0x00010000U 4102 #define GPIO_DOUTTGL3_0_DIO2_S 16U 4103 #define GPIO_DOUTTGL3_0_DIO2_TOGGLE 0x00010000U 4104 #define GPIO_DOUTTGL3_0_DIO2_NOEFF 0x00000000U 4105 4106 // Field: [8] DIO1 4107 // 4108 // Toggles bit DOUT31_0.DIO1 4109 // ENUMs: 4110 // TOGGLE Toggle 4111 // NOEFF No effect 4112 #define GPIO_DOUTTGL3_0_DIO1 0x00000100U 4113 #define GPIO_DOUTTGL3_0_DIO1_M 0x00000100U 4114 #define GPIO_DOUTTGL3_0_DIO1_S 8U 4115 #define GPIO_DOUTTGL3_0_DIO1_TOGGLE 0x00000100U 4116 #define GPIO_DOUTTGL3_0_DIO1_NOEFF 0x00000000U 4117 4118 // Field: [0] DIO0 4119 // 4120 // Toggles bit DOUT31_0.DIO0 4121 // ENUMs: 4122 // TOGGLE Toggle 4123 // NOEFF No effect 4124 #define GPIO_DOUTTGL3_0_DIO0 0x00000001U 4125 #define GPIO_DOUTTGL3_0_DIO0_M 0x00000001U 4126 #define GPIO_DOUTTGL3_0_DIO0_S 0U 4127 #define GPIO_DOUTTGL3_0_DIO0_TOGGLE 0x00000001U 4128 #define GPIO_DOUTTGL3_0_DIO0_NOEFF 0x00000000U 4129 4130 //***************************************************************************** 4131 // 4132 // Register: GPIO_O_DOUTTGL7_4 4133 // 4134 //***************************************************************************** 4135 // Field: [24] DIO7 4136 // 4137 // Toggles bit DOUT31_0.DIO7 4138 // ENUMs: 4139 // TOGGLE Toggle 4140 // NOEFF No effect 4141 #define GPIO_DOUTTGL7_4_DIO7 0x01000000U 4142 #define GPIO_DOUTTGL7_4_DIO7_M 0x01000000U 4143 #define GPIO_DOUTTGL7_4_DIO7_S 24U 4144 #define GPIO_DOUTTGL7_4_DIO7_TOGGLE 0x01000000U 4145 #define GPIO_DOUTTGL7_4_DIO7_NOEFF 0x00000000U 4146 4147 // Field: [16] DIO6 4148 // 4149 // Toggles bit DOUT31_0.DIO6 4150 // ENUMs: 4151 // TOGGLE Toggle 4152 // NOEFF No effect 4153 #define GPIO_DOUTTGL7_4_DIO6 0x00010000U 4154 #define GPIO_DOUTTGL7_4_DIO6_M 0x00010000U 4155 #define GPIO_DOUTTGL7_4_DIO6_S 16U 4156 #define GPIO_DOUTTGL7_4_DIO6_TOGGLE 0x00010000U 4157 #define GPIO_DOUTTGL7_4_DIO6_NOEFF 0x00000000U 4158 4159 // Field: [8] DIO5 4160 // 4161 // Toggles bit DOUT31_0.DIO5 4162 // ENUMs: 4163 // TOGGLE Toggle 4164 // NOEFF No effect 4165 #define GPIO_DOUTTGL7_4_DIO5 0x00000100U 4166 #define GPIO_DOUTTGL7_4_DIO5_M 0x00000100U 4167 #define GPIO_DOUTTGL7_4_DIO5_S 8U 4168 #define GPIO_DOUTTGL7_4_DIO5_TOGGLE 0x00000100U 4169 #define GPIO_DOUTTGL7_4_DIO5_NOEFF 0x00000000U 4170 4171 // Field: [0] DIO4 4172 // 4173 // Toggles bit DOUT31_0.DIO4 4174 // ENUMs: 4175 // TOGGLE Toggle 4176 // NOEFF No effect 4177 #define GPIO_DOUTTGL7_4_DIO4 0x00000001U 4178 #define GPIO_DOUTTGL7_4_DIO4_M 0x00000001U 4179 #define GPIO_DOUTTGL7_4_DIO4_S 0U 4180 #define GPIO_DOUTTGL7_4_DIO4_TOGGLE 0x00000001U 4181 #define GPIO_DOUTTGL7_4_DIO4_NOEFF 0x00000000U 4182 4183 //***************************************************************************** 4184 // 4185 // Register: GPIO_O_DOUTTGL11_8 4186 // 4187 //***************************************************************************** 4188 // Field: [24] DIO11 4189 // 4190 // Toggles bit DOUT31_0.DIO11 4191 // ENUMs: 4192 // TOGGLE Toggle 4193 // NOEFF No effect 4194 #define GPIO_DOUTTGL11_8_DIO11 0x01000000U 4195 #define GPIO_DOUTTGL11_8_DIO11_M 0x01000000U 4196 #define GPIO_DOUTTGL11_8_DIO11_S 24U 4197 #define GPIO_DOUTTGL11_8_DIO11_TOGGLE 0x01000000U 4198 #define GPIO_DOUTTGL11_8_DIO11_NOEFF 0x00000000U 4199 4200 // Field: [16] DIO10 4201 // 4202 // Toggles bit DOUT31_0.DIO10 4203 // ENUMs: 4204 // TOGGLE Toggle 4205 // NOEFF No effect 4206 #define GPIO_DOUTTGL11_8_DIO10 0x00010000U 4207 #define GPIO_DOUTTGL11_8_DIO10_M 0x00010000U 4208 #define GPIO_DOUTTGL11_8_DIO10_S 16U 4209 #define GPIO_DOUTTGL11_8_DIO10_TOGGLE 0x00010000U 4210 #define GPIO_DOUTTGL11_8_DIO10_NOEFF 0x00000000U 4211 4212 // Field: [8] DIO9 4213 // 4214 // Toggles bit DOUT31_0.DIO9 4215 // ENUMs: 4216 // TOGGLE Toggle 4217 // NOEFF No effect 4218 #define GPIO_DOUTTGL11_8_DIO9 0x00000100U 4219 #define GPIO_DOUTTGL11_8_DIO9_M 0x00000100U 4220 #define GPIO_DOUTTGL11_8_DIO9_S 8U 4221 #define GPIO_DOUTTGL11_8_DIO9_TOGGLE 0x00000100U 4222 #define GPIO_DOUTTGL11_8_DIO9_NOEFF 0x00000000U 4223 4224 // Field: [0] DIO8 4225 // 4226 // Toggles bit DOUT31_0.DIO8 4227 // ENUMs: 4228 // TOGGLE Toggle 4229 // NOEFF No effect 4230 #define GPIO_DOUTTGL11_8_DIO8 0x00000001U 4231 #define GPIO_DOUTTGL11_8_DIO8_M 0x00000001U 4232 #define GPIO_DOUTTGL11_8_DIO8_S 0U 4233 #define GPIO_DOUTTGL11_8_DIO8_TOGGLE 0x00000001U 4234 #define GPIO_DOUTTGL11_8_DIO8_NOEFF 0x00000000U 4235 4236 //***************************************************************************** 4237 // 4238 // Register: GPIO_O_DOUTTGL15_12 4239 // 4240 //***************************************************************************** 4241 // Field: [24] DIO15 4242 // 4243 // Toggles bit DOUT31_0.DIO15 4244 // ENUMs: 4245 // TOGGLE Toggle 4246 // NOEFF No effect 4247 #define GPIO_DOUTTGL15_12_DIO15 0x01000000U 4248 #define GPIO_DOUTTGL15_12_DIO15_M 0x01000000U 4249 #define GPIO_DOUTTGL15_12_DIO15_S 24U 4250 #define GPIO_DOUTTGL15_12_DIO15_TOGGLE 0x01000000U 4251 #define GPIO_DOUTTGL15_12_DIO15_NOEFF 0x00000000U 4252 4253 // Field: [16] DIO14 4254 // 4255 // Toggles bit DOUT31_0.DIO14 4256 // ENUMs: 4257 // TOGGLE Toggle 4258 // NOEFF No effect 4259 #define GPIO_DOUTTGL15_12_DIO14 0x00010000U 4260 #define GPIO_DOUTTGL15_12_DIO14_M 0x00010000U 4261 #define GPIO_DOUTTGL15_12_DIO14_S 16U 4262 #define GPIO_DOUTTGL15_12_DIO14_TOGGLE 0x00010000U 4263 #define GPIO_DOUTTGL15_12_DIO14_NOEFF 0x00000000U 4264 4265 // Field: [8] DIO13 4266 // 4267 // Toggles bit DOUT31_0.DIO13 4268 // ENUMs: 4269 // TOGGLE Toggle 4270 // NOEFF No effect 4271 #define GPIO_DOUTTGL15_12_DIO13 0x00000100U 4272 #define GPIO_DOUTTGL15_12_DIO13_M 0x00000100U 4273 #define GPIO_DOUTTGL15_12_DIO13_S 8U 4274 #define GPIO_DOUTTGL15_12_DIO13_TOGGLE 0x00000100U 4275 #define GPIO_DOUTTGL15_12_DIO13_NOEFF 0x00000000U 4276 4277 // Field: [0] DIO12 4278 // 4279 // Toggles bit DOUT31_0.DIO12 4280 // ENUMs: 4281 // TOGGLE Toggle 4282 // NOEFF No effect 4283 #define GPIO_DOUTTGL15_12_DIO12 0x00000001U 4284 #define GPIO_DOUTTGL15_12_DIO12_M 0x00000001U 4285 #define GPIO_DOUTTGL15_12_DIO12_S 0U 4286 #define GPIO_DOUTTGL15_12_DIO12_TOGGLE 0x00000001U 4287 #define GPIO_DOUTTGL15_12_DIO12_NOEFF 0x00000000U 4288 4289 //***************************************************************************** 4290 // 4291 // Register: GPIO_O_DOUTTGL19_16 4292 // 4293 //***************************************************************************** 4294 // Field: [24] DIO19 4295 // 4296 // Toggles bit DOUT31_0.DIO19 4297 // ENUMs: 4298 // TOGGLE Toggle 4299 // NOEFF No effect 4300 #define GPIO_DOUTTGL19_16_DIO19 0x01000000U 4301 #define GPIO_DOUTTGL19_16_DIO19_M 0x01000000U 4302 #define GPIO_DOUTTGL19_16_DIO19_S 24U 4303 #define GPIO_DOUTTGL19_16_DIO19_TOGGLE 0x01000000U 4304 #define GPIO_DOUTTGL19_16_DIO19_NOEFF 0x00000000U 4305 4306 // Field: [16] DIO18 4307 // 4308 // Toggles bit DOUT31_0.DIO18 4309 // ENUMs: 4310 // TOGGLE Toggle 4311 // NOEFF No effect 4312 #define GPIO_DOUTTGL19_16_DIO18 0x00010000U 4313 #define GPIO_DOUTTGL19_16_DIO18_M 0x00010000U 4314 #define GPIO_DOUTTGL19_16_DIO18_S 16U 4315 #define GPIO_DOUTTGL19_16_DIO18_TOGGLE 0x00010000U 4316 #define GPIO_DOUTTGL19_16_DIO18_NOEFF 0x00000000U 4317 4318 // Field: [8] DIO17 4319 // 4320 // Toggles bit DOUT31_0.DIO17 4321 // ENUMs: 4322 // TOGGLE Toggle 4323 // NOEFF No effect 4324 #define GPIO_DOUTTGL19_16_DIO17 0x00000100U 4325 #define GPIO_DOUTTGL19_16_DIO17_M 0x00000100U 4326 #define GPIO_DOUTTGL19_16_DIO17_S 8U 4327 #define GPIO_DOUTTGL19_16_DIO17_TOGGLE 0x00000100U 4328 #define GPIO_DOUTTGL19_16_DIO17_NOEFF 0x00000000U 4329 4330 // Field: [0] DIO16 4331 // 4332 // Toggles bit DOUT31_0.DIO16 4333 // ENUMs: 4334 // TOGGLE Toggle 4335 // NOEFF No effect 4336 #define GPIO_DOUTTGL19_16_DIO16 0x00000001U 4337 #define GPIO_DOUTTGL19_16_DIO16_M 0x00000001U 4338 #define GPIO_DOUTTGL19_16_DIO16_S 0U 4339 #define GPIO_DOUTTGL19_16_DIO16_TOGGLE 0x00000001U 4340 #define GPIO_DOUTTGL19_16_DIO16_NOEFF 0x00000000U 4341 4342 //***************************************************************************** 4343 // 4344 // Register: GPIO_O_DOUTTGL23_20 4345 // 4346 //***************************************************************************** 4347 // Field: [24] DIO23 4348 // 4349 // Toggles bit DOUT31_0.DIO23 4350 // ENUMs: 4351 // TOGGLE Toggle 4352 // NOEFF No effect 4353 #define GPIO_DOUTTGL23_20_DIO23 0x01000000U 4354 #define GPIO_DOUTTGL23_20_DIO23_M 0x01000000U 4355 #define GPIO_DOUTTGL23_20_DIO23_S 24U 4356 #define GPIO_DOUTTGL23_20_DIO23_TOGGLE 0x01000000U 4357 #define GPIO_DOUTTGL23_20_DIO23_NOEFF 0x00000000U 4358 4359 // Field: [16] DIO22 4360 // 4361 // Toggles bit DOUT31_0.DIO22 4362 // ENUMs: 4363 // TOGGLE Toggle 4364 // NOEFF No effect 4365 #define GPIO_DOUTTGL23_20_DIO22 0x00010000U 4366 #define GPIO_DOUTTGL23_20_DIO22_M 0x00010000U 4367 #define GPIO_DOUTTGL23_20_DIO22_S 16U 4368 #define GPIO_DOUTTGL23_20_DIO22_TOGGLE 0x00010000U 4369 #define GPIO_DOUTTGL23_20_DIO22_NOEFF 0x00000000U 4370 4371 // Field: [8] DIO21 4372 // 4373 // Toggles bit DOUT31_0.DIO21 4374 // ENUMs: 4375 // TOGGLE Toggle 4376 // NOEFF No effect 4377 #define GPIO_DOUTTGL23_20_DIO21 0x00000100U 4378 #define GPIO_DOUTTGL23_20_DIO21_M 0x00000100U 4379 #define GPIO_DOUTTGL23_20_DIO21_S 8U 4380 #define GPIO_DOUTTGL23_20_DIO21_TOGGLE 0x00000100U 4381 #define GPIO_DOUTTGL23_20_DIO21_NOEFF 0x00000000U 4382 4383 // Field: [0] DIO20 4384 // 4385 // Toggles bit DOUT31_0.DIO20 4386 // ENUMs: 4387 // TOGGLE Toggle 4388 // NOEFF No effect 4389 #define GPIO_DOUTTGL23_20_DIO20 0x00000001U 4390 #define GPIO_DOUTTGL23_20_DIO20_M 0x00000001U 4391 #define GPIO_DOUTTGL23_20_DIO20_S 0U 4392 #define GPIO_DOUTTGL23_20_DIO20_TOGGLE 0x00000001U 4393 #define GPIO_DOUTTGL23_20_DIO20_NOEFF 0x00000000U 4394 4395 //***************************************************************************** 4396 // 4397 // Register: GPIO_O_DOUTTGL27_24 4398 // 4399 //***************************************************************************** 4400 // Field: [8] DIO25 4401 // 4402 // Toggles bit DOUT31_0.DIO25 4403 // ENUMs: 4404 // TOGGLE Toggle 4405 // NOEFF No effect 4406 #define GPIO_DOUTTGL27_24_DIO25 0x00000100U 4407 #define GPIO_DOUTTGL27_24_DIO25_M 0x00000100U 4408 #define GPIO_DOUTTGL27_24_DIO25_S 8U 4409 #define GPIO_DOUTTGL27_24_DIO25_TOGGLE 0x00000100U 4410 #define GPIO_DOUTTGL27_24_DIO25_NOEFF 0x00000000U 4411 4412 // Field: [0] DIO24 4413 // 4414 // Toggles bit DOUT31_0.DIO24 4415 // ENUMs: 4416 // TOGGLE Toggle 4417 // NOEFF No effect 4418 #define GPIO_DOUTTGL27_24_DIO24 0x00000001U 4419 #define GPIO_DOUTTGL27_24_DIO24_M 0x00000001U 4420 #define GPIO_DOUTTGL27_24_DIO24_S 0U 4421 #define GPIO_DOUTTGL27_24_DIO24_TOGGLE 0x00000001U 4422 #define GPIO_DOUTTGL27_24_DIO24_NOEFF 0x00000000U 4423 4424 //***************************************************************************** 4425 // 4426 // Register: GPIO_O_DOE3_0 4427 // 4428 //***************************************************************************** 4429 // Field: [24] DIO3 4430 // 4431 // Data output enable for DIO3 4432 // ENUMs: 4433 // EN Output enabled 4434 // DIS Output disabled 4435 #define GPIO_DOE3_0_DIO3 0x01000000U 4436 #define GPIO_DOE3_0_DIO3_M 0x01000000U 4437 #define GPIO_DOE3_0_DIO3_S 24U 4438 #define GPIO_DOE3_0_DIO3_EN 0x01000000U 4439 #define GPIO_DOE3_0_DIO3_DIS 0x00000000U 4440 4441 // Field: [16] DIO2 4442 // 4443 // Data output enable for DIO2 4444 // ENUMs: 4445 // EN Output enabled 4446 // DIS Output disabled 4447 #define GPIO_DOE3_0_DIO2 0x00010000U 4448 #define GPIO_DOE3_0_DIO2_M 0x00010000U 4449 #define GPIO_DOE3_0_DIO2_S 16U 4450 #define GPIO_DOE3_0_DIO2_EN 0x00010000U 4451 #define GPIO_DOE3_0_DIO2_DIS 0x00000000U 4452 4453 // Field: [8] DIO1 4454 // 4455 // Data output enable for DIO1 4456 // ENUMs: 4457 // EN Output enabled 4458 // DIS Output disabled 4459 #define GPIO_DOE3_0_DIO1 0x00000100U 4460 #define GPIO_DOE3_0_DIO1_M 0x00000100U 4461 #define GPIO_DOE3_0_DIO1_S 8U 4462 #define GPIO_DOE3_0_DIO1_EN 0x00000100U 4463 #define GPIO_DOE3_0_DIO1_DIS 0x00000000U 4464 4465 // Field: [0] DIO0 4466 // 4467 // Data output enable for DIO0 4468 // ENUMs: 4469 // EN Output enabled 4470 // DIS Output disabled 4471 #define GPIO_DOE3_0_DIO0 0x00000001U 4472 #define GPIO_DOE3_0_DIO0_M 0x00000001U 4473 #define GPIO_DOE3_0_DIO0_S 0U 4474 #define GPIO_DOE3_0_DIO0_EN 0x00000001U 4475 #define GPIO_DOE3_0_DIO0_DIS 0x00000000U 4476 4477 //***************************************************************************** 4478 // 4479 // Register: GPIO_O_DOE7_4 4480 // 4481 //***************************************************************************** 4482 // Field: [24] DIO7 4483 // 4484 // Data output enable for DIO7 4485 // ENUMs: 4486 // EN Output enabled 4487 // DIS Output disabled 4488 #define GPIO_DOE7_4_DIO7 0x01000000U 4489 #define GPIO_DOE7_4_DIO7_M 0x01000000U 4490 #define GPIO_DOE7_4_DIO7_S 24U 4491 #define GPIO_DOE7_4_DIO7_EN 0x01000000U 4492 #define GPIO_DOE7_4_DIO7_DIS 0x00000000U 4493 4494 // Field: [16] DIO6 4495 // 4496 // Data output enable for DIO6 4497 // ENUMs: 4498 // EN Output enabled 4499 // DIS Output disabled 4500 #define GPIO_DOE7_4_DIO6 0x00010000U 4501 #define GPIO_DOE7_4_DIO6_M 0x00010000U 4502 #define GPIO_DOE7_4_DIO6_S 16U 4503 #define GPIO_DOE7_4_DIO6_EN 0x00010000U 4504 #define GPIO_DOE7_4_DIO6_DIS 0x00000000U 4505 4506 // Field: [8] DIO5 4507 // 4508 // Data output enable for DIO5 4509 // ENUMs: 4510 // EN Output enabled 4511 // DIS Output disabled 4512 #define GPIO_DOE7_4_DIO5 0x00000100U 4513 #define GPIO_DOE7_4_DIO5_M 0x00000100U 4514 #define GPIO_DOE7_4_DIO5_S 8U 4515 #define GPIO_DOE7_4_DIO5_EN 0x00000100U 4516 #define GPIO_DOE7_4_DIO5_DIS 0x00000000U 4517 4518 // Field: [0] DIO4 4519 // 4520 // Data output enable for DIO4 4521 // ENUMs: 4522 // EN Output enabled 4523 // DIS Output disabled 4524 #define GPIO_DOE7_4_DIO4 0x00000001U 4525 #define GPIO_DOE7_4_DIO4_M 0x00000001U 4526 #define GPIO_DOE7_4_DIO4_S 0U 4527 #define GPIO_DOE7_4_DIO4_EN 0x00000001U 4528 #define GPIO_DOE7_4_DIO4_DIS 0x00000000U 4529 4530 //***************************************************************************** 4531 // 4532 // Register: GPIO_O_DOE11_8 4533 // 4534 //***************************************************************************** 4535 // Field: [24] DIO11 4536 // 4537 // Data output enable for DIO11 4538 // ENUMs: 4539 // EN Output enabled 4540 // DIS Output disabled 4541 #define GPIO_DOE11_8_DIO11 0x01000000U 4542 #define GPIO_DOE11_8_DIO11_M 0x01000000U 4543 #define GPIO_DOE11_8_DIO11_S 24U 4544 #define GPIO_DOE11_8_DIO11_EN 0x01000000U 4545 #define GPIO_DOE11_8_DIO11_DIS 0x00000000U 4546 4547 // Field: [16] DIO10 4548 // 4549 // Data output enable for DIO10 4550 // ENUMs: 4551 // EN Output enabled 4552 // DIS Output disabled 4553 #define GPIO_DOE11_8_DIO10 0x00010000U 4554 #define GPIO_DOE11_8_DIO10_M 0x00010000U 4555 #define GPIO_DOE11_8_DIO10_S 16U 4556 #define GPIO_DOE11_8_DIO10_EN 0x00010000U 4557 #define GPIO_DOE11_8_DIO10_DIS 0x00000000U 4558 4559 // Field: [8] DIO9 4560 // 4561 // Data output enable for DIO9 4562 // ENUMs: 4563 // EN Output enabled 4564 // DIS Output disabled 4565 #define GPIO_DOE11_8_DIO9 0x00000100U 4566 #define GPIO_DOE11_8_DIO9_M 0x00000100U 4567 #define GPIO_DOE11_8_DIO9_S 8U 4568 #define GPIO_DOE11_8_DIO9_EN 0x00000100U 4569 #define GPIO_DOE11_8_DIO9_DIS 0x00000000U 4570 4571 // Field: [0] DIO8 4572 // 4573 // Data output enable for DIO8 4574 // ENUMs: 4575 // EN Output enabled 4576 // DIS Output disabled 4577 #define GPIO_DOE11_8_DIO8 0x00000001U 4578 #define GPIO_DOE11_8_DIO8_M 0x00000001U 4579 #define GPIO_DOE11_8_DIO8_S 0U 4580 #define GPIO_DOE11_8_DIO8_EN 0x00000001U 4581 #define GPIO_DOE11_8_DIO8_DIS 0x00000000U 4582 4583 //***************************************************************************** 4584 // 4585 // Register: GPIO_O_DOE15_12 4586 // 4587 //***************************************************************************** 4588 // Field: [24] DIO15 4589 // 4590 // Data output enable for DIO15 4591 // ENUMs: 4592 // EN Output enabled 4593 // DIS Output disabled 4594 #define GPIO_DOE15_12_DIO15 0x01000000U 4595 #define GPIO_DOE15_12_DIO15_M 0x01000000U 4596 #define GPIO_DOE15_12_DIO15_S 24U 4597 #define GPIO_DOE15_12_DIO15_EN 0x01000000U 4598 #define GPIO_DOE15_12_DIO15_DIS 0x00000000U 4599 4600 // Field: [16] DIO14 4601 // 4602 // Data output enable for DIO14 4603 // ENUMs: 4604 // EN Output enabled 4605 // DIS Output disabled 4606 #define GPIO_DOE15_12_DIO14 0x00010000U 4607 #define GPIO_DOE15_12_DIO14_M 0x00010000U 4608 #define GPIO_DOE15_12_DIO14_S 16U 4609 #define GPIO_DOE15_12_DIO14_EN 0x00010000U 4610 #define GPIO_DOE15_12_DIO14_DIS 0x00000000U 4611 4612 // Field: [8] DIO13 4613 // 4614 // Data output enable for DIO13 4615 // ENUMs: 4616 // EN Output enabled 4617 // DIS Output disabled 4618 #define GPIO_DOE15_12_DIO13 0x00000100U 4619 #define GPIO_DOE15_12_DIO13_M 0x00000100U 4620 #define GPIO_DOE15_12_DIO13_S 8U 4621 #define GPIO_DOE15_12_DIO13_EN 0x00000100U 4622 #define GPIO_DOE15_12_DIO13_DIS 0x00000000U 4623 4624 // Field: [0] DIO12 4625 // 4626 // Data output enable for DIO12 4627 // ENUMs: 4628 // EN Output enabled 4629 // DIS Output disabled 4630 #define GPIO_DOE15_12_DIO12 0x00000001U 4631 #define GPIO_DOE15_12_DIO12_M 0x00000001U 4632 #define GPIO_DOE15_12_DIO12_S 0U 4633 #define GPIO_DOE15_12_DIO12_EN 0x00000001U 4634 #define GPIO_DOE15_12_DIO12_DIS 0x00000000U 4635 4636 //***************************************************************************** 4637 // 4638 // Register: GPIO_O_DOE19_16 4639 // 4640 //***************************************************************************** 4641 // Field: [24] DIO19 4642 // 4643 // Data output enable for DIO19 4644 // ENUMs: 4645 // EN Output enabled 4646 // DIS Output disabled 4647 #define GPIO_DOE19_16_DIO19 0x01000000U 4648 #define GPIO_DOE19_16_DIO19_M 0x01000000U 4649 #define GPIO_DOE19_16_DIO19_S 24U 4650 #define GPIO_DOE19_16_DIO19_EN 0x01000000U 4651 #define GPIO_DOE19_16_DIO19_DIS 0x00000000U 4652 4653 // Field: [16] DIO18 4654 // 4655 // Data output enable for DIO18 4656 // ENUMs: 4657 // EN Output enabled 4658 // DIS Output disabled 4659 #define GPIO_DOE19_16_DIO18 0x00010000U 4660 #define GPIO_DOE19_16_DIO18_M 0x00010000U 4661 #define GPIO_DOE19_16_DIO18_S 16U 4662 #define GPIO_DOE19_16_DIO18_EN 0x00010000U 4663 #define GPIO_DOE19_16_DIO18_DIS 0x00000000U 4664 4665 // Field: [8] DIO17 4666 // 4667 // Data output enable for DIO17 4668 // ENUMs: 4669 // EN Output enabled 4670 // DIS Output disabled 4671 #define GPIO_DOE19_16_DIO17 0x00000100U 4672 #define GPIO_DOE19_16_DIO17_M 0x00000100U 4673 #define GPIO_DOE19_16_DIO17_S 8U 4674 #define GPIO_DOE19_16_DIO17_EN 0x00000100U 4675 #define GPIO_DOE19_16_DIO17_DIS 0x00000000U 4676 4677 // Field: [0] DIO16 4678 // 4679 // Data output enable for DIO16 4680 // ENUMs: 4681 // EN Output enabled 4682 // DIS Output disabled 4683 #define GPIO_DOE19_16_DIO16 0x00000001U 4684 #define GPIO_DOE19_16_DIO16_M 0x00000001U 4685 #define GPIO_DOE19_16_DIO16_S 0U 4686 #define GPIO_DOE19_16_DIO16_EN 0x00000001U 4687 #define GPIO_DOE19_16_DIO16_DIS 0x00000000U 4688 4689 //***************************************************************************** 4690 // 4691 // Register: GPIO_O_DOE23_20 4692 // 4693 //***************************************************************************** 4694 // Field: [24] DIO23 4695 // 4696 // Data output enable for DIO23 4697 // ENUMs: 4698 // EN Output enabled 4699 // DIS Output disabled 4700 #define GPIO_DOE23_20_DIO23 0x01000000U 4701 #define GPIO_DOE23_20_DIO23_M 0x01000000U 4702 #define GPIO_DOE23_20_DIO23_S 24U 4703 #define GPIO_DOE23_20_DIO23_EN 0x01000000U 4704 #define GPIO_DOE23_20_DIO23_DIS 0x00000000U 4705 4706 // Field: [16] DIO22 4707 // 4708 // Data output enable for DIO22 4709 // ENUMs: 4710 // EN Output enabled 4711 // DIS Output disabled 4712 #define GPIO_DOE23_20_DIO22 0x00010000U 4713 #define GPIO_DOE23_20_DIO22_M 0x00010000U 4714 #define GPIO_DOE23_20_DIO22_S 16U 4715 #define GPIO_DOE23_20_DIO22_EN 0x00010000U 4716 #define GPIO_DOE23_20_DIO22_DIS 0x00000000U 4717 4718 // Field: [8] DIO21 4719 // 4720 // Data output enable for DIO21 4721 // ENUMs: 4722 // EN Output enabled 4723 // DIS Output disabled 4724 #define GPIO_DOE23_20_DIO21 0x00000100U 4725 #define GPIO_DOE23_20_DIO21_M 0x00000100U 4726 #define GPIO_DOE23_20_DIO21_S 8U 4727 #define GPIO_DOE23_20_DIO21_EN 0x00000100U 4728 #define GPIO_DOE23_20_DIO21_DIS 0x00000000U 4729 4730 // Field: [0] DIO20 4731 // 4732 // Data output enable for DIO20 4733 // ENUMs: 4734 // EN Output enabled 4735 // DIS Output disabled 4736 #define GPIO_DOE23_20_DIO20 0x00000001U 4737 #define GPIO_DOE23_20_DIO20_M 0x00000001U 4738 #define GPIO_DOE23_20_DIO20_S 0U 4739 #define GPIO_DOE23_20_DIO20_EN 0x00000001U 4740 #define GPIO_DOE23_20_DIO20_DIS 0x00000000U 4741 4742 //***************************************************************************** 4743 // 4744 // Register: GPIO_O_DOE27_24 4745 // 4746 //***************************************************************************** 4747 // Field: [8] DIO25 4748 // 4749 // Data output enable for DIO25 4750 // ENUMs: 4751 // EN Output enabled 4752 // DIS Output disabled 4753 #define GPIO_DOE27_24_DIO25 0x00000100U 4754 #define GPIO_DOE27_24_DIO25_M 0x00000100U 4755 #define GPIO_DOE27_24_DIO25_S 8U 4756 #define GPIO_DOE27_24_DIO25_EN 0x00000100U 4757 #define GPIO_DOE27_24_DIO25_DIS 0x00000000U 4758 4759 // Field: [0] DIO24 4760 // 4761 // Data output enable for DIO24 4762 // ENUMs: 4763 // EN Output enabled 4764 // DIS Output disabled 4765 #define GPIO_DOE27_24_DIO24 0x00000001U 4766 #define GPIO_DOE27_24_DIO24_M 0x00000001U 4767 #define GPIO_DOE27_24_DIO24_S 0U 4768 #define GPIO_DOE27_24_DIO24_EN 0x00000001U 4769 #define GPIO_DOE27_24_DIO24_DIS 0x00000000U 4770 4771 //***************************************************************************** 4772 // 4773 // Register: GPIO_O_DOE31_0 4774 // 4775 //***************************************************************************** 4776 // Field: [25] DIO25 4777 // 4778 // Data output enable for DIO25 4779 // ENUMs: 4780 // EN Output enabled 4781 // DIS Output disabled 4782 #define GPIO_DOE31_0_DIO25 0x02000000U 4783 #define GPIO_DOE31_0_DIO25_M 0x02000000U 4784 #define GPIO_DOE31_0_DIO25_S 25U 4785 #define GPIO_DOE31_0_DIO25_EN 0x02000000U 4786 #define GPIO_DOE31_0_DIO25_DIS 0x00000000U 4787 4788 // Field: [24] DIO24 4789 // 4790 // Data output enable for DIO24 4791 // ENUMs: 4792 // EN Output enabled 4793 // DIS Output disabled 4794 #define GPIO_DOE31_0_DIO24 0x01000000U 4795 #define GPIO_DOE31_0_DIO24_M 0x01000000U 4796 #define GPIO_DOE31_0_DIO24_S 24U 4797 #define GPIO_DOE31_0_DIO24_EN 0x01000000U 4798 #define GPIO_DOE31_0_DIO24_DIS 0x00000000U 4799 4800 // Field: [23] DIO23 4801 // 4802 // Data output enable for DIO23 4803 // ENUMs: 4804 // EN Output enabled 4805 // DIS Output disabled 4806 #define GPIO_DOE31_0_DIO23 0x00800000U 4807 #define GPIO_DOE31_0_DIO23_M 0x00800000U 4808 #define GPIO_DOE31_0_DIO23_S 23U 4809 #define GPIO_DOE31_0_DIO23_EN 0x00800000U 4810 #define GPIO_DOE31_0_DIO23_DIS 0x00000000U 4811 4812 // Field: [22] DIO22 4813 // 4814 // Data output enable for DIO22 4815 // ENUMs: 4816 // EN Output enabled 4817 // DIS Output disabled 4818 #define GPIO_DOE31_0_DIO22 0x00400000U 4819 #define GPIO_DOE31_0_DIO22_M 0x00400000U 4820 #define GPIO_DOE31_0_DIO22_S 22U 4821 #define GPIO_DOE31_0_DIO22_EN 0x00400000U 4822 #define GPIO_DOE31_0_DIO22_DIS 0x00000000U 4823 4824 // Field: [21] DIO21 4825 // 4826 // Data output enable for DIO21 4827 // ENUMs: 4828 // EN Output enabled 4829 // DIS Output disabled 4830 #define GPIO_DOE31_0_DIO21 0x00200000U 4831 #define GPIO_DOE31_0_DIO21_M 0x00200000U 4832 #define GPIO_DOE31_0_DIO21_S 21U 4833 #define GPIO_DOE31_0_DIO21_EN 0x00200000U 4834 #define GPIO_DOE31_0_DIO21_DIS 0x00000000U 4835 4836 // Field: [20] DIO20 4837 // 4838 // Data output enable for DIO20 4839 // ENUMs: 4840 // EN Output enabled 4841 // DIS Output disabled 4842 #define GPIO_DOE31_0_DIO20 0x00100000U 4843 #define GPIO_DOE31_0_DIO20_M 0x00100000U 4844 #define GPIO_DOE31_0_DIO20_S 20U 4845 #define GPIO_DOE31_0_DIO20_EN 0x00100000U 4846 #define GPIO_DOE31_0_DIO20_DIS 0x00000000U 4847 4848 // Field: [19] DIO19 4849 // 4850 // Data output enable for DIO19 4851 // ENUMs: 4852 // EN Output enabled 4853 // DIS Output disabled 4854 #define GPIO_DOE31_0_DIO19 0x00080000U 4855 #define GPIO_DOE31_0_DIO19_M 0x00080000U 4856 #define GPIO_DOE31_0_DIO19_S 19U 4857 #define GPIO_DOE31_0_DIO19_EN 0x00080000U 4858 #define GPIO_DOE31_0_DIO19_DIS 0x00000000U 4859 4860 // Field: [18] DIO18 4861 // 4862 // Data output enable for DIO18 4863 // ENUMs: 4864 // EN Output enabled 4865 // DIS Output disabled 4866 #define GPIO_DOE31_0_DIO18 0x00040000U 4867 #define GPIO_DOE31_0_DIO18_M 0x00040000U 4868 #define GPIO_DOE31_0_DIO18_S 18U 4869 #define GPIO_DOE31_0_DIO18_EN 0x00040000U 4870 #define GPIO_DOE31_0_DIO18_DIS 0x00000000U 4871 4872 // Field: [17] DIO17 4873 // 4874 // Data output enable for DIO17 4875 // ENUMs: 4876 // EN Output enabled 4877 // DIS Output disabled 4878 #define GPIO_DOE31_0_DIO17 0x00020000U 4879 #define GPIO_DOE31_0_DIO17_M 0x00020000U 4880 #define GPIO_DOE31_0_DIO17_S 17U 4881 #define GPIO_DOE31_0_DIO17_EN 0x00020000U 4882 #define GPIO_DOE31_0_DIO17_DIS 0x00000000U 4883 4884 // Field: [16] DIO16 4885 // 4886 // Data output enable for DIO16 4887 // ENUMs: 4888 // EN Output enabled 4889 // DIS Output disabled 4890 #define GPIO_DOE31_0_DIO16 0x00010000U 4891 #define GPIO_DOE31_0_DIO16_M 0x00010000U 4892 #define GPIO_DOE31_0_DIO16_S 16U 4893 #define GPIO_DOE31_0_DIO16_EN 0x00010000U 4894 #define GPIO_DOE31_0_DIO16_DIS 0x00000000U 4895 4896 // Field: [15] DIO15 4897 // 4898 // Data output enable for DIO15 4899 // ENUMs: 4900 // EN Output enabled 4901 // DIS Output disabled 4902 #define GPIO_DOE31_0_DIO15 0x00008000U 4903 #define GPIO_DOE31_0_DIO15_M 0x00008000U 4904 #define GPIO_DOE31_0_DIO15_S 15U 4905 #define GPIO_DOE31_0_DIO15_EN 0x00008000U 4906 #define GPIO_DOE31_0_DIO15_DIS 0x00000000U 4907 4908 // Field: [14] DIO14 4909 // 4910 // Data output enable for DIO14 4911 // ENUMs: 4912 // EN Output enabled 4913 // DIS Output disabled 4914 #define GPIO_DOE31_0_DIO14 0x00004000U 4915 #define GPIO_DOE31_0_DIO14_M 0x00004000U 4916 #define GPIO_DOE31_0_DIO14_S 14U 4917 #define GPIO_DOE31_0_DIO14_EN 0x00004000U 4918 #define GPIO_DOE31_0_DIO14_DIS 0x00000000U 4919 4920 // Field: [13] DIO13 4921 // 4922 // Data output enable for DIO13 4923 // ENUMs: 4924 // EN Output enabled 4925 // DIS Output disabled 4926 #define GPIO_DOE31_0_DIO13 0x00002000U 4927 #define GPIO_DOE31_0_DIO13_M 0x00002000U 4928 #define GPIO_DOE31_0_DIO13_S 13U 4929 #define GPIO_DOE31_0_DIO13_EN 0x00002000U 4930 #define GPIO_DOE31_0_DIO13_DIS 0x00000000U 4931 4932 // Field: [12] DIO12 4933 // 4934 // Data output enable for DIO12 4935 // ENUMs: 4936 // EN Output enabled 4937 // DIS Output disabled 4938 #define GPIO_DOE31_0_DIO12 0x00001000U 4939 #define GPIO_DOE31_0_DIO12_M 0x00001000U 4940 #define GPIO_DOE31_0_DIO12_S 12U 4941 #define GPIO_DOE31_0_DIO12_EN 0x00001000U 4942 #define GPIO_DOE31_0_DIO12_DIS 0x00000000U 4943 4944 // Field: [11] DIO11 4945 // 4946 // Data output enable for DIO11 4947 // ENUMs: 4948 // EN Output enabled 4949 // DIS Output disabled 4950 #define GPIO_DOE31_0_DIO11 0x00000800U 4951 #define GPIO_DOE31_0_DIO11_M 0x00000800U 4952 #define GPIO_DOE31_0_DIO11_S 11U 4953 #define GPIO_DOE31_0_DIO11_EN 0x00000800U 4954 #define GPIO_DOE31_0_DIO11_DIS 0x00000000U 4955 4956 // Field: [10] DIO10 4957 // 4958 // Data output enable for DIO10 4959 // ENUMs: 4960 // EN Output enabled 4961 // DIS Output disabled 4962 #define GPIO_DOE31_0_DIO10 0x00000400U 4963 #define GPIO_DOE31_0_DIO10_M 0x00000400U 4964 #define GPIO_DOE31_0_DIO10_S 10U 4965 #define GPIO_DOE31_0_DIO10_EN 0x00000400U 4966 #define GPIO_DOE31_0_DIO10_DIS 0x00000000U 4967 4968 // Field: [9] DIO9 4969 // 4970 // Data output enable for DIO9 4971 // ENUMs: 4972 // EN Output enabled 4973 // DIS Output disabled 4974 #define GPIO_DOE31_0_DIO9 0x00000200U 4975 #define GPIO_DOE31_0_DIO9_M 0x00000200U 4976 #define GPIO_DOE31_0_DIO9_S 9U 4977 #define GPIO_DOE31_0_DIO9_EN 0x00000200U 4978 #define GPIO_DOE31_0_DIO9_DIS 0x00000000U 4979 4980 // Field: [8] DIO8 4981 // 4982 // Data output enable for DIO8 4983 // ENUMs: 4984 // EN Output enabled 4985 // DIS Output disabled 4986 #define GPIO_DOE31_0_DIO8 0x00000100U 4987 #define GPIO_DOE31_0_DIO8_M 0x00000100U 4988 #define GPIO_DOE31_0_DIO8_S 8U 4989 #define GPIO_DOE31_0_DIO8_EN 0x00000100U 4990 #define GPIO_DOE31_0_DIO8_DIS 0x00000000U 4991 4992 // Field: [7] DIO7 4993 // 4994 // Data output enable for DIO7 4995 // ENUMs: 4996 // EN Output enabled 4997 // DIS Output disabled 4998 #define GPIO_DOE31_0_DIO7 0x00000080U 4999 #define GPIO_DOE31_0_DIO7_M 0x00000080U 5000 #define GPIO_DOE31_0_DIO7_S 7U 5001 #define GPIO_DOE31_0_DIO7_EN 0x00000080U 5002 #define GPIO_DOE31_0_DIO7_DIS 0x00000000U 5003 5004 // Field: [6] DIO6 5005 // 5006 // Data output enable for DIO6 5007 // ENUMs: 5008 // EN Output enabled 5009 // DIS Output disabled 5010 #define GPIO_DOE31_0_DIO6 0x00000040U 5011 #define GPIO_DOE31_0_DIO6_M 0x00000040U 5012 #define GPIO_DOE31_0_DIO6_S 6U 5013 #define GPIO_DOE31_0_DIO6_EN 0x00000040U 5014 #define GPIO_DOE31_0_DIO6_DIS 0x00000000U 5015 5016 // Field: [5] DIO5 5017 // 5018 // Data output enable for DIO5 5019 // ENUMs: 5020 // EN Output enabled 5021 // DIS Output disabled 5022 #define GPIO_DOE31_0_DIO5 0x00000020U 5023 #define GPIO_DOE31_0_DIO5_M 0x00000020U 5024 #define GPIO_DOE31_0_DIO5_S 5U 5025 #define GPIO_DOE31_0_DIO5_EN 0x00000020U 5026 #define GPIO_DOE31_0_DIO5_DIS 0x00000000U 5027 5028 // Field: [4] DIO4 5029 // 5030 // Data output enable for DIO4 5031 // ENUMs: 5032 // EN Output enabled 5033 // DIS Output disabled 5034 #define GPIO_DOE31_0_DIO4 0x00000010U 5035 #define GPIO_DOE31_0_DIO4_M 0x00000010U 5036 #define GPIO_DOE31_0_DIO4_S 4U 5037 #define GPIO_DOE31_0_DIO4_EN 0x00000010U 5038 #define GPIO_DOE31_0_DIO4_DIS 0x00000000U 5039 5040 // Field: [3] DIO3 5041 // 5042 // Data output enable for DIO3 5043 // ENUMs: 5044 // EN Output enabled 5045 // DIS Output disabled 5046 #define GPIO_DOE31_0_DIO3 0x00000008U 5047 #define GPIO_DOE31_0_DIO3_M 0x00000008U 5048 #define GPIO_DOE31_0_DIO3_S 3U 5049 #define GPIO_DOE31_0_DIO3_EN 0x00000008U 5050 #define GPIO_DOE31_0_DIO3_DIS 0x00000000U 5051 5052 // Field: [2] DIO2 5053 // 5054 // Data output enable for DIO2 5055 // ENUMs: 5056 // EN Output enabled 5057 // DIS Output disabled 5058 #define GPIO_DOE31_0_DIO2 0x00000004U 5059 #define GPIO_DOE31_0_DIO2_M 0x00000004U 5060 #define GPIO_DOE31_0_DIO2_S 2U 5061 #define GPIO_DOE31_0_DIO2_EN 0x00000004U 5062 #define GPIO_DOE31_0_DIO2_DIS 0x00000000U 5063 5064 // Field: [1] DIO1 5065 // 5066 // Data output enable for DIO1 5067 // ENUMs: 5068 // EN Output enabled 5069 // DIS Output disabled 5070 #define GPIO_DOE31_0_DIO1 0x00000002U 5071 #define GPIO_DOE31_0_DIO1_M 0x00000002U 5072 #define GPIO_DOE31_0_DIO1_S 1U 5073 #define GPIO_DOE31_0_DIO1_EN 0x00000002U 5074 #define GPIO_DOE31_0_DIO1_DIS 0x00000000U 5075 5076 // Field: [0] DIO0 5077 // 5078 // Data output enable for DIO0 5079 // ENUMs: 5080 // EN Output enabled 5081 // DIS Output disabled 5082 #define GPIO_DOE31_0_DIO0 0x00000001U 5083 #define GPIO_DOE31_0_DIO0_M 0x00000001U 5084 #define GPIO_DOE31_0_DIO0_S 0U 5085 #define GPIO_DOE31_0_DIO0_EN 0x00000001U 5086 #define GPIO_DOE31_0_DIO0_DIS 0x00000000U 5087 5088 //***************************************************************************** 5089 // 5090 // Register: GPIO_O_DOESET31_0 5091 // 5092 //***************************************************************************** 5093 // Field: [25] DIO25 5094 // 5095 // Sets bit DOE31_0.DIO25 5096 // ENUMs: 5097 // SET 5098 // NOEFF No effect 5099 #define GPIO_DOESET31_0_DIO25 0x02000000U 5100 #define GPIO_DOESET31_0_DIO25_M 0x02000000U 5101 #define GPIO_DOESET31_0_DIO25_S 25U 5102 #define GPIO_DOESET31_0_DIO25_SET 0x02000000U 5103 #define GPIO_DOESET31_0_DIO25_NOEFF 0x00000000U 5104 5105 // Field: [24] DIO24 5106 // 5107 // Sets bit DOE31_0.DIO24 5108 // ENUMs: 5109 // SET 5110 // NOEFF No effect 5111 #define GPIO_DOESET31_0_DIO24 0x01000000U 5112 #define GPIO_DOESET31_0_DIO24_M 0x01000000U 5113 #define GPIO_DOESET31_0_DIO24_S 24U 5114 #define GPIO_DOESET31_0_DIO24_SET 0x01000000U 5115 #define GPIO_DOESET31_0_DIO24_NOEFF 0x00000000U 5116 5117 // Field: [23] DIO23 5118 // 5119 // Sets bit DOE31_0.DIO23 5120 // ENUMs: 5121 // SET 5122 // NOEFF No effect 5123 #define GPIO_DOESET31_0_DIO23 0x00800000U 5124 #define GPIO_DOESET31_0_DIO23_M 0x00800000U 5125 #define GPIO_DOESET31_0_DIO23_S 23U 5126 #define GPIO_DOESET31_0_DIO23_SET 0x00800000U 5127 #define GPIO_DOESET31_0_DIO23_NOEFF 0x00000000U 5128 5129 // Field: [22] DIO22 5130 // 5131 // Sets bit DOE31_0.DIO22 5132 // ENUMs: 5133 // SET 5134 // NOEFF No effect 5135 #define GPIO_DOESET31_0_DIO22 0x00400000U 5136 #define GPIO_DOESET31_0_DIO22_M 0x00400000U 5137 #define GPIO_DOESET31_0_DIO22_S 22U 5138 #define GPIO_DOESET31_0_DIO22_SET 0x00400000U 5139 #define GPIO_DOESET31_0_DIO22_NOEFF 0x00000000U 5140 5141 // Field: [21] DIO21 5142 // 5143 // Sets bit DOE31_0.DIO21 5144 // ENUMs: 5145 // SET 5146 // NOEFF No effect 5147 #define GPIO_DOESET31_0_DIO21 0x00200000U 5148 #define GPIO_DOESET31_0_DIO21_M 0x00200000U 5149 #define GPIO_DOESET31_0_DIO21_S 21U 5150 #define GPIO_DOESET31_0_DIO21_SET 0x00200000U 5151 #define GPIO_DOESET31_0_DIO21_NOEFF 0x00000000U 5152 5153 // Field: [20] DIO20 5154 // 5155 // Sets bit DOE31_0.DIO20 5156 // ENUMs: 5157 // SET 5158 // NOEFF No effect 5159 #define GPIO_DOESET31_0_DIO20 0x00100000U 5160 #define GPIO_DOESET31_0_DIO20_M 0x00100000U 5161 #define GPIO_DOESET31_0_DIO20_S 20U 5162 #define GPIO_DOESET31_0_DIO20_SET 0x00100000U 5163 #define GPIO_DOESET31_0_DIO20_NOEFF 0x00000000U 5164 5165 // Field: [19] DIO19 5166 // 5167 // Sets bit DOE31_0.DIO19 5168 // ENUMs: 5169 // SET 5170 // NOEFF No effect 5171 #define GPIO_DOESET31_0_DIO19 0x00080000U 5172 #define GPIO_DOESET31_0_DIO19_M 0x00080000U 5173 #define GPIO_DOESET31_0_DIO19_S 19U 5174 #define GPIO_DOESET31_0_DIO19_SET 0x00080000U 5175 #define GPIO_DOESET31_0_DIO19_NOEFF 0x00000000U 5176 5177 // Field: [18] DIO18 5178 // 5179 // Sets bit DOE31_0.DIO18 5180 // ENUMs: 5181 // SET 5182 // NOEFF No effect 5183 #define GPIO_DOESET31_0_DIO18 0x00040000U 5184 #define GPIO_DOESET31_0_DIO18_M 0x00040000U 5185 #define GPIO_DOESET31_0_DIO18_S 18U 5186 #define GPIO_DOESET31_0_DIO18_SET 0x00040000U 5187 #define GPIO_DOESET31_0_DIO18_NOEFF 0x00000000U 5188 5189 // Field: [17] DIO17 5190 // 5191 // Sets bit DOE31_0.DIO17 5192 // ENUMs: 5193 // SET 5194 // NOEFF No effect 5195 #define GPIO_DOESET31_0_DIO17 0x00020000U 5196 #define GPIO_DOESET31_0_DIO17_M 0x00020000U 5197 #define GPIO_DOESET31_0_DIO17_S 17U 5198 #define GPIO_DOESET31_0_DIO17_SET 0x00020000U 5199 #define GPIO_DOESET31_0_DIO17_NOEFF 0x00000000U 5200 5201 // Field: [16] DIO16 5202 // 5203 // Sets bit DOE31_0.DIO16 5204 // ENUMs: 5205 // SET 5206 // NOEFF No effect 5207 #define GPIO_DOESET31_0_DIO16 0x00010000U 5208 #define GPIO_DOESET31_0_DIO16_M 0x00010000U 5209 #define GPIO_DOESET31_0_DIO16_S 16U 5210 #define GPIO_DOESET31_0_DIO16_SET 0x00010000U 5211 #define GPIO_DOESET31_0_DIO16_NOEFF 0x00000000U 5212 5213 // Field: [15] DIO15 5214 // 5215 // Sets bit DOE31_0.DIO15 5216 // ENUMs: 5217 // SET 5218 // NOEFF No effect 5219 #define GPIO_DOESET31_0_DIO15 0x00008000U 5220 #define GPIO_DOESET31_0_DIO15_M 0x00008000U 5221 #define GPIO_DOESET31_0_DIO15_S 15U 5222 #define GPIO_DOESET31_0_DIO15_SET 0x00008000U 5223 #define GPIO_DOESET31_0_DIO15_NOEFF 0x00000000U 5224 5225 // Field: [14] DIO14 5226 // 5227 // Sets bit DOE31_0.DIO14 5228 // ENUMs: 5229 // SET 5230 // NOEFF No effect 5231 #define GPIO_DOESET31_0_DIO14 0x00004000U 5232 #define GPIO_DOESET31_0_DIO14_M 0x00004000U 5233 #define GPIO_DOESET31_0_DIO14_S 14U 5234 #define GPIO_DOESET31_0_DIO14_SET 0x00004000U 5235 #define GPIO_DOESET31_0_DIO14_NOEFF 0x00000000U 5236 5237 // Field: [13] DIO13 5238 // 5239 // Sets bit DOE31_0.DIO13 5240 // ENUMs: 5241 // SET 5242 // NOEFF No effect 5243 #define GPIO_DOESET31_0_DIO13 0x00002000U 5244 #define GPIO_DOESET31_0_DIO13_M 0x00002000U 5245 #define GPIO_DOESET31_0_DIO13_S 13U 5246 #define GPIO_DOESET31_0_DIO13_SET 0x00002000U 5247 #define GPIO_DOESET31_0_DIO13_NOEFF 0x00000000U 5248 5249 // Field: [12] DIO12 5250 // 5251 // Sets bit DOE31_0.DIO12 5252 // ENUMs: 5253 // SET 5254 // NOEFF No effect 5255 #define GPIO_DOESET31_0_DIO12 0x00001000U 5256 #define GPIO_DOESET31_0_DIO12_M 0x00001000U 5257 #define GPIO_DOESET31_0_DIO12_S 12U 5258 #define GPIO_DOESET31_0_DIO12_SET 0x00001000U 5259 #define GPIO_DOESET31_0_DIO12_NOEFF 0x00000000U 5260 5261 // Field: [11] DIO11 5262 // 5263 // Sets bit DOE31_0.DIO11 5264 // ENUMs: 5265 // SET 5266 // NOEFF No effect 5267 #define GPIO_DOESET31_0_DIO11 0x00000800U 5268 #define GPIO_DOESET31_0_DIO11_M 0x00000800U 5269 #define GPIO_DOESET31_0_DIO11_S 11U 5270 #define GPIO_DOESET31_0_DIO11_SET 0x00000800U 5271 #define GPIO_DOESET31_0_DIO11_NOEFF 0x00000000U 5272 5273 // Field: [10] DIO10 5274 // 5275 // Sets bit DOE31_0.DIO10 5276 // ENUMs: 5277 // SET 5278 // NOEFF No effect 5279 #define GPIO_DOESET31_0_DIO10 0x00000400U 5280 #define GPIO_DOESET31_0_DIO10_M 0x00000400U 5281 #define GPIO_DOESET31_0_DIO10_S 10U 5282 #define GPIO_DOESET31_0_DIO10_SET 0x00000400U 5283 #define GPIO_DOESET31_0_DIO10_NOEFF 0x00000000U 5284 5285 // Field: [9] DIO9 5286 // 5287 // Sets bit DOE31_0.DIO9 5288 // ENUMs: 5289 // SET 5290 // NOEFF No effect 5291 #define GPIO_DOESET31_0_DIO9 0x00000200U 5292 #define GPIO_DOESET31_0_DIO9_M 0x00000200U 5293 #define GPIO_DOESET31_0_DIO9_S 9U 5294 #define GPIO_DOESET31_0_DIO9_SET 0x00000200U 5295 #define GPIO_DOESET31_0_DIO9_NOEFF 0x00000000U 5296 5297 // Field: [8] DIO8 5298 // 5299 // Sets bit DOE31_0.DIO8 5300 // ENUMs: 5301 // SET 5302 // NOEFF No effect 5303 #define GPIO_DOESET31_0_DIO8 0x00000100U 5304 #define GPIO_DOESET31_0_DIO8_M 0x00000100U 5305 #define GPIO_DOESET31_0_DIO8_S 8U 5306 #define GPIO_DOESET31_0_DIO8_SET 0x00000100U 5307 #define GPIO_DOESET31_0_DIO8_NOEFF 0x00000000U 5308 5309 // Field: [7] DIO7 5310 // 5311 // Sets bit DOE31_0.DIO7 5312 // ENUMs: 5313 // SET 5314 // NOEFF No effect 5315 #define GPIO_DOESET31_0_DIO7 0x00000080U 5316 #define GPIO_DOESET31_0_DIO7_M 0x00000080U 5317 #define GPIO_DOESET31_0_DIO7_S 7U 5318 #define GPIO_DOESET31_0_DIO7_SET 0x00000080U 5319 #define GPIO_DOESET31_0_DIO7_NOEFF 0x00000000U 5320 5321 // Field: [6] DIO6 5322 // 5323 // Sets bit DOE31_0.DIO6 5324 // ENUMs: 5325 // SET 5326 // NOEFF No effect 5327 #define GPIO_DOESET31_0_DIO6 0x00000040U 5328 #define GPIO_DOESET31_0_DIO6_M 0x00000040U 5329 #define GPIO_DOESET31_0_DIO6_S 6U 5330 #define GPIO_DOESET31_0_DIO6_SET 0x00000040U 5331 #define GPIO_DOESET31_0_DIO6_NOEFF 0x00000000U 5332 5333 // Field: [5] DIO5 5334 // 5335 // Sets bit DOE31_0.DIO5 5336 // ENUMs: 5337 // SET 5338 // NOEFF No effect 5339 #define GPIO_DOESET31_0_DIO5 0x00000020U 5340 #define GPIO_DOESET31_0_DIO5_M 0x00000020U 5341 #define GPIO_DOESET31_0_DIO5_S 5U 5342 #define GPIO_DOESET31_0_DIO5_SET 0x00000020U 5343 #define GPIO_DOESET31_0_DIO5_NOEFF 0x00000000U 5344 5345 // Field: [4] DIO4 5346 // 5347 // Sets bit DOE31_0.DIO4 5348 // ENUMs: 5349 // SET 5350 // NOEFF No effect 5351 #define GPIO_DOESET31_0_DIO4 0x00000010U 5352 #define GPIO_DOESET31_0_DIO4_M 0x00000010U 5353 #define GPIO_DOESET31_0_DIO4_S 4U 5354 #define GPIO_DOESET31_0_DIO4_SET 0x00000010U 5355 #define GPIO_DOESET31_0_DIO4_NOEFF 0x00000000U 5356 5357 // Field: [3] DIO3 5358 // 5359 // Sets bit DOE31_0.DIO3 5360 // ENUMs: 5361 // SET 5362 // NOEFF No effect 5363 #define GPIO_DOESET31_0_DIO3 0x00000008U 5364 #define GPIO_DOESET31_0_DIO3_M 0x00000008U 5365 #define GPIO_DOESET31_0_DIO3_S 3U 5366 #define GPIO_DOESET31_0_DIO3_SET 0x00000008U 5367 #define GPIO_DOESET31_0_DIO3_NOEFF 0x00000000U 5368 5369 // Field: [2] DIO2 5370 // 5371 // Sets bit DOE31_0.DIO2 5372 // ENUMs: 5373 // SET 5374 // NOEFF No effect 5375 #define GPIO_DOESET31_0_DIO2 0x00000004U 5376 #define GPIO_DOESET31_0_DIO2_M 0x00000004U 5377 #define GPIO_DOESET31_0_DIO2_S 2U 5378 #define GPIO_DOESET31_0_DIO2_SET 0x00000004U 5379 #define GPIO_DOESET31_0_DIO2_NOEFF 0x00000000U 5380 5381 // Field: [1] DIO1 5382 // 5383 // Sets bit DOE31_0.DIO1 5384 // ENUMs: 5385 // SET 5386 // NOEFF No effect 5387 #define GPIO_DOESET31_0_DIO1 0x00000002U 5388 #define GPIO_DOESET31_0_DIO1_M 0x00000002U 5389 #define GPIO_DOESET31_0_DIO1_S 1U 5390 #define GPIO_DOESET31_0_DIO1_SET 0x00000002U 5391 #define GPIO_DOESET31_0_DIO1_NOEFF 0x00000000U 5392 5393 // Field: [0] DIO0 5394 // 5395 // Sets bit DOE31_0.DIO0 5396 // ENUMs: 5397 // SET 5398 // NOEFF No effect 5399 #define GPIO_DOESET31_0_DIO0 0x00000001U 5400 #define GPIO_DOESET31_0_DIO0_M 0x00000001U 5401 #define GPIO_DOESET31_0_DIO0_S 0U 5402 #define GPIO_DOESET31_0_DIO0_SET 0x00000001U 5403 #define GPIO_DOESET31_0_DIO0_NOEFF 0x00000000U 5404 5405 //***************************************************************************** 5406 // 5407 // Register: GPIO_O_DOECLR31_0 5408 // 5409 //***************************************************************************** 5410 // Field: [25] DIO25 5411 // 5412 // Clears bit DOE31_0.DIO25 5413 // ENUMs: 5414 // CLR Clear 5415 // NOEFF No effect 5416 #define GPIO_DOECLR31_0_DIO25 0x02000000U 5417 #define GPIO_DOECLR31_0_DIO25_M 0x02000000U 5418 #define GPIO_DOECLR31_0_DIO25_S 25U 5419 #define GPIO_DOECLR31_0_DIO25_CLR 0x02000000U 5420 #define GPIO_DOECLR31_0_DIO25_NOEFF 0x00000000U 5421 5422 // Field: [24] DIO24 5423 // 5424 // Clears bit DOE31_0.DIO24 5425 // ENUMs: 5426 // CLR Clear 5427 // NOEFF No effect 5428 #define GPIO_DOECLR31_0_DIO24 0x01000000U 5429 #define GPIO_DOECLR31_0_DIO24_M 0x01000000U 5430 #define GPIO_DOECLR31_0_DIO24_S 24U 5431 #define GPIO_DOECLR31_0_DIO24_CLR 0x01000000U 5432 #define GPIO_DOECLR31_0_DIO24_NOEFF 0x00000000U 5433 5434 // Field: [23] DIO23 5435 // 5436 // Clears bit DOE31_0.DIO23 5437 // ENUMs: 5438 // CLR Clear 5439 // NOEFF No effect 5440 #define GPIO_DOECLR31_0_DIO23 0x00800000U 5441 #define GPIO_DOECLR31_0_DIO23_M 0x00800000U 5442 #define GPIO_DOECLR31_0_DIO23_S 23U 5443 #define GPIO_DOECLR31_0_DIO23_CLR 0x00800000U 5444 #define GPIO_DOECLR31_0_DIO23_NOEFF 0x00000000U 5445 5446 // Field: [22] DIO22 5447 // 5448 // Clears bit DOE31_0.DIO22 5449 // ENUMs: 5450 // CLR Clear 5451 // NOEFF No effect 5452 #define GPIO_DOECLR31_0_DIO22 0x00400000U 5453 #define GPIO_DOECLR31_0_DIO22_M 0x00400000U 5454 #define GPIO_DOECLR31_0_DIO22_S 22U 5455 #define GPIO_DOECLR31_0_DIO22_CLR 0x00400000U 5456 #define GPIO_DOECLR31_0_DIO22_NOEFF 0x00000000U 5457 5458 // Field: [21] DIO21 5459 // 5460 // Clears bit DOE31_0.DIO21 5461 // ENUMs: 5462 // CLR Clear 5463 // NOEFF No effect 5464 #define GPIO_DOECLR31_0_DIO21 0x00200000U 5465 #define GPIO_DOECLR31_0_DIO21_M 0x00200000U 5466 #define GPIO_DOECLR31_0_DIO21_S 21U 5467 #define GPIO_DOECLR31_0_DIO21_CLR 0x00200000U 5468 #define GPIO_DOECLR31_0_DIO21_NOEFF 0x00000000U 5469 5470 // Field: [20] DIO20 5471 // 5472 // Clears bit DOE31_0.DIO20 5473 // ENUMs: 5474 // CLR Clear 5475 // NOEFF No effect 5476 #define GPIO_DOECLR31_0_DIO20 0x00100000U 5477 #define GPIO_DOECLR31_0_DIO20_M 0x00100000U 5478 #define GPIO_DOECLR31_0_DIO20_S 20U 5479 #define GPIO_DOECLR31_0_DIO20_CLR 0x00100000U 5480 #define GPIO_DOECLR31_0_DIO20_NOEFF 0x00000000U 5481 5482 // Field: [19] DIO19 5483 // 5484 // Clears bit DOE31_0.DIO19 5485 // ENUMs: 5486 // CLR Clear 5487 // NOEFF No effect 5488 #define GPIO_DOECLR31_0_DIO19 0x00080000U 5489 #define GPIO_DOECLR31_0_DIO19_M 0x00080000U 5490 #define GPIO_DOECLR31_0_DIO19_S 19U 5491 #define GPIO_DOECLR31_0_DIO19_CLR 0x00080000U 5492 #define GPIO_DOECLR31_0_DIO19_NOEFF 0x00000000U 5493 5494 // Field: [18] DIO18 5495 // 5496 // Clears bit DOE31_0.DIO18 5497 // ENUMs: 5498 // CLR Clear 5499 // NOEFF No effect 5500 #define GPIO_DOECLR31_0_DIO18 0x00040000U 5501 #define GPIO_DOECLR31_0_DIO18_M 0x00040000U 5502 #define GPIO_DOECLR31_0_DIO18_S 18U 5503 #define GPIO_DOECLR31_0_DIO18_CLR 0x00040000U 5504 #define GPIO_DOECLR31_0_DIO18_NOEFF 0x00000000U 5505 5506 // Field: [17] DIO17 5507 // 5508 // Clears bit DOE31_0.DIO17 5509 // ENUMs: 5510 // CLR Clear 5511 // NOEFF No effect 5512 #define GPIO_DOECLR31_0_DIO17 0x00020000U 5513 #define GPIO_DOECLR31_0_DIO17_M 0x00020000U 5514 #define GPIO_DOECLR31_0_DIO17_S 17U 5515 #define GPIO_DOECLR31_0_DIO17_CLR 0x00020000U 5516 #define GPIO_DOECLR31_0_DIO17_NOEFF 0x00000000U 5517 5518 // Field: [16] DIO16 5519 // 5520 // Clears bit DOE31_0.DIO16 5521 // ENUMs: 5522 // CLR Clear 5523 // NOEFF No effect 5524 #define GPIO_DOECLR31_0_DIO16 0x00010000U 5525 #define GPIO_DOECLR31_0_DIO16_M 0x00010000U 5526 #define GPIO_DOECLR31_0_DIO16_S 16U 5527 #define GPIO_DOECLR31_0_DIO16_CLR 0x00010000U 5528 #define GPIO_DOECLR31_0_DIO16_NOEFF 0x00000000U 5529 5530 // Field: [15] DIO15 5531 // 5532 // Clears bit DOE31_0.DIO15 5533 // ENUMs: 5534 // CLR Clear 5535 // NOEFF No effect 5536 #define GPIO_DOECLR31_0_DIO15 0x00008000U 5537 #define GPIO_DOECLR31_0_DIO15_M 0x00008000U 5538 #define GPIO_DOECLR31_0_DIO15_S 15U 5539 #define GPIO_DOECLR31_0_DIO15_CLR 0x00008000U 5540 #define GPIO_DOECLR31_0_DIO15_NOEFF 0x00000000U 5541 5542 // Field: [14] DIO14 5543 // 5544 // Clears bit DOE31_0.DIO14 5545 // ENUMs: 5546 // CLR Clear 5547 // NOEFF No effect 5548 #define GPIO_DOECLR31_0_DIO14 0x00004000U 5549 #define GPIO_DOECLR31_0_DIO14_M 0x00004000U 5550 #define GPIO_DOECLR31_0_DIO14_S 14U 5551 #define GPIO_DOECLR31_0_DIO14_CLR 0x00004000U 5552 #define GPIO_DOECLR31_0_DIO14_NOEFF 0x00000000U 5553 5554 // Field: [13] DIO13 5555 // 5556 // Clears bit DOE31_0.DIO13 5557 // ENUMs: 5558 // CLR Clear 5559 // NOEFF No effect 5560 #define GPIO_DOECLR31_0_DIO13 0x00002000U 5561 #define GPIO_DOECLR31_0_DIO13_M 0x00002000U 5562 #define GPIO_DOECLR31_0_DIO13_S 13U 5563 #define GPIO_DOECLR31_0_DIO13_CLR 0x00002000U 5564 #define GPIO_DOECLR31_0_DIO13_NOEFF 0x00000000U 5565 5566 // Field: [12] DIO12 5567 // 5568 // Clears bit DOE31_0.DIO12 5569 // ENUMs: 5570 // CLR Clear 5571 // NOEFF No effect 5572 #define GPIO_DOECLR31_0_DIO12 0x00001000U 5573 #define GPIO_DOECLR31_0_DIO12_M 0x00001000U 5574 #define GPIO_DOECLR31_0_DIO12_S 12U 5575 #define GPIO_DOECLR31_0_DIO12_CLR 0x00001000U 5576 #define GPIO_DOECLR31_0_DIO12_NOEFF 0x00000000U 5577 5578 // Field: [11] DIO11 5579 // 5580 // Clears bit DOE31_0.DIO11 5581 // ENUMs: 5582 // CLR Clear 5583 // NOEFF No effect 5584 #define GPIO_DOECLR31_0_DIO11 0x00000800U 5585 #define GPIO_DOECLR31_0_DIO11_M 0x00000800U 5586 #define GPIO_DOECLR31_0_DIO11_S 11U 5587 #define GPIO_DOECLR31_0_DIO11_CLR 0x00000800U 5588 #define GPIO_DOECLR31_0_DIO11_NOEFF 0x00000000U 5589 5590 // Field: [10] DIO10 5591 // 5592 // Clears bit DOE31_0.DIO10 5593 // ENUMs: 5594 // CLR Clear 5595 // NOEFF No effect 5596 #define GPIO_DOECLR31_0_DIO10 0x00000400U 5597 #define GPIO_DOECLR31_0_DIO10_M 0x00000400U 5598 #define GPIO_DOECLR31_0_DIO10_S 10U 5599 #define GPIO_DOECLR31_0_DIO10_CLR 0x00000400U 5600 #define GPIO_DOECLR31_0_DIO10_NOEFF 0x00000000U 5601 5602 // Field: [9] DIO9 5603 // 5604 // Clears bit DOE31_0.DIO9 5605 // ENUMs: 5606 // CLR Clear 5607 // NOEFF No effect 5608 #define GPIO_DOECLR31_0_DIO9 0x00000200U 5609 #define GPIO_DOECLR31_0_DIO9_M 0x00000200U 5610 #define GPIO_DOECLR31_0_DIO9_S 9U 5611 #define GPIO_DOECLR31_0_DIO9_CLR 0x00000200U 5612 #define GPIO_DOECLR31_0_DIO9_NOEFF 0x00000000U 5613 5614 // Field: [8] DIO8 5615 // 5616 // Clears bit DOE31_0.DIO8 5617 // ENUMs: 5618 // CLR Clear 5619 // NOEFF No effect 5620 #define GPIO_DOECLR31_0_DIO8 0x00000100U 5621 #define GPIO_DOECLR31_0_DIO8_M 0x00000100U 5622 #define GPIO_DOECLR31_0_DIO8_S 8U 5623 #define GPIO_DOECLR31_0_DIO8_CLR 0x00000100U 5624 #define GPIO_DOECLR31_0_DIO8_NOEFF 0x00000000U 5625 5626 // Field: [7] DIO7 5627 // 5628 // Clears bit DOE31_0.DIO7 5629 // ENUMs: 5630 // CLR Clear 5631 // NOEFF No effect 5632 #define GPIO_DOECLR31_0_DIO7 0x00000080U 5633 #define GPIO_DOECLR31_0_DIO7_M 0x00000080U 5634 #define GPIO_DOECLR31_0_DIO7_S 7U 5635 #define GPIO_DOECLR31_0_DIO7_CLR 0x00000080U 5636 #define GPIO_DOECLR31_0_DIO7_NOEFF 0x00000000U 5637 5638 // Field: [6] DIO6 5639 // 5640 // Clears bit DOE31_0.DIO6 5641 // ENUMs: 5642 // CLR Clear 5643 // NOEFF No effect 5644 #define GPIO_DOECLR31_0_DIO6 0x00000040U 5645 #define GPIO_DOECLR31_0_DIO6_M 0x00000040U 5646 #define GPIO_DOECLR31_0_DIO6_S 6U 5647 #define GPIO_DOECLR31_0_DIO6_CLR 0x00000040U 5648 #define GPIO_DOECLR31_0_DIO6_NOEFF 0x00000000U 5649 5650 // Field: [5] DIO5 5651 // 5652 // Clears bit DOE31_0.DIO5 5653 // ENUMs: 5654 // CLR Clear 5655 // NOEFF No effect 5656 #define GPIO_DOECLR31_0_DIO5 0x00000020U 5657 #define GPIO_DOECLR31_0_DIO5_M 0x00000020U 5658 #define GPIO_DOECLR31_0_DIO5_S 5U 5659 #define GPIO_DOECLR31_0_DIO5_CLR 0x00000020U 5660 #define GPIO_DOECLR31_0_DIO5_NOEFF 0x00000000U 5661 5662 // Field: [4] DIO4 5663 // 5664 // Clears bit DOE31_0.DIO4 5665 // ENUMs: 5666 // CLR Clear 5667 // NOEFF No effect 5668 #define GPIO_DOECLR31_0_DIO4 0x00000010U 5669 #define GPIO_DOECLR31_0_DIO4_M 0x00000010U 5670 #define GPIO_DOECLR31_0_DIO4_S 4U 5671 #define GPIO_DOECLR31_0_DIO4_CLR 0x00000010U 5672 #define GPIO_DOECLR31_0_DIO4_NOEFF 0x00000000U 5673 5674 // Field: [3] DIO3 5675 // 5676 // Clears bit DOE31_0.DIO3 5677 // ENUMs: 5678 // CLR Clear 5679 // NOEFF No effect 5680 #define GPIO_DOECLR31_0_DIO3 0x00000008U 5681 #define GPIO_DOECLR31_0_DIO3_M 0x00000008U 5682 #define GPIO_DOECLR31_0_DIO3_S 3U 5683 #define GPIO_DOECLR31_0_DIO3_CLR 0x00000008U 5684 #define GPIO_DOECLR31_0_DIO3_NOEFF 0x00000000U 5685 5686 // Field: [2] DIO2 5687 // 5688 // Clears bit DOE31_0.DIO2 5689 // ENUMs: 5690 // CLR Clear 5691 // NOEFF No effect 5692 #define GPIO_DOECLR31_0_DIO2 0x00000004U 5693 #define GPIO_DOECLR31_0_DIO2_M 0x00000004U 5694 #define GPIO_DOECLR31_0_DIO2_S 2U 5695 #define GPIO_DOECLR31_0_DIO2_CLR 0x00000004U 5696 #define GPIO_DOECLR31_0_DIO2_NOEFF 0x00000000U 5697 5698 // Field: [1] DIO1 5699 // 5700 // Clears bit DOE31_0.DIO1 5701 // ENUMs: 5702 // CLR Clear 5703 // NOEFF No effect 5704 #define GPIO_DOECLR31_0_DIO1 0x00000002U 5705 #define GPIO_DOECLR31_0_DIO1_M 0x00000002U 5706 #define GPIO_DOECLR31_0_DIO1_S 1U 5707 #define GPIO_DOECLR31_0_DIO1_CLR 0x00000002U 5708 #define GPIO_DOECLR31_0_DIO1_NOEFF 0x00000000U 5709 5710 // Field: [0] DIO0 5711 // 5712 // Clears bit DOE31_0.DIO0 5713 // ENUMs: 5714 // CLR Clear 5715 // NOEFF No effect 5716 #define GPIO_DOECLR31_0_DIO0 0x00000001U 5717 #define GPIO_DOECLR31_0_DIO0_M 0x00000001U 5718 #define GPIO_DOECLR31_0_DIO0_S 0U 5719 #define GPIO_DOECLR31_0_DIO0_CLR 0x00000001U 5720 #define GPIO_DOECLR31_0_DIO0_NOEFF 0x00000000U 5721 5722 //***************************************************************************** 5723 // 5724 // Register: GPIO_O_DOETGL31_0 5725 // 5726 //***************************************************************************** 5727 // Field: [25] DIO25 5728 // 5729 // Toggles bit DOE31_0.DIO25 5730 // ENUMs: 5731 // TOGGLE Toggle 5732 // NOEFF No effect 5733 #define GPIO_DOETGL31_0_DIO25 0x02000000U 5734 #define GPIO_DOETGL31_0_DIO25_M 0x02000000U 5735 #define GPIO_DOETGL31_0_DIO25_S 25U 5736 #define GPIO_DOETGL31_0_DIO25_TOGGLE 0x02000000U 5737 #define GPIO_DOETGL31_0_DIO25_NOEFF 0x00000000U 5738 5739 // Field: [24] DIO24 5740 // 5741 // Toggles bit DOE31_0.DIO24 5742 // ENUMs: 5743 // TOGGLE Toggle 5744 // NOEFF No effect 5745 #define GPIO_DOETGL31_0_DIO24 0x01000000U 5746 #define GPIO_DOETGL31_0_DIO24_M 0x01000000U 5747 #define GPIO_DOETGL31_0_DIO24_S 24U 5748 #define GPIO_DOETGL31_0_DIO24_TOGGLE 0x01000000U 5749 #define GPIO_DOETGL31_0_DIO24_NOEFF 0x00000000U 5750 5751 // Field: [23] DIO23 5752 // 5753 // Toggles bit DOE31_0.DIO23 5754 // ENUMs: 5755 // TOGGLE Toggle 5756 // NOEFF No effect 5757 #define GPIO_DOETGL31_0_DIO23 0x00800000U 5758 #define GPIO_DOETGL31_0_DIO23_M 0x00800000U 5759 #define GPIO_DOETGL31_0_DIO23_S 23U 5760 #define GPIO_DOETGL31_0_DIO23_TOGGLE 0x00800000U 5761 #define GPIO_DOETGL31_0_DIO23_NOEFF 0x00000000U 5762 5763 // Field: [22] DIO22 5764 // 5765 // Toggles bit DOE31_0.DIO22 5766 // ENUMs: 5767 // TOGGLE Toggle 5768 // NOEFF No effect 5769 #define GPIO_DOETGL31_0_DIO22 0x00400000U 5770 #define GPIO_DOETGL31_0_DIO22_M 0x00400000U 5771 #define GPIO_DOETGL31_0_DIO22_S 22U 5772 #define GPIO_DOETGL31_0_DIO22_TOGGLE 0x00400000U 5773 #define GPIO_DOETGL31_0_DIO22_NOEFF 0x00000000U 5774 5775 // Field: [21] DIO21 5776 // 5777 // Toggles bit DOE31_0.DIO21 5778 // ENUMs: 5779 // TOGGLE Toggle 5780 // NOEFF No effect 5781 #define GPIO_DOETGL31_0_DIO21 0x00200000U 5782 #define GPIO_DOETGL31_0_DIO21_M 0x00200000U 5783 #define GPIO_DOETGL31_0_DIO21_S 21U 5784 #define GPIO_DOETGL31_0_DIO21_TOGGLE 0x00200000U 5785 #define GPIO_DOETGL31_0_DIO21_NOEFF 0x00000000U 5786 5787 // Field: [20] DIO20 5788 // 5789 // Toggles bit DOE31_0.DIO20 5790 // ENUMs: 5791 // TOGGLE Toggle 5792 // NOEFF No effect 5793 #define GPIO_DOETGL31_0_DIO20 0x00100000U 5794 #define GPIO_DOETGL31_0_DIO20_M 0x00100000U 5795 #define GPIO_DOETGL31_0_DIO20_S 20U 5796 #define GPIO_DOETGL31_0_DIO20_TOGGLE 0x00100000U 5797 #define GPIO_DOETGL31_0_DIO20_NOEFF 0x00000000U 5798 5799 // Field: [19] DIO19 5800 // 5801 // Toggles bit DOE31_0.DIO19 5802 // ENUMs: 5803 // TOGGLE Toggle 5804 // NOEFF No effect 5805 #define GPIO_DOETGL31_0_DIO19 0x00080000U 5806 #define GPIO_DOETGL31_0_DIO19_M 0x00080000U 5807 #define GPIO_DOETGL31_0_DIO19_S 19U 5808 #define GPIO_DOETGL31_0_DIO19_TOGGLE 0x00080000U 5809 #define GPIO_DOETGL31_0_DIO19_NOEFF 0x00000000U 5810 5811 // Field: [18] DIO18 5812 // 5813 // Toggles bit DOE31_0.DIO18 5814 // ENUMs: 5815 // TOGGLE Toggle 5816 // NOEFF No effect 5817 #define GPIO_DOETGL31_0_DIO18 0x00040000U 5818 #define GPIO_DOETGL31_0_DIO18_M 0x00040000U 5819 #define GPIO_DOETGL31_0_DIO18_S 18U 5820 #define GPIO_DOETGL31_0_DIO18_TOGGLE 0x00040000U 5821 #define GPIO_DOETGL31_0_DIO18_NOEFF 0x00000000U 5822 5823 // Field: [17] DIO17 5824 // 5825 // Toggles bit DOE31_0.DIO17 5826 // ENUMs: 5827 // TOGGLE Toggle 5828 // NOEFF No effect 5829 #define GPIO_DOETGL31_0_DIO17 0x00020000U 5830 #define GPIO_DOETGL31_0_DIO17_M 0x00020000U 5831 #define GPIO_DOETGL31_0_DIO17_S 17U 5832 #define GPIO_DOETGL31_0_DIO17_TOGGLE 0x00020000U 5833 #define GPIO_DOETGL31_0_DIO17_NOEFF 0x00000000U 5834 5835 // Field: [16] DIO16 5836 // 5837 // Toggles bit DOE31_0.DIO16 5838 // ENUMs: 5839 // TOGGLE Toggle 5840 // NOEFF No effect 5841 #define GPIO_DOETGL31_0_DIO16 0x00010000U 5842 #define GPIO_DOETGL31_0_DIO16_M 0x00010000U 5843 #define GPIO_DOETGL31_0_DIO16_S 16U 5844 #define GPIO_DOETGL31_0_DIO16_TOGGLE 0x00010000U 5845 #define GPIO_DOETGL31_0_DIO16_NOEFF 0x00000000U 5846 5847 // Field: [15] DIO15 5848 // 5849 // Toggles bit DOE31_0.DIO15 5850 // ENUMs: 5851 // TOGGLE Toggle 5852 // NOEFF No effect 5853 #define GPIO_DOETGL31_0_DIO15 0x00008000U 5854 #define GPIO_DOETGL31_0_DIO15_M 0x00008000U 5855 #define GPIO_DOETGL31_0_DIO15_S 15U 5856 #define GPIO_DOETGL31_0_DIO15_TOGGLE 0x00008000U 5857 #define GPIO_DOETGL31_0_DIO15_NOEFF 0x00000000U 5858 5859 // Field: [14] DIO14 5860 // 5861 // Toggles bit DOE31_0.DIO14 5862 // ENUMs: 5863 // TOGGLE Toggle 5864 // NOEFF No effect 5865 #define GPIO_DOETGL31_0_DIO14 0x00004000U 5866 #define GPIO_DOETGL31_0_DIO14_M 0x00004000U 5867 #define GPIO_DOETGL31_0_DIO14_S 14U 5868 #define GPIO_DOETGL31_0_DIO14_TOGGLE 0x00004000U 5869 #define GPIO_DOETGL31_0_DIO14_NOEFF 0x00000000U 5870 5871 // Field: [13] DIO13 5872 // 5873 // Toggles bit DOE31_0.DIO13 5874 // ENUMs: 5875 // TOGGLE Toggle 5876 // NOEFF No effect 5877 #define GPIO_DOETGL31_0_DIO13 0x00002000U 5878 #define GPIO_DOETGL31_0_DIO13_M 0x00002000U 5879 #define GPIO_DOETGL31_0_DIO13_S 13U 5880 #define GPIO_DOETGL31_0_DIO13_TOGGLE 0x00002000U 5881 #define GPIO_DOETGL31_0_DIO13_NOEFF 0x00000000U 5882 5883 // Field: [12] DIO12 5884 // 5885 // Toggles bit DOE31_0.DIO12 5886 // ENUMs: 5887 // TOGGLE Toggle 5888 // NOEFF No effect 5889 #define GPIO_DOETGL31_0_DIO12 0x00001000U 5890 #define GPIO_DOETGL31_0_DIO12_M 0x00001000U 5891 #define GPIO_DOETGL31_0_DIO12_S 12U 5892 #define GPIO_DOETGL31_0_DIO12_TOGGLE 0x00001000U 5893 #define GPIO_DOETGL31_0_DIO12_NOEFF 0x00000000U 5894 5895 // Field: [11] DIO11 5896 // 5897 // Toggles bit DOE31_0.DIO11 5898 // ENUMs: 5899 // TOGGLE Toggle 5900 // NOEFF No effect 5901 #define GPIO_DOETGL31_0_DIO11 0x00000800U 5902 #define GPIO_DOETGL31_0_DIO11_M 0x00000800U 5903 #define GPIO_DOETGL31_0_DIO11_S 11U 5904 #define GPIO_DOETGL31_0_DIO11_TOGGLE 0x00000800U 5905 #define GPIO_DOETGL31_0_DIO11_NOEFF 0x00000000U 5906 5907 // Field: [10] DIO10 5908 // 5909 // Toggles bit DOE31_0.DIO10 5910 // ENUMs: 5911 // TOGGLE Toggle 5912 // NOEFF No effect 5913 #define GPIO_DOETGL31_0_DIO10 0x00000400U 5914 #define GPIO_DOETGL31_0_DIO10_M 0x00000400U 5915 #define GPIO_DOETGL31_0_DIO10_S 10U 5916 #define GPIO_DOETGL31_0_DIO10_TOGGLE 0x00000400U 5917 #define GPIO_DOETGL31_0_DIO10_NOEFF 0x00000000U 5918 5919 // Field: [9] DIO9 5920 // 5921 // Toggles bit DOE31_0.DIO9 5922 // ENUMs: 5923 // TOGGLE Toggle 5924 // NOEFF No effect 5925 #define GPIO_DOETGL31_0_DIO9 0x00000200U 5926 #define GPIO_DOETGL31_0_DIO9_M 0x00000200U 5927 #define GPIO_DOETGL31_0_DIO9_S 9U 5928 #define GPIO_DOETGL31_0_DIO9_TOGGLE 0x00000200U 5929 #define GPIO_DOETGL31_0_DIO9_NOEFF 0x00000000U 5930 5931 // Field: [8] DIO8 5932 // 5933 // Toggles bit DOE31_0.DIO8 5934 // ENUMs: 5935 // TOGGLE Toggle 5936 // NOEFF No effect 5937 #define GPIO_DOETGL31_0_DIO8 0x00000100U 5938 #define GPIO_DOETGL31_0_DIO8_M 0x00000100U 5939 #define GPIO_DOETGL31_0_DIO8_S 8U 5940 #define GPIO_DOETGL31_0_DIO8_TOGGLE 0x00000100U 5941 #define GPIO_DOETGL31_0_DIO8_NOEFF 0x00000000U 5942 5943 // Field: [7] DIO7 5944 // 5945 // Toggles bit DOE31_0.DIO7 5946 // ENUMs: 5947 // TOGGLE Toggle 5948 // NOEFF No effect 5949 #define GPIO_DOETGL31_0_DIO7 0x00000080U 5950 #define GPIO_DOETGL31_0_DIO7_M 0x00000080U 5951 #define GPIO_DOETGL31_0_DIO7_S 7U 5952 #define GPIO_DOETGL31_0_DIO7_TOGGLE 0x00000080U 5953 #define GPIO_DOETGL31_0_DIO7_NOEFF 0x00000000U 5954 5955 // Field: [6] DIO6 5956 // 5957 // Toggles bit DOE31_0.DIO6 5958 // ENUMs: 5959 // TOGGLE Toggle 5960 // NOEFF No effect 5961 #define GPIO_DOETGL31_0_DIO6 0x00000040U 5962 #define GPIO_DOETGL31_0_DIO6_M 0x00000040U 5963 #define GPIO_DOETGL31_0_DIO6_S 6U 5964 #define GPIO_DOETGL31_0_DIO6_TOGGLE 0x00000040U 5965 #define GPIO_DOETGL31_0_DIO6_NOEFF 0x00000000U 5966 5967 // Field: [5] DIO5 5968 // 5969 // Toggles bit DOE31_0.DIO5 5970 // ENUMs: 5971 // TOGGLE Toggle 5972 // NOEFF No effect 5973 #define GPIO_DOETGL31_0_DIO5 0x00000020U 5974 #define GPIO_DOETGL31_0_DIO5_M 0x00000020U 5975 #define GPIO_DOETGL31_0_DIO5_S 5U 5976 #define GPIO_DOETGL31_0_DIO5_TOGGLE 0x00000020U 5977 #define GPIO_DOETGL31_0_DIO5_NOEFF 0x00000000U 5978 5979 // Field: [4] DIO4 5980 // 5981 // Toggles bit DOE31_0.DIO4 5982 // ENUMs: 5983 // TOGGLE Toggle 5984 // NOEFF No effect 5985 #define GPIO_DOETGL31_0_DIO4 0x00000010U 5986 #define GPIO_DOETGL31_0_DIO4_M 0x00000010U 5987 #define GPIO_DOETGL31_0_DIO4_S 4U 5988 #define GPIO_DOETGL31_0_DIO4_TOGGLE 0x00000010U 5989 #define GPIO_DOETGL31_0_DIO4_NOEFF 0x00000000U 5990 5991 // Field: [3] DIO3 5992 // 5993 // Toggles bit DOE31_0.DIO3 5994 // ENUMs: 5995 // TOGGLE Toggle 5996 // NOEFF No effect 5997 #define GPIO_DOETGL31_0_DIO3 0x00000008U 5998 #define GPIO_DOETGL31_0_DIO3_M 0x00000008U 5999 #define GPIO_DOETGL31_0_DIO3_S 3U 6000 #define GPIO_DOETGL31_0_DIO3_TOGGLE 0x00000008U 6001 #define GPIO_DOETGL31_0_DIO3_NOEFF 0x00000000U 6002 6003 // Field: [2] DIO2 6004 // 6005 // Toggles bit DOE31_0.DIO2 6006 // ENUMs: 6007 // TOGGLE Toggle 6008 // NOEFF No effect 6009 #define GPIO_DOETGL31_0_DIO2 0x00000004U 6010 #define GPIO_DOETGL31_0_DIO2_M 0x00000004U 6011 #define GPIO_DOETGL31_0_DIO2_S 2U 6012 #define GPIO_DOETGL31_0_DIO2_TOGGLE 0x00000004U 6013 #define GPIO_DOETGL31_0_DIO2_NOEFF 0x00000000U 6014 6015 // Field: [1] DIO1 6016 // 6017 // Toggles bit DOE31_0.DIO1 6018 // ENUMs: 6019 // TOGGLE Toggle 6020 // NOEFF No effect 6021 #define GPIO_DOETGL31_0_DIO1 0x00000002U 6022 #define GPIO_DOETGL31_0_DIO1_M 0x00000002U 6023 #define GPIO_DOETGL31_0_DIO1_S 1U 6024 #define GPIO_DOETGL31_0_DIO1_TOGGLE 0x00000002U 6025 #define GPIO_DOETGL31_0_DIO1_NOEFF 0x00000000U 6026 6027 // Field: [0] DIO0 6028 // 6029 // Toggles bit DOE31_0.DIO0 6030 // ENUMs: 6031 // TOGGLE Toggle 6032 // NOEFF No effect 6033 #define GPIO_DOETGL31_0_DIO0 0x00000001U 6034 #define GPIO_DOETGL31_0_DIO0_M 0x00000001U 6035 #define GPIO_DOETGL31_0_DIO0_S 0U 6036 #define GPIO_DOETGL31_0_DIO0_TOGGLE 0x00000001U 6037 #define GPIO_DOETGL31_0_DIO0_NOEFF 0x00000000U 6038 6039 //***************************************************************************** 6040 // 6041 // Register: GPIO_O_DIN3_0 6042 // 6043 //***************************************************************************** 6044 // Field: [24] DIO3 6045 // 6046 // Data input from DIO3 6047 // ENUMs: 6048 // ONE Input value is 1 6049 // ZERO Input value is 0 6050 #define GPIO_DIN3_0_DIO3 0x01000000U 6051 #define GPIO_DIN3_0_DIO3_M 0x01000000U 6052 #define GPIO_DIN3_0_DIO3_S 24U 6053 #define GPIO_DIN3_0_DIO3_ONE 0x01000000U 6054 #define GPIO_DIN3_0_DIO3_ZERO 0x00000000U 6055 6056 // Field: [16] DIO2 6057 // 6058 // Data input from DIO2 6059 // ENUMs: 6060 // ONE Input value is 1 6061 // ZERO Input value is 0 6062 #define GPIO_DIN3_0_DIO2 0x00010000U 6063 #define GPIO_DIN3_0_DIO2_M 0x00010000U 6064 #define GPIO_DIN3_0_DIO2_S 16U 6065 #define GPIO_DIN3_0_DIO2_ONE 0x00010000U 6066 #define GPIO_DIN3_0_DIO2_ZERO 0x00000000U 6067 6068 // Field: [8] DIO1 6069 // 6070 // Data input from DIO1 6071 // ENUMs: 6072 // ONE Input value is 1 6073 // ZERO Input value is 0 6074 #define GPIO_DIN3_0_DIO1 0x00000100U 6075 #define GPIO_DIN3_0_DIO1_M 0x00000100U 6076 #define GPIO_DIN3_0_DIO1_S 8U 6077 #define GPIO_DIN3_0_DIO1_ONE 0x00000100U 6078 #define GPIO_DIN3_0_DIO1_ZERO 0x00000000U 6079 6080 // Field: [0] DIO0 6081 // 6082 // Data input from DIO0 6083 // ENUMs: 6084 // ONE Input value is 1 6085 // ZERO Input value is 0 6086 #define GPIO_DIN3_0_DIO0 0x00000001U 6087 #define GPIO_DIN3_0_DIO0_M 0x00000001U 6088 #define GPIO_DIN3_0_DIO0_S 0U 6089 #define GPIO_DIN3_0_DIO0_ONE 0x00000001U 6090 #define GPIO_DIN3_0_DIO0_ZERO 0x00000000U 6091 6092 //***************************************************************************** 6093 // 6094 // Register: GPIO_O_DIN7_4 6095 // 6096 //***************************************************************************** 6097 // Field: [24] DIO7 6098 // 6099 // Data input from DIO7 6100 // ENUMs: 6101 // ONE Input value is 1 6102 // ZERO Input value is 0 6103 #define GPIO_DIN7_4_DIO7 0x01000000U 6104 #define GPIO_DIN7_4_DIO7_M 0x01000000U 6105 #define GPIO_DIN7_4_DIO7_S 24U 6106 #define GPIO_DIN7_4_DIO7_ONE 0x01000000U 6107 #define GPIO_DIN7_4_DIO7_ZERO 0x00000000U 6108 6109 // Field: [16] DIO6 6110 // 6111 // Data input from DIO6 6112 // ENUMs: 6113 // ONE Input value is 1 6114 // ZERO Input value is 0 6115 #define GPIO_DIN7_4_DIO6 0x00010000U 6116 #define GPIO_DIN7_4_DIO6_M 0x00010000U 6117 #define GPIO_DIN7_4_DIO6_S 16U 6118 #define GPIO_DIN7_4_DIO6_ONE 0x00010000U 6119 #define GPIO_DIN7_4_DIO6_ZERO 0x00000000U 6120 6121 // Field: [8] DIO5 6122 // 6123 // Data input from DIO5 6124 // ENUMs: 6125 // ONE Input value is 1 6126 // ZERO Input value is 0 6127 #define GPIO_DIN7_4_DIO5 0x00000100U 6128 #define GPIO_DIN7_4_DIO5_M 0x00000100U 6129 #define GPIO_DIN7_4_DIO5_S 8U 6130 #define GPIO_DIN7_4_DIO5_ONE 0x00000100U 6131 #define GPIO_DIN7_4_DIO5_ZERO 0x00000000U 6132 6133 // Field: [0] DIO4 6134 // 6135 // Data input from DIO4 6136 // ENUMs: 6137 // ONE Input value is 1 6138 // ZERO Input value is 0 6139 #define GPIO_DIN7_4_DIO4 0x00000001U 6140 #define GPIO_DIN7_4_DIO4_M 0x00000001U 6141 #define GPIO_DIN7_4_DIO4_S 0U 6142 #define GPIO_DIN7_4_DIO4_ONE 0x00000001U 6143 #define GPIO_DIN7_4_DIO4_ZERO 0x00000000U 6144 6145 //***************************************************************************** 6146 // 6147 // Register: GPIO_O_DIN11_8 6148 // 6149 //***************************************************************************** 6150 // Field: [24] DIO11 6151 // 6152 // Data input from DIO11 6153 // ENUMs: 6154 // ONE Input value is 1 6155 // ZERO Input value is 0 6156 #define GPIO_DIN11_8_DIO11 0x01000000U 6157 #define GPIO_DIN11_8_DIO11_M 0x01000000U 6158 #define GPIO_DIN11_8_DIO11_S 24U 6159 #define GPIO_DIN11_8_DIO11_ONE 0x01000000U 6160 #define GPIO_DIN11_8_DIO11_ZERO 0x00000000U 6161 6162 // Field: [16] DIO10 6163 // 6164 // Data input from DIO10 6165 // ENUMs: 6166 // ONE Input value is 1 6167 // ZERO Input value is 0 6168 #define GPIO_DIN11_8_DIO10 0x00010000U 6169 #define GPIO_DIN11_8_DIO10_M 0x00010000U 6170 #define GPIO_DIN11_8_DIO10_S 16U 6171 #define GPIO_DIN11_8_DIO10_ONE 0x00010000U 6172 #define GPIO_DIN11_8_DIO10_ZERO 0x00000000U 6173 6174 // Field: [8] DIO9 6175 // 6176 // Data input from DIO9 6177 // ENUMs: 6178 // ONE Input value is 1 6179 // ZERO Input value is 0 6180 #define GPIO_DIN11_8_DIO9 0x00000100U 6181 #define GPIO_DIN11_8_DIO9_M 0x00000100U 6182 #define GPIO_DIN11_8_DIO9_S 8U 6183 #define GPIO_DIN11_8_DIO9_ONE 0x00000100U 6184 #define GPIO_DIN11_8_DIO9_ZERO 0x00000000U 6185 6186 // Field: [0] DIO8 6187 // 6188 // Data input from DIO8 6189 // ENUMs: 6190 // ONE Input value is 1 6191 // ZERO Input value is 0 6192 #define GPIO_DIN11_8_DIO8 0x00000001U 6193 #define GPIO_DIN11_8_DIO8_M 0x00000001U 6194 #define GPIO_DIN11_8_DIO8_S 0U 6195 #define GPIO_DIN11_8_DIO8_ONE 0x00000001U 6196 #define GPIO_DIN11_8_DIO8_ZERO 0x00000000U 6197 6198 //***************************************************************************** 6199 // 6200 // Register: GPIO_O_DIN15_12 6201 // 6202 //***************************************************************************** 6203 // Field: [24] DIO15 6204 // 6205 // Data input from DIO15 6206 // ENUMs: 6207 // ONE Input value is 1 6208 // ZERO Input value is 0 6209 #define GPIO_DIN15_12_DIO15 0x01000000U 6210 #define GPIO_DIN15_12_DIO15_M 0x01000000U 6211 #define GPIO_DIN15_12_DIO15_S 24U 6212 #define GPIO_DIN15_12_DIO15_ONE 0x01000000U 6213 #define GPIO_DIN15_12_DIO15_ZERO 0x00000000U 6214 6215 // Field: [16] DIO14 6216 // 6217 // Data input from DIO14 6218 // ENUMs: 6219 // ONE Input value is 1 6220 // ZERO Input value is 0 6221 #define GPIO_DIN15_12_DIO14 0x00010000U 6222 #define GPIO_DIN15_12_DIO14_M 0x00010000U 6223 #define GPIO_DIN15_12_DIO14_S 16U 6224 #define GPIO_DIN15_12_DIO14_ONE 0x00010000U 6225 #define GPIO_DIN15_12_DIO14_ZERO 0x00000000U 6226 6227 // Field: [8] DIO13 6228 // 6229 // Data input from DIO13 6230 // ENUMs: 6231 // ONE Input value is 1 6232 // ZERO Input value is 0 6233 #define GPIO_DIN15_12_DIO13 0x00000100U 6234 #define GPIO_DIN15_12_DIO13_M 0x00000100U 6235 #define GPIO_DIN15_12_DIO13_S 8U 6236 #define GPIO_DIN15_12_DIO13_ONE 0x00000100U 6237 #define GPIO_DIN15_12_DIO13_ZERO 0x00000000U 6238 6239 // Field: [0] DIO12 6240 // 6241 // Data input from DIO12 6242 // ENUMs: 6243 // ONE Input value is 1 6244 // ZERO Input value is 0 6245 #define GPIO_DIN15_12_DIO12 0x00000001U 6246 #define GPIO_DIN15_12_DIO12_M 0x00000001U 6247 #define GPIO_DIN15_12_DIO12_S 0U 6248 #define GPIO_DIN15_12_DIO12_ONE 0x00000001U 6249 #define GPIO_DIN15_12_DIO12_ZERO 0x00000000U 6250 6251 //***************************************************************************** 6252 // 6253 // Register: GPIO_O_DIN19_16 6254 // 6255 //***************************************************************************** 6256 // Field: [24] DIO19 6257 // 6258 // Data input from DIO19 6259 // ENUMs: 6260 // ONE Input value is 1 6261 // ZERO Input value is 0 6262 #define GPIO_DIN19_16_DIO19 0x01000000U 6263 #define GPIO_DIN19_16_DIO19_M 0x01000000U 6264 #define GPIO_DIN19_16_DIO19_S 24U 6265 #define GPIO_DIN19_16_DIO19_ONE 0x01000000U 6266 #define GPIO_DIN19_16_DIO19_ZERO 0x00000000U 6267 6268 // Field: [16] DIO18 6269 // 6270 // Data input from DIO18 6271 // ENUMs: 6272 // ONE Input value is 1 6273 // ZERO Input value is 0 6274 #define GPIO_DIN19_16_DIO18 0x00010000U 6275 #define GPIO_DIN19_16_DIO18_M 0x00010000U 6276 #define GPIO_DIN19_16_DIO18_S 16U 6277 #define GPIO_DIN19_16_DIO18_ONE 0x00010000U 6278 #define GPIO_DIN19_16_DIO18_ZERO 0x00000000U 6279 6280 // Field: [8] DIO17 6281 // 6282 // Data input from DIO17 6283 // ENUMs: 6284 // ONE Input value is 1 6285 // ZERO Input value is 0 6286 #define GPIO_DIN19_16_DIO17 0x00000100U 6287 #define GPIO_DIN19_16_DIO17_M 0x00000100U 6288 #define GPIO_DIN19_16_DIO17_S 8U 6289 #define GPIO_DIN19_16_DIO17_ONE 0x00000100U 6290 #define GPIO_DIN19_16_DIO17_ZERO 0x00000000U 6291 6292 // Field: [0] DIO16 6293 // 6294 // Data input from DIO16 6295 // ENUMs: 6296 // ONE Input value is 1 6297 // ZERO Input value is 0 6298 #define GPIO_DIN19_16_DIO16 0x00000001U 6299 #define GPIO_DIN19_16_DIO16_M 0x00000001U 6300 #define GPIO_DIN19_16_DIO16_S 0U 6301 #define GPIO_DIN19_16_DIO16_ONE 0x00000001U 6302 #define GPIO_DIN19_16_DIO16_ZERO 0x00000000U 6303 6304 //***************************************************************************** 6305 // 6306 // Register: GPIO_O_DIN23_20 6307 // 6308 //***************************************************************************** 6309 // Field: [24] DIO23 6310 // 6311 // Data input from DIO23 6312 // ENUMs: 6313 // ONE Input value is 1 6314 // ZERO Input value is 0 6315 #define GPIO_DIN23_20_DIO23 0x01000000U 6316 #define GPIO_DIN23_20_DIO23_M 0x01000000U 6317 #define GPIO_DIN23_20_DIO23_S 24U 6318 #define GPIO_DIN23_20_DIO23_ONE 0x01000000U 6319 #define GPIO_DIN23_20_DIO23_ZERO 0x00000000U 6320 6321 // Field: [16] DIO22 6322 // 6323 // Data input from DIO22 6324 // ENUMs: 6325 // ONE Input value is 1 6326 // ZERO Input value is 0 6327 #define GPIO_DIN23_20_DIO22 0x00010000U 6328 #define GPIO_DIN23_20_DIO22_M 0x00010000U 6329 #define GPIO_DIN23_20_DIO22_S 16U 6330 #define GPIO_DIN23_20_DIO22_ONE 0x00010000U 6331 #define GPIO_DIN23_20_DIO22_ZERO 0x00000000U 6332 6333 // Field: [8] DIO21 6334 // 6335 // Data input from DIO21 6336 // ENUMs: 6337 // ONE Input value is 1 6338 // ZERO Input value is 0 6339 #define GPIO_DIN23_20_DIO21 0x00000100U 6340 #define GPIO_DIN23_20_DIO21_M 0x00000100U 6341 #define GPIO_DIN23_20_DIO21_S 8U 6342 #define GPIO_DIN23_20_DIO21_ONE 0x00000100U 6343 #define GPIO_DIN23_20_DIO21_ZERO 0x00000000U 6344 6345 // Field: [0] DIO20 6346 // 6347 // Data input from DIO20 6348 // ENUMs: 6349 // ONE Input value is 1 6350 // ZERO Input value is 0 6351 #define GPIO_DIN23_20_DIO20 0x00000001U 6352 #define GPIO_DIN23_20_DIO20_M 0x00000001U 6353 #define GPIO_DIN23_20_DIO20_S 0U 6354 #define GPIO_DIN23_20_DIO20_ONE 0x00000001U 6355 #define GPIO_DIN23_20_DIO20_ZERO 0x00000000U 6356 6357 //***************************************************************************** 6358 // 6359 // Register: GPIO_O_DIN27_24 6360 // 6361 //***************************************************************************** 6362 // Field: [8] DIO25 6363 // 6364 // Data input from DIO25 6365 // ENUMs: 6366 // ONE Input value is 1 6367 // ZERO Input value is 0 6368 #define GPIO_DIN27_24_DIO25 0x00000100U 6369 #define GPIO_DIN27_24_DIO25_M 0x00000100U 6370 #define GPIO_DIN27_24_DIO25_S 8U 6371 #define GPIO_DIN27_24_DIO25_ONE 0x00000100U 6372 #define GPIO_DIN27_24_DIO25_ZERO 0x00000000U 6373 6374 // Field: [0] DIO24 6375 // 6376 // Data input from DIO24 6377 // ENUMs: 6378 // ONE Input value is 1 6379 // ZERO Input value is 0 6380 #define GPIO_DIN27_24_DIO24 0x00000001U 6381 #define GPIO_DIN27_24_DIO24_M 0x00000001U 6382 #define GPIO_DIN27_24_DIO24_S 0U 6383 #define GPIO_DIN27_24_DIO24_ONE 0x00000001U 6384 #define GPIO_DIN27_24_DIO24_ZERO 0x00000000U 6385 6386 //***************************************************************************** 6387 // 6388 // Register: GPIO_O_DIN31_0 6389 // 6390 //***************************************************************************** 6391 // Field: [25] DIO25 6392 // 6393 // Data input from DIO25 6394 // ENUMs: 6395 // ONE Input value is 1 6396 // ZERO Input value is 0 6397 #define GPIO_DIN31_0_DIO25 0x02000000U 6398 #define GPIO_DIN31_0_DIO25_M 0x02000000U 6399 #define GPIO_DIN31_0_DIO25_S 25U 6400 #define GPIO_DIN31_0_DIO25_ONE 0x02000000U 6401 #define GPIO_DIN31_0_DIO25_ZERO 0x00000000U 6402 6403 // Field: [24] DIO24 6404 // 6405 // Data input from DIO24 6406 // ENUMs: 6407 // ONE Input value is 1 6408 // ZERO Input value is 0 6409 #define GPIO_DIN31_0_DIO24 0x01000000U 6410 #define GPIO_DIN31_0_DIO24_M 0x01000000U 6411 #define GPIO_DIN31_0_DIO24_S 24U 6412 #define GPIO_DIN31_0_DIO24_ONE 0x01000000U 6413 #define GPIO_DIN31_0_DIO24_ZERO 0x00000000U 6414 6415 // Field: [23] DIO23 6416 // 6417 // Data input from DIO23 6418 // ENUMs: 6419 // ONE Input value is 1 6420 // ZERO Input value is 0 6421 #define GPIO_DIN31_0_DIO23 0x00800000U 6422 #define GPIO_DIN31_0_DIO23_M 0x00800000U 6423 #define GPIO_DIN31_0_DIO23_S 23U 6424 #define GPIO_DIN31_0_DIO23_ONE 0x00800000U 6425 #define GPIO_DIN31_0_DIO23_ZERO 0x00000000U 6426 6427 // Field: [22] DIO22 6428 // 6429 // Data input from DIO22 6430 // ENUMs: 6431 // ONE Input value is 1 6432 // ZERO Input value is 0 6433 #define GPIO_DIN31_0_DIO22 0x00400000U 6434 #define GPIO_DIN31_0_DIO22_M 0x00400000U 6435 #define GPIO_DIN31_0_DIO22_S 22U 6436 #define GPIO_DIN31_0_DIO22_ONE 0x00400000U 6437 #define GPIO_DIN31_0_DIO22_ZERO 0x00000000U 6438 6439 // Field: [21] DIO21 6440 // 6441 // Data input from DIO21 6442 // ENUMs: 6443 // ONE Input value is 1 6444 // ZERO Input value is 0 6445 #define GPIO_DIN31_0_DIO21 0x00200000U 6446 #define GPIO_DIN31_0_DIO21_M 0x00200000U 6447 #define GPIO_DIN31_0_DIO21_S 21U 6448 #define GPIO_DIN31_0_DIO21_ONE 0x00200000U 6449 #define GPIO_DIN31_0_DIO21_ZERO 0x00000000U 6450 6451 // Field: [20] DIO20 6452 // 6453 // Data input from DIO20 6454 // ENUMs: 6455 // ONE Input value is 1 6456 // ZERO Input value is 0 6457 #define GPIO_DIN31_0_DIO20 0x00100000U 6458 #define GPIO_DIN31_0_DIO20_M 0x00100000U 6459 #define GPIO_DIN31_0_DIO20_S 20U 6460 #define GPIO_DIN31_0_DIO20_ONE 0x00100000U 6461 #define GPIO_DIN31_0_DIO20_ZERO 0x00000000U 6462 6463 // Field: [19] DIO19 6464 // 6465 // Data input from DIO19 6466 // ENUMs: 6467 // ONE Input value is 1 6468 // ZERO Input value is 0 6469 #define GPIO_DIN31_0_DIO19 0x00080000U 6470 #define GPIO_DIN31_0_DIO19_M 0x00080000U 6471 #define GPIO_DIN31_0_DIO19_S 19U 6472 #define GPIO_DIN31_0_DIO19_ONE 0x00080000U 6473 #define GPIO_DIN31_0_DIO19_ZERO 0x00000000U 6474 6475 // Field: [18] DIO18 6476 // 6477 // Data input from DIO18 6478 // ENUMs: 6479 // ONE Input value is 1 6480 // ZERO Input value is 0 6481 #define GPIO_DIN31_0_DIO18 0x00040000U 6482 #define GPIO_DIN31_0_DIO18_M 0x00040000U 6483 #define GPIO_DIN31_0_DIO18_S 18U 6484 #define GPIO_DIN31_0_DIO18_ONE 0x00040000U 6485 #define GPIO_DIN31_0_DIO18_ZERO 0x00000000U 6486 6487 // Field: [17] DIO17 6488 // 6489 // Data input from DIO17 6490 // ENUMs: 6491 // ONE Input value is 1 6492 // ZERO Input value is 0 6493 #define GPIO_DIN31_0_DIO17 0x00020000U 6494 #define GPIO_DIN31_0_DIO17_M 0x00020000U 6495 #define GPIO_DIN31_0_DIO17_S 17U 6496 #define GPIO_DIN31_0_DIO17_ONE 0x00020000U 6497 #define GPIO_DIN31_0_DIO17_ZERO 0x00000000U 6498 6499 // Field: [16] DIO16 6500 // 6501 // Data input from DIO16 6502 // ENUMs: 6503 // ONE Input value is 1 6504 // ZERO Input value is 0 6505 #define GPIO_DIN31_0_DIO16 0x00010000U 6506 #define GPIO_DIN31_0_DIO16_M 0x00010000U 6507 #define GPIO_DIN31_0_DIO16_S 16U 6508 #define GPIO_DIN31_0_DIO16_ONE 0x00010000U 6509 #define GPIO_DIN31_0_DIO16_ZERO 0x00000000U 6510 6511 // Field: [15] DIO15 6512 // 6513 // Data input from DIO15 6514 // ENUMs: 6515 // ONE Input value is 1 6516 // ZERO Input value is 0 6517 #define GPIO_DIN31_0_DIO15 0x00008000U 6518 #define GPIO_DIN31_0_DIO15_M 0x00008000U 6519 #define GPIO_DIN31_0_DIO15_S 15U 6520 #define GPIO_DIN31_0_DIO15_ONE 0x00008000U 6521 #define GPIO_DIN31_0_DIO15_ZERO 0x00000000U 6522 6523 // Field: [14] DIO14 6524 // 6525 // Data input from DIO14 6526 // ENUMs: 6527 // ONE Input value is 1 6528 // ZERO Input value is 0 6529 #define GPIO_DIN31_0_DIO14 0x00004000U 6530 #define GPIO_DIN31_0_DIO14_M 0x00004000U 6531 #define GPIO_DIN31_0_DIO14_S 14U 6532 #define GPIO_DIN31_0_DIO14_ONE 0x00004000U 6533 #define GPIO_DIN31_0_DIO14_ZERO 0x00000000U 6534 6535 // Field: [13] DIO13 6536 // 6537 // Data input from DIO13 6538 // ENUMs: 6539 // ONE Input value is 1 6540 // ZERO Input value is 0 6541 #define GPIO_DIN31_0_DIO13 0x00002000U 6542 #define GPIO_DIN31_0_DIO13_M 0x00002000U 6543 #define GPIO_DIN31_0_DIO13_S 13U 6544 #define GPIO_DIN31_0_DIO13_ONE 0x00002000U 6545 #define GPIO_DIN31_0_DIO13_ZERO 0x00000000U 6546 6547 // Field: [12] DIO12 6548 // 6549 // Data input from DIO12 6550 // ENUMs: 6551 // ONE Input value is 1 6552 // ZERO Input value is 0 6553 #define GPIO_DIN31_0_DIO12 0x00001000U 6554 #define GPIO_DIN31_0_DIO12_M 0x00001000U 6555 #define GPIO_DIN31_0_DIO12_S 12U 6556 #define GPIO_DIN31_0_DIO12_ONE 0x00001000U 6557 #define GPIO_DIN31_0_DIO12_ZERO 0x00000000U 6558 6559 // Field: [11] DIO11 6560 // 6561 // Data input from DIO11 6562 // ENUMs: 6563 // ONE Input value is 1 6564 // ZERO Input value is 0 6565 #define GPIO_DIN31_0_DIO11 0x00000800U 6566 #define GPIO_DIN31_0_DIO11_M 0x00000800U 6567 #define GPIO_DIN31_0_DIO11_S 11U 6568 #define GPIO_DIN31_0_DIO11_ONE 0x00000800U 6569 #define GPIO_DIN31_0_DIO11_ZERO 0x00000000U 6570 6571 // Field: [10] DIO10 6572 // 6573 // Data input from DIO10 6574 // ENUMs: 6575 // ONE Input value is 1 6576 // ZERO Input value is 0 6577 #define GPIO_DIN31_0_DIO10 0x00000400U 6578 #define GPIO_DIN31_0_DIO10_M 0x00000400U 6579 #define GPIO_DIN31_0_DIO10_S 10U 6580 #define GPIO_DIN31_0_DIO10_ONE 0x00000400U 6581 #define GPIO_DIN31_0_DIO10_ZERO 0x00000000U 6582 6583 // Field: [9] DIO9 6584 // 6585 // Data input from DIO9 6586 // ENUMs: 6587 // ONE Input value is 1 6588 // ZERO Input value is 0 6589 #define GPIO_DIN31_0_DIO9 0x00000200U 6590 #define GPIO_DIN31_0_DIO9_M 0x00000200U 6591 #define GPIO_DIN31_0_DIO9_S 9U 6592 #define GPIO_DIN31_0_DIO9_ONE 0x00000200U 6593 #define GPIO_DIN31_0_DIO9_ZERO 0x00000000U 6594 6595 // Field: [8] DIO8 6596 // 6597 // Data input from DIO8 6598 // ENUMs: 6599 // ONE Input value is 1 6600 // ZERO Input value is 0 6601 #define GPIO_DIN31_0_DIO8 0x00000100U 6602 #define GPIO_DIN31_0_DIO8_M 0x00000100U 6603 #define GPIO_DIN31_0_DIO8_S 8U 6604 #define GPIO_DIN31_0_DIO8_ONE 0x00000100U 6605 #define GPIO_DIN31_0_DIO8_ZERO 0x00000000U 6606 6607 // Field: [7] DIO7 6608 // 6609 // Data input from DIO7 6610 // ENUMs: 6611 // ONE Input value is 1 6612 // ZERO Input value is 0 6613 #define GPIO_DIN31_0_DIO7 0x00000080U 6614 #define GPIO_DIN31_0_DIO7_M 0x00000080U 6615 #define GPIO_DIN31_0_DIO7_S 7U 6616 #define GPIO_DIN31_0_DIO7_ONE 0x00000080U 6617 #define GPIO_DIN31_0_DIO7_ZERO 0x00000000U 6618 6619 // Field: [6] DIO6 6620 // 6621 // Data input from DIO6 6622 // ENUMs: 6623 // ONE Input value is 1 6624 // ZERO Input value is 0 6625 #define GPIO_DIN31_0_DIO6 0x00000040U 6626 #define GPIO_DIN31_0_DIO6_M 0x00000040U 6627 #define GPIO_DIN31_0_DIO6_S 6U 6628 #define GPIO_DIN31_0_DIO6_ONE 0x00000040U 6629 #define GPIO_DIN31_0_DIO6_ZERO 0x00000000U 6630 6631 // Field: [5] DIO5 6632 // 6633 // Data input from DIO5 6634 // ENUMs: 6635 // ONE Input value is 1 6636 // ZERO Input value is 0 6637 #define GPIO_DIN31_0_DIO5 0x00000020U 6638 #define GPIO_DIN31_0_DIO5_M 0x00000020U 6639 #define GPIO_DIN31_0_DIO5_S 5U 6640 #define GPIO_DIN31_0_DIO5_ONE 0x00000020U 6641 #define GPIO_DIN31_0_DIO5_ZERO 0x00000000U 6642 6643 // Field: [4] DIO4 6644 // 6645 // Data input from DIO4 6646 // ENUMs: 6647 // ONE Input value is 1 6648 // ZERO Input value is 0 6649 #define GPIO_DIN31_0_DIO4 0x00000010U 6650 #define GPIO_DIN31_0_DIO4_M 0x00000010U 6651 #define GPIO_DIN31_0_DIO4_S 4U 6652 #define GPIO_DIN31_0_DIO4_ONE 0x00000010U 6653 #define GPIO_DIN31_0_DIO4_ZERO 0x00000000U 6654 6655 // Field: [3] DIO3 6656 // 6657 // Data input from DIO3 6658 // ENUMs: 6659 // ONE Input value is 1 6660 // ZERO Input value is 0 6661 #define GPIO_DIN31_0_DIO3 0x00000008U 6662 #define GPIO_DIN31_0_DIO3_M 0x00000008U 6663 #define GPIO_DIN31_0_DIO3_S 3U 6664 #define GPIO_DIN31_0_DIO3_ONE 0x00000008U 6665 #define GPIO_DIN31_0_DIO3_ZERO 0x00000000U 6666 6667 // Field: [2] DIO2 6668 // 6669 // Data input from DIO2 6670 // ENUMs: 6671 // ONE Input value is 1 6672 // ZERO Input value is 0 6673 #define GPIO_DIN31_0_DIO2 0x00000004U 6674 #define GPIO_DIN31_0_DIO2_M 0x00000004U 6675 #define GPIO_DIN31_0_DIO2_S 2U 6676 #define GPIO_DIN31_0_DIO2_ONE 0x00000004U 6677 #define GPIO_DIN31_0_DIO2_ZERO 0x00000000U 6678 6679 // Field: [1] DIO1 6680 // 6681 // Data input from DIO1 6682 // ENUMs: 6683 // ONE Input value is 1 6684 // ZERO Input value is 0 6685 #define GPIO_DIN31_0_DIO1 0x00000002U 6686 #define GPIO_DIN31_0_DIO1_M 0x00000002U 6687 #define GPIO_DIN31_0_DIO1_S 1U 6688 #define GPIO_DIN31_0_DIO1_ONE 0x00000002U 6689 #define GPIO_DIN31_0_DIO1_ZERO 0x00000000U 6690 6691 // Field: [0] DIO0 6692 // 6693 // Data input from DIO0 6694 // ENUMs: 6695 // ONE Input value is 1 6696 // ZERO Input value is 0 6697 #define GPIO_DIN31_0_DIO0 0x00000001U 6698 #define GPIO_DIN31_0_DIO0_M 0x00000001U 6699 #define GPIO_DIN31_0_DIO0_S 0U 6700 #define GPIO_DIN31_0_DIO0_ONE 0x00000001U 6701 #define GPIO_DIN31_0_DIO0_ZERO 0x00000000U 6702 6703 //***************************************************************************** 6704 // 6705 // Register: GPIO_O_EVTCFG 6706 // 6707 //***************************************************************************** 6708 // Field: [8] EVTEN 6709 // 6710 // Enables GPIO to publish edge qualified selected DIO event on SVT event 6711 // fabric. 6712 // Design note: The edge detector flop is cleared automatically for the 6713 // selected DIO once the event is published. 6714 // ENUMs: 6715 // EN Enable 6716 // DIS Disable 6717 #define GPIO_EVTCFG_EVTEN 0x00000100U 6718 #define GPIO_EVTCFG_EVTEN_M 0x00000100U 6719 #define GPIO_EVTCFG_EVTEN_S 8U 6720 #define GPIO_EVTCFG_EVTEN_EN 0x00000100U 6721 #define GPIO_EVTCFG_EVTEN_DIS 0x00000000U 6722 6723 // Field: [5:0] DIOSEL 6724 // 6725 // This is used to select DIO for event generation. For example, DIOSEL = 0x0 6726 // selects DIO0 and DIOSEL = 0x8 selects DIO8. 6727 // ENUMs: 6728 // MAXIMUM Maximum value 6729 // MINIMUM Minimum value 6730 #define GPIO_EVTCFG_DIOSEL_W 6U 6731 #define GPIO_EVTCFG_DIOSEL_M 0x0000003FU 6732 #define GPIO_EVTCFG_DIOSEL_S 0U 6733 #define GPIO_EVTCFG_DIOSEL_MAXIMUM 0x0000003FU 6734 #define GPIO_EVTCFG_DIOSEL_MINIMUM 0x00000000U 6735 6736 6737 #endif // __GPIO__ 6738
