1 /****************************************************************************** 2 * Filename: hw_flash_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_FLASH_H__ 34 #define __HW_FLASH_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // FLASH component 40 // 41 //***************************************************************************** 42 // Interrupt Mask Register 43 #define FLASH_O_IMASK 0x00000028U 44 45 // Raw Interrupt Status Register 46 #define FLASH_O_RIS 0x00000030U 47 48 // Masked Interrupt Status Register 49 #define FLASH_O_MIS 0x00000038U 50 51 // Interrupt Set Register 52 #define FLASH_O_ISET 0x00000040U 53 54 // Interrupt Clear Register 55 #define FLASH_O_ICLR 0x00000048U 56 57 // Hardware Version Description Register 58 #define FLASH_O_DESC 0x000000FCU 59 60 // Command Execute Register 61 #define FLASH_O_CMDEXEC 0x00000100U 62 63 // Command Type Register 64 #define FLASH_O_CMDTYPE 0x00000104U 65 66 // Command Control Register 67 #define FLASH_O_CMDCTL 0x00000108U 68 69 // Command Address Register 70 #define FLASH_O_CMDADDR 0x00000120U 71 72 // Command Program Byte Enable Register 73 #define FLASH_O_CMDBYTEN 0x00000124U 74 75 // Command Data Register 0 76 #define FLASH_O_CMDDATA0 0x00000130U 77 78 // Command Data Register 1 79 #define FLASH_O_CMDDATA1 0x00000134U 80 81 // Command Data Register 2 82 #define FLASH_O_CMDDATA2 0x00000138U 83 84 // Command Data Register Bits 127:96 85 #define FLASH_O_CMDDATA3 0x0000013CU 86 87 // Command Write Erase Protect A Register 88 #define FLASH_O_CMDWEPROTA 0x000001D0U 89 90 // Command Write Erase Protect B Register 91 #define FLASH_O_CMDWEPROTB 0x000001D4U 92 93 // Command Write Erase Protect Non-Main Register 94 #define FLASH_O_CMDWEPROTNM 0x00000210U 95 96 // Command Write Erase Protect Trim Register 97 #define FLASH_O_CMDWEPROTTR 0x00000214U 98 99 // Command Write Erase Protect Engr Register 100 #define FLASH_O_CMDWEPROTEN 0x00000218U 101 102 // Command Configuration Register 103 #define FLASH_O_CFGCMD 0x000003B0U 104 105 // Pulse Counter Configuration Register 106 #define FLASH_O_CFGPCNT 0x000003B4U 107 108 // Command Status Register 109 #define FLASH_O_STATCMD 0x000003D0U 110 111 // Address Status Register 112 #define FLASH_O_STATADDR 0x000003D4U 113 114 // Pulse Count Status Register 115 #define FLASH_O_STATPCNT 0x000003D8U 116 117 // Mode Status Register 118 #define FLASH_O_STATMODE 0x000003DCU 119 120 // Global Information Register 0 121 #define FLASH_O_GBLINFO0 0x000003F0U 122 123 // Global Information Register 1 124 #define FLASH_O_GBLINFO1 0x000003F4U 125 126 // Global Information Register 2 127 #define FLASH_O_GBLINFO2 0x000003F8U 128 129 // Bank Information Register 0 for Bank 0 130 #define FLASH_O_BANK0INFO0 0x00000400U 131 132 // Bank Information Register 1 for Bank 0 133 #define FLASH_O_BANK0INFO1 0x00000404U 134 135 //***************************************************************************** 136 // 137 // Register: FLASH_O_IMASK 138 // 139 //***************************************************************************** 140 // Field: [0] DONE 141 // 142 // Interrupt mask for DONE: 143 // 0: Interrupt is disabled in MIS register 144 // 1: Interrupt is enabled in MIS register 145 // ENUMs: 146 // ENABLED Interrupt will request an interrupt service 147 // routine and corresponding bit in IPSTANDARD.MIS 148 // will be set 149 // DISABLED Interrupt is masked out 150 #define FLASH_IMASK_DONE 0x00000001U 151 #define FLASH_IMASK_DONE_M 0x00000001U 152 #define FLASH_IMASK_DONE_S 0U 153 #define FLASH_IMASK_DONE_ENABLED 0x00000001U 154 #define FLASH_IMASK_DONE_DISABLED 0x00000000U 155 156 //***************************************************************************** 157 // 158 // Register: FLASH_O_RIS 159 // 160 //***************************************************************************** 161 // Field: [0] DONE 162 // 163 // Flash wrapper operation completed. 164 // This interrupt bit is set by firmware or the corresponding bit in the ISET 165 // register. 166 // It is cleared by the corresponding bit in in the ICLR register or reading 167 // the IIDX register when this interrupt is the highest priority. 168 // ENUMs: 169 // SET Interrupt occurred 170 // CLR Interrupt did not occur 171 #define FLASH_RIS_DONE 0x00000001U 172 #define FLASH_RIS_DONE_M 0x00000001U 173 #define FLASH_RIS_DONE_S 0U 174 #define FLASH_RIS_DONE_SET 0x00000001U 175 #define FLASH_RIS_DONE_CLR 0x00000000U 176 177 //***************************************************************************** 178 // 179 // Register: FLASH_O_MIS 180 // 181 //***************************************************************************** 182 // Field: [0] DONE 183 // 184 // Flash wrapper operation completed. 185 // This masked interrupt bit reflects the bitwise AND of the corresponding RIS 186 // and IMASK bits. 187 // ENUMs: 188 // SET Masked interrupt occurred 189 // CLR Masked interrupt did not occur 190 #define FLASH_MIS_DONE 0x00000001U 191 #define FLASH_MIS_DONE_M 0x00000001U 192 #define FLASH_MIS_DONE_S 0U 193 #define FLASH_MIS_DONE_SET 0x00000001U 194 #define FLASH_MIS_DONE_CLR 0x00000000U 195 196 //***************************************************************************** 197 // 198 // Register: FLASH_O_ISET 199 // 200 //***************************************************************************** 201 // Field: [0] DONE 202 // 203 // 0: No effect 204 // 1: Set the DONE interrupt in the RIS register 205 // ENUMs: 206 // SET Set IPSTANDARD.RIS bit 207 // NO_EFFECT Writing a 0 has no effect 208 #define FLASH_ISET_DONE 0x00000001U 209 #define FLASH_ISET_DONE_M 0x00000001U 210 #define FLASH_ISET_DONE_S 0U 211 #define FLASH_ISET_DONE_SET 0x00000001U 212 #define FLASH_ISET_DONE_NO_EFFECT 0x00000000U 213 214 //***************************************************************************** 215 // 216 // Register: FLASH_O_ICLR 217 // 218 //***************************************************************************** 219 // Field: [0] DONE 220 // 221 // 0: No effect 222 // 1: Clear the DONE interrupt in the RIS register 223 // ENUMs: 224 // CLR Clear IPSTANDARD.RIS bit 225 // NO_EFFECT Writing a 0 has no effect 226 #define FLASH_ICLR_DONE 0x00000001U 227 #define FLASH_ICLR_DONE_M 0x00000001U 228 #define FLASH_ICLR_DONE_S 0U 229 #define FLASH_ICLR_DONE_CLR 0x00000001U 230 #define FLASH_ICLR_DONE_NO_EFFECT 0x00000000U 231 232 //***************************************************************************** 233 // 234 // Register: FLASH_O_DESC 235 // 236 //***************************************************************************** 237 // Field: [31:16] MODULEID 238 // 239 // Module ID 240 // ENUMs: 241 // MAXIMUM Highest possible value 242 // MINIMUM Smallest value 243 #define FLASH_DESC_MODULEID_W 16U 244 #define FLASH_DESC_MODULEID_M 0xFFFF0000U 245 #define FLASH_DESC_MODULEID_S 16U 246 #define FLASH_DESC_MODULEID_MAXIMUM 0xFFFF0000U 247 #define FLASH_DESC_MODULEID_MINIMUM 0x00000000U 248 249 // Field: [15:12] FEATUREVER 250 // 251 // Feature set 252 // ENUMs: 253 // MAXIMUM Maximum Value 254 // MINIMUM Minimum Value 255 #define FLASH_DESC_FEATUREVER_W 4U 256 #define FLASH_DESC_FEATUREVER_M 0x0000F000U 257 #define FLASH_DESC_FEATUREVER_S 12U 258 #define FLASH_DESC_FEATUREVER_MAXIMUM 0x0000F000U 259 #define FLASH_DESC_FEATUREVER_MINIMUM 0x00000000U 260 261 // Field: [11:8] INSTNUM 262 // 263 // Instance number 264 // ENUMs: 265 // MAXIMUM Highest possible value 266 // MINIMUM Smallest value 267 #define FLASH_DESC_INSTNUM_W 4U 268 #define FLASH_DESC_INSTNUM_M 0x00000F00U 269 #define FLASH_DESC_INSTNUM_S 8U 270 #define FLASH_DESC_INSTNUM_MAXIMUM 0x00000F00U 271 #define FLASH_DESC_INSTNUM_MINIMUM 0x00000000U 272 273 // Field: [7:4] MAJREV 274 // 275 // Major Revision 276 // ENUMs: 277 // MAXIMUM Highest possible value 278 // MINIMUM Smallest value 279 #define FLASH_DESC_MAJREV_W 4U 280 #define FLASH_DESC_MAJREV_M 0x000000F0U 281 #define FLASH_DESC_MAJREV_S 4U 282 #define FLASH_DESC_MAJREV_MAXIMUM 0x000000F0U 283 #define FLASH_DESC_MAJREV_MINIMUM 0x00000000U 284 285 // Field: [3:0] MINREV 286 // 287 // Minor Revision 288 // ENUMs: 289 // MAXIMUM Highest possible value 290 // MINIMUM Smallest value 291 #define FLASH_DESC_MINREV_W 4U 292 #define FLASH_DESC_MINREV_M 0x0000000FU 293 #define FLASH_DESC_MINREV_S 0U 294 #define FLASH_DESC_MINREV_MAXIMUM 0x0000000FU 295 #define FLASH_DESC_MINREV_MINIMUM 0x00000000U 296 297 //***************************************************************************** 298 // 299 // Register: FLASH_O_CMDEXEC 300 // 301 //***************************************************************************** 302 // Field: [0] VAL 303 // 304 // Command Execute value 305 // Initiates execution of the command specified in the CMDTYPE register. 306 // ENUMs: 307 // EXECUTE Command will execute or is executing in flash 308 // wrapper 309 // NOEXECUTE Command will not execute or is not executing in 310 // flash wrapper 311 #define FLASH_CMDEXEC_VAL 0x00000001U 312 #define FLASH_CMDEXEC_VAL_M 0x00000001U 313 #define FLASH_CMDEXEC_VAL_S 0U 314 #define FLASH_CMDEXEC_VAL_EXECUTE 0x00000001U 315 #define FLASH_CMDEXEC_VAL_NOEXECUTE 0x00000000U 316 317 //***************************************************************************** 318 // 319 // Register: FLASH_O_CMDTYPE 320 // 321 //***************************************************************************** 322 // Field: [6:4] SIZE 323 // 324 // Command size 325 // ENUMs: 326 // BANK Operate on an entire flash bank 327 // SECTOR Operate on a flash sector 328 // EIGHTWORD Operate on 8 flash words 329 // FOURWORD Operate on 4 flash words 330 // TWOWORD Operate on 2 flash words 331 // ONEWORD Operate on 1 flash word 332 #define FLASH_CMDTYPE_SIZE_W 3U 333 #define FLASH_CMDTYPE_SIZE_M 0x00000070U 334 #define FLASH_CMDTYPE_SIZE_S 4U 335 #define FLASH_CMDTYPE_SIZE_BANK 0x00000050U 336 #define FLASH_CMDTYPE_SIZE_SECTOR 0x00000040U 337 #define FLASH_CMDTYPE_SIZE_EIGHTWORD 0x00000030U 338 #define FLASH_CMDTYPE_SIZE_FOURWORD 0x00000020U 339 #define FLASH_CMDTYPE_SIZE_TWOWORD 0x00000010U 340 #define FLASH_CMDTYPE_SIZE_ONEWORD 0x00000000U 341 342 // Field: [2:0] COMMAND 343 // 344 // Command type 345 // ENUMs: 346 // BLANKVERIFY Blank Verify - Check whether a flash word is in 347 // the erased state. 348 // This command may only be 349 // used with CMDTYPE.SIZE = ONEWORD 350 // CLEARSTATUS Clear Status - Clear status bits in FW_SMSTAT 351 // only. 352 // MODECHANGE Mode Change - Perform a mode change only, no other 353 // operation. 354 // ERASE Erase 355 // PROGRAM Program 356 // NOOP No Operation 357 #define FLASH_CMDTYPE_COMMAND_W 3U 358 #define FLASH_CMDTYPE_COMMAND_M 0x00000007U 359 #define FLASH_CMDTYPE_COMMAND_S 0U 360 #define FLASH_CMDTYPE_COMMAND_BLANKVERIFY 0x00000006U 361 #define FLASH_CMDTYPE_COMMAND_CLEARSTATUS 0x00000005U 362 #define FLASH_CMDTYPE_COMMAND_MODECHANGE 0x00000004U 363 #define FLASH_CMDTYPE_COMMAND_ERASE 0x00000002U 364 #define FLASH_CMDTYPE_COMMAND_PROGRAM 0x00000001U 365 #define FLASH_CMDTYPE_COMMAND_NOOP 0x00000000U 366 367 //***************************************************************************** 368 // 369 // Register: FLASH_O_CMDCTL 370 // 371 //***************************************************************************** 372 // Field: [21] DATAVEREN 373 // 374 // Enable invalid data verify. 375 // This checks for 0->1 transitions in the memory when 376 // a program operation is initiated. If such a transition is found, the 377 // program will 378 // fail with an error without executing the program. 379 // ENUMs: 380 // ENABLE Enable 381 // DISABLE Disable 382 #define FLASH_CMDCTL_DATAVEREN 0x00200000U 383 #define FLASH_CMDCTL_DATAVEREN_M 0x00200000U 384 #define FLASH_CMDCTL_DATAVEREN_S 21U 385 #define FLASH_CMDCTL_DATAVEREN_ENABLE 0x00200000U 386 #define FLASH_CMDCTL_DATAVEREN_DISABLE 0x00000000U 387 388 // Field: [20] SSERASEDIS 389 // 390 // Disable Stair-Step Erase. If set, the default VHV trim voltage setting will 391 // be used 392 // for all erase pulses. 393 // By default, this bit is reset, meaning that the VHV voltage will be stepped 394 // during 395 // successive erase pulses. The step count, step voltage, begin and end 396 // voltages 397 // are all hard-wired. 398 // ENUMs: 399 // DISABLE Disable 400 // ENABLE Enable 401 #define FLASH_CMDCTL_SSERASEDIS 0x00100000U 402 #define FLASH_CMDCTL_SSERASEDIS_M 0x00100000U 403 #define FLASH_CMDCTL_SSERASEDIS_S 20U 404 #define FLASH_CMDCTL_SSERASEDIS_DISABLE 0x00100000U 405 #define FLASH_CMDCTL_SSERASEDIS_ENABLE 0x00000000U 406 407 // Field: [16] ADDRXLATEOVR 408 // 409 // Override hardware address translation of address in CMDADDR from a 410 // system address to a bank address and bank ID. Use data written to 411 // CMDADDR directly as the bank address. Use the value written to 412 // CMDCTL.BANKSEL directly as the bank ID. Use the value written to 413 // CMDCTL.REGIONSEL directly as the region ID. 414 // ENUMs: 415 // OVERRIDE Override 416 // NOOVERRIDE Do not override 417 #define FLASH_CMDCTL_ADDRXLATEOVR 0x00010000U 418 #define FLASH_CMDCTL_ADDRXLATEOVR_M 0x00010000U 419 #define FLASH_CMDCTL_ADDRXLATEOVR_S 16U 420 #define FLASH_CMDCTL_ADDRXLATEOVR_OVERRIDE 0x00010000U 421 #define FLASH_CMDCTL_ADDRXLATEOVR_NOOVERRIDE 0x00000000U 422 423 // Field: [12:9] REGIONSEL 424 // 425 // Bank Region 426 // A specific region ID can be written to this field to indicate to which 427 // region an 428 // operation is to be applied if CMDCTL.ADDRXLATEOVR is set. 429 // ENUMs: 430 // ENGR Engr Region 431 // TRIM Trim Region 432 // NONMAIN Non-Main Region 433 // MAIN Main Region 434 #define FLASH_CMDCTL_REGIONSEL_W 4U 435 #define FLASH_CMDCTL_REGIONSEL_M 0x00001E00U 436 #define FLASH_CMDCTL_REGIONSEL_S 9U 437 #define FLASH_CMDCTL_REGIONSEL_ENGR 0x00001000U 438 #define FLASH_CMDCTL_REGIONSEL_TRIM 0x00000800U 439 #define FLASH_CMDCTL_REGIONSEL_NONMAIN 0x00000400U 440 #define FLASH_CMDCTL_REGIONSEL_MAIN 0x00000200U 441 442 // Field: [3:0] MODESEL 443 // 444 // Mode 445 // This field is only used for the Mode Change command type. Otherwise, bank 446 // and pump modes are set automaticlly through the NW hardware. 447 // ENUMs: 448 // ERASEBNK Erase Bank 449 // PGMMW Program Multiple Word 450 // ERASESECT Erase Sector 451 // ERASEVER Erase Verify Mode 452 // PGMSW Program Single Word 453 // PGMVER Program Verify Mode 454 // RDMARG1B Read Margin 1B Mode 455 // RDMARG0B Read Margin 0B Mode 456 // RDMARG1 Read Margin 1 Mode 457 // RDMARG0 Read Margin 0 Mode 458 // READ Read Mode 459 #define FLASH_CMDCTL_MODESEL_W 4U 460 #define FLASH_CMDCTL_MODESEL_M 0x0000000FU 461 #define FLASH_CMDCTL_MODESEL_S 0U 462 #define FLASH_CMDCTL_MODESEL_ERASEBNK 0x0000000FU 463 #define FLASH_CMDCTL_MODESEL_PGMMW 0x0000000EU 464 #define FLASH_CMDCTL_MODESEL_ERASESECT 0x0000000CU 465 #define FLASH_CMDCTL_MODESEL_ERASEVER 0x0000000BU 466 #define FLASH_CMDCTL_MODESEL_PGMSW 0x0000000AU 467 #define FLASH_CMDCTL_MODESEL_PGMVER 0x00000009U 468 #define FLASH_CMDCTL_MODESEL_RDMARG1B 0x00000007U 469 #define FLASH_CMDCTL_MODESEL_RDMARG0B 0x00000006U 470 #define FLASH_CMDCTL_MODESEL_RDMARG1 0x00000004U 471 #define FLASH_CMDCTL_MODESEL_RDMARG0 0x00000002U 472 #define FLASH_CMDCTL_MODESEL_READ 0x00000000U 473 474 //***************************************************************************** 475 // 476 // Register: FLASH_O_CMDADDR 477 // 478 //***************************************************************************** 479 // Field: [31:0] VAL 480 // 481 // Address value 482 // ENUMs: 483 // MAXIMUM Maximum value of VAL 484 // MINIMUM Minimum value of VAL 485 #define FLASH_CMDADDR_VAL_W 32U 486 #define FLASH_CMDADDR_VAL_M 0xFFFFFFFFU 487 #define FLASH_CMDADDR_VAL_S 0U 488 #define FLASH_CMDADDR_VAL_MAXIMUM 0xFFFFFFFFU 489 #define FLASH_CMDADDR_VAL_MINIMUM 0x00000000U 490 491 //***************************************************************************** 492 // 493 // Register: FLASH_O_CMDBYTEN 494 // 495 //***************************************************************************** 496 // Field: [15:0] VAL 497 // 498 // Command Byte Enable value. 499 // A 1-bit per flash word byte value is placed in this register. 500 // ENUMs: 501 // MAXIMUM Maximum value of VAL 502 // MINIMUM Minimum value of VAL 503 #define FLASH_CMDBYTEN_VAL_W 16U 504 #define FLASH_CMDBYTEN_VAL_M 0x0000FFFFU 505 #define FLASH_CMDBYTEN_VAL_S 0U 506 #define FLASH_CMDBYTEN_VAL_MAXIMUM 0x0003FFFFU 507 #define FLASH_CMDBYTEN_VAL_MINIMUM 0x00000000U 508 509 //***************************************************************************** 510 // 511 // Register: FLASH_O_CMDDATA0 512 // 513 //***************************************************************************** 514 // Field: [31:0] VAL 515 // 516 // A 32-bit data value is placed in this field. 517 // ENUMs: 518 // MAXIMUM Maximum value of VAL 519 // MINIMUM Minimum value of VAL 520 #define FLASH_CMDDATA0_VAL_W 32U 521 #define FLASH_CMDDATA0_VAL_M 0xFFFFFFFFU 522 #define FLASH_CMDDATA0_VAL_S 0U 523 #define FLASH_CMDDATA0_VAL_MAXIMUM 0xFFFFFFFFU 524 #define FLASH_CMDDATA0_VAL_MINIMUM 0x00000000U 525 526 //***************************************************************************** 527 // 528 // Register: FLASH_O_CMDDATA1 529 // 530 //***************************************************************************** 531 // Field: [31:0] VAL 532 // 533 // A 32-bit data value is placed in this field. 534 // ENUMs: 535 // MAXIMUM Maximum value of VAL 536 // MINIMUM Minimum value of VAL 537 #define FLASH_CMDDATA1_VAL_W 32U 538 #define FLASH_CMDDATA1_VAL_M 0xFFFFFFFFU 539 #define FLASH_CMDDATA1_VAL_S 0U 540 #define FLASH_CMDDATA1_VAL_MAXIMUM 0xFFFFFFFFU 541 #define FLASH_CMDDATA1_VAL_MINIMUM 0x00000000U 542 543 //***************************************************************************** 544 // 545 // Register: FLASH_O_CMDDATA2 546 // 547 //***************************************************************************** 548 // Field: [31:0] VAL 549 // 550 // A 32-bit data value is placed in this field. 551 // ENUMs: 552 // MAXIMUM Maximum value of VAL 553 // MINIMUM Minimum value of VAL 554 #define FLASH_CMDDATA2_VAL_W 32U 555 #define FLASH_CMDDATA2_VAL_M 0xFFFFFFFFU 556 #define FLASH_CMDDATA2_VAL_S 0U 557 #define FLASH_CMDDATA2_VAL_MAXIMUM 0xFFFFFFFFU 558 #define FLASH_CMDDATA2_VAL_MINIMUM 0x00000000U 559 560 //***************************************************************************** 561 // 562 // Register: FLASH_O_CMDDATA3 563 // 564 //***************************************************************************** 565 // Field: [31:0] VAL 566 // 567 // A 32-bit data value is placed in this field. 568 // ENUMs: 569 // MAXIMUM Maximum value of VAL 570 // MINIMUM Minimum value of VAL 571 #define FLASH_CMDDATA3_VAL_W 32U 572 #define FLASH_CMDDATA3_VAL_M 0xFFFFFFFFU 573 #define FLASH_CMDDATA3_VAL_S 0U 574 #define FLASH_CMDDATA3_VAL_MAXIMUM 0xFFFFFFFFU 575 #define FLASH_CMDDATA3_VAL_MINIMUM 0x00000000U 576 577 //***************************************************************************** 578 // 579 // Register: FLASH_O_CMDWEPROTA 580 // 581 //***************************************************************************** 582 // Field: [31:0] VAL 583 // 584 // Each bit protects 1 sector. 585 // 586 // bit [0]: When 1, sector 0 of the flash memory will be protected from program 587 // and erase. 588 // bit [1]: When 1, sector 1 of the flash memory will be protected from program 589 // and erase. 590 // : 591 // : 592 // bit [31]: When 1, sector 31 of the flash memory will be protected from 593 // program 594 // and erase. 595 // ENUMs: 596 // MAXIMUM Maximum value of VAL 597 // MINIMUM Minimum value of VAL 598 #define FLASH_CMDWEPROTA_VAL_W 32U 599 #define FLASH_CMDWEPROTA_VAL_M 0xFFFFFFFFU 600 #define FLASH_CMDWEPROTA_VAL_S 0U 601 #define FLASH_CMDWEPROTA_VAL_MAXIMUM 0xFFFFFFFFU 602 #define FLASH_CMDWEPROTA_VAL_MINIMUM 0x00000000U 603 604 //***************************************************************************** 605 // 606 // Register: FLASH_O_CMDWEPROTB 607 // 608 //***************************************************************************** 609 // Field: [27:0] VAL 610 // 611 // Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 612 // sectors 613 // in the flash will be protected from program and erase. A maximum of 256 614 // sectors can be protected with this register. 615 // ENUMs: 616 // MAXIMUM Maximum value of VAL 617 // MINIMUM Minimum value of VAL 618 #define FLASH_CMDWEPROTB_VAL_W 28U 619 #define FLASH_CMDWEPROTB_VAL_M 0x0FFFFFFFU 620 #define FLASH_CMDWEPROTB_VAL_S 0U 621 #define FLASH_CMDWEPROTB_VAL_MAXIMUM 0xFFFFFFFFU 622 #define FLASH_CMDWEPROTB_VAL_MINIMUM 0x00000000U 623 624 //***************************************************************************** 625 // 626 // Register: FLASH_O_CMDWEPROTNM 627 // 628 //***************************************************************************** 629 // Field: [0] VAL 630 // 631 // Each bit protects 1 sector. 632 // 633 // bit [0]: When 1, sector 0 of the non-main region will be protected from 634 // program 635 // and erase. 636 // bit [1]: When 1, sector 1 of the non-main region will be protected from 637 // program 638 // and erase. 639 // : 640 // : 641 // bit [31]: When 1, sector 31 of the non-main will be protected from program 642 // and erase. 643 // ENUMs: 644 // MAXIMUM Maximum value of VAL 645 // MINIMUM Minimum value of VAL 646 #define FLASH_CMDWEPROTNM_VAL 0x00000001U 647 #define FLASH_CMDWEPROTNM_VAL_M 0x00000001U 648 #define FLASH_CMDWEPROTNM_VAL_S 0U 649 #define FLASH_CMDWEPROTNM_VAL_MAXIMUM 0xFFFFFFFFU 650 #define FLASH_CMDWEPROTNM_VAL_MINIMUM 0x00000000U 651 652 //***************************************************************************** 653 // 654 // Register: FLASH_O_CMDWEPROTTR 655 // 656 //***************************************************************************** 657 // Field: [0] VAL 658 // 659 // Each bit protects 1 sector. 660 // 661 // bit [0]: When 1, sector 0 of the engr region will be protected from program 662 // and erase. 663 // bit [1]: When 1, sector 1 of the engr region will be protected from program 664 // and erase. 665 // : 666 // : 667 // bit [31]: When 1, sector 31 of the engr region will be protected from 668 // program 669 // and erase. 670 // ENUMs: 671 // MAXIMUM Maximum value of VAL 672 // MINIMUM Minimum value of VAL 673 #define FLASH_CMDWEPROTTR_VAL 0x00000001U 674 #define FLASH_CMDWEPROTTR_VAL_M 0x00000001U 675 #define FLASH_CMDWEPROTTR_VAL_S 0U 676 #define FLASH_CMDWEPROTTR_VAL_MAXIMUM 0xFFFFFFFFU 677 #define FLASH_CMDWEPROTTR_VAL_MINIMUM 0x00000000U 678 679 //***************************************************************************** 680 // 681 // Register: FLASH_O_CMDWEPROTEN 682 // 683 //***************************************************************************** 684 // Field: [0] VAL 685 // 686 // Each bit protects 1 sector. 687 // 688 // bit [0]: When 1, sector 0 of the engr region will be protected from program 689 // and erase. 690 // bit [1]: When 1, sector 1 of the engr region will be protected from program 691 // and erase. 692 // : 693 // : 694 // bit [31]: When 1, sector 31 of the engr region will be protected from 695 // program 696 // and erase. 697 // ENUMs: 698 // MAXIMUM Maximum value of VAL 699 // MINIMUM Minimum value of VAL 700 #define FLASH_CMDWEPROTEN_VAL 0x00000001U 701 #define FLASH_CMDWEPROTEN_VAL_M 0x00000001U 702 #define FLASH_CMDWEPROTEN_VAL_S 0U 703 #define FLASH_CMDWEPROTEN_VAL_MAXIMUM 0xFFFFFFFFU 704 #define FLASH_CMDWEPROTEN_VAL_MINIMUM 0x00000000U 705 706 //***************************************************************************** 707 // 708 // Register: FLASH_O_CFGCMD 709 // 710 //***************************************************************************** 711 // Field: [3:0] WAITSTATE 712 // 713 // Wait State setting for verify reads 714 // ENUMs: 715 // MAXIMUM Maximum value 716 // MINIMUM Minimum value 717 #define FLASH_CFGCMD_WAITSTATE_W 4U 718 #define FLASH_CFGCMD_WAITSTATE_M 0x0000000FU 719 #define FLASH_CFGCMD_WAITSTATE_S 0U 720 #define FLASH_CFGCMD_WAITSTATE_MAXIMUM 0x0000000FU 721 #define FLASH_CFGCMD_WAITSTATE_MINIMUM 0x00000000U 722 723 //***************************************************************************** 724 // 725 // Register: FLASH_O_CFGPCNT 726 // 727 //***************************************************************************** 728 // Field: [11:4] MAXPCNTVAL 729 // 730 // Override maximum pulse counter with this value. 731 // If MAXPCNTOVR = 0, then this field is ignored. 732 // If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used 733 // to override the max pulse count for both program and erase. Full max value 734 // will be {4'h0, MAXPCNTVAL} . 735 // If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used 736 // to override the max pulse count for program only. Full max value will be 737 // {4'h0, MAXPCNTVAL}. 738 // ENUMs: 739 // MAXIMUM Maximum value 740 // MINIMUM Minimum value 741 #define FLASH_CFGPCNT_MAXPCNTVAL_W 8U 742 #define FLASH_CFGPCNT_MAXPCNTVAL_M 0x00000FF0U 743 #define FLASH_CFGPCNT_MAXPCNTVAL_S 4U 744 #define FLASH_CFGPCNT_MAXPCNTVAL_MAXIMUM 0x00000FF0U 745 #define FLASH_CFGPCNT_MAXPCNTVAL_MINIMUM 0x00000000U 746 747 // Field: [0] MAXPCNTOVR 748 // 749 // Override hard-wired maximum pulse count. If MAXERSPCNTOVR 750 // is not set, then setting this value alone will override the max pulse count 751 // for 752 // both program and erase. If MAXERSPCNTOVR is set, then this bit will only 753 // control the max pulse count setting for program. 754 // By default, this bit is 0, and a hard-wired max pulse count is used. 755 // ENUMs: 756 // OVERRIDE Use value from MAXPCNTVAL field as maximum puse 757 // count 758 // DEFAULT Use hard-wired (default) value for maximum pulse 759 // count 760 #define FLASH_CFGPCNT_MAXPCNTOVR 0x00000001U 761 #define FLASH_CFGPCNT_MAXPCNTOVR_M 0x00000001U 762 #define FLASH_CFGPCNT_MAXPCNTOVR_S 0U 763 #define FLASH_CFGPCNT_MAXPCNTOVR_OVERRIDE 0x00000001U 764 #define FLASH_CFGPCNT_MAXPCNTOVR_DEFAULT 0x00000000U 765 766 //***************************************************************************** 767 // 768 // Register: FLASH_O_STATCMD 769 // 770 //***************************************************************************** 771 // Field: [12] FAILMISC 772 // 773 // Command failed due to error other than write/erase protect violation or 774 // verify 775 // error. This is an extra bit in case a new failure mechanism is added which 776 // requires a status bit. 777 // ENUMs: 778 // STATFAIL Fail 779 // STATNOFAIL No Fail 780 #define FLASH_STATCMD_FAILMISC 0x00001000U 781 #define FLASH_STATCMD_FAILMISC_M 0x00001000U 782 #define FLASH_STATCMD_FAILMISC_S 12U 783 #define FLASH_STATCMD_FAILMISC_STATFAIL 0x00001000U 784 #define FLASH_STATCMD_FAILMISC_STATNOFAIL 0x00000000U 785 786 // Field: [8] FAILINVDATA 787 // 788 // Program command failed because an attempt was made to program a stored 789 // 0 value to a 1. 790 // ENUMs: 791 // STATFAIL Fail 792 // STATNOFAIL No Fail 793 #define FLASH_STATCMD_FAILINVDATA 0x00000100U 794 #define FLASH_STATCMD_FAILINVDATA_M 0x00000100U 795 #define FLASH_STATCMD_FAILINVDATA_S 8U 796 #define FLASH_STATCMD_FAILINVDATA_STATFAIL 0x00000100U 797 #define FLASH_STATCMD_FAILINVDATA_STATNOFAIL 0x00000000U 798 799 // Field: [7] FAILMODE 800 // 801 // Command failed because a bank has been set to a mode other than READ. 802 // Program and Erase commands cannot be initiated unless all banks are in READ 803 // mode. 804 // ENUMs: 805 // STATFAIL Fail 806 // STATNOFAIL No Fail 807 #define FLASH_STATCMD_FAILMODE 0x00000080U 808 #define FLASH_STATCMD_FAILMODE_M 0x00000080U 809 #define FLASH_STATCMD_FAILMODE_S 7U 810 #define FLASH_STATCMD_FAILMODE_STATFAIL 0x00000080U 811 #define FLASH_STATCMD_FAILMODE_STATNOFAIL 0x00000000U 812 813 // Field: [6] FAILILLADDR 814 // 815 // Command failed due to the use of an illegal address 816 // ENUMs: 817 // STATFAIL Fail 818 // STATNOFAIL No Fail 819 #define FLASH_STATCMD_FAILILLADDR 0x00000040U 820 #define FLASH_STATCMD_FAILILLADDR_M 0x00000040U 821 #define FLASH_STATCMD_FAILILLADDR_S 6U 822 #define FLASH_STATCMD_FAILILLADDR_STATFAIL 0x00000040U 823 #define FLASH_STATCMD_FAILILLADDR_STATNOFAIL 0x00000000U 824 825 // Field: [5] FAILVERIFY 826 // 827 // Command failed due to verify error 828 // ENUMs: 829 // STATFAIL Fail 830 // STATNOFAIL No Fail 831 #define FLASH_STATCMD_FAILVERIFY 0x00000020U 832 #define FLASH_STATCMD_FAILVERIFY_M 0x00000020U 833 #define FLASH_STATCMD_FAILVERIFY_S 5U 834 #define FLASH_STATCMD_FAILVERIFY_STATFAIL 0x00000020U 835 #define FLASH_STATCMD_FAILVERIFY_STATNOFAIL 0x00000000U 836 837 // Field: [4] FAILWEPROT 838 // 839 // Command failed due to Write/Erase Protect Sector Violation 840 // ENUMs: 841 // STATFAIL Fail 842 // STATNOFAIL No Fail 843 #define FLASH_STATCMD_FAILWEPROT 0x00000010U 844 #define FLASH_STATCMD_FAILWEPROT_M 0x00000010U 845 #define FLASH_STATCMD_FAILWEPROT_S 4U 846 #define FLASH_STATCMD_FAILWEPROT_STATFAIL 0x00000010U 847 #define FLASH_STATCMD_FAILWEPROT_STATNOFAIL 0x00000000U 848 849 // Field: [2] CMDINPROGRESS 850 // 851 // Command In Progress 852 // ENUMs: 853 // STATINPROGRESS In Progress 854 // STATCOMPLETE Complete 855 #define FLASH_STATCMD_CMDINPROGRESS 0x00000004U 856 #define FLASH_STATCMD_CMDINPROGRESS_M 0x00000004U 857 #define FLASH_STATCMD_CMDINPROGRESS_S 2U 858 #define FLASH_STATCMD_CMDINPROGRESS_STATINPROGRESS 0x00000004U 859 #define FLASH_STATCMD_CMDINPROGRESS_STATCOMPLETE 0x00000000U 860 861 // Field: [1] CMDPASS 862 // 863 // Command Pass - valid when CMD_DONE field is 1 864 // ENUMs: 865 // STATPASS Pass 866 // STATFAIL Fail 867 #define FLASH_STATCMD_CMDPASS 0x00000002U 868 #define FLASH_STATCMD_CMDPASS_M 0x00000002U 869 #define FLASH_STATCMD_CMDPASS_S 1U 870 #define FLASH_STATCMD_CMDPASS_STATPASS 0x00000002U 871 #define FLASH_STATCMD_CMDPASS_STATFAIL 0x00000000U 872 873 // Field: [0] CMDDONE 874 // 875 // Command Done 876 // ENUMs: 877 // STATDONE Done 878 // STATNOTDONE Not Done 879 #define FLASH_STATCMD_CMDDONE 0x00000001U 880 #define FLASH_STATCMD_CMDDONE_M 0x00000001U 881 #define FLASH_STATCMD_CMDDONE_S 0U 882 #define FLASH_STATCMD_CMDDONE_STATDONE 0x00000001U 883 #define FLASH_STATCMD_CMDDONE_STATNOTDONE 0x00000000U 884 885 //***************************************************************************** 886 // 887 // Register: FLASH_O_STATADDR 888 // 889 //***************************************************************************** 890 // Field: [25:21] BANKID 891 // 892 // Current Bank ID 893 // A bank indicator is stored in this register which represents the current 894 // bank on 895 // which the state machine is operating. There is 1 bit per bank. 896 // ENUMs: 897 // BANK4 Bank 4 898 // BANK3 Bank 3 899 // BANK2 Bank 2 900 // BANK1 Bank 1 901 // BANK0 Bank 0 902 #define FLASH_STATADDR_BANKID_W 5U 903 #define FLASH_STATADDR_BANKID_M 0x03E00000U 904 #define FLASH_STATADDR_BANKID_S 21U 905 #define FLASH_STATADDR_BANKID_BANK4 0x02000000U 906 #define FLASH_STATADDR_BANKID_BANK3 0x01000000U 907 #define FLASH_STATADDR_BANKID_BANK2 0x00800000U 908 #define FLASH_STATADDR_BANKID_BANK1 0x00400000U 909 #define FLASH_STATADDR_BANKID_BANK0 0x00200000U 910 911 // Field: [20:16] REGIONID 912 // 913 // Current Region ID 914 // A region indicator is stored in this register which represents the current 915 // flash 916 // region on which the state machine is operating. 917 // ENUMs: 918 // ENGR Engr Region 919 // TRIM Trim Region 920 // NONMAIN Non-Main Region 921 // MAIN Main Region 922 #define FLASH_STATADDR_REGIONID_W 5U 923 #define FLASH_STATADDR_REGIONID_M 0x001F0000U 924 #define FLASH_STATADDR_REGIONID_S 16U 925 #define FLASH_STATADDR_REGIONID_ENGR 0x00080000U 926 #define FLASH_STATADDR_REGIONID_TRIM 0x00040000U 927 #define FLASH_STATADDR_REGIONID_NONMAIN 0x00020000U 928 #define FLASH_STATADDR_REGIONID_MAIN 0x00010000U 929 930 // Field: [15:0] BANKADDR 931 // 932 // Current Bank Address 933 // A bank offset address is stored in this register. 934 // ENUMs: 935 // MAXIMUM Maximum value 936 // MINIMUM Minimum value 937 #define FLASH_STATADDR_BANKADDR_W 16U 938 #define FLASH_STATADDR_BANKADDR_M 0x0000FFFFU 939 #define FLASH_STATADDR_BANKADDR_S 0U 940 #define FLASH_STATADDR_BANKADDR_MAXIMUM 0x0000FFFFU 941 #define FLASH_STATADDR_BANKADDR_MINIMUM 0x00000000U 942 943 //***************************************************************************** 944 // 945 // Register: FLASH_O_STATPCNT 946 // 947 //***************************************************************************** 948 // Field: [11:0] PULSECNT 949 // 950 // Current Pulse Counter Value 951 // ENUMs: 952 // MAXIMUM Maximum value 953 // MINIMUM Minimum value 954 #define FLASH_STATPCNT_PULSECNT_W 12U 955 #define FLASH_STATPCNT_PULSECNT_M 0x00000FFFU 956 #define FLASH_STATPCNT_PULSECNT_S 0U 957 #define FLASH_STATPCNT_PULSECNT_MAXIMUM 0x00000FFFU 958 #define FLASH_STATPCNT_PULSECNT_MINIMUM 0x00000000U 959 960 //***************************************************************************** 961 // 962 // Register: FLASH_O_STATMODE 963 // 964 //***************************************************************************** 965 // Field: [17] BANK1TRDY 966 // 967 // Bank 1T Ready. 968 // Bank(s) are ready for 1T access. This is accomplished when the bank and 969 // pump 970 // have been trimmed. 971 // ENUMs: 972 // TRUE Ready 973 // FALSE Not ready 974 #define FLASH_STATMODE_BANK1TRDY 0x00020000U 975 #define FLASH_STATMODE_BANK1TRDY_M 0x00020000U 976 #define FLASH_STATMODE_BANK1TRDY_S 17U 977 #define FLASH_STATMODE_BANK1TRDY_TRUE 0x00020000U 978 #define FLASH_STATMODE_BANK1TRDY_FALSE 0x00000000U 979 980 // Field: [16] BANK2TRDY 981 // 982 // Bank 2T Ready. 983 // Bank(s) are ready for 2T access. This is accomplished when the pump has 984 // fully driven power rails to the bank(s). 985 // ENUMs: 986 // TRUE Ready 987 // FALSE Not ready 988 #define FLASH_STATMODE_BANK2TRDY 0x00010000U 989 #define FLASH_STATMODE_BANK2TRDY_M 0x00010000U 990 #define FLASH_STATMODE_BANK2TRDY_S 16U 991 #define FLASH_STATMODE_BANK2TRDY_TRUE 0x00010000U 992 #define FLASH_STATMODE_BANK2TRDY_FALSE 0x00000000U 993 994 // Field: [11:8] BANKMODE 995 // 996 // Indicates mode of bank(s) that are not in READ mode 997 // ENUMs: 998 // ERASEBNK Erase Bank 999 // PGMMW Program Multiple Word 1000 // ERASESECT Erase Sector 1001 // ERASEVER Erase Verify Mode 1002 // PGMSW Program Single Word 1003 // PGMVER Program Verify Mode 1004 // RDMARG1B Read Margin 1B Mode 1005 // RDMARG0B Read Margin 0B Mode 1006 // RDMARG1 Read Margin 1 Mode 1007 // RDMARG0 Read Margin 0 Mode 1008 // READ Read Mode 1009 #define FLASH_STATMODE_BANKMODE_W 4U 1010 #define FLASH_STATMODE_BANKMODE_M 0x00000F00U 1011 #define FLASH_STATMODE_BANKMODE_S 8U 1012 #define FLASH_STATMODE_BANKMODE_ERASEBNK 0x00000F00U 1013 #define FLASH_STATMODE_BANKMODE_PGMMW 0x00000E00U 1014 #define FLASH_STATMODE_BANKMODE_ERASESECT 0x00000C00U 1015 #define FLASH_STATMODE_BANKMODE_ERASEVER 0x00000B00U 1016 #define FLASH_STATMODE_BANKMODE_PGMSW 0x00000A00U 1017 #define FLASH_STATMODE_BANKMODE_PGMVER 0x00000900U 1018 #define FLASH_STATMODE_BANKMODE_RDMARG1B 0x00000700U 1019 #define FLASH_STATMODE_BANKMODE_RDMARG0B 0x00000600U 1020 #define FLASH_STATMODE_BANKMODE_RDMARG1 0x00000400U 1021 #define FLASH_STATMODE_BANKMODE_RDMARG0 0x00000200U 1022 #define FLASH_STATMODE_BANKMODE_READ 0x00000000U 1023 1024 // Field: [0] BANKNOTINRD 1025 // 1026 // Bank not in read mode. 1027 // Indicates which banks are not in READ mode. There is 1 bit per bank. 1028 // ENUMs: 1029 // BANK4 Bank 4 1030 // BANK3 Bank 3 1031 // BANK2 Bank 2 1032 // BANK1 Bank 1 1033 // BANK0 Bank 0 1034 #define FLASH_STATMODE_BANKNOTINRD 0x00000001U 1035 #define FLASH_STATMODE_BANKNOTINRD_M 0x00000001U 1036 #define FLASH_STATMODE_BANKNOTINRD_S 0U 1037 #define FLASH_STATMODE_BANKNOTINRD_BANK4 0x00000010U 1038 #define FLASH_STATMODE_BANKNOTINRD_BANK3 0x00000008U 1039 #define FLASH_STATMODE_BANKNOTINRD_BANK2 0x00000004U 1040 #define FLASH_STATMODE_BANKNOTINRD_BANK1 0x00000002U 1041 #define FLASH_STATMODE_BANKNOTINRD_BANK0 0x00000001U 1042 1043 //***************************************************************************** 1044 // 1045 // Register: FLASH_O_GBLINFO0 1046 // 1047 //***************************************************************************** 1048 // Field: [18:16] NUMBANKS 1049 // 1050 // Number of banks instantiated 1051 // Minimum: 1 1052 // Maximum: 5 1053 // ENUMs: 1054 // MAXIMUM Maximum value 1055 // MINIMUM Minimum value 1056 #define FLASH_GBLINFO0_NUMBANKS_W 3U 1057 #define FLASH_GBLINFO0_NUMBANKS_M 0x00070000U 1058 #define FLASH_GBLINFO0_NUMBANKS_S 16U 1059 #define FLASH_GBLINFO0_NUMBANKS_MAXIMUM 0x00050000U 1060 #define FLASH_GBLINFO0_NUMBANKS_MINIMUM 0x00010000U 1061 1062 // Field: [15:0] SECTORSIZE 1063 // 1064 // Sector size in bytes 1065 // ENUMs: 1066 // TWOKB Sector size is TWOKB 1067 // ONEKB Sector size is ONEKB 1068 #define FLASH_GBLINFO0_SECTORSIZE_W 16U 1069 #define FLASH_GBLINFO0_SECTORSIZE_M 0x0000FFFFU 1070 #define FLASH_GBLINFO0_SECTORSIZE_S 0U 1071 #define FLASH_GBLINFO0_SECTORSIZE_TWOKB 0x00000800U 1072 #define FLASH_GBLINFO0_SECTORSIZE_ONEKB 0x00000400U 1073 1074 //***************************************************************************** 1075 // 1076 // Register: FLASH_O_GBLINFO1 1077 // 1078 //***************************************************************************** 1079 // Field: [18:16] REDWIDTH 1080 // 1081 // Redundant data width in bits 1082 // ENUMs: 1083 // W4BIT Redundant data width is 4 bits 1084 // W2BIT Redundant data width is 2 bits 1085 // W0BIT Redundant data width is 0. Redundancy/Repair not 1086 // present. 1087 #define FLASH_GBLINFO1_REDWIDTH_W 3U 1088 #define FLASH_GBLINFO1_REDWIDTH_M 0x00070000U 1089 #define FLASH_GBLINFO1_REDWIDTH_S 16U 1090 #define FLASH_GBLINFO1_REDWIDTH_W4BIT 0x00040000U 1091 #define FLASH_GBLINFO1_REDWIDTH_W2BIT 0x00020000U 1092 #define FLASH_GBLINFO1_REDWIDTH_W0BIT 0x00000000U 1093 1094 // Field: [12:8] ECCWIDTH 1095 // 1096 // ECC data width in bits 1097 // ENUMs: 1098 // W16BIT ECC data width is 16 bits 1099 // W8BIT ECC data width is 8 bits 1100 // W0BIT ECC data width is 0. ECC not used. 1101 #define FLASH_GBLINFO1_ECCWIDTH_W 5U 1102 #define FLASH_GBLINFO1_ECCWIDTH_M 0x00001F00U 1103 #define FLASH_GBLINFO1_ECCWIDTH_S 8U 1104 #define FLASH_GBLINFO1_ECCWIDTH_W16BIT 0x00001000U 1105 #define FLASH_GBLINFO1_ECCWIDTH_W8BIT 0x00000800U 1106 #define FLASH_GBLINFO1_ECCWIDTH_W0BIT 0x00000000U 1107 1108 // Field: [7:0] DATAWIDTH 1109 // 1110 // Data width in bits 1111 // ENUMs: 1112 // W128BIT Data width is 128 bits 1113 // W64BIT Data width is 64 bits 1114 #define FLASH_GBLINFO1_DATAWIDTH_W 8U 1115 #define FLASH_GBLINFO1_DATAWIDTH_M 0x000000FFU 1116 #define FLASH_GBLINFO1_DATAWIDTH_S 0U 1117 #define FLASH_GBLINFO1_DATAWIDTH_W128BIT 0x00000080U 1118 #define FLASH_GBLINFO1_DATAWIDTH_W64BIT 0x00000040U 1119 1120 //***************************************************************************** 1121 // 1122 // Register: FLASH_O_GBLINFO2 1123 // 1124 //***************************************************************************** 1125 // Field: [3:0] DATAREGISTERS 1126 // 1127 // Number of data registers present. 1128 // ENUMs: 1129 // MAXIMUM Maximum value of DATAREGISTERS 1130 // MINIMUM Minimum value of DATAREGISTERS 1131 #define FLASH_GBLINFO2_DATAREGISTERS_W 4U 1132 #define FLASH_GBLINFO2_DATAREGISTERS_M 0x0000000FU 1133 #define FLASH_GBLINFO2_DATAREGISTERS_S 0U 1134 #define FLASH_GBLINFO2_DATAREGISTERS_MAXIMUM 0x00000008U 1135 #define FLASH_GBLINFO2_DATAREGISTERS_MINIMUM 0x00000001U 1136 1137 //***************************************************************************** 1138 // 1139 // Register: FLASH_O_BANK0INFO0 1140 // 1141 //***************************************************************************** 1142 // Field: [11:0] MAINSIZE 1143 // 1144 // Main region size in sectors 1145 // Minimum: 0x8 (8) 1146 // Maximum: 0x200 (512) 1147 // ENUMs: 1148 // MAXSECTORS Maximum value of MAINSIZE 1149 // MINSECTORS Minimum value of MAINSIZE 1150 #define FLASH_BANK0INFO0_MAINSIZE_W 12U 1151 #define FLASH_BANK0INFO0_MAINSIZE_M 0x00000FFFU 1152 #define FLASH_BANK0INFO0_MAINSIZE_S 0U 1153 #define FLASH_BANK0INFO0_MAINSIZE_MAXSECTORS 0x00000200U 1154 #define FLASH_BANK0INFO0_MAINSIZE_MINSECTORS 0x00000008U 1155 1156 //***************************************************************************** 1157 // 1158 // Register: FLASH_O_BANK0INFO1 1159 // 1160 //***************************************************************************** 1161 // Field: [23:16] ENGRSIZE 1162 // 1163 // Engr region size in sectors 1164 // Minimum: 0x0 (0) 1165 // Maximum: 0x10 (16) 1166 // ENUMs: 1167 // MAXSECTORS Maximum value of ENGRSIZE 1168 // MINSECTORS Minimum value of ENGRSIZE 1169 #define FLASH_BANK0INFO1_ENGRSIZE_W 8U 1170 #define FLASH_BANK0INFO1_ENGRSIZE_M 0x00FF0000U 1171 #define FLASH_BANK0INFO1_ENGRSIZE_S 16U 1172 #define FLASH_BANK0INFO1_ENGRSIZE_MAXSECTORS 0x00200000U 1173 #define FLASH_BANK0INFO1_ENGRSIZE_MINSECTORS 0x00000000U 1174 1175 // Field: [15:8] TRIMSIZE 1176 // 1177 // Trim region size in sectors 1178 // Minimum: 0x0 (0) 1179 // Maximum: 0x10 (16) 1180 // ENUMs: 1181 // MAXSECTORS Maximum value of TRIMSIZE 1182 // MINSECTORS Minimum value of TRIMSIZE 1183 #define FLASH_BANK0INFO1_TRIMSIZE_W 8U 1184 #define FLASH_BANK0INFO1_TRIMSIZE_M 0x0000FF00U 1185 #define FLASH_BANK0INFO1_TRIMSIZE_S 8U 1186 #define FLASH_BANK0INFO1_TRIMSIZE_MAXSECTORS 0x00002000U 1187 #define FLASH_BANK0INFO1_TRIMSIZE_MINSECTORS 0x00000000U 1188 1189 // Field: [7:0] NONMAINSIZE 1190 // 1191 // Non-main region size in sectors 1192 // Minimum: 0x0 (0) 1193 // Maximum: 0x10 (16) 1194 // ENUMs: 1195 // MAXSECTORS Maximum value of NONMAINSIZE 1196 // MINSECTORS Minimum value of NONMAINSIZE 1197 #define FLASH_BANK0INFO1_NONMAINSIZE_W 8U 1198 #define FLASH_BANK0INFO1_NONMAINSIZE_M 0x000000FFU 1199 #define FLASH_BANK0INFO1_NONMAINSIZE_S 0U 1200 #define FLASH_BANK0INFO1_NONMAINSIZE_MAXSECTORS 0x00000020U 1201 #define FLASH_BANK0INFO1_NONMAINSIZE_MINSECTORS 0x00000000U 1202 1203 1204 #endif // __FLASH__ 1205
