1 /****************************************************************************** 2 * Filename: hw_memmap_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_MEMMAP_H__ 34 #define __HW_MEMMAP_H__ 35 36 //***************************************************************************** 37 // 38 // The following are defines for the base address of the memories and 39 // peripherals on the CPU_MMAP interface 40 // 41 //***************************************************************************** 42 #define FLASH_MAIN_BASE 0x00000000 // FLASH_MAIN 43 #define FLASH_MAIN_SIZE 0x80000 44 #define ROM_BASE 0x0F000000 // ROM 45 #define ROM_SIZE 0x3000 46 #define SRAM_BASE 0x20000000 // SRAM 47 #define SRAM_SIZE 0x9000 48 #define PMCTL_BASE 0x40000000 // PMCTL 49 #define CKMD_BASE 0x40001000 // CKMD 50 #define RTC_BASE 0x40002000 // RTC 51 #define IOC_BASE 0x40003000 // IOC 52 #define SYS0_BASE 0x40004000 // SYS0 53 #define EVTULL_BASE 0x40005000 // EVTULL 54 #define PMUD_BASE 0x40006000 // PMUD 55 #define DBGSS_BASE 0x4000F000 // DBGSS 56 #define CLKCTL_BASE 0x40020000 // CLKCTL 57 #define FLASH_BASE 0x40021000 // FLASH 58 #define SYSTIM_BASE 0x40022000 // SYSTIM 59 #define GPIO_BASE 0x40023000 // GPIO 60 #define VIMS_BASE 0x40024000 // VIMS 61 #define EVTSVT_BASE 0x40025000 // EVTSVT 62 #define DMA_BASE 0x40026000 // DMA 63 #define SPI0_BASE 0x40030000 // SPI 64 #define UART0_BASE 0x40034000 // UART 65 #define I2C0_BASE 0x40038000 // I2C 66 #define ADC_BASE 0x40050000 // ADC 67 #define LGPT0_BASE 0x40060000 // LGPT0 68 #define LGPT1_BASE 0x40061000 // LGPT1 69 #define LGPT2_BASE 0x40062000 // LGPT2 70 #define LGPT3_BASE 0x40063000 // LGPT3 71 #define LRFDDBELL_BASE 0x40080000 // LRFDDBELL 72 #define LRFDPBE_BASE 0x40081000 // LRFDPBE 73 #define LRFDPBE32_BASE 0x40081400 // LRFDPBE32 74 #define LRFDTXF_BASE 0x40081800 // LRFDTXF 75 #define LRFDRXF_BASE 0x40081C00 // LRFDRXF 76 #define LRFDMDM_BASE 0x40082000 // LRFDMDM 77 #define LRFDMDM32_BASE 0x40082400 // LRFDMDM32 78 #define LRFDRFE_BASE 0x40083000 // LRFDRFE 79 #define LRFDRFE32_BASE 0x40083400 // LRFDRFE32 80 #define LRFDTRC_BASE 0x40084000 // LRFDTRC 81 #define LRFDS2R_BASE 0x40085000 // LRFDS2R 82 #define LRFD_PBERAM_BASE 0x40090000 // LRFD_PBERAM 83 #define LRFD_PBERAM_SIZE 0x1000 84 #define LRFD_BUFRAM_BASE 0x40092000 // LRFD_BUFRAM 85 #define LRFD_BUFRAM_SIZE 0x600 86 #define LRFD_MCERAM_BASE 0x40094000 // LRFD_MCERAM 87 #define LRFD_MCERAM_SIZE 0x1000 88 #define LRFD_RFERAM_BASE 0x40096000 // LRFD_RFERAM 89 #define LRFD_RFERAM_SIZE 0x1000 90 #define LRFD_S2RRAM_BASE 0x40098000 // LRFD_S2RRAM 91 #define LRFD_S2RRAM_SIZE 0x1000 92 #define AES_BASE 0x400C0000 // AES 93 #define FCFG_BASE 0x4E000000 // FCFG 94 #define FCFG_SIZE 0x400 95 #define CCFG_BASE 0x4E020000 // CCFG 96 #define CCFG_SIZE 0x800 97 #define BPU_BASE 0xE0002000 // BPU 98 #define NVIC_BASE 0xE000E000 // NVIC 99 #define SYSTICK_BASE 0xE000E010 // SYSTICK 100 #define SCB_BASE 0xE000ED00 // SCB 101 #define DCB_BASE 0xE000ED30 // DCB 102 #define SCSCS_BASE 0xE000EFC0 // SCSCS 103 #define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE 104 105 #endif // __HW_MEMMAP__ 106
