1 /****************************************************************************** 2 * Filename: hw_evtsvt_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_EVTSVT_H__ 34 #define __HW_EVTSVT_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // EVTSVT component 40 // 41 //***************************************************************************** 42 // Description 43 #define EVTSVT_O_DESC 0x00000000U 44 45 // Extended Description 46 #define EVTSVT_O_DESCEX 0x00000004U 47 48 // Digital test bus control 49 #define EVTSVT_O_DTB 0x00000064U 50 51 // Output Selection for CPU NMI Exception 52 #define EVTSVT_O_NMISEL 0x00000400U 53 54 // Output Selection for CPU Interrupt CPUIRQ0 55 #define EVTSVT_O_CPUIRQ0SEL 0x00000404U 56 57 // Output Selection for CPU Interrupt CPUIRQ1 58 #define EVTSVT_O_CPUIRQ1SEL 0x00000408U 59 60 // Output Selection for CPU Interrupt CPUIRQ2 61 #define EVTSVT_O_CPUIRQ2SEL 0x0000040CU 62 63 // Output Selection for CPU Interrupt CPUIRQ3 64 #define EVTSVT_O_CPUIRQ3SEL 0x00000410U 65 66 // Output Selection for CPU Interrupt CPUIRQ4 67 #define EVTSVT_O_CPUIRQ4SEL 0x00000414U 68 69 // Output Selection for CPU Interrupt CPUIRQ5 70 #define EVTSVT_O_CPUIRQ5SEL 0x00000418U 71 72 // Output Selection for CPU Interrupt CPUIRQ6 73 #define EVTSVT_O_CPUIRQ6SEL 0x0000041CU 74 75 // Output Selection for CPU Interrupt CPUIRQ7 76 #define EVTSVT_O_CPUIRQ7SEL 0x00000420U 77 78 // Output Selection for CPU Interrupt CPUIRQ8 79 #define EVTSVT_O_CPUIRQ8SEL 0x00000424U 80 81 // Output Selection for CPU Interrupt CPUIRQ9 82 #define EVTSVT_O_CPUIRQ9SEL 0x00000428U 83 84 // Output Selection for CPU Interrupt CPUIRQ10 85 #define EVTSVT_O_CPUIRQ10SEL 0x0000042CU 86 87 // Output Selection for CPU Interrupt CPUIRQ11 88 #define EVTSVT_O_CPUIRQ11SEL 0x00000430U 89 90 // Output Selection for CPU Interrupt CPUIRQ12 91 #define EVTSVT_O_CPUIRQ12SEL 0x00000434U 92 93 // Output Selection for CPU Interrupt CPUIRQ13 94 #define EVTSVT_O_CPUIRQ13SEL 0x00000438U 95 96 // Output Selection for CPU Interrupt CPUIRQ14 97 #define EVTSVT_O_CPUIRQ14SEL 0x0000043CU 98 99 // Output Selection for CPU Interrupt CPUIRQ15 100 #define EVTSVT_O_CPUIRQ15SEL 0x00000440U 101 102 // Output Selection for CPU Interrupt CPUIRQ16 103 #define EVTSVT_O_CPUIRQ16SEL 0x00000444U 104 105 // Output Selection for CPU Interrupt CPUIRQ17 106 #define EVTSVT_O_CPUIRQ17SEL 0x00000448U 107 108 // Output Selection for CPU Interrupt CPUIRQ18 109 #define EVTSVT_O_CPUIRQ18SEL 0x0000044CU 110 111 // Output Selection for SYSTIMC0 112 #define EVTSVT_O_SYSTIMC0SEL 0x00000450U 113 114 // Output Selection for SYSTIMC1 115 #define EVTSVT_O_SYSTIMC1SEL 0x00000454U 116 117 // Output Selection for SYSTIMC2 118 #define EVTSVT_O_SYSTIMC2SEL 0x00000458U 119 120 // Output Selection for SYSTIMC3 121 #define EVTSVT_O_SYSTIMC3SEL 0x0000045CU 122 123 // Output Selection for SYSTIMC4 124 #define EVTSVT_O_SYSTIMC4SEL 0x00000460U 125 126 // Output Selection for ADCTRG 127 #define EVTSVT_O_ADCTRGSEL 0x00000464U 128 129 // Output Selection for LGPTSYNC 130 #define EVTSVT_O_LGPTSYNCSEL 0x00000468U 131 132 // Output Selection for LGPT0IN0 133 #define EVTSVT_O_LGPT0IN0SEL 0x0000046CU 134 135 // Output Selection for LGPT0IN1 136 #define EVTSVT_O_LGPT0IN1SEL 0x00000470U 137 138 // Output Selection for LGPT0IN2 139 #define EVTSVT_O_LGPT0IN2SEL 0x00000474U 140 141 // Output Selection for LGPT0TEN 142 #define EVTSVT_O_LGPT0TENSEL 0x00000478U 143 144 // Output Selection for LGPT1IN0 145 #define EVTSVT_O_LGPT1IN0SEL 0x0000047CU 146 147 // Output Selection for LGPT1IN1 148 #define EVTSVT_O_LGPT1IN1SEL 0x00000480U 149 150 // Output Selection for LGPT1IN2 151 #define EVTSVT_O_LGPT1IN2SEL 0x00000484U 152 153 // Output Selection for LGPT1TEN 154 #define EVTSVT_O_LGPT1TENSEL 0x00000488U 155 156 // Output Selection for LGPT2IN0 157 #define EVTSVT_O_LGPT2IN0SEL 0x0000048CU 158 159 // Output Selection for LGPT2IN1 160 #define EVTSVT_O_LGPT2IN1SEL 0x00000490U 161 162 // Output Selection for LGPT2IN2 163 #define EVTSVT_O_LGPT2IN2SEL 0x00000494U 164 165 // Output Selection for LGPT2TEN 166 #define EVTSVT_O_LGPT2TENSEL 0x00000498U 167 168 // Output Selection for LGPT3IN0 169 #define EVTSVT_O_LGPT3IN0SEL 0x0000049CU 170 171 // Output Selection for LGPT3IN1 172 #define EVTSVT_O_LGPT3IN1SEL 0x000004A0U 173 174 // Output Selection for LGPT3IN2 175 #define EVTSVT_O_LGPT3IN2SEL 0x000004A4U 176 177 // Output Selection for LGPT3TEN 178 #define EVTSVT_O_LGPT3TENSEL 0x000004A8U 179 180 // Output Selection for LRFDIN0 181 #define EVTSVT_O_LRFDIN0SEL 0x000004ACU 182 183 // Output Selection for LRFDIN1 184 #define EVTSVT_O_LRFDIN1SEL 0x000004B0U 185 186 // Output Selection for LRFDIN2 187 #define EVTSVT_O_LRFDIN2SEL 0x000004B4U 188 189 // Output Selection for DMA CH0 190 #define EVTSVT_O_DMACH0SEL 0x00000C00U 191 192 // Output Selection for DMA CH1 193 #define EVTSVT_O_DMACH1SEL 0x00000C04U 194 195 // Output Selection for DMA CH2 196 #define EVTSVT_O_DMACH2SEL 0x00000C08U 197 198 // Output Selection for DMA CH3 199 #define EVTSVT_O_DMACH3SEL 0x00000C0CU 200 201 // Output Selection for DMA CH4 202 #define EVTSVT_O_DMACH4SEL 0x00000C10U 203 204 // Output Selection for DMA CH5 205 #define EVTSVT_O_DMACH5SEL 0x00000C14U 206 207 // Output Selection for DMA CH6 208 #define EVTSVT_O_DMACH6SEL 0x00000C18U 209 210 // Output Selection for DMA CH7 211 #define EVTSVT_O_DMACH7SEL 0x00000C1CU 212 213 //***************************************************************************** 214 // 215 // Register: EVTSVT_O_DESC 216 // 217 //***************************************************************************** 218 // Field: [31:16] MODID 219 // 220 // Module identifier used to uniquely identify this IP. 221 #define EVTSVT_DESC_MODID_W 16U 222 #define EVTSVT_DESC_MODID_M 0xFFFF0000U 223 #define EVTSVT_DESC_MODID_S 16U 224 225 // Field: [15:12] STDIPOFF 226 // 227 // Standard IP MMR block offset. Standard IP MMRs are the set of from 228 // aggregated IRQ registers till DTB. 229 // 0: Standard IP MMRs do not exist 230 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 231 // address) 232 #define EVTSVT_DESC_STDIPOFF_W 4U 233 #define EVTSVT_DESC_STDIPOFF_M 0x0000F000U 234 #define EVTSVT_DESC_STDIPOFF_S 12U 235 236 // Field: [11:8] INSTIDX 237 // 238 // IP Instance ID number. If multiple instances of IP exist in the device, this 239 // field can identify the instance number (0-15). 240 #define EVTSVT_DESC_INSTIDX_W 4U 241 #define EVTSVT_DESC_INSTIDX_M 0x00000F00U 242 #define EVTSVT_DESC_INSTIDX_S 8U 243 244 // Field: [7:4] MAJREV 245 // 246 // Major revision of IP (0-15). 247 #define EVTSVT_DESC_MAJREV_W 4U 248 #define EVTSVT_DESC_MAJREV_M 0x000000F0U 249 #define EVTSVT_DESC_MAJREV_S 4U 250 251 // Field: [3:0] MINREV 252 // 253 // Minor revision of IP (0-15). 254 #define EVTSVT_DESC_MINREV_W 4U 255 #define EVTSVT_DESC_MINREV_M 0x0000000FU 256 #define EVTSVT_DESC_MINREV_S 0U 257 258 //***************************************************************************** 259 // 260 // Register: EVTSVT_O_DESCEX 261 // 262 //***************************************************************************** 263 // Field: [31:22] IDMA 264 // 265 // Number of DMA input channels 266 #define EVTSVT_DESCEX_IDMA_W 10U 267 #define EVTSVT_DESCEX_IDMA_M 0xFFC00000U 268 #define EVTSVT_DESCEX_IDMA_S 22U 269 270 // Field: [21:17] NDMA 271 // 272 // Number of DMA output channels 273 #define EVTSVT_DESCEX_NDMA_W 5U 274 #define EVTSVT_DESCEX_NDMA_M 0x003E0000U 275 #define EVTSVT_DESCEX_NDMA_S 17U 276 277 // Field: [16] PD 278 // 279 // Power Domain. 280 // 0 : SVT 281 // 1 : ULL 282 #define EVTSVT_DESCEX_PD 0x00010000U 283 #define EVTSVT_DESCEX_PD_M 0x00010000U 284 #define EVTSVT_DESCEX_PD_S 16U 285 286 // Field: [15:8] NSUB 287 // 288 // Number of Subscribers 289 #define EVTSVT_DESCEX_NSUB_W 8U 290 #define EVTSVT_DESCEX_NSUB_M 0x0000FF00U 291 #define EVTSVT_DESCEX_NSUB_S 8U 292 293 // Field: [7:0] NPUB 294 // 295 // Number of Publishers 296 #define EVTSVT_DESCEX_NPUB_W 8U 297 #define EVTSVT_DESCEX_NPUB_M 0x000000FFU 298 #define EVTSVT_DESCEX_NPUB_S 0U 299 300 //***************************************************************************** 301 // 302 // Register: EVTSVT_O_DTB 303 // 304 //***************************************************************************** 305 // Field: [1:0] SEL 306 // 307 // Digital test bus selection mux control. 308 // Non-zero select values output a 16 bit selected group of signals per value. 309 // ENUMs: 310 // DIS All 16 observation signals are set to zero. 311 #define EVTSVT_DTB_SEL_W 2U 312 #define EVTSVT_DTB_SEL_M 0x00000003U 313 #define EVTSVT_DTB_SEL_S 0U 314 #define EVTSVT_DTB_SEL_DIS 0x00000000U 315 316 //***************************************************************************** 317 // 318 // Register: EVTSVT_O_NMISEL 319 // 320 //***************************************************************************** 321 // Field: [5:0] PUBID 322 // 323 // Read/write selection value. 324 // Writing any other value than values defined by a ENUM may result in 325 // undefined behavior. 326 // ENUMs: 327 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 328 // LGPT3:ADCTRG setting 329 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 330 // setting 331 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 332 // found here LGPT3:MIS 333 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 334 // by LGPT3:C2CFG setting 335 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 336 // by LGPT3:C1CFG setting 337 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 338 // by LGPT3:C0CFG setting 339 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 340 // LGPT2:ADCTRG setting 341 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 342 // setting 343 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 344 // found here LGPT2:MIS 345 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 346 // by LGPT2:C2CFG setting 347 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 348 // by LGPT2:C1CFG setting 349 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 350 // by LGPT2:C0CFG setting 351 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 352 // LRFDDBELL:SYSTIMOEV.SRC2 353 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 354 // LRFDDBELL:SYSTIMOEV.SRC1 355 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 356 // LRFDDBELL:SYSTIMOEV.SRC0 357 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 358 // LGPT1:ADCTRG setting 359 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 360 // setting 361 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 362 // by LGPT1:C2CFG setting 363 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 364 // by LGPT1:C1CFG setting 365 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 366 // by LGPT1:C0CFG setting 367 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 368 // LGPT0:ADCTRG setting 369 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 370 // setting 371 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 372 // by LGPT0:C2CFG setting 373 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 374 // by LGPT0:C1CFG setting 375 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 376 // by LGPT0:C0CFG setting 377 // SYSTIM4 SYSTIM Channel 4 event, event flag is 378 // SYSTIM:MIS.EVT4 379 // SYSTIM3 SYSTIM Channel 3 event, event flag is 380 // SYSTIM:MIS.EVT3 381 // SYSTIM2 SYSTIM Channel 2 event, event flag is 382 // SYSTIM:MIS.EVT2 383 // SYSTIM1 SYSTIM Channel 1 event, event flag is 384 // SYSTIM:MIS.EVT1 385 // SYSTIM0 SYSTIM Channel 0 event, event flag is 386 // SYSTIM:MIS.EVT0 387 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 388 // signal to SVT clock 389 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 390 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 391 // found here I2C0:MIS 392 // UART0_COMB UART0 combined interrupt, interrupt flags are 393 // found here UART0:MIS 394 // AES_COMB AES accelerator combined interrupt request, 395 // interrupt flags can be found here AES:MIS 396 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 397 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 398 // can be found here DMA:REQDONE 399 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 400 // found here LGPT1:MIS 401 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 402 // found here LGPT0:MIS 403 // ADC_EVT ADC general published event, interrupt flags can 404 // be found here ADC:MIS1 405 // ADC_COMB ADC combined interrupt request, interrupt flags 406 // can be found here ADC:MIS0 407 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 408 // can be found here SPI0:MIS 409 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 410 // here LRFDDBELL:MIS2 411 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 412 // here LRFDDBELL:MIS1 413 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 414 // here LRFDDBELL:MIS0 415 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 416 // flash operation has completed, interrupt flags 417 // can be found here FLASH:MIS 418 // GPIO_EVT GPIO generic published event, controlled by 419 // GPIO:EVTCFG 420 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 421 // can be found here GPIO:MIS 422 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 423 // found here SYSTIM:MIS 424 // AON_NMI_SEL Selects an AON_NMI source, controlled by 425 // EVTULL:NMISEL 426 // NONE Always inactive 427 #define EVTSVT_NMISEL_PUBID_W 6U 428 #define EVTSVT_NMISEL_PUBID_M 0x0000003FU 429 #define EVTSVT_NMISEL_PUBID_S 0U 430 #define EVTSVT_NMISEL_PUBID_LGPT3_ADC 0x00000039U 431 #define EVTSVT_NMISEL_PUBID_LGPT3_DMA 0x00000038U 432 #define EVTSVT_NMISEL_PUBID_LGPT3_COMB 0x00000037U 433 #define EVTSVT_NMISEL_PUBID_LGPT3C2 0x00000036U 434 #define EVTSVT_NMISEL_PUBID_LGPT3C1 0x00000035U 435 #define EVTSVT_NMISEL_PUBID_LGPT3C0 0x00000034U 436 #define EVTSVT_NMISEL_PUBID_LGPT2_ADC 0x00000033U 437 #define EVTSVT_NMISEL_PUBID_LGPT2_DMA 0x00000032U 438 #define EVTSVT_NMISEL_PUBID_LGPT2_COMB 0x00000031U 439 #define EVTSVT_NMISEL_PUBID_LGPT2C2 0x00000030U 440 #define EVTSVT_NMISEL_PUBID_LGPT2C1 0x0000002FU 441 #define EVTSVT_NMISEL_PUBID_LGPT2C0 0x0000002EU 442 #define EVTSVT_NMISEL_PUBID_LRFD_EVT2 0x0000002CU 443 #define EVTSVT_NMISEL_PUBID_LRFD_EVT1 0x0000002BU 444 #define EVTSVT_NMISEL_PUBID_LRFD_EVT0 0x0000002AU 445 #define EVTSVT_NMISEL_PUBID_LGPT1_ADC 0x00000029U 446 #define EVTSVT_NMISEL_PUBID_LGPT1_DMA 0x00000028U 447 #define EVTSVT_NMISEL_PUBID_LGPT1C2 0x00000027U 448 #define EVTSVT_NMISEL_PUBID_LGPT1C1 0x00000026U 449 #define EVTSVT_NMISEL_PUBID_LGPT1C0 0x00000025U 450 #define EVTSVT_NMISEL_PUBID_LGPT0_ADC 0x00000024U 451 #define EVTSVT_NMISEL_PUBID_LGPT0_DMA 0x00000023U 452 #define EVTSVT_NMISEL_PUBID_LGPT0C2 0x00000022U 453 #define EVTSVT_NMISEL_PUBID_LGPT0C1 0x00000021U 454 #define EVTSVT_NMISEL_PUBID_LGPT0C0 0x00000020U 455 #define EVTSVT_NMISEL_PUBID_SYSTIM4 0x0000001FU 456 #define EVTSVT_NMISEL_PUBID_SYSTIM3 0x0000001EU 457 #define EVTSVT_NMISEL_PUBID_SYSTIM2 0x0000001DU 458 #define EVTSVT_NMISEL_PUBID_SYSTIM1 0x0000001CU 459 #define EVTSVT_NMISEL_PUBID_SYSTIM0 0x0000001BU 460 #define EVTSVT_NMISEL_PUBID_SYSTIM_LT 0x0000001AU 461 #define EVTSVT_NMISEL_PUBID_SYSTIM_HB 0x00000019U 462 #define EVTSVT_NMISEL_PUBID_I2C0_IRQ 0x00000018U 463 #define EVTSVT_NMISEL_PUBID_UART0_COMB 0x00000017U 464 #define EVTSVT_NMISEL_PUBID_AES_COMB 0x00000016U 465 #define EVTSVT_NMISEL_PUBID_DMA_ERR 0x00000015U 466 #define EVTSVT_NMISEL_PUBID_DMA_DONE_COMB 0x00000014U 467 #define EVTSVT_NMISEL_PUBID_LGPT1_COMB 0x00000013U 468 #define EVTSVT_NMISEL_PUBID_LGPT0_COMB 0x00000012U 469 #define EVTSVT_NMISEL_PUBID_ADC_EVT 0x00000011U 470 #define EVTSVT_NMISEL_PUBID_ADC_COMB 0x00000010U 471 #define EVTSVT_NMISEL_PUBID_SPI0_COMB 0x0000000FU 472 #define EVTSVT_NMISEL_PUBID_LRFD_IRQ2 0x0000000EU 473 #define EVTSVT_NMISEL_PUBID_LRFD_IRQ1 0x0000000DU 474 #define EVTSVT_NMISEL_PUBID_LRFD_IRQ0 0x0000000CU 475 #define EVTSVT_NMISEL_PUBID_FLASH_IRQ 0x0000000BU 476 #define EVTSVT_NMISEL_PUBID_GPIO_EVT 0x0000000AU 477 #define EVTSVT_NMISEL_PUBID_GPIO_COMB 0x00000009U 478 #define EVTSVT_NMISEL_PUBID_SYSTIM_COMB 0x00000008U 479 #define EVTSVT_NMISEL_PUBID_AON_NMI_SEL 0x00000001U 480 #define EVTSVT_NMISEL_PUBID_NONE 0x00000000U 481 482 //***************************************************************************** 483 // 484 // Register: EVTSVT_O_CPUIRQ0SEL 485 // 486 //***************************************************************************** 487 // Field: [5:0] PUBID 488 // 489 // Read/write selection value. 490 // Writing any other value than values defined by a ENUM may result in 491 // undefined behavior. 492 // ENUMs: 493 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 494 // LGPT3:ADCTRG setting 495 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 496 // setting 497 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 498 // found here LGPT3:MIS 499 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 500 // by LGPT3:C2CFG setting 501 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 502 // by LGPT3:C1CFG setting 503 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 504 // by LGPT3:C0CFG setting 505 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 506 // LGPT2:ADCTRG setting 507 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 508 // setting 509 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 510 // found here LGPT2:MIS 511 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 512 // by LGPT2:C2CFG setting 513 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 514 // by LGPT2:C1CFG setting 515 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 516 // by LGPT2:C0CFG setting 517 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 518 // LRFDDBELL:SYSTIMOEV.SRC2 519 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 520 // LRFDDBELL:SYSTIMOEV.SRC1 521 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 522 // LRFDDBELL:SYSTIMOEV.SRC0 523 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 524 // LGPT1:ADCTRG setting 525 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 526 // setting 527 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 528 // by LGPT1:C2CFG setting 529 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 530 // by LGPT1:C1CFG setting 531 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 532 // by LGPT1:C0CFG setting 533 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 534 // LGPT0:ADCTRG setting 535 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 536 // setting 537 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 538 // by LGPT0:C2CFG setting 539 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 540 // by LGPT0:C1CFG setting 541 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 542 // by LGPT0:C0CFG setting 543 // SYSTIM4 SYSTIM Channel 4 event, event flag is 544 // SYSTIM:MIS.EVT4 545 // SYSTIM3 SYSTIM Channel 3 event, event flag is 546 // SYSTIM:MIS.EVT3 547 // SYSTIM2 SYSTIM Channel 2 event, event flag is 548 // SYSTIM:MIS.EVT2 549 // SYSTIM1 SYSTIM Channel 1 event, event flag is 550 // SYSTIM:MIS.EVT1 551 // SYSTIM0 SYSTIM Channel 0 event, event flag is 552 // SYSTIM:MIS.EVT0 553 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 554 // signal to SVT clock 555 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 556 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 557 // found here I2C0:MIS 558 // UART0_COMB UART0 combined interrupt, interrupt flags are 559 // found here UART0:MIS 560 // AES_COMB AES accelerator combined interrupt request, 561 // interrupt flags can be found here AES:MIS 562 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 563 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 564 // can be found here DMA:REQDONE 565 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 566 // found here LGPT1:MIS 567 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 568 // found here LGPT0:MIS 569 // ADC_EVT ADC general published event, interrupt flags can 570 // be found here ADC:MIS1 571 // ADC_COMB ADC combined interrupt request, interrupt flags 572 // can be found here ADC:MIS0 573 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 574 // can be found here SPI0:MIS 575 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 576 // here LRFDDBELL:MIS2 577 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 578 // here LRFDDBELL:MIS1 579 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 580 // here LRFDDBELL:MIS0 581 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 582 // flash operation has completed, interrupt flags 583 // can be found here FLASH:MIS 584 // GPIO_EVT GPIO generic published event, controlled by 585 // GPIO:EVTCFG 586 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 587 // can be found here GPIO:MIS 588 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 589 // found here SYSTIM:MIS 590 // AON_IOC_COMB IOC synchronous combined event, controlled by 591 // IOC:EVTCFG 592 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 593 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 594 // found here DBGSS:MIS 595 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 596 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 597 // can be found here CKMD:MIS 598 // AON_PMU_COMB PMU combined interrupt request for BATMON, 599 // interrupt flags can be found here PMUD:EVENT 600 // NONE Always inactive 601 #define EVTSVT_CPUIRQ0SEL_PUBID_W 6U 602 #define EVTSVT_CPUIRQ0SEL_PUBID_M 0x0000003FU 603 #define EVTSVT_CPUIRQ0SEL_PUBID_S 0U 604 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT3_ADC 0x00000039U 605 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT3_DMA 0x00000038U 606 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT3_COMB 0x00000037U 607 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT3C2 0x00000036U 608 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT3C1 0x00000035U 609 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT3C0 0x00000034U 610 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT2_ADC 0x00000033U 611 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT2_DMA 0x00000032U 612 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT2_COMB 0x00000031U 613 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT2C2 0x00000030U 614 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT2C1 0x0000002FU 615 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT2C0 0x0000002EU 616 #define EVTSVT_CPUIRQ0SEL_PUBID_LRFD_EVT2 0x0000002CU 617 #define EVTSVT_CPUIRQ0SEL_PUBID_LRFD_EVT1 0x0000002BU 618 #define EVTSVT_CPUIRQ0SEL_PUBID_LRFD_EVT0 0x0000002AU 619 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT1_ADC 0x00000029U 620 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT1_DMA 0x00000028U 621 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT1C2 0x00000027U 622 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT1C1 0x00000026U 623 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT1C0 0x00000025U 624 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT0_ADC 0x00000024U 625 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT0_DMA 0x00000023U 626 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT0C2 0x00000022U 627 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT0C1 0x00000021U 628 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT0C0 0x00000020U 629 #define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM4 0x0000001FU 630 #define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM3 0x0000001EU 631 #define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM2 0x0000001DU 632 #define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM1 0x0000001CU 633 #define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM0 0x0000001BU 634 #define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM_LT 0x0000001AU 635 #define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM_HB 0x00000019U 636 #define EVTSVT_CPUIRQ0SEL_PUBID_I2C0_IRQ 0x00000018U 637 #define EVTSVT_CPUIRQ0SEL_PUBID_UART0_COMB 0x00000017U 638 #define EVTSVT_CPUIRQ0SEL_PUBID_AES_COMB 0x00000016U 639 #define EVTSVT_CPUIRQ0SEL_PUBID_DMA_ERR 0x00000015U 640 #define EVTSVT_CPUIRQ0SEL_PUBID_DMA_DONE_COMB 0x00000014U 641 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT1_COMB 0x00000013U 642 #define EVTSVT_CPUIRQ0SEL_PUBID_LGPT0_COMB 0x00000012U 643 #define EVTSVT_CPUIRQ0SEL_PUBID_ADC_EVT 0x00000011U 644 #define EVTSVT_CPUIRQ0SEL_PUBID_ADC_COMB 0x00000010U 645 #define EVTSVT_CPUIRQ0SEL_PUBID_SPI0_COMB 0x0000000FU 646 #define EVTSVT_CPUIRQ0SEL_PUBID_LRFD_IRQ2 0x0000000EU 647 #define EVTSVT_CPUIRQ0SEL_PUBID_LRFD_IRQ1 0x0000000DU 648 #define EVTSVT_CPUIRQ0SEL_PUBID_LRFD_IRQ0 0x0000000CU 649 #define EVTSVT_CPUIRQ0SEL_PUBID_FLASH_IRQ 0x0000000BU 650 #define EVTSVT_CPUIRQ0SEL_PUBID_GPIO_EVT 0x0000000AU 651 #define EVTSVT_CPUIRQ0SEL_PUBID_GPIO_COMB 0x00000009U 652 #define EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM_COMB 0x00000008U 653 #define EVTSVT_CPUIRQ0SEL_PUBID_AON_IOC_COMB 0x00000007U 654 #define EVTSVT_CPUIRQ0SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 655 #define EVTSVT_CPUIRQ0SEL_PUBID_AON_DBG_COMB 0x00000005U 656 #define EVTSVT_CPUIRQ0SEL_PUBID_AON_RTC_COMB 0x00000004U 657 #define EVTSVT_CPUIRQ0SEL_PUBID_AON_CKM_COMB 0x00000003U 658 #define EVTSVT_CPUIRQ0SEL_PUBID_AON_PMU_COMB 0x00000002U 659 #define EVTSVT_CPUIRQ0SEL_PUBID_NONE 0x00000000U 660 661 //***************************************************************************** 662 // 663 // Register: EVTSVT_O_CPUIRQ1SEL 664 // 665 //***************************************************************************** 666 // Field: [5:0] PUBID 667 // 668 // Read/write selection value. 669 // Writing any other value than values defined by a ENUM may result in 670 // undefined behavior. 671 // ENUMs: 672 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 673 // LGPT3:ADCTRG setting 674 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 675 // setting 676 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 677 // found here LGPT3:MIS 678 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 679 // by LGPT3:C2CFG setting 680 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 681 // by LGPT3:C1CFG setting 682 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 683 // by LGPT3:C0CFG setting 684 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 685 // LGPT2:ADCTRG setting 686 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 687 // setting 688 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 689 // found here LGPT2:MIS 690 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 691 // by LGPT2:C2CFG setting 692 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 693 // by LGPT2:C1CFG setting 694 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 695 // by LGPT2:C0CFG setting 696 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 697 // LRFDDBELL:SYSTIMOEV.SRC2 698 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 699 // LRFDDBELL:SYSTIMOEV.SRC1 700 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 701 // LRFDDBELL:SYSTIMOEV.SRC0 702 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 703 // LGPT1:ADCTRG setting 704 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 705 // setting 706 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 707 // by LGPT1:C2CFG setting 708 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 709 // by LGPT1:C1CFG setting 710 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 711 // by LGPT1:C0CFG setting 712 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 713 // LGPT0:ADCTRG setting 714 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 715 // setting 716 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 717 // by LGPT0:C2CFG setting 718 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 719 // by LGPT0:C1CFG setting 720 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 721 // by LGPT0:C0CFG setting 722 // SYSTIM4 SYSTIM Channel 4 event, event flag is 723 // SYSTIM:MIS.EVT4 724 // SYSTIM3 SYSTIM Channel 3 event, event flag is 725 // SYSTIM:MIS.EVT3 726 // SYSTIM2 SYSTIM Channel 2 event, event flag is 727 // SYSTIM:MIS.EVT2 728 // SYSTIM1 SYSTIM Channel 1 event, event flag is 729 // SYSTIM:MIS.EVT1 730 // SYSTIM0 SYSTIM Channel 0 event, event flag is 731 // SYSTIM:MIS.EVT0 732 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 733 // signal to SVT clock 734 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 735 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 736 // found here I2C0:MIS 737 // UART0_COMB UART0 combined interrupt, interrupt flags are 738 // found here UART0:MIS 739 // AES_COMB AES accelerator combined interrupt request, 740 // interrupt flags can be found here AES:MIS 741 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 742 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 743 // can be found here DMA:REQDONE 744 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 745 // found here LGPT1:MIS 746 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 747 // found here LGPT0:MIS 748 // ADC_EVT ADC general published event, interrupt flags can 749 // be found here ADC:MIS1 750 // ADC_COMB ADC combined interrupt request, interrupt flags 751 // can be found here ADC:MIS0 752 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 753 // can be found here SPI0:MIS 754 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 755 // here LRFDDBELL:MIS2 756 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 757 // here LRFDDBELL:MIS1 758 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 759 // here LRFDDBELL:MIS0 760 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 761 // flash operation has completed, interrupt flags 762 // can be found here FLASH:MIS 763 // GPIO_EVT GPIO generic published event, controlled by 764 // GPIO:EVTCFG 765 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 766 // can be found here GPIO:MIS 767 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 768 // found here SYSTIM:MIS 769 // AON_IOC_COMB IOC synchronous combined event, controlled by 770 // IOC:EVTCFG 771 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 772 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 773 // found here DBGSS:MIS 774 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 775 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 776 // can be found here CKMD:MIS 777 // AON_PMU_COMB PMU combined interrupt request for BATMON, 778 // interrupt flags can be found here PMUD:EVENT 779 // NONE Always inactive 780 #define EVTSVT_CPUIRQ1SEL_PUBID_W 6U 781 #define EVTSVT_CPUIRQ1SEL_PUBID_M 0x0000003FU 782 #define EVTSVT_CPUIRQ1SEL_PUBID_S 0U 783 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT3_ADC 0x00000039U 784 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT3_DMA 0x00000038U 785 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT3_COMB 0x00000037U 786 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT3C2 0x00000036U 787 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT3C1 0x00000035U 788 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT3C0 0x00000034U 789 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT2_ADC 0x00000033U 790 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT2_DMA 0x00000032U 791 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT2_COMB 0x00000031U 792 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT2C2 0x00000030U 793 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT2C1 0x0000002FU 794 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT2C0 0x0000002EU 795 #define EVTSVT_CPUIRQ1SEL_PUBID_LRFD_EVT2 0x0000002CU 796 #define EVTSVT_CPUIRQ1SEL_PUBID_LRFD_EVT1 0x0000002BU 797 #define EVTSVT_CPUIRQ1SEL_PUBID_LRFD_EVT0 0x0000002AU 798 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT1_ADC 0x00000029U 799 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT1_DMA 0x00000028U 800 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT1C2 0x00000027U 801 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT1C1 0x00000026U 802 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT1C0 0x00000025U 803 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT0_ADC 0x00000024U 804 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT0_DMA 0x00000023U 805 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT0C2 0x00000022U 806 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT0C1 0x00000021U 807 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT0C0 0x00000020U 808 #define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM4 0x0000001FU 809 #define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM3 0x0000001EU 810 #define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM2 0x0000001DU 811 #define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM1 0x0000001CU 812 #define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM0 0x0000001BU 813 #define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM_LT 0x0000001AU 814 #define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM_HB 0x00000019U 815 #define EVTSVT_CPUIRQ1SEL_PUBID_I2C0_IRQ 0x00000018U 816 #define EVTSVT_CPUIRQ1SEL_PUBID_UART0_COMB 0x00000017U 817 #define EVTSVT_CPUIRQ1SEL_PUBID_AES_COMB 0x00000016U 818 #define EVTSVT_CPUIRQ1SEL_PUBID_DMA_ERR 0x00000015U 819 #define EVTSVT_CPUIRQ1SEL_PUBID_DMA_DONE_COMB 0x00000014U 820 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT1_COMB 0x00000013U 821 #define EVTSVT_CPUIRQ1SEL_PUBID_LGPT0_COMB 0x00000012U 822 #define EVTSVT_CPUIRQ1SEL_PUBID_ADC_EVT 0x00000011U 823 #define EVTSVT_CPUIRQ1SEL_PUBID_ADC_COMB 0x00000010U 824 #define EVTSVT_CPUIRQ1SEL_PUBID_SPI0_COMB 0x0000000FU 825 #define EVTSVT_CPUIRQ1SEL_PUBID_LRFD_IRQ2 0x0000000EU 826 #define EVTSVT_CPUIRQ1SEL_PUBID_LRFD_IRQ1 0x0000000DU 827 #define EVTSVT_CPUIRQ1SEL_PUBID_LRFD_IRQ0 0x0000000CU 828 #define EVTSVT_CPUIRQ1SEL_PUBID_FLASH_IRQ 0x0000000BU 829 #define EVTSVT_CPUIRQ1SEL_PUBID_GPIO_EVT 0x0000000AU 830 #define EVTSVT_CPUIRQ1SEL_PUBID_GPIO_COMB 0x00000009U 831 #define EVTSVT_CPUIRQ1SEL_PUBID_SYSTIM_COMB 0x00000008U 832 #define EVTSVT_CPUIRQ1SEL_PUBID_AON_IOC_COMB 0x00000007U 833 #define EVTSVT_CPUIRQ1SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 834 #define EVTSVT_CPUIRQ1SEL_PUBID_AON_DBG_COMB 0x00000005U 835 #define EVTSVT_CPUIRQ1SEL_PUBID_AON_RTC_COMB 0x00000004U 836 #define EVTSVT_CPUIRQ1SEL_PUBID_AON_CKM_COMB 0x00000003U 837 #define EVTSVT_CPUIRQ1SEL_PUBID_AON_PMU_COMB 0x00000002U 838 #define EVTSVT_CPUIRQ1SEL_PUBID_NONE 0x00000000U 839 840 //***************************************************************************** 841 // 842 // Register: EVTSVT_O_CPUIRQ2SEL 843 // 844 //***************************************************************************** 845 // Field: [5:0] PUBID 846 // 847 // Read/write selection value. 848 // Writing any other value than values defined by a ENUM may result in 849 // undefined behavior. 850 // ENUMs: 851 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 852 // found here LGPT3:MIS 853 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 854 // found here LGPT2:MIS 855 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 856 // found here I2C0:MIS 857 // UART0_COMB UART0 combined interrupt, interrupt flags are 858 // found here UART0:MIS 859 // AES_COMB AES accelerator combined interrupt request, 860 // interrupt flags can be found here AES:MIS 861 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 862 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 863 // can be found here DMA:REQDONE 864 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 865 // found here LGPT1:MIS 866 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 867 // found here LGPT0:MIS 868 // ADC_COMB ADC combined interrupt request, interrupt flags 869 // can be found here ADC:MIS0 870 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 871 // can be found here SPI0:MIS 872 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 873 // here LRFDDBELL:MIS2 874 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 875 // here LRFDDBELL:MIS1 876 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 877 // here LRFDDBELL:MIS0 878 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 879 // flash operation has completed, interrupt flags 880 // can be found here FLASH:MIS 881 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 882 // can be found here GPIO:MIS 883 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 884 // found here SYSTIM:MIS 885 // AON_IOC_COMB IOC synchronous combined event, controlled by 886 // IOC:EVTCFG 887 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 888 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 889 // found here DBGSS:MIS 890 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 891 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 892 // can be found here CKMD:MIS 893 // AON_PMU_COMB PMU combined interrupt request for BATMON, 894 // interrupt flags can be found here PMUD:EVENT 895 // NONE Always inactive 896 #define EVTSVT_CPUIRQ2SEL_PUBID_W 6U 897 #define EVTSVT_CPUIRQ2SEL_PUBID_M 0x0000003FU 898 #define EVTSVT_CPUIRQ2SEL_PUBID_S 0U 899 #define EVTSVT_CPUIRQ2SEL_PUBID_LGPT3_COMB 0x00000037U 900 #define EVTSVT_CPUIRQ2SEL_PUBID_LGPT2_COMB 0x00000031U 901 #define EVTSVT_CPUIRQ2SEL_PUBID_I2C0_IRQ 0x00000018U 902 #define EVTSVT_CPUIRQ2SEL_PUBID_UART0_COMB 0x00000017U 903 #define EVTSVT_CPUIRQ2SEL_PUBID_AES_COMB 0x00000016U 904 #define EVTSVT_CPUIRQ2SEL_PUBID_DMA_ERR 0x00000015U 905 #define EVTSVT_CPUIRQ2SEL_PUBID_DMA_DONE_COMB 0x00000014U 906 #define EVTSVT_CPUIRQ2SEL_PUBID_LGPT1_COMB 0x00000013U 907 #define EVTSVT_CPUIRQ2SEL_PUBID_LGPT0_COMB 0x00000012U 908 #define EVTSVT_CPUIRQ2SEL_PUBID_ADC_COMB 0x00000010U 909 #define EVTSVT_CPUIRQ2SEL_PUBID_SPI0_COMB 0x0000000FU 910 #define EVTSVT_CPUIRQ2SEL_PUBID_LRFD_IRQ2 0x0000000EU 911 #define EVTSVT_CPUIRQ2SEL_PUBID_LRFD_IRQ1 0x0000000DU 912 #define EVTSVT_CPUIRQ2SEL_PUBID_LRFD_IRQ0 0x0000000CU 913 #define EVTSVT_CPUIRQ2SEL_PUBID_FLASH_IRQ 0x0000000BU 914 #define EVTSVT_CPUIRQ2SEL_PUBID_GPIO_COMB 0x00000009U 915 #define EVTSVT_CPUIRQ2SEL_PUBID_SYSTIM_COMB 0x00000008U 916 #define EVTSVT_CPUIRQ2SEL_PUBID_AON_IOC_COMB 0x00000007U 917 #define EVTSVT_CPUIRQ2SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 918 #define EVTSVT_CPUIRQ2SEL_PUBID_AON_DBG_COMB 0x00000005U 919 #define EVTSVT_CPUIRQ2SEL_PUBID_AON_RTC_COMB 0x00000004U 920 #define EVTSVT_CPUIRQ2SEL_PUBID_AON_CKM_COMB 0x00000003U 921 #define EVTSVT_CPUIRQ2SEL_PUBID_AON_PMU_COMB 0x00000002U 922 #define EVTSVT_CPUIRQ2SEL_PUBID_NONE 0x00000000U 923 924 //***************************************************************************** 925 // 926 // Register: EVTSVT_O_CPUIRQ3SEL 927 // 928 //***************************************************************************** 929 // Field: [5:0] PUBID 930 // 931 // Read/write selection value. 932 // Writing any other value than values defined by a ENUM may result in 933 // undefined behavior. 934 // ENUMs: 935 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 936 // found here LGPT3:MIS 937 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 938 // found here LGPT2:MIS 939 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 940 // found here I2C0:MIS 941 // UART0_COMB UART0 combined interrupt, interrupt flags are 942 // found here UART0:MIS 943 // AES_COMB AES accelerator combined interrupt request, 944 // interrupt flags can be found here AES:MIS 945 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 946 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 947 // can be found here DMA:REQDONE 948 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 949 // found here LGPT1:MIS 950 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 951 // found here LGPT0:MIS 952 // ADC_COMB ADC combined interrupt request, interrupt flags 953 // can be found here ADC:MIS0 954 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 955 // can be found here SPI0:MIS 956 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 957 // here LRFDDBELL:MIS2 958 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 959 // here LRFDDBELL:MIS1 960 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 961 // here LRFDDBELL:MIS0 962 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 963 // flash operation has completed, interrupt flags 964 // can be found here FLASH:MIS 965 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 966 // can be found here GPIO:MIS 967 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 968 // found here SYSTIM:MIS 969 // AON_IOC_COMB IOC synchronous combined event, controlled by 970 // IOC:EVTCFG 971 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 972 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 973 // found here DBGSS:MIS 974 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 975 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 976 // can be found here CKMD:MIS 977 // AON_PMU_COMB PMU combined interrupt request for BATMON, 978 // interrupt flags can be found here PMUD:EVENT 979 // NONE Always inactive 980 #define EVTSVT_CPUIRQ3SEL_PUBID_W 6U 981 #define EVTSVT_CPUIRQ3SEL_PUBID_M 0x0000003FU 982 #define EVTSVT_CPUIRQ3SEL_PUBID_S 0U 983 #define EVTSVT_CPUIRQ3SEL_PUBID_LGPT3_COMB 0x00000037U 984 #define EVTSVT_CPUIRQ3SEL_PUBID_LGPT2_COMB 0x00000031U 985 #define EVTSVT_CPUIRQ3SEL_PUBID_I2C0_IRQ 0x00000018U 986 #define EVTSVT_CPUIRQ3SEL_PUBID_UART0_COMB 0x00000017U 987 #define EVTSVT_CPUIRQ3SEL_PUBID_AES_COMB 0x00000016U 988 #define EVTSVT_CPUIRQ3SEL_PUBID_DMA_ERR 0x00000015U 989 #define EVTSVT_CPUIRQ3SEL_PUBID_DMA_DONE_COMB 0x00000014U 990 #define EVTSVT_CPUIRQ3SEL_PUBID_LGPT1_COMB 0x00000013U 991 #define EVTSVT_CPUIRQ3SEL_PUBID_LGPT0_COMB 0x00000012U 992 #define EVTSVT_CPUIRQ3SEL_PUBID_ADC_COMB 0x00000010U 993 #define EVTSVT_CPUIRQ3SEL_PUBID_SPI0_COMB 0x0000000FU 994 #define EVTSVT_CPUIRQ3SEL_PUBID_LRFD_IRQ2 0x0000000EU 995 #define EVTSVT_CPUIRQ3SEL_PUBID_LRFD_IRQ1 0x0000000DU 996 #define EVTSVT_CPUIRQ3SEL_PUBID_LRFD_IRQ0 0x0000000CU 997 #define EVTSVT_CPUIRQ3SEL_PUBID_FLASH_IRQ 0x0000000BU 998 #define EVTSVT_CPUIRQ3SEL_PUBID_GPIO_COMB 0x00000009U 999 #define EVTSVT_CPUIRQ3SEL_PUBID_SYSTIM_COMB 0x00000008U 1000 #define EVTSVT_CPUIRQ3SEL_PUBID_AON_IOC_COMB 0x00000007U 1001 #define EVTSVT_CPUIRQ3SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 1002 #define EVTSVT_CPUIRQ3SEL_PUBID_AON_DBG_COMB 0x00000005U 1003 #define EVTSVT_CPUIRQ3SEL_PUBID_AON_RTC_COMB 0x00000004U 1004 #define EVTSVT_CPUIRQ3SEL_PUBID_AON_CKM_COMB 0x00000003U 1005 #define EVTSVT_CPUIRQ3SEL_PUBID_AON_PMU_COMB 0x00000002U 1006 #define EVTSVT_CPUIRQ3SEL_PUBID_NONE 0x00000000U 1007 1008 //***************************************************************************** 1009 // 1010 // Register: EVTSVT_O_CPUIRQ4SEL 1011 // 1012 //***************************************************************************** 1013 // Field: [5:0] PUBID 1014 // 1015 // Read/write selection value. 1016 // Writing any other value than values defined by a ENUM may result in 1017 // undefined behavior. 1018 // ENUMs: 1019 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 1020 // found here LGPT3:MIS 1021 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 1022 // found here LGPT2:MIS 1023 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 1024 // found here I2C0:MIS 1025 // UART0_COMB UART0 combined interrupt, interrupt flags are 1026 // found here UART0:MIS 1027 // AES_COMB AES accelerator combined interrupt request, 1028 // interrupt flags can be found here AES:MIS 1029 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 1030 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 1031 // can be found here DMA:REQDONE 1032 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 1033 // found here LGPT1:MIS 1034 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 1035 // found here LGPT0:MIS 1036 // ADC_COMB ADC combined interrupt request, interrupt flags 1037 // can be found here ADC:MIS0 1038 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 1039 // can be found here SPI0:MIS 1040 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 1041 // here LRFDDBELL:MIS2 1042 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 1043 // here LRFDDBELL:MIS1 1044 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 1045 // here LRFDDBELL:MIS0 1046 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 1047 // flash operation has completed, interrupt flags 1048 // can be found here FLASH:MIS 1049 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 1050 // can be found here GPIO:MIS 1051 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 1052 // found here SYSTIM:MIS 1053 // AON_IOC_COMB IOC synchronous combined event, controlled by 1054 // IOC:EVTCFG 1055 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 1056 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 1057 // found here DBGSS:MIS 1058 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 1059 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 1060 // can be found here CKMD:MIS 1061 // AON_PMU_COMB PMU combined interrupt request for BATMON, 1062 // interrupt flags can be found here PMUD:EVENT 1063 // NONE Always inactive 1064 #define EVTSVT_CPUIRQ4SEL_PUBID_W 6U 1065 #define EVTSVT_CPUIRQ4SEL_PUBID_M 0x0000003FU 1066 #define EVTSVT_CPUIRQ4SEL_PUBID_S 0U 1067 #define EVTSVT_CPUIRQ4SEL_PUBID_LGPT3_COMB 0x00000037U 1068 #define EVTSVT_CPUIRQ4SEL_PUBID_LGPT2_COMB 0x00000031U 1069 #define EVTSVT_CPUIRQ4SEL_PUBID_I2C0_IRQ 0x00000018U 1070 #define EVTSVT_CPUIRQ4SEL_PUBID_UART0_COMB 0x00000017U 1071 #define EVTSVT_CPUIRQ4SEL_PUBID_AES_COMB 0x00000016U 1072 #define EVTSVT_CPUIRQ4SEL_PUBID_DMA_ERR 0x00000015U 1073 #define EVTSVT_CPUIRQ4SEL_PUBID_DMA_DONE_COMB 0x00000014U 1074 #define EVTSVT_CPUIRQ4SEL_PUBID_LGPT1_COMB 0x00000013U 1075 #define EVTSVT_CPUIRQ4SEL_PUBID_LGPT0_COMB 0x00000012U 1076 #define EVTSVT_CPUIRQ4SEL_PUBID_ADC_COMB 0x00000010U 1077 #define EVTSVT_CPUIRQ4SEL_PUBID_SPI0_COMB 0x0000000FU 1078 #define EVTSVT_CPUIRQ4SEL_PUBID_LRFD_IRQ2 0x0000000EU 1079 #define EVTSVT_CPUIRQ4SEL_PUBID_LRFD_IRQ1 0x0000000DU 1080 #define EVTSVT_CPUIRQ4SEL_PUBID_LRFD_IRQ0 0x0000000CU 1081 #define EVTSVT_CPUIRQ4SEL_PUBID_FLASH_IRQ 0x0000000BU 1082 #define EVTSVT_CPUIRQ4SEL_PUBID_GPIO_COMB 0x00000009U 1083 #define EVTSVT_CPUIRQ4SEL_PUBID_SYSTIM_COMB 0x00000008U 1084 #define EVTSVT_CPUIRQ4SEL_PUBID_AON_IOC_COMB 0x00000007U 1085 #define EVTSVT_CPUIRQ4SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 1086 #define EVTSVT_CPUIRQ4SEL_PUBID_AON_DBG_COMB 0x00000005U 1087 #define EVTSVT_CPUIRQ4SEL_PUBID_AON_RTC_COMB 0x00000004U 1088 #define EVTSVT_CPUIRQ4SEL_PUBID_AON_CKM_COMB 0x00000003U 1089 #define EVTSVT_CPUIRQ4SEL_PUBID_AON_PMU_COMB 0x00000002U 1090 #define EVTSVT_CPUIRQ4SEL_PUBID_NONE 0x00000000U 1091 1092 //***************************************************************************** 1093 // 1094 // Register: EVTSVT_O_CPUIRQ5SEL 1095 // 1096 //***************************************************************************** 1097 // Field: [5:0] PUBID 1098 // 1099 // Read only selection value 1100 // ENUMs: 1101 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 1102 // can be found here GPIO:MIS 1103 #define EVTSVT_CPUIRQ5SEL_PUBID_W 6U 1104 #define EVTSVT_CPUIRQ5SEL_PUBID_M 0x0000003FU 1105 #define EVTSVT_CPUIRQ5SEL_PUBID_S 0U 1106 #define EVTSVT_CPUIRQ5SEL_PUBID_GPIO_COMB 0x00000009U 1107 1108 //***************************************************************************** 1109 // 1110 // Register: EVTSVT_O_CPUIRQ6SEL 1111 // 1112 //***************************************************************************** 1113 // Field: [5:0] PUBID 1114 // 1115 // Read only selection value 1116 // ENUMs: 1117 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 1118 // here LRFDDBELL:MIS0 1119 #define EVTSVT_CPUIRQ6SEL_PUBID_W 6U 1120 #define EVTSVT_CPUIRQ6SEL_PUBID_M 0x0000003FU 1121 #define EVTSVT_CPUIRQ6SEL_PUBID_S 0U 1122 #define EVTSVT_CPUIRQ6SEL_PUBID_LRFD_IRQ0 0x0000000CU 1123 1124 //***************************************************************************** 1125 // 1126 // Register: EVTSVT_O_CPUIRQ7SEL 1127 // 1128 //***************************************************************************** 1129 // Field: [5:0] PUBID 1130 // 1131 // Read only selection value 1132 // ENUMs: 1133 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 1134 // here LRFDDBELL:MIS1 1135 #define EVTSVT_CPUIRQ7SEL_PUBID_W 6U 1136 #define EVTSVT_CPUIRQ7SEL_PUBID_M 0x0000003FU 1137 #define EVTSVT_CPUIRQ7SEL_PUBID_S 0U 1138 #define EVTSVT_CPUIRQ7SEL_PUBID_LRFD_IRQ1 0x0000000DU 1139 1140 //***************************************************************************** 1141 // 1142 // Register: EVTSVT_O_CPUIRQ8SEL 1143 // 1144 //***************************************************************************** 1145 // Field: [5:0] PUBID 1146 // 1147 // Read only selection value 1148 // ENUMs: 1149 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 1150 // can be found here DMA:REQDONE 1151 #define EVTSVT_CPUIRQ8SEL_PUBID_W 6U 1152 #define EVTSVT_CPUIRQ8SEL_PUBID_M 0x0000003FU 1153 #define EVTSVT_CPUIRQ8SEL_PUBID_S 0U 1154 #define EVTSVT_CPUIRQ8SEL_PUBID_DMA_DONE_COMB 0x00000014U 1155 1156 //***************************************************************************** 1157 // 1158 // Register: EVTSVT_O_CPUIRQ9SEL 1159 // 1160 //***************************************************************************** 1161 // Field: [5:0] PUBID 1162 // 1163 // Read only selection value 1164 // ENUMs: 1165 // AES_COMB AES accelerator combined interrupt request, 1166 // interrupt flags can be found here AES:MIS 1167 #define EVTSVT_CPUIRQ9SEL_PUBID_W 6U 1168 #define EVTSVT_CPUIRQ9SEL_PUBID_M 0x0000003FU 1169 #define EVTSVT_CPUIRQ9SEL_PUBID_S 0U 1170 #define EVTSVT_CPUIRQ9SEL_PUBID_AES_COMB 0x00000016U 1171 1172 //***************************************************************************** 1173 // 1174 // Register: EVTSVT_O_CPUIRQ10SEL 1175 // 1176 //***************************************************************************** 1177 // Field: [5:0] PUBID 1178 // 1179 // Read only selection value 1180 // ENUMs: 1181 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 1182 // can be found here SPI0:MIS 1183 #define EVTSVT_CPUIRQ10SEL_PUBID_W 6U 1184 #define EVTSVT_CPUIRQ10SEL_PUBID_M 0x0000003FU 1185 #define EVTSVT_CPUIRQ10SEL_PUBID_S 0U 1186 #define EVTSVT_CPUIRQ10SEL_PUBID_SPI0_COMB 0x0000000FU 1187 1188 //***************************************************************************** 1189 // 1190 // Register: EVTSVT_O_CPUIRQ11SEL 1191 // 1192 //***************************************************************************** 1193 // Field: [5:0] PUBID 1194 // 1195 // Read only selection value 1196 // ENUMs: 1197 // UART0_COMB UART0 combined interrupt, interrupt flags are 1198 // found here UART0:MIS 1199 #define EVTSVT_CPUIRQ11SEL_PUBID_W 6U 1200 #define EVTSVT_CPUIRQ11SEL_PUBID_M 0x0000003FU 1201 #define EVTSVT_CPUIRQ11SEL_PUBID_S 0U 1202 #define EVTSVT_CPUIRQ11SEL_PUBID_UART0_COMB 0x00000017U 1203 1204 //***************************************************************************** 1205 // 1206 // Register: EVTSVT_O_CPUIRQ12SEL 1207 // 1208 //***************************************************************************** 1209 // Field: [5:0] PUBID 1210 // 1211 // Read only selection value 1212 // ENUMs: 1213 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 1214 // found here I2C0:MIS 1215 #define EVTSVT_CPUIRQ12SEL_PUBID_W 6U 1216 #define EVTSVT_CPUIRQ12SEL_PUBID_M 0x0000003FU 1217 #define EVTSVT_CPUIRQ12SEL_PUBID_S 0U 1218 #define EVTSVT_CPUIRQ12SEL_PUBID_I2C0_IRQ 0x00000018U 1219 1220 //***************************************************************************** 1221 // 1222 // Register: EVTSVT_O_CPUIRQ13SEL 1223 // 1224 //***************************************************************************** 1225 // Field: [5:0] PUBID 1226 // 1227 // Read only selection value 1228 // ENUMs: 1229 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 1230 // found here LGPT0:MIS 1231 #define EVTSVT_CPUIRQ13SEL_PUBID_W 6U 1232 #define EVTSVT_CPUIRQ13SEL_PUBID_M 0x0000003FU 1233 #define EVTSVT_CPUIRQ13SEL_PUBID_S 0U 1234 #define EVTSVT_CPUIRQ13SEL_PUBID_LGPT0_COMB 0x00000012U 1235 1236 //***************************************************************************** 1237 // 1238 // Register: EVTSVT_O_CPUIRQ14SEL 1239 // 1240 //***************************************************************************** 1241 // Field: [5:0] PUBID 1242 // 1243 // Read only selection value 1244 // ENUMs: 1245 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 1246 // found here LGPT1:MIS 1247 #define EVTSVT_CPUIRQ14SEL_PUBID_W 6U 1248 #define EVTSVT_CPUIRQ14SEL_PUBID_M 0x0000003FU 1249 #define EVTSVT_CPUIRQ14SEL_PUBID_S 0U 1250 #define EVTSVT_CPUIRQ14SEL_PUBID_LGPT1_COMB 0x00000013U 1251 1252 //***************************************************************************** 1253 // 1254 // Register: EVTSVT_O_CPUIRQ15SEL 1255 // 1256 //***************************************************************************** 1257 // Field: [5:0] PUBID 1258 // 1259 // Read only selection value 1260 // ENUMs: 1261 // ADC_COMB ADC combined interrupt request, interrupt flags 1262 // can be found here ADC:MIS0 1263 #define EVTSVT_CPUIRQ15SEL_PUBID_W 6U 1264 #define EVTSVT_CPUIRQ15SEL_PUBID_M 0x0000003FU 1265 #define EVTSVT_CPUIRQ15SEL_PUBID_S 0U 1266 #define EVTSVT_CPUIRQ15SEL_PUBID_ADC_COMB 0x00000010U 1267 1268 //***************************************************************************** 1269 // 1270 // Register: EVTSVT_O_CPUIRQ16SEL 1271 // 1272 //***************************************************************************** 1273 // Field: [5:0] PUBID 1274 // 1275 // Read/write selection value. 1276 // Writing any other value than values defined by a ENUM may result in 1277 // undefined behavior. 1278 // ENUMs: 1279 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 1280 // LGPT3:ADCTRG setting 1281 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 1282 // setting 1283 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 1284 // found here LGPT3:MIS 1285 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 1286 // by LGPT3:C2CFG setting 1287 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 1288 // by LGPT3:C1CFG setting 1289 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 1290 // by LGPT3:C0CFG setting 1291 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 1292 // LGPT2:ADCTRG setting 1293 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 1294 // setting 1295 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 1296 // found here LGPT2:MIS 1297 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 1298 // by LGPT2:C2CFG setting 1299 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 1300 // by LGPT2:C1CFG setting 1301 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 1302 // by LGPT2:C0CFG setting 1303 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 1304 // LRFDDBELL:SYSTIMOEV.SRC2 1305 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 1306 // LRFDDBELL:SYSTIMOEV.SRC1 1307 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 1308 // LRFDDBELL:SYSTIMOEV.SRC0 1309 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 1310 // LGPT1:ADCTRG setting 1311 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 1312 // setting 1313 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 1314 // by LGPT1:C2CFG setting 1315 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 1316 // by LGPT1:C1CFG setting 1317 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 1318 // by LGPT1:C0CFG setting 1319 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 1320 // LGPT0:ADCTRG setting 1321 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 1322 // setting 1323 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 1324 // by LGPT0:C2CFG setting 1325 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 1326 // by LGPT0:C1CFG setting 1327 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 1328 // by LGPT0:C0CFG setting 1329 // SYSTIM4 SYSTIM Channel 4 event, event flag is 1330 // SYSTIM:MIS.EVT4 1331 // SYSTIM3 SYSTIM Channel 3 event, event flag is 1332 // SYSTIM:MIS.EVT3 1333 // SYSTIM2 SYSTIM Channel 2 event, event flag is 1334 // SYSTIM:MIS.EVT2 1335 // SYSTIM1 SYSTIM Channel 1 event, event flag is 1336 // SYSTIM:MIS.EVT1 1337 // SYSTIM0 SYSTIM Channel 0 event, event flag is 1338 // SYSTIM:MIS.EVT0 1339 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 1340 // signal to SVT clock 1341 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 1342 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 1343 // found here I2C0:MIS 1344 // UART0_COMB UART0 combined interrupt, interrupt flags are 1345 // found here UART0:MIS 1346 // AES_COMB AES accelerator combined interrupt request, 1347 // interrupt flags can be found here AES:MIS 1348 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 1349 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 1350 // can be found here DMA:REQDONE 1351 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 1352 // found here LGPT1:MIS 1353 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 1354 // found here LGPT0:MIS 1355 // ADC_EVT ADC general published event, interrupt flags can 1356 // be found here ADC:MIS1 1357 // ADC_COMB ADC combined interrupt request, interrupt flags 1358 // can be found here ADC:MIS0 1359 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 1360 // can be found here SPI0:MIS 1361 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 1362 // here LRFDDBELL:MIS2 1363 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 1364 // here LRFDDBELL:MIS1 1365 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 1366 // here LRFDDBELL:MIS0 1367 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 1368 // flash operation has completed, interrupt flags 1369 // can be found here FLASH:MIS 1370 // GPIO_EVT GPIO generic published event, controlled by 1371 // GPIO:EVTCFG 1372 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 1373 // can be found here GPIO:MIS 1374 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 1375 // found here SYSTIM:MIS 1376 // AON_IOC_COMB IOC synchronous combined event, controlled by 1377 // IOC:EVTCFG 1378 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 1379 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 1380 // found here DBGSS:MIS 1381 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 1382 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 1383 // can be found here CKMD:MIS 1384 // AON_PMU_COMB PMU combined interrupt request for BATMON, 1385 // interrupt flags can be found here PMUD:EVENT 1386 // NONE Always inactive 1387 #define EVTSVT_CPUIRQ16SEL_PUBID_W 6U 1388 #define EVTSVT_CPUIRQ16SEL_PUBID_M 0x0000003FU 1389 #define EVTSVT_CPUIRQ16SEL_PUBID_S 0U 1390 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT3_ADC 0x00000039U 1391 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT3_DMA 0x00000038U 1392 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT3_COMB 0x00000037U 1393 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT3C2 0x00000036U 1394 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT3C1 0x00000035U 1395 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT3C0 0x00000034U 1396 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT2_ADC 0x00000033U 1397 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT2_DMA 0x00000032U 1398 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT2_COMB 0x00000031U 1399 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT2C2 0x00000030U 1400 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT2C1 0x0000002FU 1401 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT2C0 0x0000002EU 1402 #define EVTSVT_CPUIRQ16SEL_PUBID_LRFD_EVT2 0x0000002CU 1403 #define EVTSVT_CPUIRQ16SEL_PUBID_LRFD_EVT1 0x0000002BU 1404 #define EVTSVT_CPUIRQ16SEL_PUBID_LRFD_EVT0 0x0000002AU 1405 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT1_ADC 0x00000029U 1406 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT1_DMA 0x00000028U 1407 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT1C2 0x00000027U 1408 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT1C1 0x00000026U 1409 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT1C0 0x00000025U 1410 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT0_ADC 0x00000024U 1411 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT0_DMA 0x00000023U 1412 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT0C2 0x00000022U 1413 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT0C1 0x00000021U 1414 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT0C0 0x00000020U 1415 #define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM4 0x0000001FU 1416 #define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM3 0x0000001EU 1417 #define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM2 0x0000001DU 1418 #define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM1 0x0000001CU 1419 #define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM0 0x0000001BU 1420 #define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM_LT 0x0000001AU 1421 #define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM_HB 0x00000019U 1422 #define EVTSVT_CPUIRQ16SEL_PUBID_I2C0_IRQ 0x00000018U 1423 #define EVTSVT_CPUIRQ16SEL_PUBID_UART0_COMB 0x00000017U 1424 #define EVTSVT_CPUIRQ16SEL_PUBID_AES_COMB 0x00000016U 1425 #define EVTSVT_CPUIRQ16SEL_PUBID_DMA_ERR 0x00000015U 1426 #define EVTSVT_CPUIRQ16SEL_PUBID_DMA_DONE_COMB 0x00000014U 1427 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT1_COMB 0x00000013U 1428 #define EVTSVT_CPUIRQ16SEL_PUBID_LGPT0_COMB 0x00000012U 1429 #define EVTSVT_CPUIRQ16SEL_PUBID_ADC_EVT 0x00000011U 1430 #define EVTSVT_CPUIRQ16SEL_PUBID_ADC_COMB 0x00000010U 1431 #define EVTSVT_CPUIRQ16SEL_PUBID_SPI0_COMB 0x0000000FU 1432 #define EVTSVT_CPUIRQ16SEL_PUBID_LRFD_IRQ2 0x0000000EU 1433 #define EVTSVT_CPUIRQ16SEL_PUBID_LRFD_IRQ1 0x0000000DU 1434 #define EVTSVT_CPUIRQ16SEL_PUBID_LRFD_IRQ0 0x0000000CU 1435 #define EVTSVT_CPUIRQ16SEL_PUBID_FLASH_IRQ 0x0000000BU 1436 #define EVTSVT_CPUIRQ16SEL_PUBID_GPIO_EVT 0x0000000AU 1437 #define EVTSVT_CPUIRQ16SEL_PUBID_GPIO_COMB 0x00000009U 1438 #define EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM_COMB 0x00000008U 1439 #define EVTSVT_CPUIRQ16SEL_PUBID_AON_IOC_COMB 0x00000007U 1440 #define EVTSVT_CPUIRQ16SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 1441 #define EVTSVT_CPUIRQ16SEL_PUBID_AON_DBG_COMB 0x00000005U 1442 #define EVTSVT_CPUIRQ16SEL_PUBID_AON_RTC_COMB 0x00000004U 1443 #define EVTSVT_CPUIRQ16SEL_PUBID_AON_CKM_COMB 0x00000003U 1444 #define EVTSVT_CPUIRQ16SEL_PUBID_AON_PMU_COMB 0x00000002U 1445 #define EVTSVT_CPUIRQ16SEL_PUBID_NONE 0x00000000U 1446 1447 //***************************************************************************** 1448 // 1449 // Register: EVTSVT_O_CPUIRQ17SEL 1450 // 1451 //***************************************************************************** 1452 // Field: [5:0] PUBID 1453 // 1454 // Read only selection value 1455 // ENUMs: 1456 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 1457 // found here LGPT2:MIS 1458 #define EVTSVT_CPUIRQ17SEL_PUBID_W 6U 1459 #define EVTSVT_CPUIRQ17SEL_PUBID_M 0x0000003FU 1460 #define EVTSVT_CPUIRQ17SEL_PUBID_S 0U 1461 #define EVTSVT_CPUIRQ17SEL_PUBID_LGPT2_COMB 0x00000031U 1462 1463 //***************************************************************************** 1464 // 1465 // Register: EVTSVT_O_CPUIRQ18SEL 1466 // 1467 //***************************************************************************** 1468 // Field: [5:0] PUBID 1469 // 1470 // Read only selection value 1471 // ENUMs: 1472 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 1473 // found here LGPT3:MIS 1474 #define EVTSVT_CPUIRQ18SEL_PUBID_W 6U 1475 #define EVTSVT_CPUIRQ18SEL_PUBID_M 0x0000003FU 1476 #define EVTSVT_CPUIRQ18SEL_PUBID_S 0U 1477 #define EVTSVT_CPUIRQ18SEL_PUBID_LGPT3_COMB 0x00000037U 1478 1479 //***************************************************************************** 1480 // 1481 // Register: EVTSVT_O_SYSTIMC0SEL 1482 // 1483 //***************************************************************************** 1484 // Field: [5:0] PUBID 1485 // 1486 // Read only selection value 1487 // ENUMs: 1488 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 1489 #define EVTSVT_SYSTIMC0SEL_PUBID_W 6U 1490 #define EVTSVT_SYSTIMC0SEL_PUBID_M 0x0000003FU 1491 #define EVTSVT_SYSTIMC0SEL_PUBID_S 0U 1492 #define EVTSVT_SYSTIMC0SEL_PUBID_AON_RTC_COMB 0x00000004U 1493 1494 //***************************************************************************** 1495 // 1496 // Register: EVTSVT_O_SYSTIMC1SEL 1497 // 1498 //***************************************************************************** 1499 // Field: [5:0] PUBID 1500 // 1501 // Read/write selection value. 1502 // Writing any other value than values defined by a ENUM may result in 1503 // undefined behavior. 1504 // ENUMs: 1505 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 1506 // LGPT3:ADCTRG setting 1507 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 1508 // setting 1509 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 1510 // found here LGPT3:MIS 1511 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 1512 // by LGPT3:C2CFG setting 1513 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 1514 // by LGPT3:C1CFG setting 1515 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 1516 // by LGPT3:C0CFG setting 1517 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 1518 // LGPT2:ADCTRG setting 1519 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 1520 // setting 1521 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 1522 // found here LGPT2:MIS 1523 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 1524 // by LGPT2:C2CFG setting 1525 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 1526 // by LGPT2:C1CFG setting 1527 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 1528 // by LGPT2:C0CFG setting 1529 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 1530 // LRFDDBELL:SYSTIMOEV.SRC2 1531 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 1532 // LRFDDBELL:SYSTIMOEV.SRC1 1533 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 1534 // LRFDDBELL:SYSTIMOEV.SRC0 1535 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 1536 // LGPT1:ADCTRG setting 1537 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 1538 // setting 1539 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 1540 // by LGPT1:C2CFG setting 1541 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 1542 // by LGPT1:C1CFG setting 1543 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 1544 // by LGPT1:C0CFG setting 1545 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 1546 // LGPT0:ADCTRG setting 1547 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 1548 // setting 1549 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 1550 // by LGPT0:C2CFG setting 1551 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 1552 // by LGPT0:C1CFG setting 1553 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 1554 // by LGPT0:C0CFG setting 1555 // SYSTIM4 SYSTIM Channel 4 event, event flag is 1556 // SYSTIM:MIS.EVT4 1557 // SYSTIM3 SYSTIM Channel 3 event, event flag is 1558 // SYSTIM:MIS.EVT3 1559 // SYSTIM2 SYSTIM Channel 2 event, event flag is 1560 // SYSTIM:MIS.EVT2 1561 // SYSTIM1 SYSTIM Channel 1 event, event flag is 1562 // SYSTIM:MIS.EVT1 1563 // SYSTIM0 SYSTIM Channel 0 event, event flag is 1564 // SYSTIM:MIS.EVT0 1565 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 1566 // signal to SVT clock 1567 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 1568 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 1569 // found here I2C0:MIS 1570 // UART0_COMB UART0 combined interrupt, interrupt flags are 1571 // found here UART0:MIS 1572 // AES_COMB AES accelerator combined interrupt request, 1573 // interrupt flags can be found here AES:MIS 1574 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 1575 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 1576 // can be found here DMA:REQDONE 1577 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 1578 // found here LGPT1:MIS 1579 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 1580 // found here LGPT0:MIS 1581 // ADC_EVT ADC general published event, interrupt flags can 1582 // be found here ADC:MIS1 1583 // ADC_COMB ADC combined interrupt request, interrupt flags 1584 // can be found here ADC:MIS0 1585 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 1586 // can be found here SPI0:MIS 1587 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 1588 // here LRFDDBELL:MIS2 1589 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 1590 // here LRFDDBELL:MIS1 1591 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 1592 // here LRFDDBELL:MIS0 1593 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 1594 // flash operation has completed, interrupt flags 1595 // can be found here FLASH:MIS 1596 // GPIO_EVT GPIO generic published event, controlled by 1597 // GPIO:EVTCFG 1598 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 1599 // can be found here GPIO:MIS 1600 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 1601 // found here SYSTIM:MIS 1602 // AON_IOC_COMB IOC synchronous combined event, controlled by 1603 // IOC:EVTCFG 1604 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 1605 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 1606 // found here DBGSS:MIS 1607 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 1608 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 1609 // can be found here CKMD:MIS 1610 // AON_PMU_COMB PMU combined interrupt request for BATMON, 1611 // interrupt flags can be found here PMUD:EVENT 1612 // NONE Always inactive 1613 #define EVTSVT_SYSTIMC1SEL_PUBID_W 6U 1614 #define EVTSVT_SYSTIMC1SEL_PUBID_M 0x0000003FU 1615 #define EVTSVT_SYSTIMC1SEL_PUBID_S 0U 1616 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT3_ADC 0x00000039U 1617 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT3_DMA 0x00000038U 1618 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT3_COMB 0x00000037U 1619 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT3C2 0x00000036U 1620 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT3C1 0x00000035U 1621 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT3C0 0x00000034U 1622 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT2_ADC 0x00000033U 1623 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT2_DMA 0x00000032U 1624 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT2_COMB 0x00000031U 1625 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT2C2 0x00000030U 1626 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT2C1 0x0000002FU 1627 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT2C0 0x0000002EU 1628 #define EVTSVT_SYSTIMC1SEL_PUBID_LRFD_EVT2 0x0000002CU 1629 #define EVTSVT_SYSTIMC1SEL_PUBID_LRFD_EVT1 0x0000002BU 1630 #define EVTSVT_SYSTIMC1SEL_PUBID_LRFD_EVT0 0x0000002AU 1631 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT1_ADC 0x00000029U 1632 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT1_DMA 0x00000028U 1633 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT1C2 0x00000027U 1634 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT1C1 0x00000026U 1635 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT1C0 0x00000025U 1636 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT0_ADC 0x00000024U 1637 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT0_DMA 0x00000023U 1638 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT0C2 0x00000022U 1639 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT0C1 0x00000021U 1640 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT0C0 0x00000020U 1641 #define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM4 0x0000001FU 1642 #define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM3 0x0000001EU 1643 #define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM2 0x0000001DU 1644 #define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM1 0x0000001CU 1645 #define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM0 0x0000001BU 1646 #define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM_LT 0x0000001AU 1647 #define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM_HB 0x00000019U 1648 #define EVTSVT_SYSTIMC1SEL_PUBID_I2C0_IRQ 0x00000018U 1649 #define EVTSVT_SYSTIMC1SEL_PUBID_UART0_COMB 0x00000017U 1650 #define EVTSVT_SYSTIMC1SEL_PUBID_AES_COMB 0x00000016U 1651 #define EVTSVT_SYSTIMC1SEL_PUBID_DMA_ERR 0x00000015U 1652 #define EVTSVT_SYSTIMC1SEL_PUBID_DMA_DONE_COMB 0x00000014U 1653 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT1_COMB 0x00000013U 1654 #define EVTSVT_SYSTIMC1SEL_PUBID_LGPT0_COMB 0x00000012U 1655 #define EVTSVT_SYSTIMC1SEL_PUBID_ADC_EVT 0x00000011U 1656 #define EVTSVT_SYSTIMC1SEL_PUBID_ADC_COMB 0x00000010U 1657 #define EVTSVT_SYSTIMC1SEL_PUBID_SPI0_COMB 0x0000000FU 1658 #define EVTSVT_SYSTIMC1SEL_PUBID_LRFD_IRQ2 0x0000000EU 1659 #define EVTSVT_SYSTIMC1SEL_PUBID_LRFD_IRQ1 0x0000000DU 1660 #define EVTSVT_SYSTIMC1SEL_PUBID_LRFD_IRQ0 0x0000000CU 1661 #define EVTSVT_SYSTIMC1SEL_PUBID_FLASH_IRQ 0x0000000BU 1662 #define EVTSVT_SYSTIMC1SEL_PUBID_GPIO_EVT 0x0000000AU 1663 #define EVTSVT_SYSTIMC1SEL_PUBID_GPIO_COMB 0x00000009U 1664 #define EVTSVT_SYSTIMC1SEL_PUBID_SYSTIM_COMB 0x00000008U 1665 #define EVTSVT_SYSTIMC1SEL_PUBID_AON_IOC_COMB 0x00000007U 1666 #define EVTSVT_SYSTIMC1SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 1667 #define EVTSVT_SYSTIMC1SEL_PUBID_AON_DBG_COMB 0x00000005U 1668 #define EVTSVT_SYSTIMC1SEL_PUBID_AON_RTC_COMB 0x00000004U 1669 #define EVTSVT_SYSTIMC1SEL_PUBID_AON_CKM_COMB 0x00000003U 1670 #define EVTSVT_SYSTIMC1SEL_PUBID_AON_PMU_COMB 0x00000002U 1671 #define EVTSVT_SYSTIMC1SEL_PUBID_NONE 0x00000000U 1672 1673 //***************************************************************************** 1674 // 1675 // Register: EVTSVT_O_SYSTIMC2SEL 1676 // 1677 //***************************************************************************** 1678 // Field: [5:0] PUBID 1679 // 1680 // Read only selection value 1681 // ENUMs: 1682 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 1683 // LRFDDBELL:SYSTIMOEV.SRC0 1684 #define EVTSVT_SYSTIMC2SEL_PUBID_W 6U 1685 #define EVTSVT_SYSTIMC2SEL_PUBID_M 0x0000003FU 1686 #define EVTSVT_SYSTIMC2SEL_PUBID_S 0U 1687 #define EVTSVT_SYSTIMC2SEL_PUBID_LRFD_EVT0 0x0000002AU 1688 1689 //***************************************************************************** 1690 // 1691 // Register: EVTSVT_O_SYSTIMC3SEL 1692 // 1693 //***************************************************************************** 1694 // Field: [5:0] PUBID 1695 // 1696 // Read only selection value 1697 // ENUMs: 1698 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 1699 // LRFDDBELL:SYSTIMOEV.SRC1 1700 #define EVTSVT_SYSTIMC3SEL_PUBID_W 6U 1701 #define EVTSVT_SYSTIMC3SEL_PUBID_M 0x0000003FU 1702 #define EVTSVT_SYSTIMC3SEL_PUBID_S 0U 1703 #define EVTSVT_SYSTIMC3SEL_PUBID_LRFD_EVT1 0x0000002BU 1704 1705 //***************************************************************************** 1706 // 1707 // Register: EVTSVT_O_SYSTIMC4SEL 1708 // 1709 //***************************************************************************** 1710 // Field: [5:0] PUBID 1711 // 1712 // Read only selection value 1713 // ENUMs: 1714 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 1715 // LRFDDBELL:SYSTIMOEV.SRC2 1716 #define EVTSVT_SYSTIMC4SEL_PUBID_W 6U 1717 #define EVTSVT_SYSTIMC4SEL_PUBID_M 0x0000003FU 1718 #define EVTSVT_SYSTIMC4SEL_PUBID_S 0U 1719 #define EVTSVT_SYSTIMC4SEL_PUBID_LRFD_EVT2 0x0000002CU 1720 1721 //***************************************************************************** 1722 // 1723 // Register: EVTSVT_O_ADCTRGSEL 1724 // 1725 //***************************************************************************** 1726 // Field: [5:0] PUBID 1727 // 1728 // Read/write selection value. 1729 // Writing any other value than values defined by a ENUM may result in 1730 // undefined behavior. 1731 // ENUMs: 1732 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 1733 // LGPT3:ADCTRG setting 1734 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 1735 // setting 1736 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 1737 // found here LGPT3:MIS 1738 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 1739 // by LGPT3:C2CFG setting 1740 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 1741 // by LGPT3:C1CFG setting 1742 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 1743 // by LGPT3:C0CFG setting 1744 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 1745 // LGPT2:ADCTRG setting 1746 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 1747 // setting 1748 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 1749 // found here LGPT2:MIS 1750 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 1751 // by LGPT2:C2CFG setting 1752 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 1753 // by LGPT2:C1CFG setting 1754 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 1755 // by LGPT2:C0CFG setting 1756 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 1757 // LRFDDBELL:SYSTIMOEV.SRC2 1758 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 1759 // LRFDDBELL:SYSTIMOEV.SRC1 1760 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 1761 // LRFDDBELL:SYSTIMOEV.SRC0 1762 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 1763 // LGPT1:ADCTRG setting 1764 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 1765 // setting 1766 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 1767 // by LGPT1:C2CFG setting 1768 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 1769 // by LGPT1:C1CFG setting 1770 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 1771 // by LGPT1:C0CFG setting 1772 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 1773 // LGPT0:ADCTRG setting 1774 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 1775 // setting 1776 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 1777 // by LGPT0:C2CFG setting 1778 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 1779 // by LGPT0:C1CFG setting 1780 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 1781 // by LGPT0:C0CFG setting 1782 // SYSTIM4 SYSTIM Channel 4 event, event flag is 1783 // SYSTIM:MIS.EVT4 1784 // SYSTIM3 SYSTIM Channel 3 event, event flag is 1785 // SYSTIM:MIS.EVT3 1786 // SYSTIM2 SYSTIM Channel 2 event, event flag is 1787 // SYSTIM:MIS.EVT2 1788 // SYSTIM1 SYSTIM Channel 1 event, event flag is 1789 // SYSTIM:MIS.EVT1 1790 // SYSTIM0 SYSTIM Channel 0 event, event flag is 1791 // SYSTIM:MIS.EVT0 1792 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 1793 // signal to SVT clock 1794 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 1795 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 1796 // found here I2C0:MIS 1797 // UART0_COMB UART0 combined interrupt, interrupt flags are 1798 // found here UART0:MIS 1799 // AES_COMB AES accelerator combined interrupt request, 1800 // interrupt flags can be found here AES:MIS 1801 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 1802 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 1803 // can be found here DMA:REQDONE 1804 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 1805 // found here LGPT1:MIS 1806 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 1807 // found here LGPT0:MIS 1808 // ADC_EVT ADC general published event, interrupt flags can 1809 // be found here ADC:MIS1 1810 // ADC_COMB ADC combined interrupt request, interrupt flags 1811 // can be found here ADC:MIS0 1812 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 1813 // can be found here SPI0:MIS 1814 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 1815 // here LRFDDBELL:MIS2 1816 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 1817 // here LRFDDBELL:MIS1 1818 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 1819 // here LRFDDBELL:MIS0 1820 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 1821 // flash operation has completed, interrupt flags 1822 // can be found here FLASH:MIS 1823 // GPIO_EVT GPIO generic published event, controlled by 1824 // GPIO:EVTCFG 1825 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 1826 // can be found here GPIO:MIS 1827 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 1828 // found here SYSTIM:MIS 1829 // AON_IOC_COMB IOC synchronous combined event, controlled by 1830 // IOC:EVTCFG 1831 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 1832 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 1833 // found here DBGSS:MIS 1834 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 1835 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 1836 // can be found here CKMD:MIS 1837 // AON_PMU_COMB PMU combined interrupt request for BATMON, 1838 // interrupt flags can be found here PMUD:EVENT 1839 // NONE Always inactive 1840 #define EVTSVT_ADCTRGSEL_PUBID_W 6U 1841 #define EVTSVT_ADCTRGSEL_PUBID_M 0x0000003FU 1842 #define EVTSVT_ADCTRGSEL_PUBID_S 0U 1843 #define EVTSVT_ADCTRGSEL_PUBID_LGPT3_ADC 0x00000039U 1844 #define EVTSVT_ADCTRGSEL_PUBID_LGPT3_DMA 0x00000038U 1845 #define EVTSVT_ADCTRGSEL_PUBID_LGPT3_COMB 0x00000037U 1846 #define EVTSVT_ADCTRGSEL_PUBID_LGPT3C2 0x00000036U 1847 #define EVTSVT_ADCTRGSEL_PUBID_LGPT3C1 0x00000035U 1848 #define EVTSVT_ADCTRGSEL_PUBID_LGPT3C0 0x00000034U 1849 #define EVTSVT_ADCTRGSEL_PUBID_LGPT2_ADC 0x00000033U 1850 #define EVTSVT_ADCTRGSEL_PUBID_LGPT2_DMA 0x00000032U 1851 #define EVTSVT_ADCTRGSEL_PUBID_LGPT2_COMB 0x00000031U 1852 #define EVTSVT_ADCTRGSEL_PUBID_LGPT2C2 0x00000030U 1853 #define EVTSVT_ADCTRGSEL_PUBID_LGPT2C1 0x0000002FU 1854 #define EVTSVT_ADCTRGSEL_PUBID_LGPT2C0 0x0000002EU 1855 #define EVTSVT_ADCTRGSEL_PUBID_LRFD_EVT2 0x0000002CU 1856 #define EVTSVT_ADCTRGSEL_PUBID_LRFD_EVT1 0x0000002BU 1857 #define EVTSVT_ADCTRGSEL_PUBID_LRFD_EVT0 0x0000002AU 1858 #define EVTSVT_ADCTRGSEL_PUBID_LGPT1_ADC 0x00000029U 1859 #define EVTSVT_ADCTRGSEL_PUBID_LGPT1_DMA 0x00000028U 1860 #define EVTSVT_ADCTRGSEL_PUBID_LGPT1C2 0x00000027U 1861 #define EVTSVT_ADCTRGSEL_PUBID_LGPT1C1 0x00000026U 1862 #define EVTSVT_ADCTRGSEL_PUBID_LGPT1C0 0x00000025U 1863 #define EVTSVT_ADCTRGSEL_PUBID_LGPT0_ADC 0x00000024U 1864 #define EVTSVT_ADCTRGSEL_PUBID_LGPT0_DMA 0x00000023U 1865 #define EVTSVT_ADCTRGSEL_PUBID_LGPT0C2 0x00000022U 1866 #define EVTSVT_ADCTRGSEL_PUBID_LGPT0C1 0x00000021U 1867 #define EVTSVT_ADCTRGSEL_PUBID_LGPT0C0 0x00000020U 1868 #define EVTSVT_ADCTRGSEL_PUBID_SYSTIM4 0x0000001FU 1869 #define EVTSVT_ADCTRGSEL_PUBID_SYSTIM3 0x0000001EU 1870 #define EVTSVT_ADCTRGSEL_PUBID_SYSTIM2 0x0000001DU 1871 #define EVTSVT_ADCTRGSEL_PUBID_SYSTIM1 0x0000001CU 1872 #define EVTSVT_ADCTRGSEL_PUBID_SYSTIM0 0x0000001BU 1873 #define EVTSVT_ADCTRGSEL_PUBID_SYSTIM_LT 0x0000001AU 1874 #define EVTSVT_ADCTRGSEL_PUBID_SYSTIM_HB 0x00000019U 1875 #define EVTSVT_ADCTRGSEL_PUBID_I2C0_IRQ 0x00000018U 1876 #define EVTSVT_ADCTRGSEL_PUBID_UART0_COMB 0x00000017U 1877 #define EVTSVT_ADCTRGSEL_PUBID_AES_COMB 0x00000016U 1878 #define EVTSVT_ADCTRGSEL_PUBID_DMA_ERR 0x00000015U 1879 #define EVTSVT_ADCTRGSEL_PUBID_DMA_DONE_COMB 0x00000014U 1880 #define EVTSVT_ADCTRGSEL_PUBID_LGPT1_COMB 0x00000013U 1881 #define EVTSVT_ADCTRGSEL_PUBID_LGPT0_COMB 0x00000012U 1882 #define EVTSVT_ADCTRGSEL_PUBID_ADC_EVT 0x00000011U 1883 #define EVTSVT_ADCTRGSEL_PUBID_ADC_COMB 0x00000010U 1884 #define EVTSVT_ADCTRGSEL_PUBID_SPI0_COMB 0x0000000FU 1885 #define EVTSVT_ADCTRGSEL_PUBID_LRFD_IRQ2 0x0000000EU 1886 #define EVTSVT_ADCTRGSEL_PUBID_LRFD_IRQ1 0x0000000DU 1887 #define EVTSVT_ADCTRGSEL_PUBID_LRFD_IRQ0 0x0000000CU 1888 #define EVTSVT_ADCTRGSEL_PUBID_FLASH_IRQ 0x0000000BU 1889 #define EVTSVT_ADCTRGSEL_PUBID_GPIO_EVT 0x0000000AU 1890 #define EVTSVT_ADCTRGSEL_PUBID_GPIO_COMB 0x00000009U 1891 #define EVTSVT_ADCTRGSEL_PUBID_SYSTIM_COMB 0x00000008U 1892 #define EVTSVT_ADCTRGSEL_PUBID_AON_IOC_COMB 0x00000007U 1893 #define EVTSVT_ADCTRGSEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 1894 #define EVTSVT_ADCTRGSEL_PUBID_AON_DBG_COMB 0x00000005U 1895 #define EVTSVT_ADCTRGSEL_PUBID_AON_RTC_COMB 0x00000004U 1896 #define EVTSVT_ADCTRGSEL_PUBID_AON_CKM_COMB 0x00000003U 1897 #define EVTSVT_ADCTRGSEL_PUBID_AON_PMU_COMB 0x00000002U 1898 #define EVTSVT_ADCTRGSEL_PUBID_NONE 0x00000000U 1899 1900 //***************************************************************************** 1901 // 1902 // Register: EVTSVT_O_LGPTSYNCSEL 1903 // 1904 //***************************************************************************** 1905 // Field: [5:0] PUBID 1906 // 1907 // Read/write selection value. 1908 // Writing any other value than values defined by a ENUM may result in 1909 // undefined behavior. 1910 // ENUMs: 1911 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 1912 // LGPT3:ADCTRG setting 1913 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 1914 // setting 1915 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 1916 // found here LGPT3:MIS 1917 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 1918 // by LGPT3:C2CFG setting 1919 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 1920 // by LGPT3:C1CFG setting 1921 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 1922 // by LGPT3:C0CFG setting 1923 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 1924 // LGPT2:ADCTRG setting 1925 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 1926 // setting 1927 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 1928 // found here LGPT2:MIS 1929 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 1930 // by LGPT2:C2CFG setting 1931 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 1932 // by LGPT2:C1CFG setting 1933 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 1934 // by LGPT2:C0CFG setting 1935 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 1936 // LRFDDBELL:SYSTIMOEV.SRC2 1937 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 1938 // LRFDDBELL:SYSTIMOEV.SRC1 1939 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 1940 // LRFDDBELL:SYSTIMOEV.SRC0 1941 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 1942 // LGPT1:ADCTRG setting 1943 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 1944 // setting 1945 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 1946 // by LGPT1:C2CFG setting 1947 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 1948 // by LGPT1:C1CFG setting 1949 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 1950 // by LGPT1:C0CFG setting 1951 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 1952 // LGPT0:ADCTRG setting 1953 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 1954 // setting 1955 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 1956 // by LGPT0:C2CFG setting 1957 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 1958 // by LGPT0:C1CFG setting 1959 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 1960 // by LGPT0:C0CFG setting 1961 // SYSTIM4 SYSTIM Channel 4 event, event flag is 1962 // SYSTIM:MIS.EVT4 1963 // SYSTIM3 SYSTIM Channel 3 event, event flag is 1964 // SYSTIM:MIS.EVT3 1965 // SYSTIM2 SYSTIM Channel 2 event, event flag is 1966 // SYSTIM:MIS.EVT2 1967 // SYSTIM1 SYSTIM Channel 1 event, event flag is 1968 // SYSTIM:MIS.EVT1 1969 // SYSTIM0 SYSTIM Channel 0 event, event flag is 1970 // SYSTIM:MIS.EVT0 1971 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 1972 // signal to SVT clock 1973 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 1974 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 1975 // found here I2C0:MIS 1976 // UART0_COMB UART0 combined interrupt, interrupt flags are 1977 // found here UART0:MIS 1978 // AES_COMB AES accelerator combined interrupt request, 1979 // interrupt flags can be found here AES:MIS 1980 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 1981 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 1982 // can be found here DMA:REQDONE 1983 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 1984 // found here LGPT1:MIS 1985 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 1986 // found here LGPT0:MIS 1987 // ADC_EVT ADC general published event, interrupt flags can 1988 // be found here ADC:MIS1 1989 // ADC_COMB ADC combined interrupt request, interrupt flags 1990 // can be found here ADC:MIS0 1991 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 1992 // can be found here SPI0:MIS 1993 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 1994 // here LRFDDBELL:MIS2 1995 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 1996 // here LRFDDBELL:MIS1 1997 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 1998 // here LRFDDBELL:MIS0 1999 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 2000 // flash operation has completed, interrupt flags 2001 // can be found here FLASH:MIS 2002 // GPIO_EVT GPIO generic published event, controlled by 2003 // GPIO:EVTCFG 2004 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 2005 // can be found here GPIO:MIS 2006 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 2007 // found here SYSTIM:MIS 2008 // AON_IOC_COMB IOC synchronous combined event, controlled by 2009 // IOC:EVTCFG 2010 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 2011 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 2012 // found here DBGSS:MIS 2013 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 2014 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 2015 // can be found here CKMD:MIS 2016 // AON_PMU_COMB PMU combined interrupt request for BATMON, 2017 // interrupt flags can be found here PMUD:EVENT 2018 // NONE Always inactive 2019 #define EVTSVT_LGPTSYNCSEL_PUBID_W 6U 2020 #define EVTSVT_LGPTSYNCSEL_PUBID_M 0x0000003FU 2021 #define EVTSVT_LGPTSYNCSEL_PUBID_S 0U 2022 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT3_ADC 0x00000039U 2023 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT3_DMA 0x00000038U 2024 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT3_COMB 0x00000037U 2025 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT3C2 0x00000036U 2026 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT3C1 0x00000035U 2027 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT3C0 0x00000034U 2028 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT2_ADC 0x00000033U 2029 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT2_DMA 0x00000032U 2030 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT2_COMB 0x00000031U 2031 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT2C2 0x00000030U 2032 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT2C1 0x0000002FU 2033 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT2C0 0x0000002EU 2034 #define EVTSVT_LGPTSYNCSEL_PUBID_LRFD_EVT2 0x0000002CU 2035 #define EVTSVT_LGPTSYNCSEL_PUBID_LRFD_EVT1 0x0000002BU 2036 #define EVTSVT_LGPTSYNCSEL_PUBID_LRFD_EVT0 0x0000002AU 2037 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT1_ADC 0x00000029U 2038 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT1_DMA 0x00000028U 2039 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT1C2 0x00000027U 2040 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT1C1 0x00000026U 2041 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT1C0 0x00000025U 2042 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT0_ADC 0x00000024U 2043 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT0_DMA 0x00000023U 2044 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT0C2 0x00000022U 2045 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT0C1 0x00000021U 2046 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT0C0 0x00000020U 2047 #define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM4 0x0000001FU 2048 #define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM3 0x0000001EU 2049 #define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM2 0x0000001DU 2050 #define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM1 0x0000001CU 2051 #define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM0 0x0000001BU 2052 #define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM_LT 0x0000001AU 2053 #define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM_HB 0x00000019U 2054 #define EVTSVT_LGPTSYNCSEL_PUBID_I2C0_IRQ 0x00000018U 2055 #define EVTSVT_LGPTSYNCSEL_PUBID_UART0_COMB 0x00000017U 2056 #define EVTSVT_LGPTSYNCSEL_PUBID_AES_COMB 0x00000016U 2057 #define EVTSVT_LGPTSYNCSEL_PUBID_DMA_ERR 0x00000015U 2058 #define EVTSVT_LGPTSYNCSEL_PUBID_DMA_DONE_COMB 0x00000014U 2059 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT1_COMB 0x00000013U 2060 #define EVTSVT_LGPTSYNCSEL_PUBID_LGPT0_COMB 0x00000012U 2061 #define EVTSVT_LGPTSYNCSEL_PUBID_ADC_EVT 0x00000011U 2062 #define EVTSVT_LGPTSYNCSEL_PUBID_ADC_COMB 0x00000010U 2063 #define EVTSVT_LGPTSYNCSEL_PUBID_SPI0_COMB 0x0000000FU 2064 #define EVTSVT_LGPTSYNCSEL_PUBID_LRFD_IRQ2 0x0000000EU 2065 #define EVTSVT_LGPTSYNCSEL_PUBID_LRFD_IRQ1 0x0000000DU 2066 #define EVTSVT_LGPTSYNCSEL_PUBID_LRFD_IRQ0 0x0000000CU 2067 #define EVTSVT_LGPTSYNCSEL_PUBID_FLASH_IRQ 0x0000000BU 2068 #define EVTSVT_LGPTSYNCSEL_PUBID_GPIO_EVT 0x0000000AU 2069 #define EVTSVT_LGPTSYNCSEL_PUBID_GPIO_COMB 0x00000009U 2070 #define EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM_COMB 0x00000008U 2071 #define EVTSVT_LGPTSYNCSEL_PUBID_AON_IOC_COMB 0x00000007U 2072 #define EVTSVT_LGPTSYNCSEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 2073 #define EVTSVT_LGPTSYNCSEL_PUBID_AON_DBG_COMB 0x00000005U 2074 #define EVTSVT_LGPTSYNCSEL_PUBID_AON_RTC_COMB 0x00000004U 2075 #define EVTSVT_LGPTSYNCSEL_PUBID_AON_CKM_COMB 0x00000003U 2076 #define EVTSVT_LGPTSYNCSEL_PUBID_AON_PMU_COMB 0x00000002U 2077 #define EVTSVT_LGPTSYNCSEL_PUBID_NONE 0x00000000U 2078 2079 //***************************************************************************** 2080 // 2081 // Register: EVTSVT_O_LGPT0IN0SEL 2082 // 2083 //***************************************************************************** 2084 // Field: [5:0] PUBID 2085 // 2086 // Read/write selection value. 2087 // Writing any other value than values defined by a ENUM may result in 2088 // undefined behavior. 2089 // ENUMs: 2090 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 2091 // LGPT3:ADCTRG setting 2092 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 2093 // setting 2094 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 2095 // found here LGPT3:MIS 2096 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 2097 // by LGPT3:C2CFG setting 2098 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 2099 // by LGPT3:C1CFG setting 2100 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 2101 // by LGPT3:C0CFG setting 2102 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 2103 // LGPT2:ADCTRG setting 2104 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 2105 // setting 2106 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 2107 // found here LGPT2:MIS 2108 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 2109 // by LGPT2:C2CFG setting 2110 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 2111 // by LGPT2:C1CFG setting 2112 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 2113 // by LGPT2:C0CFG setting 2114 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 2115 // LRFDDBELL:SYSTIMOEV.SRC2 2116 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 2117 // LRFDDBELL:SYSTIMOEV.SRC1 2118 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 2119 // LRFDDBELL:SYSTIMOEV.SRC0 2120 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 2121 // LGPT1:ADCTRG setting 2122 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 2123 // setting 2124 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 2125 // by LGPT1:C2CFG setting 2126 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 2127 // by LGPT1:C1CFG setting 2128 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 2129 // by LGPT1:C0CFG setting 2130 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 2131 // LGPT0:ADCTRG setting 2132 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 2133 // setting 2134 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 2135 // by LGPT0:C2CFG setting 2136 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 2137 // by LGPT0:C1CFG setting 2138 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 2139 // by LGPT0:C0CFG setting 2140 // SYSTIM4 SYSTIM Channel 4 event, event flag is 2141 // SYSTIM:MIS.EVT4 2142 // SYSTIM3 SYSTIM Channel 3 event, event flag is 2143 // SYSTIM:MIS.EVT3 2144 // SYSTIM2 SYSTIM Channel 2 event, event flag is 2145 // SYSTIM:MIS.EVT2 2146 // SYSTIM1 SYSTIM Channel 1 event, event flag is 2147 // SYSTIM:MIS.EVT1 2148 // SYSTIM0 SYSTIM Channel 0 event, event flag is 2149 // SYSTIM:MIS.EVT0 2150 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 2151 // signal to SVT clock 2152 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 2153 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 2154 // found here I2C0:MIS 2155 // UART0_COMB UART0 combined interrupt, interrupt flags are 2156 // found here UART0:MIS 2157 // AES_COMB AES accelerator combined interrupt request, 2158 // interrupt flags can be found here AES:MIS 2159 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 2160 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 2161 // can be found here DMA:REQDONE 2162 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 2163 // found here LGPT1:MIS 2164 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 2165 // found here LGPT0:MIS 2166 // ADC_EVT ADC general published event, interrupt flags can 2167 // be found here ADC:MIS1 2168 // ADC_COMB ADC combined interrupt request, interrupt flags 2169 // can be found here ADC:MIS0 2170 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 2171 // can be found here SPI0:MIS 2172 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 2173 // here LRFDDBELL:MIS2 2174 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 2175 // here LRFDDBELL:MIS1 2176 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 2177 // here LRFDDBELL:MIS0 2178 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 2179 // flash operation has completed, interrupt flags 2180 // can be found here FLASH:MIS 2181 // GPIO_EVT GPIO generic published event, controlled by 2182 // GPIO:EVTCFG 2183 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 2184 // can be found here GPIO:MIS 2185 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 2186 // found here SYSTIM:MIS 2187 // AON_IOC_COMB IOC synchronous combined event, controlled by 2188 // IOC:EVTCFG 2189 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 2190 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 2191 // found here DBGSS:MIS 2192 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 2193 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 2194 // can be found here CKMD:MIS 2195 // AON_PMU_COMB PMU combined interrupt request for BATMON, 2196 // interrupt flags can be found here PMUD:EVENT 2197 // NONE Always inactive 2198 #define EVTSVT_LGPT0IN0SEL_PUBID_W 6U 2199 #define EVTSVT_LGPT0IN0SEL_PUBID_M 0x0000003FU 2200 #define EVTSVT_LGPT0IN0SEL_PUBID_S 0U 2201 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT3_ADC 0x00000039U 2202 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT3_DMA 0x00000038U 2203 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT3_COMB 0x00000037U 2204 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT3C2 0x00000036U 2205 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT3C1 0x00000035U 2206 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT3C0 0x00000034U 2207 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT2_ADC 0x00000033U 2208 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT2_DMA 0x00000032U 2209 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT2_COMB 0x00000031U 2210 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT2C2 0x00000030U 2211 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT2C1 0x0000002FU 2212 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT2C0 0x0000002EU 2213 #define EVTSVT_LGPT0IN0SEL_PUBID_LRFD_EVT2 0x0000002CU 2214 #define EVTSVT_LGPT0IN0SEL_PUBID_LRFD_EVT1 0x0000002BU 2215 #define EVTSVT_LGPT0IN0SEL_PUBID_LRFD_EVT0 0x0000002AU 2216 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT1_ADC 0x00000029U 2217 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT1_DMA 0x00000028U 2218 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT1C2 0x00000027U 2219 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT1C1 0x00000026U 2220 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT1C0 0x00000025U 2221 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT0_ADC 0x00000024U 2222 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT0_DMA 0x00000023U 2223 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT0C2 0x00000022U 2224 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT0C1 0x00000021U 2225 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT0C0 0x00000020U 2226 #define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM4 0x0000001FU 2227 #define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM3 0x0000001EU 2228 #define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM2 0x0000001DU 2229 #define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM1 0x0000001CU 2230 #define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM0 0x0000001BU 2231 #define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM_LT 0x0000001AU 2232 #define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM_HB 0x00000019U 2233 #define EVTSVT_LGPT0IN0SEL_PUBID_I2C0_IRQ 0x00000018U 2234 #define EVTSVT_LGPT0IN0SEL_PUBID_UART0_COMB 0x00000017U 2235 #define EVTSVT_LGPT0IN0SEL_PUBID_AES_COMB 0x00000016U 2236 #define EVTSVT_LGPT0IN0SEL_PUBID_DMA_ERR 0x00000015U 2237 #define EVTSVT_LGPT0IN0SEL_PUBID_DMA_DONE_COMB 0x00000014U 2238 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT1_COMB 0x00000013U 2239 #define EVTSVT_LGPT0IN0SEL_PUBID_LGPT0_COMB 0x00000012U 2240 #define EVTSVT_LGPT0IN0SEL_PUBID_ADC_EVT 0x00000011U 2241 #define EVTSVT_LGPT0IN0SEL_PUBID_ADC_COMB 0x00000010U 2242 #define EVTSVT_LGPT0IN0SEL_PUBID_SPI0_COMB 0x0000000FU 2243 #define EVTSVT_LGPT0IN0SEL_PUBID_LRFD_IRQ2 0x0000000EU 2244 #define EVTSVT_LGPT0IN0SEL_PUBID_LRFD_IRQ1 0x0000000DU 2245 #define EVTSVT_LGPT0IN0SEL_PUBID_LRFD_IRQ0 0x0000000CU 2246 #define EVTSVT_LGPT0IN0SEL_PUBID_FLASH_IRQ 0x0000000BU 2247 #define EVTSVT_LGPT0IN0SEL_PUBID_GPIO_EVT 0x0000000AU 2248 #define EVTSVT_LGPT0IN0SEL_PUBID_GPIO_COMB 0x00000009U 2249 #define EVTSVT_LGPT0IN0SEL_PUBID_SYSTIM_COMB 0x00000008U 2250 #define EVTSVT_LGPT0IN0SEL_PUBID_AON_IOC_COMB 0x00000007U 2251 #define EVTSVT_LGPT0IN0SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 2252 #define EVTSVT_LGPT0IN0SEL_PUBID_AON_DBG_COMB 0x00000005U 2253 #define EVTSVT_LGPT0IN0SEL_PUBID_AON_RTC_COMB 0x00000004U 2254 #define EVTSVT_LGPT0IN0SEL_PUBID_AON_CKM_COMB 0x00000003U 2255 #define EVTSVT_LGPT0IN0SEL_PUBID_AON_PMU_COMB 0x00000002U 2256 #define EVTSVT_LGPT0IN0SEL_PUBID_NONE 0x00000000U 2257 2258 //***************************************************************************** 2259 // 2260 // Register: EVTSVT_O_LGPT0IN1SEL 2261 // 2262 //***************************************************************************** 2263 // Field: [5:0] PUBID 2264 // 2265 // Read/write selection value. 2266 // Writing any other value than values defined by a ENUM may result in 2267 // undefined behavior. 2268 // ENUMs: 2269 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 2270 // LGPT3:ADCTRG setting 2271 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 2272 // setting 2273 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 2274 // by LGPT3:C2CFG setting 2275 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 2276 // by LGPT3:C1CFG setting 2277 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 2278 // by LGPT3:C0CFG setting 2279 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 2280 // LGPT2:ADCTRG setting 2281 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 2282 // setting 2283 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 2284 // by LGPT2:C2CFG setting 2285 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 2286 // by LGPT2:C1CFG setting 2287 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 2288 // by LGPT2:C0CFG setting 2289 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 2290 // LRFDDBELL:SYSTIMOEV.SRC2 2291 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 2292 // LRFDDBELL:SYSTIMOEV.SRC1 2293 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 2294 // LRFDDBELL:SYSTIMOEV.SRC0 2295 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 2296 // LGPT1:ADCTRG setting 2297 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 2298 // setting 2299 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 2300 // by LGPT1:C2CFG setting 2301 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 2302 // by LGPT1:C1CFG setting 2303 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 2304 // by LGPT1:C0CFG setting 2305 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 2306 // LGPT0:ADCTRG setting 2307 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 2308 // setting 2309 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 2310 // by LGPT0:C2CFG setting 2311 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 2312 // by LGPT0:C1CFG setting 2313 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 2314 // by LGPT0:C0CFG setting 2315 // SYSTIM4 SYSTIM Channel 4 event, event flag is 2316 // SYSTIM:MIS.EVT4 2317 // SYSTIM3 SYSTIM Channel 3 event, event flag is 2318 // SYSTIM:MIS.EVT3 2319 // SYSTIM2 SYSTIM Channel 2 event, event flag is 2320 // SYSTIM:MIS.EVT2 2321 // SYSTIM1 SYSTIM Channel 1 event, event flag is 2322 // SYSTIM:MIS.EVT1 2323 // SYSTIM0 SYSTIM Channel 0 event, event flag is 2324 // SYSTIM:MIS.EVT0 2325 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 2326 // signal to SVT clock 2327 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 2328 // ADC_EVT ADC general published event, interrupt flags can 2329 // be found here ADC:MIS1 2330 // GPIO_EVT GPIO generic published event, controlled by 2331 // GPIO:EVTCFG 2332 // NONE Always inactive 2333 #define EVTSVT_LGPT0IN1SEL_PUBID_W 6U 2334 #define EVTSVT_LGPT0IN1SEL_PUBID_M 0x0000003FU 2335 #define EVTSVT_LGPT0IN1SEL_PUBID_S 0U 2336 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT3_ADC 0x00000039U 2337 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT3_DMA 0x00000038U 2338 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT3C2 0x00000036U 2339 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT3C1 0x00000035U 2340 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT3C0 0x00000034U 2341 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT2_ADC 0x00000033U 2342 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT2_DMA 0x00000032U 2343 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT2C2 0x00000030U 2344 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT2C1 0x0000002FU 2345 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT2C0 0x0000002EU 2346 #define EVTSVT_LGPT0IN1SEL_PUBID_LRFD_EVT2 0x0000002CU 2347 #define EVTSVT_LGPT0IN1SEL_PUBID_LRFD_EVT1 0x0000002BU 2348 #define EVTSVT_LGPT0IN1SEL_PUBID_LRFD_EVT0 0x0000002AU 2349 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT1_ADC 0x00000029U 2350 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT1_DMA 0x00000028U 2351 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT1C2 0x00000027U 2352 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT1C1 0x00000026U 2353 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT1C0 0x00000025U 2354 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT0_ADC 0x00000024U 2355 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT0_DMA 0x00000023U 2356 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT0C2 0x00000022U 2357 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT0C1 0x00000021U 2358 #define EVTSVT_LGPT0IN1SEL_PUBID_LGPT0C0 0x00000020U 2359 #define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM4 0x0000001FU 2360 #define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM3 0x0000001EU 2361 #define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM2 0x0000001DU 2362 #define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM1 0x0000001CU 2363 #define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM0 0x0000001BU 2364 #define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM_LT 0x0000001AU 2365 #define EVTSVT_LGPT0IN1SEL_PUBID_SYSTIM_HB 0x00000019U 2366 #define EVTSVT_LGPT0IN1SEL_PUBID_ADC_EVT 0x00000011U 2367 #define EVTSVT_LGPT0IN1SEL_PUBID_GPIO_EVT 0x0000000AU 2368 #define EVTSVT_LGPT0IN1SEL_PUBID_NONE 0x00000000U 2369 2370 //***************************************************************************** 2371 // 2372 // Register: EVTSVT_O_LGPT0IN2SEL 2373 // 2374 //***************************************************************************** 2375 // Field: [5:0] PUBID 2376 // 2377 // Read/write selection value. 2378 // Writing any other value than values defined by a ENUM may result in 2379 // undefined behavior. 2380 // ENUMs: 2381 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 2382 // LGPT3:ADCTRG setting 2383 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 2384 // setting 2385 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 2386 // by LGPT3:C2CFG setting 2387 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 2388 // by LGPT3:C1CFG setting 2389 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 2390 // by LGPT3:C0CFG setting 2391 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 2392 // LGPT2:ADCTRG setting 2393 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 2394 // setting 2395 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 2396 // by LGPT2:C2CFG setting 2397 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 2398 // by LGPT2:C1CFG setting 2399 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 2400 // by LGPT2:C0CFG setting 2401 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 2402 // LRFDDBELL:SYSTIMOEV.SRC2 2403 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 2404 // LRFDDBELL:SYSTIMOEV.SRC1 2405 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 2406 // LRFDDBELL:SYSTIMOEV.SRC0 2407 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 2408 // LGPT1:ADCTRG setting 2409 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 2410 // setting 2411 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 2412 // by LGPT1:C2CFG setting 2413 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 2414 // by LGPT1:C1CFG setting 2415 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 2416 // by LGPT1:C0CFG setting 2417 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 2418 // LGPT0:ADCTRG setting 2419 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 2420 // setting 2421 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 2422 // by LGPT0:C2CFG setting 2423 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 2424 // by LGPT0:C1CFG setting 2425 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 2426 // by LGPT0:C0CFG setting 2427 // SYSTIM4 SYSTIM Channel 4 event, event flag is 2428 // SYSTIM:MIS.EVT4 2429 // SYSTIM3 SYSTIM Channel 3 event, event flag is 2430 // SYSTIM:MIS.EVT3 2431 // SYSTIM2 SYSTIM Channel 2 event, event flag is 2432 // SYSTIM:MIS.EVT2 2433 // SYSTIM1 SYSTIM Channel 1 event, event flag is 2434 // SYSTIM:MIS.EVT1 2435 // SYSTIM0 SYSTIM Channel 0 event, event flag is 2436 // SYSTIM:MIS.EVT0 2437 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 2438 // signal to SVT clock 2439 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 2440 // ADC_EVT ADC general published event, interrupt flags can 2441 // be found here ADC:MIS1 2442 // GPIO_EVT GPIO generic published event, controlled by 2443 // GPIO:EVTCFG 2444 // NONE Always inactive 2445 #define EVTSVT_LGPT0IN2SEL_PUBID_W 6U 2446 #define EVTSVT_LGPT0IN2SEL_PUBID_M 0x0000003FU 2447 #define EVTSVT_LGPT0IN2SEL_PUBID_S 0U 2448 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT3_ADC 0x00000039U 2449 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT3_DMA 0x00000038U 2450 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT3C2 0x00000036U 2451 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT3C1 0x00000035U 2452 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT3C0 0x00000034U 2453 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT2_ADC 0x00000033U 2454 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT2_DMA 0x00000032U 2455 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT2C2 0x00000030U 2456 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT2C1 0x0000002FU 2457 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT2C0 0x0000002EU 2458 #define EVTSVT_LGPT0IN2SEL_PUBID_LRFD_EVT2 0x0000002CU 2459 #define EVTSVT_LGPT0IN2SEL_PUBID_LRFD_EVT1 0x0000002BU 2460 #define EVTSVT_LGPT0IN2SEL_PUBID_LRFD_EVT0 0x0000002AU 2461 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT1_ADC 0x00000029U 2462 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT1_DMA 0x00000028U 2463 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT1C2 0x00000027U 2464 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT1C1 0x00000026U 2465 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT1C0 0x00000025U 2466 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT0_ADC 0x00000024U 2467 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT0_DMA 0x00000023U 2468 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT0C2 0x00000022U 2469 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT0C1 0x00000021U 2470 #define EVTSVT_LGPT0IN2SEL_PUBID_LGPT0C0 0x00000020U 2471 #define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM4 0x0000001FU 2472 #define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM3 0x0000001EU 2473 #define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM2 0x0000001DU 2474 #define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM1 0x0000001CU 2475 #define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM0 0x0000001BU 2476 #define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM_LT 0x0000001AU 2477 #define EVTSVT_LGPT0IN2SEL_PUBID_SYSTIM_HB 0x00000019U 2478 #define EVTSVT_LGPT0IN2SEL_PUBID_ADC_EVT 0x00000011U 2479 #define EVTSVT_LGPT0IN2SEL_PUBID_GPIO_EVT 0x0000000AU 2480 #define EVTSVT_LGPT0IN2SEL_PUBID_NONE 0x00000000U 2481 2482 //***************************************************************************** 2483 // 2484 // Register: EVTSVT_O_LGPT0TENSEL 2485 // 2486 //***************************************************************************** 2487 // Field: [5:0] PUBID 2488 // 2489 // Read/write selection value. 2490 // Writing any other value than values defined by a ENUM may result in 2491 // undefined behavior. 2492 // ENUMs: 2493 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 2494 // LGPT3:ADCTRG setting 2495 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 2496 // setting 2497 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 2498 // by LGPT3:C2CFG setting 2499 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 2500 // by LGPT3:C1CFG setting 2501 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 2502 // by LGPT3:C0CFG setting 2503 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 2504 // LGPT2:ADCTRG setting 2505 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 2506 // setting 2507 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 2508 // by LGPT2:C2CFG setting 2509 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 2510 // by LGPT2:C1CFG setting 2511 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 2512 // by LGPT2:C0CFG setting 2513 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 2514 // LRFDDBELL:SYSTIMOEV.SRC2 2515 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 2516 // LRFDDBELL:SYSTIMOEV.SRC1 2517 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 2518 // LRFDDBELL:SYSTIMOEV.SRC0 2519 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 2520 // LGPT1:ADCTRG setting 2521 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 2522 // setting 2523 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 2524 // by LGPT1:C2CFG setting 2525 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 2526 // by LGPT1:C1CFG setting 2527 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 2528 // by LGPT1:C0CFG setting 2529 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 2530 // LGPT0:ADCTRG setting 2531 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 2532 // setting 2533 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 2534 // by LGPT0:C2CFG setting 2535 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 2536 // by LGPT0:C1CFG setting 2537 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 2538 // by LGPT0:C0CFG setting 2539 // SYSTIM4 SYSTIM Channel 4 event, event flag is 2540 // SYSTIM:MIS.EVT4 2541 // SYSTIM3 SYSTIM Channel 3 event, event flag is 2542 // SYSTIM:MIS.EVT3 2543 // SYSTIM2 SYSTIM Channel 2 event, event flag is 2544 // SYSTIM:MIS.EVT2 2545 // SYSTIM1 SYSTIM Channel 1 event, event flag is 2546 // SYSTIM:MIS.EVT1 2547 // SYSTIM0 SYSTIM Channel 0 event, event flag is 2548 // SYSTIM:MIS.EVT0 2549 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 2550 // signal to SVT clock 2551 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 2552 // ADC_EVT ADC general published event, interrupt flags can 2553 // be found here ADC:MIS1 2554 // GPIO_EVT GPIO generic published event, controlled by 2555 // GPIO:EVTCFG 2556 // NONE Always inactive 2557 #define EVTSVT_LGPT0TENSEL_PUBID_W 6U 2558 #define EVTSVT_LGPT0TENSEL_PUBID_M 0x0000003FU 2559 #define EVTSVT_LGPT0TENSEL_PUBID_S 0U 2560 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT3_ADC 0x00000039U 2561 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT3_DMA 0x00000038U 2562 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT3C2 0x00000036U 2563 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT3C1 0x00000035U 2564 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT3C0 0x00000034U 2565 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT2_ADC 0x00000033U 2566 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT2_DMA 0x00000032U 2567 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT2C2 0x00000030U 2568 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT2C1 0x0000002FU 2569 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT2C0 0x0000002EU 2570 #define EVTSVT_LGPT0TENSEL_PUBID_LRFD_EVT2 0x0000002CU 2571 #define EVTSVT_LGPT0TENSEL_PUBID_LRFD_EVT1 0x0000002BU 2572 #define EVTSVT_LGPT0TENSEL_PUBID_LRFD_EVT0 0x0000002AU 2573 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT1_ADC 0x00000029U 2574 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT1_DMA 0x00000028U 2575 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT1C2 0x00000027U 2576 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT1C1 0x00000026U 2577 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT1C0 0x00000025U 2578 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT0_ADC 0x00000024U 2579 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT0_DMA 0x00000023U 2580 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT0C2 0x00000022U 2581 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT0C1 0x00000021U 2582 #define EVTSVT_LGPT0TENSEL_PUBID_LGPT0C0 0x00000020U 2583 #define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM4 0x0000001FU 2584 #define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM3 0x0000001EU 2585 #define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM2 0x0000001DU 2586 #define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM1 0x0000001CU 2587 #define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM0 0x0000001BU 2588 #define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM_LT 0x0000001AU 2589 #define EVTSVT_LGPT0TENSEL_PUBID_SYSTIM_HB 0x00000019U 2590 #define EVTSVT_LGPT0TENSEL_PUBID_ADC_EVT 0x00000011U 2591 #define EVTSVT_LGPT0TENSEL_PUBID_GPIO_EVT 0x0000000AU 2592 #define EVTSVT_LGPT0TENSEL_PUBID_NONE 0x00000000U 2593 2594 //***************************************************************************** 2595 // 2596 // Register: EVTSVT_O_LGPT1IN0SEL 2597 // 2598 //***************************************************************************** 2599 // Field: [5:0] PUBID 2600 // 2601 // Read/write selection value. 2602 // Writing any other value than values defined by a ENUM may result in 2603 // undefined behavior. 2604 // ENUMs: 2605 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 2606 // LGPT3:ADCTRG setting 2607 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 2608 // setting 2609 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 2610 // found here LGPT3:MIS 2611 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 2612 // by LGPT3:C2CFG setting 2613 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 2614 // by LGPT3:C1CFG setting 2615 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 2616 // by LGPT3:C0CFG setting 2617 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 2618 // LGPT2:ADCTRG setting 2619 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 2620 // setting 2621 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 2622 // found here LGPT2:MIS 2623 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 2624 // by LGPT2:C2CFG setting 2625 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 2626 // by LGPT2:C1CFG setting 2627 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 2628 // by LGPT2:C0CFG setting 2629 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 2630 // LRFDDBELL:SYSTIMOEV.SRC2 2631 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 2632 // LRFDDBELL:SYSTIMOEV.SRC1 2633 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 2634 // LRFDDBELL:SYSTIMOEV.SRC0 2635 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 2636 // LGPT1:ADCTRG setting 2637 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 2638 // setting 2639 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 2640 // by LGPT1:C2CFG setting 2641 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 2642 // by LGPT1:C1CFG setting 2643 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 2644 // by LGPT1:C0CFG setting 2645 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 2646 // LGPT0:ADCTRG setting 2647 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 2648 // setting 2649 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 2650 // by LGPT0:C2CFG setting 2651 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 2652 // by LGPT0:C1CFG setting 2653 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 2654 // by LGPT0:C0CFG setting 2655 // SYSTIM4 SYSTIM Channel 4 event, event flag is 2656 // SYSTIM:MIS.EVT4 2657 // SYSTIM3 SYSTIM Channel 3 event, event flag is 2658 // SYSTIM:MIS.EVT3 2659 // SYSTIM2 SYSTIM Channel 2 event, event flag is 2660 // SYSTIM:MIS.EVT2 2661 // SYSTIM1 SYSTIM Channel 1 event, event flag is 2662 // SYSTIM:MIS.EVT1 2663 // SYSTIM0 SYSTIM Channel 0 event, event flag is 2664 // SYSTIM:MIS.EVT0 2665 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 2666 // signal to SVT clock 2667 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 2668 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 2669 // found here I2C0:MIS 2670 // UART0_COMB UART0 combined interrupt, interrupt flags are 2671 // found here UART0:MIS 2672 // AES_COMB AES accelerator combined interrupt request, 2673 // interrupt flags can be found here AES:MIS 2674 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 2675 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 2676 // can be found here DMA:REQDONE 2677 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 2678 // found here LGPT1:MIS 2679 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 2680 // found here LGPT0:MIS 2681 // ADC_EVT ADC general published event, interrupt flags can 2682 // be found here ADC:MIS1 2683 // ADC_COMB ADC combined interrupt request, interrupt flags 2684 // can be found here ADC:MIS0 2685 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 2686 // can be found here SPI0:MIS 2687 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 2688 // here LRFDDBELL:MIS2 2689 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 2690 // here LRFDDBELL:MIS1 2691 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 2692 // here LRFDDBELL:MIS0 2693 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 2694 // flash operation has completed, interrupt flags 2695 // can be found here FLASH:MIS 2696 // GPIO_EVT GPIO generic published event, controlled by 2697 // GPIO:EVTCFG 2698 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 2699 // can be found here GPIO:MIS 2700 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 2701 // found here SYSTIM:MIS 2702 // AON_IOC_COMB IOC synchronous combined event, controlled by 2703 // IOC:EVTCFG 2704 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 2705 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 2706 // found here DBGSS:MIS 2707 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 2708 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 2709 // can be found here CKMD:MIS 2710 // AON_PMU_COMB PMU combined interrupt request for BATMON, 2711 // interrupt flags can be found here PMUD:EVENT 2712 // NONE Always inactive 2713 #define EVTSVT_LGPT1IN0SEL_PUBID_W 6U 2714 #define EVTSVT_LGPT1IN0SEL_PUBID_M 0x0000003FU 2715 #define EVTSVT_LGPT1IN0SEL_PUBID_S 0U 2716 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT3_ADC 0x00000039U 2717 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT3_DMA 0x00000038U 2718 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT3_COMB 0x00000037U 2719 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT3C2 0x00000036U 2720 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT3C1 0x00000035U 2721 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT3C0 0x00000034U 2722 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT2_ADC 0x00000033U 2723 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT2_DMA 0x00000032U 2724 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT2_COMB 0x00000031U 2725 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT2C2 0x00000030U 2726 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT2C1 0x0000002FU 2727 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT2C0 0x0000002EU 2728 #define EVTSVT_LGPT1IN0SEL_PUBID_LRFD_EVT2 0x0000002CU 2729 #define EVTSVT_LGPT1IN0SEL_PUBID_LRFD_EVT1 0x0000002BU 2730 #define EVTSVT_LGPT1IN0SEL_PUBID_LRFD_EVT0 0x0000002AU 2731 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT1_ADC 0x00000029U 2732 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT1_DMA 0x00000028U 2733 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT1C2 0x00000027U 2734 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT1C1 0x00000026U 2735 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT1C0 0x00000025U 2736 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT0_ADC 0x00000024U 2737 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT0_DMA 0x00000023U 2738 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT0C2 0x00000022U 2739 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT0C1 0x00000021U 2740 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT0C0 0x00000020U 2741 #define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM4 0x0000001FU 2742 #define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM3 0x0000001EU 2743 #define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM2 0x0000001DU 2744 #define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM1 0x0000001CU 2745 #define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM0 0x0000001BU 2746 #define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM_LT 0x0000001AU 2747 #define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM_HB 0x00000019U 2748 #define EVTSVT_LGPT1IN0SEL_PUBID_I2C0_IRQ 0x00000018U 2749 #define EVTSVT_LGPT1IN0SEL_PUBID_UART0_COMB 0x00000017U 2750 #define EVTSVT_LGPT1IN0SEL_PUBID_AES_COMB 0x00000016U 2751 #define EVTSVT_LGPT1IN0SEL_PUBID_DMA_ERR 0x00000015U 2752 #define EVTSVT_LGPT1IN0SEL_PUBID_DMA_DONE_COMB 0x00000014U 2753 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT1_COMB 0x00000013U 2754 #define EVTSVT_LGPT1IN0SEL_PUBID_LGPT0_COMB 0x00000012U 2755 #define EVTSVT_LGPT1IN0SEL_PUBID_ADC_EVT 0x00000011U 2756 #define EVTSVT_LGPT1IN0SEL_PUBID_ADC_COMB 0x00000010U 2757 #define EVTSVT_LGPT1IN0SEL_PUBID_SPI0_COMB 0x0000000FU 2758 #define EVTSVT_LGPT1IN0SEL_PUBID_LRFD_IRQ2 0x0000000EU 2759 #define EVTSVT_LGPT1IN0SEL_PUBID_LRFD_IRQ1 0x0000000DU 2760 #define EVTSVT_LGPT1IN0SEL_PUBID_LRFD_IRQ0 0x0000000CU 2761 #define EVTSVT_LGPT1IN0SEL_PUBID_FLASH_IRQ 0x0000000BU 2762 #define EVTSVT_LGPT1IN0SEL_PUBID_GPIO_EVT 0x0000000AU 2763 #define EVTSVT_LGPT1IN0SEL_PUBID_GPIO_COMB 0x00000009U 2764 #define EVTSVT_LGPT1IN0SEL_PUBID_SYSTIM_COMB 0x00000008U 2765 #define EVTSVT_LGPT1IN0SEL_PUBID_AON_IOC_COMB 0x00000007U 2766 #define EVTSVT_LGPT1IN0SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 2767 #define EVTSVT_LGPT1IN0SEL_PUBID_AON_DBG_COMB 0x00000005U 2768 #define EVTSVT_LGPT1IN0SEL_PUBID_AON_RTC_COMB 0x00000004U 2769 #define EVTSVT_LGPT1IN0SEL_PUBID_AON_CKM_COMB 0x00000003U 2770 #define EVTSVT_LGPT1IN0SEL_PUBID_AON_PMU_COMB 0x00000002U 2771 #define EVTSVT_LGPT1IN0SEL_PUBID_NONE 0x00000000U 2772 2773 //***************************************************************************** 2774 // 2775 // Register: EVTSVT_O_LGPT1IN1SEL 2776 // 2777 //***************************************************************************** 2778 // Field: [5:0] PUBID 2779 // 2780 // Read/write selection value. 2781 // Writing any other value than values defined by a ENUM may result in 2782 // undefined behavior. 2783 // ENUMs: 2784 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 2785 // LGPT3:ADCTRG setting 2786 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 2787 // setting 2788 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 2789 // by LGPT3:C2CFG setting 2790 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 2791 // by LGPT3:C1CFG setting 2792 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 2793 // by LGPT3:C0CFG setting 2794 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 2795 // LGPT2:ADCTRG setting 2796 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 2797 // setting 2798 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 2799 // by LGPT2:C2CFG setting 2800 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 2801 // by LGPT2:C1CFG setting 2802 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 2803 // by LGPT2:C0CFG setting 2804 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 2805 // LRFDDBELL:SYSTIMOEV.SRC2 2806 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 2807 // LRFDDBELL:SYSTIMOEV.SRC1 2808 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 2809 // LRFDDBELL:SYSTIMOEV.SRC0 2810 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 2811 // LGPT1:ADCTRG setting 2812 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 2813 // setting 2814 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 2815 // by LGPT1:C2CFG setting 2816 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 2817 // by LGPT1:C1CFG setting 2818 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 2819 // by LGPT1:C0CFG setting 2820 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 2821 // LGPT0:ADCTRG setting 2822 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 2823 // setting 2824 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 2825 // by LGPT0:C2CFG setting 2826 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 2827 // by LGPT0:C1CFG setting 2828 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 2829 // by LGPT0:C0CFG setting 2830 // SYSTIM4 SYSTIM Channel 4 event, event flag is 2831 // SYSTIM:MIS.EVT4 2832 // SYSTIM3 SYSTIM Channel 3 event, event flag is 2833 // SYSTIM:MIS.EVT3 2834 // SYSTIM2 SYSTIM Channel 2 event, event flag is 2835 // SYSTIM:MIS.EVT2 2836 // SYSTIM1 SYSTIM Channel 1 event, event flag is 2837 // SYSTIM:MIS.EVT1 2838 // SYSTIM0 SYSTIM Channel 0 event, event flag is 2839 // SYSTIM:MIS.EVT0 2840 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 2841 // signal to SVT clock 2842 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 2843 // ADC_EVT ADC general published event, interrupt flags can 2844 // be found here ADC:MIS1 2845 // GPIO_EVT GPIO generic published event, controlled by 2846 // GPIO:EVTCFG 2847 // NONE Always inactive 2848 #define EVTSVT_LGPT1IN1SEL_PUBID_W 6U 2849 #define EVTSVT_LGPT1IN1SEL_PUBID_M 0x0000003FU 2850 #define EVTSVT_LGPT1IN1SEL_PUBID_S 0U 2851 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT3_ADC 0x00000039U 2852 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT3_DMA 0x00000038U 2853 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT3C2 0x00000036U 2854 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT3C1 0x00000035U 2855 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT3C0 0x00000034U 2856 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT2_ADC 0x00000033U 2857 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT2_DMA 0x00000032U 2858 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT2C2 0x00000030U 2859 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT2C1 0x0000002FU 2860 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT2C0 0x0000002EU 2861 #define EVTSVT_LGPT1IN1SEL_PUBID_LRFD_EVT2 0x0000002CU 2862 #define EVTSVT_LGPT1IN1SEL_PUBID_LRFD_EVT1 0x0000002BU 2863 #define EVTSVT_LGPT1IN1SEL_PUBID_LRFD_EVT0 0x0000002AU 2864 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT1_ADC 0x00000029U 2865 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT1_DMA 0x00000028U 2866 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT1C2 0x00000027U 2867 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT1C1 0x00000026U 2868 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT1C0 0x00000025U 2869 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT0_ADC 0x00000024U 2870 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT0_DMA 0x00000023U 2871 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT0C2 0x00000022U 2872 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT0C1 0x00000021U 2873 #define EVTSVT_LGPT1IN1SEL_PUBID_LGPT0C0 0x00000020U 2874 #define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM4 0x0000001FU 2875 #define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM3 0x0000001EU 2876 #define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM2 0x0000001DU 2877 #define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM1 0x0000001CU 2878 #define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM0 0x0000001BU 2879 #define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM_LT 0x0000001AU 2880 #define EVTSVT_LGPT1IN1SEL_PUBID_SYSTIM_HB 0x00000019U 2881 #define EVTSVT_LGPT1IN1SEL_PUBID_ADC_EVT 0x00000011U 2882 #define EVTSVT_LGPT1IN1SEL_PUBID_GPIO_EVT 0x0000000AU 2883 #define EVTSVT_LGPT1IN1SEL_PUBID_NONE 0x00000000U 2884 2885 //***************************************************************************** 2886 // 2887 // Register: EVTSVT_O_LGPT1IN2SEL 2888 // 2889 //***************************************************************************** 2890 // Field: [5:0] PUBID 2891 // 2892 // Read/write selection value. 2893 // Writing any other value than values defined by a ENUM may result in 2894 // undefined behavior. 2895 // ENUMs: 2896 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 2897 // LGPT3:ADCTRG setting 2898 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 2899 // setting 2900 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 2901 // by LGPT3:C2CFG setting 2902 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 2903 // by LGPT3:C1CFG setting 2904 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 2905 // by LGPT3:C0CFG setting 2906 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 2907 // LGPT2:ADCTRG setting 2908 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 2909 // setting 2910 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 2911 // by LGPT2:C2CFG setting 2912 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 2913 // by LGPT2:C1CFG setting 2914 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 2915 // by LGPT2:C0CFG setting 2916 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 2917 // LRFDDBELL:SYSTIMOEV.SRC2 2918 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 2919 // LRFDDBELL:SYSTIMOEV.SRC1 2920 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 2921 // LRFDDBELL:SYSTIMOEV.SRC0 2922 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 2923 // LGPT1:ADCTRG setting 2924 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 2925 // setting 2926 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 2927 // by LGPT1:C2CFG setting 2928 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 2929 // by LGPT1:C1CFG setting 2930 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 2931 // by LGPT1:C0CFG setting 2932 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 2933 // LGPT0:ADCTRG setting 2934 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 2935 // setting 2936 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 2937 // by LGPT0:C2CFG setting 2938 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 2939 // by LGPT0:C1CFG setting 2940 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 2941 // by LGPT0:C0CFG setting 2942 // SYSTIM4 SYSTIM Channel 4 event, event flag is 2943 // SYSTIM:MIS.EVT4 2944 // SYSTIM3 SYSTIM Channel 3 event, event flag is 2945 // SYSTIM:MIS.EVT3 2946 // SYSTIM2 SYSTIM Channel 2 event, event flag is 2947 // SYSTIM:MIS.EVT2 2948 // SYSTIM1 SYSTIM Channel 1 event, event flag is 2949 // SYSTIM:MIS.EVT1 2950 // SYSTIM0 SYSTIM Channel 0 event, event flag is 2951 // SYSTIM:MIS.EVT0 2952 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 2953 // signal to SVT clock 2954 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 2955 // ADC_EVT ADC general published event, interrupt flags can 2956 // be found here ADC:MIS1 2957 // GPIO_EVT GPIO generic published event, controlled by 2958 // GPIO:EVTCFG 2959 // NONE Always inactive 2960 #define EVTSVT_LGPT1IN2SEL_PUBID_W 6U 2961 #define EVTSVT_LGPT1IN2SEL_PUBID_M 0x0000003FU 2962 #define EVTSVT_LGPT1IN2SEL_PUBID_S 0U 2963 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT3_ADC 0x00000039U 2964 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT3_DMA 0x00000038U 2965 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT3C2 0x00000036U 2966 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT3C1 0x00000035U 2967 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT3C0 0x00000034U 2968 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT2_ADC 0x00000033U 2969 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT2_DMA 0x00000032U 2970 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT2C2 0x00000030U 2971 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT2C1 0x0000002FU 2972 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT2C0 0x0000002EU 2973 #define EVTSVT_LGPT1IN2SEL_PUBID_LRFD_EVT2 0x0000002CU 2974 #define EVTSVT_LGPT1IN2SEL_PUBID_LRFD_EVT1 0x0000002BU 2975 #define EVTSVT_LGPT1IN2SEL_PUBID_LRFD_EVT0 0x0000002AU 2976 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT1_ADC 0x00000029U 2977 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT1_DMA 0x00000028U 2978 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT1C2 0x00000027U 2979 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT1C1 0x00000026U 2980 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT1C0 0x00000025U 2981 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT0_ADC 0x00000024U 2982 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT0_DMA 0x00000023U 2983 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT0C2 0x00000022U 2984 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT0C1 0x00000021U 2985 #define EVTSVT_LGPT1IN2SEL_PUBID_LGPT0C0 0x00000020U 2986 #define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM4 0x0000001FU 2987 #define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM3 0x0000001EU 2988 #define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM2 0x0000001DU 2989 #define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM1 0x0000001CU 2990 #define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM0 0x0000001BU 2991 #define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM_LT 0x0000001AU 2992 #define EVTSVT_LGPT1IN2SEL_PUBID_SYSTIM_HB 0x00000019U 2993 #define EVTSVT_LGPT1IN2SEL_PUBID_ADC_EVT 0x00000011U 2994 #define EVTSVT_LGPT1IN2SEL_PUBID_GPIO_EVT 0x0000000AU 2995 #define EVTSVT_LGPT1IN2SEL_PUBID_NONE 0x00000000U 2996 2997 //***************************************************************************** 2998 // 2999 // Register: EVTSVT_O_LGPT1TENSEL 3000 // 3001 //***************************************************************************** 3002 // Field: [5:0] PUBID 3003 // 3004 // Read/write selection value. 3005 // Writing any other value than values defined by a ENUM may result in 3006 // undefined behavior. 3007 // ENUMs: 3008 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 3009 // LGPT3:ADCTRG setting 3010 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 3011 // setting 3012 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 3013 // by LGPT3:C2CFG setting 3014 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 3015 // by LGPT3:C1CFG setting 3016 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 3017 // by LGPT3:C0CFG setting 3018 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 3019 // LGPT2:ADCTRG setting 3020 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 3021 // setting 3022 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 3023 // by LGPT2:C2CFG setting 3024 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 3025 // by LGPT2:C1CFG setting 3026 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 3027 // by LGPT2:C0CFG setting 3028 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 3029 // LRFDDBELL:SYSTIMOEV.SRC2 3030 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 3031 // LRFDDBELL:SYSTIMOEV.SRC1 3032 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 3033 // LRFDDBELL:SYSTIMOEV.SRC0 3034 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 3035 // LGPT1:ADCTRG setting 3036 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 3037 // setting 3038 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 3039 // by LGPT1:C2CFG setting 3040 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 3041 // by LGPT1:C1CFG setting 3042 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 3043 // by LGPT1:C0CFG setting 3044 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 3045 // LGPT0:ADCTRG setting 3046 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 3047 // setting 3048 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 3049 // by LGPT0:C2CFG setting 3050 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 3051 // by LGPT0:C1CFG setting 3052 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 3053 // by LGPT0:C0CFG setting 3054 // SYSTIM4 SYSTIM Channel 4 event, event flag is 3055 // SYSTIM:MIS.EVT4 3056 // SYSTIM3 SYSTIM Channel 3 event, event flag is 3057 // SYSTIM:MIS.EVT3 3058 // SYSTIM2 SYSTIM Channel 2 event, event flag is 3059 // SYSTIM:MIS.EVT2 3060 // SYSTIM1 SYSTIM Channel 1 event, event flag is 3061 // SYSTIM:MIS.EVT1 3062 // SYSTIM0 SYSTIM Channel 0 event, event flag is 3063 // SYSTIM:MIS.EVT0 3064 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 3065 // signal to SVT clock 3066 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 3067 // ADC_EVT ADC general published event, interrupt flags can 3068 // be found here ADC:MIS1 3069 // GPIO_EVT GPIO generic published event, controlled by 3070 // GPIO:EVTCFG 3071 // NONE Always inactive 3072 #define EVTSVT_LGPT1TENSEL_PUBID_W 6U 3073 #define EVTSVT_LGPT1TENSEL_PUBID_M 0x0000003FU 3074 #define EVTSVT_LGPT1TENSEL_PUBID_S 0U 3075 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT3_ADC 0x00000039U 3076 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT3_DMA 0x00000038U 3077 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT3C2 0x00000036U 3078 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT3C1 0x00000035U 3079 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT3C0 0x00000034U 3080 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT2_ADC 0x00000033U 3081 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT2_DMA 0x00000032U 3082 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT2C2 0x00000030U 3083 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT2C1 0x0000002FU 3084 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT2C0 0x0000002EU 3085 #define EVTSVT_LGPT1TENSEL_PUBID_LRFD_EVT2 0x0000002CU 3086 #define EVTSVT_LGPT1TENSEL_PUBID_LRFD_EVT1 0x0000002BU 3087 #define EVTSVT_LGPT1TENSEL_PUBID_LRFD_EVT0 0x0000002AU 3088 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT1_ADC 0x00000029U 3089 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT1_DMA 0x00000028U 3090 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT1C2 0x00000027U 3091 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT1C1 0x00000026U 3092 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT1C0 0x00000025U 3093 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT0_ADC 0x00000024U 3094 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT0_DMA 0x00000023U 3095 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT0C2 0x00000022U 3096 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT0C1 0x00000021U 3097 #define EVTSVT_LGPT1TENSEL_PUBID_LGPT0C0 0x00000020U 3098 #define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM4 0x0000001FU 3099 #define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM3 0x0000001EU 3100 #define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM2 0x0000001DU 3101 #define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM1 0x0000001CU 3102 #define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM0 0x0000001BU 3103 #define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM_LT 0x0000001AU 3104 #define EVTSVT_LGPT1TENSEL_PUBID_SYSTIM_HB 0x00000019U 3105 #define EVTSVT_LGPT1TENSEL_PUBID_ADC_EVT 0x00000011U 3106 #define EVTSVT_LGPT1TENSEL_PUBID_GPIO_EVT 0x0000000AU 3107 #define EVTSVT_LGPT1TENSEL_PUBID_NONE 0x00000000U 3108 3109 //***************************************************************************** 3110 // 3111 // Register: EVTSVT_O_LGPT2IN0SEL 3112 // 3113 //***************************************************************************** 3114 // Field: [5:0] PUBID 3115 // 3116 // Read/write selection value. 3117 // Writing any other value than values defined by a ENUM may result in 3118 // undefined behavior. 3119 // ENUMs: 3120 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 3121 // LGPT3:ADCTRG setting 3122 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 3123 // setting 3124 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 3125 // found here LGPT3:MIS 3126 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 3127 // by LGPT3:C2CFG setting 3128 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 3129 // by LGPT3:C1CFG setting 3130 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 3131 // by LGPT3:C0CFG setting 3132 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 3133 // LGPT2:ADCTRG setting 3134 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 3135 // setting 3136 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 3137 // found here LGPT2:MIS 3138 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 3139 // by LGPT2:C2CFG setting 3140 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 3141 // by LGPT2:C1CFG setting 3142 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 3143 // by LGPT2:C0CFG setting 3144 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 3145 // LRFDDBELL:SYSTIMOEV.SRC2 3146 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 3147 // LRFDDBELL:SYSTIMOEV.SRC1 3148 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 3149 // LRFDDBELL:SYSTIMOEV.SRC0 3150 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 3151 // LGPT1:ADCTRG setting 3152 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 3153 // setting 3154 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 3155 // by LGPT1:C2CFG setting 3156 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 3157 // by LGPT1:C1CFG setting 3158 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 3159 // by LGPT1:C0CFG setting 3160 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 3161 // LGPT0:ADCTRG setting 3162 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 3163 // setting 3164 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 3165 // by LGPT0:C2CFG setting 3166 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 3167 // by LGPT0:C1CFG setting 3168 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 3169 // by LGPT0:C0CFG setting 3170 // SYSTIM4 SYSTIM Channel 4 event, event flag is 3171 // SYSTIM:MIS.EVT4 3172 // SYSTIM3 SYSTIM Channel 3 event, event flag is 3173 // SYSTIM:MIS.EVT3 3174 // SYSTIM2 SYSTIM Channel 2 event, event flag is 3175 // SYSTIM:MIS.EVT2 3176 // SYSTIM1 SYSTIM Channel 1 event, event flag is 3177 // SYSTIM:MIS.EVT1 3178 // SYSTIM0 SYSTIM Channel 0 event, event flag is 3179 // SYSTIM:MIS.EVT0 3180 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 3181 // signal to SVT clock 3182 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 3183 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 3184 // found here I2C0:MIS 3185 // UART0_COMB UART0 combined interrupt, interrupt flags are 3186 // found here UART0:MIS 3187 // AES_COMB AES accelerator combined interrupt request, 3188 // interrupt flags can be found here AES:MIS 3189 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 3190 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 3191 // can be found here DMA:REQDONE 3192 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 3193 // found here LGPT1:MIS 3194 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 3195 // found here LGPT0:MIS 3196 // ADC_EVT ADC general published event, interrupt flags can 3197 // be found here ADC:MIS1 3198 // ADC_COMB ADC combined interrupt request, interrupt flags 3199 // can be found here ADC:MIS0 3200 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 3201 // can be found here SPI0:MIS 3202 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 3203 // here LRFDDBELL:MIS2 3204 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 3205 // here LRFDDBELL:MIS1 3206 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 3207 // here LRFDDBELL:MIS0 3208 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 3209 // flash operation has completed, interrupt flags 3210 // can be found here FLASH:MIS 3211 // GPIO_EVT GPIO generic published event, controlled by 3212 // GPIO:EVTCFG 3213 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 3214 // can be found here GPIO:MIS 3215 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 3216 // found here SYSTIM:MIS 3217 // AON_IOC_COMB IOC synchronous combined event, controlled by 3218 // IOC:EVTCFG 3219 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 3220 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 3221 // found here DBGSS:MIS 3222 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 3223 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 3224 // can be found here CKMD:MIS 3225 // AON_PMU_COMB PMU combined interrupt request for BATMON, 3226 // interrupt flags can be found here PMUD:EVENT 3227 // NONE Always inactive 3228 #define EVTSVT_LGPT2IN0SEL_PUBID_W 6U 3229 #define EVTSVT_LGPT2IN0SEL_PUBID_M 0x0000003FU 3230 #define EVTSVT_LGPT2IN0SEL_PUBID_S 0U 3231 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT3_ADC 0x00000039U 3232 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT3_DMA 0x00000038U 3233 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT3_COMB 0x00000037U 3234 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT3C2 0x00000036U 3235 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT3C1 0x00000035U 3236 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT3C0 0x00000034U 3237 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT2_ADC 0x00000033U 3238 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT2_DMA 0x00000032U 3239 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT2_COMB 0x00000031U 3240 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT2C2 0x00000030U 3241 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT2C1 0x0000002FU 3242 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT2C0 0x0000002EU 3243 #define EVTSVT_LGPT2IN0SEL_PUBID_LRFD_EVT2 0x0000002CU 3244 #define EVTSVT_LGPT2IN0SEL_PUBID_LRFD_EVT1 0x0000002BU 3245 #define EVTSVT_LGPT2IN0SEL_PUBID_LRFD_EVT0 0x0000002AU 3246 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT1_ADC 0x00000029U 3247 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT1_DMA 0x00000028U 3248 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT1C2 0x00000027U 3249 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT1C1 0x00000026U 3250 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT1C0 0x00000025U 3251 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT0_ADC 0x00000024U 3252 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT0_DMA 0x00000023U 3253 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT0C2 0x00000022U 3254 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT0C1 0x00000021U 3255 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT0C0 0x00000020U 3256 #define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM4 0x0000001FU 3257 #define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM3 0x0000001EU 3258 #define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM2 0x0000001DU 3259 #define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM1 0x0000001CU 3260 #define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM0 0x0000001BU 3261 #define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM_LT 0x0000001AU 3262 #define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM_HB 0x00000019U 3263 #define EVTSVT_LGPT2IN0SEL_PUBID_I2C0_IRQ 0x00000018U 3264 #define EVTSVT_LGPT2IN0SEL_PUBID_UART0_COMB 0x00000017U 3265 #define EVTSVT_LGPT2IN0SEL_PUBID_AES_COMB 0x00000016U 3266 #define EVTSVT_LGPT2IN0SEL_PUBID_DMA_ERR 0x00000015U 3267 #define EVTSVT_LGPT2IN0SEL_PUBID_DMA_DONE_COMB 0x00000014U 3268 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT1_COMB 0x00000013U 3269 #define EVTSVT_LGPT2IN0SEL_PUBID_LGPT0_COMB 0x00000012U 3270 #define EVTSVT_LGPT2IN0SEL_PUBID_ADC_EVT 0x00000011U 3271 #define EVTSVT_LGPT2IN0SEL_PUBID_ADC_COMB 0x00000010U 3272 #define EVTSVT_LGPT2IN0SEL_PUBID_SPI0_COMB 0x0000000FU 3273 #define EVTSVT_LGPT2IN0SEL_PUBID_LRFD_IRQ2 0x0000000EU 3274 #define EVTSVT_LGPT2IN0SEL_PUBID_LRFD_IRQ1 0x0000000DU 3275 #define EVTSVT_LGPT2IN0SEL_PUBID_LRFD_IRQ0 0x0000000CU 3276 #define EVTSVT_LGPT2IN0SEL_PUBID_FLASH_IRQ 0x0000000BU 3277 #define EVTSVT_LGPT2IN0SEL_PUBID_GPIO_EVT 0x0000000AU 3278 #define EVTSVT_LGPT2IN0SEL_PUBID_GPIO_COMB 0x00000009U 3279 #define EVTSVT_LGPT2IN0SEL_PUBID_SYSTIM_COMB 0x00000008U 3280 #define EVTSVT_LGPT2IN0SEL_PUBID_AON_IOC_COMB 0x00000007U 3281 #define EVTSVT_LGPT2IN0SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 3282 #define EVTSVT_LGPT2IN0SEL_PUBID_AON_DBG_COMB 0x00000005U 3283 #define EVTSVT_LGPT2IN0SEL_PUBID_AON_RTC_COMB 0x00000004U 3284 #define EVTSVT_LGPT2IN0SEL_PUBID_AON_CKM_COMB 0x00000003U 3285 #define EVTSVT_LGPT2IN0SEL_PUBID_AON_PMU_COMB 0x00000002U 3286 #define EVTSVT_LGPT2IN0SEL_PUBID_NONE 0x00000000U 3287 3288 //***************************************************************************** 3289 // 3290 // Register: EVTSVT_O_LGPT2IN1SEL 3291 // 3292 //***************************************************************************** 3293 // Field: [5:0] PUBID 3294 // 3295 // Read/write selection value. 3296 // Writing any other value than values defined by a ENUM may result in 3297 // undefined behavior. 3298 // ENUMs: 3299 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 3300 // LGPT3:ADCTRG setting 3301 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 3302 // setting 3303 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 3304 // by LGPT3:C2CFG setting 3305 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 3306 // by LGPT3:C1CFG setting 3307 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 3308 // by LGPT3:C0CFG setting 3309 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 3310 // LGPT2:ADCTRG setting 3311 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 3312 // setting 3313 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 3314 // by LGPT2:C2CFG setting 3315 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 3316 // by LGPT2:C1CFG setting 3317 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 3318 // by LGPT2:C0CFG setting 3319 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 3320 // LRFDDBELL:SYSTIMOEV.SRC2 3321 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 3322 // LRFDDBELL:SYSTIMOEV.SRC1 3323 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 3324 // LRFDDBELL:SYSTIMOEV.SRC0 3325 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 3326 // LGPT1:ADCTRG setting 3327 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 3328 // setting 3329 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 3330 // by LGPT1:C2CFG setting 3331 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 3332 // by LGPT1:C1CFG setting 3333 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 3334 // by LGPT1:C0CFG setting 3335 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 3336 // LGPT0:ADCTRG setting 3337 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 3338 // setting 3339 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 3340 // by LGPT0:C2CFG setting 3341 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 3342 // by LGPT0:C1CFG setting 3343 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 3344 // by LGPT0:C0CFG setting 3345 // SYSTIM4 SYSTIM Channel 4 event, event flag is 3346 // SYSTIM:MIS.EVT4 3347 // SYSTIM3 SYSTIM Channel 3 event, event flag is 3348 // SYSTIM:MIS.EVT3 3349 // SYSTIM2 SYSTIM Channel 2 event, event flag is 3350 // SYSTIM:MIS.EVT2 3351 // SYSTIM1 SYSTIM Channel 1 event, event flag is 3352 // SYSTIM:MIS.EVT1 3353 // SYSTIM0 SYSTIM Channel 0 event, event flag is 3354 // SYSTIM:MIS.EVT0 3355 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 3356 // signal to SVT clock 3357 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 3358 // ADC_EVT ADC general published event, interrupt flags can 3359 // be found here ADC:MIS1 3360 // GPIO_EVT GPIO generic published event, controlled by 3361 // GPIO:EVTCFG 3362 // NONE Always inactive 3363 #define EVTSVT_LGPT2IN1SEL_PUBID_W 6U 3364 #define EVTSVT_LGPT2IN1SEL_PUBID_M 0x0000003FU 3365 #define EVTSVT_LGPT2IN1SEL_PUBID_S 0U 3366 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT3_ADC 0x00000039U 3367 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT3_DMA 0x00000038U 3368 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT3C2 0x00000036U 3369 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT3C1 0x00000035U 3370 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT3C0 0x00000034U 3371 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT2_ADC 0x00000033U 3372 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT2_DMA 0x00000032U 3373 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT2C2 0x00000030U 3374 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT2C1 0x0000002FU 3375 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT2C0 0x0000002EU 3376 #define EVTSVT_LGPT2IN1SEL_PUBID_LRFD_EVT2 0x0000002CU 3377 #define EVTSVT_LGPT2IN1SEL_PUBID_LRFD_EVT1 0x0000002BU 3378 #define EVTSVT_LGPT2IN1SEL_PUBID_LRFD_EVT0 0x0000002AU 3379 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT1_ADC 0x00000029U 3380 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT1_DMA 0x00000028U 3381 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT1C2 0x00000027U 3382 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT1C1 0x00000026U 3383 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT1C0 0x00000025U 3384 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT0_ADC 0x00000024U 3385 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT0_DMA 0x00000023U 3386 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT0C2 0x00000022U 3387 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT0C1 0x00000021U 3388 #define EVTSVT_LGPT2IN1SEL_PUBID_LGPT0C0 0x00000020U 3389 #define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM4 0x0000001FU 3390 #define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM3 0x0000001EU 3391 #define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM2 0x0000001DU 3392 #define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM1 0x0000001CU 3393 #define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM0 0x0000001BU 3394 #define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM_LT 0x0000001AU 3395 #define EVTSVT_LGPT2IN1SEL_PUBID_SYSTIM_HB 0x00000019U 3396 #define EVTSVT_LGPT2IN1SEL_PUBID_ADC_EVT 0x00000011U 3397 #define EVTSVT_LGPT2IN1SEL_PUBID_GPIO_EVT 0x0000000AU 3398 #define EVTSVT_LGPT2IN1SEL_PUBID_NONE 0x00000000U 3399 3400 //***************************************************************************** 3401 // 3402 // Register: EVTSVT_O_LGPT2IN2SEL 3403 // 3404 //***************************************************************************** 3405 // Field: [5:0] PUBID 3406 // 3407 // Read/write selection value. 3408 // Writing any other value than values defined by a ENUM may result in 3409 // undefined behavior. 3410 // ENUMs: 3411 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 3412 // LGPT3:ADCTRG setting 3413 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 3414 // setting 3415 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 3416 // by LGPT3:C2CFG setting 3417 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 3418 // by LGPT3:C1CFG setting 3419 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 3420 // by LGPT3:C0CFG setting 3421 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 3422 // LGPT2:ADCTRG setting 3423 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 3424 // setting 3425 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 3426 // by LGPT2:C2CFG setting 3427 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 3428 // by LGPT2:C1CFG setting 3429 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 3430 // by LGPT2:C0CFG setting 3431 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 3432 // LRFDDBELL:SYSTIMOEV.SRC2 3433 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 3434 // LRFDDBELL:SYSTIMOEV.SRC1 3435 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 3436 // LRFDDBELL:SYSTIMOEV.SRC0 3437 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 3438 // LGPT1:ADCTRG setting 3439 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 3440 // setting 3441 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 3442 // by LGPT1:C2CFG setting 3443 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 3444 // by LGPT1:C1CFG setting 3445 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 3446 // by LGPT1:C0CFG setting 3447 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 3448 // LGPT0:ADCTRG setting 3449 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 3450 // setting 3451 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 3452 // by LGPT0:C2CFG setting 3453 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 3454 // by LGPT0:C1CFG setting 3455 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 3456 // by LGPT0:C0CFG setting 3457 // SYSTIM4 SYSTIM Channel 4 event, event flag is 3458 // SYSTIM:MIS.EVT4 3459 // SYSTIM3 SYSTIM Channel 3 event, event flag is 3460 // SYSTIM:MIS.EVT3 3461 // SYSTIM2 SYSTIM Channel 2 event, event flag is 3462 // SYSTIM:MIS.EVT2 3463 // SYSTIM1 SYSTIM Channel 1 event, event flag is 3464 // SYSTIM:MIS.EVT1 3465 // SYSTIM0 SYSTIM Channel 0 event, event flag is 3466 // SYSTIM:MIS.EVT0 3467 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 3468 // signal to SVT clock 3469 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 3470 // ADC_EVT ADC general published event, interrupt flags can 3471 // be found here ADC:MIS1 3472 // GPIO_EVT GPIO generic published event, controlled by 3473 // GPIO:EVTCFG 3474 // NONE Always inactive 3475 #define EVTSVT_LGPT2IN2SEL_PUBID_W 6U 3476 #define EVTSVT_LGPT2IN2SEL_PUBID_M 0x0000003FU 3477 #define EVTSVT_LGPT2IN2SEL_PUBID_S 0U 3478 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT3_ADC 0x00000039U 3479 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT3_DMA 0x00000038U 3480 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT3C2 0x00000036U 3481 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT3C1 0x00000035U 3482 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT3C0 0x00000034U 3483 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT2_ADC 0x00000033U 3484 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT2_DMA 0x00000032U 3485 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT2C2 0x00000030U 3486 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT2C1 0x0000002FU 3487 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT2C0 0x0000002EU 3488 #define EVTSVT_LGPT2IN2SEL_PUBID_LRFD_EVT2 0x0000002CU 3489 #define EVTSVT_LGPT2IN2SEL_PUBID_LRFD_EVT1 0x0000002BU 3490 #define EVTSVT_LGPT2IN2SEL_PUBID_LRFD_EVT0 0x0000002AU 3491 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT1_ADC 0x00000029U 3492 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT1_DMA 0x00000028U 3493 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT1C2 0x00000027U 3494 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT1C1 0x00000026U 3495 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT1C0 0x00000025U 3496 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT0_ADC 0x00000024U 3497 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT0_DMA 0x00000023U 3498 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT0C2 0x00000022U 3499 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT0C1 0x00000021U 3500 #define EVTSVT_LGPT2IN2SEL_PUBID_LGPT0C0 0x00000020U 3501 #define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM4 0x0000001FU 3502 #define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM3 0x0000001EU 3503 #define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM2 0x0000001DU 3504 #define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM1 0x0000001CU 3505 #define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM0 0x0000001BU 3506 #define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM_LT 0x0000001AU 3507 #define EVTSVT_LGPT2IN2SEL_PUBID_SYSTIM_HB 0x00000019U 3508 #define EVTSVT_LGPT2IN2SEL_PUBID_ADC_EVT 0x00000011U 3509 #define EVTSVT_LGPT2IN2SEL_PUBID_GPIO_EVT 0x0000000AU 3510 #define EVTSVT_LGPT2IN2SEL_PUBID_NONE 0x00000000U 3511 3512 //***************************************************************************** 3513 // 3514 // Register: EVTSVT_O_LGPT2TENSEL 3515 // 3516 //***************************************************************************** 3517 // Field: [5:0] PUBID 3518 // 3519 // Read/write selection value. 3520 // Writing any other value than values defined by a ENUM may result in 3521 // undefined behavior. 3522 // ENUMs: 3523 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 3524 // LGPT3:ADCTRG setting 3525 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 3526 // setting 3527 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 3528 // by LGPT3:C2CFG setting 3529 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 3530 // by LGPT3:C1CFG setting 3531 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 3532 // by LGPT3:C0CFG setting 3533 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 3534 // LGPT2:ADCTRG setting 3535 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 3536 // setting 3537 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 3538 // by LGPT2:C2CFG setting 3539 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 3540 // by LGPT2:C1CFG setting 3541 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 3542 // by LGPT2:C0CFG setting 3543 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 3544 // LRFDDBELL:SYSTIMOEV.SRC2 3545 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 3546 // LRFDDBELL:SYSTIMOEV.SRC1 3547 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 3548 // LRFDDBELL:SYSTIMOEV.SRC0 3549 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 3550 // LGPT1:ADCTRG setting 3551 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 3552 // setting 3553 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 3554 // by LGPT1:C2CFG setting 3555 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 3556 // by LGPT1:C1CFG setting 3557 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 3558 // by LGPT1:C0CFG setting 3559 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 3560 // LGPT0:ADCTRG setting 3561 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 3562 // setting 3563 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 3564 // by LGPT0:C2CFG setting 3565 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 3566 // by LGPT0:C1CFG setting 3567 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 3568 // by LGPT0:C0CFG setting 3569 // SYSTIM4 SYSTIM Channel 4 event, event flag is 3570 // SYSTIM:MIS.EVT4 3571 // SYSTIM3 SYSTIM Channel 3 event, event flag is 3572 // SYSTIM:MIS.EVT3 3573 // SYSTIM2 SYSTIM Channel 2 event, event flag is 3574 // SYSTIM:MIS.EVT2 3575 // SYSTIM1 SYSTIM Channel 1 event, event flag is 3576 // SYSTIM:MIS.EVT1 3577 // SYSTIM0 SYSTIM Channel 0 event, event flag is 3578 // SYSTIM:MIS.EVT0 3579 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 3580 // signal to SVT clock 3581 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 3582 // ADC_EVT ADC general published event, interrupt flags can 3583 // be found here ADC:MIS1 3584 // GPIO_EVT GPIO generic published event, controlled by 3585 // GPIO:EVTCFG 3586 // NONE Always inactive 3587 #define EVTSVT_LGPT2TENSEL_PUBID_W 6U 3588 #define EVTSVT_LGPT2TENSEL_PUBID_M 0x0000003FU 3589 #define EVTSVT_LGPT2TENSEL_PUBID_S 0U 3590 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT3_ADC 0x00000039U 3591 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT3_DMA 0x00000038U 3592 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT3C2 0x00000036U 3593 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT3C1 0x00000035U 3594 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT3C0 0x00000034U 3595 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT2_ADC 0x00000033U 3596 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT2_DMA 0x00000032U 3597 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT2C2 0x00000030U 3598 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT2C1 0x0000002FU 3599 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT2C0 0x0000002EU 3600 #define EVTSVT_LGPT2TENSEL_PUBID_LRFD_EVT2 0x0000002CU 3601 #define EVTSVT_LGPT2TENSEL_PUBID_LRFD_EVT1 0x0000002BU 3602 #define EVTSVT_LGPT2TENSEL_PUBID_LRFD_EVT0 0x0000002AU 3603 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT1_ADC 0x00000029U 3604 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT1_DMA 0x00000028U 3605 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT1C2 0x00000027U 3606 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT1C1 0x00000026U 3607 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT1C0 0x00000025U 3608 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT0_ADC 0x00000024U 3609 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT0_DMA 0x00000023U 3610 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT0C2 0x00000022U 3611 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT0C1 0x00000021U 3612 #define EVTSVT_LGPT2TENSEL_PUBID_LGPT0C0 0x00000020U 3613 #define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM4 0x0000001FU 3614 #define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM3 0x0000001EU 3615 #define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM2 0x0000001DU 3616 #define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM1 0x0000001CU 3617 #define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM0 0x0000001BU 3618 #define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM_LT 0x0000001AU 3619 #define EVTSVT_LGPT2TENSEL_PUBID_SYSTIM_HB 0x00000019U 3620 #define EVTSVT_LGPT2TENSEL_PUBID_ADC_EVT 0x00000011U 3621 #define EVTSVT_LGPT2TENSEL_PUBID_GPIO_EVT 0x0000000AU 3622 #define EVTSVT_LGPT2TENSEL_PUBID_NONE 0x00000000U 3623 3624 //***************************************************************************** 3625 // 3626 // Register: EVTSVT_O_LGPT3IN0SEL 3627 // 3628 //***************************************************************************** 3629 // Field: [5:0] PUBID 3630 // 3631 // Read/write selection value. 3632 // Writing any other value than values defined by a ENUM may result in 3633 // undefined behavior. 3634 // ENUMs: 3635 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 3636 // LGPT3:ADCTRG setting 3637 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 3638 // setting 3639 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 3640 // found here LGPT3:MIS 3641 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 3642 // by LGPT3:C2CFG setting 3643 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 3644 // by LGPT3:C1CFG setting 3645 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 3646 // by LGPT3:C0CFG setting 3647 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 3648 // LGPT2:ADCTRG setting 3649 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 3650 // setting 3651 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 3652 // found here LGPT2:MIS 3653 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 3654 // by LGPT2:C2CFG setting 3655 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 3656 // by LGPT2:C1CFG setting 3657 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 3658 // by LGPT2:C0CFG setting 3659 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 3660 // LRFDDBELL:SYSTIMOEV.SRC2 3661 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 3662 // LRFDDBELL:SYSTIMOEV.SRC1 3663 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 3664 // LRFDDBELL:SYSTIMOEV.SRC0 3665 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 3666 // LGPT1:ADCTRG setting 3667 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 3668 // setting 3669 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 3670 // by LGPT1:C2CFG setting 3671 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 3672 // by LGPT1:C1CFG setting 3673 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 3674 // by LGPT1:C0CFG setting 3675 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 3676 // LGPT0:ADCTRG setting 3677 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 3678 // setting 3679 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 3680 // by LGPT0:C2CFG setting 3681 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 3682 // by LGPT0:C1CFG setting 3683 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 3684 // by LGPT0:C0CFG setting 3685 // SYSTIM4 SYSTIM Channel 4 event, event flag is 3686 // SYSTIM:MIS.EVT4 3687 // SYSTIM3 SYSTIM Channel 3 event, event flag is 3688 // SYSTIM:MIS.EVT3 3689 // SYSTIM2 SYSTIM Channel 2 event, event flag is 3690 // SYSTIM:MIS.EVT2 3691 // SYSTIM1 SYSTIM Channel 1 event, event flag is 3692 // SYSTIM:MIS.EVT1 3693 // SYSTIM0 SYSTIM Channel 0 event, event flag is 3694 // SYSTIM:MIS.EVT0 3695 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 3696 // signal to SVT clock 3697 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 3698 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 3699 // found here I2C0:MIS 3700 // UART0_COMB UART0 combined interrupt, interrupt flags are 3701 // found here UART0:MIS 3702 // AES_COMB AES accelerator combined interrupt request, 3703 // interrupt flags can be found here AES:MIS 3704 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 3705 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 3706 // can be found here DMA:REQDONE 3707 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 3708 // found here LGPT1:MIS 3709 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 3710 // found here LGPT0:MIS 3711 // ADC_EVT ADC general published event, interrupt flags can 3712 // be found here ADC:MIS1 3713 // ADC_COMB ADC combined interrupt request, interrupt flags 3714 // can be found here ADC:MIS0 3715 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 3716 // can be found here SPI0:MIS 3717 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 3718 // here LRFDDBELL:MIS2 3719 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 3720 // here LRFDDBELL:MIS1 3721 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 3722 // here LRFDDBELL:MIS0 3723 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 3724 // flash operation has completed, interrupt flags 3725 // can be found here FLASH:MIS 3726 // GPIO_EVT GPIO generic published event, controlled by 3727 // GPIO:EVTCFG 3728 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 3729 // can be found here GPIO:MIS 3730 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 3731 // found here SYSTIM:MIS 3732 // AON_IOC_COMB IOC synchronous combined event, controlled by 3733 // IOC:EVTCFG 3734 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 3735 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 3736 // found here DBGSS:MIS 3737 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 3738 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 3739 // can be found here CKMD:MIS 3740 // AON_PMU_COMB PMU combined interrupt request for BATMON, 3741 // interrupt flags can be found here PMUD:EVENT 3742 // NONE Always inactive 3743 #define EVTSVT_LGPT3IN0SEL_PUBID_W 6U 3744 #define EVTSVT_LGPT3IN0SEL_PUBID_M 0x0000003FU 3745 #define EVTSVT_LGPT3IN0SEL_PUBID_S 0U 3746 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT3_ADC 0x00000039U 3747 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT3_DMA 0x00000038U 3748 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT3_COMB 0x00000037U 3749 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT3C2 0x00000036U 3750 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT3C1 0x00000035U 3751 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT3C0 0x00000034U 3752 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT2_ADC 0x00000033U 3753 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT2_DMA 0x00000032U 3754 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT2_COMB 0x00000031U 3755 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT2C2 0x00000030U 3756 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT2C1 0x0000002FU 3757 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT2C0 0x0000002EU 3758 #define EVTSVT_LGPT3IN0SEL_PUBID_LRFD_EVT2 0x0000002CU 3759 #define EVTSVT_LGPT3IN0SEL_PUBID_LRFD_EVT1 0x0000002BU 3760 #define EVTSVT_LGPT3IN0SEL_PUBID_LRFD_EVT0 0x0000002AU 3761 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT1_ADC 0x00000029U 3762 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT1_DMA 0x00000028U 3763 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT1C2 0x00000027U 3764 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT1C1 0x00000026U 3765 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT1C0 0x00000025U 3766 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT0_ADC 0x00000024U 3767 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT0_DMA 0x00000023U 3768 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT0C2 0x00000022U 3769 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT0C1 0x00000021U 3770 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT0C0 0x00000020U 3771 #define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM4 0x0000001FU 3772 #define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM3 0x0000001EU 3773 #define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM2 0x0000001DU 3774 #define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM1 0x0000001CU 3775 #define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM0 0x0000001BU 3776 #define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM_LT 0x0000001AU 3777 #define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM_HB 0x00000019U 3778 #define EVTSVT_LGPT3IN0SEL_PUBID_I2C0_IRQ 0x00000018U 3779 #define EVTSVT_LGPT3IN0SEL_PUBID_UART0_COMB 0x00000017U 3780 #define EVTSVT_LGPT3IN0SEL_PUBID_AES_COMB 0x00000016U 3781 #define EVTSVT_LGPT3IN0SEL_PUBID_DMA_ERR 0x00000015U 3782 #define EVTSVT_LGPT3IN0SEL_PUBID_DMA_DONE_COMB 0x00000014U 3783 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT1_COMB 0x00000013U 3784 #define EVTSVT_LGPT3IN0SEL_PUBID_LGPT0_COMB 0x00000012U 3785 #define EVTSVT_LGPT3IN0SEL_PUBID_ADC_EVT 0x00000011U 3786 #define EVTSVT_LGPT3IN0SEL_PUBID_ADC_COMB 0x00000010U 3787 #define EVTSVT_LGPT3IN0SEL_PUBID_SPI0_COMB 0x0000000FU 3788 #define EVTSVT_LGPT3IN0SEL_PUBID_LRFD_IRQ2 0x0000000EU 3789 #define EVTSVT_LGPT3IN0SEL_PUBID_LRFD_IRQ1 0x0000000DU 3790 #define EVTSVT_LGPT3IN0SEL_PUBID_LRFD_IRQ0 0x0000000CU 3791 #define EVTSVT_LGPT3IN0SEL_PUBID_FLASH_IRQ 0x0000000BU 3792 #define EVTSVT_LGPT3IN0SEL_PUBID_GPIO_EVT 0x0000000AU 3793 #define EVTSVT_LGPT3IN0SEL_PUBID_GPIO_COMB 0x00000009U 3794 #define EVTSVT_LGPT3IN0SEL_PUBID_SYSTIM_COMB 0x00000008U 3795 #define EVTSVT_LGPT3IN0SEL_PUBID_AON_IOC_COMB 0x00000007U 3796 #define EVTSVT_LGPT3IN0SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 3797 #define EVTSVT_LGPT3IN0SEL_PUBID_AON_DBG_COMB 0x00000005U 3798 #define EVTSVT_LGPT3IN0SEL_PUBID_AON_RTC_COMB 0x00000004U 3799 #define EVTSVT_LGPT3IN0SEL_PUBID_AON_CKM_COMB 0x00000003U 3800 #define EVTSVT_LGPT3IN0SEL_PUBID_AON_PMU_COMB 0x00000002U 3801 #define EVTSVT_LGPT3IN0SEL_PUBID_NONE 0x00000000U 3802 3803 //***************************************************************************** 3804 // 3805 // Register: EVTSVT_O_LGPT3IN1SEL 3806 // 3807 //***************************************************************************** 3808 // Field: [5:0] PUBID 3809 // 3810 // Read/write selection value. 3811 // Writing any other value than values defined by a ENUM may result in 3812 // undefined behavior. 3813 // ENUMs: 3814 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 3815 // LGPT3:ADCTRG setting 3816 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 3817 // setting 3818 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 3819 // by LGPT3:C2CFG setting 3820 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 3821 // by LGPT3:C1CFG setting 3822 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 3823 // by LGPT3:C0CFG setting 3824 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 3825 // LGPT2:ADCTRG setting 3826 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 3827 // setting 3828 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 3829 // by LGPT2:C2CFG setting 3830 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 3831 // by LGPT2:C1CFG setting 3832 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 3833 // by LGPT2:C0CFG setting 3834 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 3835 // LRFDDBELL:SYSTIMOEV.SRC2 3836 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 3837 // LRFDDBELL:SYSTIMOEV.SRC1 3838 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 3839 // LRFDDBELL:SYSTIMOEV.SRC0 3840 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 3841 // LGPT1:ADCTRG setting 3842 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 3843 // setting 3844 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 3845 // by LGPT1:C2CFG setting 3846 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 3847 // by LGPT1:C1CFG setting 3848 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 3849 // by LGPT1:C0CFG setting 3850 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 3851 // LGPT0:ADCTRG setting 3852 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 3853 // setting 3854 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 3855 // by LGPT0:C2CFG setting 3856 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 3857 // by LGPT0:C1CFG setting 3858 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 3859 // by LGPT0:C0CFG setting 3860 // SYSTIM4 SYSTIM Channel 4 event, event flag is 3861 // SYSTIM:MIS.EVT4 3862 // SYSTIM3 SYSTIM Channel 3 event, event flag is 3863 // SYSTIM:MIS.EVT3 3864 // SYSTIM2 SYSTIM Channel 2 event, event flag is 3865 // SYSTIM:MIS.EVT2 3866 // SYSTIM1 SYSTIM Channel 1 event, event flag is 3867 // SYSTIM:MIS.EVT1 3868 // SYSTIM0 SYSTIM Channel 0 event, event flag is 3869 // SYSTIM:MIS.EVT0 3870 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 3871 // signal to SVT clock 3872 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 3873 // ADC_EVT ADC general published event, interrupt flags can 3874 // be found here ADC:MIS1 3875 // GPIO_EVT GPIO generic published event, controlled by 3876 // GPIO:EVTCFG 3877 // NONE Always inactive 3878 #define EVTSVT_LGPT3IN1SEL_PUBID_W 6U 3879 #define EVTSVT_LGPT3IN1SEL_PUBID_M 0x0000003FU 3880 #define EVTSVT_LGPT3IN1SEL_PUBID_S 0U 3881 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT3_ADC 0x00000039U 3882 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT3_DMA 0x00000038U 3883 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT3C2 0x00000036U 3884 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT3C1 0x00000035U 3885 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT3C0 0x00000034U 3886 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT2_ADC 0x00000033U 3887 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT2_DMA 0x00000032U 3888 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT2C2 0x00000030U 3889 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT2C1 0x0000002FU 3890 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT2C0 0x0000002EU 3891 #define EVTSVT_LGPT3IN1SEL_PUBID_LRFD_EVT2 0x0000002CU 3892 #define EVTSVT_LGPT3IN1SEL_PUBID_LRFD_EVT1 0x0000002BU 3893 #define EVTSVT_LGPT3IN1SEL_PUBID_LRFD_EVT0 0x0000002AU 3894 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT1_ADC 0x00000029U 3895 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT1_DMA 0x00000028U 3896 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT1C2 0x00000027U 3897 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT1C1 0x00000026U 3898 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT1C0 0x00000025U 3899 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT0_ADC 0x00000024U 3900 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT0_DMA 0x00000023U 3901 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT0C2 0x00000022U 3902 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT0C1 0x00000021U 3903 #define EVTSVT_LGPT3IN1SEL_PUBID_LGPT0C0 0x00000020U 3904 #define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM4 0x0000001FU 3905 #define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM3 0x0000001EU 3906 #define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM2 0x0000001DU 3907 #define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM1 0x0000001CU 3908 #define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM0 0x0000001BU 3909 #define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM_LT 0x0000001AU 3910 #define EVTSVT_LGPT3IN1SEL_PUBID_SYSTIM_HB 0x00000019U 3911 #define EVTSVT_LGPT3IN1SEL_PUBID_ADC_EVT 0x00000011U 3912 #define EVTSVT_LGPT3IN1SEL_PUBID_GPIO_EVT 0x0000000AU 3913 #define EVTSVT_LGPT3IN1SEL_PUBID_NONE 0x00000000U 3914 3915 //***************************************************************************** 3916 // 3917 // Register: EVTSVT_O_LGPT3IN2SEL 3918 // 3919 //***************************************************************************** 3920 // Field: [5:0] PUBID 3921 // 3922 // Read/write selection value. 3923 // Writing any other value than values defined by a ENUM may result in 3924 // undefined behavior. 3925 // ENUMs: 3926 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 3927 // LGPT3:ADCTRG setting 3928 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 3929 // setting 3930 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 3931 // by LGPT3:C2CFG setting 3932 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 3933 // by LGPT3:C1CFG setting 3934 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 3935 // by LGPT3:C0CFG setting 3936 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 3937 // LGPT2:ADCTRG setting 3938 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 3939 // setting 3940 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 3941 // by LGPT2:C2CFG setting 3942 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 3943 // by LGPT2:C1CFG setting 3944 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 3945 // by LGPT2:C0CFG setting 3946 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 3947 // LRFDDBELL:SYSTIMOEV.SRC2 3948 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 3949 // LRFDDBELL:SYSTIMOEV.SRC1 3950 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 3951 // LRFDDBELL:SYSTIMOEV.SRC0 3952 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 3953 // LGPT1:ADCTRG setting 3954 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 3955 // setting 3956 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 3957 // by LGPT1:C2CFG setting 3958 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 3959 // by LGPT1:C1CFG setting 3960 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 3961 // by LGPT1:C0CFG setting 3962 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 3963 // LGPT0:ADCTRG setting 3964 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 3965 // setting 3966 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 3967 // by LGPT0:C2CFG setting 3968 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 3969 // by LGPT0:C1CFG setting 3970 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 3971 // by LGPT0:C0CFG setting 3972 // SYSTIM4 SYSTIM Channel 4 event, event flag is 3973 // SYSTIM:MIS.EVT4 3974 // SYSTIM3 SYSTIM Channel 3 event, event flag is 3975 // SYSTIM:MIS.EVT3 3976 // SYSTIM2 SYSTIM Channel 2 event, event flag is 3977 // SYSTIM:MIS.EVT2 3978 // SYSTIM1 SYSTIM Channel 1 event, event flag is 3979 // SYSTIM:MIS.EVT1 3980 // SYSTIM0 SYSTIM Channel 0 event, event flag is 3981 // SYSTIM:MIS.EVT0 3982 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 3983 // signal to SVT clock 3984 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 3985 // ADC_EVT ADC general published event, interrupt flags can 3986 // be found here ADC:MIS1 3987 // GPIO_EVT GPIO generic published event, controlled by 3988 // GPIO:EVTCFG 3989 // NONE Always inactive 3990 #define EVTSVT_LGPT3IN2SEL_PUBID_W 6U 3991 #define EVTSVT_LGPT3IN2SEL_PUBID_M 0x0000003FU 3992 #define EVTSVT_LGPT3IN2SEL_PUBID_S 0U 3993 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT3_ADC 0x00000039U 3994 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT3_DMA 0x00000038U 3995 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT3C2 0x00000036U 3996 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT3C1 0x00000035U 3997 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT3C0 0x00000034U 3998 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT2_ADC 0x00000033U 3999 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT2_DMA 0x00000032U 4000 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT2C2 0x00000030U 4001 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT2C1 0x0000002FU 4002 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT2C0 0x0000002EU 4003 #define EVTSVT_LGPT3IN2SEL_PUBID_LRFD_EVT2 0x0000002CU 4004 #define EVTSVT_LGPT3IN2SEL_PUBID_LRFD_EVT1 0x0000002BU 4005 #define EVTSVT_LGPT3IN2SEL_PUBID_LRFD_EVT0 0x0000002AU 4006 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT1_ADC 0x00000029U 4007 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT1_DMA 0x00000028U 4008 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT1C2 0x00000027U 4009 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT1C1 0x00000026U 4010 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT1C0 0x00000025U 4011 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT0_ADC 0x00000024U 4012 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT0_DMA 0x00000023U 4013 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT0C2 0x00000022U 4014 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT0C1 0x00000021U 4015 #define EVTSVT_LGPT3IN2SEL_PUBID_LGPT0C0 0x00000020U 4016 #define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM4 0x0000001FU 4017 #define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM3 0x0000001EU 4018 #define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM2 0x0000001DU 4019 #define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM1 0x0000001CU 4020 #define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM0 0x0000001BU 4021 #define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM_LT 0x0000001AU 4022 #define EVTSVT_LGPT3IN2SEL_PUBID_SYSTIM_HB 0x00000019U 4023 #define EVTSVT_LGPT3IN2SEL_PUBID_ADC_EVT 0x00000011U 4024 #define EVTSVT_LGPT3IN2SEL_PUBID_GPIO_EVT 0x0000000AU 4025 #define EVTSVT_LGPT3IN2SEL_PUBID_NONE 0x00000000U 4026 4027 //***************************************************************************** 4028 // 4029 // Register: EVTSVT_O_LGPT3TENSEL 4030 // 4031 //***************************************************************************** 4032 // Field: [5:0] PUBID 4033 // 4034 // Read/write selection value. 4035 // Writing any other value than values defined by a ENUM may result in 4036 // undefined behavior. 4037 // ENUMs: 4038 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 4039 // LGPT3:ADCTRG setting 4040 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 4041 // setting 4042 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 4043 // by LGPT3:C2CFG setting 4044 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 4045 // by LGPT3:C1CFG setting 4046 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 4047 // by LGPT3:C0CFG setting 4048 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 4049 // LGPT2:ADCTRG setting 4050 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 4051 // setting 4052 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 4053 // by LGPT2:C2CFG setting 4054 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 4055 // by LGPT2:C1CFG setting 4056 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 4057 // by LGPT2:C0CFG setting 4058 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 4059 // LRFDDBELL:SYSTIMOEV.SRC2 4060 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 4061 // LRFDDBELL:SYSTIMOEV.SRC1 4062 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 4063 // LRFDDBELL:SYSTIMOEV.SRC0 4064 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 4065 // LGPT1:ADCTRG setting 4066 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 4067 // setting 4068 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 4069 // by LGPT1:C2CFG setting 4070 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 4071 // by LGPT1:C1CFG setting 4072 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 4073 // by LGPT1:C0CFG setting 4074 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 4075 // LGPT0:ADCTRG setting 4076 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 4077 // setting 4078 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 4079 // by LGPT0:C2CFG setting 4080 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 4081 // by LGPT0:C1CFG setting 4082 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 4083 // by LGPT0:C0CFG setting 4084 // SYSTIM4 SYSTIM Channel 4 event, event flag is 4085 // SYSTIM:MIS.EVT4 4086 // SYSTIM3 SYSTIM Channel 3 event, event flag is 4087 // SYSTIM:MIS.EVT3 4088 // SYSTIM2 SYSTIM Channel 2 event, event flag is 4089 // SYSTIM:MIS.EVT2 4090 // SYSTIM1 SYSTIM Channel 1 event, event flag is 4091 // SYSTIM:MIS.EVT1 4092 // SYSTIM0 SYSTIM Channel 0 event, event flag is 4093 // SYSTIM:MIS.EVT0 4094 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 4095 // signal to SVT clock 4096 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 4097 // ADC_EVT ADC general published event, interrupt flags can 4098 // be found here ADC:MIS1 4099 // GPIO_EVT GPIO generic published event, controlled by 4100 // GPIO:EVTCFG 4101 // NONE Always inactive 4102 #define EVTSVT_LGPT3TENSEL_PUBID_W 6U 4103 #define EVTSVT_LGPT3TENSEL_PUBID_M 0x0000003FU 4104 #define EVTSVT_LGPT3TENSEL_PUBID_S 0U 4105 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT3_ADC 0x00000039U 4106 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT3_DMA 0x00000038U 4107 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT3C2 0x00000036U 4108 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT3C1 0x00000035U 4109 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT3C0 0x00000034U 4110 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT2_ADC 0x00000033U 4111 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT2_DMA 0x00000032U 4112 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT2C2 0x00000030U 4113 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT2C1 0x0000002FU 4114 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT2C0 0x0000002EU 4115 #define EVTSVT_LGPT3TENSEL_PUBID_LRFD_EVT2 0x0000002CU 4116 #define EVTSVT_LGPT3TENSEL_PUBID_LRFD_EVT1 0x0000002BU 4117 #define EVTSVT_LGPT3TENSEL_PUBID_LRFD_EVT0 0x0000002AU 4118 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT1_ADC 0x00000029U 4119 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT1_DMA 0x00000028U 4120 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT1C2 0x00000027U 4121 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT1C1 0x00000026U 4122 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT1C0 0x00000025U 4123 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT0_ADC 0x00000024U 4124 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT0_DMA 0x00000023U 4125 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT0C2 0x00000022U 4126 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT0C1 0x00000021U 4127 #define EVTSVT_LGPT3TENSEL_PUBID_LGPT0C0 0x00000020U 4128 #define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM4 0x0000001FU 4129 #define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM3 0x0000001EU 4130 #define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM2 0x0000001DU 4131 #define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM1 0x0000001CU 4132 #define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM0 0x0000001BU 4133 #define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM_LT 0x0000001AU 4134 #define EVTSVT_LGPT3TENSEL_PUBID_SYSTIM_HB 0x00000019U 4135 #define EVTSVT_LGPT3TENSEL_PUBID_ADC_EVT 0x00000011U 4136 #define EVTSVT_LGPT3TENSEL_PUBID_GPIO_EVT 0x0000000AU 4137 #define EVTSVT_LGPT3TENSEL_PUBID_NONE 0x00000000U 4138 4139 //***************************************************************************** 4140 // 4141 // Register: EVTSVT_O_LRFDIN0SEL 4142 // 4143 //***************************************************************************** 4144 // Field: [5:0] PUBID 4145 // 4146 // Read only selection value 4147 // ENUMs: 4148 // SYSTIM2 SYSTIM Channel 2 event, event flag is 4149 // SYSTIM:MIS.EVT2 4150 #define EVTSVT_LRFDIN0SEL_PUBID_W 6U 4151 #define EVTSVT_LRFDIN0SEL_PUBID_M 0x0000003FU 4152 #define EVTSVT_LRFDIN0SEL_PUBID_S 0U 4153 #define EVTSVT_LRFDIN0SEL_PUBID_SYSTIM2 0x0000001DU 4154 4155 //***************************************************************************** 4156 // 4157 // Register: EVTSVT_O_LRFDIN1SEL 4158 // 4159 //***************************************************************************** 4160 // Field: [5:0] PUBID 4161 // 4162 // Read only selection value 4163 // ENUMs: 4164 // SYSTIM3 SYSTIM Channel 3 event, event flag is 4165 // SYSTIM:MIS.EVT3 4166 #define EVTSVT_LRFDIN1SEL_PUBID_W 6U 4167 #define EVTSVT_LRFDIN1SEL_PUBID_M 0x0000003FU 4168 #define EVTSVT_LRFDIN1SEL_PUBID_S 0U 4169 #define EVTSVT_LRFDIN1SEL_PUBID_SYSTIM3 0x0000001EU 4170 4171 //***************************************************************************** 4172 // 4173 // Register: EVTSVT_O_LRFDIN2SEL 4174 // 4175 //***************************************************************************** 4176 // Field: [5:0] PUBID 4177 // 4178 // Read only selection value 4179 // ENUMs: 4180 // SYSTIM4 SYSTIM Channel 4 event, event flag is 4181 // SYSTIM:MIS.EVT4 4182 #define EVTSVT_LRFDIN2SEL_PUBID_W 6U 4183 #define EVTSVT_LRFDIN2SEL_PUBID_M 0x0000003FU 4184 #define EVTSVT_LRFDIN2SEL_PUBID_S 0U 4185 #define EVTSVT_LRFDIN2SEL_PUBID_SYSTIM4 0x0000001FU 4186 4187 //***************************************************************************** 4188 // 4189 // Register: EVTSVT_O_DMACH0SEL 4190 // 4191 //***************************************************************************** 4192 // Field: [2:0] IPID 4193 // 4194 // Read/write selection value. 4195 // Writing any other value than values defined by a ENUM may result in 4196 // undefined behavior. 4197 // ENUMs: 4198 // UART0RXTRG Selects uart0rxtrg as channel source 4199 // SPI0TXTRG Selects spi0txtrg as channel source 4200 #define EVTSVT_DMACH0SEL_IPID_W 3U 4201 #define EVTSVT_DMACH0SEL_IPID_M 0x00000007U 4202 #define EVTSVT_DMACH0SEL_IPID_S 0U 4203 #define EVTSVT_DMACH0SEL_IPID_UART0RXTRG 0x00000007U 4204 #define EVTSVT_DMACH0SEL_IPID_SPI0TXTRG 0x00000000U 4205 4206 //***************************************************************************** 4207 // 4208 // Register: EVTSVT_O_DMACH1SEL 4209 // 4210 //***************************************************************************** 4211 // Field: [2:0] IPID 4212 // 4213 // Read/write selection value. 4214 // Writing any other value than values defined by a ENUM may result in 4215 // undefined behavior. 4216 // ENUMs: 4217 // UART0TXTRG Selects uart0txtrg as channel source 4218 // SPI0RXTRG Selects spi0rxtrg as channel source 4219 #define EVTSVT_DMACH1SEL_IPID_W 3U 4220 #define EVTSVT_DMACH1SEL_IPID_M 0x00000007U 4221 #define EVTSVT_DMACH1SEL_IPID_S 0U 4222 #define EVTSVT_DMACH1SEL_IPID_UART0TXTRG 0x00000006U 4223 #define EVTSVT_DMACH1SEL_IPID_SPI0RXTRG 0x00000001U 4224 4225 //***************************************************************************** 4226 // 4227 // Register: EVTSVT_O_DMACH2SEL 4228 // 4229 //***************************************************************************** 4230 // Field: [2:0] IPID 4231 // 4232 // Read/write selection value. 4233 // Writing any other value than values defined by a ENUM may result in 4234 // undefined behavior. 4235 // ENUMs: 4236 // UART0TXTRG Selects uart0txtrg as channel source 4237 // RSVD Reserved value. Should not be programmed. 4238 #define EVTSVT_DMACH2SEL_IPID_W 3U 4239 #define EVTSVT_DMACH2SEL_IPID_M 0x00000007U 4240 #define EVTSVT_DMACH2SEL_IPID_S 0U 4241 #define EVTSVT_DMACH2SEL_IPID_UART0TXTRG 0x00000006U 4242 #define EVTSVT_DMACH2SEL_IPID_RSVD 0x00000002U 4243 4244 //***************************************************************************** 4245 // 4246 // Register: EVTSVT_O_DMACH3SEL 4247 // 4248 //***************************************************************************** 4249 // Field: [2:0] IPID 4250 // 4251 // Read/write selection value. 4252 // Writing any other value than values defined by a ENUM may result in 4253 // undefined behavior. 4254 // ENUMs: 4255 // UART0RXTRG Selects uart0rxtrg as channel source 4256 // ADC0TRG Selects adc0trg as channel source 4257 #define EVTSVT_DMACH3SEL_IPID_W 3U 4258 #define EVTSVT_DMACH3SEL_IPID_M 0x00000007U 4259 #define EVTSVT_DMACH3SEL_IPID_S 0U 4260 #define EVTSVT_DMACH3SEL_IPID_UART0RXTRG 0x00000007U 4261 #define EVTSVT_DMACH3SEL_IPID_ADC0TRG 0x00000005U 4262 4263 //***************************************************************************** 4264 // 4265 // Register: EVTSVT_O_DMACH4SEL 4266 // 4267 //***************************************************************************** 4268 // Field: [2:0] IPID 4269 // 4270 // Read/write selection value. 4271 // Writing any other value than values defined by a ENUM may result in 4272 // undefined behavior. 4273 // ENUMs: 4274 // LAESTRGA Selects laestrga as channel source 4275 // RSVD Reserved value. Should not be programmed. 4276 #define EVTSVT_DMACH4SEL_IPID_W 3U 4277 #define EVTSVT_DMACH4SEL_IPID_M 0x00000007U 4278 #define EVTSVT_DMACH4SEL_IPID_S 0U 4279 #define EVTSVT_DMACH4SEL_IPID_LAESTRGA 0x00000003U 4280 #define EVTSVT_DMACH4SEL_IPID_RSVD 0x00000002U 4281 4282 //***************************************************************************** 4283 // 4284 // Register: EVTSVT_O_DMACH5SEL 4285 // 4286 //***************************************************************************** 4287 // Field: [2:0] IPID 4288 // 4289 // Read/write selection value. 4290 // Writing any other value than values defined by a ENUM may result in 4291 // undefined behavior. 4292 // ENUMs: 4293 // ADC0TRG Selects adc0trg as channel source 4294 // LAESTRGB Selects laestrgb as channel source 4295 #define EVTSVT_DMACH5SEL_IPID_W 3U 4296 #define EVTSVT_DMACH5SEL_IPID_M 0x00000007U 4297 #define EVTSVT_DMACH5SEL_IPID_S 0U 4298 #define EVTSVT_DMACH5SEL_IPID_ADC0TRG 0x00000005U 4299 #define EVTSVT_DMACH5SEL_IPID_LAESTRGB 0x00000004U 4300 4301 //***************************************************************************** 4302 // 4303 // Register: EVTSVT_O_DMACH6SEL 4304 // 4305 //***************************************************************************** 4306 // Field: [16] EDGDETDIS 4307 // 4308 // Edge detect disable. 4309 // 0: Enabled. 4310 // 1: Disabled 4311 #define EVTSVT_DMACH6SEL_EDGDETDIS 0x00010000U 4312 #define EVTSVT_DMACH6SEL_EDGDETDIS_M 0x00010000U 4313 #define EVTSVT_DMACH6SEL_EDGDETDIS_S 16U 4314 4315 // Field: [5:0] PUBID 4316 // 4317 // Read/write selection value. 4318 // Writing any other value than values defined by a ENUM may result in 4319 // undefined behavior. 4320 // ENUMs: 4321 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 4322 // LGPT3:ADCTRG setting 4323 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 4324 // setting 4325 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 4326 // found here LGPT3:MIS 4327 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 4328 // by LGPT3:C2CFG setting 4329 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 4330 // by LGPT3:C1CFG setting 4331 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 4332 // by LGPT3:C0CFG setting 4333 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 4334 // LGPT2:ADCTRG setting 4335 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 4336 // setting 4337 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 4338 // found here LGPT2:MIS 4339 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 4340 // by LGPT2:C2CFG setting 4341 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 4342 // by LGPT2:C1CFG setting 4343 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 4344 // by LGPT2:C0CFG setting 4345 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 4346 // LRFDDBELL:SYSTIMOEV.SRC2 4347 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 4348 // LRFDDBELL:SYSTIMOEV.SRC1 4349 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 4350 // LRFDDBELL:SYSTIMOEV.SRC0 4351 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 4352 // LGPT1:ADCTRG setting 4353 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 4354 // setting 4355 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 4356 // by LGPT1:C2CFG setting 4357 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 4358 // by LGPT1:C1CFG setting 4359 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 4360 // by LGPT1:C0CFG setting 4361 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 4362 // LGPT0:ADCTRG setting 4363 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 4364 // setting 4365 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 4366 // by LGPT0:C2CFG setting 4367 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 4368 // by LGPT0:C1CFG setting 4369 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 4370 // by LGPT0:C0CFG setting 4371 // SYSTIM4 SYSTIM Channel 4 event, event flag is 4372 // SYSTIM:MIS.EVT4 4373 // SYSTIM3 SYSTIM Channel 3 event, event flag is 4374 // SYSTIM:MIS.EVT3 4375 // SYSTIM2 SYSTIM Channel 2 event, event flag is 4376 // SYSTIM:MIS.EVT2 4377 // SYSTIM1 SYSTIM Channel 1 event, event flag is 4378 // SYSTIM:MIS.EVT1 4379 // SYSTIM0 SYSTIM Channel 0 event, event flag is 4380 // SYSTIM:MIS.EVT0 4381 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 4382 // signal to SVT clock 4383 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 4384 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 4385 // found here I2C0:MIS 4386 // UART0_COMB UART0 combined interrupt, interrupt flags are 4387 // found here UART0:MIS 4388 // AES_COMB AES accelerator combined interrupt request, 4389 // interrupt flags can be found here AES:MIS 4390 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 4391 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 4392 // can be found here DMA:REQDONE 4393 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 4394 // found here LGPT1:MIS 4395 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 4396 // found here LGPT0:MIS 4397 // ADC_EVT ADC general published event, interrupt flags can 4398 // be found here ADC:MIS1 4399 // ADC_COMB ADC combined interrupt request, interrupt flags 4400 // can be found here ADC:MIS0 4401 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 4402 // can be found here SPI0:MIS 4403 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 4404 // here LRFDDBELL:MIS2 4405 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 4406 // here LRFDDBELL:MIS1 4407 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 4408 // here LRFDDBELL:MIS0 4409 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 4410 // flash operation has completed, interrupt flags 4411 // can be found here FLASH:MIS 4412 // GPIO_EVT GPIO generic published event, controlled by 4413 // GPIO:EVTCFG 4414 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 4415 // can be found here GPIO:MIS 4416 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 4417 // found here SYSTIM:MIS 4418 // AON_IOC_COMB IOC synchronous combined event, controlled by 4419 // IOC:EVTCFG 4420 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 4421 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 4422 // found here DBGSS:MIS 4423 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 4424 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 4425 // can be found here CKMD:MIS 4426 // AON_PMU_COMB PMU combined interrupt request for BATMON, 4427 // interrupt flags can be found here PMUD:EVENT 4428 // NONE Always inactive 4429 #define EVTSVT_DMACH6SEL_PUBID_W 6U 4430 #define EVTSVT_DMACH6SEL_PUBID_M 0x0000003FU 4431 #define EVTSVT_DMACH6SEL_PUBID_S 0U 4432 #define EVTSVT_DMACH6SEL_PUBID_LGPT3_ADC 0x00000039U 4433 #define EVTSVT_DMACH6SEL_PUBID_LGPT3_DMA 0x00000038U 4434 #define EVTSVT_DMACH6SEL_PUBID_LGPT3_COMB 0x00000037U 4435 #define EVTSVT_DMACH6SEL_PUBID_LGPT3C2 0x00000036U 4436 #define EVTSVT_DMACH6SEL_PUBID_LGPT3C1 0x00000035U 4437 #define EVTSVT_DMACH6SEL_PUBID_LGPT3C0 0x00000034U 4438 #define EVTSVT_DMACH6SEL_PUBID_LGPT2_ADC 0x00000033U 4439 #define EVTSVT_DMACH6SEL_PUBID_LGPT2_DMA 0x00000032U 4440 #define EVTSVT_DMACH6SEL_PUBID_LGPT2_COMB 0x00000031U 4441 #define EVTSVT_DMACH6SEL_PUBID_LGPT2C2 0x00000030U 4442 #define EVTSVT_DMACH6SEL_PUBID_LGPT2C1 0x0000002FU 4443 #define EVTSVT_DMACH6SEL_PUBID_LGPT2C0 0x0000002EU 4444 #define EVTSVT_DMACH6SEL_PUBID_LRFD_EVT2 0x0000002CU 4445 #define EVTSVT_DMACH6SEL_PUBID_LRFD_EVT1 0x0000002BU 4446 #define EVTSVT_DMACH6SEL_PUBID_LRFD_EVT0 0x0000002AU 4447 #define EVTSVT_DMACH6SEL_PUBID_LGPT1_ADC 0x00000029U 4448 #define EVTSVT_DMACH6SEL_PUBID_LGPT1_DMA 0x00000028U 4449 #define EVTSVT_DMACH6SEL_PUBID_LGPT1C2 0x00000027U 4450 #define EVTSVT_DMACH6SEL_PUBID_LGPT1C1 0x00000026U 4451 #define EVTSVT_DMACH6SEL_PUBID_LGPT1C0 0x00000025U 4452 #define EVTSVT_DMACH6SEL_PUBID_LGPT0_ADC 0x00000024U 4453 #define EVTSVT_DMACH6SEL_PUBID_LGPT0_DMA 0x00000023U 4454 #define EVTSVT_DMACH6SEL_PUBID_LGPT0C2 0x00000022U 4455 #define EVTSVT_DMACH6SEL_PUBID_LGPT0C1 0x00000021U 4456 #define EVTSVT_DMACH6SEL_PUBID_LGPT0C0 0x00000020U 4457 #define EVTSVT_DMACH6SEL_PUBID_SYSTIM4 0x0000001FU 4458 #define EVTSVT_DMACH6SEL_PUBID_SYSTIM3 0x0000001EU 4459 #define EVTSVT_DMACH6SEL_PUBID_SYSTIM2 0x0000001DU 4460 #define EVTSVT_DMACH6SEL_PUBID_SYSTIM1 0x0000001CU 4461 #define EVTSVT_DMACH6SEL_PUBID_SYSTIM0 0x0000001BU 4462 #define EVTSVT_DMACH6SEL_PUBID_SYSTIM_LT 0x0000001AU 4463 #define EVTSVT_DMACH6SEL_PUBID_SYSTIM_HB 0x00000019U 4464 #define EVTSVT_DMACH6SEL_PUBID_I2C0_IRQ 0x00000018U 4465 #define EVTSVT_DMACH6SEL_PUBID_UART0_COMB 0x00000017U 4466 #define EVTSVT_DMACH6SEL_PUBID_AES_COMB 0x00000016U 4467 #define EVTSVT_DMACH6SEL_PUBID_DMA_ERR 0x00000015U 4468 #define EVTSVT_DMACH6SEL_PUBID_DMA_DONE_COMB 0x00000014U 4469 #define EVTSVT_DMACH6SEL_PUBID_LGPT1_COMB 0x00000013U 4470 #define EVTSVT_DMACH6SEL_PUBID_LGPT0_COMB 0x00000012U 4471 #define EVTSVT_DMACH6SEL_PUBID_ADC_EVT 0x00000011U 4472 #define EVTSVT_DMACH6SEL_PUBID_ADC_COMB 0x00000010U 4473 #define EVTSVT_DMACH6SEL_PUBID_SPI0_COMB 0x0000000FU 4474 #define EVTSVT_DMACH6SEL_PUBID_LRFD_IRQ2 0x0000000EU 4475 #define EVTSVT_DMACH6SEL_PUBID_LRFD_IRQ1 0x0000000DU 4476 #define EVTSVT_DMACH6SEL_PUBID_LRFD_IRQ0 0x0000000CU 4477 #define EVTSVT_DMACH6SEL_PUBID_FLASH_IRQ 0x0000000BU 4478 #define EVTSVT_DMACH6SEL_PUBID_GPIO_EVT 0x0000000AU 4479 #define EVTSVT_DMACH6SEL_PUBID_GPIO_COMB 0x00000009U 4480 #define EVTSVT_DMACH6SEL_PUBID_SYSTIM_COMB 0x00000008U 4481 #define EVTSVT_DMACH6SEL_PUBID_AON_IOC_COMB 0x00000007U 4482 #define EVTSVT_DMACH6SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 4483 #define EVTSVT_DMACH6SEL_PUBID_AON_DBG_COMB 0x00000005U 4484 #define EVTSVT_DMACH6SEL_PUBID_AON_RTC_COMB 0x00000004U 4485 #define EVTSVT_DMACH6SEL_PUBID_AON_CKM_COMB 0x00000003U 4486 #define EVTSVT_DMACH6SEL_PUBID_AON_PMU_COMB 0x00000002U 4487 #define EVTSVT_DMACH6SEL_PUBID_NONE 0x00000000U 4488 4489 //***************************************************************************** 4490 // 4491 // Register: EVTSVT_O_DMACH7SEL 4492 // 4493 //***************************************************************************** 4494 // Field: [16] EDGDETDIS 4495 // 4496 // Edge detect disable. 4497 // 0: Enabled. 4498 // 1: Disabled 4499 #define EVTSVT_DMACH7SEL_EDGDETDIS 0x00010000U 4500 #define EVTSVT_DMACH7SEL_EDGDETDIS_M 0x00010000U 4501 #define EVTSVT_DMACH7SEL_EDGDETDIS_S 16U 4502 4503 // Field: [5:0] PUBID 4504 // 4505 // Read/write selection value. 4506 // Writing any other value than values defined by a ENUM may result in 4507 // undefined behavior. 4508 // ENUMs: 4509 // LGPT3_ADC LGPT3 ADC trigger event, controlled by 4510 // LGPT3:ADCTRG setting 4511 // LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA 4512 // setting 4513 // LGPT3_COMB LGPT3 combined interrupt, interrupt flags are 4514 // found here LGPT3:MIS 4515 // LGPT3C2 LGPT3 compare/capture output event 2, controlled 4516 // by LGPT3:C2CFG setting 4517 // LGPT3C1 LGPT3 compare/capture output event 1, controlled 4518 // by LGPT3:C1CFG setting 4519 // LGPT3C0 LGPT3 compare/capture output event 0, controlled 4520 // by LGPT3:C0CFG setting 4521 // LGPT2_ADC LGPT2 ADC trigger event, controlled by 4522 // LGPT2:ADCTRG setting 4523 // LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA 4524 // setting 4525 // LGPT2_COMB LGPT2 combined interrupt, interrupt flags are 4526 // found here LGPT2:MIS 4527 // LGPT2C2 LGPT0 compare/capture output event 2, controlled 4528 // by LGPT2:C2CFG setting 4529 // LGPT2C1 LGPT2 compare/capture output event 1, controlled 4530 // by LGPT2:C1CFG setting 4531 // LGPT2C0 LGPT2 compare/capture output event 0, controlled 4532 // by LGPT2:C0CFG setting 4533 // LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by 4534 // LRFDDBELL:SYSTIMOEV.SRC2 4535 // LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by 4536 // LRFDDBELL:SYSTIMOEV.SRC1 4537 // LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by 4538 // LRFDDBELL:SYSTIMOEV.SRC0 4539 // LGPT1_ADC LGPT1 ADC trigger event, controlled by 4540 // LGPT1:ADCTRG setting 4541 // LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA 4542 // setting 4543 // LGPT1C2 LGPT1 compare/capture output event 2, controlled 4544 // by LGPT1:C2CFG setting 4545 // LGPT1C1 LGPT1 compare/capture output event 1, controlled 4546 // by LGPT1:C1CFG setting 4547 // LGPT1C0 LGPT1 compare/capture output event 0, controlled 4548 // by LGPT1:C0CFG setting 4549 // LGPT0_ADC LGPT0 ADC trigger event, controlled by 4550 // LGPT0:ADCTRG setting 4551 // LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA 4552 // setting 4553 // LGPT0C2 LGPT0 compare/capture output event 2, controlled 4554 // by LGPT0:C2CFG setting 4555 // LGPT0C1 LGPT0 compare/capture output event 1, controlled 4556 // by LGPT0:C1CFG setting 4557 // LGPT0C0 LGPT0 compare/capture output event 0, controlled 4558 // by LGPT0:C0CFG setting 4559 // SYSTIM4 SYSTIM Channel 4 event, event flag is 4560 // SYSTIM:MIS.EVT4 4561 // SYSTIM3 SYSTIM Channel 3 event, event flag is 4562 // SYSTIM:MIS.EVT3 4563 // SYSTIM2 SYSTIM Channel 2 event, event flag is 4564 // SYSTIM:MIS.EVT2 4565 // SYSTIM1 SYSTIM Channel 1 event, event flag is 4566 // SYSTIM:MIS.EVT1 4567 // SYSTIM0 SYSTIM Channel 0 event, event flag is 4568 // SYSTIM:MIS.EVT0 4569 // SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK 4570 // signal to SVT clock 4571 // SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT 4572 // I2C0_IRQ Interrupt event from I2C0, interrupt flags can be 4573 // found here I2C0:MIS 4574 // UART0_COMB UART0 combined interrupt, interrupt flags are 4575 // found here UART0:MIS 4576 // AES_COMB AES accelerator combined interrupt request, 4577 // interrupt flags can be found here AES:MIS 4578 // DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS 4579 // DMA_DONE_COMB DMA combined done interrupt, corresponding flags 4580 // can be found here DMA:REQDONE 4581 // LGPT1_COMB LGPT1 combined interrupt, interrupt flags are 4582 // found here LGPT1:MIS 4583 // LGPT0_COMB LGPT0 combined interrupt, interrupt flags are 4584 // found here LGPT0:MIS 4585 // ADC_EVT ADC general published event, interrupt flags can 4586 // be found here ADC:MIS1 4587 // ADC_COMB ADC combined interrupt request, interrupt flags 4588 // can be found here ADC:MIS0 4589 // SPI0_COMB SPI0 combined interrupt request, interrupt flags 4590 // can be found here SPI0:MIS 4591 // LRFD_IRQ2 LRFD combined event, interrupt flags can be found 4592 // here LRFDDBELL:MIS2 4593 // LRFD_IRQ1 LRFD combined event, interrupt flags can be found 4594 // here LRFDDBELL:MIS1 4595 // LRFD_IRQ0 LRFD combined event, interrupt flags can be found 4596 // here LRFDDBELL:MIS0 4597 // FLASH_IRQ NoWrapper Flash interrupt indicating that the 4598 // flash operation has completed, interrupt flags 4599 // can be found here FLASH:MIS 4600 // GPIO_EVT GPIO generic published event, controlled by 4601 // GPIO:EVTCFG 4602 // GPIO_COMB GPIO combined wake up interrupt, interrupt flags 4603 // can be found here GPIO:MIS 4604 // SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are 4605 // found here SYSTIM:MIS 4606 // AON_IOC_COMB IOC synchronous combined event, controlled by 4607 // IOC:EVTCFG 4608 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 4609 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 4610 // found here DBGSS:MIS 4611 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 4612 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 4613 // can be found here CKMD:MIS 4614 // AON_PMU_COMB PMU combined interrupt request for BATMON, 4615 // interrupt flags can be found here PMUD:EVENT 4616 // NONE Always inactive 4617 #define EVTSVT_DMACH7SEL_PUBID_W 6U 4618 #define EVTSVT_DMACH7SEL_PUBID_M 0x0000003FU 4619 #define EVTSVT_DMACH7SEL_PUBID_S 0U 4620 #define EVTSVT_DMACH7SEL_PUBID_LGPT3_ADC 0x00000039U 4621 #define EVTSVT_DMACH7SEL_PUBID_LGPT3_DMA 0x00000038U 4622 #define EVTSVT_DMACH7SEL_PUBID_LGPT3_COMB 0x00000037U 4623 #define EVTSVT_DMACH7SEL_PUBID_LGPT3C2 0x00000036U 4624 #define EVTSVT_DMACH7SEL_PUBID_LGPT3C1 0x00000035U 4625 #define EVTSVT_DMACH7SEL_PUBID_LGPT3C0 0x00000034U 4626 #define EVTSVT_DMACH7SEL_PUBID_LGPT2_ADC 0x00000033U 4627 #define EVTSVT_DMACH7SEL_PUBID_LGPT2_DMA 0x00000032U 4628 #define EVTSVT_DMACH7SEL_PUBID_LGPT2_COMB 0x00000031U 4629 #define EVTSVT_DMACH7SEL_PUBID_LGPT2C2 0x00000030U 4630 #define EVTSVT_DMACH7SEL_PUBID_LGPT2C1 0x0000002FU 4631 #define EVTSVT_DMACH7SEL_PUBID_LGPT2C0 0x0000002EU 4632 #define EVTSVT_DMACH7SEL_PUBID_LRFD_EVT2 0x0000002CU 4633 #define EVTSVT_DMACH7SEL_PUBID_LRFD_EVT1 0x0000002BU 4634 #define EVTSVT_DMACH7SEL_PUBID_LRFD_EVT0 0x0000002AU 4635 #define EVTSVT_DMACH7SEL_PUBID_LGPT1_ADC 0x00000029U 4636 #define EVTSVT_DMACH7SEL_PUBID_LGPT1_DMA 0x00000028U 4637 #define EVTSVT_DMACH7SEL_PUBID_LGPT1C2 0x00000027U 4638 #define EVTSVT_DMACH7SEL_PUBID_LGPT1C1 0x00000026U 4639 #define EVTSVT_DMACH7SEL_PUBID_LGPT1C0 0x00000025U 4640 #define EVTSVT_DMACH7SEL_PUBID_LGPT0_ADC 0x00000024U 4641 #define EVTSVT_DMACH7SEL_PUBID_LGPT0_DMA 0x00000023U 4642 #define EVTSVT_DMACH7SEL_PUBID_LGPT0C2 0x00000022U 4643 #define EVTSVT_DMACH7SEL_PUBID_LGPT0C1 0x00000021U 4644 #define EVTSVT_DMACH7SEL_PUBID_LGPT0C0 0x00000020U 4645 #define EVTSVT_DMACH7SEL_PUBID_SYSTIM4 0x0000001FU 4646 #define EVTSVT_DMACH7SEL_PUBID_SYSTIM3 0x0000001EU 4647 #define EVTSVT_DMACH7SEL_PUBID_SYSTIM2 0x0000001DU 4648 #define EVTSVT_DMACH7SEL_PUBID_SYSTIM1 0x0000001CU 4649 #define EVTSVT_DMACH7SEL_PUBID_SYSTIM0 0x0000001BU 4650 #define EVTSVT_DMACH7SEL_PUBID_SYSTIM_LT 0x0000001AU 4651 #define EVTSVT_DMACH7SEL_PUBID_SYSTIM_HB 0x00000019U 4652 #define EVTSVT_DMACH7SEL_PUBID_I2C0_IRQ 0x00000018U 4653 #define EVTSVT_DMACH7SEL_PUBID_UART0_COMB 0x00000017U 4654 #define EVTSVT_DMACH7SEL_PUBID_AES_COMB 0x00000016U 4655 #define EVTSVT_DMACH7SEL_PUBID_DMA_ERR 0x00000015U 4656 #define EVTSVT_DMACH7SEL_PUBID_DMA_DONE_COMB 0x00000014U 4657 #define EVTSVT_DMACH7SEL_PUBID_LGPT1_COMB 0x00000013U 4658 #define EVTSVT_DMACH7SEL_PUBID_LGPT0_COMB 0x00000012U 4659 #define EVTSVT_DMACH7SEL_PUBID_ADC_EVT 0x00000011U 4660 #define EVTSVT_DMACH7SEL_PUBID_ADC_COMB 0x00000010U 4661 #define EVTSVT_DMACH7SEL_PUBID_SPI0_COMB 0x0000000FU 4662 #define EVTSVT_DMACH7SEL_PUBID_LRFD_IRQ2 0x0000000EU 4663 #define EVTSVT_DMACH7SEL_PUBID_LRFD_IRQ1 0x0000000DU 4664 #define EVTSVT_DMACH7SEL_PUBID_LRFD_IRQ0 0x0000000CU 4665 #define EVTSVT_DMACH7SEL_PUBID_FLASH_IRQ 0x0000000BU 4666 #define EVTSVT_DMACH7SEL_PUBID_GPIO_EVT 0x0000000AU 4667 #define EVTSVT_DMACH7SEL_PUBID_GPIO_COMB 0x00000009U 4668 #define EVTSVT_DMACH7SEL_PUBID_SYSTIM_COMB 0x00000008U 4669 #define EVTSVT_DMACH7SEL_PUBID_AON_IOC_COMB 0x00000007U 4670 #define EVTSVT_DMACH7SEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 4671 #define EVTSVT_DMACH7SEL_PUBID_AON_DBG_COMB 0x00000005U 4672 #define EVTSVT_DMACH7SEL_PUBID_AON_RTC_COMB 0x00000004U 4673 #define EVTSVT_DMACH7SEL_PUBID_AON_CKM_COMB 0x00000003U 4674 #define EVTSVT_DMACH7SEL_PUBID_AON_PMU_COMB 0x00000002U 4675 #define EVTSVT_DMACH7SEL_PUBID_NONE 0x00000000U 4676 4677 4678 #endif // __EVTSVT__ 4679
