Home
last modified time | relevance | path

Searched refs:EUSCI_A_CMSIS (Results 1 – 3 of 3) sorted by relevance

/hal_ti-latest/simplelink/source/ti/devices/msp432p4xx/driverlib/
Duart.c69 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; in UART_initModule()
72 EUSCI_A_CMSIS(moduleInstance)->CTLW0 = in UART_initModule()
73 (EUSCI_A_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_A_CTLW0_SSEL_MASK) in UART_initModule()
78 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 1; in UART_initModule()
80 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 0; in UART_initModule()
84 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 1; in UART_initModule()
86 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 0; in UART_initModule()
92 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 0; in UART_initModule()
95 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1; in UART_initModule()
96 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 0; in UART_initModule()
[all …]
Dspi.c94 EUSCI_A_CMSIS(moduleInstance)->CTLW0 = in SPI_initMaster()
95 (EUSCI_A_CMSIS(moduleInstance)->CTLW0 in SPI_initMaster()
102 EUSCI_A_CMSIS(moduleInstance)->BRW = in SPI_initMaster()
107 EUSCI_A_CMSIS(moduleInstance)->MCTLW = 0; in SPI_initMaster()
225 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; in SPI_initSlave()
228 EUSCI_A_CMSIS(moduleInstance)->CTLW0 = in SPI_initSlave()
229 (EUSCI_A_CMSIS(moduleInstance)->CTLW0 in SPI_initSlave()
416 & EUSCI_A_CMSIS(moduleInstance)->IE; in SPI_getEnabledInterruptStatus()
978 EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0 in EUSCI_A_SPI_select4PinFunctionality()
1000 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; in EUSCI_A_SPI_masterChangeClock()
[all …]
Deusci.h37 #define EUSCI_A_CMSIS(x) ((EUSCI_A_Type *) x) macro