Searched refs:DMA_BASE (Results 1 – 9 of 9) sorted by relevance
51 HWREG(DMA_BASE + DMA_O_SETBURST) = channelBitMask; in uDMAEnableChannelAttribute()57 HWREG(DMA_BASE + DMA_O_SETREQMASK) = channelBitMask; in uDMAEnableChannelAttribute()64 HWREG(DMA_BASE + DMA_O_SETCHNLPRIALT) = channelBitMask; in uDMAEnableChannelAttribute()70 HWREG(DMA_BASE + DMA_O_SETCHNLPRIORITY) = channelBitMask; in uDMAEnableChannelAttribute()87 HWREG(DMA_BASE + DMA_O_CLEARBURST) = channelBitMask; in uDMADisableChannelAttribute()93 HWREG(DMA_BASE + DMA_O_CLEARREQMASK) = channelBitMask; in uDMADisableChannelAttribute()100 HWREG(DMA_BASE + DMA_O_CLEARCHNLPRIALT) = channelBitMask; in uDMADisableChannelAttribute()106 HWREG(DMA_BASE + DMA_O_CLEARCHNLPRIORITY) = channelBitMask; in uDMADisableChannelAttribute()120 if (HWREG(DMA_BASE + DMA_O_SETBURST) & (channelBitMask)) in uDMAGetChannelAttribute()126 if (HWREG(DMA_BASE + DMA_O_SETCHNLPRIALT) & (channelBitMask)) in uDMAGetChannelAttribute()[all …]
295 HWREG(DMA_BASE + DMA_O_CFG) = DMA_CFG_MASTERENABLE; in uDMAEnable()311 HWREG(DMA_BASE + DMA_O_CFG) = 0; in uDMADisable()328 return (HWREG(DMA_BASE + DMA_O_ERROR)); in uDMAGetErrorStatus()344 HWREG(DMA_BASE + DMA_O_ERROR) = DMA_ERROR_STATUS; in uDMAClearErrorStatus()366 HWREG(DMA_BASE + DMA_O_SETCHANNELEN) = channelBitMask; in uDMAEnableChannel()384 HWREG(DMA_BASE + DMA_O_CLEARCHANNELEN) = channelBitMask; in uDMADisableChannel()406 return ((HWREG(DMA_BASE + DMA_O_SETCHANNELEN) & (channelBitMask)) ? true : false); in uDMAIsChannelEnabled()443 HWREG(DMA_BASE + DMA_O_CTRL) = (uint32_t)pControlTable; in uDMASetControlBase()461 return ((void *)HWREG(DMA_BASE + DMA_O_CTRL)); in uDMAGetControlBase()479 return ((void *)HWREG(DMA_BASE + DMA_O_ALTCTRL)); in uDMAGetControlAlternateBase()[all …]
62 #define DMA_BASE 0x40026000 // DMA macro
282 #define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address … macro1344 #define DMA_Channel ((DMA_Channel_Type *) DMA_BASE)1345 #define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000))
273 #define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address … macro1397 #define DMA_Channel ((DMA_Channel_Type *) DMA_BASE)1398 #define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000))
274 #define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address … macro1249 #define DMA_Channel ((DMA_Channel_Type *) DMA_BASE)1250 #define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000))
