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Searched refs:CRYPTO_O_IRQEN (Results 1 – 10 of 10) sorted by relevance

/hal_ti-latest/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/
Dcrypto.c106 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | in CRYPTOAesLoadKey()
182 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; in CRYPTOAesCbc()
285 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; in CRYPTOAesEcb()
417 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | in CRYPTOCcmAuthEncrypt()
523 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE; in CRYPTOCcmAuthEncrypt()
534 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; in CRYPTOCcmAuthEncrypt()
664 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | in CRYPTOCcmInvAuthDecrypt()
771 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE; in CRYPTOCcmInvAuthDecrypt()
782 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; in CRYPTOCcmInvAuthDecrypt()
Dsha2.h598 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; in SHA2IntEnable()
623 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; in SHA2IntDisable()
642 mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); in SHA2IntStatusMasked()
Daes.h624 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; in AESIntEnable()
649 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; in AESIntDisable()
668 mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); in AESIntStatusMasked()
Dcrypto.h616 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= ui32IntFlags; in CRYPTOIntEnable()
642 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~ui32IntFlags; in CRYPTOIntDisable()
671 ui32Mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); in CRYPTOIntStatus()
Daes.c191 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE_M | CRYPTO_IRQEN_RESULT_AVAIL_M; in AESWriteToKeyStore()
/hal_ti-latest/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/
Dsha2.h596 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; in SHA2IntEnable()
621 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; in SHA2IntDisable()
640 mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); in SHA2IntStatusMasked()
Daes.h667 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; in AESIntEnable()
692 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; in AESIntDisable()
711 mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); in AESIntStatusMasked()
Daes.c240 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE_M | CRYPTO_IRQEN_RESULT_AVAIL_M; in AESWriteToKeyStore()
/hal_ti-latest/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/inc/
Dhw_crypto.h341 #define CRYPTO_O_IRQEN 0x00000784 macro
/hal_ti-latest/simplelink/source/ti/devices/cc13x2_cc26x2/inc/
Dhw_crypto.h341 #define CRYPTO_O_IRQEN 0x00000784 macro