Searched refs:COMMON_REG_BASE (Results 1 – 6 of 6) sorted by relevance
654 HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x1; in GPIODMATriggerEnable()658 HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x2; in GPIODMATriggerEnable()662 HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x4; in GPIODMATriggerEnable()666 HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x8; in GPIODMATriggerEnable()696 HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x1; in GPIODMATriggerDisable()700 HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x2; in GPIODMATriggerDisable()704 HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x4; in GPIODMATriggerDisable()708 HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x8; in GPIODMATriggerDisable()
61 COMMON_REG_BASE + COMMON_REG_O_SPI_Properties_Register249 ui32SemVal = ((HWREG(COMMON_REG_BASE + in HwSpinLockTest()254 ui32SemVal = ((HWREG(COMMON_REG_BASE + in HwSpinLockTest()
2183 ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register); in PRCMCC3200MCUInit()2185 HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register) = ulRegVal; in PRCMCC3200MCUInit()2190 ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register); in PRCMCC3200MCUInit()2192 HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register) = ulRegVal; in PRCMCC3200MCUInit()
107 #define N2A_INT_MASK_SET (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_SET)109 #define N2A_INT_MASK_CLR (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_CLR)111 #define N2A_INT_ACK (COMMON_REG_BASE + COMMON_REG_O_NW_INT_ACK)115 #define A2N_INT_STS_CLR (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_CLR)117 #define A2N_INT_TRIG (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_TRIG)119 #define A2N_INT_STS_RAW (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_RAW)
59 #define COMMON_REG_BASE 0x400F7000 macro
166 ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register); in I2CCC32XX_initHw()
