1 /****************************************************************************** 2 * Filename: hw_ckmd_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_CKMD_H__ 34 #define __HW_CKMD_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // CKMD component 40 // 41 //***************************************************************************** 42 // Description Register. 43 #define CKMD_O_DESC 0x00000000U 44 45 // Interrupt mask. 46 #define CKMD_O_IMASK 0x00000044U 47 48 // Raw interrupt status. 49 #define CKMD_O_RIS 0x00000048U 50 51 // Masked interrupt status. 52 #define CKMD_O_MIS 0x0000004CU 53 54 // Interrupt set register. 55 #define CKMD_O_ISET 0x00000050U 56 57 // Interrupt clear register. 58 #define CKMD_O_ICLR 0x00000054U 59 60 // Interrupt mask set register. 61 #define CKMD_O_IMSET 0x00000058U 62 63 // Interrupt mask clear register. 64 #define CKMD_O_IMCLR 0x0000005CU 65 66 // Internal. Only to be used through TI provided API. 67 #define CKMD_O_HFOSCCTL 0x00000080U 68 69 // High frequency crystal control 70 #define CKMD_O_HFXTCTL 0x00000084U 71 72 // Low frequency oscillator control 73 #define CKMD_O_LFOSCCTL 0x0000008CU 74 75 // Low frequency crystal control 76 #define CKMD_O_LFXTCTL 0x00000090U 77 78 // Low frequency clock qualification control 79 #define CKMD_O_LFQUALCTL 0x00000094U 80 81 // Low frequency time increment control 82 #define CKMD_O_LFINCCTL 0x00000098U 83 84 // Low frequency time increment override control 85 #define CKMD_O_LFINCOVR 0x0000009CU 86 87 // Internal. Only to be used through TI provided API. 88 #define CKMD_O_AMPADCCTL 0x000000A0U 89 90 // High frequency tracking loop control 91 #define CKMD_O_HFTRACKCTL 0x000000A4U 92 93 // Internal. Only to be used through TI provided API. 94 #define CKMD_O_LDOCTL 0x000000A8U 95 96 // Nanoamp-bias control 97 #define CKMD_O_NABIASCTL 0x000000ACU 98 99 // Low-frequency clock-monitor control 100 #define CKMD_O_LFMONCTL 0x000000B0U 101 102 // Low frequency clock selection 103 #define CKMD_O_LFCLKSEL 0x000000C0U 104 105 // Internal. Only to be used through TI provided API. 106 #define CKMD_O_TDCCLKSEL 0x000000C4U 107 108 // ADC clock selection 109 #define CKMD_O_ADCCLKSEL 0x000000C8U 110 111 // Low-frequency clock status 112 #define CKMD_O_LFCLKSTAT 0x000000E0U 113 114 // HFXT status information 115 #define CKMD_O_HFXTSTAT 0x000000E4U 116 117 // Internal. Only to be used through TI provided API. 118 #define CKMD_O_AMPADCSTAT 0x000000E8U 119 120 // HFOSC tracking loop status information 121 #define CKMD_O_TRACKSTAT 0x000000ECU 122 123 // HFXT Amplitude Compensation Status 124 #define CKMD_O_AMPSTAT 0x000000F0U 125 126 // Internal. Only to be used through TI provided API. 127 #define CKMD_O_ATBCTL0 0x00000100U 128 129 // Internal. Only to be used through TI provided API. 130 #define CKMD_O_ATBCTL1 0x00000104U 131 132 // Digital test bus mux control 133 #define CKMD_O_DTBCTL 0x00000108U 134 135 // Internal. Only to be used through TI provided API. 136 #define CKMD_O_TRIM0 0x00000110U 137 138 // Internal. Only to be used through TI provided API. 139 #define CKMD_O_TRIM1 0x00000114U 140 141 // Initial values for HFXT ramping 142 #define CKMD_O_HFXTINIT 0x00000118U 143 144 // Target values for HFXT ramping 145 #define CKMD_O_HFXTTARG 0x0000011CU 146 147 // Alternative target values for HFXT configuration 148 #define CKMD_O_HFXTDYN 0x00000120U 149 150 // Amplitude Compensation Configuration 0 151 #define CKMD_O_AMPCFG0 0x00000124U 152 153 // Amplitude Compensation Configuration 1 154 #define CKMD_O_AMPCFG1 0x00000128U 155 156 // Configuration Register for the Tracking Loop 157 #define CKMD_O_LOOPCFG 0x0000012CU 158 159 // Internal. Only to be used through TI provided API. 160 #define CKMD_O_TDCCTL 0x00000200U 161 162 // Internal. Only to be used through TI provided API. 163 #define CKMD_O_TDCSTAT 0x00000204U 164 165 // Internal. Only to be used through TI provided API. 166 #define CKMD_O_TDCRESULT 0x00000208U 167 168 // Internal. Only to be used through TI provided API. 169 #define CKMD_O_TDCSATCFG 0x0000020CU 170 171 // Internal. Only to be used through TI provided API. 172 #define CKMD_O_TDCTRIGSRC 0x00000210U 173 174 // Internal. Only to be used through TI provided API. 175 #define CKMD_O_TDCTRIGCNT 0x00000214U 176 177 // Internal. Only to be used through TI provided API. 178 #define CKMD_O_TDCTRIGCNTLOAD 0x00000218U 179 180 // Internal. Only to be used through TI provided API. 181 #define CKMD_O_TDCTRIGCNTCFG 0x0000021CU 182 183 // Internal. Only to be used through TI provided API. 184 #define CKMD_O_TDCPRECTL 0x00000220U 185 186 // Internal. Only to be used through TI provided API. 187 #define CKMD_O_TDCPRECNTR 0x00000224U 188 189 // WDT counter value register 190 #define CKMD_O_WDTCNT 0x00000300U 191 192 // WDT test mode register 193 #define CKMD_O_WDTTEST 0x00000304U 194 195 // WDT lock register 196 #define CKMD_O_WDTLOCK 0x00000308U 197 198 //***************************************************************************** 199 // 200 // Register: CKMD_O_DESC 201 // 202 //***************************************************************************** 203 // Field: [31:16] MODID 204 // 205 // Module identifier used to uniquely identify this IP. 206 #define CKMD_DESC_MODID_W 16U 207 #define CKMD_DESC_MODID_M 0xFFFF0000U 208 #define CKMD_DESC_MODID_S 16U 209 210 // Field: [15:12] STDIPOFF 211 // 212 // Standard IP MMR block offset. Standard IP MMRs are the set of from 213 // aggregated IRQ registers till DTB. 214 // 0: Standard IP MMRs do not exist 215 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 216 // address) 217 // 218 // NOTE: This IP does not have DTB as part of the Standard IP MMRs. It uses 219 // DTBCTL instead. 220 #define CKMD_DESC_STDIPOFF_W 4U 221 #define CKMD_DESC_STDIPOFF_M 0x0000F000U 222 #define CKMD_DESC_STDIPOFF_S 12U 223 224 // Field: [7:4] MAJREV 225 // 226 // Major revision of IP (0-15). 227 #define CKMD_DESC_MAJREV_W 4U 228 #define CKMD_DESC_MAJREV_M 0x000000F0U 229 #define CKMD_DESC_MAJREV_S 4U 230 231 // Field: [3:0] MINREV 232 // 233 // Minor revision of IP (0-15). 234 #define CKMD_DESC_MINREV_W 4U 235 #define CKMD_DESC_MINREV_M 0x0000000FU 236 #define CKMD_DESC_MINREV_S 0U 237 238 //***************************************************************************** 239 // 240 // Register: CKMD_O_IMASK 241 // 242 //***************************************************************************** 243 // Field: [17] LFTICK 244 // 245 // 32kHz TICK to RTC and WDT. 246 // 247 // Either derived from selected LFCLK or generated from CLKULL in absence of 248 // LFCLK. 249 #define CKMD_IMASK_LFTICK 0x00020000U 250 #define CKMD_IMASK_LFTICK_M 0x00020000U 251 #define CKMD_IMASK_LFTICK_S 17U 252 253 // Field: [16] LFGEARRSTRT 254 // 255 // LFINC filter gearing restart. 256 // 257 // Indicates that the LFINC filter restarted gearing. Subsequent LFINC 258 // estimates may have higher variation. 259 #define CKMD_IMASK_LFGEARRSTRT 0x00010000U 260 #define CKMD_IMASK_LFGEARRSTRT_M 0x00010000U 261 #define CKMD_IMASK_LFGEARRSTRT_S 16U 262 263 // Field: [15] AMPSETTLED 264 // 265 // HFXT Amplitude compensation - settled 266 // 267 // Indicates that the amplitude compensation FSM has reached the SETTLED or 268 // TCXOMODE state, 269 // and the controls configured in HFXTTARG or HFXTDYN are reached. 270 #define CKMD_IMASK_AMPSETTLED 0x00008000U 271 #define CKMD_IMASK_AMPSETTLED_M 0x00008000U 272 #define CKMD_IMASK_AMPSETTLED_S 15U 273 274 // Field: [14] AMPCTRLATTARG 275 // 276 // HFXT Amplitude compensation - controls at target 277 // 278 // Indicates that the control values configured in HFXTTARG or HFXTDYN are 279 // reached. 280 // Applies to Q1CAP, Q2CAP and IREF. 281 #define CKMD_IMASK_AMPCTRLATTARG 0x00004000U 282 #define CKMD_IMASK_AMPCTRLATTARG_M 0x00004000U 283 #define CKMD_IMASK_AMPCTRLATTARG_S 14U 284 285 // Field: [13] PRELFEDGE 286 // 287 // Pre-LF clock edge detect. 288 // 289 // Indicates that a positive edge occured on the selected pre-LF clock 290 // LFCLKSEL.PRE. 291 // Can be used by software to confirm that a LF clock source is running and 292 // within the expected frequency, 293 // before selecting it as the main LF clock source. 294 #define CKMD_IMASK_PRELFEDGE 0x00002000U 295 #define CKMD_IMASK_PRELFEDGE_M 0x00002000U 296 #define CKMD_IMASK_PRELFEDGE_S 13U 297 298 // Field: [12] LFCLKLOSS 299 // 300 // LF clock is lost. 301 // 302 // Indicates that no LF clock edge occured for ~49us (~1.6 times nominal 303 // period). 304 // The system will automatically fall-back to generating LFTICK based on 305 // CLKULL, 306 // to avoid timing corruption. 307 // Note that this signal is NOT related to the analog LF clock-loss detector 308 // which can reset the device during STANDBY. 309 #define CKMD_IMASK_LFCLKLOSS 0x00001000U 310 #define CKMD_IMASK_LFCLKLOSS_M 0x00001000U 311 #define CKMD_IMASK_LFCLKLOSS_S 12U 312 313 // Field: [11] LFCLKOOR 314 // 315 // LF clock period out-of-range. 316 // 317 // Indicates that a LF clock period was measured to be out-of-range, 318 // according to LFQUALCTL.MAXERR. 319 #define CKMD_IMASK_LFCLKOOR 0x00000800U 320 #define CKMD_IMASK_LFCLKOOR_M 0x00000800U 321 #define CKMD_IMASK_LFCLKOOR_S 11U 322 323 // Field: [10] LFCLKGOOD 324 // 325 // LF clock good. 326 // 327 // Indicates that the LF clock is good, according to the configuration in 328 // LFQUALCTL. 329 #define CKMD_IMASK_LFCLKGOOD 0x00000400U 330 #define CKMD_IMASK_LFCLKGOOD_M 0x00000400U 331 #define CKMD_IMASK_LFCLKGOOD_S 10U 332 333 // Field: [9] LFINCUPD 334 // 335 // LFINC updated. 336 // 337 // Indicates that a new LFINC measurement value is available in 338 // LFCLKSTAT.LFINC. 339 #define CKMD_IMASK_LFINCUPD 0x00000200U 340 #define CKMD_IMASK_LFINCUPD_M 0x00000200U 341 #define CKMD_IMASK_LFINCUPD_S 9U 342 343 // Field: [8] TDCDONE 344 // 345 // TDC done event. 346 // 347 // Indicates that the TDC measurement is done. 348 #define CKMD_IMASK_TDCDONE 0x00000100U 349 #define CKMD_IMASK_TDCDONE_M 0x00000100U 350 #define CKMD_IMASK_TDCDONE_S 8U 351 352 // Field: [7] ADCPEAKUPD 353 // 354 // HFXT-ADC PEAK measurement update event. 355 // 356 // Indicates that the HFXT-ADC PEAK measurement is done. 357 #define CKMD_IMASK_ADCPEAKUPD 0x00000080U 358 #define CKMD_IMASK_ADCPEAKUPD_M 0x00000080U 359 #define CKMD_IMASK_ADCPEAKUPD_S 7U 360 361 // Field: [6] ADCBIASUPD 362 // 363 // HFXT-ADC BIAS measurement update event. 364 // 365 // Indicates that the HFXT-ADC BIAS measurement is done. 366 #define CKMD_IMASK_ADCBIASUPD 0x00000040U 367 #define CKMD_IMASK_ADCBIASUPD_M 0x00000040U 368 #define CKMD_IMASK_ADCBIASUPD_S 6U 369 370 // Field: [5] ADCCOMPUPD 371 // 372 // HFXT-ADC comparison update event. 373 // 374 // Indicates that the HFXT-ADC comparison is done. 375 #define CKMD_IMASK_ADCCOMPUPD 0x00000020U 376 #define CKMD_IMASK_ADCCOMPUPD_M 0x00000020U 377 #define CKMD_IMASK_ADCCOMPUPD_S 5U 378 379 // Field: [4] TRACKREFOOR 380 // 381 // Out-of-range indication from the tracking loop. 382 // 383 // Indicates that the selected reference clock frequency of the tracking loop 384 // is out-of-range. 385 #define CKMD_IMASK_TRACKREFOOR 0x00000010U 386 #define CKMD_IMASK_TRACKREFOOR_M 0x00000010U 387 #define CKMD_IMASK_TRACKREFOOR_S 4U 388 389 // Field: [3] TRACKREFLOSS 390 // 391 // Clock loss indication from the tracking loop. 392 // 393 // Indicates that the selected reference clock of the tracking loop is lost. 394 #define CKMD_IMASK_TRACKREFLOSS 0x00000008U 395 #define CKMD_IMASK_TRACKREFLOSS_M 0x00000008U 396 #define CKMD_IMASK_TRACKREFLOSS_S 3U 397 398 // Field: [2] HFXTAMPGOOD 399 // 400 // HFXT amplitude good indication. 401 #define CKMD_IMASK_HFXTAMPGOOD 0x00000004U 402 #define CKMD_IMASK_HFXTAMPGOOD_M 0x00000004U 403 #define CKMD_IMASK_HFXTAMPGOOD_S 2U 404 405 // Field: [1] HFXTFAULT 406 // 407 // HFXT fault indication. 408 // 409 // Indicates that HFXT did not start correctly, or its frequency is too low. 410 // HFXT will not recover from this fault and has to be restarted. 411 // This is only a one-time check at HFXT startup. 412 #define CKMD_IMASK_HFXTFAULT 0x00000002U 413 #define CKMD_IMASK_HFXTFAULT_M 0x00000002U 414 #define CKMD_IMASK_HFXTFAULT_S 1U 415 416 // Field: [0] HFXTGOOD 417 // 418 // HFXT good indication. 419 // 420 // Indicates that HFXT started correctly. The frequency is not necessarily good 421 // enough for radio operation. 422 // This is only a one-time check at HFXT startup. 423 #define CKMD_IMASK_HFXTGOOD 0x00000001U 424 #define CKMD_IMASK_HFXTGOOD_M 0x00000001U 425 #define CKMD_IMASK_HFXTGOOD_S 0U 426 427 //***************************************************************************** 428 // 429 // Register: CKMD_O_RIS 430 // 431 //***************************************************************************** 432 // Field: [17] LFTICK 433 // 434 // 32kHz TICK to RTC and WDT. 435 // 436 // Either derived from selected LFCLK or generated from CLKULL in absence of 437 // LFCLK. 438 #define CKMD_RIS_LFTICK 0x00020000U 439 #define CKMD_RIS_LFTICK_M 0x00020000U 440 #define CKMD_RIS_LFTICK_S 17U 441 442 // Field: [16] LFGEARRSTRT 443 // 444 // LFINC filter gearing restart. 445 // 446 // Indicates that the LFINC filter restarted gearing. Subsequent LFINC 447 // estimates may have higher variation. 448 #define CKMD_RIS_LFGEARRSTRT 0x00010000U 449 #define CKMD_RIS_LFGEARRSTRT_M 0x00010000U 450 #define CKMD_RIS_LFGEARRSTRT_S 16U 451 452 // Field: [15] AMPSETTLED 453 // 454 // HFXT Amplitude compensation - settled 455 // 456 // Indicates that the amplitude compensation FSM has reached the SETTLED or 457 // TCXOMODE state, 458 // and the controls configured in HFXTTARG or HFXTDYN are reached. 459 #define CKMD_RIS_AMPSETTLED 0x00008000U 460 #define CKMD_RIS_AMPSETTLED_M 0x00008000U 461 #define CKMD_RIS_AMPSETTLED_S 15U 462 463 // Field: [14] AMPCTRLATTARG 464 // 465 // HFXT Amplitude compensation - controls at target 466 // 467 // Indicates that the control values configured in HFXTTARG or HFXTDYN are 468 // reached. 469 // Applies to Q1CAP, Q2CAP and IREF. 470 #define CKMD_RIS_AMPCTRLATTARG 0x00004000U 471 #define CKMD_RIS_AMPCTRLATTARG_M 0x00004000U 472 #define CKMD_RIS_AMPCTRLATTARG_S 14U 473 474 // Field: [13] PRELFEDGE 475 // 476 // Pre-LF clock edge detect. 477 // 478 // Indicates that a positive edge occured on the selected pre-LF clock 479 // LFCLKSEL.PRE. 480 // Can be used by software to confirm that a LF clock source is running and 481 // within the expected frequency, 482 // before selecting it as the main LF clock source. 483 #define CKMD_RIS_PRELFEDGE 0x00002000U 484 #define CKMD_RIS_PRELFEDGE_M 0x00002000U 485 #define CKMD_RIS_PRELFEDGE_S 13U 486 487 // Field: [12] LFCLKLOSS 488 // 489 // LF clock is lost. 490 // 491 // Indicates that no LF clock edge occured for ~49us (~1.6 times nominal 492 // period). 493 // The system will automatically fall-back to generating LFTICK based on 494 // CLKULL, 495 // to avoid timing corruption. 496 // Note that this signal is NOT related to the analog LF clock-loss detector 497 // which can reset the device during STANDBY. 498 #define CKMD_RIS_LFCLKLOSS 0x00001000U 499 #define CKMD_RIS_LFCLKLOSS_M 0x00001000U 500 #define CKMD_RIS_LFCLKLOSS_S 12U 501 502 // Field: [11] LFCLKOOR 503 // 504 // LF clock period out-of-range. 505 // 506 // Indicates that a LF clock period was measured to be out-of-range, 507 // according to LFQUALCTL.MAXERR. 508 #define CKMD_RIS_LFCLKOOR 0x00000800U 509 #define CKMD_RIS_LFCLKOOR_M 0x00000800U 510 #define CKMD_RIS_LFCLKOOR_S 11U 511 512 // Field: [10] LFCLKGOOD 513 // 514 // LF clock good. 515 // 516 // Indicates that the LF clock is good, according to the configuration in 517 // LFQUALCTL. 518 #define CKMD_RIS_LFCLKGOOD 0x00000400U 519 #define CKMD_RIS_LFCLKGOOD_M 0x00000400U 520 #define CKMD_RIS_LFCLKGOOD_S 10U 521 522 // Field: [9] LFINCUPD 523 // 524 // LFINC updated. 525 // 526 // Indicates that a new LFINC measurement value is available in 527 // LFCLKSTAT.LFINC. 528 #define CKMD_RIS_LFINCUPD 0x00000200U 529 #define CKMD_RIS_LFINCUPD_M 0x00000200U 530 #define CKMD_RIS_LFINCUPD_S 9U 531 532 // Field: [8] TDCDONE 533 // 534 // TDC done event. 535 // 536 // Indicates that the TDC measurement is done. 537 #define CKMD_RIS_TDCDONE 0x00000100U 538 #define CKMD_RIS_TDCDONE_M 0x00000100U 539 #define CKMD_RIS_TDCDONE_S 8U 540 541 // Field: [7] ADCPEAKUPD 542 // 543 // HFXT-ADC PEAK measurement update event. 544 // 545 // Indicates that the HFXT-ADC PEAK measurement is done. 546 #define CKMD_RIS_ADCPEAKUPD 0x00000080U 547 #define CKMD_RIS_ADCPEAKUPD_M 0x00000080U 548 #define CKMD_RIS_ADCPEAKUPD_S 7U 549 550 // Field: [6] ADCBIASUPD 551 // 552 // HFXT-ADC BIAS measurement update event. 553 // 554 // Indicates that the HFXT-ADC BIAS measurement is done. 555 #define CKMD_RIS_ADCBIASUPD 0x00000040U 556 #define CKMD_RIS_ADCBIASUPD_M 0x00000040U 557 #define CKMD_RIS_ADCBIASUPD_S 6U 558 559 // Field: [5] ADCCOMPUPD 560 // 561 // HFXT-ADC comparison update event. 562 // 563 // Indicates that the HFXT-ADC comparison is done. 564 #define CKMD_RIS_ADCCOMPUPD 0x00000020U 565 #define CKMD_RIS_ADCCOMPUPD_M 0x00000020U 566 #define CKMD_RIS_ADCCOMPUPD_S 5U 567 568 // Field: [4] TRACKREFOOR 569 // 570 // Out-of-range indication from the tracking loop. 571 // 572 // Indicates that the selected reference clock frequency of the tracking loop 573 // is out-of-range. 574 #define CKMD_RIS_TRACKREFOOR 0x00000010U 575 #define CKMD_RIS_TRACKREFOOR_M 0x00000010U 576 #define CKMD_RIS_TRACKREFOOR_S 4U 577 578 // Field: [3] TRACKREFLOSS 579 // 580 // Clock loss indication from the tracking loop. 581 // 582 // Indicates that the selected reference clock of the tracking loop is lost. 583 #define CKMD_RIS_TRACKREFLOSS 0x00000008U 584 #define CKMD_RIS_TRACKREFLOSS_M 0x00000008U 585 #define CKMD_RIS_TRACKREFLOSS_S 3U 586 587 // Field: [2] HFXTAMPGOOD 588 // 589 // HFXT amplitude good indication. 590 #define CKMD_RIS_HFXTAMPGOOD 0x00000004U 591 #define CKMD_RIS_HFXTAMPGOOD_M 0x00000004U 592 #define CKMD_RIS_HFXTAMPGOOD_S 2U 593 594 // Field: [1] HFXTFAULT 595 // 596 // HFXT fault indication. 597 // 598 // Indicates that HFXT did not start correctly, or its frequency is too low. 599 // HFXT will not recover from this fault and has to be restarted. 600 // This is only a one-time check at HFXT startup. 601 #define CKMD_RIS_HFXTFAULT 0x00000002U 602 #define CKMD_RIS_HFXTFAULT_M 0x00000002U 603 #define CKMD_RIS_HFXTFAULT_S 1U 604 605 // Field: [0] HFXTGOOD 606 // 607 // HFXT good indication. 608 // 609 // Indicates that HFXT started correctly. The frequency is not necessarily good 610 // enough for radio operation. 611 // This is only a one-time check at HFXT startup. 612 #define CKMD_RIS_HFXTGOOD 0x00000001U 613 #define CKMD_RIS_HFXTGOOD_M 0x00000001U 614 #define CKMD_RIS_HFXTGOOD_S 0U 615 616 //***************************************************************************** 617 // 618 // Register: CKMD_O_MIS 619 // 620 //***************************************************************************** 621 // Field: [17] LFTICK 622 // 623 // 32kHz TICK to RTC and WDT. 624 // 625 // Either derived from selected LFCLK or generated from CLKULL in absence of 626 // LFCLK. 627 #define CKMD_MIS_LFTICK 0x00020000U 628 #define CKMD_MIS_LFTICK_M 0x00020000U 629 #define CKMD_MIS_LFTICK_S 17U 630 631 // Field: [16] LFGEARRSTRT 632 // 633 // LFINC filter gearing restart. 634 // 635 // Indicates that the LFINC filter restarted gearing. Subsequent LFINC 636 // estimates may have higher variation. 637 #define CKMD_MIS_LFGEARRSTRT 0x00010000U 638 #define CKMD_MIS_LFGEARRSTRT_M 0x00010000U 639 #define CKMD_MIS_LFGEARRSTRT_S 16U 640 641 // Field: [15] AMPSETTLED 642 // 643 // HFXT Amplitude compensation - settled 644 // 645 // Indicates that the amplitude compensation FSM has reached the SETTLED or 646 // TCXOMODE state, 647 // and the controls configured in HFXTTARG or HFXTDYN are reached. 648 #define CKMD_MIS_AMPSETTLED 0x00008000U 649 #define CKMD_MIS_AMPSETTLED_M 0x00008000U 650 #define CKMD_MIS_AMPSETTLED_S 15U 651 652 // Field: [14] AMPCTRLATTARG 653 // 654 // HFXT Amplitude compensation - controls at target 655 // 656 // Indicates that the control values configured in HFXTTARG or HFXTDYN are 657 // reached. 658 // Applies to Q1CAP, Q2CAP and IREF. 659 #define CKMD_MIS_AMPCTRLATTARG 0x00004000U 660 #define CKMD_MIS_AMPCTRLATTARG_M 0x00004000U 661 #define CKMD_MIS_AMPCTRLATTARG_S 14U 662 663 // Field: [13] PRELFEDGE 664 // 665 // Pre-LF clock edge detect. 666 // 667 // Indicates that a positive edge occured on the selected pre-LF clock 668 // LFCLKSEL.PRE. 669 // Can be used by software to confirm that a LF clock source is running and 670 // within the expected frequency, 671 // before selecting it as the main LF clock source. 672 #define CKMD_MIS_PRELFEDGE 0x00002000U 673 #define CKMD_MIS_PRELFEDGE_M 0x00002000U 674 #define CKMD_MIS_PRELFEDGE_S 13U 675 676 // Field: [12] LFCLKLOSS 677 // 678 // LF clock is lost. 679 // 680 // Indicates that no LF clock edge occured for ~49us (~1.6 times nominal 681 // period). 682 // The system will automatically fall-back to generating LFTICK based on 683 // CLKULL, 684 // to avoid timing corruption. 685 // Note that this signal is NOT related to the analog LF clock-loss detector 686 // which can reset the device during STANDBY. 687 #define CKMD_MIS_LFCLKLOSS 0x00001000U 688 #define CKMD_MIS_LFCLKLOSS_M 0x00001000U 689 #define CKMD_MIS_LFCLKLOSS_S 12U 690 691 // Field: [11] LFCLKOOR 692 // 693 // LF clock period out-of-range. 694 // 695 // Indicates that a LF clock period was measured to be out-of-range, 696 // according to LFQUALCTL.MAXERR. 697 #define CKMD_MIS_LFCLKOOR 0x00000800U 698 #define CKMD_MIS_LFCLKOOR_M 0x00000800U 699 #define CKMD_MIS_LFCLKOOR_S 11U 700 701 // Field: [10] LFCLKGOOD 702 // 703 // LF clock good. 704 // 705 // Indicates that the LF clock is good, according to the configuration in 706 // LFQUALCTL. 707 #define CKMD_MIS_LFCLKGOOD 0x00000400U 708 #define CKMD_MIS_LFCLKGOOD_M 0x00000400U 709 #define CKMD_MIS_LFCLKGOOD_S 10U 710 711 // Field: [9] LFINCUPD 712 // 713 // LFINC updated. 714 // 715 // Indicates that a new LFINC measurement value is available in 716 // LFCLKSTAT.LFINC. 717 #define CKMD_MIS_LFINCUPD 0x00000200U 718 #define CKMD_MIS_LFINCUPD_M 0x00000200U 719 #define CKMD_MIS_LFINCUPD_S 9U 720 721 // Field: [8] TDCDONE 722 // 723 // TDC done event. 724 // 725 // Indicates that the TDC measurement is done. 726 #define CKMD_MIS_TDCDONE 0x00000100U 727 #define CKMD_MIS_TDCDONE_M 0x00000100U 728 #define CKMD_MIS_TDCDONE_S 8U 729 730 // Field: [7] ADCPEAKUPD 731 // 732 // HFXT-ADC PEAK measurement update event. 733 // 734 // Indicates that the HFXT-ADC PEAK measurement is done. 735 #define CKMD_MIS_ADCPEAKUPD 0x00000080U 736 #define CKMD_MIS_ADCPEAKUPD_M 0x00000080U 737 #define CKMD_MIS_ADCPEAKUPD_S 7U 738 739 // Field: [6] ADCBIASUPD 740 // 741 // HFXT-ADC BIAS measurement update event. 742 // 743 // Indicates that the HFXT-ADC BIAS measurement is done. 744 #define CKMD_MIS_ADCBIASUPD 0x00000040U 745 #define CKMD_MIS_ADCBIASUPD_M 0x00000040U 746 #define CKMD_MIS_ADCBIASUPD_S 6U 747 748 // Field: [5] ADCCOMPUPD 749 // 750 // HFXT-ADC comparison update event. 751 // 752 // Indicates that the HFXT-ADC comparison is done. 753 #define CKMD_MIS_ADCCOMPUPD 0x00000020U 754 #define CKMD_MIS_ADCCOMPUPD_M 0x00000020U 755 #define CKMD_MIS_ADCCOMPUPD_S 5U 756 757 // Field: [4] TRACKREFOOR 758 // 759 // Out-of-range indication from the tracking loop. 760 // 761 // Indicates that the selected reference clock frequency of the tracking loop 762 // is out-of-range. 763 #define CKMD_MIS_TRACKREFOOR 0x00000010U 764 #define CKMD_MIS_TRACKREFOOR_M 0x00000010U 765 #define CKMD_MIS_TRACKREFOOR_S 4U 766 767 // Field: [3] TRACKREFLOSS 768 // 769 // Clock loss indication from the tracking loop. 770 // 771 // Indicates that the selected reference clock of the tracking loop is lost. 772 #define CKMD_MIS_TRACKREFLOSS 0x00000008U 773 #define CKMD_MIS_TRACKREFLOSS_M 0x00000008U 774 #define CKMD_MIS_TRACKREFLOSS_S 3U 775 776 // Field: [2] HFXTAMPGOOD 777 // 778 // HFXT amplitude good indication. 779 #define CKMD_MIS_HFXTAMPGOOD 0x00000004U 780 #define CKMD_MIS_HFXTAMPGOOD_M 0x00000004U 781 #define CKMD_MIS_HFXTAMPGOOD_S 2U 782 783 // Field: [1] HFXTFAULT 784 // 785 // HFXT fault indication. 786 // 787 // Indicates that HFXT did not start correctly, or its frequency is too low. 788 // HFXT will not recover from this fault and has to be restarted. 789 // This is only a one-time check at HFXT startup. 790 #define CKMD_MIS_HFXTFAULT 0x00000002U 791 #define CKMD_MIS_HFXTFAULT_M 0x00000002U 792 #define CKMD_MIS_HFXTFAULT_S 1U 793 794 // Field: [0] HFXTGOOD 795 // 796 // HFXT good indication. 797 // 798 // Indicates that HFXT started correctly. The frequency is not necessarily good 799 // enough for radio operation. 800 // This is only a one-time check at HFXT startup. 801 #define CKMD_MIS_HFXTGOOD 0x00000001U 802 #define CKMD_MIS_HFXTGOOD_M 0x00000001U 803 #define CKMD_MIS_HFXTGOOD_S 0U 804 805 //***************************************************************************** 806 // 807 // Register: CKMD_O_ISET 808 // 809 //***************************************************************************** 810 // Field: [17] LFTICK 811 // 812 // 32kHz TICK to RTC and WDT. 813 // 814 // Either derived from selected LFCLK or generated from CLKULL in absence of 815 // LFCLK. 816 #define CKMD_ISET_LFTICK 0x00020000U 817 #define CKMD_ISET_LFTICK_M 0x00020000U 818 #define CKMD_ISET_LFTICK_S 17U 819 820 // Field: [16] LFGEARRSTRT 821 // 822 // LFINC filter gearing restart. 823 // 824 // Indicates that the LFINC filter restarted gearing. Subsequent LFINC 825 // estimates may have higher variation. 826 #define CKMD_ISET_LFGEARRSTRT 0x00010000U 827 #define CKMD_ISET_LFGEARRSTRT_M 0x00010000U 828 #define CKMD_ISET_LFGEARRSTRT_S 16U 829 830 // Field: [15] AMPSETTLED 831 // 832 // HFXT Amplitude compensation - settled 833 // 834 // Indicates that the amplitude compensation FSM has reached the SETTLED or 835 // TCXOMODE state, 836 // and the controls configured in HFXTTARG or HFXTDYN are reached. 837 #define CKMD_ISET_AMPSETTLED 0x00008000U 838 #define CKMD_ISET_AMPSETTLED_M 0x00008000U 839 #define CKMD_ISET_AMPSETTLED_S 15U 840 841 // Field: [14] AMPCTRLATTARG 842 // 843 // HFXT Amplitude compensation - controls at target 844 // 845 // Indicates that the control values configured in HFXTTARG.Q1CAP, 846 // HFXTTARG.Q2CAP and HFXTTARG.IREF or HFXTDYN.Q1CAP, HFXTDYN.Q2CAP and 847 // HFXTDYN.IREF are reached. 848 #define CKMD_ISET_AMPCTRLATTARG 0x00004000U 849 #define CKMD_ISET_AMPCTRLATTARG_M 0x00004000U 850 #define CKMD_ISET_AMPCTRLATTARG_S 14U 851 852 // Field: [13] PRELFEDGE 853 // 854 // Pre-LF clock edge detect. 855 // 856 // Indicates that a positive edge occured on the selected pre-LF clock 857 // LFCLKSEL.PRE. 858 // Can be used by software to confirm that a LF clock source is running and 859 // within the expected frequency, 860 // before selecting it as the main LF clock source. 861 #define CKMD_ISET_PRELFEDGE 0x00002000U 862 #define CKMD_ISET_PRELFEDGE_M 0x00002000U 863 #define CKMD_ISET_PRELFEDGE_S 13U 864 865 // Field: [12] LFCLKLOSS 866 // 867 // LF clock is lost. 868 // 869 // Indicates that no LF clock edge occured for ~49us (~1.6 times nominal 870 // period). 871 // The system will automatically fall-back to generating LFTICK based on 872 // CLKULL, 873 // to avoid timing corruption. 874 // Note that this signal is NOT related to the analog LF clock-loss detector 875 // which can reset the device during STANDBY. 876 #define CKMD_ISET_LFCLKLOSS 0x00001000U 877 #define CKMD_ISET_LFCLKLOSS_M 0x00001000U 878 #define CKMD_ISET_LFCLKLOSS_S 12U 879 880 // Field: [11] LFCLKOOR 881 // 882 // LF clock period out-of-range. 883 // 884 // Indicates that a LF clock period was measured to be out-of-range, 885 // according to LFQUALCTL.MAXERR. 886 #define CKMD_ISET_LFCLKOOR 0x00000800U 887 #define CKMD_ISET_LFCLKOOR_M 0x00000800U 888 #define CKMD_ISET_LFCLKOOR_S 11U 889 890 // Field: [10] LFCLKGOOD 891 // 892 // LF clock good. 893 // 894 // Indicates that the LF clock is good, according to the configuration in 895 // LFQUALCTL. 896 #define CKMD_ISET_LFCLKGOOD 0x00000400U 897 #define CKMD_ISET_LFCLKGOOD_M 0x00000400U 898 #define CKMD_ISET_LFCLKGOOD_S 10U 899 900 // Field: [9] LFINCUPD 901 // 902 // LFINC updated. 903 // 904 // Indicates that a new LFINC measurement value is available in 905 // LFCLKSTAT.LFINC. 906 #define CKMD_ISET_LFINCUPD 0x00000200U 907 #define CKMD_ISET_LFINCUPD_M 0x00000200U 908 #define CKMD_ISET_LFINCUPD_S 9U 909 910 // Field: [8] TDCDONE 911 // 912 // TDC done event. 913 // 914 // Indicates that the TDC measurement is done. 915 #define CKMD_ISET_TDCDONE 0x00000100U 916 #define CKMD_ISET_TDCDONE_M 0x00000100U 917 #define CKMD_ISET_TDCDONE_S 8U 918 919 // Field: [7] ADCPEAKUPD 920 // 921 // HFXT-ADC PEAK measurement update event. 922 // 923 // Indicates that the HFXT-ADC PEAK measurement is done. 924 #define CKMD_ISET_ADCPEAKUPD 0x00000080U 925 #define CKMD_ISET_ADCPEAKUPD_M 0x00000080U 926 #define CKMD_ISET_ADCPEAKUPD_S 7U 927 928 // Field: [6] ADCBIASUPD 929 // 930 // HFXT-ADC BIAS measurement update event. 931 // 932 // Indicates that the HFXT-ADC BIAS measurement is done. 933 #define CKMD_ISET_ADCBIASUPD 0x00000040U 934 #define CKMD_ISET_ADCBIASUPD_M 0x00000040U 935 #define CKMD_ISET_ADCBIASUPD_S 6U 936 937 // Field: [5] ADCCOMPUPD 938 // 939 // HFXT-ADC comparison update event. 940 // 941 // Indicates that the HFXT-ADC comparison is done. 942 #define CKMD_ISET_ADCCOMPUPD 0x00000020U 943 #define CKMD_ISET_ADCCOMPUPD_M 0x00000020U 944 #define CKMD_ISET_ADCCOMPUPD_S 5U 945 946 // Field: [4] TRACKREFOOR 947 // 948 // Out-of-range indication from the tracking loop. 949 // 950 // Indicates that the selected reference clock frequency of the tracking loop 951 // is out-of-range. 952 #define CKMD_ISET_TRACKREFOOR 0x00000010U 953 #define CKMD_ISET_TRACKREFOOR_M 0x00000010U 954 #define CKMD_ISET_TRACKREFOOR_S 4U 955 956 // Field: [3] TRACKREFLOSS 957 // 958 // Clock loss indication from the tracking loop. 959 // 960 // Indicates that the selected reference clock of the tracking loop is lost. 961 #define CKMD_ISET_TRACKREFLOSS 0x00000008U 962 #define CKMD_ISET_TRACKREFLOSS_M 0x00000008U 963 #define CKMD_ISET_TRACKREFLOSS_S 3U 964 965 // Field: [2] HFXTAMPGOOD 966 // 967 // HFXT amplitude good indication. 968 #define CKMD_ISET_HFXTAMPGOOD 0x00000004U 969 #define CKMD_ISET_HFXTAMPGOOD_M 0x00000004U 970 #define CKMD_ISET_HFXTAMPGOOD_S 2U 971 972 // Field: [1] HFXTFAULT 973 // 974 // HFXT fault indication. 975 // 976 // Indicates that HFXT did not start correctly, or its frequency is too low. 977 // HFXT will not recover from this fault and has to be restarted. 978 // This is only a one-time check at HFXT startup. 979 #define CKMD_ISET_HFXTFAULT 0x00000002U 980 #define CKMD_ISET_HFXTFAULT_M 0x00000002U 981 #define CKMD_ISET_HFXTFAULT_S 1U 982 983 // Field: [0] HFXTGOOD 984 // 985 // HFXT good indication. 986 // 987 // Indicates that HFXT started correctly. The frequency is not necessarily good 988 // enough for radio operation. 989 // This is only a one-time check at HFXT startup. 990 #define CKMD_ISET_HFXTGOOD 0x00000001U 991 #define CKMD_ISET_HFXTGOOD_M 0x00000001U 992 #define CKMD_ISET_HFXTGOOD_S 0U 993 994 //***************************************************************************** 995 // 996 // Register: CKMD_O_ICLR 997 // 998 //***************************************************************************** 999 // Field: [17] LFTICK 1000 // 1001 // 32kHz TICK to RTC and WDT. 1002 // 1003 // Either derived from selected LFCLK or generated from CLKULL in absence of 1004 // LFCLK. 1005 #define CKMD_ICLR_LFTICK 0x00020000U 1006 #define CKMD_ICLR_LFTICK_M 0x00020000U 1007 #define CKMD_ICLR_LFTICK_S 17U 1008 1009 // Field: [16] LFGEARRSTRT 1010 // 1011 // LFINC filter gearing restart. 1012 // 1013 // Indicates that the LFINC filter restarted gearing. Subsequent LFINC 1014 // estimates may have higher variation. 1015 #define CKMD_ICLR_LFGEARRSTRT 0x00010000U 1016 #define CKMD_ICLR_LFGEARRSTRT_M 0x00010000U 1017 #define CKMD_ICLR_LFGEARRSTRT_S 16U 1018 1019 // Field: [15] AMPSETTLED 1020 // 1021 // HFXT Amplitude compensation - settled 1022 // 1023 // Indicates that the amplitude compensation FSM has reached the SETTLED or 1024 // TCXOMODE state, 1025 // and the controls configured in HFXTTARG or HFXTDYN are reached. 1026 #define CKMD_ICLR_AMPSETTLED 0x00008000U 1027 #define CKMD_ICLR_AMPSETTLED_M 0x00008000U 1028 #define CKMD_ICLR_AMPSETTLED_S 15U 1029 1030 // Field: [14] AMPCTRLATTARG 1031 // 1032 // HFXT Amplitude compensation - controls at target 1033 // 1034 // Indicates that the control values configured in HFXTTARG or HFXTDYN are 1035 // reached. 1036 // Applies to Q1CAP, Q2CAP and IREF. 1037 #define CKMD_ICLR_AMPCTRLATTARG 0x00004000U 1038 #define CKMD_ICLR_AMPCTRLATTARG_M 0x00004000U 1039 #define CKMD_ICLR_AMPCTRLATTARG_S 14U 1040 1041 // Field: [13] PRELFEDGE 1042 // 1043 // Pre-LF clock edge detect. 1044 // 1045 // Indicates that a positive edge occured on the selected pre-LF clock 1046 // LFCLKSEL.PRE. 1047 // Can be used by software to confirm that a LF clock source is running and 1048 // within the expected frequency, 1049 // before selecting it as the main LF clock source. 1050 #define CKMD_ICLR_PRELFEDGE 0x00002000U 1051 #define CKMD_ICLR_PRELFEDGE_M 0x00002000U 1052 #define CKMD_ICLR_PRELFEDGE_S 13U 1053 1054 // Field: [12] LFCLKLOSS 1055 // 1056 // LF clock is lost. 1057 // 1058 // Indicates that no LF clock edge occured for ~49us (~1.6 times nominal 1059 // period). 1060 // The system will automatically fall-back to generating LFTICK based on 1061 // CLKULL, 1062 // to avoid timing corruption. 1063 // Note that this signal is NOT related to the analog LF clock-loss detector 1064 // which can reset the device during STANDBY. 1065 #define CKMD_ICLR_LFCLKLOSS 0x00001000U 1066 #define CKMD_ICLR_LFCLKLOSS_M 0x00001000U 1067 #define CKMD_ICLR_LFCLKLOSS_S 12U 1068 1069 // Field: [11] LFCLKOOR 1070 // 1071 // LF clock period out-of-range. 1072 // 1073 // Indicates that a LF clock period was measured to be out-of-range, 1074 // according to LFQUALCTL.MAXERR. 1075 #define CKMD_ICLR_LFCLKOOR 0x00000800U 1076 #define CKMD_ICLR_LFCLKOOR_M 0x00000800U 1077 #define CKMD_ICLR_LFCLKOOR_S 11U 1078 1079 // Field: [10] LFCLKGOOD 1080 // 1081 // LF clock good. 1082 // 1083 // Indicates that the LF clock is good, according to the configuration in 1084 // LFQUALCTL. 1085 #define CKMD_ICLR_LFCLKGOOD 0x00000400U 1086 #define CKMD_ICLR_LFCLKGOOD_M 0x00000400U 1087 #define CKMD_ICLR_LFCLKGOOD_S 10U 1088 1089 // Field: [9] LFINCUPD 1090 // 1091 // LFINC updated. 1092 // 1093 // Indicates that a new LFINC measurement value is available in 1094 // LFCLKSTAT.LFINC. 1095 #define CKMD_ICLR_LFINCUPD 0x00000200U 1096 #define CKMD_ICLR_LFINCUPD_M 0x00000200U 1097 #define CKMD_ICLR_LFINCUPD_S 9U 1098 1099 // Field: [8] TDCDONE 1100 // 1101 // TDC done event. 1102 // 1103 // Indicates that the TDC measurement is done. 1104 #define CKMD_ICLR_TDCDONE 0x00000100U 1105 #define CKMD_ICLR_TDCDONE_M 0x00000100U 1106 #define CKMD_ICLR_TDCDONE_S 8U 1107 1108 // Field: [7] ADCPEAKUPD 1109 // 1110 // HFXT-ADC PEAK measurement update event. 1111 // 1112 // Indicates that the HFXT-ADC PEAK measurement is done. 1113 #define CKMD_ICLR_ADCPEAKUPD 0x00000080U 1114 #define CKMD_ICLR_ADCPEAKUPD_M 0x00000080U 1115 #define CKMD_ICLR_ADCPEAKUPD_S 7U 1116 1117 // Field: [6] ADCBIASUPD 1118 // 1119 // HFXT-ADC BIAS measurement update event. 1120 // 1121 // Indicates that the HFXT-ADC BIAS measurement is done. 1122 #define CKMD_ICLR_ADCBIASUPD 0x00000040U 1123 #define CKMD_ICLR_ADCBIASUPD_M 0x00000040U 1124 #define CKMD_ICLR_ADCBIASUPD_S 6U 1125 1126 // Field: [5] ADCCOMPUPD 1127 // 1128 // HFXT-ADC comparison update event. 1129 // 1130 // Indicates that the HFXT-ADC comparison is done. 1131 #define CKMD_ICLR_ADCCOMPUPD 0x00000020U 1132 #define CKMD_ICLR_ADCCOMPUPD_M 0x00000020U 1133 #define CKMD_ICLR_ADCCOMPUPD_S 5U 1134 1135 // Field: [4] TRACKREFOOR 1136 // 1137 // Out-of-range indication from the tracking loop. 1138 // 1139 // Indicates that the selected reference clock frequency of the tracking loop 1140 // is out-of-range. 1141 #define CKMD_ICLR_TRACKREFOOR 0x00000010U 1142 #define CKMD_ICLR_TRACKREFOOR_M 0x00000010U 1143 #define CKMD_ICLR_TRACKREFOOR_S 4U 1144 1145 // Field: [3] TRACKREFLOSS 1146 // 1147 // Clock loss indication from the tracking loop. 1148 // 1149 // Indicates that the selected reference clock of the tracking loop is lost. 1150 #define CKMD_ICLR_TRACKREFLOSS 0x00000008U 1151 #define CKMD_ICLR_TRACKREFLOSS_M 0x00000008U 1152 #define CKMD_ICLR_TRACKREFLOSS_S 3U 1153 1154 // Field: [2] HFXTAMPGOOD 1155 // 1156 // HFXT amplitude good indication. 1157 #define CKMD_ICLR_HFXTAMPGOOD 0x00000004U 1158 #define CKMD_ICLR_HFXTAMPGOOD_M 0x00000004U 1159 #define CKMD_ICLR_HFXTAMPGOOD_S 2U 1160 1161 // Field: [1] HFXTFAULT 1162 // 1163 // HFXT fault indication. 1164 // 1165 // Indicates that HFXT did not start correctly, or its frequency is too low. 1166 // HFXT will not recover from this fault and has to be restarted. 1167 // This is only a one-time check at HFXT startup. 1168 #define CKMD_ICLR_HFXTFAULT 0x00000002U 1169 #define CKMD_ICLR_HFXTFAULT_M 0x00000002U 1170 #define CKMD_ICLR_HFXTFAULT_S 1U 1171 1172 // Field: [0] HFXTGOOD 1173 // 1174 // HFXT good indication. 1175 // 1176 // Indicates that HFXT started correctly. The frequency is not necessarily good 1177 // enough for radio operation. 1178 // This is only a one-time check at HFXT startup. 1179 #define CKMD_ICLR_HFXTGOOD 0x00000001U 1180 #define CKMD_ICLR_HFXTGOOD_M 0x00000001U 1181 #define CKMD_ICLR_HFXTGOOD_S 0U 1182 1183 //***************************************************************************** 1184 // 1185 // Register: CKMD_O_IMSET 1186 // 1187 //***************************************************************************** 1188 // Field: [17] LFTICK 1189 // 1190 // 32kHz TICK to RTC and WDT. 1191 // 1192 // Either derived from selected LFCLK or generated from CLKULL in absence of 1193 // LFCLK. 1194 #define CKMD_IMSET_LFTICK 0x00020000U 1195 #define CKMD_IMSET_LFTICK_M 0x00020000U 1196 #define CKMD_IMSET_LFTICK_S 17U 1197 1198 // Field: [16] LFGEARRSTRT 1199 // 1200 // LFINC filter gearing restart. 1201 // 1202 // Indicates that the LFINC filter restarted gearing. Subsequent LFINC 1203 // estimates may have higher variation. 1204 #define CKMD_IMSET_LFGEARRSTRT 0x00010000U 1205 #define CKMD_IMSET_LFGEARRSTRT_M 0x00010000U 1206 #define CKMD_IMSET_LFGEARRSTRT_S 16U 1207 1208 // Field: [15] AMPSETTLED 1209 // 1210 // HFXT Amplitude compensation - settled 1211 // 1212 // Indicates that the amplitude compensation FSM has reached the SETTLED or 1213 // TCXOMODE state, 1214 // and the controls configured in HFXTTARG or HFXTDYN are reached. 1215 #define CKMD_IMSET_AMPSETTLED 0x00008000U 1216 #define CKMD_IMSET_AMPSETTLED_M 0x00008000U 1217 #define CKMD_IMSET_AMPSETTLED_S 15U 1218 1219 // Field: [14] AMPCTRLATTARG 1220 // 1221 // HFXT Amplitude compensation - controls at target 1222 // 1223 // Indicates that the control values configured in HFXTTARG or HFXTDYN are 1224 // reached. 1225 // Applies to Q1CAP, Q2CAP and IREF. 1226 #define CKMD_IMSET_AMPCTRLATTARG 0x00004000U 1227 #define CKMD_IMSET_AMPCTRLATTARG_M 0x00004000U 1228 #define CKMD_IMSET_AMPCTRLATTARG_S 14U 1229 1230 // Field: [13] PRELFEDGE 1231 // 1232 // Pre-LF clock edge detect. 1233 // 1234 // Indicates that a positive edge occured on the selected pre-LF clock 1235 // LFCLKSEL.PRE. 1236 // Can be used by software to confirm that a LF clock source is running and 1237 // within the expected frequency, 1238 // before selecting it as the main LF clock source. 1239 #define CKMD_IMSET_PRELFEDGE 0x00002000U 1240 #define CKMD_IMSET_PRELFEDGE_M 0x00002000U 1241 #define CKMD_IMSET_PRELFEDGE_S 13U 1242 1243 // Field: [12] LFCLKLOSS 1244 // 1245 // LF clock is lost. 1246 // 1247 // Indicates that no LF clock edge occured for ~49us (~1.6 times nominal 1248 // period). 1249 // The system will automatically fall-back to generating LFTICK based on 1250 // CLKULL, 1251 // to avoid timing corruption. 1252 // Note that this signal is NOT related to the analog LF clock-loss detector 1253 // which can reset the device during STANDBY. 1254 #define CKMD_IMSET_LFCLKLOSS 0x00001000U 1255 #define CKMD_IMSET_LFCLKLOSS_M 0x00001000U 1256 #define CKMD_IMSET_LFCLKLOSS_S 12U 1257 1258 // Field: [11] LFCLKOOR 1259 // 1260 // LF clock period out-of-range. 1261 // 1262 // Indicates that a LF clock period was measured to be out-of-range, 1263 // according to LFQUALCTL.MAXERR. 1264 #define CKMD_IMSET_LFCLKOOR 0x00000800U 1265 #define CKMD_IMSET_LFCLKOOR_M 0x00000800U 1266 #define CKMD_IMSET_LFCLKOOR_S 11U 1267 1268 // Field: [10] LFCLKGOOD 1269 // 1270 // LF clock good. 1271 // 1272 // Indicates that the LF clock is good, according to the configuration in 1273 // LFQUALCTL. 1274 #define CKMD_IMSET_LFCLKGOOD 0x00000400U 1275 #define CKMD_IMSET_LFCLKGOOD_M 0x00000400U 1276 #define CKMD_IMSET_LFCLKGOOD_S 10U 1277 1278 // Field: [9] LFINCUPD 1279 // 1280 // LFINC updated. 1281 // 1282 // Indicates that a new LFINC measurement value is available in 1283 // LFCLKSTAT.LFINC. 1284 #define CKMD_IMSET_LFINCUPD 0x00000200U 1285 #define CKMD_IMSET_LFINCUPD_M 0x00000200U 1286 #define CKMD_IMSET_LFINCUPD_S 9U 1287 1288 // Field: [8] TDCDONE 1289 // 1290 // TDC done event. 1291 // 1292 // Indicates that the TDC measurement is done. 1293 #define CKMD_IMSET_TDCDONE 0x00000100U 1294 #define CKMD_IMSET_TDCDONE_M 0x00000100U 1295 #define CKMD_IMSET_TDCDONE_S 8U 1296 1297 // Field: [7] ADCPEAKUPD 1298 // 1299 // HFXT-ADC PEAK measurement update event. 1300 // 1301 // Indicates that the HFXT-ADC PEAK measurement is done. 1302 #define CKMD_IMSET_ADCPEAKUPD 0x00000080U 1303 #define CKMD_IMSET_ADCPEAKUPD_M 0x00000080U 1304 #define CKMD_IMSET_ADCPEAKUPD_S 7U 1305 1306 // Field: [6] ADCBIASUPD 1307 // 1308 // HFXT-ADC BIAS measurement update event. 1309 // 1310 // Indicates that the HFXT-ADC BIAS measurement is done. 1311 #define CKMD_IMSET_ADCBIASUPD 0x00000040U 1312 #define CKMD_IMSET_ADCBIASUPD_M 0x00000040U 1313 #define CKMD_IMSET_ADCBIASUPD_S 6U 1314 1315 // Field: [5] ADCCOMPUPD 1316 // 1317 // HFXT-ADC comparison update event. 1318 // 1319 // Indicates that the HFXT-ADC comparison is done. 1320 #define CKMD_IMSET_ADCCOMPUPD 0x00000020U 1321 #define CKMD_IMSET_ADCCOMPUPD_M 0x00000020U 1322 #define CKMD_IMSET_ADCCOMPUPD_S 5U 1323 1324 // Field: [4] TRACKREFOOR 1325 // 1326 // Out-of-range indication from the tracking loop. 1327 // 1328 // Indicates that the selected reference clock frequency of the tracking loop 1329 // is out-of-range. 1330 #define CKMD_IMSET_TRACKREFOOR 0x00000010U 1331 #define CKMD_IMSET_TRACKREFOOR_M 0x00000010U 1332 #define CKMD_IMSET_TRACKREFOOR_S 4U 1333 1334 // Field: [3] TRACKREFLOSS 1335 // 1336 // Clock loss indication from the tracking loop. 1337 // 1338 // Indicates that the selected reference clock of the tracking loop is lost. 1339 #define CKMD_IMSET_TRACKREFLOSS 0x00000008U 1340 #define CKMD_IMSET_TRACKREFLOSS_M 0x00000008U 1341 #define CKMD_IMSET_TRACKREFLOSS_S 3U 1342 1343 // Field: [2] HFXTAMPGOOD 1344 // 1345 // HFXT amplitude good indication. 1346 #define CKMD_IMSET_HFXTAMPGOOD 0x00000004U 1347 #define CKMD_IMSET_HFXTAMPGOOD_M 0x00000004U 1348 #define CKMD_IMSET_HFXTAMPGOOD_S 2U 1349 1350 // Field: [1] HFXTFAULT 1351 // 1352 // HFXT fault indication. 1353 // 1354 // Indicates that HFXT did not start correctly, or its frequency is too low. 1355 // HFXT will not recover from this fault and has to be restarted. 1356 // This is only a one-time check at HFXT startup. 1357 #define CKMD_IMSET_HFXTFAULT 0x00000002U 1358 #define CKMD_IMSET_HFXTFAULT_M 0x00000002U 1359 #define CKMD_IMSET_HFXTFAULT_S 1U 1360 1361 // Field: [0] HFXTGOOD 1362 // 1363 // HFXT good indication. 1364 // 1365 // Indicates that HFXT started correctly. The frequency is not necessarily good 1366 // enough for radio operation. 1367 // This is only a one-time check at HFXT startup. 1368 #define CKMD_IMSET_HFXTGOOD 0x00000001U 1369 #define CKMD_IMSET_HFXTGOOD_M 0x00000001U 1370 #define CKMD_IMSET_HFXTGOOD_S 0U 1371 1372 //***************************************************************************** 1373 // 1374 // Register: CKMD_O_IMCLR 1375 // 1376 //***************************************************************************** 1377 // Field: [17] LFTICK 1378 // 1379 // 32kHz TICK to RTC and WDT. 1380 // 1381 // Either derived from selected LFCLK or generated from CLKULL in absence of 1382 // LFCLK. 1383 #define CKMD_IMCLR_LFTICK 0x00020000U 1384 #define CKMD_IMCLR_LFTICK_M 0x00020000U 1385 #define CKMD_IMCLR_LFTICK_S 17U 1386 1387 // Field: [16] LFGEARRSTRT 1388 // 1389 // LFINC filter gearing restart. 1390 // 1391 // Indicates that the LFINC filter restarted gearing. Subsequent LFINC 1392 // estimates may have higher variation. 1393 #define CKMD_IMCLR_LFGEARRSTRT 0x00010000U 1394 #define CKMD_IMCLR_LFGEARRSTRT_M 0x00010000U 1395 #define CKMD_IMCLR_LFGEARRSTRT_S 16U 1396 1397 // Field: [15] AMPSETTLED 1398 // 1399 // HFXT Amplitude compensation - settled 1400 // 1401 // Indicates that the amplitude compensation FSM has reached the SETTLED or 1402 // TCXOMODE state, 1403 // and the controls configured in HFXTTARG or HFXTDYN are reached. 1404 #define CKMD_IMCLR_AMPSETTLED 0x00008000U 1405 #define CKMD_IMCLR_AMPSETTLED_M 0x00008000U 1406 #define CKMD_IMCLR_AMPSETTLED_S 15U 1407 1408 // Field: [14] AMPCTRLATTARG 1409 // 1410 // HFXT Amplitude compensation - controls at target 1411 // 1412 // Indicates that the control values configured in HFXTTARG or HFXTDYN are 1413 // reached. 1414 // Applies to Q1CAP, Q2CAP and IREF. 1415 #define CKMD_IMCLR_AMPCTRLATTARG 0x00004000U 1416 #define CKMD_IMCLR_AMPCTRLATTARG_M 0x00004000U 1417 #define CKMD_IMCLR_AMPCTRLATTARG_S 14U 1418 1419 // Field: [13] PRELFEDGE 1420 // 1421 // Pre-LF clock edge detect. 1422 // 1423 // Indicates that a positive edge occured on the selected pre-LF clock 1424 // LFCLKSEL.PRE. 1425 // Can be used by software to confirm that a LF clock source is running and 1426 // within the expected frequency, 1427 // before selecting it as the main LF clock source. 1428 #define CKMD_IMCLR_PRELFEDGE 0x00002000U 1429 #define CKMD_IMCLR_PRELFEDGE_M 0x00002000U 1430 #define CKMD_IMCLR_PRELFEDGE_S 13U 1431 1432 // Field: [12] LFCLKLOSS 1433 // 1434 // LF clock is lost. 1435 // 1436 // Indicates that no LF clock edge occured for ~49us (~1.6 times nominal 1437 // period). 1438 // The system will automatically fall-back to generating LFTICK based on 1439 // CLKULL, 1440 // to avoid timing corruption. 1441 // Note that this signal is NOT related to the analog LF clock-loss detector 1442 // which can reset the device during STANDBY. 1443 #define CKMD_IMCLR_LFCLKLOSS 0x00001000U 1444 #define CKMD_IMCLR_LFCLKLOSS_M 0x00001000U 1445 #define CKMD_IMCLR_LFCLKLOSS_S 12U 1446 1447 // Field: [11] LFCLKOOR 1448 // 1449 // LF clock period out-of-range. 1450 // 1451 // Indicates that a LF clock period was measured to be out-of-range, 1452 // according to LFQUALCTL.MAXERR. 1453 #define CKMD_IMCLR_LFCLKOOR 0x00000800U 1454 #define CKMD_IMCLR_LFCLKOOR_M 0x00000800U 1455 #define CKMD_IMCLR_LFCLKOOR_S 11U 1456 1457 // Field: [10] LFCLKGOOD 1458 // 1459 // LF clock good. 1460 // 1461 // Indicates that the LF clock is good, according to the configuration in 1462 // LFQUALCTL. 1463 #define CKMD_IMCLR_LFCLKGOOD 0x00000400U 1464 #define CKMD_IMCLR_LFCLKGOOD_M 0x00000400U 1465 #define CKMD_IMCLR_LFCLKGOOD_S 10U 1466 1467 // Field: [9] LFINCUPD 1468 // 1469 // LFINC updated. 1470 // 1471 // Indicates that a new LFINC measurement value is available in 1472 // LFCLKSTAT.LFINC. 1473 #define CKMD_IMCLR_LFINCUPD 0x00000200U 1474 #define CKMD_IMCLR_LFINCUPD_M 0x00000200U 1475 #define CKMD_IMCLR_LFINCUPD_S 9U 1476 1477 // Field: [8] TDCDONE 1478 // 1479 // TDC done event. 1480 // 1481 // Indicates that the TDC measurement is done. 1482 #define CKMD_IMCLR_TDCDONE 0x00000100U 1483 #define CKMD_IMCLR_TDCDONE_M 0x00000100U 1484 #define CKMD_IMCLR_TDCDONE_S 8U 1485 1486 // Field: [7] ADCPEAKUPD 1487 // 1488 // HFXT-ADC PEAK measurement update event. 1489 // 1490 // Indicates that the HFXT-ADC PEAK measurement is done. 1491 #define CKMD_IMCLR_ADCPEAKUPD 0x00000080U 1492 #define CKMD_IMCLR_ADCPEAKUPD_M 0x00000080U 1493 #define CKMD_IMCLR_ADCPEAKUPD_S 7U 1494 1495 // Field: [6] ADCBIASUPD 1496 // 1497 // HFXT-ADC BIAS measurement update event. 1498 // 1499 // Indicates that the HFXT-ADC BIAS measurement is done. 1500 #define CKMD_IMCLR_ADCBIASUPD 0x00000040U 1501 #define CKMD_IMCLR_ADCBIASUPD_M 0x00000040U 1502 #define CKMD_IMCLR_ADCBIASUPD_S 6U 1503 1504 // Field: [5] ADCCOMPUPD 1505 // 1506 // HFXT-ADC comparison update event. 1507 // 1508 // Indicates that the HFXT-ADC comparison is done. 1509 #define CKMD_IMCLR_ADCCOMPUPD 0x00000020U 1510 #define CKMD_IMCLR_ADCCOMPUPD_M 0x00000020U 1511 #define CKMD_IMCLR_ADCCOMPUPD_S 5U 1512 1513 // Field: [4] TRACKREFOOR 1514 // 1515 // Out-of-range indication from the tracking loop. 1516 // 1517 // Indicates that the selected reference clock frequency of the tracking loop 1518 // is out-of-range. 1519 #define CKMD_IMCLR_TRACKREFOOR 0x00000010U 1520 #define CKMD_IMCLR_TRACKREFOOR_M 0x00000010U 1521 #define CKMD_IMCLR_TRACKREFOOR_S 4U 1522 1523 // Field: [3] TRACKREFLOSS 1524 // 1525 // Clock loss indication from the tracking loop. 1526 // 1527 // Indicates that the selected reference clock of the tracking loop is lost. 1528 #define CKMD_IMCLR_TRACKREFLOSS 0x00000008U 1529 #define CKMD_IMCLR_TRACKREFLOSS_M 0x00000008U 1530 #define CKMD_IMCLR_TRACKREFLOSS_S 3U 1531 1532 // Field: [2] HFXTAMPGOOD 1533 // 1534 // HFXT amplitude good indication. 1535 #define CKMD_IMCLR_HFXTAMPGOOD 0x00000004U 1536 #define CKMD_IMCLR_HFXTAMPGOOD_M 0x00000004U 1537 #define CKMD_IMCLR_HFXTAMPGOOD_S 2U 1538 1539 // Field: [1] HFXTFAULT 1540 // 1541 // HFXT fault indication. 1542 // 1543 // Indicates that HFXT did not start correctly, or its frequency is too low. 1544 // HFXT will not recover from this fault and has to be restarted. 1545 // This is only a one-time check at HFXT startup. 1546 #define CKMD_IMCLR_HFXTFAULT 0x00000002U 1547 #define CKMD_IMCLR_HFXTFAULT_M 0x00000002U 1548 #define CKMD_IMCLR_HFXTFAULT_S 1U 1549 1550 // Field: [0] HFXTGOOD 1551 // 1552 // HFXT good indication. 1553 // 1554 // Indicates that HFXT started correctly. The frequency is not necessarily good 1555 // enough for radio operation. 1556 // This is only a one-time check at HFXT startup. 1557 #define CKMD_IMCLR_HFXTGOOD 0x00000001U 1558 #define CKMD_IMCLR_HFXTGOOD_M 0x00000001U 1559 #define CKMD_IMCLR_HFXTGOOD_S 0U 1560 1561 //***************************************************************************** 1562 // 1563 // Register: CKMD_O_HFOSCCTL 1564 // 1565 //***************************************************************************** 1566 // Field: [31:24] PW 1567 // 1568 // Internal. Only to be used through TI provided API. 1569 #define CKMD_HFOSCCTL_PW_W 8U 1570 #define CKMD_HFOSCCTL_PW_M 0xFF000000U 1571 #define CKMD_HFOSCCTL_PW_S 24U 1572 1573 // Field: [8] CLKSVTOVR 1574 // 1575 // Internal. Only to be used through TI provided API. 1576 // ENUMs: 1577 // HFXT Internal. Only to be used through TI provided API. 1578 // HFOSC Internal. Only to be used through TI provided API. 1579 #define CKMD_HFOSCCTL_CLKSVTOVR 0x00000100U 1580 #define CKMD_HFOSCCTL_CLKSVTOVR_M 0x00000100U 1581 #define CKMD_HFOSCCTL_CLKSVTOVR_S 8U 1582 #define CKMD_HFOSCCTL_CLKSVTOVR_HFXT 0x00000100U 1583 #define CKMD_HFOSCCTL_CLKSVTOVR_HFOSC 0x00000000U 1584 1585 // Field: [1] FORCEOFF 1586 // 1587 // Internal. Only to be used through TI provided API. 1588 #define CKMD_HFOSCCTL_FORCEOFF 0x00000002U 1589 #define CKMD_HFOSCCTL_FORCEOFF_M 0x00000002U 1590 #define CKMD_HFOSCCTL_FORCEOFF_S 1U 1591 1592 // Field: [0] QUALBYP 1593 // 1594 // Internal. Only to be used through TI provided API. 1595 #define CKMD_HFOSCCTL_QUALBYP 0x00000001U 1596 #define CKMD_HFOSCCTL_QUALBYP_M 0x00000001U 1597 #define CKMD_HFOSCCTL_QUALBYP_S 0U 1598 1599 //***************************************************************************** 1600 // 1601 // Register: CKMD_O_HFXTCTL 1602 // 1603 //***************************************************************************** 1604 // Field: [31] AMPOVR 1605 // 1606 // Internal. Only to be used through TI provided API. 1607 #define CKMD_HFXTCTL_AMPOVR 0x80000000U 1608 #define CKMD_HFXTCTL_AMPOVR_M 0x80000000U 1609 #define CKMD_HFXTCTL_AMPOVR_S 31U 1610 1611 // Field: [26] BIASEN 1612 // 1613 // Internal. Only to be used through TI provided API. 1614 #define CKMD_HFXTCTL_BIASEN 0x04000000U 1615 #define CKMD_HFXTCTL_BIASEN_M 0x04000000U 1616 #define CKMD_HFXTCTL_BIASEN_S 26U 1617 1618 // Field: [25] LPBUFEN 1619 // 1620 // Internal. Only to be used through TI provided API. 1621 #define CKMD_HFXTCTL_LPBUFEN 0x02000000U 1622 #define CKMD_HFXTCTL_LPBUFEN_M 0x02000000U 1623 #define CKMD_HFXTCTL_LPBUFEN_S 25U 1624 1625 // Field: [24] INJECT 1626 // 1627 // Internal. Only to be used through TI provided API. 1628 #define CKMD_HFXTCTL_INJECT 0x01000000U 1629 #define CKMD_HFXTCTL_INJECT_M 0x01000000U 1630 #define CKMD_HFXTCTL_INJECT_S 24U 1631 1632 // Field: [23] QUALBYP 1633 // 1634 // Internal. Only to be used through TI provided API. 1635 #define CKMD_HFXTCTL_QUALBYP 0x00800000U 1636 #define CKMD_HFXTCTL_QUALBYP_M 0x00800000U 1637 #define CKMD_HFXTCTL_QUALBYP_S 23U 1638 1639 // Field: [19:8] QUALDLY 1640 // 1641 // Skip potentially unstable clock cycles after enabling HFXT. 1642 // Number of cycles skipped is 8*QUALDLY. 1643 #define CKMD_HFXTCTL_QUALDLY_W 12U 1644 #define CKMD_HFXTCTL_QUALDLY_M 0x000FFF00U 1645 #define CKMD_HFXTCTL_QUALDLY_S 8U 1646 1647 // Field: [7] TCXOMODE 1648 // 1649 // Temperature compensated crystal oscillator mode. 1650 // 1651 // Set this bit if a TXCO is connected. 1652 #define CKMD_HFXTCTL_TCXOMODE 0x00000080U 1653 #define CKMD_HFXTCTL_TCXOMODE_M 0x00000080U 1654 #define CKMD_HFXTCTL_TCXOMODE_S 7U 1655 1656 // Field: [6] TCXOTYPE 1657 // 1658 // Type of temperature compensated crystal used. 1659 // 1660 // Only has effect if TCXOMODE is set. 1661 // ENUMs: 1662 // CMOS Use with CMOS TCXO 1663 // CLIPPEDSINE Use with clipped-sine TCXO 1664 #define CKMD_HFXTCTL_TCXOTYPE 0x00000040U 1665 #define CKMD_HFXTCTL_TCXOTYPE_M 0x00000040U 1666 #define CKMD_HFXTCTL_TCXOTYPE_S 6U 1667 #define CKMD_HFXTCTL_TCXOTYPE_CMOS 0x00000040U 1668 #define CKMD_HFXTCTL_TCXOTYPE_CLIPPEDSINE 0x00000000U 1669 1670 // Field: [2] AUTOEN 1671 // 1672 // Internal. Only to be used through TI provided API. 1673 #define CKMD_HFXTCTL_AUTOEN 0x00000004U 1674 #define CKMD_HFXTCTL_AUTOEN_M 0x00000004U 1675 #define CKMD_HFXTCTL_AUTOEN_S 2U 1676 1677 // Field: [1] HPBUFEN 1678 // 1679 // High performance clock buffer enable. 1680 // 1681 // This bit controls the clock output for the RF PLL. 1682 // It is required for radio operation. 1683 #define CKMD_HFXTCTL_HPBUFEN 0x00000002U 1684 #define CKMD_HFXTCTL_HPBUFEN_M 0x00000002U 1685 #define CKMD_HFXTCTL_HPBUFEN_S 1U 1686 1687 // Field: [0] EN 1688 // 1689 // Internal. Only to be used through TI provided API. 1690 #define CKMD_HFXTCTL_EN 0x00000001U 1691 #define CKMD_HFXTCTL_EN_M 0x00000001U 1692 #define CKMD_HFXTCTL_EN_S 0U 1693 1694 //***************************************************************************** 1695 // 1696 // Register: CKMD_O_LFOSCCTL 1697 // 1698 //***************************************************************************** 1699 // Field: [0] EN 1700 // 1701 // LFOSC enable 1702 #define CKMD_LFOSCCTL_EN 0x00000001U 1703 #define CKMD_LFOSCCTL_EN_M 0x00000001U 1704 #define CKMD_LFOSCCTL_EN_S 0U 1705 1706 //***************************************************************************** 1707 // 1708 // Register: CKMD_O_LFXTCTL 1709 // 1710 //***************************************************************************** 1711 // Field: [14:13] LEAKCOMP 1712 // 1713 // Leakage compensation control 1714 // ENUMs: 1715 // OFF No leakage compensation 1716 // HALF Half leakage compensation 1717 // FULL Full leakage compensation 1718 #define CKMD_LFXTCTL_LEAKCOMP_W 2U 1719 #define CKMD_LFXTCTL_LEAKCOMP_M 0x00006000U 1720 #define CKMD_LFXTCTL_LEAKCOMP_S 13U 1721 #define CKMD_LFXTCTL_LEAKCOMP_OFF 0x00006000U 1722 #define CKMD_LFXTCTL_LEAKCOMP_HALF 0x00002000U 1723 #define CKMD_LFXTCTL_LEAKCOMP_FULL 0x00000000U 1724 1725 // Field: [12] BUFBIAS 1726 // 1727 // Control the BIAS current of the input amp in LP buffer 1728 // ENUMs: 1729 // MAX Maximum bias current: 50nA 1730 // MIN Minimum bias current: 25nA 1731 #define CKMD_LFXTCTL_BUFBIAS 0x00001000U 1732 #define CKMD_LFXTCTL_BUFBIAS_M 0x00001000U 1733 #define CKMD_LFXTCTL_BUFBIAS_S 12U 1734 #define CKMD_LFXTCTL_BUFBIAS_MAX 0x00001000U 1735 #define CKMD_LFXTCTL_BUFBIAS_MIN 0x00000000U 1736 1737 // Field: [11:8] AMPBIAS 1738 // 1739 // Adjust current mirror ratio into oscillator core. This value is depending on 1740 // crystal and is set by FW. This field uses a 2's complement encoding. 1741 #define CKMD_LFXTCTL_AMPBIAS_W 4U 1742 #define CKMD_LFXTCTL_AMPBIAS_M 0x00000F00U 1743 #define CKMD_LFXTCTL_AMPBIAS_S 8U 1744 1745 // Field: [7:6] BIASBOOST 1746 // 1747 // Boost oscillator amplitude 1748 // 1749 // This value depends on the crystal and needs to be configured by Firmware. 1750 #define CKMD_LFXTCTL_BIASBOOST_W 2U 1751 #define CKMD_LFXTCTL_BIASBOOST_M 0x000000C0U 1752 #define CKMD_LFXTCTL_BIASBOOST_S 6U 1753 1754 // Field: [5:4] REGBIAS 1755 // 1756 // Regulation loop bias resistor value 1757 // 1758 // This value depends on the crystal and needs to be configured by Firmware. 1759 #define CKMD_LFXTCTL_REGBIAS_W 2U 1760 #define CKMD_LFXTCTL_REGBIAS_M 0x00000030U 1761 #define CKMD_LFXTCTL_REGBIAS_S 4U 1762 1763 // Field: [2] HPBUFEN 1764 // 1765 // Control the buffer used. In normal operation, low-power buffer is used in 1766 // all device modes. The high-performance buffer is only used for test 1767 // purposes. 1768 #define CKMD_LFXTCTL_HPBUFEN 0x00000004U 1769 #define CKMD_LFXTCTL_HPBUFEN_M 0x00000004U 1770 #define CKMD_LFXTCTL_HPBUFEN_S 2U 1771 1772 // Field: [1] AMPREGMODE 1773 // 1774 // Amplitude regulation mode 1775 // ENUMs: 1776 // LOOPDIS Amplitude control loop disabled 1777 // LOOPEN Amplitude control loop enabled 1778 #define CKMD_LFXTCTL_AMPREGMODE 0x00000002U 1779 #define CKMD_LFXTCTL_AMPREGMODE_M 0x00000002U 1780 #define CKMD_LFXTCTL_AMPREGMODE_S 1U 1781 #define CKMD_LFXTCTL_AMPREGMODE_LOOPDIS 0x00000002U 1782 #define CKMD_LFXTCTL_AMPREGMODE_LOOPEN 0x00000000U 1783 1784 // Field: [0] EN 1785 // 1786 // LFXT enable 1787 #define CKMD_LFXTCTL_EN 0x00000001U 1788 #define CKMD_LFXTCTL_EN_M 0x00000001U 1789 #define CKMD_LFXTCTL_EN_S 0U 1790 1791 //***************************************************************************** 1792 // 1793 // Register: CKMD_O_LFQUALCTL 1794 // 1795 //***************************************************************************** 1796 // Field: [13:8] MAXERR 1797 // 1798 // Maximum LFCLK period error. 1799 // 1800 // Value given in microseconds, 3 integer bits + 3 fractional bits. 1801 #define CKMD_LFQUALCTL_MAXERR_W 6U 1802 #define CKMD_LFQUALCTL_MAXERR_M 0x00003F00U 1803 #define CKMD_LFQUALCTL_MAXERR_S 8U 1804 1805 // Field: [7:0] CONSEC 1806 // 1807 // Number of consecutive times the LFCLK period error has to be 1808 // smaller than MAXERR to be considered "good". 1809 // Setting this value to 0 will bypass clock qualification, 1810 // and the "good" indicator will always be 1. 1811 #define CKMD_LFQUALCTL_CONSEC_W 8U 1812 #define CKMD_LFQUALCTL_CONSEC_M 0x000000FFU 1813 #define CKMD_LFQUALCTL_CONSEC_S 0U 1814 1815 //***************************************************************************** 1816 // 1817 // Register: CKMD_O_LFINCCTL 1818 // 1819 //***************************************************************************** 1820 // Field: [31] PREVENTSTBY 1821 // 1822 // Controls if the LFINC filter prevents STANBY entry until settled. 1823 // ENUMs: 1824 // ON Enable. Prevent STANDBY entry. 1825 // OFF Disable. Do not prevent STANDBY entry. 1826 #define CKMD_LFINCCTL_PREVENTSTBY 0x80000000U 1827 #define CKMD_LFINCCTL_PREVENTSTBY_M 0x80000000U 1828 #define CKMD_LFINCCTL_PREVENTSTBY_S 31U 1829 #define CKMD_LFINCCTL_PREVENTSTBY_ON 0x80000000U 1830 #define CKMD_LFINCCTL_PREVENTSTBY_OFF 0x00000000U 1831 1832 // Field: [29:8] INT 1833 // 1834 // Integral part of the LFINC filter. 1835 // 1836 // This value is updated by Hardware to reflect the current state of the 1837 // filter. 1838 // It can also be written to change the current state. 1839 #define CKMD_LFINCCTL_INT_W 22U 1840 #define CKMD_LFINCCTL_INT_M 0x3FFFFF00U 1841 #define CKMD_LFINCCTL_INT_S 8U 1842 1843 // Field: [7] STOPGEAR 1844 // 1845 // Controls the final gear of the LFINC filter. 1846 // ENUMs: 1847 // HIGH Highest final gear. Best dynamic frequency 1848 // tracking, but higher variation in filter value. 1849 // LOW Lowest final gear. Best settling, but less dynamic 1850 // frequency tracking. 1851 #define CKMD_LFINCCTL_STOPGEAR 0x00000080U 1852 #define CKMD_LFINCCTL_STOPGEAR_M 0x00000080U 1853 #define CKMD_LFINCCTL_STOPGEAR_S 7U 1854 #define CKMD_LFINCCTL_STOPGEAR_HIGH 0x00000080U 1855 #define CKMD_LFINCCTL_STOPGEAR_LOW 0x00000000U 1856 1857 // Field: [6:5] ERRTHR 1858 // 1859 // Controls the threshold for gearing restart of the LFINC filter. 1860 // 1861 // Only effective if GEARRSTRT is not ONETHR or TWOTHR. 1862 // ENUMs: 1863 // SMALL Restart gearing on small error. Potentially more 1864 // false restarts, faster response on small 1865 // frequency shifts. 1866 // MIDSMALL Middle value towards SMALL. 1867 // MIDLARGE Middle value towards LARGE. 1868 // LARGE Restart gearing on large error. Fewer false 1869 // restarts, slower response on small frequency 1870 // shifts. 1871 #define CKMD_LFINCCTL_ERRTHR_W 2U 1872 #define CKMD_LFINCCTL_ERRTHR_M 0x00000060U 1873 #define CKMD_LFINCCTL_ERRTHR_S 5U 1874 #define CKMD_LFINCCTL_ERRTHR_SMALL 0x00000060U 1875 #define CKMD_LFINCCTL_ERRTHR_MIDSMALL 0x00000040U 1876 #define CKMD_LFINCCTL_ERRTHR_MIDLARGE 0x00000020U 1877 #define CKMD_LFINCCTL_ERRTHR_LARGE 0x00000000U 1878 1879 // Field: [4:3] GEARRSTRT 1880 // 1881 // Controls gearing restart of the LFINC filter. 1882 // ENUMs: 1883 // TWOTHR Restart gearing when the error accumulator crosses 1884 // the threshold twice in a row. 1885 // ONETHR Restart gearing when the error accumulator crosses 1886 // the threshold once. 1887 // NEVER Never restart gearing. Very stable filter value, 1888 // but very slow response on frequency changes. 1889 #define CKMD_LFINCCTL_GEARRSTRT_W 2U 1890 #define CKMD_LFINCCTL_GEARRSTRT_M 0x00000018U 1891 #define CKMD_LFINCCTL_GEARRSTRT_S 3U 1892 #define CKMD_LFINCCTL_GEARRSTRT_TWOTHR 0x00000010U 1893 #define CKMD_LFINCCTL_GEARRSTRT_ONETHR 0x00000008U 1894 #define CKMD_LFINCCTL_GEARRSTRT_NEVER 0x00000000U 1895 1896 // Field: [2] SOFTRSTRT 1897 // 1898 // Use a higher gear after re-enabling / wakeup. 1899 // 1900 // The filter will require 16-24 LFCLK periods to settle (depending on 1901 // STOPGEAR), but may respond faster to frequency changes during STANDBY. 1902 // ENUMs: 1903 // ON Use soft gearing restarts 1904 // OFF Don't use soft gearing restarts 1905 #define CKMD_LFINCCTL_SOFTRSTRT 0x00000004U 1906 #define CKMD_LFINCCTL_SOFTRSTRT_M 0x00000004U 1907 #define CKMD_LFINCCTL_SOFTRSTRT_S 2U 1908 #define CKMD_LFINCCTL_SOFTRSTRT_ON 0x00000004U 1909 #define CKMD_LFINCCTL_SOFTRSTRT_OFF 0x00000000U 1910 1911 //***************************************************************************** 1912 // 1913 // Register: CKMD_O_LFINCOVR 1914 // 1915 //***************************************************************************** 1916 // Field: [31] OVERRIDE 1917 // 1918 // Override LF increment 1919 // 1920 // Use the value provided in LFINC instead of the value calculated by Hardware. 1921 #define CKMD_LFINCOVR_OVERRIDE 0x80000000U 1922 #define CKMD_LFINCOVR_OVERRIDE_M 0x80000000U 1923 #define CKMD_LFINCOVR_OVERRIDE_S 31U 1924 1925 // Field: [21:0] LFINC 1926 // 1927 // LF increment value 1928 // 1929 // This value is used when OVERRIDE is set to 1. 1930 // Otherwise the value is calculated automatically. 1931 #define CKMD_LFINCOVR_LFINC_W 22U 1932 #define CKMD_LFINCOVR_LFINC_M 0x003FFFFFU 1933 #define CKMD_LFINCOVR_LFINC_S 0U 1934 1935 //***************************************************************************** 1936 // 1937 // Register: CKMD_O_AMPADCCTL 1938 // 1939 //***************************************************************************** 1940 // Field: [31] SWOVR 1941 // 1942 // Internal. Only to be used through TI provided API. 1943 #define CKMD_AMPADCCTL_SWOVR 0x80000000U 1944 #define CKMD_AMPADCCTL_SWOVR_M 0x80000000U 1945 #define CKMD_AMPADCCTL_SWOVR_S 31U 1946 1947 // Field: [17] PEAKDETEN 1948 // 1949 // Internal. Only to be used through TI provided API. 1950 // ENUMs: 1951 // ENABLE Internal. Only to be used through TI provided API. 1952 // DISABLE Internal. Only to be used through TI provided API. 1953 #define CKMD_AMPADCCTL_PEAKDETEN 0x00020000U 1954 #define CKMD_AMPADCCTL_PEAKDETEN_M 0x00020000U 1955 #define CKMD_AMPADCCTL_PEAKDETEN_S 17U 1956 #define CKMD_AMPADCCTL_PEAKDETEN_ENABLE 0x00020000U 1957 #define CKMD_AMPADCCTL_PEAKDETEN_DISABLE 0x00000000U 1958 1959 // Field: [16] ADCEN 1960 // 1961 // Internal. Only to be used through TI provided API. 1962 // ENUMs: 1963 // ENABLE Internal. Only to be used through TI provided API. 1964 // DISABLE Internal. Only to be used through TI provided API. 1965 #define CKMD_AMPADCCTL_ADCEN 0x00010000U 1966 #define CKMD_AMPADCCTL_ADCEN_M 0x00010000U 1967 #define CKMD_AMPADCCTL_ADCEN_S 16U 1968 #define CKMD_AMPADCCTL_ADCEN_ENABLE 0x00010000U 1969 #define CKMD_AMPADCCTL_ADCEN_DISABLE 0x00000000U 1970 1971 // Field: [14:8] COMPVAL 1972 // 1973 // Internal. Only to be used through TI provided API. 1974 #define CKMD_AMPADCCTL_COMPVAL_W 7U 1975 #define CKMD_AMPADCCTL_COMPVAL_M 0x00007F00U 1976 #define CKMD_AMPADCCTL_COMPVAL_S 8U 1977 1978 // Field: [4] SRCSEL 1979 // 1980 // Internal. Only to be used through TI provided API. 1981 // ENUMs: 1982 // PEAK Internal. Only to be used through TI provided API. 1983 // BIAS Internal. Only to be used through TI provided API. 1984 #define CKMD_AMPADCCTL_SRCSEL 0x00000010U 1985 #define CKMD_AMPADCCTL_SRCSEL_M 0x00000010U 1986 #define CKMD_AMPADCCTL_SRCSEL_S 4U 1987 #define CKMD_AMPADCCTL_SRCSEL_PEAK 0x00000010U 1988 #define CKMD_AMPADCCTL_SRCSEL_BIAS 0x00000000U 1989 1990 // Field: [1] COMPSTRT 1991 // 1992 // Internal. Only to be used through TI provided API. 1993 #define CKMD_AMPADCCTL_COMPSTRT 0x00000002U 1994 #define CKMD_AMPADCCTL_COMPSTRT_M 0x00000002U 1995 #define CKMD_AMPADCCTL_COMPSTRT_S 1U 1996 1997 // Field: [0] SARSTRT 1998 // 1999 // Internal. Only to be used through TI provided API. 2000 #define CKMD_AMPADCCTL_SARSTRT 0x00000001U 2001 #define CKMD_AMPADCCTL_SARSTRT_M 0x00000001U 2002 #define CKMD_AMPADCCTL_SARSTRT_S 0U 2003 2004 //***************************************************************************** 2005 // 2006 // Register: CKMD_O_HFTRACKCTL 2007 // 2008 //***************************************************************************** 2009 // Field: [31] EN 2010 // 2011 // Enable tracking loop. 2012 #define CKMD_HFTRACKCTL_EN 0x80000000U 2013 #define CKMD_HFTRACKCTL_EN_M 0x80000000U 2014 #define CKMD_HFTRACKCTL_EN_S 31U 2015 2016 // Field: [30] DSMBYP 2017 // 2018 // Bypass Delta-Sigma-Modulation of fine trim. 2019 #define CKMD_HFTRACKCTL_DSMBYP 0x40000000U 2020 #define CKMD_HFTRACKCTL_DSMBYP_M 0x40000000U 2021 #define CKMD_HFTRACKCTL_DSMBYP_S 30U 2022 2023 // Field: [27:26] REFCLK 2024 // 2025 // Select the reference clock for the tracking loop. 2026 // Change only while the tracking loop is disabled. 2027 // ENUMs: 2028 // GPI Select GPI as reference clock. 2029 // LRF Select LRF reference clock. 2030 // HFXT Select HFXT as reference clock. 2031 #define CKMD_HFTRACKCTL_REFCLK_W 2U 2032 #define CKMD_HFTRACKCTL_REFCLK_M 0x0C000000U 2033 #define CKMD_HFTRACKCTL_REFCLK_S 26U 2034 #define CKMD_HFTRACKCTL_REFCLK_GPI 0x08000000U 2035 #define CKMD_HFTRACKCTL_REFCLK_LRF 0x04000000U 2036 #define CKMD_HFTRACKCTL_REFCLK_HFXT 0x00000000U 2037 2038 // Field: [25:0] RATIO 2039 // 2040 // Reference clock ratio. 2041 // 2042 // RATIO = 24MHz / (2*reference-frequency) * 2^24 2043 // Commonly used reference clock frequencies are provided as enumerations. 2044 // ENUMs: 2045 // REF4M Use for 4MHz reference clock 2046 // REF8M Use for 8MHz reference clock 2047 // REF48M Use for 48MHz reference clock 2048 #define CKMD_HFTRACKCTL_RATIO_W 26U 2049 #define CKMD_HFTRACKCTL_RATIO_M 0x03FFFFFFU 2050 #define CKMD_HFTRACKCTL_RATIO_S 0U 2051 #define CKMD_HFTRACKCTL_RATIO_REF4M 0x03000000U 2052 #define CKMD_HFTRACKCTL_RATIO_REF8M 0x01800000U 2053 #define CKMD_HFTRACKCTL_RATIO_REF48M 0x00400000U 2054 2055 //***************************************************************************** 2056 // 2057 // Register: CKMD_O_LDOCTL 2058 // 2059 //***************************************************************************** 2060 // Field: [31] SWOVR 2061 // 2062 // Internal. Only to be used through TI provided API. 2063 #define CKMD_LDOCTL_SWOVR 0x80000000U 2064 #define CKMD_LDOCTL_SWOVR_M 0x80000000U 2065 #define CKMD_LDOCTL_SWOVR_S 31U 2066 2067 // Field: [4] HFXTLVLEN 2068 // 2069 // Internal. Only to be used through TI provided API. 2070 #define CKMD_LDOCTL_HFXTLVLEN 0x00000010U 2071 #define CKMD_LDOCTL_HFXTLVLEN_M 0x00000010U 2072 #define CKMD_LDOCTL_HFXTLVLEN_S 4U 2073 2074 // Field: [3] STARTCTL 2075 // 2076 // Internal. Only to be used through TI provided API. 2077 #define CKMD_LDOCTL_STARTCTL 0x00000008U 2078 #define CKMD_LDOCTL_STARTCTL_M 0x00000008U 2079 #define CKMD_LDOCTL_STARTCTL_S 3U 2080 2081 // Field: [2] START 2082 // 2083 // Internal. Only to be used through TI provided API. 2084 #define CKMD_LDOCTL_START 0x00000004U 2085 #define CKMD_LDOCTL_START_M 0x00000004U 2086 #define CKMD_LDOCTL_START_S 2U 2087 2088 // Field: [1] BYPASS 2089 // 2090 // Internal. Only to be used through TI provided API. 2091 #define CKMD_LDOCTL_BYPASS 0x00000002U 2092 #define CKMD_LDOCTL_BYPASS_M 0x00000002U 2093 #define CKMD_LDOCTL_BYPASS_S 1U 2094 2095 // Field: [0] EN 2096 // 2097 // Internal. Only to be used through TI provided API. 2098 #define CKMD_LDOCTL_EN 0x00000001U 2099 #define CKMD_LDOCTL_EN_M 0x00000001U 2100 #define CKMD_LDOCTL_EN_S 0U 2101 2102 //***************************************************************************** 2103 // 2104 // Register: CKMD_O_NABIASCTL 2105 // 2106 //***************************************************************************** 2107 // Field: [0] EN 2108 // 2109 // Enable nanoamp-bias 2110 #define CKMD_NABIASCTL_EN 0x00000001U 2111 #define CKMD_NABIASCTL_EN_M 0x00000001U 2112 #define CKMD_NABIASCTL_EN_S 0U 2113 2114 //***************************************************************************** 2115 // 2116 // Register: CKMD_O_LFMONCTL 2117 // 2118 //***************************************************************************** 2119 // Field: [0] EN 2120 // 2121 // Enable LFMONITOR. 2122 // Enable only after a LF clock source has been selected, enabled and is 2123 // stable. 2124 // If LFMONITOR detects a clock loss, the system will be reset. 2125 #define CKMD_LFMONCTL_EN 0x00000001U 2126 #define CKMD_LFMONCTL_EN_M 0x00000001U 2127 #define CKMD_LFMONCTL_EN_S 0U 2128 2129 //***************************************************************************** 2130 // 2131 // Register: CKMD_O_LFCLKSEL 2132 // 2133 //***************************************************************************** 2134 // Field: [3:2] PRE 2135 // 2136 // Select low frequency clock source for the PRELFCLK interrupt. 2137 // 2138 // Can be used by Software to confirm that the clock is running and it's 2139 // frequency is good, before selecting it in MAIN. 2140 // ENUMs: 2141 // EXTLF External LF clock through GPI. 2142 // LFXT Low frequency crystal oscillator 2143 // LFOSC Low frequency on-chip oscillator 2144 // NONE No clock. Output will be tied low. 2145 #define CKMD_LFCLKSEL_PRE_W 2U 2146 #define CKMD_LFCLKSEL_PRE_M 0x0000000CU 2147 #define CKMD_LFCLKSEL_PRE_S 2U 2148 #define CKMD_LFCLKSEL_PRE_EXTLF 0x0000000CU 2149 #define CKMD_LFCLKSEL_PRE_LFXT 0x00000008U 2150 #define CKMD_LFCLKSEL_PRE_LFOSC 0x00000004U 2151 #define CKMD_LFCLKSEL_PRE_NONE 0x00000000U 2152 2153 // Field: [1:0] MAIN 2154 // 2155 // Select the main low frequency clock source. 2156 // 2157 // If running, this clock will be used to generate LFTICK and as CLKULL during 2158 // STANDBY. 2159 // If not running, LFTICK will be generated from HFOSC and STANDBY entry will 2160 // be prevented. 2161 // ENUMs: 2162 // EXTLF External LF clock through GPI. 2163 // LFXT Low frequency crystal oscillator 2164 // LFOSC Low frequency on-chip oscillator 2165 // FAKE No LF clock selected. LFTICK will be generated 2166 // from HFOSC, STANDBY entry will be prevented. 2167 #define CKMD_LFCLKSEL_MAIN_W 2U 2168 #define CKMD_LFCLKSEL_MAIN_M 0x00000003U 2169 #define CKMD_LFCLKSEL_MAIN_S 0U 2170 #define CKMD_LFCLKSEL_MAIN_EXTLF 0x00000003U 2171 #define CKMD_LFCLKSEL_MAIN_LFXT 0x00000002U 2172 #define CKMD_LFCLKSEL_MAIN_LFOSC 0x00000001U 2173 #define CKMD_LFCLKSEL_MAIN_FAKE 0x00000000U 2174 2175 //***************************************************************************** 2176 // 2177 // Register: CKMD_O_TDCCLKSEL 2178 // 2179 //***************************************************************************** 2180 // Field: [1:0] REFCLK 2181 // 2182 // Internal. Only to be used through TI provided API. 2183 // ENUMs: 2184 // GPI Internal. Only to be used through TI provided API. 2185 // CLKULL Internal. Only to be used through TI provided API. 2186 // CLKSVT Internal. Only to be used through TI provided API. 2187 // NONE Internal. Only to be used through TI provided API. 2188 #define CKMD_TDCCLKSEL_REFCLK_W 2U 2189 #define CKMD_TDCCLKSEL_REFCLK_M 0x00000003U 2190 #define CKMD_TDCCLKSEL_REFCLK_S 0U 2191 #define CKMD_TDCCLKSEL_REFCLK_GPI 0x00000003U 2192 #define CKMD_TDCCLKSEL_REFCLK_CLKULL 0x00000002U 2193 #define CKMD_TDCCLKSEL_REFCLK_CLKSVT 0x00000001U 2194 #define CKMD_TDCCLKSEL_REFCLK_NONE 0x00000000U 2195 2196 //***************************************************************************** 2197 // 2198 // Register: CKMD_O_ADCCLKSEL 2199 // 2200 //***************************************************************************** 2201 // Field: [1:0] SRC 2202 // 2203 // Select ADC clock source 2204 // 2205 // Change only while ADC is disabled. 2206 // ENUMs: 2207 // HFXT 48MHz HFXT 2208 // CLKSVT 48MHz CLKSVT 2209 #define CKMD_ADCCLKSEL_SRC_W 2U 2210 #define CKMD_ADCCLKSEL_SRC_M 0x00000003U 2211 #define CKMD_ADCCLKSEL_SRC_S 0U 2212 #define CKMD_ADCCLKSEL_SRC_HFXT 0x00000001U 2213 #define CKMD_ADCCLKSEL_SRC_CLKSVT 0x00000000U 2214 2215 //***************************************************************************** 2216 // 2217 // Register: CKMD_O_LFCLKSTAT 2218 // 2219 //***************************************************************************** 2220 // Field: [31] GOOD 2221 // 2222 // Low frequency clock good 2223 // 2224 // Note: This is only a coarse frequency check based on LFQUALCTL. The clock 2225 // may not be accurate enough for timing purposes. 2226 #define CKMD_LFCLKSTAT_GOOD 0x80000000U 2227 #define CKMD_LFCLKSTAT_GOOD_M 0x80000000U 2228 #define CKMD_LFCLKSTAT_GOOD_S 31U 2229 2230 // Field: [25] FLTSETTLED 2231 // 2232 // LFINC filter is running and settled. 2233 #define CKMD_LFCLKSTAT_FLTSETTLED 0x02000000U 2234 #define CKMD_LFCLKSTAT_FLTSETTLED_M 0x02000000U 2235 #define CKMD_LFCLKSTAT_FLTSETTLED_S 25U 2236 2237 // Field: [24] LFTICKSRC 2238 // 2239 // Source of LFTICK. 2240 // ENUMs: 2241 // FAKE LFTICK generated from CLKULL (LFCLK not available) 2242 // LFCLK LFTICK generated from the selected LFCLK 2243 #define CKMD_LFCLKSTAT_LFTICKSRC 0x01000000U 2244 #define CKMD_LFCLKSTAT_LFTICKSRC_M 0x01000000U 2245 #define CKMD_LFCLKSTAT_LFTICKSRC_S 24U 2246 #define CKMD_LFCLKSTAT_LFTICKSRC_FAKE 0x01000000U 2247 #define CKMD_LFCLKSTAT_LFTICKSRC_LFCLK 0x00000000U 2248 2249 // Field: [23:22] LFINCSRC 2250 // 2251 // Source of LFINC used by the RTC. 2252 // 2253 // This value depends on LFINCOVR.OVERRIDE, LF clock availability, HF tracking 2254 // loop status and the device state (ACTIVE/STANDBY). 2255 // ENUMs: 2256 // FAKE Using FAKE LFTICKs with corresponding LFINC value. 2257 // OVERRIDE Using override value from LFINCOVR.LFINC 2258 // AVG Using filtered / average value. 2259 // This value is updated by 2260 // hardware and can be read and updated in 2261 // LFINCCTL.INT. 2262 // MEAS Using measured value. 2263 // This value is updated by 2264 // hardware and can be read from LFINC. 2265 #define CKMD_LFCLKSTAT_LFINCSRC_W 2U 2266 #define CKMD_LFCLKSTAT_LFINCSRC_M 0x00C00000U 2267 #define CKMD_LFCLKSTAT_LFINCSRC_S 22U 2268 #define CKMD_LFCLKSTAT_LFINCSRC_FAKE 0x00C00000U 2269 #define CKMD_LFCLKSTAT_LFINCSRC_OVERRIDE 0x00800000U 2270 #define CKMD_LFCLKSTAT_LFINCSRC_AVG 0x00400000U 2271 #define CKMD_LFCLKSTAT_LFINCSRC_MEAS 0x00000000U 2272 2273 // Field: [21:0] LFINC 2274 // 2275 // Measured value of LFINC. 2276 // 2277 // Given in microseconds with 16 fractional bits. 2278 // This value is calculated by Hardware. 2279 // It is the LFCLK period according to CLKULL cycles. 2280 #define CKMD_LFCLKSTAT_LFINC_W 22U 2281 #define CKMD_LFCLKSTAT_LFINC_M 0x003FFFFFU 2282 #define CKMD_LFCLKSTAT_LFINC_S 0U 2283 2284 //***************************************************************************** 2285 // 2286 // Register: CKMD_O_HFXTSTAT 2287 // 2288 //***************************************************************************** 2289 // Field: [30:16] STARTUPTIME 2290 // 2291 // HFXT startup time 2292 // 2293 // Can be used by software to plan starting HFXT ahead in time. 2294 // Measured whenever HFXT is enabled in CLKULL periods (24MHz), from HFXTCTL.EN 2295 // until the clock is good for radio operation (amplitude compensation is 2296 // settled). 2297 #define CKMD_HFXTSTAT_STARTUPTIME_W 15U 2298 #define CKMD_HFXTSTAT_STARTUPTIME_M 0x7FFF0000U 2299 #define CKMD_HFXTSTAT_STARTUPTIME_S 16U 2300 2301 // Field: [1] FAULT 2302 // 2303 // HFXT clock fault 2304 // 2305 // Indicates a lower than expected HFXT frequency. 2306 // HFXT will not recover from this fault, disabling and re-enabling HFXT is 2307 // required. 2308 #define CKMD_HFXTSTAT_FAULT 0x00000002U 2309 #define CKMD_HFXTSTAT_FAULT_M 0x00000002U 2310 #define CKMD_HFXTSTAT_FAULT_S 1U 2311 2312 // Field: [0] GOOD 2313 // 2314 // HFXT clock available. 2315 // 2316 // The frequency is not necessarily good enough for radio operation. 2317 #define CKMD_HFXTSTAT_GOOD 0x00000001U 2318 #define CKMD_HFXTSTAT_GOOD_M 0x00000001U 2319 #define CKMD_HFXTSTAT_GOOD_S 0U 2320 2321 //***************************************************************************** 2322 // 2323 // Register: CKMD_O_AMPADCSTAT 2324 // 2325 //***************************************************************************** 2326 // Field: [24] COMPOUT 2327 // 2328 // Internal. Only to be used through TI provided API. 2329 #define CKMD_AMPADCSTAT_COMPOUT 0x01000000U 2330 #define CKMD_AMPADCSTAT_COMPOUT_M 0x01000000U 2331 #define CKMD_AMPADCSTAT_COMPOUT_S 24U 2332 2333 // Field: [22:16] PEAKRAW 2334 // 2335 // Internal. Only to be used through TI provided API. 2336 #define CKMD_AMPADCSTAT_PEAKRAW_W 7U 2337 #define CKMD_AMPADCSTAT_PEAKRAW_M 0x007F0000U 2338 #define CKMD_AMPADCSTAT_PEAKRAW_S 16U 2339 2340 // Field: [15:8] PEAK 2341 // 2342 // Internal. Only to be used through TI provided API. 2343 #define CKMD_AMPADCSTAT_PEAK_W 8U 2344 #define CKMD_AMPADCSTAT_PEAK_M 0x0000FF00U 2345 #define CKMD_AMPADCSTAT_PEAK_S 8U 2346 2347 // Field: [6:0] BIAS 2348 // 2349 // Internal. Only to be used through TI provided API. 2350 #define CKMD_AMPADCSTAT_BIAS_W 7U 2351 #define CKMD_AMPADCSTAT_BIAS_M 0x0000007FU 2352 #define CKMD_AMPADCSTAT_BIAS_S 0U 2353 2354 //***************************************************************************** 2355 // 2356 // Register: CKMD_O_TRACKSTAT 2357 // 2358 //***************************************************************************** 2359 // Field: [31] LOOPERRVLD 2360 // 2361 // Current HFOSC tracking error valid 2362 // 2363 // This bit is one if the tracking loop is running and the error value is 2364 // valid. 2365 #define CKMD_TRACKSTAT_LOOPERRVLD 0x80000000U 2366 #define CKMD_TRACKSTAT_LOOPERRVLD_M 0x80000000U 2367 #define CKMD_TRACKSTAT_LOOPERRVLD_S 31U 2368 2369 // Field: [29:16] LOOPERR 2370 // 2371 // Current HFOSC tracking error 2372 #define CKMD_TRACKSTAT_LOOPERR_W 14U 2373 #define CKMD_TRACKSTAT_LOOPERR_M 0x3FFF0000U 2374 #define CKMD_TRACKSTAT_LOOPERR_S 16U 2375 2376 // Field: [12:0] FINETRIM 2377 // 2378 // Current HFOSC Fine-trim value 2379 // 2380 // This field uses the internal fractional representation (sign, 4 integer 2381 // bits, 8 fractional bits). 2382 // The actual trim value applied to the oscillator is delta-sigma modulated 5 2383 // bits non-signed 2384 // (inverted sign bit + integer bits). 2385 #define CKMD_TRACKSTAT_FINETRIM_W 13U 2386 #define CKMD_TRACKSTAT_FINETRIM_M 0x00001FFFU 2387 #define CKMD_TRACKSTAT_FINETRIM_S 0U 2388 2389 //***************************************************************************** 2390 // 2391 // Register: CKMD_O_AMPSTAT 2392 // 2393 //***************************************************************************** 2394 // Field: [28:25] STATE 2395 // 2396 // Current AMPCOMP FSM state. 2397 // ENUMs: 2398 // SETTLED Settled state 2399 // UPDATEUP Amplitude up correction 2400 // TXCOMODE TCXO settled state 2401 // SHUTDN0 First shutdown state 2402 // INJWAIT Post injection settle wait 2403 // UPDATEDN Amplitude down correction 2404 // RAMP0 Initial amplitude ramping with HFXTINIT values 2405 // RAMP1 Transition to HFXTTARG values 2406 // INJECT Injecting HFOSC for fast startup 2407 // SHUTDN1 Second shutdown state 2408 // LDOSTART Starting LDO 2409 // IDLE FSM in idle state 2410 #define CKMD_AMPSTAT_STATE_W 4U 2411 #define CKMD_AMPSTAT_STATE_M 0x1E000000U 2412 #define CKMD_AMPSTAT_STATE_S 25U 2413 #define CKMD_AMPSTAT_STATE_SETTLED 0x1E000000U 2414 #define CKMD_AMPSTAT_STATE_UPDATEUP 0x1C000000U 2415 #define CKMD_AMPSTAT_STATE_TXCOMODE 0x18000000U 2416 #define CKMD_AMPSTAT_STATE_SHUTDN0 0x14000000U 2417 #define CKMD_AMPSTAT_STATE_INJWAIT 0x0E000000U 2418 #define CKMD_AMPSTAT_STATE_UPDATEDN 0x0C000000U 2419 #define CKMD_AMPSTAT_STATE_RAMP0 0x0A000000U 2420 #define CKMD_AMPSTAT_STATE_RAMP1 0x08000000U 2421 #define CKMD_AMPSTAT_STATE_INJECT 0x06000000U 2422 #define CKMD_AMPSTAT_STATE_SHUTDN1 0x04000000U 2423 #define CKMD_AMPSTAT_STATE_LDOSTART 0x02000000U 2424 #define CKMD_AMPSTAT_STATE_IDLE 0x00000000U 2425 2426 // Field: [24:18] IDAC 2427 // 2428 // Current IDAC control value. 2429 #define CKMD_AMPSTAT_IDAC_W 7U 2430 #define CKMD_AMPSTAT_IDAC_M 0x01FC0000U 2431 #define CKMD_AMPSTAT_IDAC_S 18U 2432 2433 // Field: [17:14] IREF 2434 // 2435 // Current IREF control value. 2436 #define CKMD_AMPSTAT_IREF_W 4U 2437 #define CKMD_AMPSTAT_IREF_M 0x0003C000U 2438 #define CKMD_AMPSTAT_IREF_S 14U 2439 2440 // Field: [13:8] Q2CAP 2441 // 2442 // Current Q2CAP control value. 2443 #define CKMD_AMPSTAT_Q2CAP_W 6U 2444 #define CKMD_AMPSTAT_Q2CAP_M 0x00003F00U 2445 #define CKMD_AMPSTAT_Q2CAP_S 8U 2446 2447 // Field: [7:2] Q1CAP 2448 // 2449 // Current Q1CAP control value. 2450 #define CKMD_AMPSTAT_Q1CAP_W 6U 2451 #define CKMD_AMPSTAT_Q1CAP_M 0x000000FCU 2452 #define CKMD_AMPSTAT_Q1CAP_S 2U 2453 2454 // Field: [1] CTRLATTARGET 2455 // 2456 // HFXT control values match target values. 2457 // 2458 // This applies to IREF, Q1CAP, Q2CAP values. 2459 #define CKMD_AMPSTAT_CTRLATTARGET 0x00000002U 2460 #define CKMD_AMPSTAT_CTRLATTARGET_M 0x00000002U 2461 #define CKMD_AMPSTAT_CTRLATTARGET_S 1U 2462 2463 // Field: [0] AMPGOOD 2464 // 2465 // HFXT amplitude good 2466 #define CKMD_AMPSTAT_AMPGOOD 0x00000001U 2467 #define CKMD_AMPSTAT_AMPGOOD_M 0x00000001U 2468 #define CKMD_AMPSTAT_AMPGOOD_S 0U 2469 2470 //***************************************************************************** 2471 // 2472 // Register: CKMD_O_ATBCTL0 2473 // 2474 //***************************************************************************** 2475 // Field: [18:0] SEL 2476 // 2477 // Internal. Only to be used through TI provided API. 2478 // ENUMs: 2479 // LFXTTESTCLK Internal. Only to be used through TI provided API. 2480 // LFOSCTESTCLK Internal. Only to be used through TI provided API. 2481 // HFXTTESTCLK Internal. Only to be used through TI provided API. 2482 // HFOSCTESTCLK Internal. Only to be used through TI provided API. 2483 // LFMONVTEST Internal. Only to be used through TI provided API. 2484 // LFOSCVDDL Internal. Only to be used through TI provided API. 2485 // HFOSCIBIAS Internal. Only to be used through TI provided API. 2486 // HFOSCVDDL Internal. Only to be used through TI provided API. 2487 // HFOSCVREF Internal. Only to be used through TI provided API. 2488 // NABIASITEST Internal. Only to be used through TI provided API. 2489 // ADCDACOUT Internal. Only to be used through TI provided API. 2490 // ADCCOMPIN Internal. Only to be used through TI provided API. 2491 // ADCCOMPOUT Internal. Only to be used through TI provided API. 2492 // LFXTANA Internal. Only to be used through TI provided API. 2493 // LDOITEST Internal. Only to be used through TI provided API. 2494 // VDDCKM Internal. Only to be used through TI provided API. 2495 // HFXTANA Internal. Only to be used through TI provided API. 2496 // OFF Internal. Only to be used through TI provided API. 2497 #define CKMD_ATBCTL0_SEL_W 19U 2498 #define CKMD_ATBCTL0_SEL_M 0x0007FFFFU 2499 #define CKMD_ATBCTL0_SEL_S 0U 2500 #define CKMD_ATBCTL0_SEL_LFXTTESTCLK 0x00070000U 2501 #define CKMD_ATBCTL0_SEL_LFOSCTESTCLK 0x00050000U 2502 #define CKMD_ATBCTL0_SEL_HFXTTESTCLK 0x00030000U 2503 #define CKMD_ATBCTL0_SEL_HFOSCTESTCLK 0x00010000U 2504 #define CKMD_ATBCTL0_SEL_LFMONVTEST 0x00001000U 2505 #define CKMD_ATBCTL0_SEL_LFOSCVDDL 0x00000800U 2506 #define CKMD_ATBCTL0_SEL_HFOSCIBIAS 0x00000400U 2507 #define CKMD_ATBCTL0_SEL_HFOSCVDDL 0x00000200U 2508 #define CKMD_ATBCTL0_SEL_HFOSCVREF 0x00000100U 2509 #define CKMD_ATBCTL0_SEL_NABIASITEST 0x00000080U 2510 #define CKMD_ATBCTL0_SEL_ADCDACOUT 0x00000040U 2511 #define CKMD_ATBCTL0_SEL_ADCCOMPIN 0x00000020U 2512 #define CKMD_ATBCTL0_SEL_ADCCOMPOUT 0x00000010U 2513 #define CKMD_ATBCTL0_SEL_LFXTANA 0x00000008U 2514 #define CKMD_ATBCTL0_SEL_LDOITEST 0x00000004U 2515 #define CKMD_ATBCTL0_SEL_VDDCKM 0x00000002U 2516 #define CKMD_ATBCTL0_SEL_HFXTANA 0x00000001U 2517 #define CKMD_ATBCTL0_SEL_OFF 0x00000000U 2518 2519 //***************************************************************************** 2520 // 2521 // Register: CKMD_O_ATBCTL1 2522 // 2523 //***************************************************************************** 2524 // Field: [14:13] LFOSC 2525 // 2526 // Internal. Only to be used through TI provided API. 2527 // ENUMs: 2528 // BOTH Internal. Only to be used through TI provided API. 2529 // VDDLOCAL Internal. Only to be used through TI provided API. 2530 // TESTCLK Internal. Only to be used through TI provided API. 2531 // OFF Internal. Only to be used through TI provided API. 2532 #define CKMD_ATBCTL1_LFOSC_W 2U 2533 #define CKMD_ATBCTL1_LFOSC_M 0x00006000U 2534 #define CKMD_ATBCTL1_LFOSC_S 13U 2535 #define CKMD_ATBCTL1_LFOSC_BOTH 0x00006000U 2536 #define CKMD_ATBCTL1_LFOSC_VDDLOCAL 0x00004000U 2537 #define CKMD_ATBCTL1_LFOSC_TESTCLK 0x00002000U 2538 #define CKMD_ATBCTL1_LFOSC_OFF 0x00000000U 2539 2540 // Field: [12] NABIAS 2541 // 2542 // Internal. Only to be used through TI provided API. 2543 #define CKMD_ATBCTL1_NABIAS 0x00001000U 2544 #define CKMD_ATBCTL1_NABIAS_M 0x00001000U 2545 #define CKMD_ATBCTL1_NABIAS_S 12U 2546 2547 // Field: [10] LFXT 2548 // 2549 // Internal. Only to be used through TI provided API. 2550 // ENUMs: 2551 // TESTCLK Internal. Only to be used through TI provided API. 2552 // OFF Internal. Only to be used through TI provided API. 2553 #define CKMD_ATBCTL1_LFXT 0x00000400U 2554 #define CKMD_ATBCTL1_LFXT_M 0x00000400U 2555 #define CKMD_ATBCTL1_LFXT_S 10U 2556 #define CKMD_ATBCTL1_LFXT_TESTCLK 0x00000400U 2557 #define CKMD_ATBCTL1_LFXT_OFF 0x00000000U 2558 2559 // Field: [9:8] LFMON 2560 // 2561 // Internal. Only to be used through TI provided API. 2562 // ENUMs: 2563 // TEST2 Internal. Only to be used through TI provided API. 2564 // TEST1 Internal. Only to be used through TI provided API. 2565 // OFF Internal. Only to be used through TI provided API. 2566 #define CKMD_ATBCTL1_LFMON_W 2U 2567 #define CKMD_ATBCTL1_LFMON_M 0x00000300U 2568 #define CKMD_ATBCTL1_LFMON_S 8U 2569 #define CKMD_ATBCTL1_LFMON_TEST2 0x00000200U 2570 #define CKMD_ATBCTL1_LFMON_TEST1 0x00000100U 2571 #define CKMD_ATBCTL1_LFMON_OFF 0x00000000U 2572 2573 // Field: [7] HFXT 2574 // 2575 // Internal. Only to be used through TI provided API. 2576 #define CKMD_ATBCTL1_HFXT 0x00000080U 2577 #define CKMD_ATBCTL1_HFXT_M 0x00000080U 2578 #define CKMD_ATBCTL1_HFXT_S 7U 2579 2580 // Field: [0] HFOSC 2581 // 2582 // Internal. Only to be used through TI provided API. 2583 #define CKMD_ATBCTL1_HFOSC 0x00000001U 2584 #define CKMD_ATBCTL1_HFOSC_M 0x00000001U 2585 #define CKMD_ATBCTL1_HFOSC_S 0U 2586 2587 //***************************************************************************** 2588 // 2589 // Register: CKMD_O_DTBCTL 2590 // 2591 //***************************************************************************** 2592 // Field: [22:18] DSEL2 2593 // 2594 // Internal. Only to be used through TI provided API. 2595 #define CKMD_DTBCTL_DSEL2_W 5U 2596 #define CKMD_DTBCTL_DSEL2_M 0x007C0000U 2597 #define CKMD_DTBCTL_DSEL2_S 18U 2598 2599 // Field: [17:13] DSEL1 2600 // 2601 // Internal. Only to be used through TI provided API. 2602 #define CKMD_DTBCTL_DSEL1_W 5U 2603 #define CKMD_DTBCTL_DSEL1_M 0x0003E000U 2604 #define CKMD_DTBCTL_DSEL1_S 13U 2605 2606 // Field: [12:8] DSEL0 2607 // 2608 // Internal. Only to be used through TI provided API. 2609 #define CKMD_DTBCTL_DSEL0_W 5U 2610 #define CKMD_DTBCTL_DSEL0_M 0x00001F00U 2611 #define CKMD_DTBCTL_DSEL0_S 8U 2612 2613 // Field: [7:4] CLKSEL 2614 // 2615 // Select clock to output on DTB[0] 2616 // ENUMs: 2617 // LFXT Select LFXT 2618 // LFOSC Select LFOSC 2619 // HFXT Select HFXT 2620 // HFXTBY8 Select HFXT divided by 8 2621 // HFOSC Select HFOSC after qualification 2622 // LFCLK Select LFCLK (selected by LFCLKSEL.MAIN) 2623 // TRACKREF Select tracking loop reference clock 2624 // CLKADC Select CLKADC (48 MHz) 2625 // CLKSVT Select CLKSVT (48 MHz) 2626 // CLKULL Select CLKULL (24 MHz during ACTIVE, 32kHz during 2627 // STANDBY) 2628 #define CKMD_DTBCTL_CLKSEL_W 4U 2629 #define CKMD_DTBCTL_CLKSEL_M 0x000000F0U 2630 #define CKMD_DTBCTL_CLKSEL_S 4U 2631 #define CKMD_DTBCTL_CLKSEL_LFXT 0x000000F0U 2632 #define CKMD_DTBCTL_CLKSEL_LFOSC 0x000000E0U 2633 #define CKMD_DTBCTL_CLKSEL_HFXT 0x000000D0U 2634 #define CKMD_DTBCTL_CLKSEL_HFXTBY8 0x000000C0U 2635 #define CKMD_DTBCTL_CLKSEL_HFOSC 0x000000A0U 2636 #define CKMD_DTBCTL_CLKSEL_LFCLK 0x00000070U 2637 #define CKMD_DTBCTL_CLKSEL_TRACKREF 0x00000040U 2638 #define CKMD_DTBCTL_CLKSEL_CLKADC 0x00000020U 2639 #define CKMD_DTBCTL_CLKSEL_CLKSVT 0x00000010U 2640 #define CKMD_DTBCTL_CLKSEL_CLKULL 0x00000000U 2641 2642 // Field: [0] EN 2643 // 2644 // Enable DTB output 2645 #define CKMD_DTBCTL_EN 0x00000001U 2646 #define CKMD_DTBCTL_EN_M 0x00000001U 2647 #define CKMD_DTBCTL_EN_S 0U 2648 2649 //***************************************************************************** 2650 // 2651 // Register: CKMD_O_TRIM0 2652 // 2653 //***************************************************************************** 2654 // Field: [8:5] HFOSC_CAP 2655 // 2656 // Internal. Only to be used through TI provided API. 2657 #define CKMD_TRIM0_HFOSC_CAP_W 4U 2658 #define CKMD_TRIM0_HFOSC_CAP_M 0x000001E0U 2659 #define CKMD_TRIM0_HFOSC_CAP_S 5U 2660 2661 // Field: [4:0] HFOSC_COARSE 2662 // 2663 // Internal. Only to be used through TI provided API. 2664 #define CKMD_TRIM0_HFOSC_COARSE_W 5U 2665 #define CKMD_TRIM0_HFOSC_COARSE_M 0x0000001FU 2666 #define CKMD_TRIM0_HFOSC_COARSE_S 0U 2667 2668 //***************************************************************************** 2669 // 2670 // Register: CKMD_O_TRIM1 2671 // 2672 //***************************************************************************** 2673 // Field: [31:30] HFXTSLICER 2674 // 2675 // Internal. Only to be used through TI provided API. 2676 #define CKMD_TRIM1_HFXTSLICER_W 2U 2677 #define CKMD_TRIM1_HFXTSLICER_M 0xC0000000U 2678 #define CKMD_TRIM1_HFXTSLICER_S 30U 2679 2680 // Field: [29:28] PEAKIBIAS 2681 // 2682 // Internal. Only to be used through TI provided API. 2683 #define CKMD_TRIM1_PEAKIBIAS_W 2U 2684 #define CKMD_TRIM1_PEAKIBIAS_M 0x30000000U 2685 #define CKMD_TRIM1_PEAKIBIAS_S 28U 2686 2687 // Field: [27] NABIAS_UDIGLDO 2688 // 2689 // Internal. Only to be used through TI provided API. 2690 #define CKMD_TRIM1_NABIAS_UDIGLDO 0x08000000U 2691 #define CKMD_TRIM1_NABIAS_UDIGLDO_M 0x08000000U 2692 #define CKMD_TRIM1_NABIAS_UDIGLDO_S 27U 2693 2694 // Field: [26:24] LDOBW 2695 // 2696 // Internal. Only to be used through TI provided API. 2697 #define CKMD_TRIM1_LDOBW_W 3U 2698 #define CKMD_TRIM1_LDOBW_M 0x07000000U 2699 #define CKMD_TRIM1_LDOBW_S 24U 2700 2701 // Field: [23:20] LDOFB 2702 // 2703 // Internal. Only to be used through TI provided API. 2704 #define CKMD_TRIM1_LDOFB_W 4U 2705 #define CKMD_TRIM1_LDOFB_M 0x00F00000U 2706 #define CKMD_TRIM1_LDOFB_S 20U 2707 2708 // Field: [19:16] LFDLY 2709 // 2710 // Internal. Only to be used through TI provided API. 2711 #define CKMD_TRIM1_LFDLY_W 4U 2712 #define CKMD_TRIM1_LFDLY_M 0x000F0000U 2713 #define CKMD_TRIM1_LFDLY_S 16U 2714 2715 // Field: [15] NABIAS_LFOSC 2716 // 2717 // Internal. Only to be used through TI provided API. 2718 #define CKMD_TRIM1_NABIAS_LFOSC 0x00008000U 2719 #define CKMD_TRIM1_NABIAS_LFOSC_M 0x00008000U 2720 #define CKMD_TRIM1_NABIAS_LFOSC_S 15U 2721 2722 // Field: [14:8] NABIAS_RES 2723 // 2724 // Internal. Only to be used through TI provided API. 2725 #define CKMD_TRIM1_NABIAS_RES_W 7U 2726 #define CKMD_TRIM1_NABIAS_RES_M 0x00007F00U 2727 #define CKMD_TRIM1_NABIAS_RES_S 8U 2728 2729 // Field: [7:0] LFOSC_CAP 2730 // 2731 // Internal. Only to be used through TI provided API. 2732 #define CKMD_TRIM1_LFOSC_CAP_W 8U 2733 #define CKMD_TRIM1_LFOSC_CAP_M 0x000000FFU 2734 #define CKMD_TRIM1_LFOSC_CAP_S 0U 2735 2736 //***************************************************************************** 2737 // 2738 // Register: CKMD_O_HFXTINIT 2739 // 2740 //***************************************************************************** 2741 // Field: [29:23] AMPTHR 2742 // 2743 // Amplitude threshold during HFXT ramping 2744 #define CKMD_HFXTINIT_AMPTHR_W 7U 2745 #define CKMD_HFXTINIT_AMPTHR_M 0x3F800000U 2746 #define CKMD_HFXTINIT_AMPTHR_S 23U 2747 2748 // Field: [22:16] IDAC 2749 // 2750 // Initial HFXT IDAC current 2751 #define CKMD_HFXTINIT_IDAC_W 7U 2752 #define CKMD_HFXTINIT_IDAC_M 0x007F0000U 2753 #define CKMD_HFXTINIT_IDAC_S 16U 2754 2755 // Field: [15:12] IREF 2756 // 2757 // Initial HFXT IREF current 2758 #define CKMD_HFXTINIT_IREF_W 4U 2759 #define CKMD_HFXTINIT_IREF_M 0x0000F000U 2760 #define CKMD_HFXTINIT_IREF_S 12U 2761 2762 // Field: [11:6] Q2CAP 2763 // 2764 // Initial HFXT Q2 cap trim 2765 #define CKMD_HFXTINIT_Q2CAP_W 6U 2766 #define CKMD_HFXTINIT_Q2CAP_M 0x00000FC0U 2767 #define CKMD_HFXTINIT_Q2CAP_S 6U 2768 2769 // Field: [5:0] Q1CAP 2770 // 2771 // Initial HFXT Q1 cap trim 2772 #define CKMD_HFXTINIT_Q1CAP_W 6U 2773 #define CKMD_HFXTINIT_Q1CAP_M 0x0000003FU 2774 #define CKMD_HFXTINIT_Q1CAP_S 0U 2775 2776 //***************************************************************************** 2777 // 2778 // Register: CKMD_O_HFXTTARG 2779 // 2780 //***************************************************************************** 2781 // Field: [31:30] AMPHYST 2782 // 2783 // ADC hysteresis used during IDAC updates. 2784 // 2785 // Every AMPCFG1.INTERVAL, IDAC will be regulated 2786 // - up as long as ADC < AMPTHR 2787 // - down as long as ADC > AMPTHR+AMPHYST 2788 #define CKMD_HFXTTARG_AMPHYST_W 2U 2789 #define CKMD_HFXTTARG_AMPHYST_M 0xC0000000U 2790 #define CKMD_HFXTTARG_AMPHYST_S 30U 2791 2792 // Field: [29:23] AMPTHR 2793 // 2794 // Minimum HFXT amplitude 2795 #define CKMD_HFXTTARG_AMPTHR_W 7U 2796 #define CKMD_HFXTTARG_AMPTHR_M 0x3F800000U 2797 #define CKMD_HFXTTARG_AMPTHR_S 23U 2798 2799 // Field: [22:16] IDAC 2800 // 2801 // Minimum IDAC current 2802 #define CKMD_HFXTTARG_IDAC_W 7U 2803 #define CKMD_HFXTTARG_IDAC_M 0x007F0000U 2804 #define CKMD_HFXTTARG_IDAC_S 16U 2805 2806 // Field: [15:12] IREF 2807 // 2808 // Target HFXT IREF current 2809 #define CKMD_HFXTTARG_IREF_W 4U 2810 #define CKMD_HFXTTARG_IREF_M 0x0000F000U 2811 #define CKMD_HFXTTARG_IREF_S 12U 2812 2813 // Field: [11:6] Q2CAP 2814 // 2815 // Target HFXT Q2 cap trim 2816 #define CKMD_HFXTTARG_Q2CAP_W 6U 2817 #define CKMD_HFXTTARG_Q2CAP_M 0x00000FC0U 2818 #define CKMD_HFXTTARG_Q2CAP_S 6U 2819 2820 // Field: [5:0] Q1CAP 2821 // 2822 // Target HFXT Q1 cap trim 2823 #define CKMD_HFXTTARG_Q1CAP_W 6U 2824 #define CKMD_HFXTTARG_Q1CAP_M 0x0000003FU 2825 #define CKMD_HFXTTARG_Q1CAP_S 0U 2826 2827 //***************************************************************************** 2828 // 2829 // Register: CKMD_O_HFXTDYN 2830 // 2831 //***************************************************************************** 2832 // Field: [31] SEL 2833 // 2834 // Select the dynamic configuration. 2835 // 2836 // Amplitude ramping will always happen using the values in HFXTINIT, and 2837 // HFXTTARG. 2838 // Afterwards, this bit can be used to select between HFXTTARG and HFXTDYN. 2839 // Hardware will ensure a smooth transition of analog control signals. 2840 // ENUMs: 2841 // DYNAMIC Select configuration in HFXTDYN. 2842 // TARGET Select configuration in HFXTTARG. 2843 #define CKMD_HFXTDYN_SEL 0x80000000U 2844 #define CKMD_HFXTDYN_SEL_M 0x80000000U 2845 #define CKMD_HFXTDYN_SEL_S 31U 2846 #define CKMD_HFXTDYN_SEL_DYNAMIC 0x80000000U 2847 #define CKMD_HFXTDYN_SEL_TARGET 0x00000000U 2848 2849 // Field: [29:23] AMPTHR 2850 // 2851 // Minimum HFXT amplitude 2852 #define CKMD_HFXTDYN_AMPTHR_W 7U 2853 #define CKMD_HFXTDYN_AMPTHR_M 0x3F800000U 2854 #define CKMD_HFXTDYN_AMPTHR_S 23U 2855 2856 // Field: [22:16] IDAC 2857 // 2858 // Minimum IDAC current 2859 #define CKMD_HFXTDYN_IDAC_W 7U 2860 #define CKMD_HFXTDYN_IDAC_M 0x007F0000U 2861 #define CKMD_HFXTDYN_IDAC_S 16U 2862 2863 // Field: [15:12] IREF 2864 // 2865 // Target HFXT IREF current 2866 #define CKMD_HFXTDYN_IREF_W 4U 2867 #define CKMD_HFXTDYN_IREF_M 0x0000F000U 2868 #define CKMD_HFXTDYN_IREF_S 12U 2869 2870 // Field: [11:6] Q2CAP 2871 // 2872 // Target HFXT Q2 cap trim 2873 #define CKMD_HFXTDYN_Q2CAP_W 6U 2874 #define CKMD_HFXTDYN_Q2CAP_M 0x00000FC0U 2875 #define CKMD_HFXTDYN_Q2CAP_S 6U 2876 2877 // Field: [5:0] Q1CAP 2878 // 2879 // Target HFXT Q1 cap trim 2880 #define CKMD_HFXTDYN_Q1CAP_W 6U 2881 #define CKMD_HFXTDYN_Q1CAP_M 0x0000003FU 2882 #define CKMD_HFXTDYN_Q1CAP_S 0U 2883 2884 //***************************************************************************** 2885 // 2886 // Register: CKMD_O_AMPCFG0 2887 // 2888 //***************************************************************************** 2889 // Field: [31:28] Q2DLY 2890 // 2891 // Q2CAP change delay. 2892 // 2893 // Number of clock cycles to wait before changing Q2CAP by one step. 2894 // Clock frequency defined in FSMRATE. 2895 #define CKMD_AMPCFG0_Q2DLY_W 4U 2896 #define CKMD_AMPCFG0_Q2DLY_M 0xF0000000U 2897 #define CKMD_AMPCFG0_Q2DLY_S 28U 2898 2899 // Field: [27:24] Q1DLY 2900 // 2901 // Q1CAP change delay. 2902 // 2903 // Number of clock cycles to wait before changing Q1CAP by one step. 2904 // Clock frequency defined in FSMRATE. 2905 #define CKMD_AMPCFG0_Q1DLY_W 4U 2906 #define CKMD_AMPCFG0_Q1DLY_M 0x0F000000U 2907 #define CKMD_AMPCFG0_Q1DLY_S 24U 2908 2909 // Field: [23:20] ADCDLY 2910 // 2911 // ADC and PEAKDET startup time. 2912 // 2913 // Number of clock cycles to wait after enabling the PEAKDET and ADC before the 2914 // first measurement. 2915 // Clock frequency defined in FSMRATE. 2916 #define CKMD_AMPCFG0_ADCDLY_W 4U 2917 #define CKMD_AMPCFG0_ADCDLY_M 0x00F00000U 2918 #define CKMD_AMPCFG0_ADCDLY_S 20U 2919 2920 // Field: [19:15] LDOSTART 2921 // 2922 // LDO startup time. 2923 // 2924 // Number of clock cycles to bypass the LDO resistors for faster startup. 2925 // Clock frequency defined in FSMRATE. 2926 #define CKMD_AMPCFG0_LDOSTART_W 5U 2927 #define CKMD_AMPCFG0_LDOSTART_M 0x000F8000U 2928 #define CKMD_AMPCFG0_LDOSTART_S 15U 2929 2930 // Field: [14:10] INJWAIT 2931 // 2932 // Inject HFOSC for faster HFXT startup. 2933 // 2934 // This value specifies the number of clock cycles to wait after injection is 2935 // done. 2936 // The clock speed is defined in FSMRATE. 2937 #define CKMD_AMPCFG0_INJWAIT_W 5U 2938 #define CKMD_AMPCFG0_INJWAIT_M 0x00007C00U 2939 #define CKMD_AMPCFG0_INJWAIT_S 10U 2940 2941 // Field: [9:5] INJTIME 2942 // 2943 // Inject HFOSC for faster HFXT startup. 2944 // 2945 // This value specifies the number of clock cycles the injection is enabled. 2946 // The clock speed is defined in FSMRATE. 2947 // Set to 0 to disable injection. 2948 #define CKMD_AMPCFG0_INJTIME_W 5U 2949 #define CKMD_AMPCFG0_INJTIME_M 0x000003E0U 2950 #define CKMD_AMPCFG0_INJTIME_S 5U 2951 2952 // Field: [4:0] FSMRATE 2953 // 2954 // Update rate for the AMPCOMP update rate. 2955 // Also affects the clock rate for the Amplitude ADC. 2956 // 2957 // The update rate is 6MHz / (FSMRATE+1). 2958 // ENUMs: 2959 // _250K 250 kHz 2960 // _500K 500 kHz 2961 // _1M 1 MHz 2962 // _2M 2 MHz 2963 // _3M 3 MHz 2964 // _6M 6 MHz 2965 #define CKMD_AMPCFG0_FSMRATE_W 5U 2966 #define CKMD_AMPCFG0_FSMRATE_M 0x0000001FU 2967 #define CKMD_AMPCFG0_FSMRATE_S 0U 2968 #define CKMD_AMPCFG0_FSMRATE__250K 0x00000017U 2969 #define CKMD_AMPCFG0_FSMRATE__500K 0x0000000BU 2970 #define CKMD_AMPCFG0_FSMRATE__1M 0x00000005U 2971 #define CKMD_AMPCFG0_FSMRATE__2M 0x00000002U 2972 #define CKMD_AMPCFG0_FSMRATE__3M 0x00000001U 2973 #define CKMD_AMPCFG0_FSMRATE__6M 0x00000000U 2974 2975 //***************************************************************************** 2976 // 2977 // Register: CKMD_O_AMPCFG1 2978 // 2979 //***************************************************************************** 2980 // Field: [31:28] IDACDLY 2981 // 2982 // IDAC change delay. 2983 // 2984 // Time to wait before changing IDAC by one step. 2985 // This time needs to be long enough for the crystal to settle. 2986 // The number of clock cycles to wait is IDACDLY<<4 + 15. 2987 // Clock frequency defined in AMPCFG0.FSMRATE. 2988 #define CKMD_AMPCFG1_IDACDLY_W 4U 2989 #define CKMD_AMPCFG1_IDACDLY_M 0xF0000000U 2990 #define CKMD_AMPCFG1_IDACDLY_S 28U 2991 2992 // Field: [27:24] IREFDLY 2993 // 2994 // IREF change delay. 2995 // 2996 // Number of clock cycles to wait before changing IREF by one step. 2997 // Clock frequency defined in AMPCFG0.FSMRATE. 2998 #define CKMD_AMPCFG1_IREFDLY_W 4U 2999 #define CKMD_AMPCFG1_IREFDLY_M 0x0F000000U 3000 #define CKMD_AMPCFG1_IREFDLY_S 24U 3001 3002 // Field: [23:12] BIASLT 3003 // 3004 // Lifetime of the amplitude ADC bias value. 3005 // This value specifies the number of adjustment intervals, 3006 // until the ADC bias value has to be measured again. 3007 // Set to 0 to disable automatic bias measurements. 3008 #define CKMD_AMPCFG1_BIASLT_W 12U 3009 #define CKMD_AMPCFG1_BIASLT_M 0x00FFF000U 3010 #define CKMD_AMPCFG1_BIASLT_S 12U 3011 3012 // Field: [11:0] INTERVAL 3013 // 3014 // Interval for amplitude adjustments. 3015 // Set to 0 to disable periodic adjustments. 3016 // 3017 // This value specifies the number of clock cycles between adjustments. 3018 // The clock speed is defined in AMPCFG0.FSMRATE. 3019 #define CKMD_AMPCFG1_INTERVAL_W 12U 3020 #define CKMD_AMPCFG1_INTERVAL_M 0x00000FFFU 3021 #define CKMD_AMPCFG1_INTERVAL_S 0U 3022 3023 //***************************************************************************** 3024 // 3025 // Register: CKMD_O_LOOPCFG 3026 // 3027 //***************************************************************************** 3028 // Field: [31:26] FINETRIM_INIT 3029 // 3030 // Initial value for the resistor fine trim 3031 #define CKMD_LOOPCFG_FINETRIM_INIT_W 6U 3032 #define CKMD_LOOPCFG_FINETRIM_INIT_M 0xFC000000U 3033 #define CKMD_LOOPCFG_FINETRIM_INIT_S 26U 3034 3035 // Field: [25:21] BOOST_TARGET 3036 // 3037 // Number of error-updates using BOOST values, before using KI/KP 3038 #define CKMD_LOOPCFG_BOOST_TARGET_W 5U 3039 #define CKMD_LOOPCFG_BOOST_TARGET_M 0x03E00000U 3040 #define CKMD_LOOPCFG_BOOST_TARGET_S 21U 3041 3042 // Field: [20:18] KP_BOOST 3043 // 3044 // Proportional loop coefficient during BOOST 3045 #define CKMD_LOOPCFG_KP_BOOST_W 3U 3046 #define CKMD_LOOPCFG_KP_BOOST_M 0x001C0000U 3047 #define CKMD_LOOPCFG_KP_BOOST_S 18U 3048 3049 // Field: [17:15] KI_BOOST 3050 // 3051 // Integral loop coefficient during BOOST 3052 #define CKMD_LOOPCFG_KI_BOOST_W 3U 3053 #define CKMD_LOOPCFG_KI_BOOST_M 0x00038000U 3054 #define CKMD_LOOPCFG_KI_BOOST_S 15U 3055 3056 // Field: [14:10] SETTLED_TARGET 3057 // 3058 // Number of updates before HFOSC is considered "settled" 3059 #define CKMD_LOOPCFG_SETTLED_TARGET_W 5U 3060 #define CKMD_LOOPCFG_SETTLED_TARGET_M 0x00007C00U 3061 #define CKMD_LOOPCFG_SETTLED_TARGET_S 10U 3062 3063 // Field: [9:6] OOR_LIMIT 3064 // 3065 // Out-of-range threshold 3066 #define CKMD_LOOPCFG_OOR_LIMIT_W 4U 3067 #define CKMD_LOOPCFG_OOR_LIMIT_M 0x000003C0U 3068 #define CKMD_LOOPCFG_OOR_LIMIT_S 6U 3069 3070 // Field: [5:3] KP 3071 // 3072 // Proportional loop coefficient 3073 #define CKMD_LOOPCFG_KP_W 3U 3074 #define CKMD_LOOPCFG_KP_M 0x00000038U 3075 #define CKMD_LOOPCFG_KP_S 3U 3076 3077 // Field: [2:0] KI 3078 // 3079 // Integral loop coefficient 3080 #define CKMD_LOOPCFG_KI_W 3U 3081 #define CKMD_LOOPCFG_KI_M 0x00000007U 3082 #define CKMD_LOOPCFG_KI_S 0U 3083 3084 //***************************************************************************** 3085 // 3086 // Register: CKMD_O_TDCCTL 3087 // 3088 //***************************************************************************** 3089 // Field: [1:0] CMD 3090 // 3091 // Internal. Only to be used through TI provided API. 3092 // ENUMs: 3093 // ABORT Internal. Only to be used through TI provided API. 3094 // RUN Internal. Only to be used through TI provided API. 3095 // RUN_SYNC_START Internal. Only to be used through TI provided API. 3096 // CLR_RESULT Internal. Only to be used through TI provided API. 3097 #define CKMD_TDCCTL_CMD_W 2U 3098 #define CKMD_TDCCTL_CMD_M 0x00000003U 3099 #define CKMD_TDCCTL_CMD_S 0U 3100 #define CKMD_TDCCTL_CMD_ABORT 0x00000003U 3101 #define CKMD_TDCCTL_CMD_RUN 0x00000002U 3102 #define CKMD_TDCCTL_CMD_RUN_SYNC_START 0x00000001U 3103 #define CKMD_TDCCTL_CMD_CLR_RESULT 0x00000000U 3104 3105 //***************************************************************************** 3106 // 3107 // Register: CKMD_O_TDCSTAT 3108 // 3109 //***************************************************************************** 3110 // Field: [9] STOP_BF 3111 // 3112 // Internal. Only to be used through TI provided API. 3113 #define CKMD_TDCSTAT_STOP_BF 0x00000200U 3114 #define CKMD_TDCSTAT_STOP_BF_M 0x00000200U 3115 #define CKMD_TDCSTAT_STOP_BF_S 9U 3116 3117 // Field: [8] START_BF 3118 // 3119 // Internal. Only to be used through TI provided API. 3120 #define CKMD_TDCSTAT_START_BF 0x00000100U 3121 #define CKMD_TDCSTAT_START_BF_M 0x00000100U 3122 #define CKMD_TDCSTAT_START_BF_S 8U 3123 3124 // Field: [7] SAT 3125 // 3126 // Internal. Only to be used through TI provided API. 3127 #define CKMD_TDCSTAT_SAT 0x00000080U 3128 #define CKMD_TDCSTAT_SAT_M 0x00000080U 3129 #define CKMD_TDCSTAT_SAT_S 7U 3130 3131 // Field: [6] DONE 3132 // 3133 // Internal. Only to be used through TI provided API. 3134 #define CKMD_TDCSTAT_DONE 0x00000040U 3135 #define CKMD_TDCSTAT_DONE_M 0x00000040U 3136 #define CKMD_TDCSTAT_DONE_S 6U 3137 3138 // Field: [5:0] STATE 3139 // 3140 // Internal. Only to be used through TI provided API. 3141 // ENUMs: 3142 // FORCE_STOP Internal. Only to be used through TI provided API. 3143 // START_FALL Internal. Only to be used through TI provided API. 3144 // WAIT_CLR_CNT_DONE Internal. Only to be used through TI provided API. 3145 // POR Internal. Only to be used through TI provided API. 3146 // GET_RESULT Internal. Only to be used through TI provided API. 3147 // WAIT_STOP_CNTDWN Internal. Only to be used through TI provided API. 3148 // WAIT_STOP Internal. Only to be used through TI provided API. 3149 // CLR_CNT Internal. Only to be used through TI provided API. 3150 // IDLE Internal. Only to be used through TI provided API. 3151 // WAIT_START_STOP_CNT_EN Internal. Only to be used through TI provided API. 3152 // WAIT_START Internal. Only to be used through TI provided API. 3153 #define CKMD_TDCSTAT_STATE_W 6U 3154 #define CKMD_TDCSTAT_STATE_M 0x0000003FU 3155 #define CKMD_TDCSTAT_STATE_S 0U 3156 #define CKMD_TDCSTAT_STATE_FORCE_STOP 0x0000002EU 3157 #define CKMD_TDCSTAT_STATE_START_FALL 0x0000001EU 3158 #define CKMD_TDCSTAT_STATE_WAIT_CLR_CNT_DONE 0x00000016U 3159 #define CKMD_TDCSTAT_STATE_POR 0x0000000FU 3160 #define CKMD_TDCSTAT_STATE_GET_RESULT 0x0000000EU 3161 #define CKMD_TDCSTAT_STATE_WAIT_STOP_CNTDWN 0x0000000CU 3162 #define CKMD_TDCSTAT_STATE_WAIT_STOP 0x00000008U 3163 #define CKMD_TDCSTAT_STATE_CLR_CNT 0x00000007U 3164 #define CKMD_TDCSTAT_STATE_IDLE 0x00000006U 3165 #define CKMD_TDCSTAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004U 3166 #define CKMD_TDCSTAT_STATE_WAIT_START 0x00000000U 3167 3168 //***************************************************************************** 3169 // 3170 // Register: CKMD_O_TDCRESULT 3171 // 3172 //***************************************************************************** 3173 // Field: [31:0] VALUE 3174 // 3175 // Internal. Only to be used through TI provided API. 3176 #define CKMD_TDCRESULT_VALUE_W 32U 3177 #define CKMD_TDCRESULT_VALUE_M 0xFFFFFFFFU 3178 #define CKMD_TDCRESULT_VALUE_S 0U 3179 3180 //***************************************************************************** 3181 // 3182 // Register: CKMD_O_TDCSATCFG 3183 // 3184 //***************************************************************************** 3185 // Field: [4:0] LIMIT 3186 // 3187 // Internal. Only to be used through TI provided API. 3188 // ENUMs: 3189 // R30 Internal. Only to be used through TI provided API. 3190 // R29 Internal. Only to be used through TI provided API. 3191 // R28 Internal. Only to be used through TI provided API. 3192 // R27 Internal. Only to be used through TI provided API. 3193 // R26 Internal. Only to be used through TI provided API. 3194 // R25 Internal. Only to be used through TI provided API. 3195 // R24 Internal. Only to be used through TI provided API. 3196 // R23 Internal. Only to be used through TI provided API. 3197 // R22 Internal. Only to be used through TI provided API. 3198 // R21 Internal. Only to be used through TI provided API. 3199 // R20 Internal. Only to be used through TI provided API. 3200 // R19 Internal. Only to be used through TI provided API. 3201 // R18 Internal. Only to be used through TI provided API. 3202 // R17 Internal. Only to be used through TI provided API. 3203 // R16 Internal. Only to be used through TI provided API. 3204 // R15 Internal. Only to be used through TI provided API. 3205 // R14 Internal. Only to be used through TI provided API. 3206 // R13 Internal. Only to be used through TI provided API. 3207 // R12 Internal. Only to be used through TI provided API. 3208 // NONE Internal. Only to be used through TI provided API. 3209 #define CKMD_TDCSATCFG_LIMIT_W 5U 3210 #define CKMD_TDCSATCFG_LIMIT_M 0x0000001FU 3211 #define CKMD_TDCSATCFG_LIMIT_S 0U 3212 #define CKMD_TDCSATCFG_LIMIT_R30 0x00000015U 3213 #define CKMD_TDCSATCFG_LIMIT_R29 0x00000014U 3214 #define CKMD_TDCSATCFG_LIMIT_R28 0x00000013U 3215 #define CKMD_TDCSATCFG_LIMIT_R27 0x00000012U 3216 #define CKMD_TDCSATCFG_LIMIT_R26 0x00000011U 3217 #define CKMD_TDCSATCFG_LIMIT_R25 0x00000010U 3218 #define CKMD_TDCSATCFG_LIMIT_R24 0x0000000FU 3219 #define CKMD_TDCSATCFG_LIMIT_R23 0x0000000EU 3220 #define CKMD_TDCSATCFG_LIMIT_R22 0x0000000DU 3221 #define CKMD_TDCSATCFG_LIMIT_R21 0x0000000CU 3222 #define CKMD_TDCSATCFG_LIMIT_R20 0x0000000BU 3223 #define CKMD_TDCSATCFG_LIMIT_R19 0x0000000AU 3224 #define CKMD_TDCSATCFG_LIMIT_R18 0x00000009U 3225 #define CKMD_TDCSATCFG_LIMIT_R17 0x00000008U 3226 #define CKMD_TDCSATCFG_LIMIT_R16 0x00000007U 3227 #define CKMD_TDCSATCFG_LIMIT_R15 0x00000006U 3228 #define CKMD_TDCSATCFG_LIMIT_R14 0x00000005U 3229 #define CKMD_TDCSATCFG_LIMIT_R13 0x00000004U 3230 #define CKMD_TDCSATCFG_LIMIT_R12 0x00000003U 3231 #define CKMD_TDCSATCFG_LIMIT_NONE 0x00000000U 3232 3233 //***************************************************************************** 3234 // 3235 // Register: CKMD_O_TDCTRIGSRC 3236 // 3237 //***************************************************************************** 3238 // Field: [15] STOP_POL 3239 // 3240 // Internal. Only to be used through TI provided API. 3241 // ENUMs: 3242 // LOW Internal. Only to be used through TI provided API. 3243 // HIGH Internal. Only to be used through TI provided API. 3244 #define CKMD_TDCTRIGSRC_STOP_POL 0x00008000U 3245 #define CKMD_TDCTRIGSRC_STOP_POL_M 0x00008000U 3246 #define CKMD_TDCTRIGSRC_STOP_POL_S 15U 3247 #define CKMD_TDCTRIGSRC_STOP_POL_LOW 0x00008000U 3248 #define CKMD_TDCTRIGSRC_STOP_POL_HIGH 0x00000000U 3249 3250 // Field: [12:8] STOP_SRC 3251 // 3252 // Internal. Only to be used through TI provided API. 3253 // ENUMs: 3254 // TDC_PRE Internal. Only to be used through TI provided API. 3255 // DTB15 Internal. Only to be used through TI provided API. 3256 // DTB14 Internal. Only to be used through TI provided API. 3257 // DTB13 Internal. Only to be used through TI provided API. 3258 // DTB12 Internal. Only to be used through TI provided API. 3259 // DTB11 Internal. Only to be used through TI provided API. 3260 // DTB10 Internal. Only to be used through TI provided API. 3261 // DTB9 Internal. Only to be used through TI provided API. 3262 // DTB8 Internal. Only to be used through TI provided API. 3263 // DTB7 Internal. Only to be used through TI provided API. 3264 // DTB6 Internal. Only to be used through TI provided API. 3265 // DTB5 Internal. Only to be used through TI provided API. 3266 // DTB4 Internal. Only to be used through TI provided API. 3267 // DTB3 Internal. Only to be used through TI provided API. 3268 // DTB2 Internal. Only to be used through TI provided API. 3269 // DTB1 Internal. Only to be used through TI provided API. 3270 // DTB0 Internal. Only to be used through TI provided API. 3271 // GPI Internal. Only to be used through TI provided API. 3272 // LFCLK_DLY Internal. Only to be used through TI provided API. 3273 // LFXT Internal. Only to be used through TI provided API. 3274 // LFOSC Internal. Only to be used through TI provided API. 3275 // LFTICK Internal. Only to be used through TI provided API. 3276 #define CKMD_TDCTRIGSRC_STOP_SRC_W 5U 3277 #define CKMD_TDCTRIGSRC_STOP_SRC_M 0x00001F00U 3278 #define CKMD_TDCTRIGSRC_STOP_SRC_S 8U 3279 #define CKMD_TDCTRIGSRC_STOP_SRC_TDC_PRE 0x00001F00U 3280 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB15 0x00001400U 3281 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB14 0x00001300U 3282 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB13 0x00001200U 3283 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB12 0x00001100U 3284 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB11 0x00001000U 3285 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB10 0x00000F00U 3286 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB9 0x00000E00U 3287 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB8 0x00000D00U 3288 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB7 0x00000C00U 3289 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB6 0x00000B00U 3290 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB5 0x00000A00U 3291 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB4 0x00000900U 3292 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB3 0x00000800U 3293 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB2 0x00000700U 3294 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB1 0x00000600U 3295 #define CKMD_TDCTRIGSRC_STOP_SRC_DTB0 0x00000500U 3296 #define CKMD_TDCTRIGSRC_STOP_SRC_GPI 0x00000400U 3297 #define CKMD_TDCTRIGSRC_STOP_SRC_LFCLK_DLY 0x00000300U 3298 #define CKMD_TDCTRIGSRC_STOP_SRC_LFXT 0x00000200U 3299 #define CKMD_TDCTRIGSRC_STOP_SRC_LFOSC 0x00000100U 3300 #define CKMD_TDCTRIGSRC_STOP_SRC_LFTICK 0x00000000U 3301 3302 // Field: [7] START_POL 3303 // 3304 // Internal. Only to be used through TI provided API. 3305 // ENUMs: 3306 // LOW Internal. Only to be used through TI provided API. 3307 // HIGH Internal. Only to be used through TI provided API. 3308 #define CKMD_TDCTRIGSRC_START_POL 0x00000080U 3309 #define CKMD_TDCTRIGSRC_START_POL_M 0x00000080U 3310 #define CKMD_TDCTRIGSRC_START_POL_S 7U 3311 #define CKMD_TDCTRIGSRC_START_POL_LOW 0x00000080U 3312 #define CKMD_TDCTRIGSRC_START_POL_HIGH 0x00000000U 3313 3314 // Field: [4:0] START_SRC 3315 // 3316 // Internal. Only to be used through TI provided API. 3317 // ENUMs: 3318 // TDC_PRE Internal. Only to be used through TI provided API. 3319 // DTB15 Internal. Only to be used through TI provided API. 3320 // DTB14 Internal. Only to be used through TI provided API. 3321 // DTB13 Internal. Only to be used through TI provided API. 3322 // DTB12 Internal. Only to be used through TI provided API. 3323 // DTB11 Internal. Only to be used through TI provided API. 3324 // DTB10 Internal. Only to be used through TI provided API. 3325 // DTB9 Internal. Only to be used through TI provided API. 3326 // DTB8 Internal. Only to be used through TI provided API. 3327 // DTB7 Internal. Only to be used through TI provided API. 3328 // DTB6 Internal. Only to be used through TI provided API. 3329 // DTB5 Internal. Only to be used through TI provided API. 3330 // DTB4 Internal. Only to be used through TI provided API. 3331 // DTB3 Internal. Only to be used through TI provided API. 3332 // DTB2 Internal. Only to be used through TI provided API. 3333 // DTB1 Internal. Only to be used through TI provided API. 3334 // DTB0 Internal. Only to be used through TI provided API. 3335 // GPI Internal. Only to be used through TI provided API. 3336 // LFCLK_DLY Internal. Only to be used through TI provided API. 3337 // LFXT Internal. Only to be used through TI provided API. 3338 // LFOSC Internal. Only to be used through TI provided API. 3339 // LFTICK Internal. Only to be used through TI provided API. 3340 #define CKMD_TDCTRIGSRC_START_SRC_W 5U 3341 #define CKMD_TDCTRIGSRC_START_SRC_M 0x0000001FU 3342 #define CKMD_TDCTRIGSRC_START_SRC_S 0U 3343 #define CKMD_TDCTRIGSRC_START_SRC_TDC_PRE 0x0000001FU 3344 #define CKMD_TDCTRIGSRC_START_SRC_DTB15 0x00000014U 3345 #define CKMD_TDCTRIGSRC_START_SRC_DTB14 0x00000013U 3346 #define CKMD_TDCTRIGSRC_START_SRC_DTB13 0x00000012U 3347 #define CKMD_TDCTRIGSRC_START_SRC_DTB12 0x00000011U 3348 #define CKMD_TDCTRIGSRC_START_SRC_DTB11 0x00000010U 3349 #define CKMD_TDCTRIGSRC_START_SRC_DTB10 0x0000000FU 3350 #define CKMD_TDCTRIGSRC_START_SRC_DTB9 0x0000000EU 3351 #define CKMD_TDCTRIGSRC_START_SRC_DTB8 0x0000000DU 3352 #define CKMD_TDCTRIGSRC_START_SRC_DTB7 0x0000000CU 3353 #define CKMD_TDCTRIGSRC_START_SRC_DTB6 0x0000000BU 3354 #define CKMD_TDCTRIGSRC_START_SRC_DTB5 0x0000000AU 3355 #define CKMD_TDCTRIGSRC_START_SRC_DTB4 0x00000009U 3356 #define CKMD_TDCTRIGSRC_START_SRC_DTB3 0x00000008U 3357 #define CKMD_TDCTRIGSRC_START_SRC_DTB2 0x00000007U 3358 #define CKMD_TDCTRIGSRC_START_SRC_DTB1 0x00000006U 3359 #define CKMD_TDCTRIGSRC_START_SRC_DTB0 0x00000005U 3360 #define CKMD_TDCTRIGSRC_START_SRC_GPI 0x00000004U 3361 #define CKMD_TDCTRIGSRC_START_SRC_LFCLK_DLY 0x00000003U 3362 #define CKMD_TDCTRIGSRC_START_SRC_LFXT 0x00000002U 3363 #define CKMD_TDCTRIGSRC_START_SRC_LFOSC 0x00000001U 3364 #define CKMD_TDCTRIGSRC_START_SRC_LFTICK 0x00000000U 3365 3366 //***************************************************************************** 3367 // 3368 // Register: CKMD_O_TDCTRIGCNT 3369 // 3370 //***************************************************************************** 3371 // Field: [15:0] CNT 3372 // 3373 // Internal. Only to be used through TI provided API. 3374 #define CKMD_TDCTRIGCNT_CNT_W 16U 3375 #define CKMD_TDCTRIGCNT_CNT_M 0x0000FFFFU 3376 #define CKMD_TDCTRIGCNT_CNT_S 0U 3377 3378 //***************************************************************************** 3379 // 3380 // Register: CKMD_O_TDCTRIGCNTLOAD 3381 // 3382 //***************************************************************************** 3383 // Field: [15:0] CNT 3384 // 3385 // Internal. Only to be used through TI provided API. 3386 #define CKMD_TDCTRIGCNTLOAD_CNT_W 16U 3387 #define CKMD_TDCTRIGCNTLOAD_CNT_M 0x0000FFFFU 3388 #define CKMD_TDCTRIGCNTLOAD_CNT_S 0U 3389 3390 //***************************************************************************** 3391 // 3392 // Register: CKMD_O_TDCTRIGCNTCFG 3393 // 3394 //***************************************************************************** 3395 // Field: [0] EN 3396 // 3397 // Internal. Only to be used through TI provided API. 3398 #define CKMD_TDCTRIGCNTCFG_EN 0x00000001U 3399 #define CKMD_TDCTRIGCNTCFG_EN_M 0x00000001U 3400 #define CKMD_TDCTRIGCNTCFG_EN_S 0U 3401 3402 //***************************************************************************** 3403 // 3404 // Register: CKMD_O_TDCPRECTL 3405 // 3406 //***************************************************************************** 3407 // Field: [7] RESET_N 3408 // 3409 // Internal. Only to be used through TI provided API. 3410 #define CKMD_TDCPRECTL_RESET_N 0x00000080U 3411 #define CKMD_TDCPRECTL_RESET_N_M 0x00000080U 3412 #define CKMD_TDCPRECTL_RESET_N_S 7U 3413 3414 // Field: [6] RATIO 3415 // 3416 // Internal. Only to be used through TI provided API. 3417 // ENUMs: 3418 // DIV64 Internal. Only to be used through TI provided API. 3419 // DIV16 Internal. Only to be used through TI provided API. 3420 #define CKMD_TDCPRECTL_RATIO 0x00000040U 3421 #define CKMD_TDCPRECTL_RATIO_M 0x00000040U 3422 #define CKMD_TDCPRECTL_RATIO_S 6U 3423 #define CKMD_TDCPRECTL_RATIO_DIV64 0x00000040U 3424 #define CKMD_TDCPRECTL_RATIO_DIV16 0x00000000U 3425 3426 // Field: [4:0] SRC 3427 // 3428 // Internal. Only to be used through TI provided API. 3429 // ENUMs: 3430 // HFXT Internal. Only to be used through TI provided API. 3431 // HFOSC Internal. Only to be used through TI provided API. 3432 // DTB15 Internal. Only to be used through TI provided API. 3433 // DTB14 Internal. Only to be used through TI provided API. 3434 // DTB13 Internal. Only to be used through TI provided API. 3435 // DTB12 Internal. Only to be used through TI provided API. 3436 // DTB11 Internal. Only to be used through TI provided API. 3437 // DTB10 Internal. Only to be used through TI provided API. 3438 // DTB9 Internal. Only to be used through TI provided API. 3439 // DTB8 Internal. Only to be used through TI provided API. 3440 // DTB7 Internal. Only to be used through TI provided API. 3441 // DTB6 Internal. Only to be used through TI provided API. 3442 // DTB5 Internal. Only to be used through TI provided API. 3443 // DTB4 Internal. Only to be used through TI provided API. 3444 // DTB3 Internal. Only to be used through TI provided API. 3445 // DTB2 Internal. Only to be used through TI provided API. 3446 // DTB1 Internal. Only to be used through TI provided API. 3447 // DTB0 Internal. Only to be used through TI provided API. 3448 // GPI Internal. Only to be used through TI provided API. 3449 // LFCLK_DLY Internal. Only to be used through TI provided API. 3450 // LFXT Internal. Only to be used through TI provided API. 3451 // LFOSC Internal. Only to be used through TI provided API. 3452 // LFTICK Internal. Only to be used through TI provided API. 3453 #define CKMD_TDCPRECTL_SRC_W 5U 3454 #define CKMD_TDCPRECTL_SRC_M 0x0000001FU 3455 #define CKMD_TDCPRECTL_SRC_S 0U 3456 #define CKMD_TDCPRECTL_SRC_HFXT 0x00000016U 3457 #define CKMD_TDCPRECTL_SRC_HFOSC 0x00000015U 3458 #define CKMD_TDCPRECTL_SRC_DTB15 0x00000014U 3459 #define CKMD_TDCPRECTL_SRC_DTB14 0x00000013U 3460 #define CKMD_TDCPRECTL_SRC_DTB13 0x00000012U 3461 #define CKMD_TDCPRECTL_SRC_DTB12 0x00000011U 3462 #define CKMD_TDCPRECTL_SRC_DTB11 0x00000010U 3463 #define CKMD_TDCPRECTL_SRC_DTB10 0x0000000FU 3464 #define CKMD_TDCPRECTL_SRC_DTB9 0x0000000EU 3465 #define CKMD_TDCPRECTL_SRC_DTB8 0x0000000DU 3466 #define CKMD_TDCPRECTL_SRC_DTB7 0x0000000CU 3467 #define CKMD_TDCPRECTL_SRC_DTB6 0x0000000BU 3468 #define CKMD_TDCPRECTL_SRC_DTB5 0x0000000AU 3469 #define CKMD_TDCPRECTL_SRC_DTB4 0x00000009U 3470 #define CKMD_TDCPRECTL_SRC_DTB3 0x00000008U 3471 #define CKMD_TDCPRECTL_SRC_DTB2 0x00000007U 3472 #define CKMD_TDCPRECTL_SRC_DTB1 0x00000006U 3473 #define CKMD_TDCPRECTL_SRC_DTB0 0x00000005U 3474 #define CKMD_TDCPRECTL_SRC_GPI 0x00000004U 3475 #define CKMD_TDCPRECTL_SRC_LFCLK_DLY 0x00000003U 3476 #define CKMD_TDCPRECTL_SRC_LFXT 0x00000002U 3477 #define CKMD_TDCPRECTL_SRC_LFOSC 0x00000001U 3478 #define CKMD_TDCPRECTL_SRC_LFTICK 0x00000000U 3479 3480 //***************************************************************************** 3481 // 3482 // Register: CKMD_O_TDCPRECNTR 3483 // 3484 //***************************************************************************** 3485 // Field: [16] CAPT 3486 // 3487 // Internal. Only to be used through TI provided API. 3488 #define CKMD_TDCPRECNTR_CAPT 0x00010000U 3489 #define CKMD_TDCPRECNTR_CAPT_M 0x00010000U 3490 #define CKMD_TDCPRECNTR_CAPT_S 16U 3491 3492 // Field: [15:0] CNT 3493 // 3494 // Internal. Only to be used through TI provided API. 3495 #define CKMD_TDCPRECNTR_CNT_W 16U 3496 #define CKMD_TDCPRECNTR_CNT_M 0x0000FFFFU 3497 #define CKMD_TDCPRECNTR_CNT_S 0U 3498 3499 //***************************************************************************** 3500 // 3501 // Register: CKMD_O_WDTCNT 3502 // 3503 //***************************************************************************** 3504 // Field: [31:0] VAL 3505 // 3506 // Counter value. 3507 // 3508 // A write to this field immediately starts (or restarts) the counter. It will 3509 // count down from the written value. 3510 // If the counter reaches 0, a reset will be generated. 3511 // A write value of 0 immediately generates a reset. 3512 // 3513 // This field is only writable if not locked. See WDTLOCK register. 3514 // Writing this field will automatically activate the lock. 3515 // 3516 // A read returns the current value of the counter. 3517 #define CKMD_WDTCNT_VAL_W 32U 3518 #define CKMD_WDTCNT_VAL_M 0xFFFFFFFFU 3519 #define CKMD_WDTCNT_VAL_S 0U 3520 3521 //***************************************************************************** 3522 // 3523 // Register: CKMD_O_WDTTEST 3524 // 3525 //***************************************************************************** 3526 // Field: [0] STALLEN 3527 // 3528 // WDT stall enable 3529 // 3530 // This field is only writable if not locked. See WDTLOCK register. 3531 // ENUMs: 3532 // EN ENABLE 3533 // 3534 // WDT stops counting while 3535 // the CPU is stopped by a debugger. 3536 // DIS DISABLE 3537 // 3538 // WDT continues counting 3539 // while the CPU is stopped by a debugger. 3540 #define CKMD_WDTTEST_STALLEN 0x00000001U 3541 #define CKMD_WDTTEST_STALLEN_M 0x00000001U 3542 #define CKMD_WDTTEST_STALLEN_S 0U 3543 #define CKMD_WDTTEST_STALLEN_EN 0x00000001U 3544 #define CKMD_WDTTEST_STALLEN_DIS 0x00000000U 3545 3546 //***************************************************************************** 3547 // 3548 // Register: CKMD_O_WDTLOCK 3549 // 3550 //***************************************************************************** 3551 // Field: [31:0] STAT 3552 // 3553 // A write with value 0x1ACCE551 unlocks the watchdog registers for write 3554 // access. 3555 // A write with any other value locks the watchdog registers for write access. 3556 // Writing the WDTCNT register will also lock the watchdog registers. 3557 // 3558 // A read of this field returns the state of the lock (0=unlocked, 1=locked). 3559 #define CKMD_WDTLOCK_STAT_W 32U 3560 #define CKMD_WDTLOCK_STAT_M 0xFFFFFFFFU 3561 #define CKMD_WDTLOCK_STAT_S 0U 3562 3563 3564 #endif // __CKMD__ 3565
