1 /****************************************************************************** 2 * Filename: hw_aes_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_AES_H__ 34 #define __HW_AES_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // AES component 40 // 41 //***************************************************************************** 42 // Description Register. 43 #define AES_O_DESC 0x00000000U 44 45 // Trigger 46 #define AES_O_TRG 0x00000010U 47 48 // Abort 49 #define AES_O_ABORT 0x00000014U 50 51 // Clear 52 #define AES_O_CLR 0x00000018U 53 54 // Status 55 #define AES_O_STA 0x0000001CU 56 57 // Direct Memory Access 58 #define AES_O_DMA 0x00000020U 59 60 // DMA Channel A data transfer 61 #define AES_O_DMACHA 0x00000024U 62 63 // DMA Channel B data transfer 64 #define AES_O_DMACHB 0x00000028U 65 66 // Automatic Configuration 67 #define AES_O_AUTOCFG 0x0000002CU 68 69 // Key Word 0 70 #define AES_O_KEY0 0x00000050U 71 72 // Key Word 1 73 #define AES_O_KEY1 0x00000054U 74 75 // Key Word 2 76 #define AES_O_KEY2 0x00000058U 77 78 // Key Word 3 79 #define AES_O_KEY3 0x0000005CU 80 81 // Text Word 0 82 #define AES_O_TXT0 0x00000070U 83 84 // Text Word 1 85 #define AES_O_TXT1 0x00000074U 86 87 // Text Word 2 88 #define AES_O_TXT2 0x00000078U 89 90 // Text Word 3 91 #define AES_O_TXT3 0x0000007CU 92 93 // Text Word 0 XOR 94 #define AES_O_TXTX0 0x00000080U 95 96 // Text Word 1 XOR 97 #define AES_O_TXTX1 0x00000084U 98 99 // Text Word 2 XOR 100 #define AES_O_TXTX2 0x00000088U 101 102 // Text Word 3 XOR 103 #define AES_O_TXTX3 0x0000008CU 104 105 // Buffer Word 0 106 #define AES_O_BUF0 0x00000090U 107 108 // Buffer Word 1 109 #define AES_O_BUF1 0x00000094U 110 111 // Buffer Word 2 112 #define AES_O_BUF2 0x00000098U 113 114 // Buffer Word 3 115 #define AES_O_BUF3 0x0000009CU 116 117 // Text Word 0 XOR Buffer Word 0 118 #define AES_O_TXTXBUF0 0x000000A0U 119 120 // Text Word 1 XOR Buffer Word 1 121 #define AES_O_TXTXBUF1 0x000000A4U 122 123 // Text Word 2 XOR Buffer Word 2 124 #define AES_O_TXTXBUF2 0x000000A8U 125 126 // Text Word 3 XOR Buffer Word3 127 #define AES_O_TXTXBUF3 0x000000ACU 128 129 // Interrupt Mask register 130 #define AES_O_IMASK 0x00000104U 131 132 // Raw Interrupt Status register 133 #define AES_O_RIS 0x00000108U 134 135 // Masked Interrupt Status register 136 #define AES_O_MIS 0x0000010CU 137 138 // Interrupt Set register 139 #define AES_O_ISET 0x00000110U 140 141 // Interrupt Clear register 142 #define AES_O_ICLR 0x00000114U 143 144 // Interrupt Mask Set register 145 #define AES_O_IMSET 0x00000118U 146 147 // Interrupt Mask Clear register 148 #define AES_O_IMCLR 0x0000011CU 149 150 //***************************************************************************** 151 // 152 // Register: AES_O_DESC 153 // 154 //***************************************************************************** 155 // Field: [31:16] MODID 156 // 157 // Module Identifier 158 // This register is used to uniquely identify this IP. 159 #define AES_DESC_MODID_W 16U 160 #define AES_DESC_MODID_M 0xFFFF0000U 161 #define AES_DESC_MODID_S 16U 162 163 // Field: [15:12] STDIPOFF 164 // 165 // Standard IP MMR block offset 166 // Standard IP MMRs are the set from aggregated IRQ registers till DTB. 167 // 168 // 0: Standard IP MMRs do not exist. 169 // 170 // 0x1-0xF: Standard IP MMRs begin at offset of 64*STDIPOFF from the base IP 171 // address. 172 #define AES_DESC_STDIPOFF_W 4U 173 #define AES_DESC_STDIPOFF_M 0x0000F000U 174 #define AES_DESC_STDIPOFF_S 12U 175 176 // Field: [11:8] INSTIDX 177 // 178 // IP Instance ID number 179 // If multiple instances of IP exist in the device, this field can 180 // identify the instance number (0-15). 181 #define AES_DESC_INSTIDX_W 4U 182 #define AES_DESC_INSTIDX_M 0x00000F00U 183 #define AES_DESC_INSTIDX_S 8U 184 185 // Field: [7:4] MAJREV 186 // 187 // Major revision of IP (0-15) 188 #define AES_DESC_MAJREV_W 4U 189 #define AES_DESC_MAJREV_M 0x000000F0U 190 #define AES_DESC_MAJREV_S 4U 191 192 // Field: [3:0] MINREV 193 // 194 // Minor Revision of IP(0-15) 195 #define AES_DESC_MINREV_W 4U 196 #define AES_DESC_MINREV_M 0x0000000FU 197 #define AES_DESC_MINREV_S 0U 198 199 //***************************************************************************** 200 // 201 // Register: AES_O_TRG 202 // 203 //***************************************************************************** 204 // Field: [3] DMACHA 205 // 206 // Manually trigger channel A request 207 // ENUMs: 208 // SET Triggers channel A request 209 // NOEFF Writing 0 has no effect 210 #define AES_TRG_DMACHA 0x00000008U 211 #define AES_TRG_DMACHA_M 0x00000008U 212 #define AES_TRG_DMACHA_S 3U 213 #define AES_TRG_DMACHA_SET 0x00000008U 214 #define AES_TRG_DMACHA_NOEFF 0x00000000U 215 216 // Field: [2] DMACHB 217 // 218 // Manually trigger channel B request 219 // ENUMs: 220 // SET Triggers channel B request 221 // NOEFF Writing 0 has no effect 222 #define AES_TRG_DMACHB 0x00000004U 223 #define AES_TRG_DMACHB_M 0x00000004U 224 #define AES_TRG_DMACHB_S 2U 225 #define AES_TRG_DMACHB_SET 0x00000004U 226 #define AES_TRG_DMACHB_NOEFF 0x00000000U 227 228 // Field: [1:0] AESOP 229 // 230 // AES Operation 231 // 232 // Write an enumerated value to this field when STA.STATE = IDLE to manually 233 // trigger an AES operation. If condition is not met, the trigger is ignored. 234 // Non-enumerated values are ignored. 235 // Enumerated value indicates source of AES operation 236 // ENUMs: 237 // TXTXBUF TXT = AES(KEY, TXT XOR BUF) 238 // BUF TXT = AES(KEY,BUF) 239 // TXT TXT = AES(KEY,TXT) 240 #define AES_TRG_AESOP_W 2U 241 #define AES_TRG_AESOP_M 0x00000003U 242 #define AES_TRG_AESOP_S 0U 243 #define AES_TRG_AESOP_TXTXBUF 0x00000003U 244 #define AES_TRG_AESOP_BUF 0x00000002U 245 #define AES_TRG_AESOP_TXT 0x00000001U 246 247 //***************************************************************************** 248 // 249 // Register: AES_O_ABORT 250 // 251 //***************************************************************************** 252 // Field: [0] ABORTAES 253 // 254 // Abort AES operation 255 // 256 // Abort an ongoing AES operation. An abort will clear TXT, BUF, DMA, AUTOCFG 257 // registers 258 // ENUMs: 259 // SET Aborts an ongoing AES operation 260 // NOEFF Writing 0 has no effect 261 #define AES_ABORT_ABORTAES 0x00000001U 262 #define AES_ABORT_ABORTAES_M 0x00000001U 263 #define AES_ABORT_ABORTAES_S 0U 264 #define AES_ABORT_ABORTAES_SET 0x00000001U 265 #define AES_ABORT_ABORTAES_NOEFF 0x00000000U 266 267 //***************************************************************************** 268 // 269 // Register: AES_O_CLR 270 // 271 //***************************************************************************** 272 // Field: [1] TXT 273 // 274 // Clear TXT 275 // ENUMs: 276 // CLR Clears TXT 277 // NOEFF Writing 0 has no effect 278 #define AES_CLR_TXT 0x00000002U 279 #define AES_CLR_TXT_M 0x00000002U 280 #define AES_CLR_TXT_S 1U 281 #define AES_CLR_TXT_CLR 0x00000002U 282 #define AES_CLR_TXT_NOEFF 0x00000000U 283 284 // Field: [0] BUF 285 // 286 // Clear BUF 287 // ENUMs: 288 // CLR Clears BUF 289 // NOEFF Writing 0 has no effect 290 #define AES_CLR_BUF 0x00000001U 291 #define AES_CLR_BUF_M 0x00000001U 292 #define AES_CLR_BUF_S 0U 293 #define AES_CLR_BUF_CLR 0x00000001U 294 #define AES_CLR_BUF_NOEFF 0x00000000U 295 296 //***************************************************************************** 297 // 298 // Register: AES_O_STA 299 // 300 //***************************************************************************** 301 // Field: [1] BUFSTA 302 // 303 // BUF Status 304 // 305 // Field gives the status of BUF, indicating EMPTY or FULL, when AUTOCFG.TRGAES 306 // = WRBUF3. 307 // If AUTOCFG.TRGAES != WRBUF3, then STA.BUFSTA will hold the value 0. 308 // Note : Useful for CBC-MAC 309 // ENUMs: 310 // FULL Data stored in BUF is not yet consumed by the AES 311 // engine. Next block of data cannot be written 312 // into BUF until STA.STATE = IDLE. 313 // EMPTY Data stored in BUF is already consumed by the AES 314 // engine and next block of data can be written in 315 // BUF. 316 #define AES_STA_BUFSTA 0x00000002U 317 #define AES_STA_BUFSTA_M 0x00000002U 318 #define AES_STA_BUFSTA_S 1U 319 #define AES_STA_BUFSTA_FULL 0x00000002U 320 #define AES_STA_BUFSTA_EMPTY 0x00000000U 321 322 // Field: [0] STATE 323 // 324 // State 325 // 326 // Field gives the state of the AES engine. 327 // ENUMs: 328 // BUSY AES operation active 329 // IDLE AES engine is IDLE 330 #define AES_STA_STATE 0x00000001U 331 #define AES_STA_STATE_M 0x00000001U 332 #define AES_STA_STATE_S 0U 333 #define AES_STA_STATE_BUSY 0x00000001U 334 #define AES_STA_STATE_IDLE 0x00000000U 335 336 //***************************************************************************** 337 // 338 // Register: AES_O_DMA 339 // 340 //***************************************************************************** 341 // Field: [19:16] DONEACT 342 // 343 // Done Action 344 // 345 // This field determines the side effects of DMA done. It is allowed to 346 // configure this field with an OR-combination of supported enums, with the 347 // exception that GATE_TRGAES_ON_CHA and GATE_TRGAES_ON_CHA_DEL must be 348 // mutually exclusive 349 // ENUMs: 350 // CLR_TXT_ON_CHB DMA channel B done event clears TXT0 thru TXT3 if 351 // STA.STATE = IDLE. Event is ignored if condition 352 // is not met. 353 // CLR_TXT_ON_CHA DMA channel A done event clears TXT0 thru TXT3 if 354 // STA.STATE = IDLE. Event is ignored if condition 355 // is not met. 356 // GATE_TRGAES_ON_CHA_DEL Delayed gating of triggers defined in 357 // AUTOCFG.TRGAES 358 // Due to the pipelining 359 // of BUF writes, in certain modes, DMA CHA Done 360 // appears before the last but one AES operation 361 // has completed. Setting this bit, will gate the 362 // triggers defined in AUTOCFG.TRGAES only after 363 // the last write by CHA is consumed by AES FSM. 364 // Used in ECB,CBC,CBC-MAC modes (having multiple 365 // blocks encryption/decryption) to avoid spurious 366 // AES operation triggered on last read by CHB. 367 // For single mode operation, 368 // DMA.GATE_TRGAES_ON_CHA must be used. 369 // GATE_TRGAES_ON_CHA Triggers defined in AUTOCFG.TRGAES are gated when 370 // RIS.CHADONE = SET 371 // DIS DMA done has no side effect 372 #define AES_DMA_DONEACT_W 4U 373 #define AES_DMA_DONEACT_M 0x000F0000U 374 #define AES_DMA_DONEACT_S 16U 375 #define AES_DMA_DONEACT_CLR_TXT_ON_CHB 0x00080000U 376 #define AES_DMA_DONEACT_CLR_TXT_ON_CHA 0x00040000U 377 #define AES_DMA_DONEACT_GATE_TRGAES_ON_CHA_DEL 0x00020000U 378 #define AES_DMA_DONEACT_GATE_TRGAES_ON_CHA 0x00010000U 379 #define AES_DMA_DONEACT_DIS 0x00000000U 380 381 // Field: [13:12] ADRCHB 382 // 383 // Channel B Read Write Address 384 // 385 // The DMA accesses DMACHB to read or write contents of TXT and BUF as a 386 // response to a burst request. This field specifes the start address of the 387 // first DMA transfer that follows the burst request. The internal address gets 388 // incremented automatically for subsequent accesses. The DMA can transfer 389 // 8-bit, 16-bit, or 32-bit words, and must always complete a 16-byte transfer 390 // before re-arbitration. 391 // ENUMs: 392 // TXTXBUF0 Start address is TXTXBUF0 393 // BUF0 Start address is BUF0 394 // TXTX0 Start address is TXTX0 395 // TXT0 Start address is TXT0 396 #define AES_DMA_ADRCHB_W 2U 397 #define AES_DMA_ADRCHB_M 0x00003000U 398 #define AES_DMA_ADRCHB_S 12U 399 #define AES_DMA_ADRCHB_TXTXBUF0 0x00003000U 400 #define AES_DMA_ADRCHB_BUF0 0x00002000U 401 #define AES_DMA_ADRCHB_TXTX0 0x00001000U 402 #define AES_DMA_ADRCHB_TXT0 0x00000000U 403 404 // Field: [10:8] TRGCHB 405 // 406 // Channel B Trigger 407 // 408 // Select the condition that triggers DMA channel B request. Non-enumerated 409 // values are not supported and ignored. 410 // ENUMs: 411 // RDTXT3 Reads of TXT3, or TXTXBUF3 trigger request 412 // WRTXT3 Writes to TXT3, TXTX3, or TXTXBUF3 trigger request 413 // AESDONE Completion of AES operation triggers request 414 // AESSTART Start of AES operation triggers request 415 // DIS DMA requests are disabled 416 #define AES_DMA_TRGCHB_W 3U 417 #define AES_DMA_TRGCHB_M 0x00000700U 418 #define AES_DMA_TRGCHB_S 8U 419 #define AES_DMA_TRGCHB_RDTXT3 0x00000400U 420 #define AES_DMA_TRGCHB_WRTXT3 0x00000300U 421 #define AES_DMA_TRGCHB_AESDONE 0x00000200U 422 #define AES_DMA_TRGCHB_AESSTART 0x00000100U 423 #define AES_DMA_TRGCHB_DIS 0x00000000U 424 425 // Field: [5:4] ADRCHA 426 // 427 // Channel A Read Write Address 428 // 429 // The DMA accesses DMACHA to read or write contents of TXT and BUF as a 430 // response to a burst request. This field specifes the start address of the 431 // first DMA transfer that follows the burst request. The internal address gets 432 // incremented automatically for subsequent accesses. The DMA can transfer 433 // 8-bit, 16-bit, or 32-bit words, and must always complete a 16-byte transfer 434 // before re-arbitration. 435 // ENUMs: 436 // TXTXBUF0 Start address is TXTXBUF0 437 // BUF0 Start address is BUF0 438 // TXTX0 Start address is TXTX0 439 // TXT0 Start address is TXT0 440 #define AES_DMA_ADRCHA_W 2U 441 #define AES_DMA_ADRCHA_M 0x00000030U 442 #define AES_DMA_ADRCHA_S 4U 443 #define AES_DMA_ADRCHA_TXTXBUF0 0x00000030U 444 #define AES_DMA_ADRCHA_BUF0 0x00000020U 445 #define AES_DMA_ADRCHA_TXTX0 0x00000010U 446 #define AES_DMA_ADRCHA_TXT0 0x00000000U 447 448 // Field: [2:0] TRGCHA 449 // 450 // Channel A Trigger 451 // 452 // Select the condition that triggers DMA channel A request. Non-enumerated 453 // values are not supported and ignored. 454 // ENUMs: 455 // RDTXT3 Reads of TXT3 or TXTXBUF3 trigger request 456 // WRTXT3 Writes to TXT3 or TXTX3 trigger request 457 // AESDONE Completion of AES operation triggers request 458 // AESSTART Start of AES operation triggers request 459 // DIS DMA requests are disabled 460 #define AES_DMA_TRGCHA_W 3U 461 #define AES_DMA_TRGCHA_M 0x00000007U 462 #define AES_DMA_TRGCHA_S 0U 463 #define AES_DMA_TRGCHA_RDTXT3 0x00000004U 464 #define AES_DMA_TRGCHA_WRTXT3 0x00000003U 465 #define AES_DMA_TRGCHA_AESDONE 0x00000002U 466 #define AES_DMA_TRGCHA_AESSTART 0x00000001U 467 #define AES_DMA_TRGCHA_DIS 0x00000000U 468 469 //***************************************************************************** 470 // 471 // Register: AES_O_DMACHA 472 // 473 //***************************************************************************** 474 // Field: [31:0] VAL 475 // 476 // Value transferred through DMA Channel A 477 #define AES_DMACHA_VAL_W 32U 478 #define AES_DMACHA_VAL_M 0xFFFFFFFFU 479 #define AES_DMACHA_VAL_S 0U 480 481 //***************************************************************************** 482 // 483 // Register: AES_O_DMACHB 484 // 485 //***************************************************************************** 486 // Field: [31:0] VAL 487 // 488 // Value transferred through DMA Channel B 489 #define AES_DMACHB_VAL_W 32U 490 #define AES_DMACHB_VAL_M 0xFFFFFFFFU 491 #define AES_DMACHB_VAL_S 0U 492 493 //***************************************************************************** 494 // 495 // Register: AES_O_AUTOCFG 496 // 497 //***************************************************************************** 498 // Field: [28] CHBDNCLR 499 // 500 // This field enable auto-clear of RIS.CHBDONE interrupt on read/write of 501 // TXT3/BUF3/TXTX3/TXTXBUF3 . 502 // 503 // ENUMs: 504 // EN Enable auto-clear of RIS.CHBDONE interrupt 505 // DIS Disable auto-clear of RIS.CHBDONE interrupt 506 #define AES_AUTOCFG_CHBDNCLR 0x10000000U 507 #define AES_AUTOCFG_CHBDNCLR_M 0x10000000U 508 #define AES_AUTOCFG_CHBDNCLR_S 28U 509 #define AES_AUTOCFG_CHBDNCLR_EN 0x10000000U 510 #define AES_AUTOCFG_CHBDNCLR_DIS 0x00000000U 511 512 // Field: [27] CHADNCLR 513 // 514 // This field enables auto-clear of RIS.CHADONE interrupt on read/write of 515 // TXT3/BUF3/TXTX3/TXTXBUF3 . 516 // 517 // ENUMs: 518 // EN Enable auto-clear of RIS.CHADONE interrupt 519 // DIS Disable auto-clear of RIS.CHADONE interrupt 520 #define AES_AUTOCFG_CHADNCLR 0x08000000U 521 #define AES_AUTOCFG_CHADNCLR_M 0x08000000U 522 #define AES_AUTOCFG_CHADNCLR_S 27U 523 #define AES_AUTOCFG_CHADNCLR_EN 0x08000000U 524 #define AES_AUTOCFG_CHADNCLR_DIS 0x00000000U 525 526 // Field: [26] CLRAESST 527 // 528 // Clear AES Start 529 // 530 // This field enables auto-clear of RIS.AESSTART interrupt on read/write of 531 // TXT3/BUF3/TXTX3/TXTXBUF3 . 532 // ENUMs: 533 // EN Enable auto-clear of RIS.AESSTART interrupt 534 // DIS Disable auto-clear of RIS.AESSTART interrupt 535 #define AES_AUTOCFG_CLRAESST 0x04000000U 536 #define AES_AUTOCFG_CLRAESST_M 0x04000000U 537 #define AES_AUTOCFG_CLRAESST_S 26U 538 #define AES_AUTOCFG_CLRAESST_EN 0x04000000U 539 #define AES_AUTOCFG_CLRAESST_DIS 0x00000000U 540 541 // Field: [25] CLRAESDN 542 // 543 // Clear AES Done 544 // 545 // This field enables auto-clear of RIS.AESDONE interrupt on read/write of 546 // TXT3/BUF3/TXTX3/TXTXBUF3 . 547 // 548 // ENUMs: 549 // EN Enable auto-clear of RIS.AESDONE interrupt 550 // DIS Disable auto-clear of RIS.AESDONE interrupt 551 #define AES_AUTOCFG_CLRAESDN 0x02000000U 552 #define AES_AUTOCFG_CLRAESDN_M 0x02000000U 553 #define AES_AUTOCFG_CLRAESDN_S 25U 554 #define AES_AUTOCFG_CLRAESDN_EN 0x02000000U 555 #define AES_AUTOCFG_CLRAESDN_DIS 0x00000000U 556 557 // Field: [24] BUSHALT 558 // 559 // Bus Halt 560 // 561 // This field decides if bus halts on access to KEY, TXT, BUF, TXTX and TXTXBUF 562 // when STA.STATE = BUSY. 563 // ENUMs: 564 // EN Enable bus halt 565 // 566 // When STA.STATE = BUSY, 567 // access to KEY, TXT, TXTX, TXTXBUF halt the bus 568 // until STA.STATE = IDLE. 569 // When STA.STATE = BUSY and 570 // if either STA.BUFSTA = FULL or AUTOCFG.CTRSIZE 571 // != DISABLE, access to BUF halts the bus until 572 // STA.STATE = IDLE. 573 // DIS Disable bus halt 574 // 575 // When STA.STATE = BUSY, 576 // writes to KEY, TXT, TXTX are ignored, reads 577 // from TXT, TXTXBUF return zero. 578 // When STA.STATE = BUSY and 579 // if either STA.BUFSTA = FULL or AUTOCFG.CTRSIZE 580 // != DISABLE, writes to BUF are ignored, reads 581 // return zero. 582 #define AES_AUTOCFG_BUSHALT 0x01000000U 583 #define AES_AUTOCFG_BUSHALT_M 0x01000000U 584 #define AES_AUTOCFG_BUSHALT_S 24U 585 #define AES_AUTOCFG_BUSHALT_EN 0x01000000U 586 #define AES_AUTOCFG_BUSHALT_DIS 0x00000000U 587 588 // Field: [21:19] CTRSIZE 589 // 590 // Counter Size 591 // 592 // Configures size of counter as either 8,16,32,64 or 128 593 // Non-enumerated values are not supported and ignored 594 // ENUMs: 595 // CTR128 Configures counter size as 128-bit 596 // CTR64 Configures counter size as 64-bit 597 // CTR32 Configures counter size as 32-bit 598 // CTR16 Configures counter size as 16-bit 599 // CTR8 Configures counter size as 8-bit 600 // DIS Disable CTR operation 601 #define AES_AUTOCFG_CTRSIZE_W 3U 602 #define AES_AUTOCFG_CTRSIZE_M 0x00380000U 603 #define AES_AUTOCFG_CTRSIZE_S 19U 604 #define AES_AUTOCFG_CTRSIZE_CTR128 0x00280000U 605 #define AES_AUTOCFG_CTRSIZE_CTR64 0x00200000U 606 #define AES_AUTOCFG_CTRSIZE_CTR32 0x00180000U 607 #define AES_AUTOCFG_CTRSIZE_CTR16 0x00100000U 608 #define AES_AUTOCFG_CTRSIZE_CTR8 0x00080000U 609 #define AES_AUTOCFG_CTRSIZE_DIS 0x00000000U 610 611 // Field: [18] CTRALIGN 612 // 613 // Counter Alignment 614 // 615 // Specifies alignment of counter 616 // ENUMs: 617 // RIGHTALIGN Indicates right aligned counter 618 // Not applicable when 619 // counter size is 128-bit 620 // For 128-bit counter, all 621 // octets will be considered 622 // 623 // If right aligned, octet 624 // 8-15 will be considered based on endianness and 625 // counter size 626 // LEFTALIGN Indicates Left Aligned Counter 627 // Not applicable for 628 // 128-bit counter size. 629 // For 128-bit counter, all 630 // octets will be considered 631 // 632 // When left aligned,,octet 633 // 0-7 will be considered , based on counter size 634 // and endianness 635 #define AES_AUTOCFG_CTRALIGN 0x00040000U 636 #define AES_AUTOCFG_CTRALIGN_M 0x00040000U 637 #define AES_AUTOCFG_CTRALIGN_S 18U 638 #define AES_AUTOCFG_CTRALIGN_RIGHTALIGN 0x00040000U 639 #define AES_AUTOCFG_CTRALIGN_LEFTALIGN 0x00000000U 640 641 // Field: [17] CTRENDN 642 // 643 // Counter Endianness 644 // 645 // Specifies Endianness of counter 646 // ENUMs: 647 // BIGENDIAN Specifies Big Endian Counter 648 // Carry will flow from 649 // octet 'n' to octet 'n-1' 650 // LITTLEENDIAN Specifies Little Endian Counter 651 // Carry will flow from 652 // octet 'n' to octet 'n+1' 653 #define AES_AUTOCFG_CTRENDN 0x00020000U 654 #define AES_AUTOCFG_CTRENDN_M 0x00020000U 655 #define AES_AUTOCFG_CTRENDN_S 17U 656 #define AES_AUTOCFG_CTRENDN_BIGENDIAN 0x00020000U 657 #define AES_AUTOCFG_CTRENDN_LITTLEENDIAN 0x00000000U 658 659 // Field: [9:8] TRGTXT 660 // 661 // Trigger for TXT 662 // 663 // This field determines if and when hardware automatically XORs BUF into TXT. 664 // Non-enumerated values are not supported and ignored. It is allowed to 665 // configure this field with an OR-combination of supported enums. 666 // ENUMs: 667 // RDTXTXBUF3 Hardware XORs content of BUF into TXT upon read of 668 // TXTXBUF3 669 // RDTXT3 Hardware XORs content of BUF into TXT upon read of 670 // TXT3 671 // DIS No hardware update of TXT 672 #define AES_AUTOCFG_TRGTXT_W 2U 673 #define AES_AUTOCFG_TRGTXT_M 0x00000300U 674 #define AES_AUTOCFG_TRGTXT_S 8U 675 #define AES_AUTOCFG_TRGTXT_RDTXTXBUF3 0x00000200U 676 #define AES_AUTOCFG_TRGTXT_RDTXT3 0x00000100U 677 #define AES_AUTOCFG_TRGTXT_DIS 0x00000000U 678 679 // Field: [5:4] AESSRC 680 // 681 // AES Source 682 // 683 // This field specifies the data source to hardware-triggered AES operations. 684 // Non-enumerated values are not supported and ignored. 685 // ENUMs: 686 // TXTXBUF TXT = AES(KEY, TXT XOR BUF) 687 // BUF TXT = AES(KEY,BUF) 688 // TXT TXT = AES(KEY,TXT) 689 #define AES_AUTOCFG_AESSRC_W 2U 690 #define AES_AUTOCFG_AESSRC_M 0x00000030U 691 #define AES_AUTOCFG_AESSRC_S 4U 692 #define AES_AUTOCFG_AESSRC_TXTXBUF 0x00000030U 693 #define AES_AUTOCFG_AESSRC_BUF 0x00000020U 694 #define AES_AUTOCFG_AESSRC_TXT 0x00000010U 695 696 // Field: [3:0] TRGAES 697 // 698 // Trigger Electronic Codebook 699 // 700 // This field specifies one or more actions that indirectly trigger AES 701 // operation. 702 // It is allowed to configure this field with an OR-combination of supported 703 // enums. 704 // ENUMs: 705 // WRBUF3S Write to BUF3 will schedule to trigger single 706 // action once STA.STATE is or becomes IDLE. 707 // Subsequent writes do not trigger action unless 708 // this setting is written again to this field. 709 // WRBUF3 All writes to BUF3 will schedule to trigger action 710 // once STA.STATE is or becomes IDLE, only when 711 // AUTOCFG.CTRSIZE = DIS 712 // RDTXT3 All reads of TXT3 or TXTXBUF3 trigger action, only 713 // when STA.STATE = IDLE 714 // WRTXT3 All writes to TXT3 or TXTX3 trigger action, only 715 // when STA.STATE = IDLE 716 // DIS No user action indirectly triggers AES operation 717 #define AES_AUTOCFG_TRGAES_W 4U 718 #define AES_AUTOCFG_TRGAES_M 0x0000000FU 719 #define AES_AUTOCFG_TRGAES_S 0U 720 #define AES_AUTOCFG_TRGAES_WRBUF3S 0x00000008U 721 #define AES_AUTOCFG_TRGAES_WRBUF3 0x00000004U 722 #define AES_AUTOCFG_TRGAES_RDTXT3 0x00000002U 723 #define AES_AUTOCFG_TRGAES_WRTXT3 0x00000001U 724 #define AES_AUTOCFG_TRGAES_DIS 0x00000000U 725 726 //***************************************************************************** 727 // 728 // Register: AES_O_KEY0 729 // 730 //***************************************************************************** 731 // Field: [31:0] VAL 732 // 733 // Value of KEY[31:0] 734 #define AES_KEY0_VAL_W 32U 735 #define AES_KEY0_VAL_M 0xFFFFFFFFU 736 #define AES_KEY0_VAL_S 0U 737 738 //***************************************************************************** 739 // 740 // Register: AES_O_KEY1 741 // 742 //***************************************************************************** 743 // Field: [31:0] VAL 744 // 745 // Value of KEY[63:32] 746 #define AES_KEY1_VAL_W 32U 747 #define AES_KEY1_VAL_M 0xFFFFFFFFU 748 #define AES_KEY1_VAL_S 0U 749 750 //***************************************************************************** 751 // 752 // Register: AES_O_KEY2 753 // 754 //***************************************************************************** 755 // Field: [31:0] VAL 756 // 757 // Value of KEY[95:64] 758 #define AES_KEY2_VAL_W 32U 759 #define AES_KEY2_VAL_M 0xFFFFFFFFU 760 #define AES_KEY2_VAL_S 0U 761 762 //***************************************************************************** 763 // 764 // Register: AES_O_KEY3 765 // 766 //***************************************************************************** 767 // Field: [31:0] VAL 768 // 769 // Value of KEY[127:96] 770 #define AES_KEY3_VAL_W 32U 771 #define AES_KEY3_VAL_M 0xFFFFFFFFU 772 #define AES_KEY3_VAL_S 0U 773 774 //***************************************************************************** 775 // 776 // Register: AES_O_TXT0 777 // 778 //***************************************************************************** 779 // Field: [31:0] VAL 780 // 781 // Value of TXT[31:0] 782 #define AES_TXT0_VAL_W 32U 783 #define AES_TXT0_VAL_M 0xFFFFFFFFU 784 #define AES_TXT0_VAL_S 0U 785 786 //***************************************************************************** 787 // 788 // Register: AES_O_TXT1 789 // 790 //***************************************************************************** 791 // Field: [31:0] VAL 792 // 793 // Value of TXT[63:32] 794 #define AES_TXT1_VAL_W 32U 795 #define AES_TXT1_VAL_M 0xFFFFFFFFU 796 #define AES_TXT1_VAL_S 0U 797 798 //***************************************************************************** 799 // 800 // Register: AES_O_TXT2 801 // 802 //***************************************************************************** 803 // Field: [31:0] VAL 804 // 805 // Value of TXT[95:64] 806 #define AES_TXT2_VAL_W 32U 807 #define AES_TXT2_VAL_M 0xFFFFFFFFU 808 #define AES_TXT2_VAL_S 0U 809 810 //***************************************************************************** 811 // 812 // Register: AES_O_TXT3 813 // 814 //***************************************************************************** 815 // Field: [31:0] VAL 816 // 817 // Value of TXT[127:96] 818 // 819 // AUTOCFG.TRGAES decides if a write to or a read of this field triggers an AES 820 // operation. 821 #define AES_TXT3_VAL_W 32U 822 #define AES_TXT3_VAL_M 0xFFFFFFFFU 823 #define AES_TXT3_VAL_S 0U 824 825 //***************************************************************************** 826 // 827 // Register: AES_O_TXTX0 828 // 829 //***************************************************************************** 830 // Field: [31:0] VAL 831 // 832 // Value in TXT0 will be TXT0.VAL = VAL XOR TXT0.VAL 833 #define AES_TXTX0_VAL_W 32U 834 #define AES_TXTX0_VAL_M 0xFFFFFFFFU 835 #define AES_TXTX0_VAL_S 0U 836 837 //***************************************************************************** 838 // 839 // Register: AES_O_TXTX1 840 // 841 //***************************************************************************** 842 // Field: [31:0] VAL 843 // 844 // Value in TXT1 will be TXT1.VAL = VAL XOR TXT1.VAL 845 #define AES_TXTX1_VAL_W 32U 846 #define AES_TXTX1_VAL_M 0xFFFFFFFFU 847 #define AES_TXTX1_VAL_S 0U 848 849 //***************************************************************************** 850 // 851 // Register: AES_O_TXTX2 852 // 853 //***************************************************************************** 854 // Field: [31:0] VAL 855 // 856 // Value in TXT2 will be TXT2.VAL = VAL XOR TXT2.VAL 857 #define AES_TXTX2_VAL_W 32U 858 #define AES_TXTX2_VAL_M 0xFFFFFFFFU 859 #define AES_TXTX2_VAL_S 0U 860 861 //***************************************************************************** 862 // 863 // Register: AES_O_TXTX3 864 // 865 //***************************************************************************** 866 // Field: [31:0] VAL 867 // 868 // Value in TXT3 will be TXT3.VAL = VAL XOR TXT3.VAL 869 #define AES_TXTX3_VAL_W 32U 870 #define AES_TXTX3_VAL_M 0xFFFFFFFFU 871 #define AES_TXTX3_VAL_S 0U 872 873 //***************************************************************************** 874 // 875 // Register: AES_O_BUF0 876 // 877 //***************************************************************************** 878 // Field: [31:0] VAL 879 // 880 // Value of BUF[31:0] 881 #define AES_BUF0_VAL_W 32U 882 #define AES_BUF0_VAL_M 0xFFFFFFFFU 883 #define AES_BUF0_VAL_S 0U 884 885 //***************************************************************************** 886 // 887 // Register: AES_O_BUF1 888 // 889 //***************************************************************************** 890 // Field: [31:0] VAL 891 // 892 // Value of BUF[63:32] 893 #define AES_BUF1_VAL_W 32U 894 #define AES_BUF1_VAL_M 0xFFFFFFFFU 895 #define AES_BUF1_VAL_S 0U 896 897 //***************************************************************************** 898 // 899 // Register: AES_O_BUF2 900 // 901 //***************************************************************************** 902 // Field: [31:0] VAL 903 // 904 // Value of BUF[95:64] 905 #define AES_BUF2_VAL_W 32U 906 #define AES_BUF2_VAL_M 0xFFFFFFFFU 907 #define AES_BUF2_VAL_S 0U 908 909 //***************************************************************************** 910 // 911 // Register: AES_O_BUF3 912 // 913 //***************************************************************************** 914 // Field: [31:0] VAL 915 // 916 // Value of BUF[127:96] 917 #define AES_BUF3_VAL_W 32U 918 #define AES_BUF3_VAL_M 0xFFFFFFFFU 919 #define AES_BUF3_VAL_S 0U 920 921 //***************************************************************************** 922 // 923 // Register: AES_O_TXTXBUF0 924 // 925 //***************************************************************************** 926 // Field: [31:0] VAL 927 // 928 // Value read will be TXT0.VAL XOR BUF0.VAL 929 #define AES_TXTXBUF0_VAL_W 32U 930 #define AES_TXTXBUF0_VAL_M 0xFFFFFFFFU 931 #define AES_TXTXBUF0_VAL_S 0U 932 933 //***************************************************************************** 934 // 935 // Register: AES_O_TXTXBUF1 936 // 937 //***************************************************************************** 938 // Field: [31:0] VAL 939 // 940 // Value read will be TXT1.VAL XOR BUF1.VAL 941 #define AES_TXTXBUF1_VAL_W 32U 942 #define AES_TXTXBUF1_VAL_M 0xFFFFFFFFU 943 #define AES_TXTXBUF1_VAL_S 0U 944 945 //***************************************************************************** 946 // 947 // Register: AES_O_TXTXBUF2 948 // 949 //***************************************************************************** 950 // Field: [31:0] VAL 951 // 952 // Value read will be TXT2.VAL XOR BUF2.VAL 953 #define AES_TXTXBUF2_VAL_W 32U 954 #define AES_TXTXBUF2_VAL_M 0xFFFFFFFFU 955 #define AES_TXTXBUF2_VAL_S 0U 956 957 //***************************************************************************** 958 // 959 // Register: AES_O_TXTXBUF3 960 // 961 //***************************************************************************** 962 // Field: [31:0] VAL 963 // 964 // Value read will be TXT3.VAL XOR BUF3.VAL 965 #define AES_TXTXBUF3_VAL_W 32U 966 #define AES_TXTXBUF3_VAL_M 0xFFFFFFFFU 967 #define AES_TXTXBUF3_VAL_S 0U 968 969 //***************************************************************************** 970 // 971 // Register: AES_O_IMASK 972 // 973 //***************************************************************************** 974 // Field: [3] CHBDONE 975 // 976 // DMA Channel B Done interrupt mask 977 // ENUMs: 978 // EN Enable interrupt mask 979 // DIS Disable interrupt mask 980 #define AES_IMASK_CHBDONE 0x00000008U 981 #define AES_IMASK_CHBDONE_M 0x00000008U 982 #define AES_IMASK_CHBDONE_S 3U 983 #define AES_IMASK_CHBDONE_EN 0x00000008U 984 #define AES_IMASK_CHBDONE_DIS 0x00000000U 985 986 // Field: [2] CHADONE 987 // 988 // DMA Channel A Done interrupt mask 989 // ENUMs: 990 // EN Enable interrupt mask 991 // DIS Disable interrupt mask 992 #define AES_IMASK_CHADONE 0x00000004U 993 #define AES_IMASK_CHADONE_M 0x00000004U 994 #define AES_IMASK_CHADONE_S 2U 995 #define AES_IMASK_CHADONE_EN 0x00000004U 996 #define AES_IMASK_CHADONE_DIS 0x00000000U 997 998 // Field: [1] AESSTART 999 // 1000 // AES Start interrupt mask 1001 // ENUMs: 1002 // EN Enable interrupt mask 1003 // DIS Disable interrupt mask 1004 #define AES_IMASK_AESSTART 0x00000002U 1005 #define AES_IMASK_AESSTART_M 0x00000002U 1006 #define AES_IMASK_AESSTART_S 1U 1007 #define AES_IMASK_AESSTART_EN 0x00000002U 1008 #define AES_IMASK_AESSTART_DIS 0x00000000U 1009 1010 // Field: [0] AESDONE 1011 // 1012 // AES Done interrupt mask 1013 // ENUMs: 1014 // EN Enable interrupt mask 1015 // DIS Disable interrupt mask 1016 #define AES_IMASK_AESDONE 0x00000001U 1017 #define AES_IMASK_AESDONE_M 0x00000001U 1018 #define AES_IMASK_AESDONE_S 0U 1019 #define AES_IMASK_AESDONE_EN 0x00000001U 1020 #define AES_IMASK_AESDONE_DIS 0x00000000U 1021 1022 //***************************************************************************** 1023 // 1024 // Register: AES_O_RIS 1025 // 1026 //***************************************************************************** 1027 // Field: [3] CHBDONE 1028 // 1029 // Raw Interrupt Status for DMA Channel B Done 1030 // ENUMs: 1031 // SET Interrupt occurred 1032 // CLR Interrupt did not occur 1033 #define AES_RIS_CHBDONE 0x00000008U 1034 #define AES_RIS_CHBDONE_M 0x00000008U 1035 #define AES_RIS_CHBDONE_S 3U 1036 #define AES_RIS_CHBDONE_SET 0x00000008U 1037 #define AES_RIS_CHBDONE_CLR 0x00000000U 1038 1039 // Field: [2] CHADONE 1040 // 1041 // Raw Interrupt Status for DMA Channel A Done 1042 // ENUMs: 1043 // SET Interrupt occurred 1044 // CLR Interrupt did not occur 1045 #define AES_RIS_CHADONE 0x00000004U 1046 #define AES_RIS_CHADONE_M 0x00000004U 1047 #define AES_RIS_CHADONE_S 2U 1048 #define AES_RIS_CHADONE_SET 0x00000004U 1049 #define AES_RIS_CHADONE_CLR 0x00000000U 1050 1051 // Field: [1] AESSTART 1052 // 1053 // Raw Interrupt Status for AES Start 1054 // ENUMs: 1055 // SET Interrupt occurred 1056 // CLR Interrupt did not occur 1057 #define AES_RIS_AESSTART 0x00000002U 1058 #define AES_RIS_AESSTART_M 0x00000002U 1059 #define AES_RIS_AESSTART_S 1U 1060 #define AES_RIS_AESSTART_SET 0x00000002U 1061 #define AES_RIS_AESSTART_CLR 0x00000000U 1062 1063 // Field: [0] AESDONE 1064 // 1065 // Raw Interrupt Status for AES Done 1066 // ENUMs: 1067 // SET Interrupt occurred 1068 // CLR Interrupt did not occur 1069 #define AES_RIS_AESDONE 0x00000001U 1070 #define AES_RIS_AESDONE_M 0x00000001U 1071 #define AES_RIS_AESDONE_S 0U 1072 #define AES_RIS_AESDONE_SET 0x00000001U 1073 #define AES_RIS_AESDONE_CLR 0x00000000U 1074 1075 //***************************************************************************** 1076 // 1077 // Register: AES_O_MIS 1078 // 1079 //***************************************************************************** 1080 // Field: [3] CHBDONE 1081 // 1082 // Masked Interrupt Status for DMA Channel B Done 1083 // ENUMs: 1084 // SET Interrupt occurred 1085 // CLR Interrupt did not occur 1086 #define AES_MIS_CHBDONE 0x00000008U 1087 #define AES_MIS_CHBDONE_M 0x00000008U 1088 #define AES_MIS_CHBDONE_S 3U 1089 #define AES_MIS_CHBDONE_SET 0x00000008U 1090 #define AES_MIS_CHBDONE_CLR 0x00000000U 1091 1092 // Field: [2] CHADONE 1093 // 1094 // Masked Interrupt Status for DMA Channel A Done 1095 // ENUMs: 1096 // SET Interrupt occurred 1097 // CLR Interrupt did not occur 1098 #define AES_MIS_CHADONE 0x00000004U 1099 #define AES_MIS_CHADONE_M 0x00000004U 1100 #define AES_MIS_CHADONE_S 2U 1101 #define AES_MIS_CHADONE_SET 0x00000004U 1102 #define AES_MIS_CHADONE_CLR 0x00000000U 1103 1104 // Field: [1] AESSTART 1105 // 1106 // Masked Interrupt Status for AES Start 1107 // ENUMs: 1108 // SET Interrupt occurred 1109 // CLR Interrupt did not occur 1110 #define AES_MIS_AESSTART 0x00000002U 1111 #define AES_MIS_AESSTART_M 0x00000002U 1112 #define AES_MIS_AESSTART_S 1U 1113 #define AES_MIS_AESSTART_SET 0x00000002U 1114 #define AES_MIS_AESSTART_CLR 0x00000000U 1115 1116 // Field: [0] AESDONE 1117 // 1118 // Masked Interrupt Status for AES Done 1119 // ENUMs: 1120 // SET Interrupt occurred 1121 // CLR Interrupt did not occur 1122 #define AES_MIS_AESDONE 0x00000001U 1123 #define AES_MIS_AESDONE_M 0x00000001U 1124 #define AES_MIS_AESDONE_S 0U 1125 #define AES_MIS_AESDONE_SET 0x00000001U 1126 #define AES_MIS_AESDONE_CLR 0x00000000U 1127 1128 //***************************************************************************** 1129 // 1130 // Register: AES_O_ISET 1131 // 1132 //***************************************************************************** 1133 // Field: [3] CHBDONE 1134 // 1135 // Set DMA Channel B Done interrupt 1136 // ENUMs: 1137 // SET Set interrupt 1138 // NOEFF Writing 0 has no effect 1139 #define AES_ISET_CHBDONE 0x00000008U 1140 #define AES_ISET_CHBDONE_M 0x00000008U 1141 #define AES_ISET_CHBDONE_S 3U 1142 #define AES_ISET_CHBDONE_SET 0x00000008U 1143 #define AES_ISET_CHBDONE_NOEFF 0x00000000U 1144 1145 // Field: [2] CHADONE 1146 // 1147 // Set DMA Channel A Done interrupt 1148 // ENUMs: 1149 // SET Set interrupt 1150 // NOEFF Writing 0 has no effect 1151 #define AES_ISET_CHADONE 0x00000004U 1152 #define AES_ISET_CHADONE_M 0x00000004U 1153 #define AES_ISET_CHADONE_S 2U 1154 #define AES_ISET_CHADONE_SET 0x00000004U 1155 #define AES_ISET_CHADONE_NOEFF 0x00000000U 1156 1157 // Field: [1] AESSTART 1158 // 1159 // Set AES Start interrupt 1160 // ENUMs: 1161 // SET Set interrupt 1162 // NOEFF Writing 0 has no effect 1163 #define AES_ISET_AESSTART 0x00000002U 1164 #define AES_ISET_AESSTART_M 0x00000002U 1165 #define AES_ISET_AESSTART_S 1U 1166 #define AES_ISET_AESSTART_SET 0x00000002U 1167 #define AES_ISET_AESSTART_NOEFF 0x00000000U 1168 1169 // Field: [0] AESDONE 1170 // 1171 // Set AES Done interrupt 1172 // ENUMs: 1173 // SET Set interrupt 1174 // NOEFF Writing 0 has no effect 1175 #define AES_ISET_AESDONE 0x00000001U 1176 #define AES_ISET_AESDONE_M 0x00000001U 1177 #define AES_ISET_AESDONE_S 0U 1178 #define AES_ISET_AESDONE_SET 0x00000001U 1179 #define AES_ISET_AESDONE_NOEFF 0x00000000U 1180 1181 //***************************************************************************** 1182 // 1183 // Register: AES_O_ICLR 1184 // 1185 //***************************************************************************** 1186 // Field: [3] CHBDONE 1187 // 1188 // Clear DMA Channel B Done interrupt 1189 // ENUMs: 1190 // CLR Clear interrupt 1191 // NOEFF Writing 0 has no effect 1192 #define AES_ICLR_CHBDONE 0x00000008U 1193 #define AES_ICLR_CHBDONE_M 0x00000008U 1194 #define AES_ICLR_CHBDONE_S 3U 1195 #define AES_ICLR_CHBDONE_CLR 0x00000008U 1196 #define AES_ICLR_CHBDONE_NOEFF 0x00000000U 1197 1198 // Field: [2] CHADONE 1199 // 1200 // Clear DMA Channel A Done interrupt 1201 // ENUMs: 1202 // CLR Clear interrupt 1203 // NOEFF Writing 0 has no effect 1204 #define AES_ICLR_CHADONE 0x00000004U 1205 #define AES_ICLR_CHADONE_M 0x00000004U 1206 #define AES_ICLR_CHADONE_S 2U 1207 #define AES_ICLR_CHADONE_CLR 0x00000004U 1208 #define AES_ICLR_CHADONE_NOEFF 0x00000000U 1209 1210 // Field: [1] AESSTART 1211 // 1212 // Clear AES Start interrupt 1213 // ENUMs: 1214 // CLR Clear interrupt 1215 // NOEFF Writing 0 has no effect 1216 #define AES_ICLR_AESSTART 0x00000002U 1217 #define AES_ICLR_AESSTART_M 0x00000002U 1218 #define AES_ICLR_AESSTART_S 1U 1219 #define AES_ICLR_AESSTART_CLR 0x00000002U 1220 #define AES_ICLR_AESSTART_NOEFF 0x00000000U 1221 1222 // Field: [0] AESDONE 1223 // 1224 // Clear AES Done interrupt 1225 // ENUMs: 1226 // CLR Clear interrupt 1227 // NOEFF Writing 0 has no effect 1228 #define AES_ICLR_AESDONE 0x00000001U 1229 #define AES_ICLR_AESDONE_M 0x00000001U 1230 #define AES_ICLR_AESDONE_S 0U 1231 #define AES_ICLR_AESDONE_CLR 0x00000001U 1232 #define AES_ICLR_AESDONE_NOEFF 0x00000000U 1233 1234 //***************************************************************************** 1235 // 1236 // Register: AES_O_IMSET 1237 // 1238 //***************************************************************************** 1239 // Field: [3] CHBDONE 1240 // 1241 // Set DMA Channel B Done interrupt mask 1242 // ENUMs: 1243 // SET Set interrupt mask 1244 // NOEFF Writing 0 has no effect 1245 #define AES_IMSET_CHBDONE 0x00000008U 1246 #define AES_IMSET_CHBDONE_M 0x00000008U 1247 #define AES_IMSET_CHBDONE_S 3U 1248 #define AES_IMSET_CHBDONE_SET 0x00000008U 1249 #define AES_IMSET_CHBDONE_NOEFF 0x00000000U 1250 1251 // Field: [2] CHADONE 1252 // 1253 // Set DMA Channel A Done interrupt mask 1254 // ENUMs: 1255 // SET Set interrupt mask 1256 // NOEFF Writing 0 has no effect 1257 #define AES_IMSET_CHADONE 0x00000004U 1258 #define AES_IMSET_CHADONE_M 0x00000004U 1259 #define AES_IMSET_CHADONE_S 2U 1260 #define AES_IMSET_CHADONE_SET 0x00000004U 1261 #define AES_IMSET_CHADONE_NOEFF 0x00000000U 1262 1263 // Field: [1] AESSTART 1264 // 1265 // Set AES Start interrupt mask 1266 // ENUMs: 1267 // SET Set interrupt mask 1268 // NOEFF Writing 0 has no effect 1269 #define AES_IMSET_AESSTART 0x00000002U 1270 #define AES_IMSET_AESSTART_M 0x00000002U 1271 #define AES_IMSET_AESSTART_S 1U 1272 #define AES_IMSET_AESSTART_SET 0x00000002U 1273 #define AES_IMSET_AESSTART_NOEFF 0x00000000U 1274 1275 // Field: [0] AESDONE 1276 // 1277 // Set AES Done interrupt mask 1278 // ENUMs: 1279 // SET Set interrupt mask 1280 // NOEFF Writing 0 has no effect 1281 #define AES_IMSET_AESDONE 0x00000001U 1282 #define AES_IMSET_AESDONE_M 0x00000001U 1283 #define AES_IMSET_AESDONE_S 0U 1284 #define AES_IMSET_AESDONE_SET 0x00000001U 1285 #define AES_IMSET_AESDONE_NOEFF 0x00000000U 1286 1287 //***************************************************************************** 1288 // 1289 // Register: AES_O_IMCLR 1290 // 1291 //***************************************************************************** 1292 // Field: [3] CHBDONE 1293 // 1294 // Clear DMA Channel B Done interrupt mask 1295 // ENUMs: 1296 // CLR Clear interrupt mask 1297 // NOEFF Writing 0 has no effect 1298 #define AES_IMCLR_CHBDONE 0x00000008U 1299 #define AES_IMCLR_CHBDONE_M 0x00000008U 1300 #define AES_IMCLR_CHBDONE_S 3U 1301 #define AES_IMCLR_CHBDONE_CLR 0x00000008U 1302 #define AES_IMCLR_CHBDONE_NOEFF 0x00000000U 1303 1304 // Field: [2] CHADONE 1305 // 1306 // Clear DMA Channel A Done interrupt mask 1307 // ENUMs: 1308 // CLR Clear interrupt mask 1309 // NOEFF Writing 0 has no effect 1310 #define AES_IMCLR_CHADONE 0x00000004U 1311 #define AES_IMCLR_CHADONE_M 0x00000004U 1312 #define AES_IMCLR_CHADONE_S 2U 1313 #define AES_IMCLR_CHADONE_CLR 0x00000004U 1314 #define AES_IMCLR_CHADONE_NOEFF 0x00000000U 1315 1316 // Field: [1] AESSTART 1317 // 1318 // Clear AES Start interrupt mask 1319 // ENUMs: 1320 // CLR Clear interrupt mask 1321 // NOEFF Writing 0 has no effect 1322 #define AES_IMCLR_AESSTART 0x00000002U 1323 #define AES_IMCLR_AESSTART_M 0x00000002U 1324 #define AES_IMCLR_AESSTART_S 1U 1325 #define AES_IMCLR_AESSTART_CLR 0x00000002U 1326 #define AES_IMCLR_AESSTART_NOEFF 0x00000000U 1327 1328 // Field: [0] AESDONE 1329 // 1330 // Clear AES Done interrupt mask 1331 // ENUMs: 1332 // CLR Clear interrupt mask 1333 // NOEFF Writing 0 has no effect 1334 #define AES_IMCLR_AESDONE 0x00000001U 1335 #define AES_IMCLR_AESDONE_M 0x00000001U 1336 #define AES_IMCLR_AESDONE_S 0U 1337 #define AES_IMCLR_AESDONE_CLR 0x00000001U 1338 #define AES_IMCLR_AESDONE_NOEFF 0x00000000U 1339 1340 1341 #endif // __AES__ 1342
