1 /* --COPYRIGHT--,BSD 2 * Copyright (c) 2017, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * --/COPYRIGHT--*/ 32 #ifndef __SYSCTL_A_H__ 33 #define __SYSCTL_A_H__ 34 35 #include <stdint.h> 36 #include <stdbool.h> 37 #include <ti/devices/msp432p4xx/inc/msp.h> 38 39 /* Define to ensure that our current MSP432 has the SYSCTL_A module. This 40 definition is included in the device specific header file */ 41 #ifdef __MCU_HAS_SYSCTL_A__ 42 43 //***************************************************************************** 44 // 45 //! \addtogroup sysctl_a_api 46 //! @{ 47 // 48 //***************************************************************************** 49 50 //***************************************************************************** 51 // 52 // If building with a C++ compiler, make all of the definitions in this header 53 // have a C binding. 54 // 55 //***************************************************************************** 56 #ifdef __cplusplus 57 extern "C" 58 { 59 #endif 60 61 //***************************************************************************** 62 // 63 // Control specific variables 64 // 65 //***************************************************************************** 66 #define SYSCTL_A_HARD_RESET 1 67 #define SYSCTL_A_SOFT_RESET 0 68 69 #define SYSCTL_A_PERIPH_LCD SYSCTL_A_PERIHALT_CTL_HALT_LCD 70 #define SYSCTL_A_PERIPH_DMA SYSCTL_A_PERIHALT_CTL_HALT_DMA 71 #define SYSCTL_A_PERIPH_WDT SYSCTL_A_PERIHALT_CTL_HALT_WDT 72 #define SYSCTL_A_PERIPH_ADC SYSCTL_A_PERIHALT_CTL_HALT_ADC 73 #define SYSCTL_A_PERIPH_EUSCIB3 SYSCTL_A_PERIHALT_CTL_HALT_EUB3 74 #define SYSCTL_A_PERIPH_EUSCIB2 SYSCTL_A_PERIHALT_CTL_HALT_EUB2 75 #define SYSCTL_A_PERIPH_EUSCIB1 SYSCTL_A_PERIHALT_CTL_HALT_EUB1 76 #define SYSCTL_A_PERIPH_EUSCIB0 SYSCTL_A_PERIHALT_CTL_HALT_EUB0 77 #define SYSCTL_A_PERIPH_EUSCIA3 SYSCTL_A_PERIHALT_CTL_HALT_EUA3 78 #define SYSCTL_A_PERIPH_EUSCIA2 SYSCTL_A_PERIHALT_CTL_HALT_EUA2 79 #define SYSCTL_A_PERIPH_EUSCIA1 SYSCTL_A_PERIHALT_CTL_HALT_EUA1 80 #define SYSCTL_A_PERIPH_EUSCIA0 SYSCTL_A_PERIHALT_CTL_HALT_EUA0 81 #define SYSCTL_A_PERIPH_TIMER32_0_MODULE SYSCTL_A_PERIHALT_CTL_HALT_T32_0 82 #define SYSCTL_A_PERIPH_TIMER16_3 SYSCTL_A_PERIHALT_CTL_HALT_T16_3 83 #define SYSCTL_A_PERIPH_TIMER16_2 SYSCTL_A_PERIHALT_CTL_HALT_T16_2 84 #define SYSCTL_A_PERIPH_TIMER16_1 SYSCTL_A_PERIHALT_CTL_HALT_T16_1 85 #define SYSCTL_A_PERIPH_TIMER16_0 SYSCTL_A_PERIHALT_CTL_HALT_T16_0 86 87 #define SYSCTL_A_NMIPIN_SRC SYSCTL_A_NMI_CTLSTAT_PIN_SRC 88 #define SYSCTL_A_PCM_SRC SYSCTL_A_NMI_CTLSTAT_PCM_SRC 89 #define SYSCTL_A_PSS_SRC SYSCTL_A_NMI_CTLSTAT_PSS_SRC 90 #define SYSCTL_A_CS_SRC SYSCTL_A_NMI_CTLSTAT_CS_SRC 91 92 #define SYSCTL_A_REBOOT_KEY 0x6900 93 94 #define SYSCTL_A_1_2V_REF (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE 95 #define SYSCTL_A_1_45V_REF (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE 96 #define SYSCTL_A_2_5V_REF (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE 97 98 #define SYSCTL_A_85_DEGREES_C 4 99 #define SYSCTL_A_30_DEGREES_C 0 100 101 #define SYSCTL_A_BANKMASK 0x80000000 102 #define SRAMCTL_CTL0_BANK 0x10000000 103 #define SRAMCTL_CTL1_BANK 0x20000000 104 #define SRAMCTL_CTL2_BANK 0x30000000 105 #define SRAMCTL_CTL3_BANK 0x40000000 106 107 108 #define TLV_START 0x00201004 109 #define TLV_TAG_RESERVED1 1 110 #define TLV_TAG_RESERVED2 2 111 #define TLV_TAG_CS 3 112 #define TLV_TAG_FLASHCTL 4 113 #define TLV_TAG_ADC14 5 114 #define TLV_TAG_RESERVED6 6 115 #define TLV_TAG_RESERVED7 7 116 #define TLV_TAG_REF 8 117 #define TLV_TAG_RESERVED9 9 118 #define TLV_TAG_RESERVED10 10 119 #define TLV_TAG_DEVINFO 11 120 #define TLV_TAG_DIEREC 12 121 #define TLV_TAG_RANDNUM 13 122 #define TLV_TAG_RESERVED14 14 123 #define TLV_TAG_BSL 15 124 #define TLV_TAGEND 0x0BD0E11D 125 126 //***************************************************************************** 127 // 128 // Structures for TLV definitions 129 // 130 //***************************************************************************** 131 typedef struct 132 { 133 uint32_t maxProgramPulses; 134 uint32_t maxErasePulses; 135 } SysCtl_A_FlashTLV_Info; 136 137 typedef struct 138 { 139 uint32_t rDCOIR_FCAL_RSEL04; 140 uint32_t rDCOIR_FCAL_RSEL5; 141 uint32_t rDCOIR_MAXPOSTUNE_RSEL04; 142 uint32_t rDCOIR_MAXNEGTUNE_RSEL04; 143 uint32_t rDCOIR_MAXPOSTUNE_RSEL5; 144 uint32_t rDCOIR_MAXNEGTUNE_RSEL5; 145 uint32_t rDCOIR_CONSTK_RSEL04; 146 uint32_t rDCOIR_CONSTK_RSEL5; 147 uint32_t rDCOER_FCAL_RSEL04; 148 uint32_t rDCOER_FCAL_RSEL5; 149 uint32_t rDCOER_MAXPOSTUNE_RSEL04; 150 uint32_t rDCOER_MAXNEGTUNE_RSEL04; 151 uint32_t rDCOER_MAXPOSTUNE_RSEL5; 152 uint32_t rDCOER_MAXNEGTUNE_RSEL5; 153 uint32_t rDCOER_CONSTK_RSEL04; 154 uint32_t rDCOER_CONSTK_RSEL5; 155 156 } SysCtl_A_CSCalTLV_Info; 157 158 //***************************************************************************** 159 // 160 // Prototypes for the APIs. 161 // 162 //***************************************************************************** 163 164 //***************************************************************************** 165 // 166 //! Gets the size of the SRAM. 167 //! 168 //! \return The total number of bytes of SRAM. 169 // 170 //***************************************************************************** 171 extern uint_least32_t SysCtl_A_getSRAMSize(void); 172 173 //***************************************************************************** 174 // 175 //! Gets the size of the flash. 176 //! 177 //! \return The total number of bytes of main flash memory. 178 //! 179 //! \note This returns the total amount of main memory flash. To find how much 180 //! INFO memory is available, use the \link SysCtl_A_getInfoFlashSize 181 //! \endlink function. 182 // 183 //***************************************************************************** 184 extern uint_least32_t SysCtl_A_getFlashSize(void); 185 186 //***************************************************************************** 187 // 188 //! Gets the size of the flash. 189 //! 190 //! \return The total number of bytes of flash of INFO flash memory. 191 //! 192 //! \note This returns the total amount of INFO memory flash. To find how much 193 //! main memory is available, use the \link SysCtl_A_getFlashSize 194 //! \endlink function. 195 // 196 //***************************************************************************** 197 extern uint_least32_t SysCtl_A_getInfoFlashSize(void); 198 199 //***************************************************************************** 200 // 201 //! Reboots the device and causes the device to re-initialize itself. 202 //! 203 //! \return This function does not return. 204 // 205 //***************************************************************************** 206 extern void SysCtl_A_rebootDevice(void); 207 208 //***************************************************************************** 209 // 210 //! The TLV structure uses a tag or base address to identify segments of the 211 //! table where information is stored. Some examples of TLV tags are Peripheral 212 //! Descriptor, Interrupts, Info Block and Die Record. This function retrieves 213 //! the value of a tag and the length of the tag. 214 //! 215 //! \param tag represents the tag for which the information needs to be 216 //! retrieved. 217 //! Valid values are: 218 //! - \b TLV_TAG_RESERVED1 219 //! - \b TLV_TAG_RESERVED2 220 //! - \b TLV_TAG_CS 221 //! - \b TLV_TAG_FLASHCTL 222 //! - \b TLV_TAG_ADC14 223 //! - \b TLV_TAG_RESERVED6 224 //! - \b TLV_TAG_RESERVED7 225 //! - \b TLV_TAG_REF 226 //! - \b TLV_TAG_RESERVED9 227 //! - \b TLV_TAG_RESERVED10 228 //! - \b TLV_TAG_DEVINFO 229 //! - \b TLV_TAG_DIEREC 230 //! - \b TLV_TAG_RANDNUM 231 //! - \b TLV_TAG_RESERVED14 232 //! \param instance In some cases a specific tag may have more than one 233 //! instance. For example there may be multiple instances of timer 234 //! calibration data present under a single Timer Cal tag. This variable 235 //! specifies the instance for which information is to be retrieved (0, 236 //! 1, etc.). When only one instance exists; 0 is passed. 237 //! \param length Acts as a return through indirect reference. The function 238 //! retrieves the value of the TLV tag length. This value is pointed to 239 //! by *length and can be used by the application level once the 240 //! function is called. If the specified tag is not found then the 241 //! pointer is null 0. 242 //! \param data_address acts as a return through indirect reference. Once the 243 //! function is called data_address points to the pointer that holds the 244 //! value retrieved from the specified TLV tag. If the specified tag is 245 //! not found then the pointer is null 0. 246 //! 247 //! \return None 248 // 249 //***************************************************************************** 250 extern void SysCtl_A_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance, 251 uint_fast8_t *length, uint32_t **data_address); 252 253 //***************************************************************************** 254 // 255 //! Enables areas of SRAM memory. This can be used to optimize power 256 //! consumption when every SRAM bank isn't needed. 257 //! This function takes in a 32-bit address to the area in SRAM to to enable. 258 //! It will convert this address into the corresponding register settings and 259 //! set them in the register accordingly. Note that passing an address to an 260 //! area other than SRAM will result in unreliable behavior. Addresses should 261 //! be given with reference to the SRAM_DATA area of SRAM (usually starting at 262 //! 0x20000000). 263 //! 264 //! \param addr Break address of SRAM to enable. All SRAM below this address 265 //! will also be enabled. If an unaligned address is given the appropriate 266 //! aligned address will be calculated. 267 //! 268 //! \note The first bank of SRAM is reserved and always enabled. 269 //! 270 //! \return true if banks were set, false otherwise. If the BNKEN_RDY bit is 271 //! not set in the STAT register, this function will return false. 272 // 273 //***************************************************************************** 274 extern bool SysCtl_A_enableSRAM(uint32_t addr); 275 276 //***************************************************************************** 277 // 278 //! Disables areas of SRAM memory. This can be used to optimize power 279 //! consumption when every SRAM bank isn't needed. It is important to note 280 //! that when a higher bank is disabled, all of the SRAM banks above that bank 281 //! are also disabled. For example, if the address of 0x2001FA0 is given, all 282 //! SRAM banks from 0x2001FA0 to the top of SRAM will be disabled. 283 //! This function takes in a 32-bit address to the area in SRAM to to disable. 284 //! It will convert this address into the corresponding register settings and 285 //! set them in the register accordingly. Note that passing an address to an 286 //! area other than SRAM will result in unreliable behavior. Addresses should 287 //! be given with reference to the SRAM_DATA area of SRAM (usually starting at 288 //! 0x20000000). 289 //! 290 //! \param addr Break address of SRAM to disable. All SRAM above this address 291 //! will also be disabled. If an unaligned address is given the appropriate 292 //! aligned address will be calculated. 293 //! 294 //! \note The first bank of SRAM is reserved and always enabled. 295 //! 296 //! \return true if banks were set, false otherwise. If the BNKEN_RDY bit is 297 //! not set in the STAT register, this function will return false. 298 // 299 //***************************************************************************** 300 extern bool SysCtl_A_disableSRAM(uint32_t addr); 301 302 //***************************************************************************** 303 // 304 //! Enables retention of the specified SRAM block address range when the device 305 //! goes into LPM3 mode. When the system is placed in LPM3 mode, the SRAM 306 //! banks specified with this function will be placed into retention mode. 307 //! Retention of individual blocks can be set without the restrictions of the 308 //! enable/disable functions. Note that any memory range given outside of SRAM 309 //! will result in unreliable behavior. Also note that any unaligned addresses 310 //! will be truncated to the closest aligned address before the address given. 311 //! Addresses should be given with reference to the SRAM_DATA area of SRAM 312 //! (usually starting at 0x20000000). 313 //! 314 //! \param startAddr Start address to enable retention 315 //! 316 //! \param endtAddr End address to enable retention 317 //! 318 //! \note Block 0 is reserved and retention is always enabled. 319 //! 320 //! \return true if banks were set, false otherwise. If the BLKEN_RDY bit is 321 //! not set in the STAT register, this function will return false. 322 // 323 //***************************************************************************** 324 extern bool SysCtl_A_enableSRAMRetention(uint32_t startAddr, 325 uint32_t endAddr); 326 327 //***************************************************************************** 328 // 329 //! Disables retention of the specified SRAM block address range when the device 330 //! goes into LPM3 mode. When the system is placed in LPM3 mode, the SRAM 331 //! banks specified with this function will be placed into retention mode. 332 //! Retention of individual blocks can be set without the restrictions of the 333 //! enable/disable functions. Note that any memory range given outside of SRAM 334 //! will result in unreliable behavior. Also note that any unaligned addresses 335 //! will be truncated to the closest aligned address before the address given. 336 //! Addresses should be given with reference to the SRAM_DATA area of SRAM 337 //! (usually starting at 0x20000000). 338 //! 339 //! \param startAddr Start address to disable retention 340 //! 341 //! \param endtAddr End address to disable retention 342 //! 343 //! \note Block 0 is reserved and retention is always enabled. 344 //! 345 //! \return true if banks were set, false otherwise. If the BLKEN_RDY bit is 346 //! not set in the STAT register, this function will return false. 347 // 348 //***************************************************************************** 349 extern bool SysCtl_A_disableSRAMRetention(uint32_t startAddr, 350 uint32_t endAddr); 351 352 //***************************************************************************** 353 // 354 //! Makes it so that the provided peripherals will either halt execution after 355 //! a CPU HALT. Parameters in this function can be combined to account for 356 //! multiple peripherals. By default, all peripherals keep running after a 357 //! CPU HALT. 358 //! 359 //! \param devices The peripherals to continue running after a CPU HALT 360 //! This can be a bitwise OR of the following values: 361 //! - \b SYSCTL_A_PERIPH_LCD, 362 //! - \b SYSCTL_A_PERIPH_DMA, 363 //! - \b SYSCTL_A_PERIPH_WDT, 364 //! - \b SYSCTL_A_PERIPH_ADC, 365 //! - \b SYSCTL_A_PERIPH_EUSCIB3, 366 //! - \b SYSCTL_A_PERIPH_EUSCIB2, 367 //! - \b SYSCTL_A_PERIPH_EUSCIB1 368 //! - \b SYSCTL_A_PERIPH_EUSCIB0, 369 //! - \b SYSCTL_A_PERIPH_EUSCIA3, 370 //! - \b SYSCTL_A_PERIPH_EUSCIA2 371 //! - \b SYSCTL_A_PERIPH_EUSCIA1, 372 //! - \b SYSCTL_A_PERIPH_EUSCIA0, 373 //! - \b SYSCTL_A_PERIPH_TIMER32_0_MODULE, 374 //! - \b SYSCTL_A_PERIPH_TIMER16_3, 375 //! - \b SYSCTL_A_PERIPH_TIMER16_2, 376 //! - \b SYSCTL_A_PERIPH_TIMER16_1, 377 //! - \b SYSCTL_A_PERIPH_TIMER16_0 378 //! 379 //! \return None. 380 // 381 // 382 //***************************************************************************** 383 extern void SysCtl_A_enablePeripheralAtCPUHalt(uint_fast16_t devices); 384 385 //***************************************************************************** 386 // 387 //! Makes it so that the provided peripherals will either halt execution after 388 //! a CPU HALT. Parameters in this function can be combined to account for 389 //! multiple peripherals. By default, all peripherals keep running after a 390 //! CPU HALT. 391 //! 392 //! \param devices The peripherals to disable after a CPU HALT 393 //! 394 //! The \e devices parameter can be a bitwise OR of the following values: 395 //! This can be a bitwise OR of the following values: 396 //! - \b SYSCTL_A_PERIPH_LCD, 397 //! - \b SYSCTL_A_PERIPH_DMA, 398 //! - \b SYSCTL_A_PERIPH_WDT, 399 //! - \b SYSCTL_A_PERIPH_ADC, 400 //! - \b SYSCTL_A_PERIPH_EUSCIB3, 401 //! - \b SYSCTL_A_PERIPH_EUSCIB2, 402 //! - \b SYSCTL_A_PERIPH_EUSCIB1 403 //! - \b SYSCTL_A_PERIPH_EUSCIB0, 404 //! - \b SYSCTL_A_PERIPH_EUSCIA3, 405 //! - \b SYSCTL_A_PERIPH_EUSCIA2 406 //! - \b SYSCTL_A_PERIPH_EUSCIA1, 407 //! - \b SYSCTL_A_PERIPH_EUSCIA0, 408 //! - \b SYSCTL_A_PERIPH_TIMER32_0_MODULE, 409 //! - \b SYSCTL_A_PERIPH_TIMER16_3, 410 //! - \b SYSCTL_A_PERIPH_TIMER16_2, 411 //! - \b SYSCTL_A_PERIPH_TIMER16_1, 412 //! - \b SYSCTL_A_PERIPH_TIMER16_0 413 //! 414 //! \return None. 415 // 416 // 417 //***************************************************************************** 418 extern void SysCtl_A_disablePeripheralAtCPUHalt(uint_fast16_t devices); 419 420 //***************************************************************************** 421 // 422 //! Sets the type of RESET that happens when a watchdog timeout occurs. 423 //! 424 //! \param resetType The type of reset to set 425 //! 426 //! The \e resetType parameter must be only one of the following values: 427 //! - \b SYSCTL_A_HARD_RESET, 428 //! - \b SYSCTL_A_SOFT_RESET 429 //! 430 //! \return None. 431 // 432 // 433 //***************************************************************************** 434 extern void SysCtl_A_setWDTTimeoutResetType(uint_fast8_t resetType); 435 436 //***************************************************************************** 437 // 438 //! Sets the type of RESET that happens when a watchdog password violation 439 //! occurs. 440 //! 441 //! \param resetType The type of reset to set 442 //! 443 //! The \e resetType parameter must be only one of the following values: 444 //! - \b SYSCTL_A_HARD_RESET, 445 //! - \b SYSCTL_A_SOFT_RESET 446 //! 447 //! \return None. 448 // 449 // 450 //***************************************************************************** 451 extern void SysCtl_A_setWDTPasswordViolationResetType(uint_fast8_t resetType); 452 453 //***************************************************************************** 454 // 455 //! Disables NMIs for the provided modules. When disabled, a NMI flag will not 456 //! occur when a fault condition comes from the corresponding modules. 457 //! 458 //! \param flags The NMI sources to disable 459 //! Can be a bitwise OR of the following parameters: 460 //! - \b SYSCTL_A_NMIPIN_SRC, 461 //! - \b SYSCTL_A_PCM_SRC, 462 //! - \b SYSCTL_A_PSS_SRC, 463 //! - \b SYSCTL_A_CS_SRC 464 //! 465 // 466 //***************************************************************************** 467 extern void SysCtl_A_disableNMISource(uint_fast8_t flags); 468 469 //***************************************************************************** 470 // 471 //! Enables NMIs for the provided modules. When enabled, a NMI flag will 472 //! occur when a fault condition comes from the corresponding modules. 473 //! 474 //! \param flags The NMI sources to enable 475 //! Can be a bitwise OR of the following parameters: 476 //! - \b SYSCTL_A_NMIPIN_SRC, 477 //! - \b SYSCTL_A_PCM_SRC, 478 //! - \b SYSCTL_A_PSS_SRC, 479 //! - \b SYSCTL_A_CS_SRC 480 //! 481 // 482 //***************************************************************************** 483 extern void SysCtl_A_enableNMISource(uint_fast8_t flags); 484 485 //***************************************************************************** 486 // 487 //! Returns the current sources of NMIs that are enabled 488 //! 489 //! \return NMI source status 490 // 491 //***************************************************************************** 492 extern uint_fast8_t SysCtl_A_getNMISourceStatus(void); 493 494 //***************************************************************************** 495 // 496 //! Enables glitch suppression on the reset pin of the device. Refer to the 497 //! device data sheet for specific information about glitch suppression 498 //! 499 //! \return None. 500 // 501 // 502 //***************************************************************************** 503 extern void SysCtl_A_enableGlitchFilter(void); 504 505 //***************************************************************************** 506 // 507 //! Disables glitch suppression on the reset pin of the device. Refer to the 508 //! device data sheet for specific information about glitch suppression 509 //! 510 //! \return None. 511 // 512 // 513 //***************************************************************************** 514 extern void SysCtl_A_disableGlitchFilter(void); 515 516 //***************************************************************************** 517 // 518 //! Retrieves the calibration constant of the temperature sensor to be used 519 //! in temperature calculation. 520 //! 521 //! \param refVoltage Reference voltage being used. 522 //! 523 //! The \e refVoltage parameter must be only one of the following values: 524 //! - \b SYSCTL_A_1_2V_REF 525 //! - \b SYSCTL_A_1_45V_REF 526 //! - \b SYSCTL_A_2_5V_REF 527 //! 528 //! \param temperature is the calibration temperature that the user wants to be 529 //! returned. 530 //! 531 //! The \e temperature parameter must be only one of the following values: 532 //! - \b SYSCTL_A_30_DEGREES_C 533 //! - \b SYSCTL_A_85_DEGREES_C 534 //! 535 //! \return None. 536 // 537 // 538 //***************************************************************************** 539 extern uint_fast16_t SysCtl_A_getTempCalibrationConstant(uint32_t refVoltage, 540 uint32_t temperature); 541 542 //***************************************************************************** 543 // 544 // Mark the end of the C bindings section for C++ compilers. 545 // 546 //***************************************************************************** 547 #ifdef __cplusplus 548 } 549 #endif 550 551 //***************************************************************************** 552 // 553 // Close the Doxygen group. 554 //! @} 555 // 556 //***************************************************************************** 557 558 #endif /* __MCU_HAS_SYSCTL_A__ */ 559 560 #endif // __SYSCTL_A_H__ 561
