Searched refs:PAD_CONFIG_BASE (Results 1 – 10 of 10) sorted by relevance
59 #define PAD_CONFIG_BASE ((OCP_SHARED_BASE + \ macro104 ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); in PinModeSet()139 ulPad = ((ulPad << 2) + PAD_CONFIG_BASE) ; in PinModeGet()186 ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); in PinDirModeSet()221 ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); in PinDirModeGet()261 ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); in PinConfigGet()333 ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); in PinConfigSet()351 ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); in PinConfigSet()
61 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) macro121 padRegister = (PinToPadGet(pin)<<2) + PAD_CONFIG_BASE; in ADCCC32XX_close()
56 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) macro488 + PAD_CONFIG_BASE; in SPICC32XXDMA_close()493 + PAD_CONFIG_BASE; in SPICC32XXDMA_close()498 + PAD_CONFIG_BASE; in SPICC32XXDMA_close()504 + PAD_CONFIG_BASE; in SPICC32XXDMA_close()
71 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) macro196 padRegister = (PinToPadGet((hwAttrs->rxPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UARTCC32XXDMA_close()198 padRegister = (PinToPadGet((hwAttrs->txPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UARTCC32XXDMA_close()202 + PAD_CONFIG_BASE; in UARTCC32XXDMA_close()205 + PAD_CONFIG_BASE; in UARTCC32XXDMA_close()
67 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) macro233 padRegister = (PinToPadGet((hwAttrs->rxPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UARTCC32XX_close()235 padRegister = (PinToPadGet((hwAttrs->txPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UARTCC32XX_close()239 + PAD_CONFIG_BASE; in UARTCC32XX_close()242 + PAD_CONFIG_BASE; in UARTCC32XX_close()
62 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) macro280 padRegister = (PinToPadGet((hwAttrs->rxPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UART2CC32XX_close()282 padRegister = (PinToPadGet((hwAttrs->txPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UART2CC32XX_close()287 + PAD_CONFIG_BASE; in UART2CC32XX_close()293 + PAD_CONFIG_BASE; in UART2CC32XX_close()
72 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) macro207 padRegister = (PinToPadGet((hwAttrs->dataPin) & 0x3f)<<2) + PAD_CONFIG_BASE; in SDHostCC32XX_close()209 padRegister = (PinToPadGet((hwAttrs->cmdPin) & 0x3f)<<2) + PAD_CONFIG_BASE; in SDHostCC32XX_close()211 padRegister = (PinToPadGet((hwAttrs->clkPin) & 0x3f)<<2) + PAD_CONFIG_BASE; in SDHostCC32XX_close()
67 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) macro639 padRegister = (PinToPadGet((hwAttrs->clkPin) & 0xff)<<2) + PAD_CONFIG_BASE; in I2CCC32XX_close()641 padRegister = (PinToPadGet((hwAttrs->dataPin) & 0xff)<<2) + PAD_CONFIG_BASE; in I2CCC32XX_close()
66 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) macro368 padRegister = (PinToPadGet((hwAttrs->pwmPin) & 0x3f)<<2) + PAD_CONFIG_BASE; in PWMTimerCC32XX_close()
69 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) macro1170 uint32_t padRegister = (PinToPadGet((pinI2S) & 0x3f)<<2) + PAD_CONFIG_BASE; in resetPin()
