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Searched refs:OCP_SHARED_BASE (Results 1 – 15 of 15) sorted by relevance

/hal_ti-3.4.0/simplelink/source/ti/devices/cc32xx/driverlib/
Dpin.c59 #define PAD_CONFIG_BASE ((OCP_SHARED_BASE + \
688 ulRegValue = (HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG ) in PinHysteresisSet()
702 HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG ) = ulRegValue; in PinHysteresisSet()
743 HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) |= ulPad; in PinLockLevelSet()
747 HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) &= ~ulPad; in PinLockLevelSet()
794 HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_7 ) = ~ulOutEnable; in PinLock()
799 HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) |= (3 << 24); in PinLock()
826 HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) &= ~(3 << 24); in PinUnlock()
Dprcm.c333 if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000280)) == 0x00000280 ) in PRCMSysResetCauseGet()
342 if(HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x1<<8)) in PRCMSysResetCauseGet()
1158 return ((PRCMHIBRegRead((OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8))>>2)&0x7); in PRCMHibernateWakeupCauseGet()
1497 if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) && in PRCMOCRRegisterWrite()
1537 if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) && in PRCMOCRRegisterRead()
2081 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= ((7<<5) | 0x1); in PRCMCC3200MCUInit()
2085 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= (1<<9); in PRCMCC3200MCUInit()
2347 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00001D00; in PRCMIORetentionEnable()
2353 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00000023); in PRCMIORetentionEnable()
2433 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00001D00); in PRCMIORetentionDisable()
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/hal_ti-3.4.0/simplelink/source/ti/devices/cc32xx/inc/
Dhw_memmap.h72 #define OCP_SHARED_BASE 0x4402E000 macro
/hal_ti-3.4.0/simplelink/source/ti/drivers/capture/
DCaptureCC32XX.c114 HWREG(OCP_SHARED_BASE + getPadOffset(hwAttrs->capturePin)) in CaptureCC32XX_close()
394 HWREG(OCP_SHARED_BASE + getPadOffset(hwAttrs->capturePin)) in initHw()
/hal_ti-3.4.0/simplelink/source/ti/drivers/adc/
DADCCC32XX.c61 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0)
/hal_ti-3.4.0/simplelink/source/ti/drivers/power/
DPowerCC32XX.c310 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_18) = 0x281; in Power_init()
313 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_19) = 0x281; in Power_init()
689 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_ALT_PC_VAL_APPS) = 1; in Power_sleep()
770 HWREG(OCP_SHARED_BASE + OCP_SHARED_O_ALT_PC_VAL_APPS) = 0; in Power_sleep()
/hal_ti-3.4.0/simplelink/source/ti/drivers/net/wifi/porting/
Dcc_pal.c71 #define NWP_SPARE_REG_5 (OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5)
/hal_ti-3.4.0/simplelink/source/ti/drivers/pwm/
DPWMTimerCC32XX.c66 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0)
/hal_ti-3.4.0/simplelink/source/ti/drivers/i2c/
DI2CCC32XX.c67 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0)
/hal_ti-3.4.0/simplelink/source/ti/drivers/spi/
DSPICC32XXDMA.c56 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0)
/hal_ti-3.4.0/simplelink/source/ti/drivers/uart/
DUARTCC32XXDMA.c71 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0)
DUARTCC32XX.c67 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0)
/hal_ti-3.4.0/simplelink/source/ti/drivers/sd/
DSDHostCC32XX.c72 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0)
/hal_ti-3.4.0/simplelink/source/ti/drivers/uart2/
DUART2CC32XX.c62 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0)
/hal_ti-3.4.0/simplelink/source/ti/drivers/i2s/
DI2SCC32XX.c69 #define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0)