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Searched refs:HIB1P2_BASE (Results 1 – 4 of 4) sorted by relevance

/hal_ti-3.4.0/simplelink/source/ti/devices/cc32xx/inc/
Dhw_memmap.h74 #define HIB1P2_BASE 0x4402F000 macro
/hal_ti-3.4.0/simplelink/source/ti/devices/cc32xx/driverlib/
Dflash.c145 HWREG(HIB1P2_BASE + HIB1P2_O_PORPOL_SPARE) = 0xFFFF0000; in FlashDisable()
162 HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; in FlashDisable()
Dprcm.c703 HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; in PRCMLPDSEnter()
770 HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; in PRCMLPDSEnterKeepDebugIf()
1349 ullRTCVal = HWREG(HIB1P2_BASE + HIB1P2_O_HIB_RTC_TIMER_MSW_1P2); in PRCMSlowClkCtrFastGet()
1351 ullRTCVal |= HWREG(HIB1P2_BASE + HIB1P2_O_HIB_RTC_TIMER_LSW_1P2); in PRCMSlowClkCtrFastGet()
1952 HWREG(HIB1P2_BASE+HIB1P2_O_CM_OSC_16M_CONFIG) = 0x00010008; in PRCMCC3200MCUInit()
/hal_ti-3.4.0/simplelink/source/ti/drivers/net/wifi/porting/
Dcc_pal.c79 #define ANA_DCDC_PARAMS0 (HIB1P2_BASE + HIB1P2_O_ANA_DCDC_PARAMETERS0)