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Searched refs:DTHE_BASE (Results 1 – 5 of 5) sorted by relevance

/hal_ti-3.4.0/simplelink/source/ti/devices/cc32xx/driverlib/
Dcrc.c103 ASSERT(ui32Base == DTHE_BASE); in CRCConfigSet()
148 ASSERT(ui32Base == DTHE_BASE); in CRCSeedSet()
181 ASSERT(ui32Base == DTHE_BASE); in CRCDataWrite()
186 HWREG(DTHE_BASE + DTHE_O_CRC_DIN) = ui32Data; in CRCDataWrite()
209 ASSERT(ui32Base == DTHE_BASE); in CRCResultRead()
214 return(HWREG(DTHE_BASE + DTHE_O_CRC_RSLT_PP)); in CRCResultRead()
254 ASSERT(ui32Base == DTHE_BASE); in CRCDataProcess()
Ddes.c607 ui32IntStatus |= ((HWREG(DTHE_BASE + DTHE_O_DES_MIS) & 0x7) << 16); in DESIntStatus()
614 ui32IntStatus |= ((HWREG(DTHE_BASE + DTHE_O_DES_MIS) & 0xD) << 16); in DESIntStatus()
656 HWREG(DTHE_BASE + DTHE_O_DES_IM) &= ~((ui32IntFlags & 0x00070000) >> 16); in DESIntEnable()
698 HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x00070000) >> 16); in DESIntDisable()
734 HWREG(DTHE_BASE + DTHE_O_DES_IC) = ((ui32IntFlags & 0x00070000) >> 16); in DESIntClear()
Dshamd5.c148 ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_MIS); in SHAMD5IntStatus()
155 ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_RIS); in SHAMD5IntStatus()
197 HWREG(DTHE_BASE + DTHE_O_SHA_IM) &= ~((ui32IntFlags & 0x00070000) >> 16); in SHAMD5IntEnable()
240 HWREG(DTHE_BASE + DTHE_O_SHA_IM) |= ((ui32IntFlags & 0x00070000) >> 16); in SHAMD5IntDisable()
286 HWREG(DTHE_BASE + DTHE_O_SHA_IC) = ((ui32IntFlags & 0x00070000) >> 16); in SHAMD5IntClear()
Daes.c1057 ui32Temp = HWREG(DTHE_BASE + DTHE_O_AES_MIS); in AESIntStatus()
1064 ui32Temp = HWREG(DTHE_BASE + DTHE_O_AES_RIS); in AESIntStatus()
1115 HWREG(DTHE_BASE + DTHE_O_AES_IM) &= ~((ui32IntFlags & 0x000F0000) >> 16); in AESIntEnable()
1164 HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x000F0000) >> 16); in AESIntDisable()
1202 HWREG(DTHE_BASE + DTHE_O_AES_IC) = ((ui32IntFlags >> 16) & 0x0000000F); in AESIntClear()
/hal_ti-3.4.0/simplelink/source/ti/devices/cc32xx/inc/
Dhw_memmap.h76 #define DTHE_BASE 0x44030000 macro