1 //***************************************************************************** 2 // 3 // Copyright (C) 2013 - 2015 Texas Instruments Incorporated - http://www.ti.com/ 4 // 5 // Redistribution and use in source and binary forms, with or without 6 // modification, are permitted provided that the following conditions 7 // are met: 8 // 9 // Redistributions of source code must retain the above copyright 10 // notice, this list of conditions and the following disclaimer. 11 // 12 // Redistributions in binary form must reproduce the above copyright 13 // notice, this list of conditions and the following disclaimer in the 14 // documentation and/or other materials provided with the 15 // distribution. 16 // 17 // Neither the name of Texas Instruments Incorporated nor the names of 18 // its contributors may be used to endorse or promote products derived 19 // from this software without specific prior written permission. 20 // 21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 // 33 // MSP430 intrinsic redefinitions for use with MSP432 Family Devices 34 // 35 //**************************************************************************** 36 37 /****************************************************************************** 38 * Definitions for 8/16/32-bit wide memory access * 39 ******************************************************************************/ 40 #define HWREG8(x) (*((volatile uint8_t *)(x))) 41 #define HWREG16(x) (*((volatile uint16_t *)(x))) 42 #define HWREG32(x) (*((volatile uint32_t *)(x))) 43 #define HWREG(x) (HWREG16(x)) 44 #define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x))) 45 #define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1))) 46 #define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x))) 47 #define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1))) 48 49 /****************************************************************************** 50 * Definitions for 8/16/32-bit wide bit band access * 51 ******************************************************************************/ 52 #define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))) 53 #define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))) 54 #define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))) 55 56 // Intrinsics with ARM equivalents 57 #if defined ( __TI_ARM__ ) /* TI CGT Compiler */ 58 59 #include <cmsis_ccs.h> 60 61 #define __sleep() __wfi() 62 #define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } 63 #define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } 64 #define __get_SP_register() __get_MSP() 65 #define __set_SP_register(x) __set_MSP(x) 66 #define __get_interrupt_state() __get_PRIMASK() 67 #define __set_interrupt_state(x) __set_PRIMASK(x) 68 #define __enable_interrupt() _enable_IRQ() 69 #define __enable_interrupts() _enable_IRQ() 70 #define __disable_interrupt() _disable_IRQ() 71 #define __disable_interrupts() _disable_IRQ() 72 #define __no_operation() __asm(" nop") 73 74 #elif defined ( __ICCARM__ ) /* IAR Compiler */ 75 76 #include <stdint.h> 77 78 #define __INLINE inline 79 #include <cmsis_iar.h> 80 81 #define __sleep() __WFI() 82 #define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __WFI(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } 83 #define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } 84 #define __get_SP_register() __get_MSP() 85 #define __set_SP_register() __set_MSP() 86 #define __get_interrupt_state() __get_PRIMASK() 87 #define __set_interrupt_state(x) __set_PRIMASK(x) 88 #define __enable_interrupt() __asm(" cpsie i") 89 #define __enable_interrupts() __asm(" cpsie i") 90 #define __disable_interrupt() __asm(" cpsid i") 91 #define __disable_interrupts() __asm(" cpsid i") 92 #define __no_operation() __asm(" nop") 93 94 // Intrinsics without ARM equivalents 95 #define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 96 #define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 97 #define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 98 #define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 99 #define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 100 #define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 101 #define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 102 #define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 103 #define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 104 #define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 105 #define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 106 #define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 107 #define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } 108 #define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } 109 #define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ } 110 111 #elif defined ( __CC_ARM ) /* ARM Compiler */ 112 113 #define __sleep() __wfi() 114 #define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } 115 #define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } 116 #define __get_SP_register() __get_MSP() 117 #define __set_SP_register(x) __set_MSP(x) 118 #define __get_interrupt_state() __get_PRIMASK() 119 #define __set_interrupt_state(x) __set_PRIMASK(x) 120 #define __enable_interrupt() __asm(" cpsie i") 121 #define __enable_interrupts() __asm(" cpsie i") 122 #define __disable_interrupt() __asm(" cpsid i") 123 #define __disable_interrupts() __asm(" cpsid i") 124 #define __no_operation() __asm(" nop") 125 126 // Intrinsics without ARM equivalents 127 #define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 128 #define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 129 #define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 130 #define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 131 #define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 132 #define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 133 #define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 134 #define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 135 #define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 136 #define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 137 #define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 138 #define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 139 #define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } 140 #define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } 141 #define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ } 142 143 #elif defined ( __GNUC__ ) /* GCC Compiler */ 144 #undef __wfi 145 #define __wfi() __asm(" wfi") 146 #define __sleep() __wfi() 147 #define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } 148 #define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } 149 #define __get_SP_register() __get_MSP() 150 #define __set_SP_register(x) __set_MSP(x) 151 #define __get_interrupt_state() __get_PRIMASK() 152 #define __set_interrupt_state(x) __set_PRIMASK(x) 153 #define __enable_interrupt() __asm(" cpsie i") 154 #define __enable_interrupts() __asm(" cpsie i") 155 #define __disable_interrupt() __asm(" cpsid i") 156 #define __disable_interrupts() __asm(" cpsid i") 157 #define __no_operation() __asm(" nop") 158 159 // Intrinsics without ARM equivalents 160 #define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 161 #define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 162 #define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 163 #define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 164 #define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 165 #define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 166 #define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 167 #define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 168 #define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 169 #define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 170 #define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 171 #define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } 172 #define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } 173 #define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } 174 #define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ } 175 176 #endif 177 178 // Intrinsics without ARM equivalents 179 #define __low_power_mode_0() { __sleep(); } 180 #define __low_power_mode_1() { __sleep(); } 181 #define __low_power_mode_2() { __sleep(); } 182 #define __low_power_mode_3() { __deep_sleep(); } 183 #define __low_power_mode_4() { __deep_sleep(); } 184 #define __data16_read_addr(x) (*((volatile uint32_t *)(x))) 185 #define __data20_read_char(x) (*((volatile uint8_t *)(x))) 186 #define __data20_read_short(x) (*((volatile uint16_t *)(x))) 187 #define __data20_read_long(x) (*((volatile uint32_t *)(x))) 188 #define __data16_write_addr(x,y) { (*((volatile uint32_t *)(x))) } 189 #define __get_SR_register() 0 190 #define __get_SR_register_on_exit() 0 191 192 // the following defines are deprecated and will be removed in future releases 193 #define ATLBASE ALTBASE 194 #define CS_CTL1_SELM_7 ((uint32_t)0x00000007) /*!< for future use. Defaults to DCOCLK. Not recommended for use to ensure future */ 195 /* compatibilities. */ 196 #define CS_CTL1_SELS_7 ((uint32_t)0x00000070) /*!< for furture use. Defaults to DCOCLK. Do not use to ensure future */ 197 /* compatibilities. */ 198 #define CS_CTL1_SELA_3 ((uint32_t)0x00000300) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ 199 /* compatibilities. */ 200 #define CS_CTL1_SELA_4 ((uint32_t)0x00000400) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ 201 /* compatibilities. */ 202 #define CS_CTL1_SELA_5 ((uint32_t)0x00000500) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ 203 /* compatibilities. */ 204 #define CS_CTL1_SELA_6 ((uint32_t)0x00000600) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ 205 /* compatibilities. */ 206 #define CS_CTL1_SELA_7 ((uint32_t)0x00000700) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ 207 /* compatibilities. */ 208 /* CS_CTL2[LFXTAGCOFF] Bits */ 209 #define CS_CTL2_LFXTAGCOFF_OFS ( 7) /*!< LFXTAGCOFF Bit Offset */ 210 #define CS_CTL2_LFXTAGCOFF ((uint32_t)0x00000080) /*!< Disables the automatic gain control of the LFXT crystal */ 211 212 /* CS_CTL3[FCNTHF2] Bits */ 213 #define CS_CTL3_FCNTHF2_OFS ( 8) /*!< FCNTHF2 Bit Offset */ 214 #define CS_CTL3_FCNTHF2_MASK ((uint32_t)0x00000300) /*!< FCNTHF2 Bit Mask */ 215 #define CS_CTL3_FCNTHF20 ((uint32_t)0x00000100) /*!< FCNTHF2 Bit 0 */ 216 #define CS_CTL3_FCNTHF21 ((uint32_t)0x00000200) /*!< FCNTHF2 Bit 1 */ 217 #define CS_CTL3_FCNTHF2_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ 218 #define CS_CTL3_FCNTHF2_1 ((uint32_t)0x00000100) /*!< 4096 cycles */ 219 #define CS_CTL3_FCNTHF2_2 ((uint32_t)0x00000200) /*!< 8192 cycles */ 220 #define CS_CTL3_FCNTHF2_3 ((uint32_t)0x00000300) /*!< 16384 cycles */ 221 #define CS_CTL3_FCNTHF2__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ 222 #define CS_CTL3_FCNTHF2__4096 ((uint32_t)0x00000100) /*!< 4096 cycles */ 223 #define CS_CTL3_FCNTHF2__8192 ((uint32_t)0x00000200) /*!< 8192 cycles */ 224 #define CS_CTL3_FCNTHF2__16384 ((uint32_t)0x00000300) /*!< 16384 cycles */ 225 /* CS_CTL3[RFCNTHF2] Bits */ 226 #define CS_CTL3_RFCNTHF2_OFS (10) /*!< RFCNTHF2 Bit Offset */ 227 #define CS_CTL3_RFCNTHF2 ((uint32_t)0x00000400) /*!< Reset start fault counter for HFXT2 */ 228 /* CS_CTL3[FCNTHF2_EN] Bits */ 229 #define CS_CTL3_FCNTHF2_EN_OFS (11) /*!< FCNTHF2_EN Bit Offset */ 230 #define CS_CTL3_FCNTHF2_EN ((uint32_t)0x00000800) /*!< Enable start fault counter for HFXT2 */ 231 /* CS_STAT[HFXT2_ON] Bits */ 232 #define CS_STAT_HFXT2_ON_OFS ( 3) /*!< HFXT2_ON Bit Offset */ 233 #define CS_STAT_HFXT2_ON ((uint32_t)0x00000008) /*!< HFXT2 status */ 234 /* CS_IE[HFXT2IE] Bits */ 235 #define CS_IE_HFXT2IE_OFS ( 2) /*!< HFXT2IE Bit Offset */ 236 #define CS_IE_HFXT2IE ((uint32_t)0x00000004) /*!< HFXT2 oscillator fault flag interrupt enable */ 237 /* CS_IE[FCNTHF2IE] Bits */ 238 #define CS_IE_FCNTHF2IE_OFS (10) /*!< FCNTHF2IE Bit Offset */ 239 #define CS_IE_FCNTHF2IE ((uint32_t)0x00000400) /*!< Start fault counter interrupt enable HFXT2 */ 240 /* CS_IE[PLLOOLIE] Bits */ 241 #define CS_IE_PLLOOLIE_OFS (12) /*!< PLLOOLIE Bit Offset */ 242 #define CS_IE_PLLOOLIE ((uint32_t)0x00001000) /*!< PLL out-of-lock interrupt enable */ 243 /* CS_IE[PLLLOSIE] Bits */ 244 #define CS_IE_PLLLOSIE_OFS (13) /*!< PLLLOSIE Bit Offset */ 245 #define CS_IE_PLLLOSIE ((uint32_t)0x00002000) /*!< PLL loss-of-signal interrupt enable */ 246 /* CS_IE[PLLOORIE] Bits */ 247 #define CS_IE_PLLOORIE_OFS (14) /*!< PLLOORIE Bit Offset */ 248 #define CS_IE_PLLOORIE ((uint32_t)0x00004000) /*!< PLL out-of-range interrupt enable */ 249 /* CS_IE[CALIE] Bits */ 250 #define CS_IE_CALIE_OFS (15) /*!< CALIE Bit Offset */ 251 #define CS_IE_CALIE ((uint32_t)0x00008000) /*!< REFCNT period counter interrupt enable */ 252 /* CS_IFG[HFXT2IFG] Bits */ 253 #define CS_IFG_HFXT2IFG_OFS ( 2) /*!< HFXT2IFG Bit Offset */ 254 #define CS_IFG_HFXT2IFG ((uint32_t)0x00000004) /*!< HFXT2 oscillator fault flag */ 255 /* CS_IFG[FCNTHF2IFG] Bits */ 256 #define CS_IFG_FCNTHF2IFG_OFS (11) /*!< FCNTHF2IFG Bit Offset */ 257 #define CS_IFG_FCNTHF2IFG ((uint32_t)0x00000800) /*!< Start fault counter interrupt flag HFXT2 */ 258 /* CS_IFG[PLLOOLIFG] Bits */ 259 #define CS_IFG_PLLOOLIFG_OFS (12) /*!< PLLOOLIFG Bit Offset */ 260 #define CS_IFG_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock interrupt flag */ 261 /* CS_IFG[PLLLOSIFG] Bits */ 262 #define CS_IFG_PLLLOSIFG_OFS (13) /*!< PLLLOSIFG Bit Offset */ 263 #define CS_IFG_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal interrupt flag */ 264 /* CS_IFG[PLLOORIFG] Bits */ 265 #define CS_IFG_PLLOORIFG_OFS (14) /*!< PLLOORIFG Bit Offset */ 266 #define CS_IFG_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range interrupt flag */ 267 /* CS_IFG[CALIFG] Bits */ 268 #define CS_IFG_CALIFG_OFS (15) /*!< CALIFG Bit Offset */ 269 #define CS_IFG_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter expired */ 270 /* CS_CLRIFG[CLR_HFXT2IFG] Bits */ 271 #define CS_CLRIFG_CLR_HFXT2IFG_OFS ( 2) /*!< CLR_HFXT2IFG Bit Offset */ 272 #define CS_CLRIFG_CLR_HFXT2IFG ((uint32_t)0x00000004) /*!< Clear HFXT2 oscillator fault interrupt flag */ 273 /* CS_CLRIFG[CLR_CALIFG] Bits */ 274 #define CS_CLRIFG_CLR_CALIFG_OFS (15) /*!< CLR_CALIFG Bit Offset */ 275 #define CS_CLRIFG_CLR_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter clear interrupt flag */ 276 /* CS_CLRIFG[CLR_FCNTHF2IFG] Bits */ 277 #define CS_CLRIFG_CLR_FCNTHF2IFG_OFS (10) /*!< CLR_FCNTHF2IFG Bit Offset */ 278 #define CS_CLRIFG_CLR_FCNTHF2IFG ((uint32_t)0x00000400) /*!< Start fault counter clear interrupt flag HFXT2 */ 279 /* CS_CLRIFG[CLR_PLLOOLIFG] Bits */ 280 #define CS_CLRIFG_CLR_PLLOOLIFG_OFS (12) /*!< CLR_PLLOOLIFG Bit Offset */ 281 #define CS_CLRIFG_CLR_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock clear interrupt flag */ 282 /* CS_CLRIFG[CLR_PLLLOSIFG] Bits */ 283 #define CS_CLRIFG_CLR_PLLLOSIFG_OFS (13) /*!< CLR_PLLLOSIFG Bit Offset */ 284 #define CS_CLRIFG_CLR_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal clear interrupt flag */ 285 /* CS_CLRIFG[CLR_PLLOORIFG] Bits */ 286 #define CS_CLRIFG_CLR_PLLOORIFG_OFS (14) /*!< CLR_PLLOORIFG Bit Offset */ 287 #define CS_CLRIFG_CLR_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range clear interrupt flag */ 288 /* CS_SETIFG[SET_HFXT2IFG] Bits */ 289 #define CS_SETIFG_SET_HFXT2IFG_OFS ( 2) /*!< SET_HFXT2IFG Bit Offset */ 290 #define CS_SETIFG_SET_HFXT2IFG ((uint32_t)0x00000004) /*!< Set HFXT2 oscillator fault interrupt flag */ 291 /* CS_SETIFG[SET_CALIFG] Bits */ 292 #define CS_SETIFG_SET_CALIFG_OFS (15) /*!< SET_CALIFG Bit Offset */ 293 #define CS_SETIFG_SET_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter set interrupt flag */ 294 /* CS_SETIFG[SET_FCNTHF2IFG] Bits */ 295 #define CS_SETIFG_SET_FCNTHF2IFG_OFS (10) /*!< SET_FCNTHF2IFG Bit Offset */ 296 #define CS_SETIFG_SET_FCNTHF2IFG ((uint32_t)0x00000400) /*!< Start fault counter set interrupt flag HFXT2 */ 297 /* CS_SETIFG[SET_PLLOOLIFG] Bits */ 298 #define CS_SETIFG_SET_PLLOOLIFG_OFS (12) /*!< SET_PLLOOLIFG Bit Offset */ 299 #define CS_SETIFG_SET_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock set interrupt flag */ 300 /* CS_SETIFG[SET_PLLLOSIFG] Bits */ 301 #define CS_SETIFG_SET_PLLLOSIFG_OFS (13) /*!< SET_PLLLOSIFG Bit Offset */ 302 #define CS_SETIFG_SET_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal set interrupt flag */ 303 /* CS_SETIFG[SET_PLLOORIFG] Bits */ 304 #define CS_SETIFG_SET_PLLOORIFG_OFS (14) /*!< SET_PLLOORIFG Bit Offset */ 305 #define CS_SETIFG_SET_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range set interrupt flag */ 306 307 /* EUSCI_x_CTLW0[SSEL] Bits */ 308 #define EUSCI_A_CTLW0_SSEL_0 ((uint16_t)0x0000) /*!< Reserved */ 309 #define EUSCI_B_CTLW0_SSEL_0 ((uint16_t)0x0000) /*!< Reserved */ 310 #define EUSCI_B_CTLW0_SSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ 311 312 /* RSTCTL_PSSRESET_STAT[SVSL] Bits */ 313 #define RSTCTL_PSSRESET_STAT_SVSL_OFS ( 0) /*!< SVSL Bit Offset */ 314 #define RSTCTL_PSSRESET_STAT_SVSL ((uint32_t)0x00000001) /*!< Indicates if POR was caused by an SVSL trip condition in the PSS */ 315 316 /* SYSCTL_SYSTEM_STAT[DBG_SEC_ACT] Bits */ 317 #define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS ( 3) /*!< DBG_SEC_ACT Bit Offset */ 318 #define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT ((uint32_t)0x00000008) /*!< Debug Security active */ 319 /* SYSCTL_SYSTEM_STAT[JTAG_SWD_LOCK_ACT] Bits */ 320 #define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS ( 4) /*!< JTAG_SWD_LOCK_ACT Bit Offset */ 321 #define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT ((uint32_t)0x00000010) /*!< Indicates if JTAG and SWD Lock is active */ 322 /* SYSCTL_SYSTEM_STAT[IP_PROT_ACT] Bits */ 323 #define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS ( 5) /*!< IP_PROT_ACT Bit Offset */ 324 #define SYSCTL_SYSTEM_STAT_IP_PROT_ACT ((uint32_t)0x00000020) /*!< Indicates if IP protection is active */ 325 326
