1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 35 #ifndef __HW_APPS_CONFIG_H__ 36 #define __HW_APPS_CONFIG_H__ 37 38 //***************************************************************************** 39 // 40 // The following are defines for the APPS_CONFIG register offsets. 41 // 42 //***************************************************************************** 43 #define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \ 44 0x00000000 // Patch trap address Register 45 // array 46 47 #define APPS_CONFIG_O_PATCH_TRAP_EN_REG \ 48 0x00000078 49 50 #define APPS_CONFIG_O_FAULT_STATUS_REG \ 51 0x0000007C 52 53 #define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \ 54 0x00000080 55 56 #define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \ 57 0x00000084 58 59 #define APPS_CONFIG_O_DMA_DONE_INT_MASK \ 60 0x0000008C 61 62 #define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \ 63 0x00000090 64 65 #define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \ 66 0x00000094 67 68 #define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \ 69 0x00000098 70 71 #define APPS_CONFIG_O_DMA_DONE_INT_ACK \ 72 0x0000009C 73 74 #define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \ 75 0x000000A0 76 77 #define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \ 78 0x000000A4 79 80 #define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \ 81 0x000000A8 82 83 #define APPS_CONFIG_O_RESERVD_REG_0 \ 84 0x000000AC 85 86 #define APPS_CONFIG_O_GPT_TRIG_SEL \ 87 0x000000B0 88 89 #define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \ 90 0x000000B4 91 92 #define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \ 93 0x000000B8 94 95 96 97 98 //****************************************************************************** 99 // 100 // The following are defines for the bit fields in the 101 // APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register. 102 // 103 //****************************************************************************** 104 #define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \ 105 0xFFFFFFFF // When PATCH_TRAP_EN[n] is set bus 106 // fault is generated for the 107 // address 108 // PATCH_TRAP_ADDR_REG[n][31:0] from 109 // Idcode bus. The exception routine 110 // should take care to jump to the 111 // location where the patch 112 // correspond to this address is 113 // kept. 114 115 #define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0 116 //****************************************************************************** 117 // 118 // The following are defines for the bit fields in the 119 // APPS_CONFIG_O_PATCH_TRAP_EN_REG register. 120 // 121 //****************************************************************************** 122 #define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \ 123 0x3FFFFFFF // When PATCH_TRAP_EN[n] is set bus 124 // fault is generated for the 125 // address PATCH_TRAP_ADD[n][31:0] 126 // from Idcode bus. The exception 127 // routine should take care to jump 128 // to the location where the patch 129 // correspond to this address is 130 // kept. 131 132 #define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0 133 //****************************************************************************** 134 // 135 // The following are defines for the bit fields in the 136 // APPS_CONFIG_O_FAULT_STATUS_REG register. 137 // 138 //****************************************************************************** 139 #define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \ 140 0x0000003E // This field shows because of 141 // which patch trap address the 142 // bus_fault is generated. If the 143 // PATCH_ERR bit is set, then it 144 // means the bus fault is generated 145 // because of 146 // PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX] 147 148 #define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1 149 #define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \ 150 0x00000001 // This bit is set when there is a 151 // bus fault because of patched 152 // address access to the Apps boot 153 // rom. Write 0 to clear this 154 // register. 155 156 //****************************************************************************** 157 // 158 // The following are defines for the bit fields in the 159 // APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register. 160 // 161 //****************************************************************************** 162 #define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \ 163 0x00000001 // This bit is set when there is a 164 // an error in memss write access. 165 // And the address causing this 166 // error is captured in 167 // MEMSS_ERR_ADDR_REG. To capture 168 // the next error address one have 169 // to clear this bit. 170 171 //****************************************************************************** 172 // 173 // The following are defines for the bit fields in the 174 // APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register. 175 // 176 //****************************************************************************** 177 //****************************************************************************** 178 // 179 // The following are defines for the bit fields in the 180 // APPS_CONFIG_O_DMA_DONE_INT_MASK register. 181 // 182 //****************************************************************************** 183 #define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \ 184 0x0000F000 // 1= disable corresponding 185 // interrupt;0 = interrupt enabled 186 // bit 14: ADC channel 7 interrupt 187 // enable/disable bit 13: ADC 188 // channel 5 interrupt 189 // enable/disable bit 12: ADC 190 // channel 3 interrupt 191 // enable/disable bit 11: ADC 192 // channel 1 interrupt 193 // enable/disable 194 195 #define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12 196 #define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \ 197 0x00000800 // 1= disable corresponding 198 // interrupt;0 = interrupt enabled 199 200 #define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \ 201 0x00000400 // 1= disable corresponding 202 // interrupt;0 = interrupt enabled 203 204 #define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \ 205 0x00000200 // 1= disable corresponding 206 // interrupt;0 = interrupt enabled 207 208 #define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \ 209 0x00000100 // 1= disable corresponding 210 // interrupt;0 = interrupt enabled 211 212 #define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \ 213 0x00000080 // 1= disable corresponding 214 // interrupt;0 = interrupt enabled 215 216 #define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \ 217 0x00000040 // 1= disable corresponding 218 // interrupt;0 = interrupt enabled 219 220 #define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \ 221 0x00000020 // 1= disable corresponding 222 // interrupt;0 = interrupt enabled 223 224 #define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \ 225 0x00000010 // 1= disable corresponding 226 // interrupt;0 = interrupt enabled 227 228 #define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \ 229 0x00000008 // 1= disable corresponding 230 // interrupt;0 = interrupt enabled 231 232 #define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \ 233 0x00000004 // 1= disable corresponding 234 // interrupt;0 = interrupt enabled 235 236 #define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \ 237 0x00000002 // 1= disable corresponding 238 // interrupt;0 = interrupt enabled 239 240 #define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \ 241 0x00000001 // 1= disable corresponding 242 // interrupt;0 = interrupt enabled 243 244 //****************************************************************************** 245 // 246 // The following are defines for the bit fields in the 247 // APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register. 248 // 249 //****************************************************************************** 250 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \ 251 0x0000F000 // write 1 to set mask of the 252 // corresponding DMA DONE IRQ;0 = no 253 // effect bit 14: ADC channel 7 DMA 254 // Done IRQ bit 13: ADC channel 5 255 // DMA Done IRQ bit 12: ADC channel 256 // 3 DMA Done IRQ bit 11: ADC 257 // channel 1 DMA Done IRQ 258 259 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12 260 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \ 261 0x00000800 // write 1 to set mask of the 262 // corresponding DMA DONE IRQ;0 = no 263 // effect 264 265 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \ 266 0x00000400 // write 1 to set mask of the 267 // corresponding DMA DONE IRQ;0 = no 268 // effect 269 270 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \ 271 0x00000200 // write 1 to set mask of the 272 // corresponding DMA DONE IRQ;0 = no 273 // effect 274 275 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \ 276 0x00000100 // write 1 to set mask of the 277 // corresponding DMA DONE IRQ;0 = no 278 // effect 279 280 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \ 281 0x00000080 // write 1 to set mask of the 282 // corresponding DMA DONE IRQ;0 = no 283 // effect 284 285 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \ 286 0x00000040 // write 1 to set mask of the 287 // corresponding DMA DONE IRQ;0 = no 288 // effect 289 290 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \ 291 0x00000020 // write 1 to set mask of the 292 // corresponding DMA DONE IRQ;0 = no 293 // effect 294 295 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \ 296 0x00000010 // write 1 to set mask of the 297 // corresponding DMA DONE IRQ;0 = no 298 // effect 299 300 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \ 301 0x00000008 // write 1 to set mask of the 302 // corresponding DMA DONE IRQ;0 = no 303 // effect 304 305 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \ 306 0x00000004 // write 1 to set mask of the 307 // corresponding DMA DONE IRQ;0 = no 308 // effect 309 310 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \ 311 0x00000002 // write 1 to set mask of the 312 // corresponding DMA DONE IRQ;0 = no 313 // effect 314 315 #define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \ 316 0x00000001 // write 1 to set mask of the 317 // corresponding DMA DONE IRQ;0 = no 318 // effect 319 320 //****************************************************************************** 321 // 322 // The following are defines for the bit fields in the 323 // APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register. 324 // 325 //****************************************************************************** 326 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \ 327 0x0000F000 // write 1 to clear mask of the 328 // corresponding DMA DONE IRQ;0 = no 329 // effect bit 14: ADC channel 7 DMA 330 // Done IRQ mask bit 13: ADC channel 331 // 5 DMA Done IRQ mask bit 12: ADC 332 // channel 3 DMA Done IRQ mask bit 333 // 11: ADC channel 1 DMA Done IRQ 334 // mask 335 336 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12 337 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \ 338 0x00000800 // write 1 to clear mask of the 339 // corresponding DMA DONE IRQ;0 = no 340 // effect 341 342 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \ 343 0x00000400 // write 1 to clear mask of the 344 // corresponding DMA DONE IRQ;0 = no 345 // effect 346 347 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \ 348 0x00000200 // write 1 to clear mask of the 349 // corresponding DMA DONE IRQ;0 = no 350 // effect 351 352 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \ 353 0x00000100 // write 1 to clear mask of the 354 // corresponding DMA DONE IRQ;0 = no 355 // effect 356 357 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \ 358 0x00000080 // write 1 to clear mask of the 359 // corresponding DMA DONE IRQ;0 = no 360 // effect 361 362 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \ 363 0x00000040 // write 1 to clear mask of the 364 // corresponding DMA DONE IRQ;0 = no 365 // effect 366 367 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \ 368 0x00000020 // write 1 to clear mask of the 369 // corresponding DMA DONE IRQ;0 = no 370 // effect 371 372 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \ 373 0x00000010 // write 1 to clear mask of the 374 // corresponding DMA DONE IRQ;0 = no 375 // effect 376 377 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \ 378 0x00000008 // write 1 to clear mask of the 379 // corresponding DMA DONE IRQ;0 = no 380 // effect 381 382 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \ 383 0x00000004 // write 1 to clear mask of the 384 // corresponding DMA DONE IRQ;0 = no 385 // effect 386 387 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \ 388 0x00000002 // write 1 to clear mask of the 389 // corresponding DMA DONE IRQ;0 = no 390 // effect 391 392 #define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \ 393 0x00000001 // write 1 to clear mask of the 394 // corresponding DMA DONE IRQ;0 = no 395 // effect 396 397 //****************************************************************************** 398 // 399 // The following are defines for the bit fields in the 400 // APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register. 401 // 402 //****************************************************************************** 403 #define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \ 404 0xFFFFFFFF // write 1 or 0 to clear all 405 // DMA_DONE interrupt; 406 407 #define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0 408 //****************************************************************************** 409 // 410 // The following are defines for the bit fields in the 411 // APPS_CONFIG_O_DMA_DONE_INT_ACK register. 412 // 413 //****************************************************************************** 414 #define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \ 415 0x0000F000 // write 1 to clear corresponding 416 // interrupt; 0 = no effect; bit 14: 417 // ADC channel 7 DMA Done IRQ bit 418 // 13: ADC channel 5 DMA Done IRQ 419 // bit 12: ADC channel 3 DMA Done 420 // IRQ bit 11: ADC channel 1 DMA 421 // Done IRQ 422 423 #define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12 424 #define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \ 425 0x00000800 // write 1 to clear corresponding 426 // interrupt; 0 = no effect; 427 428 #define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \ 429 0x00000400 // write 1 to clear corresponding 430 // interrupt; 0 = no effect; 431 432 #define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \ 433 0x00000200 // write 1 to clear corresponding 434 // interrupt; 0 = no effect; 435 436 #define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \ 437 0x00000100 // write 1 to clear corresponding 438 // interrupt; 0 = no effect; 439 440 #define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \ 441 0x00000080 // write 1 to clear corresponding 442 // interrupt; 0 = no effect; 443 444 #define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \ 445 0x00000040 // write 1 to clear corresponding 446 // interrupt; 0 = no effect; 447 448 #define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \ 449 0x00000020 // write 1 to clear corresponding 450 // interrupt; 0 = no effect; 451 452 #define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \ 453 0x00000010 // write 1 to clear corresponding 454 // interrupt; 0 = no effect; 455 456 #define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \ 457 0x00000008 // write 1 to clear corresponding 458 // interrupt; 0 = no effect; 459 460 #define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \ 461 0x00000004 // write 1 to clear corresponding 462 // interrupt; 0 = no effect; 463 464 #define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \ 465 0x00000002 // write 1 to clear corresponding 466 // interrupt; 0 = no effect; 467 468 #define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \ 469 0x00000001 // write 1 to clear corresponding 470 // interrupt; 0 = no effect; 471 472 //****************************************************************************** 473 // 474 // The following are defines for the bit fields in the 475 // APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register. 476 // 477 //****************************************************************************** 478 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \ 479 0x0000F000 // 1= corresponding interrupt is 480 // active and not masked. read is 481 // non-destructive;0 = corresponding 482 // interrupt is inactive or masked 483 // by DMA_DONE_INT mask bit 14: ADC 484 // channel 7 DMA Done IRQ bit 13: 485 // ADC channel 5 DMA Done IRQ bit 486 // 12: ADC channel 3 DMA Done IRQ 487 // bit 11: ADC channel 1 DMA Done 488 // IRQ 489 490 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12 491 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \ 492 0x00000800 // 1= corresponding interrupt is 493 // active and not masked. read is 494 // non-destructive;0 = corresponding 495 // interrupt is inactive or masked 496 // by DMA_DONE_INT mask 497 498 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \ 499 0x00000400 // 1= corresponding interrupt is 500 // active and not masked. read is 501 // non-destructive;0 = corresponding 502 // interrupt is inactive or masked 503 // by DMA_DONE_INT mask 504 505 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \ 506 0x00000200 // 1= corresponding interrupt is 507 // active and not masked. read is 508 // non-destructive;0 = corresponding 509 // interrupt is inactive or masked 510 // by DMA_DONE_INT mask 511 512 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \ 513 0x00000100 // 1= corresponding interrupt is 514 // active and not masked. read is 515 // non-destructive;0 = corresponding 516 // interrupt is inactive or masked 517 // by DMA_DONE_INT mask 518 519 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \ 520 0x00000080 // 1= corresponding interrupt is 521 // active and not masked. read is 522 // non-destructive;0 = corresponding 523 // interrupt is inactive or masked 524 // by DMA_DONE_INT mask 525 526 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \ 527 0x00000040 // 1= corresponding interrupt is 528 // active and not masked. read is 529 // non-destructive;0 = corresponding 530 // interrupt is inactive or masked 531 // by DMA_DONE_INT mask 532 533 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \ 534 0x00000020 // 1= corresponding interrupt is 535 // active and not masked. read is 536 // non-destructive;0 = corresponding 537 // interrupt is inactive or masked 538 // by DMA_DONE_INT mask 539 540 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \ 541 0x00000010 // 1= corresponding interrupt is 542 // active and not masked. read is 543 // non-destructive;0 = corresponding 544 // interrupt is inactive or masked 545 // by DMA_DONE_INT mask 546 547 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \ 548 0x00000008 // 1= corresponding interrupt is 549 // active and not masked. read is 550 // non-destructive;0 = corresponding 551 // interrupt is inactive or masked 552 // by DMA_DONE_INT mask 553 554 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \ 555 0x00000004 // 1= corresponding interrupt is 556 // active and not masked. read is 557 // non-destructive;0 = corresponding 558 // interrupt is inactive or masked 559 // by DMA_DONE_INT mask 560 561 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \ 562 0x00000002 // 1= corresponding interrupt is 563 // active and not masked. read is 564 // non-destructive;0 = corresponding 565 // interrupt is inactive or masked 566 // by DMA_DONE_INT mask 567 568 #define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \ 569 0x00000001 // 1= corresponding interrupt is 570 // active and not masked. read is 571 // non-destructive;0 = corresponding 572 // interrupt is inactive or masked 573 // by DMA_DONE_INT mask 574 575 //****************************************************************************** 576 // 577 // The following are defines for the bit fields in the 578 // APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register. 579 // 580 //****************************************************************************** 581 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \ 582 0x0000F000 // 1= corresponding interrupt is 583 // active. read is non-destructive;0 584 // = corresponding interrupt is 585 // inactive bit 14: ADC channel 7 586 // DMA Done IRQ bit 13: ADC channel 587 // 5 DMA Done IRQ bit 12: ADC 588 // channel 3 DMA Done IRQ bit 11: 589 // ADC channel 1 DMA Done IRQ 590 591 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12 592 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \ 593 0x00000800 // 1= corresponding interrupt is 594 // active. read is non-destructive;0 595 // = corresponding interrupt is 596 // inactive 597 598 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \ 599 0x00000400 // 1= corresponding interrupt is 600 // active. read is non-destructive;0 601 // = corresponding interrupt is 602 // inactive 603 604 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \ 605 0x00000200 // 1= corresponding interrupt is 606 // active. read is non-destructive;0 607 // = corresponding interrupt is 608 // inactive 609 610 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \ 611 0x00000100 // 1= corresponding interrupt is 612 // active. read is non-destructive;0 613 // = corresponding interrupt is 614 // inactive 615 616 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \ 617 0x00000080 // 1= corresponding interrupt is 618 // active. read is non-destructive;0 619 // = corresponding interrupt is 620 // inactive 621 622 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \ 623 0x00000040 // 1= corresponding interrupt is 624 // active. read is non-destructive;0 625 // = corresponding interrupt is 626 // inactive 627 628 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \ 629 0x00000020 // 1= corresponding interrupt is 630 // active. read is non-destructive;0 631 // = corresponding interrupt is 632 // inactive 633 634 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \ 635 0x00000010 // 1= corresponding interrupt is 636 // active. read is non-destructive;0 637 // = corresponding interrupt is 638 // inactive 639 640 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \ 641 0x00000008 // 1= corresponding interrupt is 642 // active. read is non-destructive;0 643 // = corresponding interrupt is 644 // inactive 645 646 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \ 647 0x00000004 // 1= corresponding interrupt is 648 // active. read is non-destructive;0 649 // = corresponding interrupt is 650 // inactive 651 652 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \ 653 0x00000002 // 1= corresponding interrupt is 654 // active. read is non-destructive;0 655 // = corresponding interrupt is 656 // inactive 657 658 #define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \ 659 0x00000001 // 1= corresponding interrupt is 660 // active. read is non-destructive;0 661 // = corresponding interrupt is 662 // inactive 663 664 //****************************************************************************** 665 // 666 // The following are defines for the bit fields in the 667 // APPS_CONFIG_O_FAULT_STATUS_CLR_REG register. 668 // 669 //****************************************************************************** 670 #define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \ 671 0x00000001 // Write 1 to clear the LSB of 672 // FAULT_STATUS_REG 673 674 //****************************************************************************** 675 // 676 // The following are defines for the bit fields in the 677 // APPS_CONFIG_O_RESERVD_REG_0 register. 678 // 679 //****************************************************************************** 680 //****************************************************************************** 681 // 682 // The following are defines for the bit fields in the 683 // APPS_CONFIG_O_GPT_TRIG_SEL register. 684 // 685 //****************************************************************************** 686 #define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \ 687 0x000000FF // This bit is implemented for GPT 688 // trigger mode select. GPT IP 689 // support 2 modes: RTC mode and 690 // external trigger. When this bit 691 // is set to logic '1': enable 692 // external trigger mode for APPS 693 // GPT CP0 and CP1 pin. bit 0: when 694 // set '1' enable external GPT 695 // trigger 0 on GPIO0 CP0 pin else 696 // RTC mode is selected. bit 1: when 697 // set '1' enable external GPT 698 // trigger 1 on GPIO0 CP1 pin else 699 // RTC mode is selected. bit 2: when 700 // set '1' enable external GPT 701 // trigger 2 on GPIO1 CP0 pin else 702 // RTC mode is selected. bit 3: when 703 // set '1' enable external GPT 704 // trigger 3 on GPIO1 CP1 pin else 705 // RTC mode is selected. bit 4: when 706 // set '1' enable external GPT 707 // trigger 4 on GPIO2 CP0 pin else 708 // RTC mode is selected. bit 5: when 709 // set '1' enable external GPT 710 // trigger 5 on GPIO2 CP1 pin else 711 // RTC mode is selected. bit 6: when 712 // set '1' enable external GPT 713 // trigger 6 on GPIO3 CP0 pin else 714 // RTC mode is selected. bit 7: when 715 // set '1' enable external GPT 716 // trigger 7 on GPIO3 CP1 pin else 717 // RTC mode is selected. 718 719 #define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0 720 //****************************************************************************** 721 // 722 // The following are defines for the bit fields in the 723 // APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register. 724 // 725 //****************************************************************************** 726 #define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \ 727 0x00000007 // Capture data from d2d_spare pads 728 729 #define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0 730 //****************************************************************************** 731 // 732 // The following are defines for the bit fields in the 733 // APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register. 734 // 735 //****************************************************************************** 736 #define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \ 737 0x00000007 // Send data to d2d_spare pads - 738 // eventually this will get 739 // registered in top die 740 741 #define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0 742 743 744 745 #endif // __HW_APPS_CONFIG_H__ 746
