1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_UDMA_H__ 35 #define __HW_UDMA_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the UDMA register offsets. 40 // 41 //***************************************************************************** 42 #define UDMA_O_STAT 0x00000000 43 #define UDMA_O_CFG 0x00000004 44 #define UDMA_O_CTLBASE 0x00000008 45 #define UDMA_O_ALTBASE 0x0000000C 46 #define UDMA_O_WAITSTAT 0x00000010 47 #define UDMA_O_SWREQ 0x00000014 48 #define UDMA_O_USEBURSTSET 0x00000018 49 #define UDMA_O_USEBURSTCLR 0x0000001C 50 #define UDMA_O_REQMASKSET 0x00000020 51 #define UDMA_O_REQMASKCLR 0x00000024 52 #define UDMA_O_ENASET 0x00000028 53 #define UDMA_O_ENACLR 0x0000002C 54 #define UDMA_O_ALTSET 0x00000030 55 #define UDMA_O_ALTCLR 0x00000034 56 #define UDMA_O_PRIOSET 0x00000038 57 #define UDMA_O_PRIOCLR 0x0000003C 58 #define UDMA_O_ERRCLR 0x0000004C 59 #define UDMA_O_CHASGN 0x00000500 60 #define UDMA_O_CHIS 0x00000504 61 #define UDMA_O_CHMAP0 0x00000510 62 #define UDMA_O_CHMAP1 0x00000514 63 #define UDMA_O_CHMAP2 0x00000518 64 #define UDMA_O_CHMAP3 0x0000051C 65 #define UDMA_O_PV 0x00000FB0 66 67 68 69 //****************************************************************************** 70 // 71 // The following are defines for the bit fields in the UDMA_O_STAT register. 72 // 73 //****************************************************************************** 74 #define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 75 #define UDMA_STAT_DMACHANS_S 16 76 #define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status 77 // 0x00000090 : UDMA_STAT_STATE_DONE 78 // : Done 0x00000000 : 79 // UDMA_STAT_STATE_IDLE : Idle 80 // 0x00000010 : 81 // UDMA_STAT_STATE_RD_CTRL : Reading 82 // channel controller data 83 // 0x00000030 : 84 // UDMA_STAT_STATE_RD_DSTENDP : 85 // Reading destination end pointer 86 // 0x00000040 : 87 // UDMA_STAT_STATE_RD_SRCDAT : 88 // Reading source data 0x00000020 : 89 // UDMA_STAT_STATE_RD_SRCENDP : 90 // Reading source end pointer 91 // 0x00000080 : 92 // UDMA_STAT_STATE_STALL : Stalled 93 // 0x000000A0 : 94 // UDMA_STAT_STATE_UNDEF : Undefined 95 // 0x00000060 : UDMA_STAT_STATE_WAIT 96 // : Waiting for uDMA request to 97 // clear 0x00000070 : 98 // UDMA_STAT_STATE_WR_CTRL : Writing 99 // channel controller data 100 // 0x00000050 : 101 // UDMA_STAT_STATE_WR_DSTDAT : 102 // Writing destination data 103 #define UDMA_STAT_STATE_S 4 104 #define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status 105 //****************************************************************************** 106 // 107 // The following are defines for the bit fields in the UDMA_O_CFG register. 108 // 109 //****************************************************************************** 110 #define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable 111 //****************************************************************************** 112 // 113 // The following are defines for the bit fields in the UDMA_O_CTLBASE register. 114 // 115 //****************************************************************************** 116 #define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address 117 #define UDMA_CTLBASE_ADDR_S 10 118 //****************************************************************************** 119 // 120 // The following are defines for the bit fields in the UDMA_O_ALTBASE register. 121 // 122 //****************************************************************************** 123 #define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address 124 // Pointer 125 #define UDMA_ALTBASE_ADDR_S 0 126 //****************************************************************************** 127 // 128 // The following are defines for the bit fields in the UDMA_O_WAITSTAT register. 129 // 130 //****************************************************************************** 131 #define UDMA_WAITSTAT_WAITREQ_M \ 132 0xFFFFFFFF // Channel [n] Wait Status 133 134 #define UDMA_WAITSTAT_WAITREQ_S 0 135 //****************************************************************************** 136 // 137 // The following are defines for the bit fields in the UDMA_O_SWREQ register. 138 // 139 //****************************************************************************** 140 #define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request 141 #define UDMA_SWREQ_S 0 142 //****************************************************************************** 143 // 144 // The following are defines for the bit fields in the 145 // UDMA_O_USEBURSTSET register. 146 // 147 //****************************************************************************** 148 #define UDMA_USEBURSTSET_SET_M \ 149 0xFFFFFFFF // Channel [n] Useburst Set 150 151 #define UDMA_USEBURSTSET_SET_S 0 152 //****************************************************************************** 153 // 154 // The following are defines for the bit fields in the 155 // UDMA_O_USEBURSTCLR register. 156 // 157 //****************************************************************************** 158 #define UDMA_USEBURSTCLR_CLR_M \ 159 0xFFFFFFFF // Channel [n] Useburst Clear 160 161 #define UDMA_USEBURSTCLR_CLR_S 0 162 //****************************************************************************** 163 // 164 // The following are defines for the bit fields in the UDMA_O_REQMASKSET register. 165 // 166 //****************************************************************************** 167 #define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set 168 #define UDMA_REQMASKSET_SET_S 0 169 //****************************************************************************** 170 // 171 // The following are defines for the bit fields in the UDMA_O_REQMASKCLR register. 172 // 173 //****************************************************************************** 174 #define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear 175 #define UDMA_REQMASKCLR_CLR_S 0 176 //****************************************************************************** 177 // 178 // The following are defines for the bit fields in the UDMA_O_ENASET register. 179 // 180 //****************************************************************************** 181 #define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set 182 #define UDMA_ENASET_CHENSET_S 0 183 //****************************************************************************** 184 // 185 // The following are defines for the bit fields in the UDMA_O_ENACLR register. 186 // 187 //****************************************************************************** 188 #define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear 189 #define UDMA_ENACLR_CLR_S 0 190 //****************************************************************************** 191 // 192 // The following are defines for the bit fields in the UDMA_O_ALTSET register. 193 // 194 //****************************************************************************** 195 #define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set 196 #define UDMA_ALTSET_SET_S 0 197 //****************************************************************************** 198 // 199 // The following are defines for the bit fields in the UDMA_O_ALTCLR register. 200 // 201 //****************************************************************************** 202 #define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear 203 #define UDMA_ALTCLR_CLR_S 0 204 //****************************************************************************** 205 // 206 // The following are defines for the bit fields in the UDMA_O_PRIOSET register. 207 // 208 //****************************************************************************** 209 #define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set 210 #define UDMA_PRIOSET_SET_S 0 211 //****************************************************************************** 212 // 213 // The following are defines for the bit fields in the UDMA_O_PRIOCLR register. 214 // 215 //****************************************************************************** 216 #define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear 217 #define UDMA_PRIOCLR_CLR_S 0 218 //****************************************************************************** 219 // 220 // The following are defines for the bit fields in the UDMA_O_ERRCLR register. 221 // 222 //****************************************************************************** 223 #define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status 224 //****************************************************************************** 225 // 226 // The following are defines for the bit fields in the UDMA_O_CHASGN register. 227 // 228 //****************************************************************************** 229 #define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select 230 #define UDMA_CHASGN_S 0 231 //****************************************************************************** 232 // 233 // The following are defines for the bit fields in the UDMA_O_CHIS register. 234 // 235 //****************************************************************************** 236 #define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status 237 #define UDMA_CHIS_S 0 238 //****************************************************************************** 239 // 240 // The following are defines for the bit fields in the UDMA_O_CHMAP0 register. 241 // 242 //****************************************************************************** 243 #define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select 244 #define UDMA_CHMAP0_CH7SEL_S 28 245 #define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select 246 #define UDMA_CHMAP0_CH6SEL_S 24 247 #define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select 248 #define UDMA_CHMAP0_CH5SEL_S 20 249 #define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select 250 #define UDMA_CHMAP0_CH4SEL_S 16 251 #define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select 252 #define UDMA_CHMAP0_CH3SEL_S 12 253 #define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select 254 #define UDMA_CHMAP0_CH2SEL_S 8 255 #define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select 256 #define UDMA_CHMAP0_CH1SEL_S 4 257 #define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select 258 #define UDMA_CHMAP0_CH0SEL_S 0 259 //****************************************************************************** 260 // 261 // The following are defines for the bit fields in the UDMA_O_CHMAP1 register. 262 // 263 //****************************************************************************** 264 #define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select 265 #define UDMA_CHMAP1_CH15SEL_S 28 266 #define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select 267 #define UDMA_CHMAP1_CH14SEL_S 24 268 #define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select 269 #define UDMA_CHMAP1_CH13SEL_S 20 270 #define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select 271 #define UDMA_CHMAP1_CH12SEL_S 16 272 #define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select 273 #define UDMA_CHMAP1_CH11SEL_S 12 274 #define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select 275 #define UDMA_CHMAP1_CH10SEL_S 8 276 #define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select 277 #define UDMA_CHMAP1_CH9SEL_S 4 278 #define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select 279 #define UDMA_CHMAP1_CH8SEL_S 0 280 //****************************************************************************** 281 // 282 // The following are defines for the bit fields in the UDMA_O_CHMAP2 register. 283 // 284 //****************************************************************************** 285 #define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select 286 #define UDMA_CHMAP2_CH23SEL_S 28 287 #define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select 288 #define UDMA_CHMAP2_CH22SEL_S 24 289 #define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select 290 #define UDMA_CHMAP2_CH21SEL_S 20 291 #define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select 292 #define UDMA_CHMAP2_CH20SEL_S 16 293 #define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select 294 #define UDMA_CHMAP2_CH19SEL_S 12 295 #define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select 296 #define UDMA_CHMAP2_CH18SEL_S 8 297 #define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select 298 #define UDMA_CHMAP2_CH17SEL_S 4 299 #define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select 300 #define UDMA_CHMAP2_CH16SEL_S 0 301 //****************************************************************************** 302 // 303 // The following are defines for the bit fields in the UDMA_O_CHMAP3 register. 304 // 305 //****************************************************************************** 306 #define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select 307 #define UDMA_CHMAP3_CH31SEL_S 28 308 #define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select 309 #define UDMA_CHMAP3_CH30SEL_S 24 310 #define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select 311 #define UDMA_CHMAP3_CH29SEL_S 20 312 #define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select 313 #define UDMA_CHMAP3_CH28SEL_S 16 314 #define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select 315 #define UDMA_CHMAP3_CH27SEL_S 12 316 #define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select 317 #define UDMA_CHMAP3_CH26SEL_S 8 318 #define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select 319 #define UDMA_CHMAP3_CH25SEL_S 4 320 #define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select 321 #define UDMA_CHMAP3_CH24SEL_S 0 322 //****************************************************************************** 323 // 324 // The following are defines for the bit fields in the UDMA_O_PV register. 325 // 326 //****************************************************************************** 327 #define UDMA_PV_MAJOR_M 0x0000FF00 // Major Revision 328 #define UDMA_PV_MAJOR_S 8 329 #define UDMA_PV_MINOR_M 0x000000FF // Minor Revision 330 #define UDMA_PV_MINOR_S 0 331 332 333 334 #endif // __HW_UDMA_H__ 335
