1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 //***************************************************************************** 34 // 35 // udma.h 36 // 37 // Prototypes and macros for the uDMA controller. 38 // 39 //***************************************************************************** 40 41 #ifndef __UDMA_H__ 42 #define __UDMA_H__ 43 44 //***************************************************************************** 45 // 46 // If building with a C++ compiler, make all of the definitions in this header 47 // have a C binding. 48 // 49 //***************************************************************************** 50 #ifdef __cplusplus 51 extern "C" 52 { 53 #endif 54 55 //***************************************************************************** 56 // 57 //! \addtogroup uDMA_Micro_Direct_Memory_Access_api 58 //! @{ 59 // 60 //***************************************************************************** 61 62 //***************************************************************************** 63 // 64 // A structure that defines an entry in the channel control table. These 65 // fields are used by the uDMA controller and normally it is not necessary for 66 // software to directly read or write fields in the table. 67 // 68 //***************************************************************************** 69 typedef struct 70 { 71 // 72 // The ending source address of the data transfer. 73 // 74 volatile void *pvSrcEndAddr; 75 76 // 77 // The ending destination address of the data transfer. 78 // 79 volatile void *pvDstEndAddr; 80 81 // 82 // The channel control mode. 83 // 84 volatile unsigned long ulControl; 85 86 // 87 // An unused location. 88 // 89 volatile unsigned long ulSpare; 90 } 91 tDMAControlTable; 92 93 //***************************************************************************** 94 // 95 //! A helper macro for building scatter-gather task table entries. 96 //! 97 //! \param ulTransferCount is the count of items to transfer for this task. 98 //! \param ulItemSize is the bit size of the items to transfer for this task. 99 //! \param ulSrcIncrement is the bit size increment for source data. 100 //! \param pvSrcAddr is the starting address of the data to transfer. 101 //! \param ulDstIncrement is the bit size increment for destination data. 102 //! \param pvDstAddr is the starting address of the destination data. 103 //! \param ulArbSize is the arbitration size to use for the transfer task. 104 //! \param ulMode is the transfer mode for this task. 105 //! 106 //! This macro is intended to be used to help populate a table of uDMA tasks 107 //! for a scatter-gather transfer. This macro will calculate the values for 108 //! the fields of a task structure entry based on the input parameters. 109 //! 110 //! There are specific requirements for the values of each parameter. No 111 //! checking is done so it is up to the caller to ensure that correct values 112 //! are used for the parameters. 113 //! 114 //! The \e ulTransferCount parameter is the number of items that will be 115 //! transferred by this task. It must be in the range 1-1024. 116 //! 117 //! The \e ulItemSize parameter is the bit size of the transfer data. It must 118 //! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. 119 //! 120 //! The \e ulSrcIncrement parameter is the increment size for the source data. 121 //! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, 122 //! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. 123 //! 124 //! The \e pvSrcAddr parameter is a void pointer to the beginning of the source 125 //! data. 126 //! 127 //! The \e ulDstIncrement parameter is the increment size for the destination 128 //! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, 129 //! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. 130 //! 131 //! The \e pvDstAddr parameter is a void pointer to the beginning of the 132 //! location where the data will be transferred. 133 //! 134 //! The \e ulArbSize parameter is the arbitration size for the transfer, and 135 //! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on 136 //! up to \b UDMA_ARB_1024. This is used to select the arbitration size in 137 //! powers of 2, from 1 to 1024. 138 //! 139 //! The \e ulMode parameter is the mode to use for this transfer task. It 140 //! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, 141 //! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note 142 //! that normally all tasks will be one of the scatter-gather modes while the 143 //! last task is a task list will be AUTO or BASIC. 144 //! 145 //! This macro is intended to be used to initialize individual entries of 146 //! a structure of tDMAControlTable type, like this: 147 //! 148 //! \verbatim 149 //! tDMAControlTable MyTaskList[] = 150 //! { 151 //! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, 152 //! UDMA_SRC_INC_8, MySourceBuf, 153 //! UDMA_DST_INC_8, MyDestBuf, 154 //! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), 155 //! uDMATaskStructEntry(Task2Count, ... ), 156 //! } 157 //! \endverbatim 158 //! 159 //! \return Nothing; this is not a function. 160 // 161 //***************************************************************************** 162 #define uDMATaskStructEntry(ulTransferCount, \ 163 ulItemSize, \ 164 ulSrcIncrement, \ 165 pvSrcAddr, \ 166 ulDstIncrement, \ 167 pvDstAddr, \ 168 ulArbSize, \ 169 ulMode) \ 170 { \ 171 (((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \ 172 ((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \ 173 ((ulSrcIncrement) >> 26)) - 1]))), \ 174 (((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \ 175 ((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \ 176 ((ulDstIncrement) >> 30)) - 1]))), \ 177 (ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \ 178 (((ulTransferCount) - 1) << 4) | \ 179 ((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ 180 ((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ 181 (ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \ 182 } 183 184 //***************************************************************************** 185 // 186 // Close the Doxygen group. 187 //! @} 188 // 189 //***************************************************************************** 190 191 //***************************************************************************** 192 // 193 // Flags that can be passed to uDMAChannelAttributeEnable(), 194 // uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). 195 // 196 //***************************************************************************** 197 #define UDMA_ATTR_USEBURST 0x00000001 198 #define UDMA_ATTR_ALTSELECT 0x00000002 199 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004 200 #define UDMA_ATTR_REQMASK 0x00000008 201 #define UDMA_ATTR_ALL 0x0000000F 202 203 //***************************************************************************** 204 // 205 // DMA control modes that can be passed to uDMAModeSet() and returned 206 // uDMAModeGet(). 207 // 208 //***************************************************************************** 209 #define UDMA_MODE_STOP 0x00000000 210 #define UDMA_MODE_BASIC 0x00000001 211 #define UDMA_MODE_AUTO 0x00000002 212 #define UDMA_MODE_PINGPONG 0x00000003 213 #define UDMA_MODE_MEM_SCATTER_GATHER \ 214 0x00000004 215 #define UDMA_MODE_PER_SCATTER_GATHER \ 216 0x00000006 217 #define UDMA_MODE_ALT_SELECT 0x00000001 218 219 //***************************************************************************** 220 // 221 // Flags to be OR'd with the channel ID to indicate if the primary or alternate 222 // control structure should be used. 223 // 224 //***************************************************************************** 225 #define UDMA_PRI_SELECT 0x00000000 226 #define UDMA_ALT_SELECT 0x00000020 227 228 //***************************************************************************** 229 // 230 // uDMA interrupt sources, to be passed to uDMAIntRegister() and 231 // uDMAIntUnregister(). 232 // 233 //***************************************************************************** 234 #define UDMA_INT_SW INT_UDMA 235 #define UDMA_INT_ERR INT_UDMAERR 236 237 //***************************************************************************** 238 239 //***************************************************************************** 240 // 241 // Channel configuration values that can be passed to uDMAControlSet(). 242 // 243 //***************************************************************************** 244 #define UDMA_DST_INC_8 0x00000000 245 #define UDMA_DST_INC_16 0x40000000 246 #define UDMA_DST_INC_32 0x80000000 247 #define UDMA_DST_INC_NONE 0xc0000000 248 #define UDMA_SRC_INC_8 0x00000000 249 #define UDMA_SRC_INC_16 0x04000000 250 #define UDMA_SRC_INC_32 0x08000000 251 #define UDMA_SRC_INC_NONE 0x0c000000 252 #define UDMA_SIZE_8 0x00000000 253 #define UDMA_SIZE_16 0x11000000 254 #define UDMA_SIZE_32 0x22000000 255 #define UDMA_ARB_1 0x00000000 256 #define UDMA_ARB_2 0x00004000 257 #define UDMA_ARB_4 0x00008000 258 #define UDMA_ARB_8 0x0000c000 259 #define UDMA_ARB_16 0x00010000 260 #define UDMA_ARB_32 0x00014000 261 #define UDMA_ARB_64 0x00018000 262 #define UDMA_ARB_128 0x0001c000 263 #define UDMA_ARB_256 0x00020000 264 #define UDMA_ARB_512 0x00024000 265 #define UDMA_ARB_1024 0x00028000 266 #define UDMA_NEXT_USEBURST 0x00000008 267 268 //***************************************************************************** 269 // 270 // Values that can be passed to uDMAChannelAssign() to select peripheral 271 // mapping for each channel. The channels named RESERVED may be assigned 272 // to a peripheral in future parts. 273 // 274 //***************************************************************************** 275 // 276 // Channel 0 277 // 278 #define UDMA_CH0_TIMERA0_A 0x00000000 279 #define UDMA_CH0_SHAMD5_CIN 0x00010000 280 #define UDMA_CH0_SW 0x00030000 281 282 // 283 // Channel 1 284 // 285 #define UDMA_CH1_TIMERA0_B 0x00000001 286 #define UDMA_CH1_SHAMD5_DIN 0x00010001 287 #define UDMA_CH1_SW 0x00030001 288 289 // 290 // Channel 2 291 // 292 #define UDMA_CH2_TIMERA1_A 0x00000002 293 #define UDMA_CH2_SHAMD5_COUT 0x00010002 294 #define UDMA_CH2_SW 0x00030002 295 296 // 297 // Channel 3 298 // 299 #define UDMA_CH3_TIMERA1_B 0x00000003 300 #define UDMA_CH3_DES_CIN 0x00010003 301 #define UDMA_CH3_SW 0x00030003 302 303 // 304 // Channel 4 305 // 306 #define UDMA_CH4_TIMERA2_A 0x00000004 307 #define UDMA_CH4_DES_DIN 0x00010004 308 #define UDMA_CH4_I2S_RX 0x00020004 309 #define UDMA_CH4_SW 0x00030004 310 311 // 312 // Channel 5 313 // 314 #define UDMA_CH5_TIMERA2_B 0x00000005 315 #define UDMA_CH5_DES_DOUT 0x00010005 316 #define UDMA_CH5_I2S_TX 0x00020005 317 #define UDMA_CH5_SW 0x00030005 318 319 // 320 // Channel 6 321 // 322 #define UDMA_CH6_TIMERA3_A 0x00000006 323 #define UDMA_CH6_GSPI_RX 0x00010006 324 #define UDMA_CH6_GPIOA2 0x00020006 325 #define UDMA_CH6_SW 0x00030006 326 327 // 328 // Channel 7 329 // 330 #define UDMA_CH7_TIMERA3_B 0x00000007 331 #define UDMA_CH7_GSPI_TX 0x00010007 332 #define UDMA_CH7_GPIOA3 0x00020007 333 #define UDMA_CH7_SW 0x00030007 334 335 336 // 337 // Channel 8 338 // 339 #define UDMA_CH8_UARTA0_RX 0x00000008 340 #define UDMA_CH8_TIMERA0_A 0x00010008 341 #define UDMA_CH8_TIMERA2_A 0x00020008 342 #define UDMA_CH8_SW 0x00030008 343 344 345 // 346 // Channel 9 347 // 348 #define UDMA_CH9_UARTA0_TX 0x00000009 349 #define UDMA_CH9_TIMERA0_B 0x00010009 350 #define UDMA_CH9_TIMERA2_B 0x00020009 351 #define UDMA_CH9_SW 0x00030009 352 353 354 // 355 // Channel 10 356 // 357 #define UDMA_CH10_UARTA1_RX 0x0000000A 358 #define UDMA_CH10_TIMERA1_A 0x0001000A 359 #define UDMA_CH10_TIMERA3_A 0x0002000A 360 #define UDMA_CH10_SW 0x0003000A 361 362 // 363 // Channel 11 364 // 365 #define UDMA_CH11_UARTA1_TX 0x0000000B 366 #define UDMA_CH11_TIMERA1_B 0x0001000B 367 #define UDMA_CH11_TIMERA3_B 0x0002000B 368 #define UDMA_CH11_SW 0x0003000B 369 370 371 // 372 // Channel 12 373 // 374 #define UDMA_CH12_LSPI_RX 0x0000000C 375 #define UDMA_CH12_SW 0x0003000C 376 377 378 // 379 // Channel 13 380 // 381 #define UDMA_CH13_LSPI_TX 0x0000000D 382 #define UDMA_CH13_SW 0x0003000D 383 384 385 // 386 // Channel 14 387 // 388 #define UDMA_CH14_ADC_CH0 0x0000000E 389 #define UDMA_CH14_SDHOST_RX 0x0002000E 390 #define UDMA_CH14_SW 0x0003000E 391 392 393 // 394 // Channel 15 395 // 396 #define UDMA_CH15_ADC_CH1 0x0000000F 397 #define UDMA_CH15_SDHOST_TX 0x0002000F 398 #define UDMA_CH15_SW 0x0003000F 399 400 401 // 402 // Channel 16 403 // 404 #define UDMA_CH16_ADC_CH2 0x00000010 405 #define UDMA_CH16_TIMERA2_A 0x00010010 406 #define UDMA_CH16_SW 0x00030010 407 408 409 // 410 // Channel 17 411 // 412 #define UDMA_CH17_ADC_CH3 0x00000011 413 #define UDMA_CH17_TIMERA2_B 0x00010011 414 #define UDMA_CH17_SW 0x00030011 415 416 // 417 // Channel 18 418 // 419 #define UDMA_CH18_GPIOA0 0x00000012 420 #define UDMA_CH18_AES_CIN 0x00010012 421 #define UDMA_CH18_I2S_RX 0x00020012 422 #define UDMA_CH18_SW 0x00030012 423 424 425 // 426 // Channel 19 427 // 428 #define UDMA_CH19_GPOIA1 0x00000013 429 #define UDMA_CH19_AES_COUT 0x00010013 430 #define UDMA_CH19_I2S_TX 0x00020013 431 #define UDMA_CH19_SW 0x00030013 432 433 434 // 435 // Channel 20 436 // 437 #define UDMA_CH20_GPIOA2 0x00000014 438 #define UDMA_CH20_AES_DIN 0x00010014 439 #define UDMA_CH20_SW 0x00030014 440 441 442 // 443 // Channel 21 444 // 445 #define UDMA_CH21_GPIOA3 0x00000015 446 #define UDMA_CH21_AES_DOUT 0x00010015 447 #define UDMA_CH21_SW 0x00030015 448 449 450 // 451 // Channel 22 452 // 453 #define UDMA_CH22_CAMERA 0x00000016 454 #define UDMA_CH22_GPIOA4 0x00010016 455 #define UDMA_CH22_SW 0x00030016 456 457 458 // 459 // Channel 23 460 // 461 #define UDMA_CH23_SDHOST_RX 0x00000017 462 #define UDMA_CH23_TIMERA3_A 0x00010017 463 #define UDMA_CH23_TIMERA2_A 0x00020017 464 #define UDMA_CH23_SW 0x00030017 465 466 467 // 468 // Channel 24 469 // 470 #define UDMA_CH24_SDHOST_TX 0x00000018 471 #define UDMA_CH24_TIMERA3_B 0x00010018 472 #define UDMA_CH24_TIMERA2_B 0x00020018 473 #define UDMA_CH24_SW 0x00030018 474 475 476 // 477 // Channel 25 478 // 479 #define UDMA_CH25_SSPI_RX 0x00000019 480 #define UDMA_CH25_I2CA0_RX 0x00010019 481 #define UDMA_CH25_SW 0x00030019 482 483 484 // 485 // Channel 26 486 // 487 #define UDMA_CH26_SSPI_TX 0x0000001A 488 #define UDMA_CH26_I2CA0_TX 0x0001001A 489 #define UDMA_CH26_SW 0x0003001A 490 491 492 // 493 // Channel 27 494 // 495 #define UDMA_CH27_GPIOA0 0x0001001B 496 #define UDMA_CH27_SW 0x0003001B 497 498 499 // 500 // Channel 28 501 // 502 #define UDMA_CH28_GPIOA1 0x0001001C 503 #define UDMA_CH28_SW 0x0003001C 504 505 506 // 507 // Channel 29 508 // 509 #define UDMA_CH29_GPIOA4 0x0000001D 510 #define UDMA_CH29_SW 0x0003001D 511 512 513 // 514 // Channel 30 515 // 516 #define UDMA_CH30_GSPI_RX 0x0000001E 517 #define UDMA_CH30_SDHOST_RX 0x0001001E 518 #define UDMA_CH30_I2CA0_RX 0x0002001E 519 #define UDMA_CH30_SW 0x0003001E 520 521 522 // 523 // Channel 31 524 // 525 #define UDMA_CH31_GSPI_TX 0x0000001F 526 #define UDMA_CH31_SDHOST_TX 0x0001001F 527 #define UDMA_CH31_I2CA0_RX 0x0002001F 528 #define UDMA_CH31_SW 0x0003001F 529 530 //***************************************************************************** 531 // 532 // The following are defines for the Micro Direct Memory Access (uDMA) offsets. 533 // 534 //***************************************************************************** 535 #define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End 536 // Pointer 537 #define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address 538 // End Pointer 539 #define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word 540 541 //***************************************************************************** 542 // 543 // The following are defines for the bit fields in the UDMA_O_SRCENDP register. 544 // 545 //***************************************************************************** 546 #define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer 547 #define UDMA_SRCENDP_ADDR_S 0 548 549 //***************************************************************************** 550 // 551 // The following are defines for the bit fields in the UDMA_O_DSTENDP register. 552 // 553 //***************************************************************************** 554 #define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer 555 #define UDMA_DSTENDP_ADDR_S 0 556 557 //***************************************************************************** 558 // 559 // The following are defines for the bit fields in the UDMA_O_CHCTL register. 560 // 561 //***************************************************************************** 562 #define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment 563 #define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte 564 #define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word 565 #define UDMA_CHCTL_DSTINC_32 0x80000000 // Word 566 #define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment 567 #define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size 568 #define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte 569 #define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word 570 #define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word 571 #define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment 572 #define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte 573 #define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word 574 #define UDMA_CHCTL_SRCINC_32 0x08000000 // Word 575 #define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment 576 #define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size 577 #define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte 578 #define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word 579 #define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word 580 #define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size 581 #define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer 582 #define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers 583 #define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers 584 #define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers 585 #define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers 586 #define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers 587 #define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers 588 #define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers 589 #define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers 590 #define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers 591 #define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers 592 #define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) 593 #define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst 594 #define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode 595 #define UDMA_CHCTL_XFERMODE_STOP \ 596 0x00000000 // Stop 597 #define UDMA_CHCTL_XFERMODE_BASIC \ 598 0x00000001 // Basic 599 #define UDMA_CHCTL_XFERMODE_AUTO \ 600 0x00000002 // Auto-Request 601 #define UDMA_CHCTL_XFERMODE_PINGPONG \ 602 0x00000003 // Ping-Pong 603 #define UDMA_CHCTL_XFERMODE_MEM_SG \ 604 0x00000004 // Memory Scatter-Gather 605 #define UDMA_CHCTL_XFERMODE_MEM_SGA \ 606 0x00000005 // Alternate Memory Scatter-Gather 607 #define UDMA_CHCTL_XFERMODE_PER_SG \ 608 0x00000006 // Peripheral Scatter-Gather 609 #define UDMA_CHCTL_XFERMODE_PER_SGA \ 610 0x00000007 // Alternate Peripheral 611 // Scatter-Gather 612 #define UDMA_CHCTL_XFERSIZE_S 4 613 614 615 616 //***************************************************************************** 617 // 618 // API Function prototypes 619 // 620 //***************************************************************************** 621 extern void uDMAEnable(void); 622 extern void uDMADisable(void); 623 extern unsigned long uDMAErrorStatusGet(void); 624 extern void uDMAErrorStatusClear(void); 625 extern void uDMAChannelEnable(unsigned long ulChannelNum); 626 extern void uDMAChannelDisable(unsigned long ulChannelNum); 627 extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum); 628 extern void uDMAControlBaseSet(void *pControlTable); 629 extern void *uDMAControlBaseGet(void); 630 extern void *uDMAControlAlternateBaseGet(void); 631 extern void uDMAChannelRequest(unsigned long ulChannelNum); 632 extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum, 633 unsigned long ulAttr); 634 extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum, 635 unsigned long ulAttr); 636 extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum); 637 extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex, 638 unsigned long ulControl); 639 extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex, 640 unsigned long ulMode, void *pvSrcAddr, 641 void *pvDstAddr, 642 unsigned long ulTransferSize); 643 extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum, 644 unsigned ulTaskCount, void *pvTaskList, 645 unsigned long ulIsPeriphSG); 646 extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex); 647 extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex); 648 extern void uDMAIntRegister(unsigned long ulIntChannel, 649 void (*pfnHandler)(void)); 650 extern void uDMAIntUnregister(unsigned long ulIntChannel); 651 extern unsigned long uDMAIntStatus(void); 652 extern void uDMAIntClear(unsigned long ulChanMask); 653 extern void uDMAChannelAssign(unsigned long ulMapping); 654 655 //***************************************************************************** 656 // 657 // Mark the end of the C bindings section for C++ compilers. 658 // 659 //***************************************************************************** 660 #ifdef __cplusplus 661 } 662 #endif 663 664 #endif // __UDMA_H__ 665
