1 /*
2  *  Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  *  Redistribution and use in source and binary forms, with or without
5  *  modification, are permitted provided that the following conditions
6  *  are met:
7  *
8  *    Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  *
11  *    Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the
14  *    distribution.
15  *
16  *    Neither the name of Texas Instruments Incorporated nor the names of
17  *    its contributors may be used to endorse or promote products derived
18  *    from this software without specific prior written permission.
19  *
20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  */
33 
34 //*****************************************************************************
35 //
36 // hw_timer.h - Defines and macros used when accessing the timer.
37 //
38 //*****************************************************************************
39 
40 //##### INTERNAL BEGIN #####
41 //
42 // This is an auto-generated file.  Do not edit by hand.
43 // Created by version 6779 of DriverLib.
44 //
45 //##### INTERNAL END #####
46 
47 #ifndef __HW_TIMER_H__
48 #define __HW_TIMER_H__
49 
50 //*****************************************************************************
51 //
52 // The following are defines for the Timer register offsets.
53 //
54 //*****************************************************************************
55 #define TIMER_O_CFG             0x00000000  // GPTM Configuration
56 #define TIMER_O_TAMR            0x00000004  // GPTM Timer A Mode
57 #define TIMER_O_TBMR            0x00000008  // GPTM Timer B Mode
58 #define TIMER_O_CTL             0x0000000C  // GPTM Control
59 //##### GARNET BEGIN #####
60 #define TIMER_O_SYNC            0x00000010  // GPTM Synchronize
61 //##### GARNET END #####
62 #define TIMER_O_IMR             0x00000018  // GPTM Interrupt Mask
63 #define TIMER_O_RIS             0x0000001C  // GPTM Raw Interrupt Status
64 #define TIMER_O_MIS             0x00000020  // GPTM Masked Interrupt Status
65 #define TIMER_O_ICR             0x00000024  // GPTM Interrupt Clear
66 #define TIMER_O_TAILR           0x00000028  // GPTM Timer A Interval Load
67 #define TIMER_O_TBILR           0x0000002C  // GPTM Timer B Interval Load
68 #define TIMER_O_TAMATCHR        0x00000030  // GPTM Timer A Match
69 #define TIMER_O_TBMATCHR        0x00000034  // GPTM Timer B Match
70 #define TIMER_O_TAPR            0x00000038  // GPTM Timer A Prescale
71 #define TIMER_O_TBPR            0x0000003C  // GPTM Timer B Prescale
72 #define TIMER_O_TAPMR           0x00000040  // GPTM TimerA Prescale Match
73 #define TIMER_O_TBPMR           0x00000044  // GPTM TimerB Prescale Match
74 #define TIMER_O_TAR             0x00000048  // GPTM Timer A
75 #define TIMER_O_TBR             0x0000004C  // GPTM Timer B
76 #define TIMER_O_TAV             0x00000050  // GPTM Timer A Value
77 #define TIMER_O_TBV             0x00000054  // GPTM Timer B Value
78 #define TIMER_O_RTCPD           0x00000058  // GPTM RTC Predivide
79 #define TIMER_O_TAPS            0x0000005C  // GPTM Timer A Prescale Snapshot
80 #define TIMER_O_TBPS            0x00000060  // GPTM Timer B Prescale Snapshot
81 #define TIMER_O_TAPV            0x00000064  // GPTM Timer A Prescale Value
82 #define TIMER_O_TBPV            0x00000068  // GPTM Timer B Prescale Value
83 #define TIMER_O_DMAEV           0x0000006C  // GPTM DMA Event
84 #define TIMER_O_PP              0x00000FC0  // GPTM Peripheral Properties
85 
86 
87 //*****************************************************************************
88 //
89 // The following are defines for the bit fields in the TIMER_O_CFG register.
90 //
91 //*****************************************************************************
92 #define TIMER_CFG_M             0x00000007  // GPTM Configuration
93 #define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration
94 #define TIMER_CFG_32_BIT_RTC    0x00000001  // 32-bit real-time clock (RTC)
95                                             // counter configuration
96 #define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration. The
97                                             // function is controlled by bits
98                                             // 1:0 of GPTMTAMR and GPTMTBMR
99 
100 //*****************************************************************************
101 //
102 // The following are defines for the bit fields in the TIMER_O_TAMR register.
103 //
104 //*****************************************************************************
105 //##### GARNET BEGIN #####
106 #define TIMER_TAMR_TAPLO        0x00000800  // GPTM Timer A PWM Legacy
107                                             // Operation
108 #define TIMER_TAMR_TAMRSU       0x00000400  // GPTM Timer A Match Register
109                                             // Update
110 #define TIMER_TAMR_TAPWMIE      0x00000200  // GPTM Timer A PWM Interrupt
111                                             // Enable
112 #define TIMER_TAMR_TAILD        0x00000100  // GPTM Timer A Interval Load Write
113 //##### GARNET END #####
114 #define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode
115 #define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger
116 #define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt
117                                             // Enable
118 #define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction
119 #define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
120                                             // Select
121 #define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
122 #define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
123 #define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
124 #define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
125 #define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
126 
127 //*****************************************************************************
128 //
129 // The following are defines for the bit fields in the TIMER_O_TBMR register.
130 //
131 //*****************************************************************************
132 //##### GARNET BEGIN #####
133 #define TIMER_TBMR_TBPLO        0x00000800  // GPTM Timer B PWM Legacy
134                                             // Operation
135 #define TIMER_TBMR_TBMRSU       0x00000400  // GPTM Timer B Match Register
136                                             // Update
137 #define TIMER_TBMR_TBPWMIE      0x00000200  // GPTM Timer B PWM Interrupt
138                                             // Enable
139 #define TIMER_TBMR_TBILD        0x00000100  // GPTM Timer B Interval Load Write
140 //##### GARNET END #####
141 #define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode
142 #define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger
143 #define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt
144                                             // Enable
145 #define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction
146 #define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
147                                             // Select
148 #define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
149 #define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
150 #define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
151 #define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
152 #define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
153 
154 //*****************************************************************************
155 //
156 // The following are defines for the bit fields in the TIMER_O_CTL register.
157 //
158 //*****************************************************************************
159 #define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
160 #define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
161                                             // Enable
162 #define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
163 #define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
164 #define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
165 #define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
166 #define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
167 #define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
168 #define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
169 #define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
170                                             // Enable
171 #define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable
172 #define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
173 #define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
174 #define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
175 #define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
176 #define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
177 #define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
178 //##### GARNET BEGIN #####
179 
180 //*****************************************************************************
181 //
182 // The following are defines for the bit fields in the TIMER_O_SYNC register.
183 //
184 //*****************************************************************************
185 #define TIMER_SYNC_SYNC11_M     0x00C00000  // Synchronize GPTM Timer 11
186 #define TIMER_SYNC_SYNC11_TA    0x00400000  // A timeout event for Timer A of
187                                             // GPTM11 is triggered
188 #define TIMER_SYNC_SYNC11_TB    0x00800000  // A timeout event for Timer B of
189                                             // GPTM11 is triggered
190 #define TIMER_SYNC_SYNC11_TATB  0x00C00000  // A timeout event for both Timer A
191                                             // and Timer B of GPTM11 is
192                                             // triggered
193 #define TIMER_SYNC_SYNC10_M     0x00300000  // Synchronize GPTM Timer 10
194 #define TIMER_SYNC_SYNC10_TA    0x00100000  // A timeout event for Timer A of
195                                             // GPTM10 is triggered
196 #define TIMER_SYNC_SYNC10_TB    0x00200000  // A timeout event for Timer B of
197                                             // GPTM10 is triggered
198 #define TIMER_SYNC_SYNC10_TATB  0x00300000  // A timeout event for both Timer A
199                                             // and Timer B of GPTM10 is
200                                             // triggered
201 #define TIMER_SYNC_SYNC9_M      0x000C0000  // Synchronize GPTM Timer 9
202 #define TIMER_SYNC_SYNC9_TA     0x00040000  // A timeout event for Timer A of
203                                             // GPTM9 is triggered
204 #define TIMER_SYNC_SYNC9_TB     0x00080000  // A timeout event for Timer B of
205                                             // GPTM9 is triggered
206 #define TIMER_SYNC_SYNC9_TATB   0x000C0000  // A timeout event for both Timer A
207                                             // and Timer B of GPTM9 is
208                                             // triggered
209 #define TIMER_SYNC_SYNC8_M      0x00030000  // Synchronize GPTM Timer 8
210 #define TIMER_SYNC_SYNC8_TA     0x00010000  // A timeout event for Timer A of
211                                             // GPTM8 is triggered
212 #define TIMER_SYNC_SYNC8_TB     0x00020000  // A timeout event for Timer B of
213                                             // GPTM8 is triggered
214 #define TIMER_SYNC_SYNC8_TATB   0x00030000  // A timeout event for both Timer A
215                                             // and Timer B of GPTM8 is
216                                             // triggered
217 #define TIMER_SYNC_SYNC7_M      0x0000C000  // Synchronize GPTM Timer 7
218 #define TIMER_SYNC_SYNC7_TA     0x00004000  // A timeout event for Timer A of
219                                             // GPTM7 is triggered
220 #define TIMER_SYNC_SYNC7_TB     0x00008000  // A timeout event for Timer B of
221                                             // GPTM7 is triggered
222 #define TIMER_SYNC_SYNC7_TATB   0x0000C000  // A timeout event for both Timer A
223                                             // and Timer B of GPTM7 is
224                                             // triggered
225 #define TIMER_SYNC_SYNC6_M      0x00003000  // Synchronize GPTM Timer 6
226 #define TIMER_SYNC_SYNC6_TA     0x00001000  // A timeout event for Timer A of
227                                             // GPTM6 is triggered
228 #define TIMER_SYNC_SYNC6_TB     0x00002000  // A timeout event for Timer B of
229                                             // GPTM6 is triggered
230 #define TIMER_SYNC_SYNC6_TATB   0x00003000  // A timeout event for both Timer A
231                                             // and Timer B of GPTM6 is
232                                             // triggered
233 #define TIMER_SYNC_SYNC5_M      0x00000C00  // Synchronize GPTM Timer 5
234 #define TIMER_SYNC_SYNC5_TA     0x00000400  // A timeout event for Timer A of
235                                             // GPTM5 is triggered
236 #define TIMER_SYNC_SYNC5_TB     0x00000800  // A timeout event for Timer B of
237                                             // GPTM5 is triggered
238 #define TIMER_SYNC_SYNC5_TATB   0x00000C00  // A timeout event for both Timer A
239                                             // and Timer B of GPTM5 is
240                                             // triggered
241 #define TIMER_SYNC_SYNC4_M      0x00000300  // Synchronize GPTM Timer 4
242 #define TIMER_SYNC_SYNC4_TA     0x00000100  // A timeout event for Timer A of
243                                             // GPTM4 is triggered
244 #define TIMER_SYNC_SYNC4_TB     0x00000200  // A timeout event for Timer B of
245                                             // GPTM4 is triggered
246 #define TIMER_SYNC_SYNC4_TATB   0x00000300  // A timeout event for both Timer A
247                                             // and Timer B of GPTM4 is
248                                             // triggered
249 #define TIMER_SYNC_SYNC3_M      0x000000C0  // Synchronize GPTM Timer 3
250 #define TIMER_SYNC_SYNC3_TA     0x00000040  // A timeout event for Timer A of
251                                             // GPTM3 is triggered
252 #define TIMER_SYNC_SYNC3_TB     0x00000080  // A timeout event for Timer B of
253                                             // GPTM3 is triggered
254 #define TIMER_SYNC_SYNC3_TATB   0x000000C0  // A timeout event for both Timer A
255                                             // and Timer B of GPTM3 is
256                                             // triggered
257 #define TIMER_SYNC_SYNC2_M      0x00000030  // Synchronize GPTM Timer 2
258 #define TIMER_SYNC_SYNC2_TA     0x00000010  // A timeout event for Timer A of
259                                             // GPTM2 is triggered
260 #define TIMER_SYNC_SYNC2_TB     0x00000020  // A timeout event for Timer B of
261                                             // GPTM2 is triggered
262 #define TIMER_SYNC_SYNC2_TATB   0x00000030  // A timeout event for both Timer A
263                                             // and Timer B of GPTM2 is
264                                             // triggered
265 #define TIMER_SYNC_SYNC1_M      0x0000000C  // Synchronize GPTM Timer 1
266 #define TIMER_SYNC_SYNC1_TA     0x00000004  // A timeout event for Timer A of
267                                             // GPTM1 is triggered
268 #define TIMER_SYNC_SYNC1_TB     0x00000008  // A timeout event for Timer B of
269                                             // GPTM1 is triggered
270 #define TIMER_SYNC_SYNC1_TATB   0x0000000C  // A timeout event for both Timer A
271                                             // and Timer B of GPTM1 is
272                                             // triggered
273 #define TIMER_SYNC_SYNC0_M      0x00000003  // Synchronize GPTM Timer 0
274 #define TIMER_SYNC_SYNC0_TA     0x00000001  // A timeout event for Timer A of
275                                             // GPTM0 is triggered
276 #define TIMER_SYNC_SYNC0_TB     0x00000002  // A timeout event for Timer B of
277                                             // GPTM0 is triggered
278 #define TIMER_SYNC_SYNC0_TATB   0x00000003  // A timeout event for both Timer A
279                                             // and Timer B of GPTM0 is
280                                             // triggered
281 //##### GARNET END #####
282 
283 //*****************************************************************************
284 //
285 // The following are defines for the bit fields in the TIMER_O_IMR register.
286 //
287 //*****************************************************************************
288 //##### GARNET BEGIN #####
289 #define TIMER_IMR_WUEIM         0x00010000  // 32/64-Bit GPTM Write Update
290                                             // Error Interrupt Mask
291 //##### GARNET END #####
292 #define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Mode Match
293                                             // Interrupt Mask
294 #define TIMER_IMR_CBEIM         0x00000400  // GPTM Capture B Event Interrupt
295                                             // Mask
296 #define TIMER_IMR_CBMIM         0x00000200  // GPTM Capture B Match Interrupt
297                                             // Mask
298 #define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
299                                             // Mask
300 #define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Mode Match
301                                             // Interrupt Mask
302 #define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
303 #define TIMER_IMR_CAEIM         0x00000004  // GPTM Capture A Event Interrupt
304                                             // Mask
305 #define TIMER_IMR_CAMIM         0x00000002  // GPTM Capture A Match Interrupt
306                                             // Mask
307 #define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
308                                             // Mask
309 
310 //*****************************************************************************
311 //
312 // The following are defines for the bit fields in the TIMER_O_RIS register.
313 //
314 //*****************************************************************************
315 //##### GARNET BEGIN #####
316 #define TIMER_RIS_WUERIS        0x00010000  // 32/64-Bit GPTM Write Update
317                                             // Error Raw Interrupt Status
318 //##### GARNET END #####
319 #define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Mode Match Raw
320                                             // Interrupt
321 #define TIMER_RIS_CBERIS        0x00000400  // GPTM Capture B Event Raw
322                                             // Interrupt
323 #define TIMER_RIS_CBMRIS        0x00000200  // GPTM Capture B Match Raw
324                                             // Interrupt
325 #define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
326                                             // Interrupt
327 #define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Mode Match Raw
328                                             // Interrupt
329 #define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
330 #define TIMER_RIS_CAERIS        0x00000004  // GPTM Capture A Event Raw
331                                             // Interrupt
332 #define TIMER_RIS_CAMRIS        0x00000002  // GPTM Capture A Match Raw
333                                             // Interrupt
334 #define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
335                                             // Interrupt
336 
337 //*****************************************************************************
338 //
339 // The following are defines for the bit fields in the TIMER_O_MIS register.
340 //
341 //*****************************************************************************
342 //##### GARNET BEGIN #####
343 #define TIMER_MIS_WUEMIS        0x00010000  // 32/64-Bit GPTM Write Update
344                                             // Error Masked Interrupt Status
345 //##### GARNET END #####
346 #define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Mode Match Masked
347                                             // Interrupt
348 #define TIMER_MIS_CBEMIS        0x00000400  // GPTM Capture B Event Masked
349                                             // Interrupt
350 #define TIMER_MIS_CBMMIS        0x00000200  // GPTM Capture B Match Masked
351                                             // Interrupt
352 #define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
353                                             // Interrupt
354 #define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Mode Match Masked
355                                             // Interrupt
356 #define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
357 #define TIMER_MIS_CAEMIS        0x00000004  // GPTM Capture A Event Masked
358                                             // Interrupt
359 #define TIMER_MIS_CAMMIS        0x00000002  // GPTM Capture A Match Masked
360                                             // Interrupt
361 #define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
362                                             // Interrupt
363 
364 //*****************************************************************************
365 //
366 // The following are defines for the bit fields in the TIMER_O_ICR register.
367 //
368 //*****************************************************************************
369 //##### GARNET BEGIN #####
370 #define TIMER_ICR_WUECINT       0x00010000  // 32/64-Bit GPTM Write Update
371                                             // Error Interrupt Clear
372 //##### GARNET END #####
373 #define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Mode Match
374                                             // Interrupt Clear
375 #define TIMER_ICR_CBECINT       0x00000400  // GPTM Capture B Event Interrupt
376                                             // Clear
377 #define TIMER_ICR_CBMCINT       0x00000200  // GPTM Capture B Match Interrupt
378                                             // Clear
379 #define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
380                                             // Clear
381 #define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Mode Match
382                                             // Interrupt Clear
383 #define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
384 #define TIMER_ICR_CAECINT       0x00000004  // GPTM Capture A Event Interrupt
385                                             // Clear
386 #define TIMER_ICR_CAMCINT       0x00000002  // GPTM Capture A Match Interrupt
387                                             // Clear
388 #define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
389                                             // Interrupt
390 
391 //*****************************************************************************
392 //
393 // The following are defines for the bit fields in the TIMER_O_TAILR register.
394 //
395 //*****************************************************************************
396 //##### GARNET BEGIN #####
397 #define TIMER_TAILR_M           0xFFFFFFFF  // GPTM Timer A Interval Load
398                                             // Register
399 //##### GARNET END #####
400 #define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM Timer A Interval Load
401                                             // Register High
402 #define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM Timer A Interval Load
403                                             // Register Low
404 #define TIMER_TAILR_TAILRH_S    16
405 #define TIMER_TAILR_TAILRL_S    0
406 //##### GARNET BEGIN #####
407 #define TIMER_TAILR_S           0
408 //##### GARNET END #####
409 
410 //*****************************************************************************
411 //
412 // The following are defines for the bit fields in the TIMER_O_TBILR register.
413 //
414 //*****************************************************************************
415 //##### GARNET BEGIN #####
416 #define TIMER_TBILR_M           0xFFFFFFFF  // GPTM Timer B Interval Load
417                                             // Register
418 //##### GARNET END #####
419 #define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM Timer B Interval Load
420                                             // Register
421 #define TIMER_TBILR_TBILRL_S    0
422 //##### GARNET BEGIN #####
423 #define TIMER_TBILR_S           0
424 //##### GARNET END #####
425 
426 //*****************************************************************************
427 //
428 // The following are defines for the bit fields in the TIMER_O_TAMATCHR
429 // register.
430 //
431 //*****************************************************************************
432 //##### GARNET BEGIN #####
433 #define TIMER_TAMATCHR_TAMR_M   0xFFFFFFFF  // GPTM Timer A Match Register
434 //##### GARNET END #####
435 #define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM Timer A Match Register High
436 #define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM Timer A Match Register Low
437 #define TIMER_TAMATCHR_TAMRH_S  16
438 #define TIMER_TAMATCHR_TAMRL_S  0
439 //##### GARNET BEGIN #####
440 #define TIMER_TAMATCHR_TAMR_S   0
441 //##### GARNET END #####
442 
443 //*****************************************************************************
444 //
445 // The following are defines for the bit fields in the TIMER_O_TBMATCHR
446 // register.
447 //
448 //*****************************************************************************
449 //##### GARNET BEGIN #####
450 #define TIMER_TBMATCHR_TBMR_M   0xFFFFFFFF  // GPTM Timer B Match Register
451 //##### GARNET END #####
452 #define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM Timer B Match Register Low
453 //##### GARNET BEGIN #####
454 #define TIMER_TBMATCHR_TBMR_S   0
455 //##### GARNET END #####
456 #define TIMER_TBMATCHR_TBMRL_S  0
457 
458 //*****************************************************************************
459 //
460 // The following are defines for the bit fields in the TIMER_O_TAPR register.
461 //
462 //*****************************************************************************
463 //##### GARNET BEGIN #####
464 #define TIMER_TAPR_TAPSRH_M     0x0000FF00  // GPTM Timer A Prescale High Byte
465 //##### GARNET END #####
466 #define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
467 //##### GARNET BEGIN #####
468 #define TIMER_TAPR_TAPSRH_S     8
469 //##### GARNET END #####
470 #define TIMER_TAPR_TAPSR_S      0
471 
472 //*****************************************************************************
473 //
474 // The following are defines for the bit fields in the TIMER_O_TBPR register.
475 //
476 //*****************************************************************************
477 //##### GARNET BEGIN #####
478 #define TIMER_TBPR_TBPSRH_M     0x0000FF00  // GPTM Timer B Prescale High Byte
479 //##### GARNET END #####
480 #define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
481 //##### GARNET BEGIN #####
482 #define TIMER_TBPR_TBPSRH_S     8
483 //##### GARNET END #####
484 #define TIMER_TBPR_TBPSR_S      0
485 
486 //*****************************************************************************
487 //
488 // The following are defines for the bit fields in the TIMER_O_TAPMR register.
489 //
490 //*****************************************************************************
491 //##### GARNET BEGIN #####
492 #define TIMER_TAPMR_TAPSMRH_M   0x0000FF00  // GPTM Timer A Prescale Match High
493                                             // Byte
494 //##### GARNET END #####
495 #define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
496 //##### GARNET BEGIN #####
497 #define TIMER_TAPMR_TAPSMRH_S   8
498 //##### GARNET END #####
499 #define TIMER_TAPMR_TAPSMR_S    0
500 
501 //*****************************************************************************
502 //
503 // The following are defines for the bit fields in the TIMER_O_TBPMR register.
504 //
505 //*****************************************************************************
506 //##### GARNET BEGIN #####
507 #define TIMER_TBPMR_TBPSMRH_M   0x0000FF00  // GPTM Timer B Prescale Match High
508                                             // Byte
509 //##### GARNET END #####
510 #define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
511 //##### GARNET BEGIN #####
512 #define TIMER_TBPMR_TBPSMRH_S   8
513 //##### GARNET END #####
514 #define TIMER_TBPMR_TBPSMR_S    0
515 
516 //*****************************************************************************
517 //
518 // The following are defines for the bit fields in the TIMER_O_TAR register.
519 //
520 //*****************************************************************************
521 //##### GARNET BEGIN #####
522 #define TIMER_TAR_M             0xFFFFFFFF  // GPTM Timer A Register
523 //##### GARNET END #####
524 #define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM Timer A Register High
525 #define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM Timer A Register Low
526 #define TIMER_TAR_TARH_S        16
527 #define TIMER_TAR_TARL_S        0
528 //##### GARNET BEGIN #####
529 #define TIMER_TAR_S             0
530 //##### GARNET END #####
531 
532 //*****************************************************************************
533 //
534 // The following are defines for the bit fields in the TIMER_O_TBR register.
535 //
536 //*****************************************************************************
537 //##### GARNET BEGIN #####
538 #define TIMER_TBR_M             0xFFFFFFFF  // GPTM Timer B Register
539 //##### GARNET END #####
540 #define TIMER_TBR_TBRL_M        0x00FFFFFF  // GPTM Timer B
541 #define TIMER_TBR_TBRL_S        0
542 //##### GARNET BEGIN #####
543 #define TIMER_TBR_S             0
544 //##### GARNET END #####
545 
546 //*****************************************************************************
547 //
548 // The following are defines for the bit fields in the TIMER_O_TAV register.
549 //
550 //*****************************************************************************
551 //##### GARNET BEGIN #####
552 #define TIMER_TAV_M             0xFFFFFFFF  // GPTM Timer A Value
553 //##### GARNET END #####
554 #define TIMER_TAV_TAVH_M        0xFFFF0000  // GPTM Timer A Value High
555 #define TIMER_TAV_TAVL_M        0x0000FFFF  // GPTM Timer A Register Low
556 #define TIMER_TAV_TAVH_S        16
557 #define TIMER_TAV_TAVL_S        0
558 //##### GARNET BEGIN #####
559 #define TIMER_TAV_S             0
560 //##### GARNET END #####
561 
562 //*****************************************************************************
563 //
564 // The following are defines for the bit fields in the TIMER_O_TBV register.
565 //
566 //*****************************************************************************
567 //##### GARNET BEGIN #####
568 #define TIMER_TBV_M             0xFFFFFFFF  // GPTM Timer B Value
569 //##### GARNET END #####
570 #define TIMER_TBV_TBVL_M        0x0000FFFF  // GPTM Timer B Register
571 #define TIMER_TBV_TBVL_S        0
572 //##### GARNET BEGIN #####
573 #define TIMER_TBV_S             0
574 
575 //*****************************************************************************
576 //
577 // The following are defines for the bit fields in the TIMER_O_RTCPD register.
578 //
579 //*****************************************************************************
580 #define TIMER_RTCPD_RTCPD_M     0x0000FFFF  // RTC Predivide Counter Value
581 #define TIMER_RTCPD_RTCPD_S     0
582 
583 //*****************************************************************************
584 //
585 // The following are defines for the bit fields in the TIMER_O_TAPS register.
586 //
587 //*****************************************************************************
588 #define TIMER_TAPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Snapshot
589 #define TIMER_TAPS_PSS_S        0
590 
591 //*****************************************************************************
592 //
593 // The following are defines for the bit fields in the TIMER_O_TBPS register.
594 //
595 //*****************************************************************************
596 #define TIMER_TBPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Value
597 #define TIMER_TBPS_PSS_S        0
598 
599 //*****************************************************************************
600 //
601 // The following are defines for the bit fields in the TIMER_O_TAPV register.
602 //
603 //*****************************************************************************
604 #define TIMER_TAPV_PSV_M        0x0000FFFF  // GPTM Timer A Prescaler Value
605 #define TIMER_TAPV_PSV_S        0
606 
607 //*****************************************************************************
608 //
609 // The following are defines for the bit fields in the TIMER_O_TBPV register.
610 //
611 //*****************************************************************************
612 #define TIMER_TBPV_PSV_M        0x0000FFFF  // GPTM Timer B Prescaler Value
613 #define TIMER_TBPV_PSV_S        0
614 
615 //*****************************************************************************
616 //
617 // The following are defines for the bit fields in the TIMER_O_PP register.
618 //
619 //*****************************************************************************
620 #define TIMER_PP_SYNCCNT        0x00000020  // Synchronize Start
621 #define TIMER_PP_CHAIN          0x00000010  // Chain with Other Timers
622 #define TIMER_PP_SIZE_M         0x0000000F  // Count Size
623 #define TIMER_PP_SIZE__0        0x00000000  // Timer A and Timer B counters are
624                                             // 16 bits each with an 8-bit
625                                             // prescale counter
626 #define TIMER_PP_SIZE__1        0x00000001  // Timer A and Timer B counters are
627                                             // 32 bits each with an 16-bit
628                                             // prescale counter
629 //##### GARNET END #####
630 
631 //*****************************************************************************
632 //
633 // The following definitions are deprecated.
634 //
635 //*****************************************************************************
636 #ifndef DEPRECATED
637 
638 //*****************************************************************************
639 //
640 // The following are deprecated defines for the bit fields in the TIMER_O_CFG
641 // register.
642 //
643 //*****************************************************************************
644 #define TIMER_CFG_CFG_MSK       0x00000007  // Configuration options mask
645 
646 //*****************************************************************************
647 //
648 // The following are deprecated defines for the bit fields in the TIMER_O_CTL
649 // register.
650 //
651 //*****************************************************************************
652 #define TIMER_CTL_TBEVENT_MSK   0x00000C00  // TimerB event mode mask
653 #define TIMER_CTL_TAEVENT_MSK   0x0000000C  // TimerA event mode mask
654 
655 //*****************************************************************************
656 //
657 // The following are deprecated defines for the bit fields in the TIMER_O_RIS
658 // register.
659 //
660 //*****************************************************************************
661 #define TIMER_RIS_CBEMIS        0x00000400  // CaptureB event masked int status
662 #define TIMER_RIS_CBMMIS        0x00000200  // CaptureB match masked int status
663 #define TIMER_RIS_TBTOMIS       0x00000100  // TimerB time out masked int stat
664 #define TIMER_RIS_RTCMIS        0x00000008  // RTC masked int status
665 #define TIMER_RIS_CAEMIS        0x00000004  // CaptureA event masked int status
666 #define TIMER_RIS_CAMMIS        0x00000002  // CaptureA match masked int status
667 #define TIMER_RIS_TATOMIS       0x00000001  // TimerA time out masked int stat
668 
669 //*****************************************************************************
670 //
671 // The following are deprecated defines for the bit fields in the TIMER_O_TAILR
672 // register.
673 //
674 //*****************************************************************************
675 #define TIMER_TAILR_TAILRH      0xFFFF0000  // TimerB load val in 32 bit mode
676 #define TIMER_TAILR_TAILRL      0x0000FFFF  // TimerA interval load value
677 
678 //*****************************************************************************
679 //
680 // The following are deprecated defines for the bit fields in the TIMER_O_TBILR
681 // register.
682 //
683 //*****************************************************************************
684 #define TIMER_TBILR_TBILRL      0x0000FFFF  // TimerB interval load value
685 
686 //*****************************************************************************
687 //
688 // The following are deprecated defines for the bit fields in the
689 // TIMER_O_TAMATCHR register.
690 //
691 //*****************************************************************************
692 #define TIMER_TAMATCHR_TAMRH    0xFFFF0000  // TimerB match val in 32 bit mode
693 #define TIMER_TAMATCHR_TAMRL    0x0000FFFF  // TimerA match value
694 
695 //*****************************************************************************
696 //
697 // The following are deprecated defines for the bit fields in the
698 // TIMER_O_TBMATCHR register.
699 //
700 //*****************************************************************************
701 #define TIMER_TBMATCHR_TBMRL    0x0000FFFF  // TimerB match load value
702 
703 //*****************************************************************************
704 //
705 // The following are deprecated defines for the bit fields in the TIMER_O_TAR
706 // register.
707 //
708 //*****************************************************************************
709 #define TIMER_TAR_TARH          0xFFFF0000  // TimerB val in 32 bit mode
710 #define TIMER_TAR_TARL          0x0000FFFF  // TimerA value
711 
712 //*****************************************************************************
713 //
714 // The following are deprecated defines for the bit fields in the TIMER_O_TBR
715 // register.
716 //
717 //*****************************************************************************
718 #define TIMER_TBR_TBRL          0x0000FFFF  // TimerB value
719 
720 //*****************************************************************************
721 //
722 // The following are deprecated defines for the reset values of the timer
723 // registers.
724 //
725 //*****************************************************************************
726 #define TIMER_RV_TAILR          0xFFFFFFFF  // TimerA interval load reg RV
727 #define TIMER_RV_TAR            0xFFFFFFFF  // TimerA register RV
728 #define TIMER_RV_TAMATCHR       0xFFFFFFFF  // TimerA match register RV
729 #define TIMER_RV_TBILR          0x0000FFFF  // TimerB interval load reg RV
730 #define TIMER_RV_TBMATCHR       0x0000FFFF  // TimerB match register RV
731 #define TIMER_RV_TBR            0x0000FFFF  // TimerB register RV
732 #define TIMER_RV_TAPR           0x00000000  // TimerA prescale register RV
733 #define TIMER_RV_CFG            0x00000000  // Configuration register RV
734 #define TIMER_RV_TBPMR          0x00000000  // TimerB prescale match regi RV
735 #define TIMER_RV_TAPMR          0x00000000  // TimerA prescale match reg RV
736 #define TIMER_RV_CTL            0x00000000  // Control register RV
737 #define TIMER_RV_ICR            0x00000000  // Interrupt clear register RV
738 #define TIMER_RV_TBMR           0x00000000  // TimerB mode register RV
739 #define TIMER_RV_MIS            0x00000000  // Masked interrupt status reg RV
740 #define TIMER_RV_RIS            0x00000000  // Interrupt status register RV
741 #define TIMER_RV_TBPR           0x00000000  // TimerB prescale register RV
742 #define TIMER_RV_IMR            0x00000000  // Interrupt mask register RV
743 #define TIMER_RV_TAMR           0x00000000  // TimerA mode register RV
744 
745 //*****************************************************************************
746 //
747 // The following are deprecated defines for the bit fields in the TIMER_TnMR
748 // register.
749 //
750 //*****************************************************************************
751 #define TIMER_TNMR_TNAMS        0x00000008  // Alternate mode select
752 #define TIMER_TNMR_TNCMR        0x00000004  // Capture mode - count or time
753 #define TIMER_TNMR_TNTMR_MSK    0x00000003  // Timer mode mask
754 #define TIMER_TNMR_TNTMR_1_SHOT 0x00000001  // Mode - one shot
755 #define TIMER_TNMR_TNTMR_PERIOD 0x00000002  // Mode - periodic
756 #define TIMER_TNMR_TNTMR_CAP    0x00000003  // Mode - capture
757 
758 //*****************************************************************************
759 //
760 // The following are deprecated defines for the bit fields in the TIMER_TnPR
761 // register.
762 //
763 //*****************************************************************************
764 #define TIMER_TNPR_TNPSR        0x000000FF  // TimerN prescale value
765 
766 //*****************************************************************************
767 //
768 // The following are deprecated defines for the bit fields in the TIMER_TnPMR
769 // register.
770 //
771 //*****************************************************************************
772 #define TIMER_TNPMR_TNPSMR      0x000000FF  // TimerN prescale match value
773 
774 #endif
775 
776 #endif // __HW_TIMER_H__
777