1 /* --COPYRIGHT--,BSD 2 * Copyright (c) 2017, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * --/COPYRIGHT--*/ 32 #ifndef __SYSCTL_H__ 33 #define __SYSCTL_H__ 34 35 #include <stdint.h> 36 #include <ti/devices/msp432p4xx/inc/msp.h> 37 38 /* Define to ensure that our current MSP432 has the SYSCTL module. This 39 definition is included in the device specific header file */ 40 #ifdef __MCU_HAS_SYSCTL__ 41 42 //***************************************************************************** 43 // 44 //! \addtogroup sysctl_api 45 //! @{ 46 // 47 //***************************************************************************** 48 49 //***************************************************************************** 50 // 51 // If building with a C++ compiler, make all of the definitions in this header 52 // have a C binding. 53 // 54 //***************************************************************************** 55 #ifdef __cplusplus 56 extern "C" 57 { 58 #endif 59 60 //***************************************************************************** 61 // 62 // Control specific variables 63 // 64 //***************************************************************************** 65 #define SYSCTL_SRAM_BANK7 SYSCTL_SRAM_BANKEN_BNK7_EN 66 #define SYSCTL_SRAM_BANK6 SYSCTL_SRAM_BANKEN_BNK6_EN 67 #define SYSCTL_SRAM_BANK5 SYSCTL_SRAM_BANKEN_BNK5_EN 68 #define SYSCTL_SRAM_BANK4 SYSCTL_SRAM_BANKEN_BNK4_EN 69 #define SYSCTL_SRAM_BANK3 SYSCTL_SRAM_BANKEN_BNK3_EN 70 #define SYSCTL_SRAM_BANK2 SYSCTL_SRAM_BANKEN_BNK2_EN 71 #define SYSCTL_SRAM_BANK1 SYSCTL_SRAM_BANKEN_BNK1_EN 72 73 #define SYSCTL_HARD_RESET 1 74 #define SYSCTL_SOFT_RESET 0 75 76 #define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_HALT_DMA 77 #define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_HALT_WDT 78 #define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_HALT_ADC 79 #define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_HALT_EUB3 80 #define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_HALT_EUB2 81 #define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_HALT_EUB1 82 #define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_HALT_EUB0 83 #define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_HALT_EUA3 84 #define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_HALT_EUA2 85 #define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_HALT_EUA1 86 #define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_HALT_EUA0 87 #define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_HALT_T32_0 88 #define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_HALT_T16_3 89 #define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_HALT_T16_2 90 #define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_HALT_T16_1 91 #define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_HALT_T16_0 92 93 #define SYSCTL_NMIPIN_SRC SYSCTL_NMI_CTLSTAT_PIN_SRC 94 #define SYSCTL_PCM_SRC SYSCTL_NMI_CTLSTAT_PCM_SRC 95 #define SYSCTL_PSS_SRC SYSCTL_NMI_CTLSTAT_PSS_SRC 96 #define SYSCTL_CS_SRC SYSCTL_NMI_CTLSTAT_CS_SRC 97 98 #define SYSCTL_REBOOT_KEY 0x6900 99 100 #define SYSCTL_1_2V_REF (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE 101 #define SYSCTL_1_45V_REF (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE 102 #define SYSCTL_2_5V_REF (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE 103 104 #define SYSCTL_85_DEGREES_C 4 105 #define SYSCTL_30_DEGREES_C 0 106 107 108 #define TLV_START 0x00201004 109 #define TLV_TAG_RESERVED1 1 110 #define TLV_TAG_RESERVED2 2 111 #define TLV_TAG_CS 3 112 #define TLV_TAG_FLASHCTL 4 113 #define TLV_TAG_ADC14 5 114 #define TLV_TAG_RESERVED6 6 115 #define TLV_TAG_RESERVED7 7 116 #define TLV_TAG_REF 8 117 #define TLV_TAG_RESERVED9 9 118 #define TLV_TAG_RESERVED10 10 119 #define TLV_TAG_DEVINFO 11 120 #define TLV_TAG_DIEREC 12 121 #define TLV_TAG_RANDNUM 13 122 #define TLV_TAG_RESERVED14 14 123 #define TLV_TAG_BSL 15 124 #define TLV_TAGEND 0x0BD0E11D 125 126 //***************************************************************************** 127 // 128 // Structures for TLV definitions 129 // 130 //***************************************************************************** 131 typedef struct 132 { 133 uint32_t maxProgramPulses; 134 uint32_t maxErasePulses; 135 } SysCtl_FlashTLV_Info; 136 137 typedef struct 138 { 139 uint32_t rDCOIR_FCAL_RSEL04; 140 uint32_t rDCOIR_FCAL_RSEL5; 141 uint32_t rDCOIR_MAXPOSTUNE_RSEL04; 142 uint32_t rDCOIR_MAXNEGTUNE_RSEL04; 143 uint32_t rDCOIR_MAXPOSTUNE_RSEL5; 144 uint32_t rDCOIR_MAXNEGTUNE_RSEL5; 145 uint32_t rDCOIR_CONSTK_RSEL04; 146 uint32_t rDCOIR_CONSTK_RSEL5; 147 uint32_t rDCOER_FCAL_RSEL04; 148 uint32_t rDCOER_FCAL_RSEL5; 149 uint32_t rDCOER_MAXPOSTUNE_RSEL04; 150 uint32_t rDCOER_MAXNEGTUNE_RSEL04; 151 uint32_t rDCOER_MAXPOSTUNE_RSEL5; 152 uint32_t rDCOER_MAXNEGTUNE_RSEL5; 153 uint32_t rDCOER_CONSTK_RSEL04; 154 uint32_t rDCOER_CONSTK_RSEL5; 155 156 } SysCtl_CSCalTLV_Info; 157 158 //***************************************************************************** 159 // 160 // Prototypes for the APIs. 161 // 162 //***************************************************************************** 163 164 //***************************************************************************** 165 // 166 //! Gets the size of the SRAM. 167 //! 168 //! \return The total number of bytes of SRAM. 169 // 170 //***************************************************************************** 171 extern uint_least32_t SysCtl_getSRAMSize(void); 172 173 //***************************************************************************** 174 // 175 //! Gets the size of the flash. 176 //! 177 //! \return The total number of bytes of flash. 178 // 179 //***************************************************************************** 180 extern uint_least32_t SysCtl_getFlashSize(void); 181 182 //***************************************************************************** 183 // 184 //! Reboots the device and causes the device to re-initialize itself. 185 //! 186 //! \return This function does not return. 187 // 188 //***************************************************************************** 189 extern void SysCtl_rebootDevice(void); 190 191 //***************************************************************************** 192 // 193 //! The TLV structure uses a tag or base address to identify segments of the 194 //! table where information is stored. Some examples of TLV tags are Peripheral 195 //! Descriptor, Interrupts, Info Block and Die Record. This function retrieves 196 //! the value of a tag and the length of the tag. 197 //! 198 //! \param tag represents the tag for which the information needs to be 199 //! retrieved. 200 //! Valid values are: 201 //! - \b TLV_TAG_RESERVED1 202 //! - \b TLV_TAG_RESERVED2 203 //! - \b TLV_TAG_CS 204 //! - \b TLV_TAG_FLASHCTL 205 //! - \b TLV_TAG_ADC14 206 //! - \b TLV_TAG_RESERVED6 207 //! - \b TLV_TAG_RESERVED7 208 //! - \b TLV_TAG_REF 209 //! - \b TLV_TAG_RESERVED9 210 //! - \b TLV_TAG_RESERVED10 211 //! - \b TLV_TAG_DEVINFO 212 //! - \b TLV_TAG_DIEREC 213 //! - \b TLV_TAG_RANDNUM 214 //! - \b TLV_TAG_RESERVED14 215 //! \param instance In some cases a specific tag may have more than one 216 //! instance. For example there may be multiple instances of timer 217 //! calibration data present under a single Timer Cal tag. This variable 218 //! specifies the instance for which information is to be retrieved (0, 219 //! 1, etc.). When only one instance exists; 0 is passed. 220 //! \param length Acts as a return through indirect reference. The function 221 //! retrieves the value of the TLV tag length. This value is pointed to 222 //! by *length and can be used by the application level once the 223 //! function is called. If the specified tag is not found then the 224 //! pointer is null 0. 225 //! \param data_address acts as a return through indirect reference. Once the 226 //! function is called data_address points to the pointer that holds the 227 //! value retrieved from the specified TLV tag. If the specified tag is 228 //! not found then the pointer is null 0. 229 //! 230 //! \return None 231 // 232 //***************************************************************************** 233 extern void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance, 234 uint_fast8_t *length, uint32_t **data_address); 235 236 //***************************************************************************** 237 // 238 //! Enables a set of banks in the SRAM. This can be used to optimize power 239 //! consumption when every SRAM bank isn't needed. It is important to note 240 //! that when a higher bank is enabled, all of the SRAM banks below that bank 241 //! are also enabled. For example, if the user enables SYSCTL_SRAM_BANK7, 242 //! the banks SYSCTL_SRAM_BANK1 through SYSCTL_SRAM_BANK7 will be enabled 243 //! (SRAM_BANK0 is reserved and always enabled). 244 //! 245 //! \param sramBank The SRAM bank tier to enable. 246 //! Must be only one of the following values: 247 //! - \b SYSCTL_SRAM_BANK1, 248 //! - \b SYSCTL_SRAM_BANK2, 249 //! - \b SYSCTL_SRAM_BANK3, 250 //! - \b SYSCTL_SRAM_BANK4, 251 //! - \b SYSCTL_SRAM_BANK5, 252 //! - \b SYSCTL_SRAM_BANK6, 253 //! - \b SYSCTL_SRAM_BANK7 254 //! 255 //! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled. 256 //! 257 //! \return None. 258 // 259 //***************************************************************************** 260 extern void SysCtl_enableSRAMBank(uint_fast8_t sramBank); 261 262 //***************************************************************************** 263 // 264 //! Disables a set of banks in the SRAM. This can be used to optimize power 265 //! consumption when every SRAM bank isn't needed. It is important to note 266 //! that when a higher bank is disabled, all of the SRAM banks above that bank 267 //! are also disabled. For example, if the user disables SYSCTL_SRAM_BANK5, 268 //! the banks SYSCTL_SRAM_BANK6 through SYSCTL_SRAM_BANK7 will be disabled. 269 //! 270 //! \param sramBank The SRAM bank tier to disable. 271 //! Must be only one of the following values: 272 //! - \b SYSCTL_SRAM_BANK1, 273 //! - \b SYSCTL_SRAM_BANK2, 274 //! - \b SYSCTL_SRAM_BANK3, 275 //! - \b SYSCTL_SRAM_BANK4, 276 //! - \b SYSCTL_SRAM_BANK5, 277 //! - \b SYSCTL_SRAM_BANK6, 278 //! - \b SYSCTL_SRAM_BANK7 279 //! 280 //! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled. 281 //! 282 //! \return None. 283 // 284 //***************************************************************************** 285 extern void SysCtl_disableSRAMBank(uint_fast8_t sramBank); 286 287 //***************************************************************************** 288 // 289 //! Enables retention of the specified SRAM bank register when the device goes 290 //! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM 291 //! banks specified with this function will be placed into retention mode. By 292 //! default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved) is 293 //! disabled. Retention of individual banks can be set without the restrictions 294 //! of the enable/disable functions. 295 //! 296 //! \param sramBank The SRAM banks to enable retention 297 //! Can be a bitwise OR of the following values: 298 //! - \b SYSCTL_SRAM_BANK1, 299 //! - \b SYSCTL_SRAM_BANK2, 300 //! - \b SYSCTL_SRAM_BANK3, 301 //! - \b SYSCTL_SRAM_BANK4, 302 //! - \b SYSCTL_SRAM_BANK5, 303 //! - \b SYSCTL_SRAM_BANK6, 304 //! - \b SYSCTL_SRAM_BANK7 305 //! \note \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled. 306 //! 307 //! 308 //! \return None. 309 // 310 //***************************************************************************** 311 extern void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank); 312 313 //***************************************************************************** 314 // 315 //! Disables retention of the specified SRAM bank register when the device goes 316 //! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM 317 //! banks specified with this function will not be placed into retention mode. 318 //! By default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved) 319 //! is disabled. Retention of individual banks can be set without the 320 //! restrictions of the enable/disable SRAM bank functions. 321 //! 322 //! \param sramBank The SRAM banks to disable retention 323 //! Can be a bitwise OR of the following values: 324 //! - \b SYSCTL_SRAM_BANK1, 325 //! - \b SYSCTL_SRAM_BANK2, 326 //! - \b SYSCTL_SRAM_BANK3, 327 //! - \b SYSCTL_SRAM_BANK4, 328 //! - \b SYSCTL_SRAM_BANK5, 329 //! - \b SYSCTL_SRAM_BANK6, 330 //! - \b SYSCTL_SRAM_BANK7 331 //! \note \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled. 332 //! 333 //! \return None. 334 // 335 // 336 //***************************************************************************** 337 extern void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank); 338 339 //***************************************************************************** 340 // 341 //! Makes it so that the provided peripherals will either halt execution after 342 //! a CPU HALT. Parameters in this function can be combined to account for 343 //! multiple peripherals. By default, all peripherals keep running after a 344 //! CPU HALT. 345 //! 346 //! \param devices The peripherals to continue running after a CPU HALT 347 //! This can be a bitwise OR of the following values: 348 //! - \b SYSCTL_PERIPH_DMA, 349 //! - \b SYSCTL_PERIPH_WDT, 350 //! - \b SYSCTL_PERIPH_ADC, 351 //! - \b SYSCTL_PERIPH_EUSCIB3, 352 //! - \b SYSCTL_PERIPH_EUSCIB2, 353 //! - \b SYSCTL_PERIPH_EUSCIB1 354 //! - \b SYSCTL_PERIPH_EUSCIB0, 355 //! - \b SYSCTL_PERIPH_EUSCIA3, 356 //! - \b SYSCTL_PERIPH_EUSCIA2 357 //! - \b SYSCTL_PERIPH_EUSCIA1, 358 //! - \b SYSCTL_PERIPH_EUSCIA0, 359 //! - \b SYSCTL_PERIPH_TIMER32_0_MODULE, 360 //! - \b SYSCTL_PERIPH_TIMER16_3, 361 //! - \b SYSCTL_PERIPH_TIMER16_2, 362 //! - \b SYSCTL_PERIPH_TIMER16_1, 363 //! - \b SYSCTL_PERIPH_TIMER16_0 364 //! 365 //! \return None. 366 // 367 // 368 //***************************************************************************** 369 extern void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices); 370 371 //***************************************************************************** 372 // 373 //! Makes it so that the provided peripherals will either halt execution after 374 //! a CPU HALT. Parameters in this function can be combined to account for 375 //! multiple peripherals. By default, all peripherals keep running after a 376 //! CPU HALT. 377 //! 378 //! \param devices The peripherals to disable after a CPU HALT 379 //! 380 //! The \e devices parameter can be a bitwise OR of the following values: 381 //! This can be a bitwise OR of the following values: 382 //! - \b SYSCTL_PERIPH_DMA, 383 //! - \b SYSCTL_PERIPH_WDT, 384 //! - \b SYSCTL_PERIPH_ADC, 385 //! - \b SYSCTL_PERIPH_EUSCIB3, 386 //! - \b SYSCTL_PERIPH_EUSCIB2, 387 //! - \b SYSCTL_PERIPH_EUSCIB1 388 //! - \b SYSCTL_PERIPH_EUSCIB0, 389 //! - \b SYSCTL_PERIPH_EUSCIA3, 390 //! - \b SYSCTL_PERIPH_EUSCIA2 391 //! - \b SYSCTL_PERIPH_EUSCIA1, 392 //! - \b SYSCTL_PERIPH_EUSCIA0, 393 //! - \b SYSCTL_PERIPH_TIMER32_0_MODULE, 394 //! - \b SYSCTL_PERIPH_TIMER16_3, 395 //! - \b SYSCTL_PERIPH_TIMER16_2, 396 //! - \b SYSCTL_PERIPH_TIMER16_1, 397 //! - \b SYSCTL_PERIPH_TIMER16_0 398 //! 399 //! \return None. 400 // 401 // 402 //***************************************************************************** 403 extern void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices); 404 405 //***************************************************************************** 406 // 407 //! Sets the type of RESET that happens when a watchdog timeout occurs. 408 //! 409 //! \param resetType The type of reset to set 410 //! 411 //! The \e resetType parameter must be only one of the following values: 412 //! - \b SYSCTL_HARD_RESET, 413 //! - \b SYSCTL_SOFT_RESET 414 //! 415 //! \return None. 416 // 417 // 418 //***************************************************************************** 419 extern void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType); 420 421 //***************************************************************************** 422 // 423 //! Sets the type of RESET that happens when a watchdog password violation 424 //! occurs. 425 //! 426 //! \param resetType The type of reset to set 427 //! 428 //! The \e resetType parameter must be only one of the following values: 429 //! - \b SYSCTL_HARD_RESET, 430 //! - \b SYSCTL_SOFT_RESET 431 //! 432 //! \return None. 433 // 434 // 435 //***************************************************************************** 436 extern void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType); 437 438 //***************************************************************************** 439 // 440 //! Disables NMIs for the provided modules. When disabled, a NMI flag will not 441 //! occur when a fault condition comes from the corresponding modules. 442 //! 443 //! \param flags The NMI sources to disable 444 //! Can be a bitwise OR of the following parameters: 445 //! - \b SYSCTL_NMIPIN_SRC, 446 //! - \b SYSCTL_PCM_SRC, 447 //! - \b SYSCTL_PSS_SRC, 448 //! - \b SYSCTL_CS_SRC 449 //! 450 // 451 //***************************************************************************** 452 extern void SysCtl_disableNMISource(uint_fast8_t flags); 453 454 //***************************************************************************** 455 // 456 //! Enables NMIs for the provided modules. When enabled, a NMI flag will 457 //! occur when a fault condition comes from the corresponding modules. 458 //! 459 //! \param flags The NMI sources to enable 460 //! Can be a bitwise OR of the following parameters: 461 //! - \b SYSCTL_NMIPIN_SRC, 462 //! - \b SYSCTL_PCM_SRC, 463 //! - \b SYSCTL_PSS_SRC, 464 //! - \b SYSCTL_CS_SRC 465 //! 466 // 467 //***************************************************************************** 468 extern void SysCtl_enableNMISource(uint_fast8_t flags); 469 470 //***************************************************************************** 471 // 472 //! Returns the current sources of NMIs that are enabled 473 //! 474 //! \return Bitwise OR of NMI flags that are enabled 475 // 476 //***************************************************************************** 477 extern uint_fast8_t SysCtl_getNMISourceStatus(void); 478 479 //***************************************************************************** 480 // 481 //! Enables glitch suppression on the reset pin of the device. Refer to the 482 //! device data sheet for specific information about glitch suppression 483 //! 484 //! \return None. 485 // 486 // 487 //***************************************************************************** 488 extern void SysCtl_enableGlitchFilter(void); 489 490 //***************************************************************************** 491 // 492 //! Disables glitch suppression on the reset pin of the device. Refer to the 493 //! device data sheet for specific information about glitch suppression 494 //! 495 //! \return None. 496 // 497 // 498 //***************************************************************************** 499 extern void SysCtl_disableGlitchFilter(void); 500 501 //***************************************************************************** 502 // 503 //! Retrieves the calibration constant of the temperature sensor to be used 504 //! in temperature calculation. 505 //! 506 //! \param refVoltage Reference voltage being used. 507 //! 508 //! The \e refVoltage parameter must be only one of the following values: 509 //! - \b SYSCTL_1_2V_REF 510 //! - \b SYSCTL_1_45V_REF 511 //! - \b SYSCTL_2_5V_REF 512 //! 513 //! \param temperature is the calibration temperature that the user wants to be 514 //! returned. 515 //! 516 //! The \e temperature parameter must be only one of the following values: 517 //! - \b SYSCTL_30_DEGREES_C 518 //! - \b SYSCTL_85_DEGREES_C 519 //! 520 //! \return None. 521 // 522 // 523 //***************************************************************************** 524 extern uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage, 525 uint32_t temperature); 526 527 //***************************************************************************** 528 // 529 // Mark the end of the C bindings section for C++ compilers. 530 // 531 //***************************************************************************** 532 #ifdef __cplusplus 533 } 534 #endif 535 536 //***************************************************************************** 537 // 538 // Close the Doxygen group. 539 //! @} 540 // 541 //***************************************************************************** 542 543 #endif /* __MCU_HAS_SYSCTL__ */ 544 545 #endif // __SYSCTL_H__ 546
