1 /****************************************************************************** 2 * Filename: hw_ssi_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_SSI_H__ 38 #define __HW_SSI_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // SSI component 44 // 45 //***************************************************************************** 46 // Control 0 47 #define SSI_O_CR0 0x00000000 48 49 // Control 1 50 #define SSI_O_CR1 0x00000004 51 52 // Data 53 #define SSI_O_DR 0x00000008 54 55 // Status 56 #define SSI_O_SR 0x0000000C 57 58 // Clock Prescale 59 #define SSI_O_CPSR 0x00000010 60 61 // Interrupt Mask Set and Clear 62 #define SSI_O_IMSC 0x00000014 63 64 // Raw Interrupt Status 65 #define SSI_O_RIS 0x00000018 66 67 // Masked Interrupt Status 68 #define SSI_O_MIS 0x0000001C 69 70 // Interrupt Clear 71 #define SSI_O_ICR 0x00000020 72 73 // DMA Control 74 #define SSI_O_DMACR 0x00000024 75 76 //***************************************************************************** 77 // 78 // Register: SSI_O_CR0 79 // 80 //***************************************************************************** 81 // Field: [15:8] SCR 82 // 83 // Serial clock rate: 84 // This is used to generate the transmit and receive bit rate of the SSI. The 85 // bit rate is 86 // (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). 87 // SCR is a value from 0-255. 88 #define SSI_CR0_SCR_W 8 89 #define SSI_CR0_SCR_M 0x0000FF00 90 #define SSI_CR0_SCR_S 8 91 92 // Field: [7] SPH 93 // 94 // CLKOUT phase (Motorola SPI frame format only) 95 // This bit selects the clock edge that captures data and enables it to change 96 // state. It 97 // has the most impact on the first bit transmitted by either permitting or not 98 // permitting a clock transition before the first data capture edge. 99 // ENUMs: 100 // 2ND_CLK_EDGE Data is captured on the second clock edge 101 // transition. 102 // 1ST_CLK_EDGE Data is captured on the first clock edge 103 // transition. 104 #define SSI_CR0_SPH 0x00000080 105 #define SSI_CR0_SPH_BITN 7 106 #define SSI_CR0_SPH_M 0x00000080 107 #define SSI_CR0_SPH_S 7 108 #define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 109 #define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 110 111 // Field: [6] SPO 112 // 113 // CLKOUT polarity (Motorola SPI frame format only) 114 // ENUMs: 115 // HIGH SSI produces a steady state HIGH value on the 116 // CLKOUT pin when data is not being transferred. 117 // LOW SSI produces a steady state LOW value on the 118 // CLKOUT pin when data is 119 // not being transferred. 120 #define SSI_CR0_SPO 0x00000040 121 #define SSI_CR0_SPO_BITN 6 122 #define SSI_CR0_SPO_M 0x00000040 123 #define SSI_CR0_SPO_S 6 124 #define SSI_CR0_SPO_HIGH 0x00000040 125 #define SSI_CR0_SPO_LOW 0x00000000 126 127 // Field: [5:4] FRF 128 // 129 // Frame format. 130 // The supported frame formats are Motorola SPI, TI synchronous serial and 131 // National Microwire. 132 // Value 0'b11 is reserved and shall not be used. 133 // ENUMs: 134 // NATIONAL_MICROWIRE National Microwire frame format 135 // TI_SYNC_SERIAL TI synchronous serial frame format 136 // MOTOROLA_SPI Motorola SPI frame format 137 #define SSI_CR0_FRF_W 2 138 #define SSI_CR0_FRF_M 0x00000030 139 #define SSI_CR0_FRF_S 4 140 #define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 141 #define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 142 #define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 143 144 // Field: [3:0] DSS 145 // 146 // Data Size Select. 147 // Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used. 148 // ENUMs: 149 // 16_BIT 16-bit data 150 // 15_BIT 15-bit data 151 // 14_BIT 14-bit data 152 // 13_BIT 13-bit data 153 // 12_BIT 12-bit data 154 // 11_BIT 11-bit data 155 // 10_BIT 10-bit data 156 // 9_BIT 9-bit data 157 // 8_BIT 8-bit data 158 // 7_BIT 7-bit data 159 // 6_BIT 6-bit data 160 // 5_BIT 5-bit data 161 // 4_BIT 4-bit data 162 #define SSI_CR0_DSS_W 4 163 #define SSI_CR0_DSS_M 0x0000000F 164 #define SSI_CR0_DSS_S 0 165 #define SSI_CR0_DSS_16_BIT 0x0000000F 166 #define SSI_CR0_DSS_15_BIT 0x0000000E 167 #define SSI_CR0_DSS_14_BIT 0x0000000D 168 #define SSI_CR0_DSS_13_BIT 0x0000000C 169 #define SSI_CR0_DSS_12_BIT 0x0000000B 170 #define SSI_CR0_DSS_11_BIT 0x0000000A 171 #define SSI_CR0_DSS_10_BIT 0x00000009 172 #define SSI_CR0_DSS_9_BIT 0x00000008 173 #define SSI_CR0_DSS_8_BIT 0x00000007 174 #define SSI_CR0_DSS_7_BIT 0x00000006 175 #define SSI_CR0_DSS_6_BIT 0x00000005 176 #define SSI_CR0_DSS_5_BIT 0x00000004 177 #define SSI_CR0_DSS_4_BIT 0x00000003 178 179 //***************************************************************************** 180 // 181 // Register: SSI_O_CR1 182 // 183 //***************************************************************************** 184 // Field: [3] SOD 185 // 186 // Slave-mode output disabled 187 // This bit is relevant only in the slave mode, MS=1. In multiple-slave 188 // systems, it is possible for an SSI master to broadcast a message to all 189 // slaves in the system while ensuring that only one slave drives data onto its 190 // serial output line. In such systems the RXD lines from multiple slaves could 191 // be tied together. To operate in such systems, this bitfield can be set if 192 // the SSI slave is not supposed to drive the TXD line: 193 // 194 // 0: SSI can drive the TXD output in slave mode. 195 // 1: SSI cannot drive the TXD output in slave mode. 196 #define SSI_CR1_SOD 0x00000008 197 #define SSI_CR1_SOD_BITN 3 198 #define SSI_CR1_SOD_M 0x00000008 199 #define SSI_CR1_SOD_S 3 200 201 // Field: [2] MS 202 // 203 // Master or slave mode select. This bit can be modified only when SSI is 204 // disabled, SSE=0. 205 // ENUMs: 206 // SLAVE Device configured as slave 207 // MASTER Device configured as master 208 #define SSI_CR1_MS 0x00000004 209 #define SSI_CR1_MS_BITN 2 210 #define SSI_CR1_MS_M 0x00000004 211 #define SSI_CR1_MS_S 2 212 #define SSI_CR1_MS_SLAVE 0x00000004 213 #define SSI_CR1_MS_MASTER 0x00000000 214 215 // Field: [1] SSE 216 // 217 // Synchronous serial interface enable. 218 // ENUMs: 219 // SSI_ENABLED Operation enabled 220 // SSI_DISABLED Operation disabled 221 #define SSI_CR1_SSE 0x00000002 222 #define SSI_CR1_SSE_BITN 1 223 #define SSI_CR1_SSE_M 0x00000002 224 #define SSI_CR1_SSE_S 1 225 #define SSI_CR1_SSE_SSI_ENABLED 0x00000002 226 #define SSI_CR1_SSE_SSI_DISABLED 0x00000000 227 228 // Field: [0] LBM 229 // 230 // Loop back mode: 231 // 232 // 0: Normal serial port operation enabled. 233 // 1: Output of transmit serial shifter is connected to input of receive serial 234 // shifter internally. 235 #define SSI_CR1_LBM 0x00000001 236 #define SSI_CR1_LBM_BITN 0 237 #define SSI_CR1_LBM_M 0x00000001 238 #define SSI_CR1_LBM_S 0 239 240 //***************************************************************************** 241 // 242 // Register: SSI_O_DR 243 // 244 //***************************************************************************** 245 // Field: [15:0] DATA 246 // 247 // Transmit/receive data 248 // The values read from this field or written to this field must be 249 // right-justified when SSI is programmed for a data size that is less than 16 250 // bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit 251 // logic. The receive logic automatically right-justifies. 252 #define SSI_DR_DATA_W 16 253 #define SSI_DR_DATA_M 0x0000FFFF 254 #define SSI_DR_DATA_S 0 255 256 //***************************************************************************** 257 // 258 // Register: SSI_O_SR 259 // 260 //***************************************************************************** 261 // Field: [4] BSY 262 // 263 // Serial interface busy: 264 // 265 // 0: SSI is idle 266 // 1: SSI is currently transmitting and/or receiving a frame or the transmit 267 // FIFO is not empty. 268 #define SSI_SR_BSY 0x00000010 269 #define SSI_SR_BSY_BITN 4 270 #define SSI_SR_BSY_M 0x00000010 271 #define SSI_SR_BSY_S 4 272 273 // Field: [3] RFF 274 // 275 // Receive FIFO full: 276 // 277 // 0: Receive FIFO is not full. 278 // 1: Receive FIFO is full. 279 #define SSI_SR_RFF 0x00000008 280 #define SSI_SR_RFF_BITN 3 281 #define SSI_SR_RFF_M 0x00000008 282 #define SSI_SR_RFF_S 3 283 284 // Field: [2] RNE 285 // 286 // Receive FIFO not empty 287 // 288 // 0: Receive FIFO is empty. 289 // 1: Receive FIFO is not empty. 290 #define SSI_SR_RNE 0x00000004 291 #define SSI_SR_RNE_BITN 2 292 #define SSI_SR_RNE_M 0x00000004 293 #define SSI_SR_RNE_S 2 294 295 // Field: [1] TNF 296 // 297 // Transmit FIFO not full: 298 // 299 // 0: Transmit FIFO is full. 300 // 1: Transmit FIFO is not full. 301 #define SSI_SR_TNF 0x00000002 302 #define SSI_SR_TNF_BITN 1 303 #define SSI_SR_TNF_M 0x00000002 304 #define SSI_SR_TNF_S 1 305 306 // Field: [0] TFE 307 // 308 // Transmit FIFO empty: 309 // 310 // 0: Transmit FIFO is not empty. 311 // 1: Transmit FIFO is empty. 312 #define SSI_SR_TFE 0x00000001 313 #define SSI_SR_TFE_BITN 0 314 #define SSI_SR_TFE_M 0x00000001 315 #define SSI_SR_TFE_S 0 316 317 //***************************************************************************** 318 // 319 // Register: SSI_O_CPSR 320 // 321 //***************************************************************************** 322 // Field: [7:0] CPSDVSR 323 // 324 // Clock prescale divisor: 325 // This field specifies the division factor by which the input system clock to 326 // SSI must be internally divided before further use. 327 // The value programmed into this field must be an even non-zero number 328 // (2-254). The least significant bit of the programmed number is hard-coded to 329 // zero. If an odd number is written to this register, data read back from 330 // this register has the least significant bit as zero. 331 #define SSI_CPSR_CPSDVSR_W 8 332 #define SSI_CPSR_CPSDVSR_M 0x000000FF 333 #define SSI_CPSR_CPSDVSR_S 0 334 335 //***************************************************************************** 336 // 337 // Register: SSI_O_IMSC 338 // 339 //***************************************************************************** 340 // Field: [3] TXIM 341 // 342 // Transmit FIFO interrupt mask: 343 // A read returns the current mask for transmit FIFO interrupt. On a write of 344 // 1, the mask for transmit FIFO interrupt is set which means the interrupt 345 // state will be reflected in MIS.TXMIS. A write of 0 clears the mask which 346 // means MIS.TXMIS will not reflect the interrupt. 347 #define SSI_IMSC_TXIM 0x00000008 348 #define SSI_IMSC_TXIM_BITN 3 349 #define SSI_IMSC_TXIM_M 0x00000008 350 #define SSI_IMSC_TXIM_S 3 351 352 // Field: [2] RXIM 353 // 354 // Receive FIFO interrupt mask: 355 // A read returns the current mask for receive FIFO interrupt. On a write of 1, 356 // the mask for receive FIFO interrupt is set which means the interrupt state 357 // will be reflected in MIS.RXMIS. A write of 0 clears the mask which means 358 // MIS.RXMIS will not reflect the interrupt. 359 #define SSI_IMSC_RXIM 0x00000004 360 #define SSI_IMSC_RXIM_BITN 2 361 #define SSI_IMSC_RXIM_M 0x00000004 362 #define SSI_IMSC_RXIM_S 2 363 364 // Field: [1] RTIM 365 // 366 // Receive timeout interrupt mask: 367 // A read returns the current mask for receive timeout interrupt. On a write of 368 // 1, the mask for receive timeout interrupt is set which means the interrupt 369 // state will be reflected in MIS.RTMIS. A write of 0 clears the mask which 370 // means MIS.RTMIS will not reflect the interrupt. 371 #define SSI_IMSC_RTIM 0x00000002 372 #define SSI_IMSC_RTIM_BITN 1 373 #define SSI_IMSC_RTIM_M 0x00000002 374 #define SSI_IMSC_RTIM_S 1 375 376 // Field: [0] RORIM 377 // 378 // Receive overrun interrupt mask: 379 // A read returns the current mask for receive overrun interrupt. On a write of 380 // 1, the mask for receive overrun interrupt is set which means the interrupt 381 // state will be reflected in MIS.RORMIS. A write of 0 clears the mask which 382 // means MIS.RORMIS will not reflect the interrupt. 383 #define SSI_IMSC_RORIM 0x00000001 384 #define SSI_IMSC_RORIM_BITN 0 385 #define SSI_IMSC_RORIM_M 0x00000001 386 #define SSI_IMSC_RORIM_S 0 387 388 //***************************************************************************** 389 // 390 // Register: SSI_O_RIS 391 // 392 //***************************************************************************** 393 // Field: [3] TXRIS 394 // 395 // Raw transmit FIFO interrupt status: 396 // The transmit interrupt is asserted when there are four or fewer valid 397 // entries in the transmit FIFO. The transmit interrupt is not qualified with 398 // the SSI enable signal. Therefore one of the following ways can be used: 399 // - data can be written to the transmit FIFO prior to enabling the SSI and 400 // the 401 // interrupts. 402 // - SSI and interrupts can be enabled so that data can be written to the 403 // transmit FIFO by an interrupt service routine. 404 #define SSI_RIS_TXRIS 0x00000008 405 #define SSI_RIS_TXRIS_BITN 3 406 #define SSI_RIS_TXRIS_M 0x00000008 407 #define SSI_RIS_TXRIS_S 3 408 409 // Field: [2] RXRIS 410 // 411 // Raw interrupt state of receive FIFO interrupt: 412 // The receive interrupt is asserted when there are four or more valid entries 413 // in the receive FIFO. 414 #define SSI_RIS_RXRIS 0x00000004 415 #define SSI_RIS_RXRIS_BITN 2 416 #define SSI_RIS_RXRIS_M 0x00000004 417 #define SSI_RIS_RXRIS_S 2 418 419 // Field: [1] RTRIS 420 // 421 // Raw interrupt state of receive timeout interrupt: 422 // The receive timeout interrupt is asserted when the receive FIFO is not empty 423 // and SSI has remained idle for a fixed 32 bit period. This mechanism can be 424 // used to notify the user that data is still present in the receive FIFO and 425 // requires servicing. This interrupt is deasserted if the receive FIFO becomes 426 // empty by subsequent reads, or if new data is received on RXD. 427 // It can also be cleared by writing to ICR.RTIC. 428 #define SSI_RIS_RTRIS 0x00000002 429 #define SSI_RIS_RTRIS_BITN 1 430 #define SSI_RIS_RTRIS_M 0x00000002 431 #define SSI_RIS_RTRIS_S 1 432 433 // Field: [0] RORRIS 434 // 435 // Raw interrupt state of receive overrun interrupt: 436 // The receive overrun interrupt is asserted when the FIFO is already full and 437 // an additional data frame is received, causing an overrun of the FIFO. Data 438 // is over-written in the 439 // receive shift register, but not the FIFO so the FIFO contents stay valid. 440 // It can also be cleared by writing to ICR.RORIC. 441 #define SSI_RIS_RORRIS 0x00000001 442 #define SSI_RIS_RORRIS_BITN 0 443 #define SSI_RIS_RORRIS_M 0x00000001 444 #define SSI_RIS_RORRIS_S 0 445 446 //***************************************************************************** 447 // 448 // Register: SSI_O_MIS 449 // 450 //***************************************************************************** 451 // Field: [3] TXMIS 452 // 453 // Masked interrupt state of transmit FIFO interrupt: 454 // This field returns the masked interrupt state of transmit FIFO interrupt 455 // which is the AND product of raw interrupt state RIS.TXRIS and the mask 456 // setting IMSC.TXIM. 457 #define SSI_MIS_TXMIS 0x00000008 458 #define SSI_MIS_TXMIS_BITN 3 459 #define SSI_MIS_TXMIS_M 0x00000008 460 #define SSI_MIS_TXMIS_S 3 461 462 // Field: [2] RXMIS 463 // 464 // Masked interrupt state of receive FIFO interrupt: 465 // This field returns the masked interrupt state of receive FIFO interrupt 466 // which is the AND product of raw interrupt state RIS.RXRIS and the mask 467 // setting IMSC.RXIM. 468 #define SSI_MIS_RXMIS 0x00000004 469 #define SSI_MIS_RXMIS_BITN 2 470 #define SSI_MIS_RXMIS_M 0x00000004 471 #define SSI_MIS_RXMIS_S 2 472 473 // Field: [1] RTMIS 474 // 475 // Masked interrupt state of receive timeout interrupt: 476 // This field returns the masked interrupt state of receive timeout interrupt 477 // which is the AND product of raw interrupt state RIS.RTRIS and the mask 478 // setting IMSC.RTIM. 479 #define SSI_MIS_RTMIS 0x00000002 480 #define SSI_MIS_RTMIS_BITN 1 481 #define SSI_MIS_RTMIS_M 0x00000002 482 #define SSI_MIS_RTMIS_S 1 483 484 // Field: [0] RORMIS 485 // 486 // Masked interrupt state of receive overrun interrupt: 487 // This field returns the masked interrupt state of receive overrun interrupt 488 // which is the AND product of raw interrupt state RIS.RORRIS and the mask 489 // setting IMSC.RORIM. 490 #define SSI_MIS_RORMIS 0x00000001 491 #define SSI_MIS_RORMIS_BITN 0 492 #define SSI_MIS_RORMIS_M 0x00000001 493 #define SSI_MIS_RORMIS_S 0 494 495 //***************************************************************************** 496 // 497 // Register: SSI_O_ICR 498 // 499 //***************************************************************************** 500 // Field: [1] RTIC 501 // 502 // Clear the receive timeout interrupt: 503 // Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 504 // has no effect. 505 #define SSI_ICR_RTIC 0x00000002 506 #define SSI_ICR_RTIC_BITN 1 507 #define SSI_ICR_RTIC_M 0x00000002 508 #define SSI_ICR_RTIC_S 1 509 510 // Field: [0] RORIC 511 // 512 // Clear the receive overrun interrupt: 513 // Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). 514 // Writing 0 has no effect. 515 #define SSI_ICR_RORIC 0x00000001 516 #define SSI_ICR_RORIC_BITN 0 517 #define SSI_ICR_RORIC_M 0x00000001 518 #define SSI_ICR_RORIC_S 0 519 520 //***************************************************************************** 521 // 522 // Register: SSI_O_DMACR 523 // 524 //***************************************************************************** 525 // Field: [1] TXDMAE 526 // 527 // Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is 528 // enabled. 529 #define SSI_DMACR_TXDMAE 0x00000002 530 #define SSI_DMACR_TXDMAE_BITN 1 531 #define SSI_DMACR_TXDMAE_M 0x00000002 532 #define SSI_DMACR_TXDMAE_S 1 533 534 // Field: [0] RXDMAE 535 // 536 // Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is 537 // enabled. 538 #define SSI_DMACR_RXDMAE 0x00000001 539 #define SSI_DMACR_RXDMAE_BITN 0 540 #define SSI_DMACR_RXDMAE_M 0x00000001 541 #define SSI_DMACR_RXDMAE_S 0 542 543 544 #endif // __SSI__ 545
