1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_SHAMD5_H__ 35 #define __HW_SHAMD5_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the SHAMD5_P register offsets. 40 // 41 //***************************************************************************** 42 #define SHAMD5_O_ODIGEST_A 0x00000000 // WRITE: Outer Digest [127:96] for 43 // MD5 [159:128] for SHA-1 [255:224] 44 // for SHA-2 / HMAC Key [31:0] for 45 // HMAC key proc READ: Outer Digest 46 // [127:96] for MD5 [159:128] for 47 // SHA-1 [255:224] for SHA-2 48 #define SHAMD5_O_ODIGEST_B 0x00000004 // WRITE: Outer Digest [95:64] for 49 // MD5 [127:96] for SHA-1 [223:192] 50 // for SHA-2 / HMAC Key [63:32] for 51 // HMAC key proc READ: Outer Digest 52 // [95:64] for MD5 [127:96] for 53 // SHA-1 [223:192] for SHA-2 54 #define SHAMD5_O_ODIGEST_C 0x00000008 // WRITE: Outer Digest [63:32] for 55 // MD5 [95:64] for SHA-1 [191:160] 56 // for SHA-2 / HMAC Key [95:64] for 57 // HMAC key proc READ: Outer Digest 58 // [63:32] for MD5 [95:64] for SHA-1 59 // [191:160] for SHA-2 60 #define SHAMD5_O_ODIGEST_D 0x0000000C // WRITE: Outer Digest [31:0] for 61 // MD5 [63:31] for SHA-1 [159:128] 62 // for SHA-2 / HMAC Key [127:96] for 63 // HMAC key proc READ: Outer Digest 64 // [31:0] for MD5 [63:32] for SHA-1 65 // [159:128] for SHA-2 66 #define SHAMD5_O_ODIGEST_E 0x00000010 // WRITE: Outer Digest [31:0] for 67 // SHA-1 [127:96] for SHA-2 / HMAC 68 // Key [159:128] for HMAC key proc 69 // READ: Outer Digest [31:0] for 70 // SHA-1 [127:96] for SHA-2 71 #define SHAMD5_O_ODIGEST_F 0x00000014 // WRITE: Outer Digest [95:64] for 72 // SHA-2 / HMAC Key [191:160] for 73 // HMAC key proc READ: Outer Digest 74 // [95:64] for SHA-2 75 #define SHAMD5_O_ODIGEST_G 0x00000018 // WRITE: Outer Digest [63:32] for 76 // SHA-2 / HMAC Key [223:192] for 77 // HMAC key proc READ: Outer Digest 78 // [63:32] for SHA-2 79 #define SHAMD5_O_ODIGEST_H 0x0000001C // WRITE: Outer Digest [31:0] for 80 // SHA-2 / HMAC Key [255:224] for 81 // HMAC key proc READ: Outer Digest 82 // [31:0] for SHA-2 83 #define SHAMD5_O_IDIGEST_A 0x00000020 // WRITE: Inner / Initial Digest 84 // [127:96] for MD5 [159:128] for 85 // SHA-1 [255:224] for SHA-2 / HMAC 86 // Key [287:256] for HMAC key proc 87 // READ: Intermediate / Inner Digest 88 // [127:96] for MD5 [159:128] for 89 // SHA-1 [255:224] for SHA-2 / 90 // Result Digest/MAC [127:96] for 91 // MD5 [159:128] for SHA-1 [223:192] 92 // for SHA-2 224 [255:224] for SHA-2 93 // 256 94 #define SHAMD5_O_IDIGEST_B 0x00000024 // WRITE: Inner / Initial Digest 95 // [95:64] for MD5 [127:96] for 96 // SHA-1 [223:192] for SHA-2 / HMAC 97 // Key [319:288] for HMAC key proc 98 // READ: Intermediate / Inner Digest 99 // [95:64] for MD5 [127:96] for 100 // SHA-1 [223:192] for SHA-2 / 101 // Result Digest/MAC [95:64] for MD5 102 // [127:96] for SHA-1 [191:160] for 103 // SHA-2 224 [223:192] for SHA-2 256 104 #define SHAMD5_O_IDIGEST_C 0x00000028 // WRITE: Inner / Initial Digest 105 // [63:32] for MD5 [95:64] for SHA-1 106 // [191:160] for SHA- 2 / HMAC Key 107 // [351:320] for HMAC key proc READ: 108 // Intermediate / Inner Digest 109 // [63:32] for MD5 [95:64] for SHA-1 110 // [191:160] for SHA-2 / Result 111 // Digest/MAC [63:32] for MD5 112 // [95:64] for SHA-1 [159:128] for 113 // SHA-2 224 [191:160] for SHA-2 256 114 #define SHAMD5_O_IDIGEST_D 0x0000002C // WRITE: Inner / Initial Digest 115 // [31:0] for MD5 [63:32] for SHA-1 116 // [159:128] for SHA-2 / HMAC Key 117 // [383:352] for HMAC key proc READ: 118 // Intermediate / Inner Digest 119 // [31:0] for MD5 [63:32] for SHA-1 120 // [159:128] for SHA-2 / Result 121 // Digest/MAC [31:0] for MD5 [63:32] 122 // for SHA-1 [127:96] for SHA-2 224 123 // [159:128] for SHA-2 256 124 #define SHAMD5_O_IDIGEST_E 0x00000030 // WRITE: Inner / Initial Digest 125 // [31:0] for SHA-1 [127:96] for 126 // SHA-2 / HMAC Key [415:384] for 127 // HMAC key proc READ: Intermediate 128 // / Inner Digest [31:0] for SHA-1 129 // [127:96] for SHA-2 / Result 130 // Digest/MAC [31:0] for SHA-1 131 // [95:64] for SHA-2 224 [127:96] 132 // for SHA-2 256 133 #define SHAMD5_O_IDIGEST_F 0x00000034 // WRITE: Inner / Initial Digest 134 // [95:64] for SHA-2 / HMAC Key 135 // [447:416] for HMAC key proc READ: 136 // Intermediate / Inner Digest 137 // [95:64] for SHA-2 / Result 138 // Digest/MAC [63:32] for SHA-2 224 139 // [95:64] for SHA-2 256 140 #define SHAMD5_O_IDIGEST_G 0x00000038 // WRITE: Inner / Initial Digest 141 // [63:32] for SHA-2 / HMAC Key 142 // [479:448] for HMAC key proc READ: 143 // Intermediate / Inner Digest 144 // [63:32] for SHA-2 / Result 145 // Digest/MAC [31:0] for SHA-2 224 146 // [63:32] for SHA-2 256 147 #define SHAMD5_O_IDIGEST_H 0x0000003C // WRITE: Inner / Initial Digest 148 // [31:0] for SHA-2 / HMAC Key 149 // [511:480] for HMAC key proc READ: 150 // Intermediate / Inner Digest 151 // [31:0] for SHA-2 / Result 152 // Digest/MAC [31:0] for SHA-2 256 153 #define SHAMD5_O_DIGEST_COUNT 0x00000040 // WRITE: Initial Digest Count 154 // ([31:6] only [5:0] assumed 0) 155 // READ: Result / IntermediateDigest 156 // Count The initial digest byte 157 // count for hash/HMAC continue 158 // operations (HMAC Key Processing = 159 // 0 and Use Algorithm Constants = 160 // 0) on the Secure World must be 161 // written to this register prior to 162 // starting the operation by writing 163 // to S_HASH_MODE. When either HMAC 164 // Key Processing is 1 or Use 165 // Algorithm Constants is 1 this 166 // register does not need to be 167 // written it will be overwritten 168 // with 64 (1 hash block of key XOR 169 // ipad) or 0 respectively 170 // automatically. When starting a 171 // HMAC operation from pre-computes 172 // (HMAC Key Processing is 0) then 173 // the value 64 must be written here 174 // to compensate for the appended 175 // key XOR ipad block. Note that the 176 // value written should always be a 177 // 64 byte multiple the lower 6 bits 178 // written are ignored. The updated 179 // digest byte count (initial digest 180 // byte count + bytes processed) can 181 // be read from this register when 182 // the status register indicates 183 // that the operation is done or 184 // suspended due to a context switch 185 // request or when a Secure World 186 // context out DMA is requested. In 187 // Advanced DMA mode when not 188 // suspended with a partial result 189 // reading the SHAMD5_DIGEST_COUNT 190 // register triggers the Hash/HMAC 191 // Engine to start the next context 192 // input DMA. Therefore reading the 193 // SHAMD5_DIGEST_COUNT register 194 // should always be the last 195 // context-read action if not 196 // suspended with a partial result 197 // (i.e. PartHashReady interrupt not 198 // pending). 199 #define SHAMD5_O_MODE 0x00000044 // Register SHAMD5_MODE 200 #define SHAMD5_O_LENGTH 0x00000048 // WRITE: Block Length / Remaining 201 // Byte Count (bytes) READ: 202 // Remaining Byte Count. The value 203 // programmed MUST be a 64-byte 204 // multiple if Close Hash is set to 205 // 0. This register is also the 206 // trigger to start processing: once 207 // this register is written the core 208 // will commence requesting input 209 // data via DMA or IRQ (if 210 // programmed length > 0) and start 211 // processing. The remaining byte 212 // count for the active operation 213 // can be read from this register 214 // when the interrupt status 215 // register indicates that the 216 // operation is suspended due to a 217 // context switch request. 218 #define SHAMD5_O_DATA0_IN 0x00000080 // Data input message 0 219 #define SHAMD5_O_DATA1_IN 0x00000084 // Data input message 1 220 #define SHAMD5_O_DATA2_IN 0x00000088 // Data input message 2 221 #define SHAMD5_O_DATA3_IN 0x0000008C // Data input message 3 222 #define SHAMD5_O_DATA4_IN 0x00000090 // Data input message 4 223 #define SHAMD5_O_DATA5_IN 0x00000094 // Data input message 5 224 #define SHAMD5_O_DATA6_IN 0x00000098 // Data input message 6 225 #define SHAMD5_O_DATA7_IN 0x0000009C // Data input message 7 226 #define SHAMD5_O_DATA8_IN 0x000000A0 // Data input message 8 227 #define SHAMD5_O_DATA9_IN 0x000000A4 // Data input message 9 228 #define SHAMD5_O_DATA10_IN 0x000000A8 // Data input message 10 229 #define SHAMD5_O_DATA11_IN 0x000000AC // Data input message 11 230 #define SHAMD5_O_DATA12_IN 0x000000B0 // Data input message 12 231 #define SHAMD5_O_DATA13_IN 0x000000B4 // Data input message 13 232 #define SHAMD5_O_DATA14_IN 0x000000B8 // Data input message 14 233 #define SHAMD5_O_DATA15_IN 0x000000BC // Data input message 15 234 #define SHAMD5_O_REVISION 0x00000100 // Register SHAMD5_REV 235 #define SHAMD5_O_SYSCONFIG 0x00000110 // Register SHAMD5_SYSCONFIG 236 #define SHAMD5_O_SYSSTATUS 0x00000114 // Register SHAMD5_SYSSTATUS 237 #define SHAMD5_O_IRQSTATUS 0x00000118 // Register SHAMD5_IRQSTATUS 238 #define SHAMD5_O_IRQENABLE 0x0000011C // Register SHAMD5_IRQENABLE. The 239 // SHAMD5_IRQENABLE register contains 240 // an enable bit for each unique 241 // interrupt for the public side. An 242 // interrupt is enabled when both 243 // the global enable in 244 // SHAMD5_SYSCONFIG (PIT_en) and the 245 // bit in this register are both set 246 // to 1. An interrupt that is 247 // enabled is propagated to the 248 // SINTREQUEST_P output. Please note 249 // that the dedicated partial hash 250 // output (SINTREQUEST_PART_P) is 251 // not affected by this register it 252 // is only affected by the global 253 // enable SHAMD5_SYSCONFIG (PIT_en). 254 #define SHAMD5_O_HASH512_ODIGEST_A \ 255 0x00000200 256 257 #define SHAMD5_O_HASH512_ODIGEST_B \ 258 0x00000204 259 260 #define SHAMD5_O_HASH512_ODIGEST_C \ 261 0x00000208 262 263 #define SHAMD5_O_HASH512_ODIGEST_D \ 264 0x0000020C 265 266 #define SHAMD5_O_HASH512_ODIGEST_E \ 267 0x00000210 268 269 #define SHAMD5_O_HASH512_ODIGEST_F \ 270 0x00000214 271 272 #define SHAMD5_O_HASH512_ODIGEST_G \ 273 0x00000218 274 275 #define SHAMD5_O_HASH512_ODIGEST_H \ 276 0x0000021C 277 278 #define SHAMD5_O_HASH512_ODIGEST_I \ 279 0x00000220 280 281 #define SHAMD5_O_HASH512_ODIGEST_J \ 282 0x00000224 283 284 #define SHAMD5_O_HASH512_ODIGEST_K \ 285 0x00000228 286 287 #define SHAMD5_O_HASH512_ODIGEST_L \ 288 0x0000022C 289 290 #define SHAMD5_O_HASH512_ODIGEST_M \ 291 0x00000230 292 293 #define SHAMD5_O_HASH512_ODIGEST_N \ 294 0x00000234 295 296 #define SHAMD5_O_HASH512_ODIGEST_O \ 297 0x00000238 298 299 #define SHAMD5_O_HASH512_ODIGEST_P \ 300 0x0000023C 301 302 #define SHAMD5_O_HASH512_IDIGEST_A \ 303 0x00000240 304 305 #define SHAMD5_O_HASH512_IDIGEST_B \ 306 0x00000244 307 308 #define SHAMD5_O_HASH512_IDIGEST_C \ 309 0x00000248 310 311 #define SHAMD5_O_HASH512_IDIGEST_D \ 312 0x0000024C 313 314 #define SHAMD5_O_HASH512_IDIGEST_E \ 315 0x00000250 316 317 #define SHAMD5_O_HASH512_IDIGEST_F \ 318 0x00000254 319 320 #define SHAMD5_O_HASH512_IDIGEST_G \ 321 0x00000258 322 323 #define SHAMD5_O_HASH512_IDIGEST_H \ 324 0x0000025C 325 326 #define SHAMD5_O_HASH512_IDIGEST_I \ 327 0x00000260 328 329 #define SHAMD5_O_HASH512_IDIGEST_J \ 330 0x00000264 331 332 #define SHAMD5_O_HASH512_IDIGEST_K \ 333 0x00000268 334 335 #define SHAMD5_O_HASH512_IDIGEST_L \ 336 0x0000026C 337 338 #define SHAMD5_O_HASH512_IDIGEST_M \ 339 0x00000270 340 341 #define SHAMD5_O_HASH512_IDIGEST_N \ 342 0x00000274 343 344 #define SHAMD5_O_HASH512_IDIGEST_O \ 345 0x00000278 346 347 #define SHAMD5_O_HASH512_IDIGEST_P \ 348 0x0000027C 349 350 #define SHAMD5_O_HASH512_DIGEST_COUNT \ 351 0x00000280 352 353 #define SHAMD5_O_HASH512_MODE 0x00000284 354 #define SHAMD5_O_HASH512_LENGTH 0x00000288 355 356 357 358 //****************************************************************************** 359 // 360 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A register. 361 // 362 //****************************************************************************** 363 #define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // data 364 #define SHAMD5_ODIGEST_A_DATA_S 0 365 //****************************************************************************** 366 // 367 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B register. 368 // 369 //****************************************************************************** 370 #define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // data 371 #define SHAMD5_ODIGEST_B_DATA_S 0 372 //****************************************************************************** 373 // 374 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C register. 375 // 376 //****************************************************************************** 377 #define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // data 378 #define SHAMD5_ODIGEST_C_DATA_S 0 379 //****************************************************************************** 380 // 381 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D register. 382 // 383 //****************************************************************************** 384 #define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // data 385 #define SHAMD5_ODIGEST_D_DATA_S 0 386 //****************************************************************************** 387 // 388 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E register. 389 // 390 //****************************************************************************** 391 #define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // data 392 #define SHAMD5_ODIGEST_E_DATA_S 0 393 //****************************************************************************** 394 // 395 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F register. 396 // 397 //****************************************************************************** 398 #define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // data 399 #define SHAMD5_ODIGEST_F_DATA_S 0 400 //****************************************************************************** 401 // 402 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G register. 403 // 404 //****************************************************************************** 405 #define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // data 406 #define SHAMD5_ODIGEST_G_DATA_S 0 407 //****************************************************************************** 408 // 409 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H register. 410 // 411 //****************************************************************************** 412 #define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // data 413 #define SHAMD5_ODIGEST_H_DATA_S 0 414 //****************************************************************************** 415 // 416 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A register. 417 // 418 //****************************************************************************** 419 #define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // data 420 #define SHAMD5_IDIGEST_A_DATA_S 0 421 //****************************************************************************** 422 // 423 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B register. 424 // 425 //****************************************************************************** 426 #define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // data 427 #define SHAMD5_IDIGEST_B_DATA_S 0 428 //****************************************************************************** 429 // 430 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C register. 431 // 432 //****************************************************************************** 433 #define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // data 434 #define SHAMD5_IDIGEST_C_DATA_S 0 435 //****************************************************************************** 436 // 437 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D register. 438 // 439 //****************************************************************************** 440 #define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // data 441 #define SHAMD5_IDIGEST_D_DATA_S 0 442 //****************************************************************************** 443 // 444 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E register. 445 // 446 //****************************************************************************** 447 #define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // data 448 #define SHAMD5_IDIGEST_E_DATA_S 0 449 //****************************************************************************** 450 // 451 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F register. 452 // 453 //****************************************************************************** 454 #define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // data 455 #define SHAMD5_IDIGEST_F_DATA_S 0 456 //****************************************************************************** 457 // 458 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G register. 459 // 460 //****************************************************************************** 461 #define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // data 462 #define SHAMD5_IDIGEST_G_DATA_S 0 463 //****************************************************************************** 464 // 465 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H register. 466 // 467 //****************************************************************************** 468 #define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // data 469 #define SHAMD5_IDIGEST_H_DATA_S 0 470 //****************************************************************************** 471 // 472 // The following are defines for the bit fields in the 473 // SHAMD5_O_DIGEST_COUNT register. 474 // 475 //****************************************************************************** 476 #define SHAMD5_DIGEST_COUNT_DATA_M \ 477 0xFFFFFFFF // data 478 479 #define SHAMD5_DIGEST_COUNT_DATA_S 0 480 //****************************************************************************** 481 // 482 // The following are defines for the bit fields in the SHAMD5_O_MODE register. 483 // 484 //****************************************************************************** 485 #define SHAMD5_MODE_HMAC_OUTER_HASH \ 486 0x00000080 // The HMAC Outer Hash is performed 487 // on the hash digest when the inner 488 // hash hash finished (block length 489 // exhausted and final hash 490 // performed if close_hash is 1). 491 // This bit should normally be set 492 // together with close_hash to 493 // finish the inner hash first or 494 // Block Length should be zero (HMAC 495 // continue with the just outer hash 496 // to be done). Auto cleared 497 // internally when outer hash 498 // performed. 0 No operation 1 hmac 499 // processing 500 501 #define SHAMD5_MODE_HMAC_KEY_PROC \ 502 0x00000020 // Performs HMAC key processing on 503 // the 512 bit HMAC key loaded into 504 // the SHAMD5_IDIGEST_{A to H} and 505 // SHAMD5_ODIGEST_{A to H} register 506 // block. Once HMAC key processing 507 // is finished this bit is 508 // automatically cleared and the 509 // resulting Inner and Outer digest 510 // is available from 511 // SHAMD5_IDIGEST_{A to H} and 512 // SHAMD5_ODIGEST_{A to H} 513 // respectively after which regular 514 // hash processing (using 515 // SHAMD5_IDIGEST_{A to H} as initial 516 // digest) will commence until the 517 // Block Length is exhausted. 0 No 518 // operation. 1 Hmac processing. 519 520 #define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding the 521 // hash/HMAC will be 'closed' at the 522 // end of the block as per 523 // MD5/SHA-1/SHA-2 specification 524 // (i.e. appropriate padding is 525 // added) or no padding is done 526 // allowing the hash to be continued 527 // later. However if the hash/HMAC 528 // is not closed then the Block 529 // Length MUST be a multiple of 64 530 // bytes to ensure correct 531 // operation. Auto cleared 532 // internally when hash closed. 0 No 533 // padding hash computation can be 534 // contimued. 1 Last packet will be 535 // padded. 536 #define SHAMD5_MODE_ALGO_CONSTANT \ 537 0x00000008 // The initial digest register will 538 // be overwritten with the algorithm 539 // constants for the selected 540 // algorithm when hashing and the 541 // initial digest count register 542 // will be reset to 0. This will 543 // start a normal hash operation. 544 // When continuing an existing hash 545 // or when performing an HMAC 546 // operation this register must be 547 // set to 0 and the 548 // intermediate/inner digest or HMAC 549 // key and digest count need to be 550 // written to the context input 551 // registers prior to writing 552 // SHAMD5_MODE. Auto cleared 553 // internally after first block 554 // processed. 0 Use pre-calculated 555 // digest (from an other operation) 556 // 1 Use constants of the selected 557 // algo. 558 559 #define SHAMD5_MODE_ALGO_M 0x00000006 // These bits select the hash 560 // algorithm to be used for 561 // processing: 0x0 md5_128 algorithm 562 // 0x1 sha1_160 algorithm 0x2 563 // sha2_224 algorithm 0x3 sha2_256 564 // algorithm 565 #define SHAMD5_MODE_ALGO_S 1 566 //****************************************************************************** 567 // 568 // The following are defines for the bit fields in the SHAMD5_O_LENGTH register. 569 // 570 //****************************************************************************** 571 #define SHAMD5_LENGTH_DATA_M 0xFFFFFFFF // data 572 #define SHAMD5_LENGTH_DATA_S 0 573 //****************************************************************************** 574 // 575 // The following are defines for the bit fields in the SHAMD5_O_DATA0_IN register. 576 // 577 //****************************************************************************** 578 #define SHAMD5_DATA0_IN_DATA0_IN_M \ 579 0xFFFFFFFF // data 580 581 #define SHAMD5_DATA0_IN_DATA0_IN_S 0 582 //****************************************************************************** 583 // 584 // The following are defines for the bit fields in the SHAMD5_O_DATA1_IN register. 585 // 586 //****************************************************************************** 587 #define SHAMD5_DATA1_IN_DATA1_IN_M \ 588 0xFFFFFFFF // data 589 590 #define SHAMD5_DATA1_IN_DATA1_IN_S 0 591 //****************************************************************************** 592 // 593 // The following are defines for the bit fields in the SHAMD5_O_DATA2_IN register. 594 // 595 //****************************************************************************** 596 #define SHAMD5_DATA2_IN_DATA2_IN_M \ 597 0xFFFFFFFF // data 598 599 #define SHAMD5_DATA2_IN_DATA2_IN_S 0 600 //****************************************************************************** 601 // 602 // The following are defines for the bit fields in the SHAMD5_O_DATA3_IN register. 603 // 604 //****************************************************************************** 605 #define SHAMD5_DATA3_IN_DATA3_IN_M \ 606 0xFFFFFFFF // data 607 608 #define SHAMD5_DATA3_IN_DATA3_IN_S 0 609 //****************************************************************************** 610 // 611 // The following are defines for the bit fields in the SHAMD5_O_DATA4_IN register. 612 // 613 //****************************************************************************** 614 #define SHAMD5_DATA4_IN_DATA4_IN_M \ 615 0xFFFFFFFF // data 616 617 #define SHAMD5_DATA4_IN_DATA4_IN_S 0 618 //****************************************************************************** 619 // 620 // The following are defines for the bit fields in the SHAMD5_O_DATA5_IN register. 621 // 622 //****************************************************************************** 623 #define SHAMD5_DATA5_IN_DATA5_IN_M \ 624 0xFFFFFFFF // data 625 626 #define SHAMD5_DATA5_IN_DATA5_IN_S 0 627 //****************************************************************************** 628 // 629 // The following are defines for the bit fields in the SHAMD5_O_DATA6_IN register. 630 // 631 //****************************************************************************** 632 #define SHAMD5_DATA6_IN_DATA6_IN_M \ 633 0xFFFFFFFF // data 634 635 #define SHAMD5_DATA6_IN_DATA6_IN_S 0 636 //****************************************************************************** 637 // 638 // The following are defines for the bit fields in the SHAMD5_O_DATA7_IN register. 639 // 640 //****************************************************************************** 641 #define SHAMD5_DATA7_IN_DATA7_IN_M \ 642 0xFFFFFFFF // data 643 644 #define SHAMD5_DATA7_IN_DATA7_IN_S 0 645 //****************************************************************************** 646 // 647 // The following are defines for the bit fields in the SHAMD5_O_DATA8_IN register. 648 // 649 //****************************************************************************** 650 #define SHAMD5_DATA8_IN_DATA8_IN_M \ 651 0xFFFFFFFF // data 652 653 #define SHAMD5_DATA8_IN_DATA8_IN_S 0 654 //****************************************************************************** 655 // 656 // The following are defines for the bit fields in the SHAMD5_O_DATA9_IN register. 657 // 658 //****************************************************************************** 659 #define SHAMD5_DATA9_IN_DATA9_IN_M \ 660 0xFFFFFFFF // data 661 662 #define SHAMD5_DATA9_IN_DATA9_IN_S 0 663 //****************************************************************************** 664 // 665 // The following are defines for the bit fields in the SHAMD5_O_DATA10_IN register. 666 // 667 //****************************************************************************** 668 #define SHAMD5_DATA10_IN_DATA10_IN_M \ 669 0xFFFFFFFF // data 670 671 #define SHAMD5_DATA10_IN_DATA10_IN_S 0 672 //****************************************************************************** 673 // 674 // The following are defines for the bit fields in the SHAMD5_O_DATA11_IN register. 675 // 676 //****************************************************************************** 677 #define SHAMD5_DATA11_IN_DATA11_IN_M \ 678 0xFFFFFFFF // data 679 680 #define SHAMD5_DATA11_IN_DATA11_IN_S 0 681 //****************************************************************************** 682 // 683 // The following are defines for the bit fields in the SHAMD5_O_DATA12_IN register. 684 // 685 //****************************************************************************** 686 #define SHAMD5_DATA12_IN_DATA12_IN_M \ 687 0xFFFFFFFF // data 688 689 #define SHAMD5_DATA12_IN_DATA12_IN_S 0 690 //****************************************************************************** 691 // 692 // The following are defines for the bit fields in the SHAMD5_O_DATA13_IN register. 693 // 694 //****************************************************************************** 695 #define SHAMD5_DATA13_IN_DATA13_IN_M \ 696 0xFFFFFFFF // data 697 698 #define SHAMD5_DATA13_IN_DATA13_IN_S 0 699 //****************************************************************************** 700 // 701 // The following are defines for the bit fields in the SHAMD5_O_DATA14_IN register. 702 // 703 //****************************************************************************** 704 #define SHAMD5_DATA14_IN_DATA14_IN_M \ 705 0xFFFFFFFF // data 706 707 #define SHAMD5_DATA14_IN_DATA14_IN_S 0 708 //****************************************************************************** 709 // 710 // The following are defines for the bit fields in the SHAMD5_O_DATA15_IN register. 711 // 712 //****************************************************************************** 713 #define SHAMD5_DATA15_IN_DATA15_IN_M \ 714 0xFFFFFFFF // data 715 716 #define SHAMD5_DATA15_IN_DATA15_IN_S 0 717 //****************************************************************************** 718 // 719 // The following are defines for the bit fields in the SHAMD5_O_REVISION register. 720 // 721 //****************************************************************************** 722 #define SHAMD5_REVISION_SCHEME_M 0xC0000000 723 #define SHAMD5_REVISION_SCHEME_S 30 724 #define SHAMD5_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software 725 // compatible module family. If 726 // there is no level of software 727 // compatibility a new Func number 728 // (and hence REVISION) should be 729 // assigned. 730 #define SHAMD5_REVISION_FUNC_S 16 731 #define SHAMD5_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP 732 // design owner. RTL follows a 733 // numbering such as X.Y.R.Z which 734 // are explained in this table. R 735 // changes ONLY when: (1) PDS 736 // uploads occur which may have been 737 // due to spec changes (2) Bug fixes 738 // occur (3) Resets to '0' when X or 739 // Y changes. Design team has an 740 // internal 'Z' (customer invisible) 741 // number which increments on every 742 // drop that happens due to DV and 743 // RTL updates. Z resets to 0 when R 744 // increments. 745 #define SHAMD5_REVISION_R_RTL_S 11 746 #define SHAMD5_REVISION_X_MAJOR_M \ 747 0x00000700 // Major Revision (X) maintained by 748 // IP specification owner. X changes 749 // ONLY when: (1) There is a major 750 // feature addition. An example 751 // would be adding Master Mode to 752 // Utopia Level2. The Func field (or 753 // Class/Type in old PID format) 754 // will remain the same. X does NOT 755 // change due to: (1) Bug fixes (2) 756 // Change in feature parameters. 757 758 #define SHAMD5_REVISION_X_MAJOR_S 8 759 #define SHAMD5_REVISION_CUSTOM_M 0x000000C0 760 #define SHAMD5_REVISION_CUSTOM_S 6 761 #define SHAMD5_REVISION_Y_MINOR_M \ 762 0x0000003F // Minor Revision (Y) maintained by 763 // IP specification owner. Y changes 764 // ONLY when: (1) Features are 765 // scaled (up or down). Flexibility 766 // exists in that this feature 767 // scalability may either be 768 // represented in the Y change or a 769 // specific register in the IP that 770 // indicates which features are 771 // exactly available. (2) When 772 // feature creeps from Is-Not list 773 // to Is list. But this may not be 774 // the case once it sees silicon; in 775 // which case X will change. Y does 776 // NOT change due to: (1) Bug fixes 777 // (2) Typos or clarifications (3) 778 // major functional/feature 779 // change/addition/deletion. Instead 780 // these changes may be reflected 781 // via R S X as applicable. Spec 782 // owner maintains a 783 // customer-invisible number 'S' 784 // which changes due to: (1) 785 // Typos/clarifications (2) Bug 786 // documentation. Note that this bug 787 // is not due to a spec change but 788 // due to implementation. 789 // Nevertheless the spec tracks the 790 // IP bugs. An RTL release (say for 791 // silicon PG1.1) that occurs due to 792 // bug fix should document the 793 // corresponding spec number (X.Y.S) 794 // in its release notes. 795 796 #define SHAMD5_REVISION_Y_MINOR_S 0 797 //****************************************************************************** 798 // 799 // The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG register. 800 // 801 //****************************************************************************** 802 #define SHAMD5_SYSCONFIG_PADVANCED \ 803 0x00000080 // If set to 1 Advanced mode is 804 // enabled for the Secure World. If 805 // set to 0 Legacy mode is enabled 806 // for the Secure World. 807 808 #define SHAMD5_SYSCONFIG_PCONT_SWT \ 809 0x00000040 // Finish all pending data and 810 // context DMA input requests (but 811 // will not assert any new requests) 812 // finish processing all data in the 813 // module and provide a saved 814 // context (partial hash result 815 // updated digest count remaining 816 // length updated mode information 817 // where applicable) for the last 818 // operation that was interrupted so 819 // that it can be resumed later. 820 821 #define SHAMD5_SYSCONFIG_PDMA_EN 0x00000008 822 #define SHAMD5_SYSCONFIG_PIT_EN 0x00000004 823 //****************************************************************************** 824 // 825 // The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS register. 826 // 827 //****************************************************************************** 828 #define SHAMD5_SYSSTATUS_RESETDONE \ 829 0x00000001 // data 830 831 //****************************************************************************** 832 // 833 // The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS register. 834 // 835 //****************************************************************************** 836 #define SHAMD5_IRQSTATUS_CONTEXT_READY \ 837 0x00000008 // indicates that the secure side 838 // context input registers are 839 // available for a new context for 840 // the next packet to be processed. 841 842 #define SHAMD5_IRQSTATUS_PARTHASH_READY \ 843 0x00000004 // After a secure side context 844 // switch request this bit will read 845 // as 1 indicating that the saved 846 // context is available from the 847 // secure side context output 848 // registers. Note that if the 849 // context switch request coincides 850 // with a final hash (when hashing) 851 // or an outer hash (when doing 852 // HMAC) that PartHashReady will not 853 // become active but a regular 854 // Output Ready will occur instead 855 // (indicating that the result is 856 // final and therefore no 857 // continuation is required). 858 859 #define SHAMD5_IRQSTATUS_INPUT_READY \ 860 0x00000002 // indicates that the secure side 861 // data FIFO is ready to receive the 862 // next 64 byte data block. 863 864 #define SHAMD5_IRQSTATUS_OUTPUT_READY \ 865 0x00000001 // Indicates that a (partial) 866 // result or saved context is 867 // available from the secure side 868 // context output registers. 869 870 //****************************************************************************** 871 // 872 // The following are defines for the bit fields in the SHAMD5_O_IRQENABLE register. 873 // 874 //****************************************************************************** 875 #define SHAMD5_IRQENABLE_M_CONTEXT_READY \ 876 0x00000008 // mask for context ready 877 878 #define SHAMD5_IRQENABLE_M_PARTHASH_READY \ 879 0x00000004 // mask for partial hash 880 881 #define SHAMD5_IRQENABLE_M_INPUT_READY \ 882 0x00000002 // mask for input_ready 883 884 #define SHAMD5_IRQENABLE_M_OUTPUT_READY \ 885 0x00000001 // mask for output_ready 886 887 //****************************************************************************** 888 // 889 // The following are defines for the bit fields in the 890 // SHAMD5_O_HASH512_ODIGEST_A register. 891 // 892 //****************************************************************************** 893 #define SHAMD5_HASH512_ODIGEST_A_DATA_M \ 894 0xFFFFFFFF 895 896 #define SHAMD5_HASH512_ODIGEST_A_DATA_S 0 897 //****************************************************************************** 898 // 899 // The following are defines for the bit fields in the 900 // SHAMD5_O_HASH512_ODIGEST_B register. 901 // 902 //****************************************************************************** 903 #define SHAMD5_HASH512_ODIGEST_B_DATA_M \ 904 0xFFFFFFFF 905 906 #define SHAMD5_HASH512_ODIGEST_B_DATA_S 0 907 //****************************************************************************** 908 // 909 // The following are defines for the bit fields in the 910 // SHAMD5_O_HASH512_ODIGEST_C register. 911 // 912 //****************************************************************************** 913 #define SHAMD5_HASH512_ODIGEST_C_DATA_M \ 914 0xFFFFFFFF 915 916 #define SHAMD5_HASH512_ODIGEST_C_DATA_S 0 917 //****************************************************************************** 918 // 919 // The following are defines for the bit fields in the 920 // SHAMD5_O_HASH512_ODIGEST_D register. 921 // 922 //****************************************************************************** 923 #define SHAMD5_HASH512_ODIGEST_D_DATA_M \ 924 0xFFFFFFFF 925 926 #define SHAMD5_HASH512_ODIGEST_D_DATA_S 0 927 //****************************************************************************** 928 // 929 // The following are defines for the bit fields in the 930 // SHAMD5_O_HASH512_ODIGEST_E register. 931 // 932 //****************************************************************************** 933 #define SHAMD5_HASH512_ODIGEST_E_DATA_M \ 934 0xFFFFFFFF 935 936 #define SHAMD5_HASH512_ODIGEST_E_DATA_S 0 937 //****************************************************************************** 938 // 939 // The following are defines for the bit fields in the 940 // SHAMD5_O_HASH512_ODIGEST_F register. 941 // 942 //****************************************************************************** 943 #define SHAMD5_HASH512_ODIGEST_F_DATA_M \ 944 0xFFFFFFFF 945 946 #define SHAMD5_HASH512_ODIGEST_F_DATA_S 0 947 //****************************************************************************** 948 // 949 // The following are defines for the bit fields in the 950 // SHAMD5_O_HASH512_ODIGEST_G register. 951 // 952 //****************************************************************************** 953 #define SHAMD5_HASH512_ODIGEST_G_DATA_M \ 954 0xFFFFFFFF 955 956 #define SHAMD5_HASH512_ODIGEST_G_DATA_S 0 957 //****************************************************************************** 958 // 959 // The following are defines for the bit fields in the 960 // SHAMD5_O_HASH512_ODIGEST_H register. 961 // 962 //****************************************************************************** 963 #define SHAMD5_HASH512_ODIGEST_H_DATA_M \ 964 0xFFFFFFFF 965 966 #define SHAMD5_HASH512_ODIGEST_H_DATA_S 0 967 //****************************************************************************** 968 // 969 // The following are defines for the bit fields in the 970 // SHAMD5_O_HASH512_ODIGEST_I register. 971 // 972 //****************************************************************************** 973 #define SHAMD5_HASH512_ODIGEST_I_DATA_M \ 974 0xFFFFFFFF 975 976 #define SHAMD5_HASH512_ODIGEST_I_DATA_S 0 977 //****************************************************************************** 978 // 979 // The following are defines for the bit fields in the 980 // SHAMD5_O_HASH512_ODIGEST_J register. 981 // 982 //****************************************************************************** 983 #define SHAMD5_HASH512_ODIGEST_J_DATA_M \ 984 0xFFFFFFFF 985 986 #define SHAMD5_HASH512_ODIGEST_J_DATA_S 0 987 //****************************************************************************** 988 // 989 // The following are defines for the bit fields in the 990 // SHAMD5_O_HASH512_ODIGEST_K register. 991 // 992 //****************************************************************************** 993 #define SHAMD5_HASH512_ODIGEST_K_DATA_M \ 994 0xFFFFFFFF 995 996 #define SHAMD5_HASH512_ODIGEST_K_DATA_S 0 997 //****************************************************************************** 998 // 999 // The following are defines for the bit fields in the 1000 // SHAMD5_O_HASH512_ODIGEST_L register. 1001 // 1002 //****************************************************************************** 1003 #define SHAMD5_HASH512_ODIGEST_L_DATA_M \ 1004 0xFFFFFFFF 1005 1006 #define SHAMD5_HASH512_ODIGEST_L_DATA_S 0 1007 //****************************************************************************** 1008 // 1009 // The following are defines for the bit fields in the 1010 // SHAMD5_O_HASH512_ODIGEST_M register. 1011 // 1012 //****************************************************************************** 1013 #define SHAMD5_HASH512_ODIGEST_M_DATA_M \ 1014 0xFFFFFFFF 1015 1016 #define SHAMD5_HASH512_ODIGEST_M_DATA_S 0 1017 //****************************************************************************** 1018 // 1019 // The following are defines for the bit fields in the 1020 // SHAMD5_O_HASH512_ODIGEST_N register. 1021 // 1022 //****************************************************************************** 1023 #define SHAMD5_HASH512_ODIGEST_N_DATA_M \ 1024 0xFFFFFFFF 1025 1026 #define SHAMD5_HASH512_ODIGEST_N_DATA_S 0 1027 //****************************************************************************** 1028 // 1029 // The following are defines for the bit fields in the 1030 // SHAMD5_O_HASH512_ODIGEST_O register. 1031 // 1032 //****************************************************************************** 1033 #define SHAMD5_HASH512_ODIGEST_O_DATA_M \ 1034 0xFFFFFFFF 1035 1036 #define SHAMD5_HASH512_ODIGEST_O_DATA_S 0 1037 //****************************************************************************** 1038 // 1039 // The following are defines for the bit fields in the 1040 // SHAMD5_O_HASH512_ODIGEST_P register. 1041 // 1042 //****************************************************************************** 1043 #define SHAMD5_HASH512_ODIGEST_DATA_M \ 1044 0xFFFFFFFF 1045 1046 #define SHAMD5_HASH512_ODIGEST_DATA_S 0 1047 //****************************************************************************** 1048 // 1049 // The following are defines for the bit fields in the 1050 // SHAMD5_O_HASH512_IDIGEST_A register. 1051 // 1052 //****************************************************************************** 1053 #define SHAMD5_HASH512_IDIGEST_A_DATA_M \ 1054 0xFFFFFFFF 1055 1056 #define SHAMD5_HASH512_IDIGEST_A_DATA_S 0 1057 //****************************************************************************** 1058 // 1059 // The following are defines for the bit fields in the 1060 // SHAMD5_O_HASH512_IDIGEST_B register. 1061 // 1062 //****************************************************************************** 1063 #define SHAMD5_HASH512_IDIGEST_B_DATA_M \ 1064 0xFFFFFFFF 1065 1066 #define SHAMD5_HASH512_IDIGEST_B_DATA_S 0 1067 //****************************************************************************** 1068 // 1069 // The following are defines for the bit fields in the 1070 // SHAMD5_O_HASH512_IDIGEST_C register. 1071 // 1072 //****************************************************************************** 1073 #define SHAMD5_HASH512_IDIGEST_C_DATA_M \ 1074 0xFFFFFFFF 1075 1076 #define SHAMD5_HASH512_IDIGEST_C_DATA_S 0 1077 //****************************************************************************** 1078 // 1079 // The following are defines for the bit fields in the 1080 // SHAMD5_O_HASH512_IDIGEST_D register. 1081 // 1082 //****************************************************************************** 1083 #define SHAMD5_HASH512_IDIGEST_D_DATA_M \ 1084 0xFFFFFFFF 1085 1086 #define SHAMD5_HASH512_IDIGEST_D_DATA_S 0 1087 //****************************************************************************** 1088 // 1089 // The following are defines for the bit fields in the 1090 // SHAMD5_O_HASH512_IDIGEST_E register. 1091 // 1092 //****************************************************************************** 1093 #define SHAMD5_HASH512_IDIGEST_E_DATA_M \ 1094 0xFFFFFFFF 1095 1096 #define SHAMD5_HASH512_IDIGEST_E_DATA_S 0 1097 //****************************************************************************** 1098 // 1099 // The following are defines for the bit fields in the 1100 // SHAMD5_O_HASH512_IDIGEST_F register. 1101 // 1102 //****************************************************************************** 1103 #define SHAMD5_HASH512_IDIGEST_F_DATA_M \ 1104 0xFFFFFFFF 1105 1106 #define SHAMD5_HASH512_IDIGEST_F_DATA_S 0 1107 //****************************************************************************** 1108 // 1109 // The following are defines for the bit fields in the 1110 // SHAMD5_O_HASH512_IDIGEST_G register. 1111 // 1112 //****************************************************************************** 1113 #define SHAMD5_HASH512_IDIGEST_G_DATA_M \ 1114 0xFFFFFFFF 1115 1116 #define SHAMD5_HASH512_IDIGEST_G_DATA_S 0 1117 //****************************************************************************** 1118 // 1119 // The following are defines for the bit fields in the 1120 // SHAMD5_O_HASH512_IDIGEST_H register. 1121 // 1122 //****************************************************************************** 1123 #define SHAMD5_HASH512_IDIGEST_H_DATA_M \ 1124 0xFFFFFFFF 1125 1126 #define SHAMD5_HASH512_IDIGEST_H_DATA_S 0 1127 //****************************************************************************** 1128 // 1129 // The following are defines for the bit fields in the 1130 // SHAMD5_O_HASH512_IDIGEST_I register. 1131 // 1132 //****************************************************************************** 1133 #define SHAMD5_HASH512_IDIGEST_I_DATA_M \ 1134 0xFFFFFFFF 1135 1136 #define SHAMD5_HASH512_IDIGEST_I_DATA_S 0 1137 //****************************************************************************** 1138 // 1139 // The following are defines for the bit fields in the 1140 // SHAMD5_O_HASH512_IDIGEST_J register. 1141 // 1142 //****************************************************************************** 1143 #define SHAMD5_HASH512_IDIGEST_J_DATA_M \ 1144 0xFFFFFFFF 1145 1146 #define SHAMD5_HASH512_IDIGEST_J_DATA_S 0 1147 //****************************************************************************** 1148 // 1149 // The following are defines for the bit fields in the 1150 // SHAMD5_O_HASH512_IDIGEST_K register. 1151 // 1152 //****************************************************************************** 1153 #define SHAMD5_HASH512_IDIGEST_K_DATA_M \ 1154 0xFFFFFFFF 1155 1156 #define SHAMD5_HASH512_IDIGEST_K_DATA_S 0 1157 //****************************************************************************** 1158 // 1159 // The following are defines for the bit fields in the 1160 // SHAMD5_O_HASH512_IDIGEST_L register. 1161 // 1162 //****************************************************************************** 1163 #define SHAMD5_HASH512_IDIGEST_L_DATA_M \ 1164 0xFFFFFFFF 1165 1166 #define SHAMD5_HASH512_IDIGEST_L_DATA_S 0 1167 //****************************************************************************** 1168 // 1169 // The following are defines for the bit fields in the 1170 // SHAMD5_O_HASH512_IDIGEST_M register. 1171 // 1172 //****************************************************************************** 1173 #define SHAMD5_HASH512_IDIGEST_M_DATA_M \ 1174 0xFFFFFFFF 1175 1176 #define SHAMD5_HASH512_IDIGEST_M_DATA_S 0 1177 //****************************************************************************** 1178 // 1179 // The following are defines for the bit fields in the 1180 // SHAMD5_O_HASH512_IDIGEST_N register. 1181 // 1182 //****************************************************************************** 1183 #define SHAMD5_HASH512_IDIGEST_N_DATA_M \ 1184 0xFFFFFFFF 1185 1186 #define SHAMD5_HASH512_IDIGEST_N_DATA_S 0 1187 //****************************************************************************** 1188 // 1189 // The following are defines for the bit fields in the 1190 // SHAMD5_O_HASH512_IDIGEST_O register. 1191 // 1192 //****************************************************************************** 1193 #define SHAMD5_HASH512_IDIGEST_O_DATA_M \ 1194 0xFFFFFFFF 1195 1196 #define SHAMD5_HASH512_IDIGEST_O_DATA_S 0 1197 //****************************************************************************** 1198 // 1199 // The following are defines for the bit fields in the 1200 // SHAMD5_O_HASH512_IDIGEST_P register. 1201 // 1202 //****************************************************************************** 1203 #define SHAMD5_HASH512_IDIGEST_DATA_M \ 1204 0xFFFFFFFF 1205 1206 #define SHAMD5_HASH512_IDIGEST_DATA_S 0 1207 //****************************************************************************** 1208 // 1209 // The following are defines for the bit fields in the 1210 // SHAMD5_O_HASH512_DIGEST_COUNT register. 1211 // 1212 //****************************************************************************** 1213 #define SHAMD5_HASH512_DIGEST_COUNT_DATA_M \ 1214 0xFFFFFFFF 1215 1216 #define SHAMD5_HASH512_DIGEST_COUNT_DATA_S 0 1217 //****************************************************************************** 1218 // 1219 // The following are defines for the bit fields in the 1220 // SHAMD5_O_HASH512_MODE register. 1221 // 1222 //****************************************************************************** 1223 #define SHAMD5_HASH512_MODE_DATA_M \ 1224 0xFFFFFFFF 1225 1226 #define SHAMD5_HASH512_MODE_DATA_S 0 1227 //****************************************************************************** 1228 // 1229 // The following are defines for the bit fields in the 1230 // SHAMD5_O_HASH512_LENGTH register. 1231 // 1232 //****************************************************************************** 1233 #define SHAMD5_HASH512_LENGTH_DATA_M \ 1234 0xFFFFFFFF 1235 1236 #define SHAMD5_HASH512_LENGTH_DATA_S 0 1237 1238 1239 1240 #endif // __HW_SHAMD5_H__ 1241
