1 /****************************************************************************** 2 * Filename: hw_rfc_dbell_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_RFC_DBELL_H__ 38 #define __HW_RFC_DBELL_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // RFC_DBELL component 44 // 45 //***************************************************************************** 46 // Doorbell Command Register 47 #define RFC_DBELL_O_CMDR 0x00000000 48 49 // Doorbell Command Status Register 50 #define RFC_DBELL_O_CMDSTA 0x00000004 51 52 // Interrupt Flags From RF Hardware Modules 53 #define RFC_DBELL_O_RFHWIFG 0x00000008 54 55 // Interrupt Enable For RF Hardware Modules 56 #define RFC_DBELL_O_RFHWIEN 0x0000000C 57 58 // Interrupt Flags For Command and Packet Engine Generated Interrupts 59 #define RFC_DBELL_O_RFCPEIFG 0x00000010 60 61 // Interrupt Enable For Command and Packet Engine Generated Interrupts 62 #define RFC_DBELL_O_RFCPEIEN 0x00000014 63 64 // Interrupt Vector Selection For Command and Packet Engine Generated 65 // Interrupts 66 #define RFC_DBELL_O_RFCPEISL 0x00000018 67 68 // Doorbell Command Acknowledgement Interrupt Flag 69 #define RFC_DBELL_O_RFACKIFG 0x0000001C 70 71 // RF Core General Purpose Output Control 72 #define RFC_DBELL_O_SYSGPOCTL 0x00000020 73 74 //***************************************************************************** 75 // 76 // Register: RFC_DBELL_O_CMDR 77 // 78 //***************************************************************************** 79 // Field: [31:0] CMD 80 // 81 // Command register. Raises an interrupt to the Command and packet engine (CPE) 82 // upon write. 83 #define RFC_DBELL_CMDR_CMD_W 32 84 #define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF 85 #define RFC_DBELL_CMDR_CMD_S 0 86 87 //***************************************************************************** 88 // 89 // Register: RFC_DBELL_O_CMDSTA 90 // 91 //***************************************************************************** 92 // Field: [31:0] STAT 93 // 94 // Status of the last command used 95 #define RFC_DBELL_CMDSTA_STAT_W 32 96 #define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF 97 #define RFC_DBELL_CMDSTA_STAT_S 0 98 99 //***************************************************************************** 100 // 101 // Register: RFC_DBELL_O_RFHWIFG 102 // 103 //***************************************************************************** 104 // Field: [19] RATCH7 105 // 106 // Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one 107 // has no effect. 108 #define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 109 #define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 110 #define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 111 #define RFC_DBELL_RFHWIFG_RATCH7_S 19 112 113 // Field: [18] RATCH6 114 // 115 // Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one 116 // has no effect. 117 #define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 118 #define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 119 #define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 120 #define RFC_DBELL_RFHWIFG_RATCH6_S 18 121 122 // Field: [17] RATCH5 123 // 124 // Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one 125 // has no effect. 126 #define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 127 #define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 128 #define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 129 #define RFC_DBELL_RFHWIFG_RATCH5_S 17 130 131 // Field: [16] RATCH4 132 // 133 // Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one 134 // has no effect. 135 #define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 136 #define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 137 #define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 138 #define RFC_DBELL_RFHWIFG_RATCH4_S 16 139 140 // Field: [15] RATCH3 141 // 142 // Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one 143 // has no effect. 144 #define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 145 #define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 146 #define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 147 #define RFC_DBELL_RFHWIFG_RATCH3_S 15 148 149 // Field: [14] RATCH2 150 // 151 // Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one 152 // has no effect. 153 #define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 154 #define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 155 #define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 156 #define RFC_DBELL_RFHWIFG_RATCH2_S 14 157 158 // Field: [13] RATCH1 159 // 160 // Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one 161 // has no effect. 162 #define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 163 #define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 164 #define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 165 #define RFC_DBELL_RFHWIFG_RATCH1_S 13 166 167 // Field: [12] RATCH0 168 // 169 // Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one 170 // has no effect. 171 #define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 172 #define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 173 #define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 174 #define RFC_DBELL_RFHWIFG_RATCH0_S 12 175 176 // Field: [11] RFESOFT2 177 // 178 // RF engine software defined interrupt 2 flag. Write zero to clear flag. Write 179 // to one has no effect. 180 #define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 181 #define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 182 #define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 183 #define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 184 185 // Field: [10] RFESOFT1 186 // 187 // RF engine software defined interrupt 1 flag. Write zero to clear flag. Write 188 // to one has no effect. 189 #define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 190 #define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 191 #define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 192 #define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 193 194 // Field: [9] RFESOFT0 195 // 196 // RF engine software defined interrupt 0 flag. Write zero to clear flag. Write 197 // to one has no effect. 198 #define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 199 #define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 200 #define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 201 #define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 202 203 // Field: [8] RFEDONE 204 // 205 // RF engine command done interrupt flag. Write zero to clear flag. Write to 206 // one has no effect. 207 #define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 208 #define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 209 #define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 210 #define RFC_DBELL_RFHWIFG_RFEDONE_S 8 211 212 // Field: [6] TRCTK 213 // 214 // Debug tracer system tick interrupt flag. Write zero to clear flag. Write to 215 // one has no effect. 216 #define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 217 #define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 218 #define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 219 #define RFC_DBELL_RFHWIFG_TRCTK_S 6 220 221 // Field: [5] MDMSOFT 222 // 223 // Modem software defined interrupt flag. Write zero to clear flag. Write to 224 // one has no effect. 225 #define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 226 #define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 227 #define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 228 #define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 229 230 // Field: [4] MDMOUT 231 // 232 // Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has 233 // no effect. 234 #define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 235 #define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 236 #define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 237 #define RFC_DBELL_RFHWIFG_MDMOUT_S 4 238 239 // Field: [3] MDMIN 240 // 241 // Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has 242 // no effect. 243 #define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 244 #define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 245 #define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 246 #define RFC_DBELL_RFHWIFG_MDMIN_S 3 247 248 // Field: [2] MDMDONE 249 // 250 // Modem command done interrupt flag. Write zero to clear flag. Write to one 251 // has no effect. 252 #define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 253 #define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 254 #define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 255 #define RFC_DBELL_RFHWIFG_MDMDONE_S 2 256 257 // Field: [1] FSCA 258 // 259 // Frequency synthesizer calibration accelerator interrupt flag. Write zero to 260 // clear flag. Write to one has no effect. 261 #define RFC_DBELL_RFHWIFG_FSCA 0x00000002 262 #define RFC_DBELL_RFHWIFG_FSCA_BITN 1 263 #define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 264 #define RFC_DBELL_RFHWIFG_FSCA_S 1 265 266 //***************************************************************************** 267 // 268 // Register: RFC_DBELL_O_RFHWIEN 269 // 270 //***************************************************************************** 271 // Field: [19] RATCH7 272 // 273 // Interrupt enable for RFHWIFG.RATCH7. 274 #define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 275 #define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 276 #define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 277 #define RFC_DBELL_RFHWIEN_RATCH7_S 19 278 279 // Field: [18] RATCH6 280 // 281 // Interrupt enable for RFHWIFG.RATCH6. 282 #define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 283 #define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 284 #define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 285 #define RFC_DBELL_RFHWIEN_RATCH6_S 18 286 287 // Field: [17] RATCH5 288 // 289 // Interrupt enable for RFHWIFG.RATCH5. 290 #define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 291 #define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 292 #define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 293 #define RFC_DBELL_RFHWIEN_RATCH5_S 17 294 295 // Field: [16] RATCH4 296 // 297 // Interrupt enable for RFHWIFG.RATCH4. 298 #define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 299 #define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 300 #define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 301 #define RFC_DBELL_RFHWIEN_RATCH4_S 16 302 303 // Field: [15] RATCH3 304 // 305 // Interrupt enable for RFHWIFG.RATCH3. 306 #define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 307 #define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 308 #define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 309 #define RFC_DBELL_RFHWIEN_RATCH3_S 15 310 311 // Field: [14] RATCH2 312 // 313 // Interrupt enable for RFHWIFG.RATCH2. 314 #define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 315 #define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 316 #define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 317 #define RFC_DBELL_RFHWIEN_RATCH2_S 14 318 319 // Field: [13] RATCH1 320 // 321 // Interrupt enable for RFHWIFG.RATCH1. 322 #define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 323 #define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 324 #define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 325 #define RFC_DBELL_RFHWIEN_RATCH1_S 13 326 327 // Field: [12] RATCH0 328 // 329 // Interrupt enable for RFHWIFG.RATCH0. 330 #define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 331 #define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 332 #define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 333 #define RFC_DBELL_RFHWIEN_RATCH0_S 12 334 335 // Field: [11] RFESOFT2 336 // 337 // Interrupt enable for RFHWIFG.RFESOFT2. 338 #define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 339 #define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 340 #define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 341 #define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 342 343 // Field: [10] RFESOFT1 344 // 345 // Interrupt enable for RFHWIFG.RFESOFT1. 346 #define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 347 #define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 348 #define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 349 #define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 350 351 // Field: [9] RFESOFT0 352 // 353 // Interrupt enable for RFHWIFG.RFESOFT0. 354 #define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 355 #define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 356 #define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 357 #define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 358 359 // Field: [8] RFEDONE 360 // 361 // Interrupt enable for RFHWIFG.RFEDONE. 362 #define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 363 #define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 364 #define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 365 #define RFC_DBELL_RFHWIEN_RFEDONE_S 8 366 367 // Field: [6] TRCTK 368 // 369 // Interrupt enable for RFHWIFG.TRCTK. 370 #define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 371 #define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 372 #define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 373 #define RFC_DBELL_RFHWIEN_TRCTK_S 6 374 375 // Field: [5] MDMSOFT 376 // 377 // Interrupt enable for RFHWIFG.MDMSOFT. 378 #define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 379 #define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 380 #define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 381 #define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 382 383 // Field: [4] MDMOUT 384 // 385 // Interrupt enable for RFHWIFG.MDMOUT. 386 #define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 387 #define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 388 #define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 389 #define RFC_DBELL_RFHWIEN_MDMOUT_S 4 390 391 // Field: [3] MDMIN 392 // 393 // Interrupt enable for RFHWIFG.MDMIN. 394 #define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 395 #define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 396 #define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 397 #define RFC_DBELL_RFHWIEN_MDMIN_S 3 398 399 // Field: [2] MDMDONE 400 // 401 // Interrupt enable for RFHWIFG.MDMDONE. 402 #define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 403 #define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 404 #define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 405 #define RFC_DBELL_RFHWIEN_MDMDONE_S 2 406 407 // Field: [1] FSCA 408 // 409 // Interrupt enable for RFHWIFG.FSCA. 410 #define RFC_DBELL_RFHWIEN_FSCA 0x00000002 411 #define RFC_DBELL_RFHWIEN_FSCA_BITN 1 412 #define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 413 #define RFC_DBELL_RFHWIEN_FSCA_S 1 414 415 //***************************************************************************** 416 // 417 // Register: RFC_DBELL_O_RFCPEIFG 418 // 419 //***************************************************************************** 420 // Field: [31] INTERNAL_ERROR 421 // 422 // Interrupt flag 31. The command and packet engine (CPE) has observed an 423 // unexpected error. A reset of the CPE is needed. This can be done by 424 // switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero 425 // to clear flag. Write to one has no effect. 426 #define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 427 #define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 428 #define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 429 #define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 430 431 // Field: [30] BOOT_DONE 432 // 433 // Interrupt flag 30. The command and packet engine (CPE) boot is finished. 434 // Write zero to clear flag. Write to one has no effect. 435 #define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 436 #define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 437 #define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 438 #define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 439 440 // Field: [29] MODULES_UNLOCKED 441 // 442 // Interrupt flag 29. As part of command and packet engine (CPE) boot process, 443 // it has opened access to RF Core modules and memories. Write zero to clear 444 // flag. Write to one has no effect. 445 #define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 446 #define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 447 #define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 448 #define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 449 450 // Field: [28] SYNTH_NO_LOCK 451 // 452 // Interrupt flag 28. The phase-locked loop in frequency synthesizer has 453 // reported loss of lock. Write zero to clear flag. Write to one has no effect. 454 #define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 455 #define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 456 #define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 457 #define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 458 459 // Field: [27] IRQ27 460 // 461 // Interrupt flag 27. Write zero to clear flag. Write to one has no effect. 462 #define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 463 #define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 464 #define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 465 #define RFC_DBELL_RFCPEIFG_IRQ27_S 27 466 467 // Field: [26] RX_ABORTED 468 // 469 // Interrupt flag 26. Packet reception stopped before packet was done. Write 470 // zero to clear flag. Write to one has no effect. 471 #define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 472 #define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 473 #define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 474 #define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 475 476 // Field: [25] RX_N_DATA_WRITTEN 477 // 478 // Interrupt flag 25. Specified number of bytes written to partial read Rx 479 // buffer. Write zero to clear flag. Write to one has no effect. 480 #define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 481 #define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 482 #define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 483 #define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 484 485 // Field: [24] RX_DATA_WRITTEN 486 // 487 // Interrupt flag 24. Data written to partial read Rx buffer. Write zero to 488 // clear flag. Write to one has no effect. 489 #define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 490 #define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 491 #define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 492 #define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 493 494 // Field: [23] RX_ENTRY_DONE 495 // 496 // Interrupt flag 23. Rx queue data entry changing state to finished. Write 497 // zero to clear flag. Write to one has no effect. 498 #define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 499 #define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 500 #define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 501 #define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 502 503 // Field: [22] RX_BUF_FULL 504 // 505 // Interrupt flag 22. Packet received that did not fit in Rx queue. BLE mode: 506 // Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame 507 // received that did not fit in the Rx queue. Write zero to clear flag. Write 508 // to one has no effect. 509 #define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 510 #define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 511 #define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 512 #define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 513 514 // Field: [21] RX_CTRL_ACK 515 // 516 // Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, 517 // not to be ignored, then acknowledgement sent. Write zero to clear flag. 518 // Write to one has no effect. 519 #define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 520 #define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 521 #define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 522 #define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 523 524 // Field: [20] RX_CTRL 525 // 526 // Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, 527 // not to be ignored. Write zero to clear flag. Write to one has no effect. 528 #define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 529 #define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 530 #define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 531 #define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 532 533 // Field: [19] RX_EMPTY 534 // 535 // Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be 536 // ignored, no payload. Write zero to clear flag. Write to one has no effect. 537 #define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 538 #define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 539 #define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 540 #define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 541 542 // Field: [18] RX_IGNORED 543 // 544 // Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet 545 // received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received 546 // with ignore flag set. Write zero to clear flag. Write to one has no effect. 547 #define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 548 #define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 549 #define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 550 #define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 551 552 // Field: [17] RX_NOK 553 // 554 // Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received 555 // with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write 556 // zero to clear flag. Write to one has no effect. 557 #define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 558 #define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 559 #define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 560 #define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 561 562 // Field: [16] RX_OK 563 // 564 // Interrupt flag 16. Packet received correctly. BLE mode: Packet received with 565 // CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received 566 // with CRC OK. Write zero to clear flag. Write to one has no effect. 567 #define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 568 #define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 569 #define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 570 #define RFC_DBELL_RFCPEIFG_RX_OK_S 16 571 572 // Field: [15] IRQ15 573 // 574 // Interrupt flag 15. Write zero to clear flag. Write to one has no effect. 575 #define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 576 #define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 577 #define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 578 #define RFC_DBELL_RFCPEIFG_IRQ15_S 15 579 580 // Field: [14] IRQ14 581 // 582 // Interrupt flag 14. Write zero to clear flag. Write to one has no effect. 583 #define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 584 #define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 585 #define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 586 #define RFC_DBELL_RFCPEIFG_IRQ14_S 14 587 588 // Field: [13] FG_COMMAND_STARTED 589 // 590 // Interrupt flag 13. IEEE 802.15.4 mode only: A foreground radio operation 591 // command has gone into active state. 592 #define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED 0x00002000 593 #define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_BITN 13 594 #define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_M 0x00002000 595 #define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_S 13 596 597 // Field: [12] COMMAND_STARTED 598 // 599 // Interrupt flag 12. A radio operation command has gone into active state. 600 #define RFC_DBELL_RFCPEIFG_COMMAND_STARTED 0x00001000 601 #define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_BITN 12 602 #define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_M 0x00001000 603 #define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_S 12 604 605 // Field: [11] TX_BUFFER_CHANGED 606 // 607 // Interrupt flag 11. BLE mode only: A buffer change is complete after 608 // CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. 609 #define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 610 #define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 611 #define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 612 #define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 613 614 // Field: [10] TX_ENTRY_DONE 615 // 616 // Interrupt flag 10. Tx queue data entry state changed to finished. Write zero 617 // to clear flag. Write to one has no effect. 618 #define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 619 #define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 620 #define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 621 #define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 622 623 // Field: [9] TX_RETRANS 624 // 625 // Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear 626 // flag. Write to one has no effect. 627 #define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 628 #define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 629 #define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 630 #define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 631 632 // Field: [8] TX_CTRL_ACK_ACK 633 // 634 // Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted 635 // LL control packet, and acknowledgement transmitted for that packet. Write 636 // zero to clear flag. Write to one has no effect. 637 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 638 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 639 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 640 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 641 642 // Field: [7] TX_CTRL_ACK 643 // 644 // Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL 645 // control packet. Write zero to clear flag. Write to one has no effect. 646 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 647 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 648 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 649 #define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 650 651 // Field: [6] TX_CTRL 652 // 653 // Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to 654 // clear flag. Write to one has no effect. 655 #define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 656 #define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 657 #define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 658 #define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 659 660 // Field: [5] TX_ACK 661 // 662 // Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted 663 // packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to 664 // clear flag. Write to one has no effect. 665 #define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 666 #define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 667 #define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 668 #define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 669 670 // Field: [4] TX_DONE 671 // 672 // Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been 673 // transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero 674 // to clear flag. Write to one has no effect. 675 #define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 676 #define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 677 #define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 678 #define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 679 680 // Field: [3] LAST_FG_COMMAND_DONE 681 // 682 // Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio 683 // operation command in a chain of commands has finished. Write zero to clear 684 // flag. Write to one has no effect. 685 #define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 686 #define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 687 #define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 688 #define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 689 690 // Field: [2] FG_COMMAND_DONE 691 // 692 // Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation 693 // command has finished. Write zero to clear flag. Write to one has no effect. 694 #define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 695 #define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 696 #define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 697 #define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 698 699 // Field: [1] LAST_COMMAND_DONE 700 // 701 // Interrupt flag 1. The last radio operation command in a chain of commands 702 // has finished. (IEEE 802.15.4 mode: The last background level radio operation 703 // command in a chain of commands has finished.) Write zero to clear flag. 704 // Write to one has no effect. 705 #define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 706 #define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 707 #define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 708 #define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 709 710 // Field: [0] COMMAND_DONE 711 // 712 // Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A 713 // background level radio operation command has finished.) Write zero to clear 714 // flag. Write to one has no effect. 715 #define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 716 #define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 717 #define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 718 #define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 719 720 //***************************************************************************** 721 // 722 // Register: RFC_DBELL_O_RFCPEIEN 723 // 724 //***************************************************************************** 725 // Field: [31] INTERNAL_ERROR 726 // 727 // Interrupt enable for RFCPEIFG.INTERNAL_ERROR. 728 #define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 729 #define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 730 #define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 731 #define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 732 733 // Field: [30] BOOT_DONE 734 // 735 // Interrupt enable for RFCPEIFG.BOOT_DONE. 736 #define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 737 #define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 738 #define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 739 #define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 740 741 // Field: [29] MODULES_UNLOCKED 742 // 743 // Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. 744 #define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 745 #define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 746 #define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 747 #define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 748 749 // Field: [28] SYNTH_NO_LOCK 750 // 751 // Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. 752 #define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 753 #define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 754 #define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 755 #define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 756 757 // Field: [27] IRQ27 758 // 759 // Interrupt enable for RFCPEIFG.IRQ27. 760 #define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 761 #define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 762 #define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 763 #define RFC_DBELL_RFCPEIEN_IRQ27_S 27 764 765 // Field: [26] RX_ABORTED 766 // 767 // Interrupt enable for RFCPEIFG.RX_ABORTED. 768 #define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 769 #define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 770 #define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 771 #define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 772 773 // Field: [25] RX_N_DATA_WRITTEN 774 // 775 // Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. 776 #define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 777 #define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 778 #define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 779 #define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 780 781 // Field: [24] RX_DATA_WRITTEN 782 // 783 // Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. 784 #define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 785 #define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 786 #define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 787 #define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 788 789 // Field: [23] RX_ENTRY_DONE 790 // 791 // Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. 792 #define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 793 #define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 794 #define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 795 #define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 796 797 // Field: [22] RX_BUF_FULL 798 // 799 // Interrupt enable for RFCPEIFG.RX_BUF_FULL. 800 #define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 801 #define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 802 #define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 803 #define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 804 805 // Field: [21] RX_CTRL_ACK 806 // 807 // Interrupt enable for RFCPEIFG.RX_CTRL_ACK. 808 #define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 809 #define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 810 #define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 811 #define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 812 813 // Field: [20] RX_CTRL 814 // 815 // Interrupt enable for RFCPEIFG.RX_CTRL. 816 #define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 817 #define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 818 #define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 819 #define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 820 821 // Field: [19] RX_EMPTY 822 // 823 // Interrupt enable for RFCPEIFG.RX_EMPTY. 824 #define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 825 #define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 826 #define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 827 #define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 828 829 // Field: [18] RX_IGNORED 830 // 831 // Interrupt enable for RFCPEIFG.RX_IGNORED. 832 #define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 833 #define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 834 #define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 835 #define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 836 837 // Field: [17] RX_NOK 838 // 839 // Interrupt enable for RFCPEIFG.RX_NOK. 840 #define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 841 #define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 842 #define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 843 #define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 844 845 // Field: [16] RX_OK 846 // 847 // Interrupt enable for RFCPEIFG.RX_OK. 848 #define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 849 #define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 850 #define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 851 #define RFC_DBELL_RFCPEIEN_RX_OK_S 16 852 853 // Field: [15] IRQ15 854 // 855 // Interrupt enable for RFCPEIFG.IRQ15. 856 #define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 857 #define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 858 #define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 859 #define RFC_DBELL_RFCPEIEN_IRQ15_S 15 860 861 // Field: [14] IRQ14 862 // 863 // Interrupt enable for RFCPEIFG.IRQ14. 864 #define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 865 #define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 866 #define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 867 #define RFC_DBELL_RFCPEIEN_IRQ14_S 14 868 869 // Field: [13] FG_COMMAND_STARTED 870 // 871 // Interrupt enable for RFCPEIFG.FG_COMMAND_STARTED. 872 #define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED 0x00002000 873 #define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_BITN 13 874 #define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_M 0x00002000 875 #define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_S 13 876 877 // Field: [12] COMMAND_STARTED 878 // 879 // Interrupt enable for RFCPEIFG.COMMAND_STARTED. 880 #define RFC_DBELL_RFCPEIEN_COMMAND_STARTED 0x00001000 881 #define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_BITN 12 882 #define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_M 0x00001000 883 #define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_S 12 884 885 // Field: [11] TX_BUFFER_CHANGED 886 // 887 // Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. 888 #define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 889 #define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 890 #define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 891 #define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 892 893 // Field: [10] TX_ENTRY_DONE 894 // 895 // Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. 896 #define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 897 #define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 898 #define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 899 #define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 900 901 // Field: [9] TX_RETRANS 902 // 903 // Interrupt enable for RFCPEIFG.TX_RETRANS. 904 #define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 905 #define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 906 #define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 907 #define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 908 909 // Field: [8] TX_CTRL_ACK_ACK 910 // 911 // Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. 912 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 913 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 914 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 915 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 916 917 // Field: [7] TX_CTRL_ACK 918 // 919 // Interrupt enable for RFCPEIFG.TX_CTRL_ACK. 920 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 921 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 922 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 923 #define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 924 925 // Field: [6] TX_CTRL 926 // 927 // Interrupt enable for RFCPEIFG.TX_CTRL. 928 #define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 929 #define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 930 #define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 931 #define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 932 933 // Field: [5] TX_ACK 934 // 935 // Interrupt enable for RFCPEIFG.TX_ACK. 936 #define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 937 #define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 938 #define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 939 #define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 940 941 // Field: [4] TX_DONE 942 // 943 // Interrupt enable for RFCPEIFG.TX_DONE. 944 #define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 945 #define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 946 #define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 947 #define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 948 949 // Field: [3] LAST_FG_COMMAND_DONE 950 // 951 // Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. 952 #define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 953 #define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 954 #define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 955 #define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 956 957 // Field: [2] FG_COMMAND_DONE 958 // 959 // Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. 960 #define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 961 #define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 962 #define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 963 #define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 964 965 // Field: [1] LAST_COMMAND_DONE 966 // 967 // Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. 968 #define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 969 #define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 970 #define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 971 #define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 972 973 // Field: [0] COMMAND_DONE 974 // 975 // Interrupt enable for RFCPEIFG.COMMAND_DONE. 976 #define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 977 #define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 978 #define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 979 #define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 980 981 //***************************************************************************** 982 // 983 // Register: RFC_DBELL_O_RFCPEISL 984 // 985 //***************************************************************************** 986 // Field: [31] INTERNAL_ERROR 987 // 988 // Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt 989 // should use. 990 // ENUMs: 991 // CPE1 Associate this interrupt line with INT_RF_CPE1 992 // interrupt vector 993 // CPE0 Associate this interrupt line with INT_RF_CPE0 994 // interrupt vector 995 #define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 996 #define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 997 #define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 998 #define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 999 #define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 1000 #define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 1001 1002 // Field: [30] BOOT_DONE 1003 // 1004 // Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should 1005 // use. 1006 // ENUMs: 1007 // CPE1 Associate this interrupt line with INT_RF_CPE1 1008 // interrupt vector 1009 // CPE0 Associate this interrupt line with INT_RF_CPE0 1010 // interrupt vector 1011 #define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 1012 #define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 1013 #define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 1014 #define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 1015 #define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 1016 #define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 1017 1018 // Field: [29] MODULES_UNLOCKED 1019 // 1020 // Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt 1021 // should use. 1022 // ENUMs: 1023 // CPE1 Associate this interrupt line with INT_RF_CPE1 1024 // interrupt vector 1025 // CPE0 Associate this interrupt line with INT_RF_CPE0 1026 // interrupt vector 1027 #define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 1028 #define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 1029 #define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 1030 #define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 1031 #define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 1032 #define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 1033 1034 // Field: [28] SYNTH_NO_LOCK 1035 // 1036 // Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt 1037 // should use. 1038 // ENUMs: 1039 // CPE1 Associate this interrupt line with INT_RF_CPE1 1040 // interrupt vector 1041 // CPE0 Associate this interrupt line with INT_RF_CPE0 1042 // interrupt vector 1043 #define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 1044 #define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 1045 #define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 1046 #define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 1047 #define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 1048 #define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 1049 1050 // Field: [27] IRQ27 1051 // 1052 // Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use. 1053 // ENUMs: 1054 // CPE1 Associate this interrupt line with INT_RF_CPE1 1055 // interrupt vector 1056 // CPE0 Associate this interrupt line with INT_RF_CPE0 1057 // interrupt vector 1058 #define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 1059 #define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 1060 #define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 1061 #define RFC_DBELL_RFCPEISL_IRQ27_S 27 1062 #define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 1063 #define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 1064 1065 // Field: [26] RX_ABORTED 1066 // 1067 // Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should 1068 // use. 1069 // ENUMs: 1070 // CPE1 Associate this interrupt line with INT_RF_CPE1 1071 // interrupt vector 1072 // CPE0 Associate this interrupt line with INT_RF_CPE0 1073 // interrupt vector 1074 #define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 1075 #define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 1076 #define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 1077 #define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 1078 #define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 1079 #define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 1080 1081 // Field: [25] RX_N_DATA_WRITTEN 1082 // 1083 // Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt 1084 // should use. 1085 // ENUMs: 1086 // CPE1 Associate this interrupt line with INT_RF_CPE1 1087 // interrupt vector 1088 // CPE0 Associate this interrupt line with INT_RF_CPE0 1089 // interrupt vector 1090 #define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 1091 #define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 1092 #define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 1093 #define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 1094 #define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 1095 #define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 1096 1097 // Field: [24] RX_DATA_WRITTEN 1098 // 1099 // Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt 1100 // should use. 1101 // ENUMs: 1102 // CPE1 Associate this interrupt line with INT_RF_CPE1 1103 // interrupt vector 1104 // CPE0 Associate this interrupt line with INT_RF_CPE0 1105 // interrupt vector 1106 #define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 1107 #define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 1108 #define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 1109 #define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 1110 #define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 1111 #define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 1112 1113 // Field: [23] RX_ENTRY_DONE 1114 // 1115 // Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt 1116 // should use. 1117 // ENUMs: 1118 // CPE1 Associate this interrupt line with INT_RF_CPE1 1119 // interrupt vector 1120 // CPE0 Associate this interrupt line with INT_RF_CPE0 1121 // interrupt vector 1122 #define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 1123 #define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 1124 #define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 1125 #define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 1126 #define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 1127 #define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 1128 1129 // Field: [22] RX_BUF_FULL 1130 // 1131 // Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should 1132 // use. 1133 // ENUMs: 1134 // CPE1 Associate this interrupt line with INT_RF_CPE1 1135 // interrupt vector 1136 // CPE0 Associate this interrupt line with INT_RF_CPE0 1137 // interrupt vector 1138 #define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 1139 #define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 1140 #define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 1141 #define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 1142 #define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 1143 #define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 1144 1145 // Field: [21] RX_CTRL_ACK 1146 // 1147 // Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should 1148 // use. 1149 // ENUMs: 1150 // CPE1 Associate this interrupt line with INT_RF_CPE1 1151 // interrupt vector 1152 // CPE0 Associate this interrupt line with INT_RF_CPE0 1153 // interrupt vector 1154 #define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 1155 #define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 1156 #define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 1157 #define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 1158 #define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 1159 #define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 1160 1161 // Field: [20] RX_CTRL 1162 // 1163 // Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use. 1164 // ENUMs: 1165 // CPE1 Associate this interrupt line with INT_RF_CPE1 1166 // interrupt vector 1167 // CPE0 Associate this interrupt line with INT_RF_CPE0 1168 // interrupt vector 1169 #define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 1170 #define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 1171 #define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 1172 #define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 1173 #define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 1174 #define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 1175 1176 // Field: [19] RX_EMPTY 1177 // 1178 // Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should 1179 // use. 1180 // ENUMs: 1181 // CPE1 Associate this interrupt line with INT_RF_CPE1 1182 // interrupt vector 1183 // CPE0 Associate this interrupt line with INT_RF_CPE0 1184 // interrupt vector 1185 #define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 1186 #define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 1187 #define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 1188 #define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 1189 #define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 1190 #define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 1191 1192 // Field: [18] RX_IGNORED 1193 // 1194 // Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should 1195 // use. 1196 // ENUMs: 1197 // CPE1 Associate this interrupt line with INT_RF_CPE1 1198 // interrupt vector 1199 // CPE0 Associate this interrupt line with INT_RF_CPE0 1200 // interrupt vector 1201 #define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 1202 #define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 1203 #define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 1204 #define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 1205 #define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 1206 #define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 1207 1208 // Field: [17] RX_NOK 1209 // 1210 // Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use. 1211 // ENUMs: 1212 // CPE1 Associate this interrupt line with INT_RF_CPE1 1213 // interrupt vector 1214 // CPE0 Associate this interrupt line with INT_RF_CPE0 1215 // interrupt vector 1216 #define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 1217 #define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 1218 #define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 1219 #define RFC_DBELL_RFCPEISL_RX_NOK_S 17 1220 #define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 1221 #define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 1222 1223 // Field: [16] RX_OK 1224 // 1225 // Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use. 1226 // ENUMs: 1227 // CPE1 Associate this interrupt line with INT_RF_CPE1 1228 // interrupt vector 1229 // CPE0 Associate this interrupt line with INT_RF_CPE0 1230 // interrupt vector 1231 #define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 1232 #define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 1233 #define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 1234 #define RFC_DBELL_RFCPEISL_RX_OK_S 16 1235 #define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 1236 #define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 1237 1238 // Field: [15] IRQ15 1239 // 1240 // Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use. 1241 // ENUMs: 1242 // CPE1 Associate this interrupt line with INT_RF_CPE1 1243 // interrupt vector 1244 // CPE0 Associate this interrupt line with INT_RF_CPE0 1245 // interrupt vector 1246 #define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 1247 #define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 1248 #define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 1249 #define RFC_DBELL_RFCPEISL_IRQ15_S 15 1250 #define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 1251 #define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 1252 1253 // Field: [14] IRQ14 1254 // 1255 // Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use. 1256 // ENUMs: 1257 // CPE1 Associate this interrupt line with INT_RF_CPE1 1258 // interrupt vector 1259 // CPE0 Associate this interrupt line with INT_RF_CPE0 1260 // interrupt vector 1261 #define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 1262 #define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 1263 #define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 1264 #define RFC_DBELL_RFCPEISL_IRQ14_S 14 1265 #define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 1266 #define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 1267 1268 // Field: [13] FG_COMMAND_STARTED 1269 // 1270 // Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_STARTED interrupt 1271 // should use. 1272 // ENUMs: 1273 // CPE1 Associate this interrupt line with INT_RF_CPE1 1274 // interrupt vector 1275 // CPE0 Associate this interrupt line with INT_RF_CPE0 1276 // interrupt vector 1277 #define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED 0x00002000 1278 #define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_BITN 13 1279 #define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_M 0x00002000 1280 #define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_S 13 1281 #define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE1 0x00002000 1282 #define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE0 0x00000000 1283 1284 // Field: [12] COMMAND_STARTED 1285 // 1286 // Select which CPU interrupt vector the RFCPEIFG.COMMAND_STARTED interrupt 1287 // should use. 1288 // ENUMs: 1289 // CPE1 Associate this interrupt line with INT_RF_CPE1 1290 // interrupt vector 1291 // CPE0 Associate this interrupt line with INT_RF_CPE0 1292 // interrupt vector 1293 #define RFC_DBELL_RFCPEISL_COMMAND_STARTED 0x00001000 1294 #define RFC_DBELL_RFCPEISL_COMMAND_STARTED_BITN 12 1295 #define RFC_DBELL_RFCPEISL_COMMAND_STARTED_M 0x00001000 1296 #define RFC_DBELL_RFCPEISL_COMMAND_STARTED_S 12 1297 #define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE1 0x00001000 1298 #define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE0 0x00000000 1299 1300 // Field: [11] TX_BUFFER_CHANGED 1301 // 1302 // Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt 1303 // should use. 1304 // ENUMs: 1305 // CPE1 Associate this interrupt line with INT_RF_CPE1 1306 // interrupt vector 1307 // CPE0 Associate this interrupt line with INT_RF_CPE0 1308 // interrupt vector 1309 #define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 1310 #define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 1311 #define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 1312 #define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 1313 #define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 1314 #define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 1315 1316 // Field: [10] TX_ENTRY_DONE 1317 // 1318 // Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt 1319 // should use. 1320 // ENUMs: 1321 // CPE1 Associate this interrupt line with INT_RF_CPE1 1322 // interrupt vector 1323 // CPE0 Associate this interrupt line with INT_RF_CPE0 1324 // interrupt vector 1325 #define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 1326 #define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 1327 #define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 1328 #define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 1329 #define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 1330 #define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 1331 1332 // Field: [9] TX_RETRANS 1333 // 1334 // Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should 1335 // use. 1336 // ENUMs: 1337 // CPE1 Associate this interrupt line with INT_RF_CPE1 1338 // interrupt vector 1339 // CPE0 Associate this interrupt line with INT_RF_CPE0 1340 // interrupt vector 1341 #define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 1342 #define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 1343 #define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 1344 #define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 1345 #define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 1346 #define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 1347 1348 // Field: [8] TX_CTRL_ACK_ACK 1349 // 1350 // Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt 1351 // should use. 1352 // ENUMs: 1353 // CPE1 Associate this interrupt line with INT_RF_CPE1 1354 // interrupt vector 1355 // CPE0 Associate this interrupt line with INT_RF_CPE0 1356 // interrupt vector 1357 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 1358 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 1359 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 1360 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 1361 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 1362 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 1363 1364 // Field: [7] TX_CTRL_ACK 1365 // 1366 // Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should 1367 // use. 1368 // ENUMs: 1369 // CPE1 Associate this interrupt line with INT_RF_CPE1 1370 // interrupt vector 1371 // CPE0 Associate this interrupt line with INT_RF_CPE0 1372 // interrupt vector 1373 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 1374 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 1375 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 1376 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 1377 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 1378 #define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 1379 1380 // Field: [6] TX_CTRL 1381 // 1382 // Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use. 1383 // ENUMs: 1384 // CPE1 Associate this interrupt line with INT_RF_CPE1 1385 // interrupt vector 1386 // CPE0 Associate this interrupt line with INT_RF_CPE0 1387 // interrupt vector 1388 #define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 1389 #define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 1390 #define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 1391 #define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 1392 #define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 1393 #define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 1394 1395 // Field: [5] TX_ACK 1396 // 1397 // Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use. 1398 // ENUMs: 1399 // CPE1 Associate this interrupt line with INT_RF_CPE1 1400 // interrupt vector 1401 // CPE0 Associate this interrupt line with INT_RF_CPE0 1402 // interrupt vector 1403 #define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 1404 #define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 1405 #define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 1406 #define RFC_DBELL_RFCPEISL_TX_ACK_S 5 1407 #define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 1408 #define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 1409 1410 // Field: [4] TX_DONE 1411 // 1412 // Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use. 1413 // ENUMs: 1414 // CPE1 Associate this interrupt line with INT_RF_CPE1 1415 // interrupt vector 1416 // CPE0 Associate this interrupt line with INT_RF_CPE0 1417 // interrupt vector 1418 #define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 1419 #define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 1420 #define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 1421 #define RFC_DBELL_RFCPEISL_TX_DONE_S 4 1422 #define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 1423 #define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 1424 1425 // Field: [3] LAST_FG_COMMAND_DONE 1426 // 1427 // Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE 1428 // interrupt should use. 1429 // ENUMs: 1430 // CPE1 Associate this interrupt line with INT_RF_CPE1 1431 // interrupt vector 1432 // CPE0 Associate this interrupt line with INT_RF_CPE0 1433 // interrupt vector 1434 #define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 1435 #define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 1436 #define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 1437 #define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 1438 #define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 1439 #define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 1440 1441 // Field: [2] FG_COMMAND_DONE 1442 // 1443 // Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt 1444 // should use. 1445 // ENUMs: 1446 // CPE1 Associate this interrupt line with INT_RF_CPE1 1447 // interrupt vector 1448 // CPE0 Associate this interrupt line with INT_RF_CPE0 1449 // interrupt vector 1450 #define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 1451 #define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 1452 #define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 1453 #define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 1454 #define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 1455 #define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 1456 1457 // Field: [1] LAST_COMMAND_DONE 1458 // 1459 // Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt 1460 // should use. 1461 // ENUMs: 1462 // CPE1 Associate this interrupt line with INT_RF_CPE1 1463 // interrupt vector 1464 // CPE0 Associate this interrupt line with INT_RF_CPE0 1465 // interrupt vector 1466 #define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 1467 #define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 1468 #define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 1469 #define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 1470 #define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 1471 #define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 1472 1473 // Field: [0] COMMAND_DONE 1474 // 1475 // Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should 1476 // use. 1477 // ENUMs: 1478 // CPE1 Associate this interrupt line with INT_RF_CPE1 1479 // interrupt vector 1480 // CPE0 Associate this interrupt line with INT_RF_CPE0 1481 // interrupt vector 1482 #define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 1483 #define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 1484 #define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 1485 #define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 1486 #define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 1487 #define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 1488 1489 //***************************************************************************** 1490 // 1491 // Register: RFC_DBELL_O_RFACKIFG 1492 // 1493 //***************************************************************************** 1494 // Field: [0] ACKFLAG 1495 // 1496 // Interrupt flag for Command ACK 1497 #define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 1498 #define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 1499 #define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 1500 #define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 1501 1502 //***************************************************************************** 1503 // 1504 // Register: RFC_DBELL_O_SYSGPOCTL 1505 // 1506 //***************************************************************************** 1507 // Field: [15:12] GPOCTL3 1508 // 1509 // RF Core GPO control bit 3. Selects which signal to output on the RF Core GPO 1510 // line 3. 1511 // ENUMs: 1512 // RATGPO3 RAT GPO line 3 1513 // RATGPO2 RAT GPO line 2 1514 // RATGPO1 RAT GPO line 1 1515 // RATGPO0 RAT GPO line 0 1516 // RFEGPO3 RFE GPO line 3 1517 // RFEGPO2 RFE GPO line 2 1518 // RFEGPO1 RFE GPO line 1 1519 // RFEGPO0 RFE GPO line 0 1520 // MCEGPO3 MCE GPO line 3 1521 // MCEGPO2 MCE GPO line 2 1522 // MCEGPO1 MCE GPO line 1 1523 // MCEGPO0 MCE GPO line 0 1524 // CPEGPO3 CPE GPO line 3 1525 // CPEGPO2 CPE GPO line 2 1526 // CPEGPO1 CPE GPO line 1 1527 // CPEGPO0 CPE GPO line 0 1528 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 1529 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 1530 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 1531 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 1532 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 1533 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 1534 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 1535 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 1536 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 1537 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 1538 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 1539 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 1540 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 1541 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 1542 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 1543 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 1544 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 1545 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 1546 #define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 1547 1548 // Field: [11:8] GPOCTL2 1549 // 1550 // RF Core GPO control bit 2. Selects which signal to output on the RF Core GPO 1551 // line 2. 1552 // ENUMs: 1553 // RATGPO3 RAT GPO line 3 1554 // RATGPO2 RAT GPO line 2 1555 // RATGPO1 RAT GPO line 1 1556 // RATGPO0 RAT GPO line 0 1557 // RFEGPO3 RFE GPO line 3 1558 // RFEGPO2 RFE GPO line 2 1559 // RFEGPO1 RFE GPO line 1 1560 // RFEGPO0 RFE GPO line 0 1561 // MCEGPO3 MCE GPO line 3 1562 // MCEGPO2 MCE GPO line 2 1563 // MCEGPO1 MCE GPO line 1 1564 // MCEGPO0 MCE GPO line 0 1565 // CPEGPO3 CPE GPO line 3 1566 // CPEGPO2 CPE GPO line 2 1567 // CPEGPO1 CPE GPO line 1 1568 // CPEGPO0 CPE GPO line 0 1569 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 1570 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 1571 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 1572 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 1573 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 1574 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 1575 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 1576 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 1577 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 1578 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 1579 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 1580 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 1581 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 1582 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 1583 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 1584 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 1585 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 1586 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 1587 #define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 1588 1589 // Field: [7:4] GPOCTL1 1590 // 1591 // RF Core GPO control bit 1. Selects which signal to output on the RF Core GPO 1592 // line 1. 1593 // ENUMs: 1594 // RATGPO3 RAT GPO line 3 1595 // RATGPO2 RAT GPO line 2 1596 // RATGPO1 RAT GPO line 1 1597 // RATGPO0 RAT GPO line 0 1598 // RFEGPO3 RFE GPO line 3 1599 // RFEGPO2 RFE GPO line 2 1600 // RFEGPO1 RFE GPO line 1 1601 // RFEGPO0 RFE GPO line 0 1602 // MCEGPO3 MCE GPO line 3 1603 // MCEGPO2 MCE GPO line 2 1604 // MCEGPO1 MCE GPO line 1 1605 // MCEGPO0 MCE GPO line 0 1606 // CPEGPO3 CPE GPO line 3 1607 // CPEGPO2 CPE GPO line 2 1608 // CPEGPO1 CPE GPO line 1 1609 // CPEGPO0 CPE GPO line 0 1610 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 1611 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 1612 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 1613 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 1614 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 1615 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 1616 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 1617 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 1618 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 1619 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 1620 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 1621 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 1622 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 1623 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 1624 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 1625 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 1626 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 1627 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 1628 #define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 1629 1630 // Field: [3:0] GPOCTL0 1631 // 1632 // RF Core GPO control bit 0. Selects which signal to output on the RF Core GPO 1633 // line 0. 1634 // ENUMs: 1635 // RATGPO3 RAT GPO line 3 1636 // RATGPO2 RAT GPO line 2 1637 // RATGPO1 RAT GPO line 1 1638 // RATGPO0 RAT GPO line 0 1639 // RFEGPO3 RFE GPO line 3 1640 // RFEGPO2 RFE GPO line 2 1641 // RFEGPO1 RFE GPO line 1 1642 // RFEGPO0 RFE GPO line 0 1643 // MCEGPO3 MCE GPO line 3 1644 // MCEGPO2 MCE GPO line 2 1645 // MCEGPO1 MCE GPO line 1 1646 // MCEGPO0 MCE GPO line 0 1647 // CPEGPO3 CPE GPO line 3 1648 // CPEGPO2 CPE GPO line 2 1649 // CPEGPO1 CPE GPO line 1 1650 // CPEGPO0 CPE GPO line 0 1651 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 1652 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F 1653 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 1654 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F 1655 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E 1656 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D 1657 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C 1658 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B 1659 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A 1660 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 1661 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 1662 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 1663 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 1664 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 1665 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 1666 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 1667 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 1668 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 1669 #define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 1670 1671 1672 #endif // __RFC_DBELL__ 1673
