1 /****************************************************************************** 2 * Filename: hw_prcm_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_PRCM_H__ 38 #define __HW_PRCM_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // PRCM component 44 // 45 //***************************************************************************** 46 // Infrastructure Clock Division Factor For Run Mode 47 #define PRCM_O_INFRCLKDIVR 0x00000000 48 49 // Infrastructure Clock Division Factor For Sleep Mode 50 #define PRCM_O_INFRCLKDIVS 0x00000004 51 52 // Infrastructure Clock Division Factor For DeepSleep Mode 53 #define PRCM_O_INFRCLKDIVDS 0x00000008 54 55 // MCU Voltage Domain Control 56 #define PRCM_O_VDCTL 0x0000000C 57 58 // Load PRCM Settings To CLKCTRL Power Domain 59 #define PRCM_O_CLKLOADCTL 0x00000028 60 61 // RFC Clock Gate 62 #define PRCM_O_RFCCLKG 0x0000002C 63 64 // VIMS Clock Gate 65 #define PRCM_O_VIMSCLKG 0x00000030 66 67 // SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes 68 #define PRCM_O_SECDMACLKGR 0x0000003C 69 70 // SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode 71 #define PRCM_O_SECDMACLKGS 0x00000040 72 73 // SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode 74 #define PRCM_O_SECDMACLKGDS 0x00000044 75 76 // GPIO Clock Gate For Run And All Modes 77 #define PRCM_O_GPIOCLKGR 0x00000048 78 79 // GPIO Clock Gate For Sleep Mode 80 #define PRCM_O_GPIOCLKGS 0x0000004C 81 82 // GPIO Clock Gate For Deep Sleep Mode 83 #define PRCM_O_GPIOCLKGDS 0x00000050 84 85 // GPT Clock Gate For Run And All Modes 86 #define PRCM_O_GPTCLKGR 0x00000054 87 88 // GPT Clock Gate For Sleep Mode 89 #define PRCM_O_GPTCLKGS 0x00000058 90 91 // GPT Clock Gate For Deep Sleep Mode 92 #define PRCM_O_GPTCLKGDS 0x0000005C 93 94 // I2C Clock Gate For Run And All Modes 95 #define PRCM_O_I2CCLKGR 0x00000060 96 97 // I2C Clock Gate For Sleep Mode 98 #define PRCM_O_I2CCLKGS 0x00000064 99 100 // I2C Clock Gate For Deep Sleep Mode 101 #define PRCM_O_I2CCLKGDS 0x00000068 102 103 // UART Clock Gate For Run And All Modes 104 #define PRCM_O_UARTCLKGR 0x0000006C 105 106 // UART Clock Gate For Sleep Mode 107 #define PRCM_O_UARTCLKGS 0x00000070 108 109 // UART Clock Gate For Deep Sleep Mode 110 #define PRCM_O_UARTCLKGDS 0x00000074 111 112 // SSI Clock Gate For Run And All Modes 113 #define PRCM_O_SSICLKGR 0x00000078 114 115 // SSI Clock Gate For Sleep Mode 116 #define PRCM_O_SSICLKGS 0x0000007C 117 118 // SSI Clock Gate For Deep Sleep Mode 119 #define PRCM_O_SSICLKGDS 0x00000080 120 121 // I2S Clock Gate For Run And All Modes 122 #define PRCM_O_I2SCLKGR 0x00000084 123 124 // I2S Clock Gate For Sleep Mode 125 #define PRCM_O_I2SCLKGS 0x00000088 126 127 // I2S Clock Gate For Deep Sleep Mode 128 #define PRCM_O_I2SCLKGDS 0x0000008C 129 130 // Internal 131 #define PRCM_O_SYSBUSCLKDIV 0x000000B4 132 133 // Internal 134 #define PRCM_O_CPUCLKDIV 0x000000B8 135 136 // Internal 137 #define PRCM_O_PERBUSCPUCLKDIV 0x000000BC 138 139 // Internal 140 #define PRCM_O_PERDMACLKDIV 0x000000C4 141 142 // I2S Clock Control 143 #define PRCM_O_I2SBCLKSEL 0x000000C8 144 145 // GPT Scalar 146 #define PRCM_O_GPTCLKDIV 0x000000CC 147 148 // I2S Clock Control 149 #define PRCM_O_I2SCLKCTL 0x000000D0 150 151 // MCLK Division Ratio 152 #define PRCM_O_I2SMCLKDIV 0x000000D4 153 154 // BCLK Division Ratio 155 #define PRCM_O_I2SBCLKDIV 0x000000D8 156 157 // WCLK Division Ratio 158 #define PRCM_O_I2SWCLKDIV 0x000000DC 159 160 // RESET For SEC (PKA And TRNG And CRYPTO) And UDMA 161 #define PRCM_O_RESETSECDMA 0x000000F0 162 163 // RESET For GPIO IPs 164 #define PRCM_O_RESETGPIO 0x000000F4 165 166 // RESET For GPT Ips 167 #define PRCM_O_RESETGPT 0x000000F8 168 169 // RESET For I2C IPs 170 #define PRCM_O_RESETI2C 0x000000FC 171 172 // RESET For UART IPs 173 #define PRCM_O_RESETUART 0x00000100 174 175 // RESET For SSI IPs 176 #define PRCM_O_RESETSSI 0x00000104 177 178 // RESET For I2S IP 179 #define PRCM_O_RESETI2S 0x00000108 180 181 // Power Domain Control 182 #define PRCM_O_PDCTL0 0x0000012C 183 184 // RFC Power Domain Control 185 #define PRCM_O_PDCTL0RFC 0x00000130 186 187 // SERIAL Power Domain Control 188 #define PRCM_O_PDCTL0SERIAL 0x00000134 189 190 // PERIPH Power Domain Control 191 #define PRCM_O_PDCTL0PERIPH 0x00000138 192 193 // Power Domain Status 194 #define PRCM_O_PDSTAT0 0x00000140 195 196 // RFC Power Domain Status 197 #define PRCM_O_PDSTAT0RFC 0x00000144 198 199 // SERIAL Power Domain Status 200 #define PRCM_O_PDSTAT0SERIAL 0x00000148 201 202 // PERIPH Power Domain Status 203 #define PRCM_O_PDSTAT0PERIPH 0x0000014C 204 205 // Power Domain Control 206 #define PRCM_O_PDCTL1 0x0000017C 207 208 // CPU Power Domain Direct Control 209 #define PRCM_O_PDCTL1CPU 0x00000184 210 211 // RFC Power Domain Direct Control 212 #define PRCM_O_PDCTL1RFC 0x00000188 213 214 // VIMS Mode Direct Control 215 #define PRCM_O_PDCTL1VIMS 0x0000018C 216 217 // Power Manager Status 218 #define PRCM_O_PDSTAT1 0x00000194 219 220 // BUS Power Domain Direct Read Status 221 #define PRCM_O_PDSTAT1BUS 0x00000198 222 223 // RFC Power Domain Direct Read Status 224 #define PRCM_O_PDSTAT1RFC 0x0000019C 225 226 // CPU Power Domain Direct Read Status 227 #define PRCM_O_PDSTAT1CPU 0x000001A0 228 229 // VIMS Mode Direct Read Status 230 #define PRCM_O_PDSTAT1VIMS 0x000001A4 231 232 // Control To RFC 233 #define PRCM_O_RFCBITS 0x000001CC 234 235 // Selected RFC Mode 236 #define PRCM_O_RFCMODESEL 0x000001D0 237 238 // Allowed RFC Modes 239 #define PRCM_O_RFCMODEHWOPT 0x000001D4 240 241 // Power Profiler Register 242 #define PRCM_O_PWRPROFSTAT 0x000001E0 243 244 // MCU SRAM configuration 245 #define PRCM_O_MCUSRAMCFG 0x0000021C 246 247 // Memory Retention Control 248 #define PRCM_O_RAMRETEN 0x00000224 249 250 // Oscillator Interrupt Mask 251 #define PRCM_O_OSCIMSC 0x00000290 252 253 // Oscillator Raw Interrupt Status 254 #define PRCM_O_OSCRIS 0x00000294 255 256 // Oscillator Raw Interrupt Clear 257 #define PRCM_O_OSCICR 0x00000298 258 259 //***************************************************************************** 260 // 261 // Register: PRCM_O_INFRCLKDIVR 262 // 263 //***************************************************************************** 264 // Field: [1:0] RATIO 265 // 266 // Division rate for clocks driving modules in the MCU_AON domain when system 267 // CPU is in run mode. Division ratio affects both infrastructure clock and 268 // perbusull clock. 269 // ENUMs: 270 // DIV32 Divide by 32 271 // DIV8 Divide by 8 272 // DIV2 Divide by 2 273 // DIV1 Divide by 1 274 #define PRCM_INFRCLKDIVR_RATIO_W 2 275 #define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 276 #define PRCM_INFRCLKDIVR_RATIO_S 0 277 #define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 278 #define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 279 #define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 280 #define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 281 282 //***************************************************************************** 283 // 284 // Register: PRCM_O_INFRCLKDIVS 285 // 286 //***************************************************************************** 287 // Field: [1:0] RATIO 288 // 289 // Division rate for clocks driving modules in the MCU_AON domain when system 290 // CPU is in sleep mode. Division ratio affects both infrastructure clock and 291 // perbusull clock. 292 // ENUMs: 293 // DIV32 Divide by 32 294 // DIV8 Divide by 8 295 // DIV2 Divide by 2 296 // DIV1 Divide by 1 297 #define PRCM_INFRCLKDIVS_RATIO_W 2 298 #define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 299 #define PRCM_INFRCLKDIVS_RATIO_S 0 300 #define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 301 #define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 302 #define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 303 #define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 304 305 //***************************************************************************** 306 // 307 // Register: PRCM_O_INFRCLKDIVDS 308 // 309 //***************************************************************************** 310 // Field: [1:0] RATIO 311 // 312 // Division rate for clocks driving modules in the MCU_AON domain when system 313 // CPU is in seepsleep mode. Division ratio affects both infrastructure clock 314 // and perbusull clock. 315 // ENUMs: 316 // DIV32 Divide by 32 317 // DIV8 Divide by 8 318 // DIV2 Divide by 2 319 // DIV1 Divide by 1 320 #define PRCM_INFRCLKDIVDS_RATIO_W 2 321 #define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 322 #define PRCM_INFRCLKDIVDS_RATIO_S 0 323 #define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 324 #define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 325 #define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 326 #define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 327 328 //***************************************************************************** 329 // 330 // Register: PRCM_O_VDCTL 331 // 332 //***************************************************************************** 333 // Field: [0] ULDO 334 // 335 // Request PMCTL to switch to uLDO. 336 // 337 // 0: No request 338 // 1: Assert request when possible 339 // 340 // The bit will have no effect before the following requirements are met: 341 // 1. PDCTL1.CPU_ON = 0 342 // 2. PDCTL1.VIMS_MODE = x0 343 // 3. SECDMACLKGDS.DMA_CLK_EN = 0 and S.CRYPTO_CLK_EN] = 0 and 344 // SECDMACLKGR.DMA_AM_CLK_EN = 0 (Note: Settings must be loaded with 345 // CLKLOADCTL.LOAD) 346 // 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 and SECDMACLKGR.CRYPTO_AM_CLK_EN = 0 347 // (Note: Settings must be loaded with CLKLOADCTL.LOAD) 348 // 5. I2SCLKGDS.CLK_EN = 0 and I2SCLKGR.AM_CLK_EN = 0 (Note: Settings must be 349 // loaded with CLKLOADCTL.LOAD) 350 // 6. RFC do no request access to BUS 351 // 7. System CPU in deepsleep 352 #define PRCM_VDCTL_ULDO 0x00000001 353 #define PRCM_VDCTL_ULDO_BITN 0 354 #define PRCM_VDCTL_ULDO_M 0x00000001 355 #define PRCM_VDCTL_ULDO_S 0 356 357 //***************************************************************************** 358 // 359 // Register: PRCM_O_CLKLOADCTL 360 // 361 //***************************************************************************** 362 // Field: [1] LOAD_DONE 363 // 364 // Status of LOAD. 365 // Will be cleared to 0 when any of the registers requiring a LOAD is written 366 // to, and be set to 1 when a LOAD is done. 367 // Note that writing no change to a register will result in the LOAD_DONE being 368 // cleared. 369 // 370 // 0 : One or more registers have been write accessed after last LOAD 371 // 1 : No registers are write accessed after last LOAD 372 #define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 373 #define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 374 #define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 375 #define PRCM_CLKLOADCTL_LOAD_DONE_S 1 376 377 // Field: [0] LOAD 378 // 379 // 380 // 0: No action 381 // 1: Load settings to CLKCTRL. Bit is HW cleared. 382 // 383 // Multiple changes to settings may be done before LOAD is written once so all 384 // changes takes place at the same time. LOAD can also be done after single 385 // setting updates. 386 // 387 // Registers that needs to be followed by LOAD before settings being applied 388 // are: 389 // - SYSBUSCLKDIV 390 // - CPUCLKDIV 391 // - PERBUSCPUCLKDIV 392 // - PERDMACLKDIV 393 // - PERBUSCPUCLKG 394 // - RFCCLKG 395 // - VIMSCLKG 396 // - SECDMACLKGR 397 // - SECDMACLKGS 398 // - SECDMACLKGDS 399 // - GPIOCLKGR 400 // - GPIOCLKGS 401 // - GPIOCLKGDS 402 // - GPTCLKGR 403 // - GPTCLKGS 404 // - GPTCLKGDS 405 // - GPTCLKDIV 406 // - I2CCLKGR 407 // - I2CCLKGS 408 // - I2CCLKGDS 409 // - SSICLKGR 410 // - SSICLKGS 411 // - SSICLKGDS 412 // - UARTCLKGR 413 // - UARTCLKGS 414 // - UARTCLKGDS 415 // - I2SCLKGR 416 // - I2SCLKGS 417 // - I2SCLKGDS 418 // - I2SBCLKSEL 419 // - I2SCLKCTL 420 // - I2SMCLKDIV 421 // - I2SBCLKDIV 422 // - I2SWCLKDIV 423 #define PRCM_CLKLOADCTL_LOAD 0x00000001 424 #define PRCM_CLKLOADCTL_LOAD_BITN 0 425 #define PRCM_CLKLOADCTL_LOAD_M 0x00000001 426 #define PRCM_CLKLOADCTL_LOAD_S 0 427 428 //***************************************************************************** 429 // 430 // Register: PRCM_O_RFCCLKG 431 // 432 //***************************************************************************** 433 // Field: [0] CLK_EN 434 // 435 // 436 // 0: Disable Clock 437 // 1: Enable clock if RFC power domain is on 438 // 439 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 440 #define PRCM_RFCCLKG_CLK_EN 0x00000001 441 #define PRCM_RFCCLKG_CLK_EN_BITN 0 442 #define PRCM_RFCCLKG_CLK_EN_M 0x00000001 443 #define PRCM_RFCCLKG_CLK_EN_S 0 444 445 //***************************************************************************** 446 // 447 // Register: PRCM_O_VIMSCLKG 448 // 449 //***************************************************************************** 450 // Field: [1:0] CLK_EN 451 // 452 // 00: Disable clock 453 // 01: Disable clock when SYSBUS clock is disabled 454 // 11: Enable clock 455 // 456 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 457 #define PRCM_VIMSCLKG_CLK_EN_W 2 458 #define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 459 #define PRCM_VIMSCLKG_CLK_EN_S 0 460 461 //***************************************************************************** 462 // 463 // Register: PRCM_O_SECDMACLKGR 464 // 465 //***************************************************************************** 466 // Field: [24] DMA_AM_CLK_EN 467 // 468 // 469 // 0: No force 470 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 471 // 472 // Overrides DMA_CLK_EN, SECDMACLKGS.DMA_CLK_EN and SECDMACLKGDS.DMA_CLK_EN 473 // when enabled. 474 // 475 // SYSBUS clock will always run when enabled 476 // 477 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 478 #define PRCM_SECDMACLKGR_DMA_AM_CLK_EN 0x01000000 479 #define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_BITN 24 480 #define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_M 0x01000000 481 #define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_S 24 482 483 // Field: [19] PKA_ZERIOZE_RESET_N 484 // 485 // Zeroization logic hardware reset. 486 // 487 // 0: pka_zeroize logic inactive. 488 // 1: pka_zeroize of memory is enabled. 489 // 490 // This register must remain active until the memory are completely zeroized 491 // which requires 256 periods on systembus clock. 492 #define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N 0x00080000 493 #define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_BITN 19 494 #define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_M 0x00080000 495 #define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_S 19 496 497 // Field: [18] PKA_AM_CLK_EN 498 // 499 // 500 // 0: No force 501 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 502 // 503 // Overrides PKA_CLK_EN, SECDMACLKGS.PKA_CLK_EN and SECDMACLKGDS.PKA_CLK_EN 504 // when enabled. 505 // 506 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 507 #define PRCM_SECDMACLKGR_PKA_AM_CLK_EN 0x00040000 508 #define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_BITN 18 509 #define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_M 0x00040000 510 #define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_S 18 511 512 // Field: [17] TRNG_AM_CLK_EN 513 // 514 // 515 // 0: No force 516 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 517 // 518 // Overrides TRNG_CLK_EN, SECDMACLKGS.TRNG_CLK_EN and SECDMACLKGDS.TRNG_CLK_EN 519 // when enabled. 520 // 521 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 522 #define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN 0x00020000 523 #define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_BITN 17 524 #define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_M 0x00020000 525 #define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_S 17 526 527 // Field: [16] CRYPTO_AM_CLK_EN 528 // 529 // 530 // 0: No force 531 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 532 // 533 // Overrides CRYPTO_CLK_EN, SECDMACLKGS.CRYPTO_CLK_EN and 534 // SECDMACLKGDS.CRYPTO_CLK_EN when enabled. 535 // 536 // SYSBUS clock will always run when enabled 537 // 538 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 539 #define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN 0x00010000 540 #define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_BITN 16 541 #define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_M 0x00010000 542 #define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_S 16 543 544 // Field: [8] DMA_CLK_EN 545 // 546 // 547 // 0: Disable clock 548 // 1: Enable clock 549 // 550 // Can be forced on by DMA_AM_CLK_EN 551 // 552 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 553 #define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 554 #define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 555 #define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 556 #define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 557 558 // Field: [2] PKA_CLK_EN 559 // 560 // 561 // 0: Disable clock 562 // 1: Enable clock 563 // 564 // Can be forced on by PKA_AM_CLK_EN 565 // 566 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 567 #define PRCM_SECDMACLKGR_PKA_CLK_EN 0x00000004 568 #define PRCM_SECDMACLKGR_PKA_CLK_EN_BITN 2 569 #define PRCM_SECDMACLKGR_PKA_CLK_EN_M 0x00000004 570 #define PRCM_SECDMACLKGR_PKA_CLK_EN_S 2 571 572 // Field: [1] TRNG_CLK_EN 573 // 574 // 575 // 0: Disable clock 576 // 1: Enable clock 577 // 578 // Can be forced on by TRNG_AM_CLK_EN 579 // 580 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 581 #define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 582 #define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 583 #define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 584 #define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 585 586 // Field: [0] CRYPTO_CLK_EN 587 // 588 // 589 // 0: Disable clock 590 // 1: Enable clock 591 // 592 // Can be forced on by CRYPTO_AM_CLK_EN 593 // 594 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 595 #define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 596 #define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 597 #define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 598 #define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 599 600 //***************************************************************************** 601 // 602 // Register: PRCM_O_SECDMACLKGS 603 // 604 //***************************************************************************** 605 // Field: [8] DMA_CLK_EN 606 // 607 // 608 // 0: Disable clock 609 // 1: Enable clock 610 // 611 // Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN 612 // 613 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 614 #define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 615 #define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 616 #define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 617 #define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 618 619 // Field: [2] PKA_CLK_EN 620 // 621 // 622 // 0: Disable clock 623 // 1: Enable clock 624 // 625 // Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN 626 // 627 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 628 #define PRCM_SECDMACLKGS_PKA_CLK_EN 0x00000004 629 #define PRCM_SECDMACLKGS_PKA_CLK_EN_BITN 2 630 #define PRCM_SECDMACLKGS_PKA_CLK_EN_M 0x00000004 631 #define PRCM_SECDMACLKGS_PKA_CLK_EN_S 2 632 633 // Field: [1] TRNG_CLK_EN 634 // 635 // 636 // 0: Disable clock 637 // 1: Enable clock 638 // 639 // Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN 640 // 641 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 642 #define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 643 #define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 644 #define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 645 #define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 646 647 // Field: [0] CRYPTO_CLK_EN 648 // 649 // 650 // 0: Disable clock 651 // 1: Enable clock 652 // 653 // Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN 654 // 655 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 656 #define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 657 #define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 658 #define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 659 #define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 660 661 //***************************************************************************** 662 // 663 // Register: PRCM_O_SECDMACLKGDS 664 // 665 //***************************************************************************** 666 // Field: [8] DMA_CLK_EN 667 // 668 // 669 // 0: Disable clock 670 // 1: Enable clock 671 // 672 // Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN 673 // 674 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 675 #define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 676 #define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 677 #define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 678 #define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 679 680 // Field: [2] PKA_CLK_EN 681 // 682 // 683 // 0: Disable clock 684 // 1: Enable clock 685 // 686 // Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN 687 // 688 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 689 #define PRCM_SECDMACLKGDS_PKA_CLK_EN 0x00000004 690 #define PRCM_SECDMACLKGDS_PKA_CLK_EN_BITN 2 691 #define PRCM_SECDMACLKGDS_PKA_CLK_EN_M 0x00000004 692 #define PRCM_SECDMACLKGDS_PKA_CLK_EN_S 2 693 694 // Field: [1] TRNG_CLK_EN 695 // 696 // 697 // 0: Disable clock 698 // 1: Enable clock 699 // 700 // SYSBUS clock will always run when enabled 701 // 702 // Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN 703 // 704 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 705 #define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 706 #define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 707 #define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 708 #define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 709 710 // Field: [0] CRYPTO_CLK_EN 711 // 712 // 713 // 0: Disable clock 714 // 1: Enable clock 715 // 716 // SYSBUS clock will always run when enabled 717 // 718 // Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN 719 // 720 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 721 #define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 722 #define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 723 #define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 724 #define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 725 726 //***************************************************************************** 727 // 728 // Register: PRCM_O_GPIOCLKGR 729 // 730 //***************************************************************************** 731 // Field: [8] AM_CLK_EN 732 // 733 // 734 // 0: No force 735 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 736 // 737 // Overrides CLK_EN, GPIOCLKGS.CLK_EN and GPIOCLKGDS.CLK_EN when enabled. 738 // 739 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 740 #define PRCM_GPIOCLKGR_AM_CLK_EN 0x00000100 741 #define PRCM_GPIOCLKGR_AM_CLK_EN_BITN 8 742 #define PRCM_GPIOCLKGR_AM_CLK_EN_M 0x00000100 743 #define PRCM_GPIOCLKGR_AM_CLK_EN_S 8 744 745 // Field: [0] CLK_EN 746 // 747 // 748 // 0: Disable clock 749 // 1: Enable clock 750 // 751 // Can be forced on by AM_CLK_EN 752 // 753 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 754 #define PRCM_GPIOCLKGR_CLK_EN 0x00000001 755 #define PRCM_GPIOCLKGR_CLK_EN_BITN 0 756 #define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 757 #define PRCM_GPIOCLKGR_CLK_EN_S 0 758 759 //***************************************************************************** 760 // 761 // Register: PRCM_O_GPIOCLKGS 762 // 763 //***************************************************************************** 764 // Field: [0] CLK_EN 765 // 766 // 767 // 0: Disable clock 768 // 1: Enable clock 769 // 770 // Can be forced on by GPIOCLKGR.AM_CLK_EN 771 // 772 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 773 #define PRCM_GPIOCLKGS_CLK_EN 0x00000001 774 #define PRCM_GPIOCLKGS_CLK_EN_BITN 0 775 #define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 776 #define PRCM_GPIOCLKGS_CLK_EN_S 0 777 778 //***************************************************************************** 779 // 780 // Register: PRCM_O_GPIOCLKGDS 781 // 782 //***************************************************************************** 783 // Field: [0] CLK_EN 784 // 785 // 786 // 0: Disable clock 787 // 1: Enable clock 788 // 789 // Can be forced on by GPIOCLKGR.AM_CLK_EN 790 // 791 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 792 #define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 793 #define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 794 #define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 795 #define PRCM_GPIOCLKGDS_CLK_EN_S 0 796 797 //***************************************************************************** 798 // 799 // Register: PRCM_O_GPTCLKGR 800 // 801 //***************************************************************************** 802 // Field: [11:8] AM_CLK_EN 803 // 804 // Each bit below has the following meaning: 805 // 806 // 0: No force 807 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 808 // 809 // Overrides CLK_EN, GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled. 810 // 811 // ENUMs can be combined 812 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 813 // ENUMs: 814 // AM_GPT3 Enable clock for GPT3 in all modes 815 // AM_GPT2 Enable clock for GPT2 in all modes 816 // AM_GPT1 Enable clock for GPT1 in all modes 817 // AM_GPT0 Enable clock for GPT0 in all modes 818 #define PRCM_GPTCLKGR_AM_CLK_EN_W 4 819 #define PRCM_GPTCLKGR_AM_CLK_EN_M 0x00000F00 820 #define PRCM_GPTCLKGR_AM_CLK_EN_S 8 821 #define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT3 0x00000800 822 #define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT2 0x00000400 823 #define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT1 0x00000200 824 #define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT0 0x00000100 825 826 // Field: [3:0] CLK_EN 827 // 828 // Each bit below has the following meaning: 829 // 830 // 0: Disable clock 831 // 1: Enable clock 832 // 833 // Can be forced on by AM_CLK_EN 834 // 835 // ENUMs can be combined 836 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 837 // ENUMs: 838 // GPT3 Enable clock for GPT3 839 // GPT2 Enable clock for GPT2 840 // GPT1 Enable clock for GPT1 841 // GPT0 Enable clock for GPT0 842 #define PRCM_GPTCLKGR_CLK_EN_W 4 843 #define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F 844 #define PRCM_GPTCLKGR_CLK_EN_S 0 845 #define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 846 #define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 847 #define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 848 #define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 849 850 //***************************************************************************** 851 // 852 // Register: PRCM_O_GPTCLKGS 853 // 854 //***************************************************************************** 855 // Field: [3:0] CLK_EN 856 // 857 // Each bit below has the following meaning: 858 // 859 // 0: Disable clock 860 // 1: Enable clock 861 // 862 // Can be forced on by GPTCLKGR.AM_CLK_EN 863 // 864 // ENUMs can be combined 865 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 866 // ENUMs: 867 // GPT3 Enable clock for GPT3 868 // GPT2 Enable clock for GPT2 869 // GPT1 Enable clock for GPT1 870 // GPT0 Enable clock for GPT0 871 #define PRCM_GPTCLKGS_CLK_EN_W 4 872 #define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F 873 #define PRCM_GPTCLKGS_CLK_EN_S 0 874 #define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 875 #define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 876 #define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 877 #define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 878 879 //***************************************************************************** 880 // 881 // Register: PRCM_O_GPTCLKGDS 882 // 883 //***************************************************************************** 884 // Field: [3:0] CLK_EN 885 // 886 // Each bit below has the following meaning: 887 // 888 // 0: Disable clock 889 // 1: Enable clock 890 // 891 // Can be forced on by GPTCLKGR.AM_CLK_EN 892 // 893 // ENUMs can be combined 894 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 895 // ENUMs: 896 // GPT3 Enable clock for GPT3 897 // GPT2 Enable clock for GPT2 898 // GPT1 Enable clock for GPT1 899 // GPT0 Enable clock for GPT0 900 #define PRCM_GPTCLKGDS_CLK_EN_W 4 901 #define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F 902 #define PRCM_GPTCLKGDS_CLK_EN_S 0 903 #define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 904 #define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 905 #define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 906 #define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 907 908 //***************************************************************************** 909 // 910 // Register: PRCM_O_I2CCLKGR 911 // 912 //***************************************************************************** 913 // Field: [8] AM_CLK_EN 914 // 915 // 916 // 0: No force 917 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 918 // 919 // Overrides CLK_EN, I2CCLKGS.CLK_EN and I2CCLKGDS.CLK_EN when enabled. 920 // 921 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 922 #define PRCM_I2CCLKGR_AM_CLK_EN 0x00000100 923 #define PRCM_I2CCLKGR_AM_CLK_EN_BITN 8 924 #define PRCM_I2CCLKGR_AM_CLK_EN_M 0x00000100 925 #define PRCM_I2CCLKGR_AM_CLK_EN_S 8 926 927 // Field: [0] CLK_EN 928 // 929 // 930 // 0: Disable clock 931 // 1: Enable clock 932 // 933 // Can be forced on by AM_CLK_EN 934 // 935 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 936 #define PRCM_I2CCLKGR_CLK_EN 0x00000001 937 #define PRCM_I2CCLKGR_CLK_EN_BITN 0 938 #define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 939 #define PRCM_I2CCLKGR_CLK_EN_S 0 940 941 //***************************************************************************** 942 // 943 // Register: PRCM_O_I2CCLKGS 944 // 945 //***************************************************************************** 946 // Field: [0] CLK_EN 947 // 948 // 949 // 0: Disable clock 950 // 1: Enable clock 951 // 952 // Can be forced on by I2CCLKGR.AM_CLK_EN 953 // 954 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 955 #define PRCM_I2CCLKGS_CLK_EN 0x00000001 956 #define PRCM_I2CCLKGS_CLK_EN_BITN 0 957 #define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 958 #define PRCM_I2CCLKGS_CLK_EN_S 0 959 960 //***************************************************************************** 961 // 962 // Register: PRCM_O_I2CCLKGDS 963 // 964 //***************************************************************************** 965 // Field: [0] CLK_EN 966 // 967 // 968 // 0: Disable clock 969 // 1: Enable clock 970 // 971 // Can be forced on by I2CCLKGR.AM_CLK_EN 972 // 973 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 974 #define PRCM_I2CCLKGDS_CLK_EN 0x00000001 975 #define PRCM_I2CCLKGDS_CLK_EN_BITN 0 976 #define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 977 #define PRCM_I2CCLKGDS_CLK_EN_S 0 978 979 //***************************************************************************** 980 // 981 // Register: PRCM_O_UARTCLKGR 982 // 983 //***************************************************************************** 984 // Field: [9:8] AM_CLK_EN 985 // 986 // 987 // 0: No force 988 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 989 // 990 // Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled. 991 // 992 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 993 // ENUMs: 994 // AM_UART1 Enable clock for UART1 995 // AM_UART0 Enable clock for UART0 996 #define PRCM_UARTCLKGR_AM_CLK_EN_W 2 997 #define PRCM_UARTCLKGR_AM_CLK_EN_M 0x00000300 998 #define PRCM_UARTCLKGR_AM_CLK_EN_S 8 999 #define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART1 0x00000200 1000 #define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART0 0x00000100 1001 1002 // Field: [1:0] CLK_EN 1003 // 1004 // 1005 // 0: Disable clock 1006 // 1: Enable clock 1007 // 1008 // Can be forced on by AM_CLK_EN 1009 // 1010 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1011 // ENUMs: 1012 // UART1 Enable clock for UART1 1013 // UART0 Enable clock for UART0 1014 #define PRCM_UARTCLKGR_CLK_EN_W 2 1015 #define PRCM_UARTCLKGR_CLK_EN_M 0x00000003 1016 #define PRCM_UARTCLKGR_CLK_EN_S 0 1017 #define PRCM_UARTCLKGR_CLK_EN_UART1 0x00000002 1018 #define PRCM_UARTCLKGR_CLK_EN_UART0 0x00000001 1019 1020 //***************************************************************************** 1021 // 1022 // Register: PRCM_O_UARTCLKGS 1023 // 1024 //***************************************************************************** 1025 // Field: [1:0] CLK_EN 1026 // 1027 // 1028 // 0: Disable clock 1029 // 1: Enable clock 1030 // 1031 // Can be forced on by UARTCLKGR.AM_CLK_EN 1032 // 1033 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1034 // ENUMs: 1035 // AM_UART1 Enable clock for UART1 1036 // AM_UART0 Enable clock for UART0 1037 #define PRCM_UARTCLKGS_CLK_EN_W 2 1038 #define PRCM_UARTCLKGS_CLK_EN_M 0x00000003 1039 #define PRCM_UARTCLKGS_CLK_EN_S 0 1040 #define PRCM_UARTCLKGS_CLK_EN_AM_UART1 0x00000002 1041 #define PRCM_UARTCLKGS_CLK_EN_AM_UART0 0x00000001 1042 1043 //***************************************************************************** 1044 // 1045 // Register: PRCM_O_UARTCLKGDS 1046 // 1047 //***************************************************************************** 1048 // Field: [1:0] CLK_EN 1049 // 1050 // 1051 // 0: Disable clock 1052 // 1: Enable clock 1053 // 1054 // Can be forced on by UARTCLKGR.AM_CLK_EN 1055 // 1056 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1057 // ENUMs: 1058 // AM_UART1 Enable clock for UART1 1059 // AM_UART0 Enable clock for UART0 1060 #define PRCM_UARTCLKGDS_CLK_EN_W 2 1061 #define PRCM_UARTCLKGDS_CLK_EN_M 0x00000003 1062 #define PRCM_UARTCLKGDS_CLK_EN_S 0 1063 #define PRCM_UARTCLKGDS_CLK_EN_AM_UART1 0x00000002 1064 #define PRCM_UARTCLKGDS_CLK_EN_AM_UART0 0x00000001 1065 1066 //***************************************************************************** 1067 // 1068 // Register: PRCM_O_SSICLKGR 1069 // 1070 //***************************************************************************** 1071 // Field: [9:8] AM_CLK_EN 1072 // 1073 // 1074 // 0: No force 1075 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 1076 // 1077 // Overrides CLK_EN, SSICLKGS.CLK_EN and SSICLKGDS.CLK_EN when enabled. 1078 // 1079 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1080 // ENUMs: 1081 // SSI1 Enable clock for SSI1 1082 // SSI0 Enable clock for SSI0 1083 #define PRCM_SSICLKGR_AM_CLK_EN_W 2 1084 #define PRCM_SSICLKGR_AM_CLK_EN_M 0x00000300 1085 #define PRCM_SSICLKGR_AM_CLK_EN_S 8 1086 #define PRCM_SSICLKGR_AM_CLK_EN_SSI1 0x00000200 1087 #define PRCM_SSICLKGR_AM_CLK_EN_SSI0 0x00000100 1088 1089 // Field: [1:0] CLK_EN 1090 // 1091 // 1092 // 0: Disable clock 1093 // 1: Enable clock 1094 // 1095 // Can be forced on by AM_CLK_EN 1096 // 1097 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1098 // ENUMs: 1099 // SSI1 Enable clock for SSI1 1100 // SSI0 Enable clock for SSI0 1101 #define PRCM_SSICLKGR_CLK_EN_W 2 1102 #define PRCM_SSICLKGR_CLK_EN_M 0x00000003 1103 #define PRCM_SSICLKGR_CLK_EN_S 0 1104 #define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 1105 #define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 1106 1107 //***************************************************************************** 1108 // 1109 // Register: PRCM_O_SSICLKGS 1110 // 1111 //***************************************************************************** 1112 // Field: [1:0] CLK_EN 1113 // 1114 // 1115 // 0: Disable clock 1116 // 1: Enable clock 1117 // 1118 // Can be forced on by SSICLKGR.AM_CLK_EN 1119 // 1120 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1121 // ENUMs: 1122 // SSI1 Enable clock for SSI1 1123 // SSI0 Enable clock for SSI0 1124 #define PRCM_SSICLKGS_CLK_EN_W 2 1125 #define PRCM_SSICLKGS_CLK_EN_M 0x00000003 1126 #define PRCM_SSICLKGS_CLK_EN_S 0 1127 #define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 1128 #define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 1129 1130 //***************************************************************************** 1131 // 1132 // Register: PRCM_O_SSICLKGDS 1133 // 1134 //***************************************************************************** 1135 // Field: [1:0] CLK_EN 1136 // 1137 // 1138 // 0: Disable clock 1139 // 1: Enable clock 1140 // 1141 // Can be forced on by SSICLKGR.AM_CLK_EN 1142 // 1143 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1144 // ENUMs: 1145 // SSI1 Enable clock for SSI1 1146 // SSI0 Enable clock for SSI0 1147 #define PRCM_SSICLKGDS_CLK_EN_W 2 1148 #define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 1149 #define PRCM_SSICLKGDS_CLK_EN_S 0 1150 #define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 1151 #define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 1152 1153 //***************************************************************************** 1154 // 1155 // Register: PRCM_O_I2SCLKGR 1156 // 1157 //***************************************************************************** 1158 // Field: [8] AM_CLK_EN 1159 // 1160 // 1161 // 0: No force 1162 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 1163 // 1164 // Overrides CLK_EN, I2SCLKGS.CLK_EN and I2SCLKGDS.CLK_EN when enabled. 1165 // SYSBUS clock will always run when enabled 1166 // 1167 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1168 #define PRCM_I2SCLKGR_AM_CLK_EN 0x00000100 1169 #define PRCM_I2SCLKGR_AM_CLK_EN_BITN 8 1170 #define PRCM_I2SCLKGR_AM_CLK_EN_M 0x00000100 1171 #define PRCM_I2SCLKGR_AM_CLK_EN_S 8 1172 1173 // Field: [0] CLK_EN 1174 // 1175 // 1176 // 0: Disable clock 1177 // 1: Enable clock 1178 // 1179 // Can be forced on by AM_CLK_EN 1180 // 1181 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1182 #define PRCM_I2SCLKGR_CLK_EN 0x00000001 1183 #define PRCM_I2SCLKGR_CLK_EN_BITN 0 1184 #define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 1185 #define PRCM_I2SCLKGR_CLK_EN_S 0 1186 1187 //***************************************************************************** 1188 // 1189 // Register: PRCM_O_I2SCLKGS 1190 // 1191 //***************************************************************************** 1192 // Field: [0] CLK_EN 1193 // 1194 // 1195 // 0: Disable clock 1196 // 1: Enable clock 1197 // 1198 // Can be forced on by I2SCLKGR.AM_CLK_EN 1199 // 1200 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1201 #define PRCM_I2SCLKGS_CLK_EN 0x00000001 1202 #define PRCM_I2SCLKGS_CLK_EN_BITN 0 1203 #define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 1204 #define PRCM_I2SCLKGS_CLK_EN_S 0 1205 1206 //***************************************************************************** 1207 // 1208 // Register: PRCM_O_I2SCLKGDS 1209 // 1210 //***************************************************************************** 1211 // Field: [0] CLK_EN 1212 // 1213 // 1214 // 0: Disable clock 1215 // 1: Enable clock 1216 // 1217 // SYSBUS clock will always run when enabled 1218 // 1219 // Can be forced on by I2SCLKGR.AM_CLK_EN 1220 // 1221 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1222 #define PRCM_I2SCLKGDS_CLK_EN 0x00000001 1223 #define PRCM_I2SCLKGDS_CLK_EN_BITN 0 1224 #define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 1225 #define PRCM_I2SCLKGDS_CLK_EN_S 0 1226 1227 //***************************************************************************** 1228 // 1229 // Register: PRCM_O_SYSBUSCLKDIV 1230 // 1231 //***************************************************************************** 1232 // Field: [2:0] RATIO 1233 // 1234 // Internal. Only to be used through TI provided API. 1235 // ENUMs: 1236 // DIV2 Internal. Only to be used through TI provided API. 1237 // DIV1 Internal. Only to be used through TI provided API. 1238 #define PRCM_SYSBUSCLKDIV_RATIO_W 3 1239 #define PRCM_SYSBUSCLKDIV_RATIO_M 0x00000007 1240 #define PRCM_SYSBUSCLKDIV_RATIO_S 0 1241 #define PRCM_SYSBUSCLKDIV_RATIO_DIV2 0x00000001 1242 #define PRCM_SYSBUSCLKDIV_RATIO_DIV1 0x00000000 1243 1244 //***************************************************************************** 1245 // 1246 // Register: PRCM_O_CPUCLKDIV 1247 // 1248 //***************************************************************************** 1249 // Field: [0] RATIO 1250 // 1251 // Internal. Only to be used through TI provided API. 1252 // ENUMs: 1253 // DIV2 Internal. Only to be used through TI provided API. 1254 // DIV1 Internal. Only to be used through TI provided API. 1255 #define PRCM_CPUCLKDIV_RATIO 0x00000001 1256 #define PRCM_CPUCLKDIV_RATIO_BITN 0 1257 #define PRCM_CPUCLKDIV_RATIO_M 0x00000001 1258 #define PRCM_CPUCLKDIV_RATIO_S 0 1259 #define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 1260 #define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 1261 1262 //***************************************************************************** 1263 // 1264 // Register: PRCM_O_PERBUSCPUCLKDIV 1265 // 1266 //***************************************************************************** 1267 // Field: [3:0] RATIO 1268 // 1269 // Internal. Only to be used through TI provided API. 1270 // ENUMs: 1271 // DIV256 Internal. Only to be used through TI provided API. 1272 // DIV128 Internal. Only to be used through TI provided API. 1273 // DIV64 Internal. Only to be used through TI provided API. 1274 // DIV32 Internal. Only to be used through TI provided API. 1275 // DIV16 Internal. Only to be used through TI provided API. 1276 // DIV8 Internal. Only to be used through TI provided API. 1277 // DIV4 Internal. Only to be used through TI provided API. 1278 // DIV2 Internal. Only to be used through TI provided API. 1279 // DIV1 Internal. Only to be used through TI provided API. 1280 #define PRCM_PERBUSCPUCLKDIV_RATIO_W 4 1281 #define PRCM_PERBUSCPUCLKDIV_RATIO_M 0x0000000F 1282 #define PRCM_PERBUSCPUCLKDIV_RATIO_S 0 1283 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV256 0x00000008 1284 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV128 0x00000007 1285 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV64 0x00000006 1286 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV32 0x00000005 1287 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV16 0x00000004 1288 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV8 0x00000003 1289 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV4 0x00000002 1290 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV2 0x00000001 1291 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV1 0x00000000 1292 1293 //***************************************************************************** 1294 // 1295 // Register: PRCM_O_PERDMACLKDIV 1296 // 1297 //***************************************************************************** 1298 // Field: [3:0] RATIO 1299 // 1300 // Internal. Only to be used through TI provided API. 1301 // ENUMs: 1302 // DIV256 Internal. Only to be used through TI provided API. 1303 // DIV128 Internal. Only to be used through TI provided API. 1304 // DIV64 Internal. Only to be used through TI provided API. 1305 // DIV32 Internal. Only to be used through TI provided API. 1306 // DIV16 Internal. Only to be used through TI provided API. 1307 // DIV8 Internal. Only to be used through TI provided API. 1308 // DIV4 Internal. Only to be used through TI provided API. 1309 // DIV2 Internal. Only to be used through TI provided API. 1310 // DIV1 Internal. Only to be used through TI provided API. 1311 #define PRCM_PERDMACLKDIV_RATIO_W 4 1312 #define PRCM_PERDMACLKDIV_RATIO_M 0x0000000F 1313 #define PRCM_PERDMACLKDIV_RATIO_S 0 1314 #define PRCM_PERDMACLKDIV_RATIO_DIV256 0x00000008 1315 #define PRCM_PERDMACLKDIV_RATIO_DIV128 0x00000007 1316 #define PRCM_PERDMACLKDIV_RATIO_DIV64 0x00000006 1317 #define PRCM_PERDMACLKDIV_RATIO_DIV32 0x00000005 1318 #define PRCM_PERDMACLKDIV_RATIO_DIV16 0x00000004 1319 #define PRCM_PERDMACLKDIV_RATIO_DIV8 0x00000003 1320 #define PRCM_PERDMACLKDIV_RATIO_DIV4 0x00000002 1321 #define PRCM_PERDMACLKDIV_RATIO_DIV2 0x00000001 1322 #define PRCM_PERDMACLKDIV_RATIO_DIV1 0x00000000 1323 1324 //***************************************************************************** 1325 // 1326 // Register: PRCM_O_I2SBCLKSEL 1327 // 1328 //***************************************************************************** 1329 // Field: [0] SRC 1330 // 1331 // BCLK source selector 1332 // 1333 // 0: Use external BCLK 1334 // 1: Use internally generated clock 1335 // 1336 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1337 #define PRCM_I2SBCLKSEL_SRC 0x00000001 1338 #define PRCM_I2SBCLKSEL_SRC_BITN 0 1339 #define PRCM_I2SBCLKSEL_SRC_M 0x00000001 1340 #define PRCM_I2SBCLKSEL_SRC_S 0 1341 1342 //***************************************************************************** 1343 // 1344 // Register: PRCM_O_GPTCLKDIV 1345 // 1346 //***************************************************************************** 1347 // Field: [3:0] RATIO 1348 // 1349 // Scalar used for GPTs. The division rate will be constant and ungated for Run 1350 // / Sleep / DeepSleep mode. For changes to take effect, CLKLOADCTL.LOAD 1351 // needs to be written Other values are not supported. 1352 // ENUMs: 1353 // DIV256 Divide by 256 1354 // DIV128 Divide by 128 1355 // DIV64 Divide by 64 1356 // DIV32 Divide by 32 1357 // DIV16 Divide by 16 1358 // DIV8 Divide by 8 1359 // DIV4 Divide by 4 1360 // DIV2 Divide by 2 1361 // DIV1 Divide by 1 1362 #define PRCM_GPTCLKDIV_RATIO_W 4 1363 #define PRCM_GPTCLKDIV_RATIO_M 0x0000000F 1364 #define PRCM_GPTCLKDIV_RATIO_S 0 1365 #define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 1366 #define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 1367 #define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 1368 #define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 1369 #define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 1370 #define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 1371 #define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 1372 #define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 1373 #define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 1374 1375 //***************************************************************************** 1376 // 1377 // Register: PRCM_O_I2SCLKCTL 1378 // 1379 //***************************************************************************** 1380 // Field: [3] SMPL_ON_POSEDGE 1381 // 1382 // On the I2S serial interface, data and WCLK is sampled and clocked out on 1383 // opposite edges of BCLK. 1384 // 1385 // 0 - data and WCLK are sampled on the negative edge and clocked out on the 1386 // positive edge. 1387 // 1 - data and WCLK are sampled on the positive edge and clocked out on the 1388 // negative edge. 1389 // 1390 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1391 #define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 1392 #define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 1393 #define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 1394 #define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 1395 1396 // Field: [2:1] WCLK_PHASE 1397 // 1398 // Decides how the WCLK division ratio is calculated and used to generate 1399 // different duty cycles (See I2SWCLKDIV.WDIV). 1400 // 1401 // 0: Single phase 1402 // 1: Dual phase 1403 // 2: User Defined 1404 // 3: Reserved/Undefined 1405 // 1406 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1407 #define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 1408 #define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 1409 #define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 1410 1411 // Field: [0] EN 1412 // 1413 // 1414 // 0: MCLK, BCLK and WCLK will be static low 1415 // 1: Enables the generation of MCLK, BCLK and WCLK 1416 // 1417 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1418 #define PRCM_I2SCLKCTL_EN 0x00000001 1419 #define PRCM_I2SCLKCTL_EN_BITN 0 1420 #define PRCM_I2SCLKCTL_EN_M 0x00000001 1421 #define PRCM_I2SCLKCTL_EN_S 0 1422 1423 //***************************************************************************** 1424 // 1425 // Register: PRCM_O_I2SMCLKDIV 1426 // 1427 //***************************************************************************** 1428 // Field: [9:0] MDIV 1429 // 1430 // An unsigned factor of the division ratio used to generate MCLK [2-1024]: 1431 // 1432 // MCLK = MCUCLK/MDIV[Hz] 1433 // MCUCLK is 48MHz. 1434 // 1435 // A value of 0 is interpreted as 1024. 1436 // A value of 1 is invalid. 1437 // If MDIV is odd the low phase of the clock is one MCUCLK period longer than 1438 // the high phase. 1439 // 1440 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1441 #define PRCM_I2SMCLKDIV_MDIV_W 10 1442 #define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF 1443 #define PRCM_I2SMCLKDIV_MDIV_S 0 1444 1445 //***************************************************************************** 1446 // 1447 // Register: PRCM_O_I2SBCLKDIV 1448 // 1449 //***************************************************************************** 1450 // Field: [9:0] BDIV 1451 // 1452 // An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: 1453 // 1454 // BCLK = MCUCLK/BDIV[Hz] 1455 // MCUCLK is 48MHz. 1456 // 1457 // A value of 0 is interpreted as 1024. 1458 // A value of 1 is invalid. 1459 // If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock 1460 // is one MCUCLK period longer than the high phase. 1461 // If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the 1462 // clock is one MCUCLK period longer than the low phase. 1463 // 1464 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1465 #define PRCM_I2SBCLKDIV_BDIV_W 10 1466 #define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF 1467 #define PRCM_I2SBCLKDIV_BDIV_S 0 1468 1469 //***************************************************************************** 1470 // 1471 // Register: PRCM_O_I2SWCLKDIV 1472 // 1473 //***************************************************************************** 1474 // Field: [15:0] WDIV 1475 // 1476 // If I2SCLKCTL.WCLK_PHASE = 0, Single phase. 1477 // WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK 1478 // periods. 1479 // 1480 // WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] 1481 // MCUCLK is 48MHz. 1482 // 1483 // If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. 1484 // Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK 1485 // periods. 1486 // 1487 // WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] 1488 // 1489 // If I2SCLKCTL.WCLK_PHASE = 2, User defined. 1490 // WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] 1491 // (unsigned, [1-255]) BCLK periods. 1492 // 1493 // WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] 1494 // 1495 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1496 #define PRCM_I2SWCLKDIV_WDIV_W 16 1497 #define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF 1498 #define PRCM_I2SWCLKDIV_WDIV_S 0 1499 1500 //***************************************************************************** 1501 // 1502 // Register: PRCM_O_RESETSECDMA 1503 // 1504 //***************************************************************************** 1505 // Field: [8] DMA 1506 // 1507 // Write 1 to reset. HW cleared. 1508 // Acess will only have effect when PERIPH power domain is on, 1509 // PDSTAT0.PERIPH_ON = 1 1510 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1511 // activated while executing from flash. This means one cannot execute from 1512 // flash when using the SW reset. 1513 #define PRCM_RESETSECDMA_DMA 0x00000100 1514 #define PRCM_RESETSECDMA_DMA_BITN 8 1515 #define PRCM_RESETSECDMA_DMA_M 0x00000100 1516 #define PRCM_RESETSECDMA_DMA_S 8 1517 1518 // Field: [2] PKA 1519 // 1520 // Write 1 to reset. HW cleared. 1521 // Acess will only have effect when PERIPH power domain is on, 1522 // PDSTAT0.PERIPH_ON = 1 1523 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1524 // activated while executing from flash. This means one cannot execute from 1525 // flash when using the SW reset. 1526 #define PRCM_RESETSECDMA_PKA 0x00000004 1527 #define PRCM_RESETSECDMA_PKA_BITN 2 1528 #define PRCM_RESETSECDMA_PKA_M 0x00000004 1529 #define PRCM_RESETSECDMA_PKA_S 2 1530 1531 // Field: [1] TRNG 1532 // 1533 // Write 1 to reset. HW cleared. 1534 // Acess will only have effect when PERIPH power domain is on, 1535 // PDSTAT0.PERIPH_ON = 1 1536 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1537 // activated while executing from flash. This means one cannot execute from 1538 // flash when using the SW reset. 1539 #define PRCM_RESETSECDMA_TRNG 0x00000002 1540 #define PRCM_RESETSECDMA_TRNG_BITN 1 1541 #define PRCM_RESETSECDMA_TRNG_M 0x00000002 1542 #define PRCM_RESETSECDMA_TRNG_S 1 1543 1544 // Field: [0] CRYPTO 1545 // 1546 // Write 1 to reset. HW cleared. 1547 // Acess will only have effect when PERIPH power domain is on, 1548 // PDSTAT0.PERIPH_ON = 1 1549 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1550 // activated while executing from flash. This means one cannot execute from 1551 // flash when using the SW reset. 1552 #define PRCM_RESETSECDMA_CRYPTO 0x00000001 1553 #define PRCM_RESETSECDMA_CRYPTO_BITN 0 1554 #define PRCM_RESETSECDMA_CRYPTO_M 0x00000001 1555 #define PRCM_RESETSECDMA_CRYPTO_S 0 1556 1557 //***************************************************************************** 1558 // 1559 // Register: PRCM_O_RESETGPIO 1560 // 1561 //***************************************************************************** 1562 // Field: [0] GPIO 1563 // 1564 // 1565 // 0: No action 1566 // 1: Reset GPIO. HW cleared. 1567 // 1568 // Acess will only have effect when PERIPH power domain is on, 1569 // PDSTAT0.PERIPH_ON = 1 1570 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1571 // activated while executing from flash. This means one cannot execute from 1572 // flash when using the SW reset. 1573 #define PRCM_RESETGPIO_GPIO 0x00000001 1574 #define PRCM_RESETGPIO_GPIO_BITN 0 1575 #define PRCM_RESETGPIO_GPIO_M 0x00000001 1576 #define PRCM_RESETGPIO_GPIO_S 0 1577 1578 //***************************************************************************** 1579 // 1580 // Register: PRCM_O_RESETGPT 1581 // 1582 //***************************************************************************** 1583 // Field: [0] GPT 1584 // 1585 // 1586 // 0: No action 1587 // 1: Reset all GPTs. HW cleared. 1588 // 1589 // Acess will only have effect when PERIPH power domain is on, 1590 // PDSTAT0.PERIPH_ON = 1 1591 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1592 // activated while executing from flash. This means one cannot execute from 1593 // flash when using the SW reset. 1594 #define PRCM_RESETGPT_GPT 0x00000001 1595 #define PRCM_RESETGPT_GPT_BITN 0 1596 #define PRCM_RESETGPT_GPT_M 0x00000001 1597 #define PRCM_RESETGPT_GPT_S 0 1598 1599 //***************************************************************************** 1600 // 1601 // Register: PRCM_O_RESETI2C 1602 // 1603 //***************************************************************************** 1604 // Field: [0] I2C 1605 // 1606 // 1607 // 0: No action 1608 // 1: Reset I2C. HW cleared. 1609 // 1610 // Acess will only have effect when SERIAL power domain is on, 1611 // PDSTAT0.SERIAL_ON = 1 1612 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1613 // activated while executing from flash. This means one cannot execute from 1614 // flash when using the SW reset. 1615 #define PRCM_RESETI2C_I2C 0x00000001 1616 #define PRCM_RESETI2C_I2C_BITN 0 1617 #define PRCM_RESETI2C_I2C_M 0x00000001 1618 #define PRCM_RESETI2C_I2C_S 0 1619 1620 //***************************************************************************** 1621 // 1622 // Register: PRCM_O_RESETUART 1623 // 1624 //***************************************************************************** 1625 // Field: [1] UART1 1626 // 1627 // 1628 // 0: No action 1629 // 1: Reset UART1. HW cleared. 1630 // 1631 // Acess will only have effect when PERIPH power domain is on, 1632 // PDSTAT0.PERIPH_ON = 1 1633 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1634 // activated while executing from flash. This means one cannot execute from 1635 // flash when using the SW reset. 1636 #define PRCM_RESETUART_UART1 0x00000002 1637 #define PRCM_RESETUART_UART1_BITN 1 1638 #define PRCM_RESETUART_UART1_M 0x00000002 1639 #define PRCM_RESETUART_UART1_S 1 1640 1641 // Field: [0] UART0 1642 // 1643 // 1644 // 0: No action 1645 // 1: Reset UART0. HW cleared. 1646 // 1647 // Acess will only have effect when SERIAL power domain is on, 1648 // PDSTAT0.SERIAL_ON = 1 1649 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1650 // activated while executing from flash. This means one cannot execute from 1651 // flash when using the SW reset. 1652 #define PRCM_RESETUART_UART0 0x00000001 1653 #define PRCM_RESETUART_UART0_BITN 0 1654 #define PRCM_RESETUART_UART0_M 0x00000001 1655 #define PRCM_RESETUART_UART0_S 0 1656 1657 //***************************************************************************** 1658 // 1659 // Register: PRCM_O_RESETSSI 1660 // 1661 //***************************************************************************** 1662 // Field: [1:0] SSI 1663 // 1664 // SSI 0: 1665 // 1666 // 0: No action 1667 // 1: Reset SSI. HW cleared. 1668 // 1669 // Acess will only have effect when SERIAL power domain is on, 1670 // PDSTAT0.SERIAL_ON = 1 1671 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1672 // activated while executing from flash. This means one cannot execute from 1673 // flash when using the SW reset. 1674 // 1675 // SSI 1: 1676 // 1677 // 0: No action 1678 // 1: Reset SSI. HW cleared. 1679 // 1680 // Acess will only have effect when PERIPH power domain is on, 1681 // PDSTAT0.PERIPH_ON = 1 1682 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1683 // activated while executing from flash. This means one cannot execute from 1684 // flash when using the SW reset. 1685 #define PRCM_RESETSSI_SSI_W 2 1686 #define PRCM_RESETSSI_SSI_M 0x00000003 1687 #define PRCM_RESETSSI_SSI_S 0 1688 1689 //***************************************************************************** 1690 // 1691 // Register: PRCM_O_RESETI2S 1692 // 1693 //***************************************************************************** 1694 // Field: [0] I2S 1695 // 1696 // 1697 // 0: No action 1698 // 1: Reset module. HW cleared. 1699 // 1700 // Acess will only have effect when PERIPH power domain is on, 1701 // PDSTAT0.PERIPH_ON = 1 1702 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1703 // activated while executing from flash. This means one cannot execute from 1704 // flash when using the SW reset. 1705 #define PRCM_RESETI2S_I2S 0x00000001 1706 #define PRCM_RESETI2S_I2S_BITN 0 1707 #define PRCM_RESETI2S_I2S_M 0x00000001 1708 #define PRCM_RESETI2S_I2S_S 0 1709 1710 //***************************************************************************** 1711 // 1712 // Register: PRCM_O_PDCTL0 1713 // 1714 //***************************************************************************** 1715 // Field: [2] PERIPH_ON 1716 // 1717 // PERIPH Power domain. 1718 // 1719 // 0: PERIPH power domain is powered down 1720 // 1: PERIPH power domain is powered up 1721 #define PRCM_PDCTL0_PERIPH_ON 0x00000004 1722 #define PRCM_PDCTL0_PERIPH_ON_BITN 2 1723 #define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 1724 #define PRCM_PDCTL0_PERIPH_ON_S 2 1725 1726 // Field: [1] SERIAL_ON 1727 // 1728 // SERIAL Power domain. 1729 // 1730 // 0: SERIAL power domain is powered down 1731 // 1: SERIAL power domain is powered up 1732 #define PRCM_PDCTL0_SERIAL_ON 0x00000002 1733 #define PRCM_PDCTL0_SERIAL_ON_BITN 1 1734 #define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 1735 #define PRCM_PDCTL0_SERIAL_ON_S 1 1736 1737 // Field: [0] RFC_ON 1738 // 1739 // 1740 // 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 1741 // 1: RFC power domain powered on 1742 #define PRCM_PDCTL0_RFC_ON 0x00000001 1743 #define PRCM_PDCTL0_RFC_ON_BITN 0 1744 #define PRCM_PDCTL0_RFC_ON_M 0x00000001 1745 #define PRCM_PDCTL0_RFC_ON_S 0 1746 1747 //***************************************************************************** 1748 // 1749 // Register: PRCM_O_PDCTL0RFC 1750 // 1751 //***************************************************************************** 1752 // Field: [0] ON 1753 // 1754 // Alias for PDCTL0.RFC_ON 1755 #define PRCM_PDCTL0RFC_ON 0x00000001 1756 #define PRCM_PDCTL0RFC_ON_BITN 0 1757 #define PRCM_PDCTL0RFC_ON_M 0x00000001 1758 #define PRCM_PDCTL0RFC_ON_S 0 1759 1760 //***************************************************************************** 1761 // 1762 // Register: PRCM_O_PDCTL0SERIAL 1763 // 1764 //***************************************************************************** 1765 // Field: [0] ON 1766 // 1767 // Alias for PDCTL0.SERIAL_ON 1768 #define PRCM_PDCTL0SERIAL_ON 0x00000001 1769 #define PRCM_PDCTL0SERIAL_ON_BITN 0 1770 #define PRCM_PDCTL0SERIAL_ON_M 0x00000001 1771 #define PRCM_PDCTL0SERIAL_ON_S 0 1772 1773 //***************************************************************************** 1774 // 1775 // Register: PRCM_O_PDCTL0PERIPH 1776 // 1777 //***************************************************************************** 1778 // Field: [0] ON 1779 // 1780 // Alias for PDCTL0.PERIPH_ON 1781 #define PRCM_PDCTL0PERIPH_ON 0x00000001 1782 #define PRCM_PDCTL0PERIPH_ON_BITN 0 1783 #define PRCM_PDCTL0PERIPH_ON_M 0x00000001 1784 #define PRCM_PDCTL0PERIPH_ON_S 0 1785 1786 //***************************************************************************** 1787 // 1788 // Register: PRCM_O_PDSTAT0 1789 // 1790 //***************************************************************************** 1791 // Field: [2] PERIPH_ON 1792 // 1793 // PERIPH Power domain. 1794 // 1795 // 0: Domain may be powered down 1796 // 1: Domain powered up (guaranteed) 1797 #define PRCM_PDSTAT0_PERIPH_ON 0x00000004 1798 #define PRCM_PDSTAT0_PERIPH_ON_BITN 2 1799 #define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 1800 #define PRCM_PDSTAT0_PERIPH_ON_S 2 1801 1802 // Field: [1] SERIAL_ON 1803 // 1804 // SERIAL Power domain. 1805 // 1806 // 0: Domain may be powered down 1807 // 1: Domain powered up (guaranteed) 1808 #define PRCM_PDSTAT0_SERIAL_ON 0x00000002 1809 #define PRCM_PDSTAT0_SERIAL_ON_BITN 1 1810 #define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 1811 #define PRCM_PDSTAT0_SERIAL_ON_S 1 1812 1813 // Field: [0] RFC_ON 1814 // 1815 // RFC Power domain 1816 // 1817 // 0: Domain may be powered down 1818 // 1: Domain powered up (guaranteed) 1819 #define PRCM_PDSTAT0_RFC_ON 0x00000001 1820 #define PRCM_PDSTAT0_RFC_ON_BITN 0 1821 #define PRCM_PDSTAT0_RFC_ON_M 0x00000001 1822 #define PRCM_PDSTAT0_RFC_ON_S 0 1823 1824 //***************************************************************************** 1825 // 1826 // Register: PRCM_O_PDSTAT0RFC 1827 // 1828 //***************************************************************************** 1829 // Field: [0] ON 1830 // 1831 // Alias for PDSTAT0.RFC_ON 1832 #define PRCM_PDSTAT0RFC_ON 0x00000001 1833 #define PRCM_PDSTAT0RFC_ON_BITN 0 1834 #define PRCM_PDSTAT0RFC_ON_M 0x00000001 1835 #define PRCM_PDSTAT0RFC_ON_S 0 1836 1837 //***************************************************************************** 1838 // 1839 // Register: PRCM_O_PDSTAT0SERIAL 1840 // 1841 //***************************************************************************** 1842 // Field: [0] ON 1843 // 1844 // Alias for PDSTAT0.SERIAL_ON 1845 #define PRCM_PDSTAT0SERIAL_ON 0x00000001 1846 #define PRCM_PDSTAT0SERIAL_ON_BITN 0 1847 #define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 1848 #define PRCM_PDSTAT0SERIAL_ON_S 0 1849 1850 //***************************************************************************** 1851 // 1852 // Register: PRCM_O_PDSTAT0PERIPH 1853 // 1854 //***************************************************************************** 1855 // Field: [0] ON 1856 // 1857 // Alias for PDSTAT0.PERIPH_ON 1858 #define PRCM_PDSTAT0PERIPH_ON 0x00000001 1859 #define PRCM_PDSTAT0PERIPH_ON_BITN 0 1860 #define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 1861 #define PRCM_PDSTAT0PERIPH_ON_S 0 1862 1863 //***************************************************************************** 1864 // 1865 // Register: PRCM_O_PDCTL1 1866 // 1867 //***************************************************************************** 1868 // Field: [4:3] VIMS_MODE 1869 // 1870 // 1871 // 00: VIMS power domain is only powered when CPU power domain is powered. 1872 // 01: VIMS power domain is powered whenever the BUS power domain is powered. 1873 // 1X: Block power up of VIMS power domain at next wake up. This mode only has 1874 // effect when VIMS power domain is not powered. Used for Autonomous RF Core. 1875 #define PRCM_PDCTL1_VIMS_MODE_W 2 1876 #define PRCM_PDCTL1_VIMS_MODE_M 0x00000018 1877 #define PRCM_PDCTL1_VIMS_MODE_S 3 1878 1879 // Field: [2] RFC_ON 1880 // 1881 // 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1: RFC power 1882 // domain powered on Bit shall be used by RFC in autonomous mode but there is 1883 // no HW restrictions fom system CPU to access the bit. 1884 #define PRCM_PDCTL1_RFC_ON 0x00000004 1885 #define PRCM_PDCTL1_RFC_ON_BITN 2 1886 #define PRCM_PDCTL1_RFC_ON_M 0x00000004 1887 #define PRCM_PDCTL1_RFC_ON_S 2 1888 1889 // Field: [1] CPU_ON 1890 // 1891 // 1892 // 0: Causes a power down of the CPU power domain when system CPU indicates it 1893 // is idle. 1894 // 1: Initiates power-on of the CPU power domain. 1895 // 1896 // This bit is automatically set by a WIC power-on event. 1897 #define PRCM_PDCTL1_CPU_ON 0x00000002 1898 #define PRCM_PDCTL1_CPU_ON_BITN 1 1899 #define PRCM_PDCTL1_CPU_ON_M 0x00000002 1900 #define PRCM_PDCTL1_CPU_ON_S 1 1901 1902 //***************************************************************************** 1903 // 1904 // Register: PRCM_O_PDCTL1CPU 1905 // 1906 //***************************************************************************** 1907 // Field: [0] ON 1908 // 1909 // This is an alias for PDCTL1.CPU_ON 1910 #define PRCM_PDCTL1CPU_ON 0x00000001 1911 #define PRCM_PDCTL1CPU_ON_BITN 0 1912 #define PRCM_PDCTL1CPU_ON_M 0x00000001 1913 #define PRCM_PDCTL1CPU_ON_S 0 1914 1915 //***************************************************************************** 1916 // 1917 // Register: PRCM_O_PDCTL1RFC 1918 // 1919 //***************************************************************************** 1920 // Field: [0] ON 1921 // 1922 // This is an alias for PDCTL1.RFC_ON 1923 #define PRCM_PDCTL1RFC_ON 0x00000001 1924 #define PRCM_PDCTL1RFC_ON_BITN 0 1925 #define PRCM_PDCTL1RFC_ON_M 0x00000001 1926 #define PRCM_PDCTL1RFC_ON_S 0 1927 1928 //***************************************************************************** 1929 // 1930 // Register: PRCM_O_PDCTL1VIMS 1931 // 1932 //***************************************************************************** 1933 // Field: [1:0] MODE 1934 // 1935 // This is an alias for PDCTL1.VIMS_MODE 1936 #define PRCM_PDCTL1VIMS_MODE_W 2 1937 #define PRCM_PDCTL1VIMS_MODE_M 0x00000003 1938 #define PRCM_PDCTL1VIMS_MODE_S 0 1939 1940 //***************************************************************************** 1941 // 1942 // Register: PRCM_O_PDSTAT1 1943 // 1944 //***************************************************************************** 1945 // Field: [4] BUS_ON 1946 // 1947 // 1948 // 0: BUS domain not accessible 1949 // 1: BUS domain is currently accessible 1950 #define PRCM_PDSTAT1_BUS_ON 0x00000010 1951 #define PRCM_PDSTAT1_BUS_ON_BITN 4 1952 #define PRCM_PDSTAT1_BUS_ON_M 0x00000010 1953 #define PRCM_PDSTAT1_BUS_ON_S 4 1954 1955 // Field: [3] VIMS_ON 1956 // 1957 // 1958 // 0: VIMS domain not accessible 1959 // 1: VIMS domain is currently accessible 1960 #define PRCM_PDSTAT1_VIMS_ON 0x00000008 1961 #define PRCM_PDSTAT1_VIMS_ON_BITN 3 1962 #define PRCM_PDSTAT1_VIMS_ON_M 0x00000008 1963 #define PRCM_PDSTAT1_VIMS_ON_S 3 1964 1965 // Field: [2] RFC_ON 1966 // 1967 // 1968 // 0: RFC domain not accessible 1969 // 1: RFC domain is currently accessible 1970 #define PRCM_PDSTAT1_RFC_ON 0x00000004 1971 #define PRCM_PDSTAT1_RFC_ON_BITN 2 1972 #define PRCM_PDSTAT1_RFC_ON_M 0x00000004 1973 #define PRCM_PDSTAT1_RFC_ON_S 2 1974 1975 // Field: [1] CPU_ON 1976 // 1977 // 1978 // 0: CPU and BUS domain not accessible 1979 // 1: CPU and BUS domains are both currently accessible 1980 #define PRCM_PDSTAT1_CPU_ON 0x00000002 1981 #define PRCM_PDSTAT1_CPU_ON_BITN 1 1982 #define PRCM_PDSTAT1_CPU_ON_M 0x00000002 1983 #define PRCM_PDSTAT1_CPU_ON_S 1 1984 1985 //***************************************************************************** 1986 // 1987 // Register: PRCM_O_PDSTAT1BUS 1988 // 1989 //***************************************************************************** 1990 // Field: [0] ON 1991 // 1992 // This is an alias for PDSTAT1.BUS_ON 1993 #define PRCM_PDSTAT1BUS_ON 0x00000001 1994 #define PRCM_PDSTAT1BUS_ON_BITN 0 1995 #define PRCM_PDSTAT1BUS_ON_M 0x00000001 1996 #define PRCM_PDSTAT1BUS_ON_S 0 1997 1998 //***************************************************************************** 1999 // 2000 // Register: PRCM_O_PDSTAT1RFC 2001 // 2002 //***************************************************************************** 2003 // Field: [0] ON 2004 // 2005 // This is an alias for PDSTAT1.RFC_ON 2006 #define PRCM_PDSTAT1RFC_ON 0x00000001 2007 #define PRCM_PDSTAT1RFC_ON_BITN 0 2008 #define PRCM_PDSTAT1RFC_ON_M 0x00000001 2009 #define PRCM_PDSTAT1RFC_ON_S 0 2010 2011 //***************************************************************************** 2012 // 2013 // Register: PRCM_O_PDSTAT1CPU 2014 // 2015 //***************************************************************************** 2016 // Field: [0] ON 2017 // 2018 // This is an alias for PDSTAT1.CPU_ON 2019 #define PRCM_PDSTAT1CPU_ON 0x00000001 2020 #define PRCM_PDSTAT1CPU_ON_BITN 0 2021 #define PRCM_PDSTAT1CPU_ON_M 0x00000001 2022 #define PRCM_PDSTAT1CPU_ON_S 0 2023 2024 //***************************************************************************** 2025 // 2026 // Register: PRCM_O_PDSTAT1VIMS 2027 // 2028 //***************************************************************************** 2029 // Field: [0] ON 2030 // 2031 // This is an alias for PDSTAT1.VIMS_ON 2032 #define PRCM_PDSTAT1VIMS_ON 0x00000001 2033 #define PRCM_PDSTAT1VIMS_ON_BITN 0 2034 #define PRCM_PDSTAT1VIMS_ON_M 0x00000001 2035 #define PRCM_PDSTAT1VIMS_ON_S 0 2036 2037 //***************************************************************************** 2038 // 2039 // Register: PRCM_O_RFCBITS 2040 // 2041 //***************************************************************************** 2042 // Field: [31:0] READ 2043 // 2044 // Control bits for RFC. The RF core CPE processor will automatically check 2045 // this register when it boots, and it can be used to immediately instruct CPE 2046 // to perform some tasks at its start-up. The supported functionality is 2047 // ROM-defined and may vary. See the technical reference manual for more 2048 // details. 2049 #define PRCM_RFCBITS_READ_W 32 2050 #define PRCM_RFCBITS_READ_M 0xFFFFFFFF 2051 #define PRCM_RFCBITS_READ_S 0 2052 2053 //***************************************************************************** 2054 // 2055 // Register: PRCM_O_RFCMODESEL 2056 // 2057 //***************************************************************************** 2058 // Field: [2:0] CURR 2059 // 2060 // Selects the set of commands that the RFC will accept. Only modes permitted 2061 // by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for 2062 // details. 2063 // ENUMs: 2064 // MODE7 Select Mode 7 2065 // MODE6 Select Mode 6 2066 // MODE5 Select Mode 5 2067 // MODE4 Select Mode 4 2068 // MODE3 Select Mode 3 2069 // MODE2 Select Mode 2 2070 // MODE1 Select Mode 1 2071 // MODE0 Select Mode 0 2072 #define PRCM_RFCMODESEL_CURR_W 3 2073 #define PRCM_RFCMODESEL_CURR_M 0x00000007 2074 #define PRCM_RFCMODESEL_CURR_S 0 2075 #define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 2076 #define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 2077 #define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 2078 #define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 2079 #define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 2080 #define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 2081 #define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 2082 #define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 2083 2084 //***************************************************************************** 2085 // 2086 // Register: PRCM_O_RFCMODEHWOPT 2087 // 2088 //***************************************************************************** 2089 // Field: [7:0] AVAIL 2090 // 2091 // Permitted RFC modes. More than one mode can be permitted. 2092 // ENUMs: 2093 // MODE7 Mode 7 permitted 2094 // MODE6 Mode 6 permitted 2095 // MODE5 Mode 5 permitted 2096 // MODE4 Mode 4 permitted 2097 // MODE3 Mode 3 permitted 2098 // MODE2 Mode 2 permitted 2099 // MODE1 Mode 1 permitted 2100 // MODE0 Mode 0 permitted 2101 #define PRCM_RFCMODEHWOPT_AVAIL_W 8 2102 #define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF 2103 #define PRCM_RFCMODEHWOPT_AVAIL_S 0 2104 #define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 2105 #define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 2106 #define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 2107 #define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 2108 #define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 2109 #define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 2110 #define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 2111 #define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 2112 2113 //***************************************************************************** 2114 // 2115 // Register: PRCM_O_PWRPROFSTAT 2116 // 2117 //***************************************************************************** 2118 // Field: [7:0] VALUE 2119 // 2120 // SW can use these bits to timestamp the application. These bits are also 2121 // available through the testtap and can thus be used by the emulator to 2122 // profile in real time. 2123 #define PRCM_PWRPROFSTAT_VALUE_W 8 2124 #define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF 2125 #define PRCM_PWRPROFSTAT_VALUE_S 0 2126 2127 //***************************************************************************** 2128 // 2129 // Register: PRCM_O_MCUSRAMCFG 2130 // 2131 //***************************************************************************** 2132 // Field: [5] BM_OFF 2133 // 2134 // Burst Mode disable 2135 // 2136 // 0: Burst Mode enabled. 2137 // 1: Burst Mode off. 2138 #define PRCM_MCUSRAMCFG_BM_OFF 0x00000020 2139 #define PRCM_MCUSRAMCFG_BM_OFF_BITN 5 2140 #define PRCM_MCUSRAMCFG_BM_OFF_M 0x00000020 2141 #define PRCM_MCUSRAMCFG_BM_OFF_S 5 2142 2143 // Field: [4] PAGE 2144 // 2145 // Page Mode select 2146 // 2147 // 0: Page Mode disabled. Memory works in standard mode 2148 // 1: Page Mode enabled. Only one half of butterfly array selected. Page Mode 2149 // will select either LSB half or MSB half of the word based on PGS setting. 2150 // 2151 // This mode can be used for additional power saving 2152 #define PRCM_MCUSRAMCFG_PAGE 0x00000010 2153 #define PRCM_MCUSRAMCFG_PAGE_BITN 4 2154 #define PRCM_MCUSRAMCFG_PAGE_M 0x00000010 2155 #define PRCM_MCUSRAMCFG_PAGE_S 4 2156 2157 // Field: [3] PGS 2158 // 2159 // 0: Select LSB half of word during Page Mode, PAGE = 1 2160 // 1: Select MSB half of word during Page Mode, PAGE = 1 2161 #define PRCM_MCUSRAMCFG_PGS 0x00000008 2162 #define PRCM_MCUSRAMCFG_PGS_BITN 3 2163 #define PRCM_MCUSRAMCFG_PGS_M 0x00000008 2164 #define PRCM_MCUSRAMCFG_PGS_S 3 2165 2166 // Field: [2] BM 2167 // 2168 // Burst Mode Enable 2169 // 2170 // 0: Burst Mode Disable. Memory works in standard mode. 2171 // 1: Burst Mode Enable 2172 // 2173 // When in Burst Mode bitline precharge and wordline firing depends on PCH_F 2174 // and PCH_L. 2175 // Burst Mode results in reduction in active power. 2176 #define PRCM_MCUSRAMCFG_BM 0x00000004 2177 #define PRCM_MCUSRAMCFG_BM_BITN 2 2178 #define PRCM_MCUSRAMCFG_BM_M 0x00000004 2179 #define PRCM_MCUSRAMCFG_BM_S 2 2180 2181 // Field: [1] PCH_F 2182 // 2183 // 0: No bitline precharge in second half of cycle 2184 // 1: Bitline precharge in second half of cycle when in Burst Mode, BM = 1 2185 #define PRCM_MCUSRAMCFG_PCH_F 0x00000002 2186 #define PRCM_MCUSRAMCFG_PCH_F_BITN 1 2187 #define PRCM_MCUSRAMCFG_PCH_F_M 0x00000002 2188 #define PRCM_MCUSRAMCFG_PCH_F_S 1 2189 2190 // Field: [0] PCH_L 2191 // 2192 // 0: No bitline precharge in first half of cycle 2193 // 1: Bitline precharge in first half of cycle when in Burst Mode, BM = 1 2194 #define PRCM_MCUSRAMCFG_PCH_L 0x00000001 2195 #define PRCM_MCUSRAMCFG_PCH_L_BITN 0 2196 #define PRCM_MCUSRAMCFG_PCH_L_M 0x00000001 2197 #define PRCM_MCUSRAMCFG_PCH_L_S 0 2198 2199 //***************************************************************************** 2200 // 2201 // Register: PRCM_O_RAMRETEN 2202 // 2203 //***************************************************************************** 2204 // Field: [3] RFCULL 2205 // 2206 // 0: Retention for RFC ULL SRAM disabled 2207 // 1: Retention for RFC ULL SRAM enabled 2208 // 2209 // Memories controlled: 2210 // CPEULLRAM 2211 #define PRCM_RAMRETEN_RFCULL 0x00000008 2212 #define PRCM_RAMRETEN_RFCULL_BITN 3 2213 #define PRCM_RAMRETEN_RFCULL_M 0x00000008 2214 #define PRCM_RAMRETEN_RFCULL_S 3 2215 2216 // Field: [2] RFC 2217 // 2218 // 0: Retention for RFC SRAM disabled 2219 // 1: Retention for RFC SRAM enabled 2220 // 2221 // Memories controlled: CPERAM MCERAM RFERAM DSBRAM 2222 #define PRCM_RAMRETEN_RFC 0x00000004 2223 #define PRCM_RAMRETEN_RFC_BITN 2 2224 #define PRCM_RAMRETEN_RFC_M 0x00000004 2225 #define PRCM_RAMRETEN_RFC_S 2 2226 2227 // Field: [1:0] VIMS 2228 // 2229 // 2230 // 0: Memory retention disabled 2231 // 1: Memory retention enabled 2232 // 2233 // Bit 0: VIMS_TRAM 2234 // Bit 1: VIMS_CRAM 2235 // 2236 // Legal modes depend on settings in VIMS:CTL.MODE 2237 // 2238 // 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to 2239 // CACHE or SPLIT mode after waking up again 2240 // 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in 2241 // GPRAM mode after wake up, alternatively select OFF mode first and then CACHE 2242 // or SPILT mode. 2243 // 10: Illegal mode 2244 // 11: No restrictions 2245 #define PRCM_RAMRETEN_VIMS_W 2 2246 #define PRCM_RAMRETEN_VIMS_M 0x00000003 2247 #define PRCM_RAMRETEN_VIMS_S 0 2248 2249 //***************************************************************************** 2250 // 2251 // Register: PRCM_O_OSCIMSC 2252 // 2253 //***************************************************************************** 2254 // Field: [7] HFSRCPENDIM 2255 // 2256 // 0: Disable interrupt generation when HFSRCPEND is qualified 2257 // 1: Enable interrupt generation when HFSRCPEND is qualified 2258 #define PRCM_OSCIMSC_HFSRCPENDIM 0x00000080 2259 #define PRCM_OSCIMSC_HFSRCPENDIM_BITN 7 2260 #define PRCM_OSCIMSC_HFSRCPENDIM_M 0x00000080 2261 #define PRCM_OSCIMSC_HFSRCPENDIM_S 7 2262 2263 // Field: [6] LFSRCDONEIM 2264 // 2265 // 0: Disable interrupt generation when LFSRCDONE is qualified 2266 // 1: Enable interrupt generation when LFSRCDONE is qualified 2267 #define PRCM_OSCIMSC_LFSRCDONEIM 0x00000040 2268 #define PRCM_OSCIMSC_LFSRCDONEIM_BITN 6 2269 #define PRCM_OSCIMSC_LFSRCDONEIM_M 0x00000040 2270 #define PRCM_OSCIMSC_LFSRCDONEIM_S 6 2271 2272 // Field: [5] XOSCDLFIM 2273 // 2274 // 0: Disable interrupt generation when XOSCDLF is qualified 2275 // 1: Enable interrupt generation when XOSCDLF is qualified 2276 #define PRCM_OSCIMSC_XOSCDLFIM 0x00000020 2277 #define PRCM_OSCIMSC_XOSCDLFIM_BITN 5 2278 #define PRCM_OSCIMSC_XOSCDLFIM_M 0x00000020 2279 #define PRCM_OSCIMSC_XOSCDLFIM_S 5 2280 2281 // Field: [4] XOSCLFIM 2282 // 2283 // 0: Disable interrupt generation when XOSCLF is qualified 2284 // 1: Enable interrupt generation when XOSCLF is qualified 2285 #define PRCM_OSCIMSC_XOSCLFIM 0x00000010 2286 #define PRCM_OSCIMSC_XOSCLFIM_BITN 4 2287 #define PRCM_OSCIMSC_XOSCLFIM_M 0x00000010 2288 #define PRCM_OSCIMSC_XOSCLFIM_S 4 2289 2290 // Field: [3] RCOSCDLFIM 2291 // 2292 // 0: Disable interrupt generation when RCOSCDLF is qualified 2293 // 1: Enable interrupt generation when RCOSCDLF is qualified 2294 #define PRCM_OSCIMSC_RCOSCDLFIM 0x00000008 2295 #define PRCM_OSCIMSC_RCOSCDLFIM_BITN 3 2296 #define PRCM_OSCIMSC_RCOSCDLFIM_M 0x00000008 2297 #define PRCM_OSCIMSC_RCOSCDLFIM_S 3 2298 2299 // Field: [2] RCOSCLFIM 2300 // 2301 // 0: Disable interrupt generation when RCOSCLF is qualified 2302 // 1: Enable interrupt generation when RCOSCLF is qualified 2303 #define PRCM_OSCIMSC_RCOSCLFIM 0x00000004 2304 #define PRCM_OSCIMSC_RCOSCLFIM_BITN 2 2305 #define PRCM_OSCIMSC_RCOSCLFIM_M 0x00000004 2306 #define PRCM_OSCIMSC_RCOSCLFIM_S 2 2307 2308 // Field: [1] XOSCHFIM 2309 // 2310 // 0: Disable interrupt generation when XOSCHF is qualified 2311 // 1: Enable interrupt generation when XOSCHF is qualified 2312 #define PRCM_OSCIMSC_XOSCHFIM 0x00000002 2313 #define PRCM_OSCIMSC_XOSCHFIM_BITN 1 2314 #define PRCM_OSCIMSC_XOSCHFIM_M 0x00000002 2315 #define PRCM_OSCIMSC_XOSCHFIM_S 1 2316 2317 // Field: [0] RCOSCHFIM 2318 // 2319 // 0: Disable interrupt generation when RCOSCHF is qualified 2320 // 1: Enable interrupt generation when RCOSCHF is qualified 2321 #define PRCM_OSCIMSC_RCOSCHFIM 0x00000001 2322 #define PRCM_OSCIMSC_RCOSCHFIM_BITN 0 2323 #define PRCM_OSCIMSC_RCOSCHFIM_M 0x00000001 2324 #define PRCM_OSCIMSC_RCOSCHFIM_S 0 2325 2326 //***************************************************************************** 2327 // 2328 // Register: PRCM_O_OSCRIS 2329 // 2330 //***************************************************************************** 2331 // Field: [7] HFSRCPENDRIS 2332 // 2333 // 0: HFSRCPEND has not been qualified 2334 // 1: HFSRCPEND has been qualified since last clear 2335 // 2336 // Interrupt is qualified regardless of OSCIMSC.HFSRCPENDIM setting. The order 2337 // of qualifying raw interrupt and enable of interrupt mask is indifferent for 2338 // generating an OSC Interrupt. 2339 // 2340 // Set by HW. Cleared by writing to OSCICR.HFSRCPENDC 2341 #define PRCM_OSCRIS_HFSRCPENDRIS 0x00000080 2342 #define PRCM_OSCRIS_HFSRCPENDRIS_BITN 7 2343 #define PRCM_OSCRIS_HFSRCPENDRIS_M 0x00000080 2344 #define PRCM_OSCRIS_HFSRCPENDRIS_S 7 2345 2346 // Field: [6] LFSRCDONERIS 2347 // 2348 // 0: LFSRCDONE has not been qualified 2349 // 1: LFSRCDONE has been qualified since last clear 2350 // 2351 // Interrupt is qualified regardless of OSCIMSC.LFSRCDONEIM setting. The order 2352 // of qualifying raw interrupt and enable of interrupt mask is indifferent for 2353 // generating an OSC Interrupt. 2354 // 2355 // Set by HW. Cleared by writing to OSCICR.LFSRCDONEC 2356 #define PRCM_OSCRIS_LFSRCDONERIS 0x00000040 2357 #define PRCM_OSCRIS_LFSRCDONERIS_BITN 6 2358 #define PRCM_OSCRIS_LFSRCDONERIS_M 0x00000040 2359 #define PRCM_OSCRIS_LFSRCDONERIS_S 6 2360 2361 // Field: [5] XOSCDLFRIS 2362 // 2363 // 0: XOSCDLF has not been qualified 2364 // 1: XOSCDLF has been qualified since last clear. 2365 // 2366 // Interrupt is qualified regardless of OSCIMSC.XOSCDLFIM setting. The order of 2367 // qualifying raw interrupt and enable of interrupt mask is indifferent for 2368 // generating an OSC Interrupt. 2369 // 2370 // Set by HW. Cleared by writing to OSCICR.XOSCDLFC 2371 #define PRCM_OSCRIS_XOSCDLFRIS 0x00000020 2372 #define PRCM_OSCRIS_XOSCDLFRIS_BITN 5 2373 #define PRCM_OSCRIS_XOSCDLFRIS_M 0x00000020 2374 #define PRCM_OSCRIS_XOSCDLFRIS_S 5 2375 2376 // Field: [4] XOSCLFRIS 2377 // 2378 // 0: XOSCLF has not been qualified 2379 // 1: XOSCLF has been qualified since last clear. 2380 // 2381 // Interrupt is qualified regardless of OSCIMSC.XOSCLFIM setting. The order of 2382 // qualifying raw interrupt and enable of interrupt mask is indifferent for 2383 // generating an OSC Interrupt. 2384 // 2385 // Set by HW. Cleared by writing to OSCICR.XOSCLFC 2386 #define PRCM_OSCRIS_XOSCLFRIS 0x00000010 2387 #define PRCM_OSCRIS_XOSCLFRIS_BITN 4 2388 #define PRCM_OSCRIS_XOSCLFRIS_M 0x00000010 2389 #define PRCM_OSCRIS_XOSCLFRIS_S 4 2390 2391 // Field: [3] RCOSCDLFRIS 2392 // 2393 // 0: RCOSCDLF has not been qualified 2394 // 1: RCOSCDLF has been qualified since last clear. 2395 // 2396 // Interrupt is qualified regardless of OSCIMSC.RCOSCDLFIM setting. The order 2397 // of qualifying raw interrupt and enable of interrupt mask is indifferent for 2398 // generating an OSC Interrupt. 2399 // 2400 // Set by HW. Cleared by writing to OSCICR.RCOSCDLFC 2401 #define PRCM_OSCRIS_RCOSCDLFRIS 0x00000008 2402 #define PRCM_OSCRIS_RCOSCDLFRIS_BITN 3 2403 #define PRCM_OSCRIS_RCOSCDLFRIS_M 0x00000008 2404 #define PRCM_OSCRIS_RCOSCDLFRIS_S 3 2405 2406 // Field: [2] RCOSCLFRIS 2407 // 2408 // 0: RCOSCLF has not been qualified 2409 // 1: RCOSCLF has been qualified since last clear. 2410 // 2411 // Interrupt is qualified regardless of OSCIMSC.RCOSCLFIM setting. The order of 2412 // qualifying raw interrupt and enable of interrupt mask is indifferent for 2413 // generating an OSC Interrupt. 2414 // 2415 // Set by HW. Cleared by writing to OSCICR.RCOSCLFC 2416 #define PRCM_OSCRIS_RCOSCLFRIS 0x00000004 2417 #define PRCM_OSCRIS_RCOSCLFRIS_BITN 2 2418 #define PRCM_OSCRIS_RCOSCLFRIS_M 0x00000004 2419 #define PRCM_OSCRIS_RCOSCLFRIS_S 2 2420 2421 // Field: [1] XOSCHFRIS 2422 // 2423 // 0: XOSCHF has not been qualified 2424 // 1: XOSCHF has been qualified since last clear. 2425 // 2426 // Interrupt is qualified regardless of OSCIMSC.XOSCHFIM setting. The order of 2427 // qualifying raw interrupt and enable of interrupt mask is indifferent for 2428 // generating an OSC Interrupt. 2429 // 2430 // Set by HW. Cleared by writing to OSCICR.XOSCHFC 2431 #define PRCM_OSCRIS_XOSCHFRIS 0x00000002 2432 #define PRCM_OSCRIS_XOSCHFRIS_BITN 1 2433 #define PRCM_OSCRIS_XOSCHFRIS_M 0x00000002 2434 #define PRCM_OSCRIS_XOSCHFRIS_S 1 2435 2436 // Field: [0] RCOSCHFRIS 2437 // 2438 // 0: RCOSCHF has not been qualified 2439 // 1: RCOSCHF has been qualified since last clear. 2440 // 2441 // Interrupt is qualified regardless of OSCIMSC.RCOSCHFIM setting. The order of 2442 // qualifying raw interrupt and enable of interrupt mask is indifferent for 2443 // generating an OSC Interrupt. 2444 // 2445 // Set by HW. Cleared by writing to OSCICR.RCOSCHFC 2446 #define PRCM_OSCRIS_RCOSCHFRIS 0x00000001 2447 #define PRCM_OSCRIS_RCOSCHFRIS_BITN 0 2448 #define PRCM_OSCRIS_RCOSCHFRIS_M 0x00000001 2449 #define PRCM_OSCRIS_RCOSCHFRIS_S 0 2450 2451 //***************************************************************************** 2452 // 2453 // Register: PRCM_O_OSCICR 2454 // 2455 //***************************************************************************** 2456 // Field: [7] HFSRCPENDC 2457 // 2458 // Writing 1 to this field clears the HFSRCPEND raw interrupt status. Writing 0 2459 // has no effect. 2460 #define PRCM_OSCICR_HFSRCPENDC 0x00000080 2461 #define PRCM_OSCICR_HFSRCPENDC_BITN 7 2462 #define PRCM_OSCICR_HFSRCPENDC_M 0x00000080 2463 #define PRCM_OSCICR_HFSRCPENDC_S 7 2464 2465 // Field: [6] LFSRCDONEC 2466 // 2467 // Writing 1 to this field clears the LFSRCDONE raw interrupt status. Writing 0 2468 // has no effect. 2469 #define PRCM_OSCICR_LFSRCDONEC 0x00000040 2470 #define PRCM_OSCICR_LFSRCDONEC_BITN 6 2471 #define PRCM_OSCICR_LFSRCDONEC_M 0x00000040 2472 #define PRCM_OSCICR_LFSRCDONEC_S 6 2473 2474 // Field: [5] XOSCDLFC 2475 // 2476 // Writing 1 to this field clears the XOSCDLF raw interrupt status. Writing 0 2477 // has no effect. 2478 #define PRCM_OSCICR_XOSCDLFC 0x00000020 2479 #define PRCM_OSCICR_XOSCDLFC_BITN 5 2480 #define PRCM_OSCICR_XOSCDLFC_M 0x00000020 2481 #define PRCM_OSCICR_XOSCDLFC_S 5 2482 2483 // Field: [4] XOSCLFC 2484 // 2485 // Writing 1 to this field clears the XOSCLF raw interrupt status. Writing 0 2486 // has no effect. 2487 #define PRCM_OSCICR_XOSCLFC 0x00000010 2488 #define PRCM_OSCICR_XOSCLFC_BITN 4 2489 #define PRCM_OSCICR_XOSCLFC_M 0x00000010 2490 #define PRCM_OSCICR_XOSCLFC_S 4 2491 2492 // Field: [3] RCOSCDLFC 2493 // 2494 // Writing 1 to this field clears the RCOSCDLF raw interrupt status. Writing 0 2495 // has no effect. 2496 #define PRCM_OSCICR_RCOSCDLFC 0x00000008 2497 #define PRCM_OSCICR_RCOSCDLFC_BITN 3 2498 #define PRCM_OSCICR_RCOSCDLFC_M 0x00000008 2499 #define PRCM_OSCICR_RCOSCDLFC_S 3 2500 2501 // Field: [2] RCOSCLFC 2502 // 2503 // Writing 1 to this field clears the RCOSCLF raw interrupt status. Writing 0 2504 // has no effect. 2505 #define PRCM_OSCICR_RCOSCLFC 0x00000004 2506 #define PRCM_OSCICR_RCOSCLFC_BITN 2 2507 #define PRCM_OSCICR_RCOSCLFC_M 0x00000004 2508 #define PRCM_OSCICR_RCOSCLFC_S 2 2509 2510 // Field: [1] XOSCHFC 2511 // 2512 // Writing 1 to this field clears the XOSCHF raw interrupt status. Writing 0 2513 // has no effect. 2514 #define PRCM_OSCICR_XOSCHFC 0x00000002 2515 #define PRCM_OSCICR_XOSCHFC_BITN 1 2516 #define PRCM_OSCICR_XOSCHFC_M 0x00000002 2517 #define PRCM_OSCICR_XOSCHFC_S 1 2518 2519 // Field: [0] RCOSCHFC 2520 // 2521 // Writing 1 to this field clears the RCOSCHF raw interrupt status. Writing 0 2522 // has no effect. 2523 #define PRCM_OSCICR_RCOSCHFC 0x00000001 2524 #define PRCM_OSCICR_RCOSCHFC_BITN 0 2525 #define PRCM_OSCICR_RCOSCHFC_M 0x00000001 2526 #define PRCM_OSCICR_RCOSCHFC_S 0 2527 2528 2529 #endif // __PRCM__ 2530
