1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_OCP_SHARED_H__ 35 #define __HW_OCP_SHARED_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the OCP_SHARED register offsets. 40 // 41 //***************************************************************************** 42 #define OCP_SHARED_O_SEMAPHORE1 0x00000000 43 #define OCP_SHARED_O_SEMAPHORE2 0x00000004 44 #define OCP_SHARED_O_SEMAPHORE3 0x00000008 45 #define OCP_SHARED_O_SEMAPHORE4 0x0000000C 46 #define OCP_SHARED_O_SEMAPHORE5 0x00000010 47 #define OCP_SHARED_O_SEMAPHORE6 0x00000014 48 #define OCP_SHARED_O_SEMAPHORE7 0x00000018 49 #define OCP_SHARED_O_SEMAPHORE8 0x0000001C 50 #define OCP_SHARED_O_SEMAPHORE9 0x00000020 51 #define OCP_SHARED_O_SEMAPHORE10 \ 52 0x00000024 53 54 #define OCP_SHARED_O_SEMAPHORE11 \ 55 0x00000028 56 57 #define OCP_SHARED_O_SEMAPHORE12 \ 58 0x0000002C 59 60 #define OCP_SHARED_O_IC_LOCKER_ID \ 61 0x00000030 62 63 #define OCP_SHARED_O_MCU_SEMAPHORE_PEND \ 64 0x00000034 65 66 #define OCP_SHARED_O_WL_SEMAPHORE_PEND \ 67 0x00000038 68 69 #define OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY \ 70 0x0000003C 71 72 #define OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY \ 73 0x00000040 74 75 #define OCP_SHARED_O_CC3XX_CONFIG_CTRL \ 76 0x00000044 77 78 #define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB \ 79 0x00000048 80 81 #define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB \ 82 0x0000004C 83 84 #define OCP_SHARED_O_WLAN_ELP_WAKE_EN \ 85 0x00000050 86 87 #define OCP_SHARED_O_DEVINIT_ROM_START_ADDR \ 88 0x00000054 89 90 #define OCP_SHARED_O_DEVINIT_ROM_END_ADDR \ 91 0x00000058 92 93 #define OCP_SHARED_O_SSBD_SEED 0x0000005C 94 #define OCP_SHARED_O_SSBD_CHK 0x00000060 95 #define OCP_SHARED_O_SSBD_POLY_SEL \ 96 0x00000064 97 98 #define OCP_SHARED_O_SPARE_REG_0 \ 99 0x00000068 100 101 #define OCP_SHARED_O_SPARE_REG_1 \ 102 0x0000006C 103 104 #define OCP_SHARED_O_SPARE_REG_2 \ 105 0x00000070 106 107 #define OCP_SHARED_O_SPARE_REG_3 \ 108 0x00000074 109 110 #define OCP_SHARED_O_GPIO_PAD_CONFIG_0 \ 111 0x000000A0 112 113 #define OCP_SHARED_O_GPIO_PAD_CONFIG_1 \ 114 0x000000A4 115 116 #define OCP_SHARED_O_GPIO_PAD_CONFIG_2 \ 117 0x000000A8 118 119 #define OCP_SHARED_O_GPIO_PAD_CONFIG_3 \ 120 0x000000AC 121 122 #define OCP_SHARED_O_GPIO_PAD_CONFIG_4 \ 123 0x000000B0 124 125 #define OCP_SHARED_O_GPIO_PAD_CONFIG_5 \ 126 0x000000B4 127 128 #define OCP_SHARED_O_GPIO_PAD_CONFIG_6 \ 129 0x000000B8 130 131 #define OCP_SHARED_O_GPIO_PAD_CONFIG_7 \ 132 0x000000BC 133 134 #define OCP_SHARED_O_GPIO_PAD_CONFIG_8 \ 135 0x000000C0 136 137 #define OCP_SHARED_O_GPIO_PAD_CONFIG_9 \ 138 0x000000C4 139 140 #define OCP_SHARED_O_GPIO_PAD_CONFIG_10 \ 141 0x000000C8 142 143 #define OCP_SHARED_O_GPIO_PAD_CONFIG_11 \ 144 0x000000CC 145 146 #define OCP_SHARED_O_GPIO_PAD_CONFIG_12 \ 147 0x000000D0 148 149 #define OCP_SHARED_O_GPIO_PAD_CONFIG_13 \ 150 0x000000D4 151 152 #define OCP_SHARED_O_GPIO_PAD_CONFIG_14 \ 153 0x000000D8 154 155 #define OCP_SHARED_O_GPIO_PAD_CONFIG_15 \ 156 0x000000DC 157 158 #define OCP_SHARED_O_GPIO_PAD_CONFIG_16 \ 159 0x000000E0 160 161 #define OCP_SHARED_O_GPIO_PAD_CONFIG_17 \ 162 0x000000E4 163 164 #define OCP_SHARED_O_GPIO_PAD_CONFIG_18 \ 165 0x000000E8 166 167 #define OCP_SHARED_O_GPIO_PAD_CONFIG_19 \ 168 0x000000EC 169 170 #define OCP_SHARED_O_GPIO_PAD_CONFIG_20 \ 171 0x000000F0 172 173 #define OCP_SHARED_O_GPIO_PAD_CONFIG_21 \ 174 0x000000F4 175 176 #define OCP_SHARED_O_GPIO_PAD_CONFIG_22 \ 177 0x000000F8 178 179 #define OCP_SHARED_O_GPIO_PAD_CONFIG_23 \ 180 0x000000FC 181 182 #define OCP_SHARED_O_GPIO_PAD_CONFIG_24 \ 183 0x00000100 184 185 #define OCP_SHARED_O_GPIO_PAD_CONFIG_25 \ 186 0x00000104 187 188 #define OCP_SHARED_O_GPIO_PAD_CONFIG_26 \ 189 0x00000108 190 191 #define OCP_SHARED_O_GPIO_PAD_CONFIG_27 \ 192 0x0000010C 193 194 #define OCP_SHARED_O_GPIO_PAD_CONFIG_28 \ 195 0x00000110 196 197 #define OCP_SHARED_O_GPIO_PAD_CONFIG_29 \ 198 0x00000114 199 200 #define OCP_SHARED_O_GPIO_PAD_CONFIG_30 \ 201 0x00000118 202 203 #define OCP_SHARED_O_GPIO_PAD_CONFIG_31 \ 204 0x0000011C 205 206 #define OCP_SHARED_O_GPIO_PAD_CONFIG_32 \ 207 0x00000120 208 209 #define OCP_SHARED_O_GPIO_PAD_CONFIG_33 \ 210 0x00000124 211 212 #define OCP_SHARED_O_GPIO_PAD_CONFIG_34 \ 213 0x00000128 214 215 #define OCP_SHARED_O_GPIO_PAD_CONFIG_35 \ 216 0x0000012C 217 218 #define OCP_SHARED_O_GPIO_PAD_CONFIG_36 \ 219 0x00000130 220 221 #define OCP_SHARED_O_GPIO_PAD_CONFIG_37 \ 222 0x00000134 223 224 #define OCP_SHARED_O_GPIO_PAD_CONFIG_38 \ 225 0x00000138 226 227 #define OCP_SHARED_O_GPIO_PAD_CONFIG_39 \ 228 0x0000013C 229 230 #define OCP_SHARED_O_GPIO_PAD_CONFIG_40 \ 231 0x00000140 232 233 #define OCP_SHARED_O_GPIO_PAD_CMN_CONFIG \ 234 0x00000144 // This register provide control to 235 // GPIO_CC3XXV1 IO PAD. Common 236 // control signals to all bottom Die 237 // IO's are controlled via this. 238 239 #define OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG \ 240 0x00000148 241 242 #define OCP_SHARED_O_D2D_TOSTACK_PAD_CONF \ 243 0x0000014C 244 245 #define OCP_SHARED_O_D2D_MISC_PAD_CONF \ 246 0x00000150 247 248 #define OCP_SHARED_O_SOP_CONF_OVERRIDE \ 249 0x00000154 250 251 #define OCP_SHARED_O_CC3XX_DEBUGSS_STATUS \ 252 0x00000158 253 254 #define OCP_SHARED_O_CC3XX_DEBUGMUX_SEL \ 255 0x0000015C 256 257 #define OCP_SHARED_O_ALT_PC_VAL_NW \ 258 0x00000160 259 260 #define OCP_SHARED_O_ALT_PC_VAL_APPS \ 261 0x00000164 262 263 #define OCP_SHARED_O_SPARE_REG_4 \ 264 0x00000168 265 266 #define OCP_SHARED_O_SPARE_REG_5 \ 267 0x0000016C 268 269 #define OCP_SHARED_O_SH_SPI_CS_MASK \ 270 0x00000170 271 272 #define OCP_SHARED_O_CC3XX_DEVICE_TYPE \ 273 0x00000174 274 275 #define OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE \ 276 0x00000178 277 278 #define OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT \ 279 0x0000017C 280 281 #define OCP_SHARED_O_AUTONMS_SPICLK_SEL \ 282 0x00000180 283 284 #define OCP_SHARED_O_CC3XX_DEV_PADCONF \ 285 0x00000184 286 287 #define OCP_SHARED_O_SPARE_REG_8 \ 288 0x00000188 289 290 #define OCP_SHARED_O_SPARE_REG_6 \ 291 0x0000018C 292 293 #define OCP_SHARED_O_SPARE_REG_7 \ 294 0x00000190 295 296 #define OCP_SHARED_O_APPS_WLAN_ORBIT \ 297 0x00000194 298 299 #define OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD \ 300 0x00000198 301 302 303 304 305 //****************************************************************************** 306 // 307 // The following are defines for the bit fields in the 308 // OCP_SHARED_O_SEMAPHORE1 register. 309 // 310 //****************************************************************************** 311 #define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_M \ 312 0x00000003 // General Purpose Semaphore for SW 313 // Usage. If any of the 2 bits of a 314 // given register is set to 1, it 315 // means that the semaphore is 316 // locked by one of the masters. 317 // Each bit represents a master IP 318 // as follows: {WLAN,NWP}. The JTAG 319 // cannot capture the semaphore but 320 // it can release it. As a master IP 321 // reads the semaphore, it will be 322 // caputed and the masters 323 // correlating bit will be set to 1 324 // (set upon read). As any IP writes 325 // to this address (independent of 326 // the written data) the semaphore 327 // will be set to 2'b00. 328 329 #define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_S 0 330 //****************************************************************************** 331 // 332 // The following are defines for the bit fields in the 333 // OCP_SHARED_O_SEMAPHORE2 register. 334 // 335 //****************************************************************************** 336 #define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_M \ 337 0x00000003 // General Purpose Semaphore for SW 338 // Usage. If any of the 2 bits of a 339 // given register is set to 1, it 340 // means that the semaphore is 341 // locked by one of the masters. 342 // Each bit represents a master IP 343 // as follows: {WLAN,NWP}. The JTAG 344 // cannot capture the semaphore but 345 // it can release it. As a master IP 346 // reads the semaphore, it will be 347 // caputed and the masters 348 // correlating bit will be set to 1 349 // (set upon read). As any IP writes 350 // to this address (independent of 351 // the written data) the semaphore 352 // will be set to 2'b00. 353 354 #define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_S 0 355 //****************************************************************************** 356 // 357 // The following are defines for the bit fields in the 358 // OCP_SHARED_O_SEMAPHORE3 register. 359 // 360 //****************************************************************************** 361 #define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_M \ 362 0x00000003 // General Purpose Semaphore for SW 363 // Usage. If any of the 2 bits of a 364 // given register is set to 1, it 365 // means that the semaphore is 366 // locked by one of the masters. 367 // Each bit represents a master IP 368 // as follows: {WLAN,NWP}. The JTAG 369 // cannot capture the semaphore but 370 // it can release it. As a master IP 371 // reads the semaphore, it will be 372 // caputed and the masters 373 // correlating bit will be set to 1 374 // (set upon read). As any IP writes 375 // to this address (independent of 376 // the written data) the semaphore 377 // will be set to 2'b00. 378 379 #define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_S 0 380 //****************************************************************************** 381 // 382 // The following are defines for the bit fields in the 383 // OCP_SHARED_O_SEMAPHORE4 register. 384 // 385 //****************************************************************************** 386 #define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_M \ 387 0x00000003 // General Purpose Semaphore for SW 388 // Usage. If any of the 2 bits of a 389 // given register is set to 1, it 390 // means that the semaphore is 391 // locked by one of the masters. 392 // Each bit represents a master IP 393 // as follows: {WLAN,NWP}. The JTAG 394 // cannot capture the semaphore but 395 // it can release it. As a master IP 396 // reads the semaphore, it will be 397 // caputed and the masters 398 // correlating bit will be set to 1 399 // (set upon read). As any IP writes 400 // to this address (independent of 401 // the written data) the semaphore 402 // will be set to 2'b00. 403 404 #define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_S 0 405 //****************************************************************************** 406 // 407 // The following are defines for the bit fields in the 408 // OCP_SHARED_O_SEMAPHORE5 register. 409 // 410 //****************************************************************************** 411 #define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_M \ 412 0x00000003 // General Purpose Semaphore for SW 413 // Usage. If any of the 2 bits of a 414 // given register is set to 1, it 415 // means that the semaphore is 416 // locked by one of the masters. 417 // Each bit represents a master IP 418 // as follows: {WLAN,NWP}. The JTAG 419 // cannot capture the semaphore but 420 // it can release it. As a master IP 421 // reads the semaphore, it will be 422 // caputed and the masters 423 // correlating bit will be set to 1 424 // (set upon read). As any IP writes 425 // to this address (independent of 426 // the written data) the semaphore 427 // will be set to 2'b00. 428 429 #define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_S 0 430 //****************************************************************************** 431 // 432 // The following are defines for the bit fields in the 433 // OCP_SHARED_O_SEMAPHORE6 register. 434 // 435 //****************************************************************************** 436 #define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_M \ 437 0x00000003 // General Purpose Semaphore for SW 438 // Usage. If any of the 2 bits of a 439 // given register is set to 1, it 440 // means that the semaphore is 441 // locked by one of the masters. 442 // Each bit represents a master IP 443 // as follows: {WLAN,NWP}. The JTAG 444 // cannot capture the semaphore but 445 // it can release it. As a master IP 446 // reads the semaphore, it will be 447 // caputed and the masters 448 // correlating bit will be set to 1 449 // (set upon read). As any IP writes 450 // to this address (independent of 451 // the written data) the semaphore 452 // will be set to 2'b00. 453 454 #define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_S 0 455 //****************************************************************************** 456 // 457 // The following are defines for the bit fields in the 458 // OCP_SHARED_O_SEMAPHORE7 register. 459 // 460 //****************************************************************************** 461 #define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_M \ 462 0x00000003 // General Purpose Semaphore for SW 463 // Usage. If any of the 2 bits of a 464 // given register is set to 1, it 465 // means that the semaphore is 466 // locked by one of the masters. 467 // Each bit represents a master IP 468 // as follows: {WLAN,NWP}. The JTAG 469 // cannot capture the semaphore but 470 // it can release it. As a master IP 471 // reads the semaphore, it will be 472 // caputed and the masters 473 // correlating bit will be set to 1 474 // (set upon read). As any IP writes 475 // to this address (independent of 476 // the written data) the semaphore 477 // will be set to 2'b00. 478 479 #define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_S 0 480 //****************************************************************************** 481 // 482 // The following are defines for the bit fields in the 483 // OCP_SHARED_O_SEMAPHORE8 register. 484 // 485 //****************************************************************************** 486 #define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_M \ 487 0x00000003 // General Purpose Semaphore for SW 488 // Usage. If any of the 2 bits of a 489 // given register is set to 1, it 490 // means that the semaphore is 491 // locked by one of the masters. 492 // Each bit represents a master IP 493 // as follows: {WLAN,NWP}. The JTAG 494 // cannot capture the semaphore but 495 // it can release it. As a master IP 496 // reads the semaphore, it will be 497 // caputed and the masters 498 // correlating bit will be set to 1 499 // (set upon read). As any IP writes 500 // to this address (independent of 501 // the written data) the semaphore 502 // will be set to 2'b00. 503 504 #define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_S 0 505 //****************************************************************************** 506 // 507 // The following are defines for the bit fields in the 508 // OCP_SHARED_O_SEMAPHORE9 register. 509 // 510 //****************************************************************************** 511 #define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_M \ 512 0x00000003 // General Purpose Semaphore for SW 513 // Usage. If any of the 2 bits of a 514 // given register is set to 1, it 515 // means that the semaphore is 516 // locked by one of the masters. 517 // Each bit represents a master IP 518 // as follows: {WLAN,NWP}. The JTAG 519 // cannot capture the semaphore but 520 // it can release it. As a master IP 521 // reads the semaphore, it will be 522 // caputed and the masters 523 // correlating bit will be set to 1 524 // (set upon read). As any IP writes 525 // to this address (independent of 526 // the written data) the semaphore 527 // will be set to 2'b00. 528 529 #define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_S 0 530 //****************************************************************************** 531 // 532 // The following are defines for the bit fields in the 533 // OCP_SHARED_O_SEMAPHORE10 register. 534 // 535 //****************************************************************************** 536 #define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_M \ 537 0x00000003 // General Purpose Semaphore for SW 538 // Usage. If any of the 2 bits of a 539 // given register is set to 1, it 540 // means that the semaphore is 541 // locked by one of the masters. 542 // Each bit represents a master IP 543 // as follows: {WLAN,NWP}. The JTAG 544 // cannot capture the semaphore but 545 // it can release it. As a master IP 546 // reads the semaphore, it will be 547 // caputed and the masters 548 // correlating bit will be set to 1 549 // (set upon read). As any IP writes 550 // to this address (independent of 551 // the written data) the semaphore 552 // will be set to 2'b00. 553 554 #define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_S 0 555 //****************************************************************************** 556 // 557 // The following are defines for the bit fields in the 558 // OCP_SHARED_O_SEMAPHORE11 register. 559 // 560 //****************************************************************************** 561 #define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_M \ 562 0x00000003 // General Purpose Semaphore for SW 563 // Usage. If any of the 2 bits of a 564 // given register is set to 1, it 565 // means that the semaphore is 566 // locked by one of the masters. 567 // Each bit represents a master IP 568 // as follows: {WLAN,NWP}. The JTAG 569 // cannot capture the semaphore but 570 // it can release it. As a master IP 571 // reads the semaphore, it will be 572 // caputed and the masters 573 // correlating bit will be set to 1 574 // (set upon read). As any IP writes 575 // to this address (independent of 576 // the written data) the semaphore 577 // will be set to 2'b00. 578 579 #define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_S 0 580 //****************************************************************************** 581 // 582 // The following are defines for the bit fields in the 583 // OCP_SHARED_O_SEMAPHORE12 register. 584 // 585 //****************************************************************************** 586 #define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_M \ 587 0x00000003 // General Purpose Semaphore for SW 588 // Usage. If any of the 2 bits of a 589 // given register is set to 1, it 590 // means that the semaphore is 591 // locked by one of the masters. 592 // Each bit represents a master IP 593 // as follows: {WLAN,NWP}. The JTAG 594 // cannot capture the semaphore but 595 // it can release it. As a master IP 596 // reads the semaphore, it will be 597 // caputed and the masters 598 // correlating bit will be set to 1 599 // (set upon read). As any IP writes 600 // to this address (independent of 601 // the written data) the semaphore 602 // will be set to 2'b00. 603 604 #define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_S 0 605 //****************************************************************************** 606 // 607 // The following are defines for the bit fields in the 608 // OCP_SHARED_O_IC_LOCKER_ID register. 609 // 610 //****************************************************************************** 611 #define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_M \ 612 0x00000007 // This register is used for 613 // allowing only one master OCP to 614 // perform write transactions to the 615 // OCP slaves. Each bit represents 616 // an IP in the following format: { 617 // JTAG,WLAN, NWP mcu}. As any of 618 // the bits is set to one, the 619 // correlating IP is preventing the 620 // other IP's from performing write 621 // transactions to the slaves. As 622 // the Inter Connect is locked, the 623 // only the locking IP can write to 624 // the register and by that 625 // releasing the lock. 3'b000 => IC 626 // is not locked. 3'b001 => IC is 627 // locked by NWP mcu. 3'b010 => IC 628 // is locked by WLAN. 3'b100 => IC 629 // is locked by JTAG. 630 631 #define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_S 0 632 //****************************************************************************** 633 // 634 // The following are defines for the bit fields in the 635 // OCP_SHARED_O_MCU_SEMAPHORE_PEND register. 636 // 637 //****************************************************************************** 638 #define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_M \ 639 0x0000FFFF // This register specifies the 640 // semaphore for which the NWP mcu 641 // is waiting to be released. It is 642 // set to the serial number of a 643 // given locked semaphore after it 644 // was read by the NWP mcu. Only 645 // [11:0] is used. 646 647 #define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_S 0 648 //****************************************************************************** 649 // 650 // The following are defines for the bit fields in the 651 // OCP_SHARED_O_WL_SEMAPHORE_PEND register. 652 // 653 //****************************************************************************** 654 #define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_M \ 655 0x0000FFFF // This register specifies the 656 // semaphore for which the WLAN is 657 // waiting to be released. It is set 658 // to the serial number of a given 659 // locked semaphore after it was 660 // read by the WLAN. Only [11:0] is 661 // used. 662 663 #define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_S 0 664 //****************************************************************************** 665 // 666 // The following are defines for the bit fields in the 667 // OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY register. 668 // 669 //****************************************************************************** 670 #define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_M \ 671 0x0000FFFF // This information serves the IPs 672 // for knowing in which platform are 673 // they integrated at: 0 = CC31XX. 674 675 #define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_S 0 676 //****************************************************************************** 677 // 678 // The following are defines for the bit fields in the 679 // OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY register. 680 // 681 //****************************************************************************** 682 #define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_M \ 683 0x00000FFF // Captured/released semaphores 684 // status for the 12 semaphores. 685 // Each bit of the 12 bits 686 // represents a semaphore. 0 => 687 // Semaphore Free. 1 => Semaphore 688 // Captured. 689 690 #define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_S 0 691 //****************************************************************************** 692 // 693 // The following are defines for the bit fields in the 694 // OCP_SHARED_O_CC3XX_CONFIG_CTRL register. 695 // 696 //****************************************************************************** 697 #define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_IC_TO_EN \ 698 0x00000010 // This bit is used to enable 699 // timeout mechanism for top_ocp_ic 700 // (for debug puropse). When 1 value 701 // , in case any ocp slave doesn't 702 // give sresponse within 16 cylcles 703 // top_ic will give error response 704 // itself to avoid bus hange. 705 706 #define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_APPS \ 707 0x00000008 // 1 bit should be accessible only 708 // in devinit. This will enable 0x4 709 // hack for apps processor 710 711 #define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_NW \ 712 0x00000004 // 1 bit, should be accessible only 713 // in devinit. This will enable 0x4 714 // hack for nw processor 715 716 #define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_EXTEND_NW_ROM \ 717 0x00000002 // When set NW can take over apps 718 // rom and flash via IDCODE bus. 719 // Apps will able to access this 720 // register only during devinit and 721 // reset value should be 0. 722 723 #define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_WLAN_HOST_INTF_SEL \ 724 0x00000001 // When this bit is set to 0 WPSI 725 // host interface wil be selected, 726 // when this bit is set to 1 , WLAN 727 // host async bridge will be 728 // selected. 729 730 //****************************************************************************** 731 // 732 // The following are defines for the bit fields in the 733 // OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB register. 734 // 735 //****************************************************************************** 736 #define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_M \ 737 0x3FFFFFFF // This register provides memss RAM 738 // column configuration for column 0 739 // to 9. 3 bits are allocated per 740 // column. This register is required 741 // to be configured before starting 742 // RAM access. Changing register 743 // setting while code is running 744 // will result into unpredictable 745 // memory behaviour. Register is 746 // supported to configured ones 747 // after core is booted up. 3 bit 748 // encoding per column is as 749 // follows: when 000 : WLAN, 001: 750 // NWP, 010: APPS, 011: PHY, 100: 751 // OCLA column 0 select: bit [2:0] 752 // :when 000 -> WLAN,001 -> NWP,010 753 // -> APPS, 011 -> PHY, 100 -> OCLA 754 // column 1 select: bit [5:3] 755 // :column 2 select: bit [8 : 6]: 756 // column 3 select : bit [11: 9] 757 // column 4 select : bit [14:12] 758 // column 5 select : bit [17:15] 759 // column 6 select : bit [20:18] 760 // column 7 select : bit [23:21] 761 // column 8 select : bit [26:24] 762 // column 9 select : bit [29:27] 763 // column 10 select 764 765 #define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_S 0 766 //****************************************************************************** 767 // 768 // The following are defines for the bit fields in the 769 // OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB register. 770 // 771 //****************************************************************************** 772 #define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_M \ 773 0x00000FFF // This register provides memss RAM 774 // column configuration for column 775 // 10 to 15. 3 bits are allocated 776 // per column. This register is 777 // required to be configured before 778 // starting RAM access. Changing 779 // register setting while code is 780 // running will result into 781 // unpredictable memory behaviour. 782 // Register is supported to 783 // configured ones after core is 784 // booted up. 3 bit encoding per 785 // column is as follows: when 000 : 786 // WLAN, 001: NWP, 010: APPS, 011: 787 // PHY, 100: OCLA column 11 select : 788 // bit [2:0] column 12 select : bit 789 // [5:3] column 13 select : bit [8 : 790 // 6] column 14 select : 791 792 #define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_S 0 793 //****************************************************************************** 794 // 795 // The following are defines for the bit fields in the 796 // OCP_SHARED_O_WLAN_ELP_WAKE_EN register. 797 // 798 //****************************************************************************** 799 #define OCP_SHARED_WLAN_ELP_WAKE_EN_MEM_WLAN_ELP_WAKE_EN \ 800 0x00000001 // when '1' : signal will enabled 801 // ELP power doamin when '0': ELP is 802 // not powered up. 803 804 //****************************************************************************** 805 // 806 // The following are defines for the bit fields in the 807 // OCP_SHARED_O_DEVINIT_ROM_START_ADDR register. 808 // 809 //****************************************************************************** 810 #define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_M \ 811 0xFFFFFFFF // 32 bit, Writable only during 812 // devinit, and whole 32 bit should 813 // be output of the config register 814 // module. This register is not used 815 // , similar register availble in 816 // GPRCM space. 817 818 #define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_S 0 819 //****************************************************************************** 820 // 821 // The following are defines for the bit fields in the 822 // OCP_SHARED_O_DEVINIT_ROM_END_ADDR register. 823 // 824 //****************************************************************************** 825 #define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_M \ 826 0xFFFFFFFF // 32 bit, Writable only during 827 // devinit, and whole 32 bit should 828 // be output of the config register 829 // module. 830 831 #define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_S 0 832 //****************************************************************************** 833 // 834 // The following are defines for the bit fields in the 835 // OCP_SHARED_O_SSBD_SEED register. 836 // 837 //****************************************************************************** 838 #define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_M \ 839 0xFFFFFFFF // 32 bit, Writable only during 840 // devinit, and whole 32 bit should 841 // be output of the config register 842 // module. 843 844 #define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_S 0 845 //****************************************************************************** 846 // 847 // The following are defines for the bit fields in the 848 // OCP_SHARED_O_SSBD_CHK register. 849 // 850 //****************************************************************************** 851 #define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_M \ 852 0xFFFFFFFF // 32 bit, Writable only during 853 // devinit, and whole 32 bit should 854 // be output of the config register 855 // module. 856 857 #define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_S 0 858 //****************************************************************************** 859 // 860 // The following are defines for the bit fields in the 861 // OCP_SHARED_O_SSBD_POLY_SEL register. 862 // 863 //****************************************************************************** 864 #define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_M \ 865 0x00000003 // 2 bit, Writable only during 866 // devinit, and whole 2 bit should 867 // be output of the config register 868 // module. 869 870 #define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_S 0 871 //****************************************************************************** 872 // 873 // The following are defines for the bit fields in the 874 // OCP_SHARED_O_SPARE_REG_0 register. 875 // 876 //****************************************************************************** 877 #define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_M \ 878 0xFFFFFFFF // Devinit code should look for 879 // whether corresponding fuse is 880 // blown and if blown write to the 881 // 11th bit of this register to 882 // disable flshtst interface 883 884 #define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_S 0 885 //****************************************************************************** 886 // 887 // The following are defines for the bit fields in the 888 // OCP_SHARED_O_SPARE_REG_1 register. 889 // 890 //****************************************************************************** 891 #define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_M \ 892 0xFFFFFFFF // NWP Software register 893 894 #define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_S 0 895 //****************************************************************************** 896 // 897 // The following are defines for the bit fields in the 898 // OCP_SHARED_O_SPARE_REG_2 register. 899 // 900 //****************************************************************************** 901 #define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_M \ 902 0xFFFFFFFF // NWP Software register 903 904 #define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_S 0 905 //****************************************************************************** 906 // 907 // The following are defines for the bit fields in the 908 // OCP_SHARED_O_SPARE_REG_3 register. 909 // 910 //****************************************************************************** 911 #define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_M \ 912 0xFFFFFFFF // APPS Software register 913 914 #define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_S 0 915 //****************************************************************************** 916 // 917 // The following are defines for the bit fields in the 918 // OCP_SHARED_O_GPIO_PAD_CONFIG_0 register. 919 // 920 //****************************************************************************** 921 #define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_M \ 922 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 923 // used for PAD IO mode selection. 924 // io_register={ "" 0 => 925 // """"CONFMODE[0]"""""" "" 1 => 926 // """"CONFMODE[1]"""""" "" 2 => 927 // """"CONFMODE[2]"""""" "" 3 => 928 // """"CONFMODE[3]"""" 4 => 929 // """"IODEN"""" --> When level ‘1’ 930 // this disables the PMOS xtors of 931 // the output stages making them 932 // open-drain type." "For example in 933 // case of I2C Value gets latched at 934 // rising edge of RET33.""" """ 5 => 935 // """"I2MAEN"""" --> Level ‘1’ 936 // enables the approx 2mA output 937 // stage""" """ 6 => """"I4MAEN"""" 938 // --> Level ‘1’ enables the approx 939 // 4mA output stage""" """ 7 => 940 // """"I8MAEN"""" --> Level ‘1’ 941 // enables the approx 8mA output 942 // stage. Note: any drive strength 943 // between 2mA and 14mA can be 944 // obtained with combination of 2mA 945 // 4mA and 8mA.""" """ 8 => 946 // """"IWKPUEN"""" --> 10uA pull up 947 // (weak strength)""" """ 9 => 948 // """"IWKPDEN"""" --> 10uA pull 949 // down (weak strength)""" """ 10 => 950 // """"IOE_N"""" --> output enable 951 // value. level ‘0’ enables the IDO 952 // to PAD path. Else PAD is 953 // tristated (except for the PU/PD 954 // which are independent)." "Value 955 // gets latched at rising edge of 956 // RET33""" """ 11 =>"""" 957 // IOE_N_OV"""" --> output enable 958 // overirde. when bit is set to 959 // logic '1' IOE_N (bit 4) value 960 // will control IO IOE_N signal else 961 // IOE_N is control via selected HW 962 // logic. strong PULL UP and PULL 963 // Down control is disabled for all 964 // IO's. both controls are tied to 965 // logic level '0'. 966 967 #define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_S 0 968 //****************************************************************************** 969 // 970 // The following are defines for the bit fields in the 971 // OCP_SHARED_O_GPIO_PAD_CONFIG_1 register. 972 // 973 //****************************************************************************** 974 #define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_M \ 975 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 976 // used for PAD IO mode selection. 977 // io_register={ "" 0 => 978 // """"CONFMODE[0]"""""" "" 1 => 979 // """"CONFMODE[1]"""""" "" 2 => 980 // """"CONFMODE[2]"""""" "" 3 => 981 // """"CONFMODE[3]"""" 4 => 982 // """"IODEN"""" --> When level ‘1’ 983 // this disables the PMOS xtors of 984 // the output stages making them 985 // open-drain type." it can be used 986 // for I2C type of peripherals. 5 => 987 // """"I2MAEN"""" --> Level ‘1’ 988 // enables the approx 2mA output 989 // stage""" """ 6 => """"I4MAEN"""" 990 // --> Level ‘1’ enables the approx 991 // 4mA output stage""" """ 7 => 992 // """"I8MAEN"""" --> Level ‘1’ 993 // enables the approx 8mA output 994 // stage. Note: any drive strength 995 // between 2mA and 14mA can be 996 // obtained with combination of 2mA 997 // 4mA and 8mA.""" """ 8 => 998 // """"IWKPUEN"""" --> 10uA pull up 999 // (weak strength)""" """ 9 => 1000 // """"IWKPDEN"""" --> 10uA pull 1001 // down (weak strength)""" """ 10 => 1002 // """"IOE_N"""" --> output enable 1003 // value. level ‘0’ enables the IDO 1004 // to PAD path. Else PAD is 1005 // tristated (except for the PU/PD 1006 // which are independent)." "Value 1007 // gets latched at rising edge of 1008 // RET33""" """ 11 =>"""" 1009 // IOE_N_OV"""" --> output enable 1010 // overirde. when bit is set to 1011 // logic '1' IOE_N (bit 4) value 1012 // will control IO IOE_N signal else 1013 // IOE_N is control via selected HW 1014 // logic. strong PULL UP and PULL 1015 // Down control is disabled for all 1016 // IO's. both controls are tied to 1017 // logic level '0'. 1018 1019 #define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_S 0 1020 //****************************************************************************** 1021 // 1022 // The following are defines for the bit fields in the 1023 // OCP_SHARED_O_GPIO_PAD_CONFIG_2 register. 1024 // 1025 //****************************************************************************** 1026 #define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_M \ 1027 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1028 // used for PAD IO mode selection. 1029 // io_register={ "" 0 => 1030 // """"CONFMODE[0]"""""" "" 1 => 1031 // """"CONFMODE[1]"""""" "" 2 => 1032 // """"CONFMODE[2]"""""" "" 3 => 1033 // """"CONFMODE[3]"""" 4 => 1034 // """"IODEN"""" --> When level ‘1’ 1035 // this disables the PMOS xtors of 1036 // the output stages making them 1037 // open-drain type." it can be used 1038 // for I2C type of peripherals. 5 => 1039 // """"I2MAEN"""" --> Level ‘1’ 1040 // enables the approx 2mA output 1041 // stage""" """ 6 => """"I4MAEN"""" 1042 // --> Level ‘1’ enables the approx 1043 // 4mA output stage""" """ 7 => 1044 // """"I8MAEN"""" --> Level ‘1’ 1045 // enables the approx 8mA output 1046 // stage. Note: any drive strength 1047 // between 2mA and 14mA can be 1048 // obtained with combination of 2mA 1049 // 4mA and 8mA.""" """ 8 => 1050 // """"IWKPUEN"""" --> 10uA pull up 1051 // (weak strength)""" """ 9 => 1052 // """"IWKPDEN"""" --> 10uA pull 1053 // down (weak strength)""" """ 10 => 1054 // """"IOE_N"""" --> output enable 1055 // value. level ‘0’ enables the IDO 1056 // to PAD path. Else PAD is 1057 // tristated (except for the PU/PD 1058 // which are independent)." "Value 1059 // gets latched at rising edge of 1060 // RET33""" """ 11 =>"""" 1061 // IOE_N_OV"""" --> output enable 1062 // overirde. when bit is set to 1063 // logic '1' IOE_N (bit 4) value 1064 // will control IO IOE_N signal else 1065 // IOE_N is control via selected HW 1066 // logic. strong PULL UP and PULL 1067 // Down control is disabled for all 1068 // IO's. both controls are tied to 1069 // logic level '0'. 1070 1071 #define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_S 0 1072 //****************************************************************************** 1073 // 1074 // The following are defines for the bit fields in the 1075 // OCP_SHARED_O_GPIO_PAD_CONFIG_3 register. 1076 // 1077 //****************************************************************************** 1078 #define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_M \ 1079 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1080 // used for PAD IO mode selection. 1081 // io_register={ "" 0 => 1082 // """"CONFMODE[0]"""""" "" 1 => 1083 // """"CONFMODE[1]"""""" "" 2 => 1084 // """"CONFMODE[2]"""""" "" 3 => 1085 // """"CONFMODE[3]"""" 4 => 1086 // """"IODEN"""" --> When level ‘1’ 1087 // this disables the PMOS xtors of 1088 // the output stages making them 1089 // open-drain type." it can be used 1090 // for I2C type of peripherals. 5 => 1091 // """"I2MAEN"""" --> Level ‘1’ 1092 // enables the approx 2mA output 1093 // stage""" """ 6 => """"I4MAEN"""" 1094 // --> Level ‘1’ enables the approx 1095 // 4mA output stage""" """ 7 => 1096 // """"I8MAEN"""" --> Level ‘1’ 1097 // enables the approx 8mA output 1098 // stage. Note: any drive strength 1099 // between 2mA and 14mA can be 1100 // obtained with combination of 2mA 1101 // 4mA and 8mA.""" """ 8 => 1102 // """"IWKPUEN"""" --> 10uA pull up 1103 // (weak strength)""" """ 9 => 1104 // """"IWKPDEN"""" --> 10uA pull 1105 // down (weak strength)""" """ 10 => 1106 // """"IOE_N"""" --> output enable 1107 // value. level ‘0’ enables the IDO 1108 // to PAD path. Else PAD is 1109 // tristated (except for the PU/PD 1110 // which are independent)." "Value 1111 // gets latched at rising edge of 1112 // RET33""" """ 11 =>"""" 1113 // IOE_N_OV"""" --> output enable 1114 // overirde. when bit is set to 1115 // logic '1' IOE_N (bit 4) value 1116 // will control IO IOE_N signal else 1117 // IOE_N is control via selected HW 1118 // logic. strong PULL UP and PULL 1119 // Down control is disabled for all 1120 // IO's. both controls are tied to 1121 // logic level '0'. 1122 1123 #define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_S 0 1124 //****************************************************************************** 1125 // 1126 // The following are defines for the bit fields in the 1127 // OCP_SHARED_O_GPIO_PAD_CONFIG_4 register. 1128 // 1129 //****************************************************************************** 1130 #define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_M \ 1131 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1132 // used for PAD IO mode selection. 1133 // io_register={ "" 0 => 1134 // """"CONFMODE[0]"""""" "" 1 => 1135 // """"CONFMODE[1]"""""" "" 2 => 1136 // """"CONFMODE[2]"""""" "" 3 => 1137 // """"CONFMODE[3]"""" 4 => 1138 // """"IODEN"""" --> When level ‘1’ 1139 // this disables the PMOS xtors of 1140 // the output stages making them 1141 // open-drain type." it can be used 1142 // for I2C type of peripherals. 5 => 1143 // """"I2MAEN"""" --> Level ‘1’ 1144 // enables the approx 2mA output 1145 // stage""" """ 6 => """"I4MAEN"""" 1146 // --> Level ‘1’ enables the approx 1147 // 4mA output stage""" """ 7 => 1148 // """"I8MAEN"""" --> Level ‘1’ 1149 // enables the approx 8mA output 1150 // stage. Note: any drive strength 1151 // between 2mA and 14mA can be 1152 // obtained with combination of 2mA 1153 // 4mA and 8mA.""" """ 8 => 1154 // """"IWKPUEN"""" --> 10uA pull up 1155 // (weak strength)""" """ 9 => 1156 // """"IWKPDEN"""" --> 10uA pull 1157 // down (weak strength)""" """ 10 => 1158 // """"IOE_N"""" --> output enable 1159 // value. level ‘0’ enables the IDO 1160 // to PAD path. Else PAD is 1161 // tristated (except for the PU/PD 1162 // which are independent)." "Value 1163 // gets latched at rising edge of 1164 // RET33""" """ 11 =>"""" 1165 // IOE_N_OV"""" --> output enable 1166 // overirde. when bit is set to 1167 // logic '1' IOE_N (bit 4) value 1168 // will control IO IOE_N signal else 1169 // IOE_N is control via selected HW 1170 // logic. strong PULL UP and PULL 1171 // Down control is disabled for all 1172 // IO's. both controls are tied to 1173 // logic level '0'. 1174 1175 #define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_S 0 1176 //****************************************************************************** 1177 // 1178 // The following are defines for the bit fields in the 1179 // OCP_SHARED_O_GPIO_PAD_CONFIG_5 register. 1180 // 1181 //****************************************************************************** 1182 #define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_M \ 1183 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1184 // used for PAD IO mode selection. 1185 // io_register={ "" 0 => 1186 // """"CONFMODE[0]"""""" "" 1 => 1187 // """"CONFMODE[1]"""""" "" 2 => 1188 // """"CONFMODE[2]"""""" "" 3 => 1189 // """"CONFMODE[3]"""" 4 => 1190 // """"IODEN"""" --> When level ‘1’ 1191 // this disables the PMOS xtors of 1192 // the output stages making them 1193 // open-drain type." it can be used 1194 // for I2C type of peripherals. 5 => 1195 // """"I2MAEN"""" --> Level ‘1’ 1196 // enables the approx 2mA output 1197 // stage""" """ 6 => """"I4MAEN"""" 1198 // --> Level ‘1’ enables the approx 1199 // 4mA output stage""" """ 7 => 1200 // """"I8MAEN"""" --> Level ‘1’ 1201 // enables the approx 8mA output 1202 // stage. Note: any drive strength 1203 // between 2mA and 14mA can be 1204 // obtained with combination of 2mA 1205 // 4mA and 8mA.""" """ 8 => 1206 // """"IWKPUEN"""" --> 10uA pull up 1207 // (weak strength)""" """ 9 => 1208 // """"IWKPDEN"""" --> 10uA pull 1209 // down (weak strength)""" """ 10 => 1210 // """"IOE_N"""" --> output enable 1211 // value. level ‘0’ enables the IDO 1212 // to PAD path. Else PAD is 1213 // tristated (except for the PU/PD 1214 // which are independent)." "Value 1215 // gets latched at rising edge of 1216 // RET33""" """ 11 =>"""" 1217 // IOE_N_OV"""" --> output enable 1218 // overirde. when bit is set to 1219 // logic '1' IOE_N (bit 4) value 1220 // will control IO IOE_N signal else 1221 // IOE_N is control via selected HW 1222 // logic. strong PULL UP and PULL 1223 // Down control is disabled for all 1224 // IO's. both controls are tied to 1225 // logic level '0'. 1226 1227 #define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_S 0 1228 //****************************************************************************** 1229 // 1230 // The following are defines for the bit fields in the 1231 // OCP_SHARED_O_GPIO_PAD_CONFIG_6 register. 1232 // 1233 //****************************************************************************** 1234 #define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_M \ 1235 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1236 // used for PAD IO mode selection. 1237 // io_register={ "" 0 => 1238 // """"CONFMODE[0]"""""" "" 1 => 1239 // """"CONFMODE[1]"""""" "" 2 => 1240 // """"CONFMODE[2]"""""" "" 3 => 1241 // """"CONFMODE[3]"""" 4 => 1242 // """"IODEN"""" --> When level ‘1’ 1243 // this disables the PMOS xtors of 1244 // the output stages making them 1245 // open-drain type." it can be used 1246 // for I2C type of peripherals. 5 => 1247 // """"I2MAEN"""" --> Level ‘1’ 1248 // enables the approx 2mA output 1249 // stage""" """ 6 => """"I4MAEN"""" 1250 // --> Level ‘1’ enables the approx 1251 // 4mA output stage""" """ 7 => 1252 // """"I8MAEN"""" --> Level ‘1’ 1253 // enables the approx 8mA output 1254 // stage. Note: any drive strength 1255 // between 2mA and 14mA can be 1256 // obtained with combination of 2mA 1257 // 4mA and 8mA.""" """ 8 => 1258 // """"IWKPUEN"""" --> 10uA pull up 1259 // (weak strength)""" """ 9 => 1260 // """"IWKPDEN"""" --> 10uA pull 1261 // down (weak strength)""" """ 10 => 1262 // """"IOE_N"""" --> output enable 1263 // value. level ‘0’ enables the IDO 1264 // to PAD path. Else PAD is 1265 // tristated (except for the PU/PD 1266 // which are independent)." "Value 1267 // gets latched at rising edge of 1268 // RET33""" """ 11 =>"""" 1269 // IOE_N_OV"""" --> output enable 1270 // overirde. when bit is set to 1271 // logic '1' IOE_N (bit 4) value 1272 // will control IO IOE_N signal else 1273 // IOE_N is control via selected HW 1274 // logic. strong PULL UP and PULL 1275 // Down control is disabled for all 1276 // IO's. both controls are tied to 1277 // logic level '0'. 1278 1279 #define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_S 0 1280 //****************************************************************************** 1281 // 1282 // The following are defines for the bit fields in the 1283 // OCP_SHARED_O_GPIO_PAD_CONFIG_7 register. 1284 // 1285 //****************************************************************************** 1286 #define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_M \ 1287 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1288 // used for PAD IO mode selection. 1289 // io_register={ "" 0 => 1290 // """"CONFMODE[0]"""""" "" 1 => 1291 // """"CONFMODE[1]"""""" "" 2 => 1292 // """"CONFMODE[2]"""""" "" 3 => 1293 // """"CONFMODE[3]"""" 4 => 1294 // """"IODEN"""" --> When level ‘1’ 1295 // this disables the PMOS xtors of 1296 // the output stages making them 1297 // open-drain type." it can be used 1298 // for I2C type of peripherals. 5 => 1299 // """"I2MAEN"""" --> Level ‘1’ 1300 // enables the approx 2mA output 1301 // stage""" """ 6 => """"I4MAEN"""" 1302 // --> Level ‘1’ enables the approx 1303 // 4mA output stage""" """ 7 => 1304 // """"I8MAEN"""" --> Level ‘1’ 1305 // enables the approx 8mA output 1306 // stage. Note: any drive strength 1307 // between 2mA and 14mA can be 1308 // obtained with combination of 2mA 1309 // 4mA and 8mA.""" """ 8 => 1310 // """"IWKPUEN"""" --> 10uA pull up 1311 // (weak strength)""" """ 9 => 1312 // """"IWKPDEN"""" --> 10uA pull 1313 // down (weak strength)""" """ 10 => 1314 // """"IOE_N"""" --> output enable 1315 // value. level ‘0’ enables the IDO 1316 // to PAD path. Else PAD is 1317 // tristated (except for the PU/PD 1318 // which are independent)." "Value 1319 // gets latched at rising edge of 1320 // RET33""" """ 11 =>"""" 1321 // IOE_N_OV"""" --> output enable 1322 // overirde. when bit is set to 1323 // logic '1' IOE_N (bit 4) value 1324 // will control IO IOE_N signal else 1325 // IOE_N is control via selected HW 1326 // logic. strong PULL UP and PULL 1327 // Down control is disabled for all 1328 // IO's. both controls are tied to 1329 // logic level '0'. 1330 1331 #define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_S 0 1332 //****************************************************************************** 1333 // 1334 // The following are defines for the bit fields in the 1335 // OCP_SHARED_O_GPIO_PAD_CONFIG_8 register. 1336 // 1337 //****************************************************************************** 1338 #define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_M \ 1339 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1340 // used for PAD IO mode selection. 1341 // io_register={ "" 0 => 1342 // """"CONFMODE[0]"""""" "" 1 => 1343 // """"CONFMODE[1]"""""" "" 2 => 1344 // """"CONFMODE[2]"""""" "" 3 => 1345 // """"CONFMODE[3]"""" 4 => 1346 // """"IODEN"""" --> When level ‘1’ 1347 // this disables the PMOS xtors of 1348 // the output stages making them 1349 // open-drain type." it can be used 1350 // for I2C type of peripherals. 5 => 1351 // """"I2MAEN"""" --> Level ‘1’ 1352 // enables the approx 2mA output 1353 // stage""" """ 6 => """"I4MAEN"""" 1354 // --> Level ‘1’ enables the approx 1355 // 4mA output stage""" """ 7 => 1356 // """"I8MAEN"""" --> Level ‘1’ 1357 // enables the approx 8mA output 1358 // stage. Note: any drive strength 1359 // between 2mA and 14mA can be 1360 // obtained with combination of 2mA 1361 // 4mA and 8mA.""" """ 8 => 1362 // """"IWKPUEN"""" --> 10uA pull up 1363 // (weak strength)""" """ 9 => 1364 // """"IWKPDEN"""" --> 10uA pull 1365 // down (weak strength)""" """ 10 => 1366 // """"IOE_N"""" --> output enable 1367 // value. level ‘0’ enables the IDO 1368 // to PAD path. Else PAD is 1369 // tristated (except for the PU/PD 1370 // which are independent)." "Value 1371 // gets latched at rising edge of 1372 // RET33""" """ 11 =>"""" 1373 // IOE_N_OV"""" --> output enable 1374 // overirde. when bit is set to 1375 // logic '1' IOE_N (bit 4) value 1376 // will control IO IOE_N signal else 1377 // IOE_N is control via selected HW 1378 // logic. strong PULL UP and PULL 1379 // Down control is disabled for all 1380 // IO's. both controls are tied to 1381 // logic level '0'. 1382 1383 #define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_S 0 1384 //****************************************************************************** 1385 // 1386 // The following are defines for the bit fields in the 1387 // OCP_SHARED_O_GPIO_PAD_CONFIG_9 register. 1388 // 1389 //****************************************************************************** 1390 #define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_M \ 1391 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1392 // used for PAD IO mode selection. 1393 // io_register={ "" 0 => 1394 // """"CONFMODE[0]"""""" "" 1 => 1395 // """"CONFMODE[1]"""""" "" 2 => 1396 // """"CONFMODE[2]"""""" "" 3 => 1397 // """"CONFMODE[3]"""" 4 => 1398 // """"IODEN"""" --> When level ‘1’ 1399 // this disables the PMOS xtors of 1400 // the output stages making them 1401 // open-drain type." it can be used 1402 // for I2C type of peripherals. 5 => 1403 // """"I2MAEN"""" --> Level ‘1’ 1404 // enables the approx 2mA output 1405 // stage""" """ 6 => """"I4MAEN"""" 1406 // --> Level ‘1’ enables the approx 1407 // 4mA output stage""" """ 7 => 1408 // """"I8MAEN"""" --> Level ‘1’ 1409 // enables the approx 8mA output 1410 // stage. Note: any drive strength 1411 // between 2mA and 14mA can be 1412 // obtained with combination of 2mA 1413 // 4mA and 8mA.""" """ 8 => 1414 // """"IWKPUEN"""" --> 10uA pull up 1415 // (weak strength)""" """ 9 => 1416 // """"IWKPDEN"""" --> 10uA pull 1417 // down (weak strength)""" """ 10 => 1418 // """"IOE_N"""" --> output enable 1419 // value. level ‘0’ enables the IDO 1420 // to PAD path. Else PAD is 1421 // tristated (except for the PU/PD 1422 // which are independent)." "Value 1423 // gets latched at rising edge of 1424 // RET33""" """ 11 =>"""" 1425 // IOE_N_OV"""" --> output enable 1426 // overirde. when bit is set to 1427 // logic '1' IOE_N (bit 4) value 1428 // will control IO IOE_N signal else 1429 // IOE_N is control via selected HW 1430 // logic. strong PULL UP and PULL 1431 // Down control is disabled for all 1432 // IO's. both controls are tied to 1433 // logic level '0'. 1434 1435 #define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_S 0 1436 //****************************************************************************** 1437 // 1438 // The following are defines for the bit fields in the 1439 // OCP_SHARED_O_GPIO_PAD_CONFIG_10 register. 1440 // 1441 //****************************************************************************** 1442 #define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_M \ 1443 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1444 // used for PAD IO mode selection. 1445 // io_register={ "" 0 => 1446 // """"CONFMODE[0]"""""" "" 1 => 1447 // """"CONFMODE[1]"""""" "" 2 => 1448 // """"CONFMODE[2]"""""" "" 3 => 1449 // """"CONFMODE[3]"""" 4 => 1450 // """"IODEN"""" --> When level ‘1’ 1451 // this disables the PMOS xtors of 1452 // the output stages making them 1453 // open-drain type." it can be used 1454 // for I2C type of peripherals. 5 => 1455 // """"I2MAEN"""" --> Level ‘1’ 1456 // enables the approx 2mA output 1457 // stage""" """ 6 => """"I4MAEN"""" 1458 // --> Level ‘1’ enables the approx 1459 // 4mA output stage""" """ 7 => 1460 // """"I8MAEN"""" --> Level ‘1’ 1461 // enables the approx 8mA output 1462 // stage. Note: any drive strength 1463 // between 2mA and 14mA can be 1464 // obtained with combination of 2mA 1465 // 4mA and 8mA.""" """ 8 => 1466 // """"IWKPUEN"""" --> 10uA pull up 1467 // (weak strength)""" """ 9 => 1468 // """"IWKPDEN"""" --> 10uA pull 1469 // down (weak strength)""" """ 10 => 1470 // """"IOE_N"""" --> output enable 1471 // value. level ‘0’ enables the IDO 1472 // to PAD path. Else PAD is 1473 // tristated (except for the PU/PD 1474 // which are independent)." "Value 1475 // gets latched at rising edge of 1476 // RET33""" """ 11 =>"""" 1477 // IOE_N_OV"""" --> output enable 1478 // overirde. when bit is set to 1479 // logic '1' IOE_N (bit 4) value 1480 // will control IO IOE_N signal else 1481 // IOE_N is control via selected HW 1482 // logic. strong PULL UP and PULL 1483 // Down control is disabled for all 1484 // IO's. both controls are tied to 1485 // logic level '0'. 1486 1487 #define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_S 0 1488 //****************************************************************************** 1489 // 1490 // The following are defines for the bit fields in the 1491 // OCP_SHARED_O_GPIO_PAD_CONFIG_11 register. 1492 // 1493 //****************************************************************************** 1494 #define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_M \ 1495 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1496 // used for PAD IO mode selection. 1497 // io_register={ "" 0 => 1498 // """"CONFMODE[0]"""""" "" 1 => 1499 // """"CONFMODE[1]"""""" "" 2 => 1500 // """"CONFMODE[2]"""""" "" 3 => 1501 // """"CONFMODE[3]"""" 4 => 1502 // """"IODEN"""" --> When level ‘1’ 1503 // this disables the PMOS xtors of 1504 // the output stages making them 1505 // open-drain type." it can be used 1506 // for I2C type of peripherals. 5 => 1507 // """"I2MAEN"""" --> Level ‘1’ 1508 // enables the approx 2mA output 1509 // stage""" """ 6 => """"I4MAEN"""" 1510 // --> Level ‘1’ enables the approx 1511 // 4mA output stage""" """ 7 => 1512 // """"I8MAEN"""" --> Level ‘1’ 1513 // enables the approx 8mA output 1514 // stage. Note: any drive strength 1515 // between 2mA and 14mA can be 1516 // obtained with combination of 2mA 1517 // 4mA and 8mA.""" """ 8 => 1518 // """"IWKPUEN"""" --> 10uA pull up 1519 // (weak strength)""" """ 9 => 1520 // """"IWKPDEN"""" --> 10uA pull 1521 // down (weak strength)""" """ 10 => 1522 // """"IOE_N"""" --> output enable 1523 // value. level ‘0’ enables the IDO 1524 // to PAD path. Else PAD is 1525 // tristated (except for the PU/PD 1526 // which are independent)." "Value 1527 // gets latched at rising edge of 1528 // RET33""" """ 11 =>"""" 1529 // IOE_N_OV"""" --> output enable 1530 // overirde. when bit is set to 1531 // logic '1' IOE_N (bit 4) value 1532 // will control IO IOE_N signal else 1533 // IOE_N is control via selected HW 1534 // logic. strong PULL UP and PULL 1535 // Down control is disabled for all 1536 // IO's. both controls are tied to 1537 // logic level '0'. 1538 1539 #define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_S 0 1540 //****************************************************************************** 1541 // 1542 // The following are defines for the bit fields in the 1543 // OCP_SHARED_O_GPIO_PAD_CONFIG_12 register. 1544 // 1545 //****************************************************************************** 1546 #define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_M \ 1547 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1548 // used for PAD IO mode selection. 1549 // io_register={ "" 0 => 1550 // """"CONFMODE[0]"""""" "" 1 => 1551 // """"CONFMODE[1]"""""" "" 2 => 1552 // """"CONFMODE[2]"""""" "" 3 => 1553 // """"CONFMODE[3]"""" 4 => 1554 // """"IODEN"""" --> When level ‘1’ 1555 // this disables the PMOS xtors of 1556 // the output stages making them 1557 // open-drain type." it can be used 1558 // for I2C type of peripherals. 5 => 1559 // """"I2MAEN"""" --> Level ‘1’ 1560 // enables the approx 2mA output 1561 // stage""" """ 6 => """"I4MAEN"""" 1562 // --> Level ‘1’ enables the approx 1563 // 4mA output stage""" """ 7 => 1564 // """"I8MAEN"""" --> Level ‘1’ 1565 // enables the approx 8mA output 1566 // stage. Note: any drive strength 1567 // between 2mA and 14mA can be 1568 // obtained with combination of 2mA 1569 // 4mA and 8mA.""" """ 8 => 1570 // """"IWKPUEN"""" --> 10uA pull up 1571 // (weak strength)""" """ 9 => 1572 // """"IWKPDEN"""" --> 10uA pull 1573 // down (weak strength)""" """ 10 => 1574 // """"IOE_N"""" --> output enable 1575 // value. level ‘0’ enables the IDO 1576 // to PAD path. Else PAD is 1577 // tristated (except for the PU/PD 1578 // which are independent)." "Value 1579 // gets latched at rising edge of 1580 // RET33""" """ 11 =>"""" 1581 // IOE_N_OV"""" --> output enable 1582 // overirde. when bit is set to 1583 // logic '1' IOE_N (bit 4) value 1584 // will control IO IOE_N signal else 1585 // IOE_N is control via selected HW 1586 // logic. strong PULL UP and PULL 1587 // Down control is disabled for all 1588 // IO's. both controls are tied to 1589 // logic level '0'. 1590 1591 #define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_S 0 1592 //****************************************************************************** 1593 // 1594 // The following are defines for the bit fields in the 1595 // OCP_SHARED_O_GPIO_PAD_CONFIG_13 register. 1596 // 1597 //****************************************************************************** 1598 #define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_M \ 1599 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1600 // used for PAD IO mode selection. 1601 // io_register={ "" 0 => 1602 // """"CONFMODE[0]"""""" "" 1 => 1603 // """"CONFMODE[1]"""""" "" 2 => 1604 // """"CONFMODE[2]"""""" "" 3 => 1605 // """"CONFMODE[3]"""" 4 => 1606 // """"IODEN"""" --> When level ‘1’ 1607 // this disables the PMOS xtors of 1608 // the output stages making them 1609 // open-drain type." it can be used 1610 // for I2C type of peripherals. 5 => 1611 // """"I2MAEN"""" --> Level ‘1’ 1612 // enables the approx 2mA output 1613 // stage""" """ 6 => """"I4MAEN"""" 1614 // --> Level ‘1’ enables the approx 1615 // 4mA output stage""" """ 7 => 1616 // """"I8MAEN"""" --> Level ‘1’ 1617 // enables the approx 8mA output 1618 // stage. Note: any drive strength 1619 // between 2mA and 14mA can be 1620 // obtained with combination of 2mA 1621 // 4mA and 8mA.""" """ 8 => 1622 // """"IWKPUEN"""" --> 10uA pull up 1623 // (weak strength)""" """ 9 => 1624 // """"IWKPDEN"""" --> 10uA pull 1625 // down (weak strength)""" """ 10 => 1626 // """"IOE_N"""" --> output enable 1627 // value. level ‘0’ enables the IDO 1628 // to PAD path. Else PAD is 1629 // tristated (except for the PU/PD 1630 // which are independent)." "Value 1631 // gets latched at rising edge of 1632 // RET33""" """ 11 =>"""" 1633 // IOE_N_OV"""" --> output enable 1634 // overirde. when bit is set to 1635 // logic '1' IOE_N (bit 4) value 1636 // will control IO IOE_N signal else 1637 // IOE_N is control via selected HW 1638 // logic. strong PULL UP and PULL 1639 // Down control is disabled for all 1640 // IO's. both controls are tied to 1641 // logic level '0'. 1642 1643 #define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_S 0 1644 //****************************************************************************** 1645 // 1646 // The following are defines for the bit fields in the 1647 // OCP_SHARED_O_GPIO_PAD_CONFIG_14 register. 1648 // 1649 //****************************************************************************** 1650 #define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_M \ 1651 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1652 // used for PAD IO mode selection. 1653 // io_register={ "" 0 => 1654 // """"CONFMODE[0]"""""" "" 1 => 1655 // """"CONFMODE[1]"""""" "" 2 => 1656 // """"CONFMODE[2]"""""" "" 3 => 1657 // """"CONFMODE[3]"""" 4 => 1658 // """"IODEN"""" --> When level ‘1’ 1659 // this disables the PMOS xtors of 1660 // the output stages making them 1661 // open-drain type." it can be used 1662 // for I2C type of peripherals. 5 => 1663 // """"I2MAEN"""" --> Level ‘1’ 1664 // enables the approx 2mA output 1665 // stage""" """ 6 => """"I4MAEN"""" 1666 // --> Level ‘1’ enables the approx 1667 // 4mA output stage""" """ 7 => 1668 // """"I8MAEN"""" --> Level ‘1’ 1669 // enables the approx 8mA output 1670 // stage. Note: any drive strength 1671 // between 2mA and 14mA can be 1672 // obtained with combination of 2mA 1673 // 4mA and 8mA.""" """ 8 => 1674 // """"IWKPUEN"""" --> 10uA pull up 1675 // (weak strength)""" """ 9 => 1676 // """"IWKPDEN"""" --> 10uA pull 1677 // down (weak strength)""" """ 10 => 1678 // """"IOE_N"""" --> output enable 1679 // value. level ‘0’ enables the IDO 1680 // to PAD path. Else PAD is 1681 // tristated (except for the PU/PD 1682 // which are independent)." "Value 1683 // gets latched at rising edge of 1684 // RET33""" """ 11 =>"""" 1685 // IOE_N_OV"""" --> output enable 1686 // overirde. when bit is set to 1687 // logic '1' IOE_N (bit 4) value 1688 // will control IO IOE_N signal else 1689 // IOE_N is control via selected HW 1690 // logic. strong PULL UP and PULL 1691 // Down control is disabled for all 1692 // IO's. both controls are tied to 1693 // logic level '0'. 1694 1695 #define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_S 0 1696 //****************************************************************************** 1697 // 1698 // The following are defines for the bit fields in the 1699 // OCP_SHARED_O_GPIO_PAD_CONFIG_15 register. 1700 // 1701 //****************************************************************************** 1702 #define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_M \ 1703 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1704 // used for PAD IO mode selection. 1705 // io_register={ "" 0 => 1706 // """"CONFMODE[0]"""""" "" 1 => 1707 // """"CONFMODE[1]"""""" "" 2 => 1708 // """"CONFMODE[2]"""""" "" 3 => 1709 // """"CONFMODE[3]"""" 4 => 1710 // """"IODEN"""" --> When level ‘1’ 1711 // this disables the PMOS xtors of 1712 // the output stages making them 1713 // open-drain type." it can be used 1714 // for I2C type of peripherals. 5 => 1715 // """"I2MAEN"""" --> Level ‘1’ 1716 // enables the approx 2mA output 1717 // stage""" """ 6 => """"I4MAEN"""" 1718 // --> Level ‘1’ enables the approx 1719 // 4mA output stage""" """ 7 => 1720 // """"I8MAEN"""" --> Level ‘1’ 1721 // enables the approx 8mA output 1722 // stage. Note: any drive strength 1723 // between 2mA and 14mA can be 1724 // obtained with combination of 2mA 1725 // 4mA and 8mA.""" """ 8 => 1726 // """"IWKPUEN"""" --> 10uA pull up 1727 // (weak strength)""" """ 9 => 1728 // """"IWKPDEN"""" --> 10uA pull 1729 // down (weak strength)""" """ 10 => 1730 // """"IOE_N"""" --> output enable 1731 // value. level ‘0’ enables the IDO 1732 // to PAD path. Else PAD is 1733 // tristated (except for the PU/PD 1734 // which are independent)." "Value 1735 // gets latched at rising edge of 1736 // RET33""" """ 11 =>"""" 1737 // IOE_N_OV"""" --> output enable 1738 // overirde. when bit is set to 1739 // logic '1' IOE_N (bit 4) value 1740 // will control IO IOE_N signal else 1741 // IOE_N is control via selected HW 1742 // logic. strong PULL UP and PULL 1743 // Down control is disabled for all 1744 // IO's. both controls are tied to 1745 // logic level '0'. 1746 1747 #define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_S 0 1748 //****************************************************************************** 1749 // 1750 // The following are defines for the bit fields in the 1751 // OCP_SHARED_O_GPIO_PAD_CONFIG_16 register. 1752 // 1753 //****************************************************************************** 1754 #define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_M \ 1755 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1756 // used for PAD IO mode selection. 1757 // io_register={ "" 0 => 1758 // """"CONFMODE[0]"""""" "" 1 => 1759 // """"CONFMODE[1]"""""" "" 2 => 1760 // """"CONFMODE[2]"""""" "" 3 => 1761 // """"CONFMODE[3]"""" 4 => 1762 // """"IODEN"""" --> When level ‘1’ 1763 // this disables the PMOS xtors of 1764 // the output stages making them 1765 // open-drain type." it can be used 1766 // for I2C type of peripherals. 5 => 1767 // """"I2MAEN"""" --> Level ‘1’ 1768 // enables the approx 2mA output 1769 // stage""" """ 6 => """"I4MAEN"""" 1770 // --> Level ‘1’ enables the approx 1771 // 4mA output stage""" """ 7 => 1772 // """"I8MAEN"""" --> Level ‘1’ 1773 // enables the approx 8mA output 1774 // stage. Note: any drive strength 1775 // between 2mA and 14mA can be 1776 // obtained with combination of 2mA 1777 // 4mA and 8mA.""" """ 8 => 1778 // """"IWKPUEN"""" --> 10uA pull up 1779 // (weak strength)""" """ 9 => 1780 // """"IWKPDEN"""" --> 10uA pull 1781 // down (weak strength)""" """ 10 => 1782 // """"IOE_N"""" --> output enable 1783 // value. level ‘0’ enables the IDO 1784 // to PAD path. Else PAD is 1785 // tristated (except for the PU/PD 1786 // which are independent)." "Value 1787 // gets latched at rising edge of 1788 // RET33""" """ 11 =>"""" 1789 // IOE_N_OV"""" --> output enable 1790 // overirde. when bit is set to 1791 // logic '1' IOE_N (bit 4) value 1792 // will control IO IOE_N signal else 1793 // IOE_N is control via selected HW 1794 // logic. strong PULL UP and PULL 1795 // Down control is disabled for all 1796 // IO's. both controls are tied to 1797 // logic level '0'. 1798 1799 #define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_S 0 1800 //****************************************************************************** 1801 // 1802 // The following are defines for the bit fields in the 1803 // OCP_SHARED_O_GPIO_PAD_CONFIG_17 register. 1804 // 1805 //****************************************************************************** 1806 #define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_M \ 1807 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1808 // used for PAD IO mode selection. 1809 // io_register={ "" 0 => 1810 // """"CONFMODE[0]"""""" "" 1 => 1811 // """"CONFMODE[1]"""""" "" 2 => 1812 // """"CONFMODE[2]"""""" "" 3 => 1813 // """"CONFMODE[3]"""" 4 => 1814 // """"IODEN"""" --> When level ‘1’ 1815 // this disables the PMOS xtors of 1816 // the output stages making them 1817 // open-drain type." it can be used 1818 // for I2C type of peripherals. 5 => 1819 // """"I2MAEN"""" --> Level ‘1’ 1820 // enables the approx 2mA output 1821 // stage""" """ 6 => """"I4MAEN"""" 1822 // --> Level ‘1’ enables the approx 1823 // 4mA output stage""" """ 7 => 1824 // """"I8MAEN"""" --> Level ‘1’ 1825 // enables the approx 8mA output 1826 // stage. Note: any drive strength 1827 // between 2mA and 14mA can be 1828 // obtained with combination of 2mA 1829 // 4mA and 8mA.""" """ 8 => 1830 // """"IWKPUEN"""" --> 10uA pull up 1831 // (weak strength)""" """ 9 => 1832 // """"IWKPDEN"""" --> 10uA pull 1833 // down (weak strength)""" """ 10 => 1834 // """"IOE_N"""" --> output enable 1835 // value. level ‘0’ enables the IDO 1836 // to PAD path. Else PAD is 1837 // tristated (except for the PU/PD 1838 // which are independent)." "Value 1839 // gets latched at rising edge of 1840 // RET33""" """ 11 =>"""" 1841 // IOE_N_OV"""" --> output enable 1842 // overirde. when bit is set to 1843 // logic '1' IOE_N (bit 4) value 1844 // will control IO IOE_N signal else 1845 // IOE_N is control via selected HW 1846 // logic. strong PULL UP and PULL 1847 // Down control is disabled for all 1848 // IO's. both controls are tied to 1849 // logic level '0'. 1850 1851 #define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_S 0 1852 //****************************************************************************** 1853 // 1854 // The following are defines for the bit fields in the 1855 // OCP_SHARED_O_GPIO_PAD_CONFIG_18 register. 1856 // 1857 //****************************************************************************** 1858 #define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_M \ 1859 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1860 // used for PAD IO mode selection. 1861 // io_register={ "" 0 => 1862 // """"CONFMODE[0]"""""" "" 1 => 1863 // """"CONFMODE[1]"""""" "" 2 => 1864 // """"CONFMODE[2]"""""" "" 3 => 1865 // """"CONFMODE[3]"""" 4 => 1866 // """"IODEN"""" --> When level ‘1’ 1867 // this disables the PMOS xtors of 1868 // the output stages making them 1869 // open-drain type." it can be used 1870 // for I2C type of peripherals. 5 => 1871 // """"I2MAEN"""" --> Level ‘1’ 1872 // enables the approx 2mA output 1873 // stage""" """ 6 => """"I4MAEN"""" 1874 // --> Level ‘1’ enables the approx 1875 // 4mA output stage""" """ 7 => 1876 // """"I8MAEN"""" --> Level ‘1’ 1877 // enables the approx 8mA output 1878 // stage. Note: any drive strength 1879 // between 2mA and 14mA can be 1880 // obtained with combination of 2mA 1881 // 4mA and 8mA.""" """ 8 => 1882 // """"IWKPUEN"""" --> 10uA pull up 1883 // (weak strength)""" """ 9 => 1884 // """"IWKPDEN"""" --> 10uA pull 1885 // down (weak strength)""" """ 10 => 1886 // """"IOE_N"""" --> output enable 1887 // value. level ‘0’ enables the IDO 1888 // to PAD path. Else PAD is 1889 // tristated (except for the PU/PD 1890 // which are independent)." "Value 1891 // gets latched at rising edge of 1892 // RET33""" """ 11 =>"""" 1893 // IOE_N_OV"""" --> output enable 1894 // overirde. when bit is set to 1895 // logic '1' IOE_N (bit 4) value 1896 // will control IO IOE_N signal else 1897 // IOE_N is control via selected HW 1898 // logic. strong PULL UP and PULL 1899 // Down control is disabled for all 1900 // IO's. both controls are tied to 1901 // logic level '0'. 1902 1903 #define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_S 0 1904 //****************************************************************************** 1905 // 1906 // The following are defines for the bit fields in the 1907 // OCP_SHARED_O_GPIO_PAD_CONFIG_19 register. 1908 // 1909 //****************************************************************************** 1910 #define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_M \ 1911 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1912 // used for PAD IO mode selection. 1913 // io_register={ "" 0 => 1914 // """"CONFMODE[0]"""""" "" 1 => 1915 // """"CONFMODE[1]"""""" "" 2 => 1916 // """"CONFMODE[2]"""""" "" 3 => 1917 // """"CONFMODE[3]"""" 4 => 1918 // """"IODEN"""" --> When level ‘1’ 1919 // this disables the PMOS xtors of 1920 // the output stages making them 1921 // open-drain type." it can be used 1922 // for I2C type of peripherals. 5 => 1923 // """"I2MAEN"""" --> Level ‘1’ 1924 // enables the approx 2mA output 1925 // stage""" """ 6 => """"I4MAEN"""" 1926 // --> Level ‘1’ enables the approx 1927 // 4mA output stage""" """ 7 => 1928 // """"I8MAEN"""" --> Level ‘1’ 1929 // enables the approx 8mA output 1930 // stage. Note: any drive strength 1931 // between 2mA and 14mA can be 1932 // obtained with combination of 2mA 1933 // 4mA and 8mA.""" """ 8 => 1934 // """"IWKPUEN"""" --> 10uA pull up 1935 // (weak strength)""" """ 9 => 1936 // """"IWKPDEN"""" --> 10uA pull 1937 // down (weak strength)""" """ 10 => 1938 // """"IOE_N"""" --> output enable 1939 // value. level ‘0’ enables the IDO 1940 // to PAD path. Else PAD is 1941 // tristated (except for the PU/PD 1942 // which are independent)." "Value 1943 // gets latched at rising edge of 1944 // RET33""" """ 11 =>"""" 1945 // IOE_N_OV"""" --> output enable 1946 // overirde. when bit is set to 1947 // logic '1' IOE_N (bit 4) value 1948 // will control IO IOE_N signal else 1949 // IOE_N is control via selected HW 1950 // logic. strong PULL UP and PULL 1951 // Down control is disabled for all 1952 // IO's. both controls are tied to 1953 // logic level '0'. 1954 1955 #define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_S 0 1956 //****************************************************************************** 1957 // 1958 // The following are defines for the bit fields in the 1959 // OCP_SHARED_O_GPIO_PAD_CONFIG_20 register. 1960 // 1961 //****************************************************************************** 1962 #define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_M \ 1963 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 1964 // used for PAD IO mode selection. 1965 // io_register={ "" 0 => 1966 // """"CONFMODE[0]"""""" "" 1 => 1967 // """"CONFMODE[1]"""""" "" 2 => 1968 // """"CONFMODE[2]"""""" "" 3 => 1969 // """"CONFMODE[3]"""" 4 => 1970 // """"IODEN"""" --> When level ‘1’ 1971 // this disables the PMOS xtors of 1972 // the output stages making them 1973 // open-drain type." it can be used 1974 // for I2C type of peripherals. 5 => 1975 // """"I2MAEN"""" --> Level ‘1’ 1976 // enables the approx 2mA output 1977 // stage""" """ 6 => """"I4MAEN"""" 1978 // --> Level ‘1’ enables the approx 1979 // 4mA output stage""" """ 7 => 1980 // """"I8MAEN"""" --> Level ‘1’ 1981 // enables the approx 8mA output 1982 // stage. Note: any drive strength 1983 // between 2mA and 14mA can be 1984 // obtained with combination of 2mA 1985 // 4mA and 8mA.""" """ 8 => 1986 // """"IWKPUEN"""" --> 10uA pull up 1987 // (weak strength)""" """ 9 => 1988 // """"IWKPDEN"""" --> 10uA pull 1989 // down (weak strength)""" """ 10 => 1990 // """"IOE_N"""" --> output enable 1991 // value. level ‘0’ enables the IDO 1992 // to PAD path. Else PAD is 1993 // tristated (except for the PU/PD 1994 // which are independent)." "Value 1995 // gets latched at rising edge of 1996 // RET33""" """ 11 =>"""" 1997 // IOE_N_OV"""" --> output enable 1998 // overirde. when bit is set to 1999 // logic '1' IOE_N (bit 4) value 2000 // will control IO IOE_N signal else 2001 // IOE_N is control via selected HW 2002 // logic. strong PULL UP and PULL 2003 // Down control is disabled for all 2004 // IO's. both controls are tied to 2005 // logic level '0'. 2006 2007 #define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_S 0 2008 //****************************************************************************** 2009 // 2010 // The following are defines for the bit fields in the 2011 // OCP_SHARED_O_GPIO_PAD_CONFIG_21 register. 2012 // 2013 //****************************************************************************** 2014 #define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_M \ 2015 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 2016 // used for PAD IO mode selection. 2017 // io_register={ "" 0 => 2018 // """"CONFMODE[0]"""""" "" 1 => 2019 // """"CONFMODE[1]"""""" "" 2 => 2020 // """"CONFMODE[2]"""""" "" 3 => 2021 // """"CONFMODE[3]"""" 4 => 2022 // """"IODEN"""" --> When level ‘1’ 2023 // this disables the PMOS xtors of 2024 // the output stages making them 2025 // open-drain type." it can be used 2026 // for I2C type of peripherals. 5 => 2027 // """"I2MAEN"""" --> Level ‘1’ 2028 // enables the approx 2mA output 2029 // stage""" """ 6 => """"I4MAEN"""" 2030 // --> Level ‘1’ enables the approx 2031 // 4mA output stage""" """ 7 => 2032 // """"I8MAEN"""" --> Level ‘1’ 2033 // enables the approx 8mA output 2034 // stage. Note: any drive strength 2035 // between 2mA and 14mA can be 2036 // obtained with combination of 2mA 2037 // 4mA and 8mA.""" """ 8 => 2038 // """"IWKPUEN"""" --> 10uA pull up 2039 // (weak strength)""" """ 9 => 2040 // """"IWKPDEN"""" --> 10uA pull 2041 // down (weak strength)""" """ 10 => 2042 // """"IOE_N"""" --> output enable 2043 // value. level ‘0’ enables the IDO 2044 // to PAD path. Else PAD is 2045 // tristated (except for the PU/PD 2046 // which are independent)." "Value 2047 // gets latched at rising edge of 2048 // RET33""" """ 11 =>"""" 2049 // IOE_N_OV"""" --> output enable 2050 // overirde. when bit is set to 2051 // logic '1' IOE_N (bit 4) value 2052 // will control IO IOE_N signal else 2053 // IOE_N is control via selected HW 2054 // logic. strong PULL UP and PULL 2055 // Down control is disabled for all 2056 // IO's. both controls are tied to 2057 // logic level '0'. 2058 2059 #define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_S 0 2060 //****************************************************************************** 2061 // 2062 // The following are defines for the bit fields in the 2063 // OCP_SHARED_O_GPIO_PAD_CONFIG_22 register. 2064 // 2065 //****************************************************************************** 2066 #define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_M \ 2067 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 2068 // used for PAD IO mode selection. 2069 // io_register={ "" 0 => 2070 // """"CONFMODE[0]"""""" "" 1 => 2071 // """"CONFMODE[1]"""""" "" 2 => 2072 // """"CONFMODE[2]"""""" "" 3 => 2073 // """"CONFMODE[3]"""" 4 => 2074 // """"IODEN"""" --> When level ‘1’ 2075 // this disables the PMOS xtors of 2076 // the output stages making them 2077 // open-drain type." it can be used 2078 // for I2C type of peripherals. 5 => 2079 // """"I2MAEN"""" --> Level ‘1’ 2080 // enables the approx 2mA output 2081 // stage""" """ 6 => """"I4MAEN"""" 2082 // --> Level ‘1’ enables the approx 2083 // 4mA output stage""" """ 7 => 2084 // """"I8MAEN"""" --> Level ‘1’ 2085 // enables the approx 8mA output 2086 // stage. Note: any drive strength 2087 // between 2mA and 14mA can be 2088 // obtained with combination of 2mA 2089 // 4mA and 8mA.""" """ 8 => 2090 // """"IWKPUEN"""" --> 10uA pull up 2091 // (weak strength)""" """ 9 => 2092 // """"IWKPDEN"""" --> 10uA pull 2093 // down (weak strength)""" """ 10 => 2094 // """"IOE_N"""" --> output enable 2095 // value. level ‘0’ enables the IDO 2096 // to PAD path. Else PAD is 2097 // tristated (except for the PU/PD 2098 // which are independent)." "Value 2099 // gets latched at rising edge of 2100 // RET33""" """ 11 =>"""" 2101 // IOE_N_OV"""" --> output enable 2102 // overirde. when bit is set to 2103 // logic '1' IOE_N (bit 4) value 2104 // will control IO IOE_N signal else 2105 // IOE_N is control via selected HW 2106 // logic. strong PULL UP and PULL 2107 // Down control is disabled for all 2108 // IO's. both controls are tied to 2109 // logic level '0'. 2110 2111 #define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_S 0 2112 //****************************************************************************** 2113 // 2114 // The following are defines for the bit fields in the 2115 // OCP_SHARED_O_GPIO_PAD_CONFIG_23 register. 2116 // 2117 //****************************************************************************** 2118 #define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_M \ 2119 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 2120 // used for PAD IO mode selection. 2121 // io_register={ "" 0 => 2122 // """"CONFMODE[0]"""""" "" 1 => 2123 // """"CONFMODE[1]"""""" "" 2 => 2124 // """"CONFMODE[2]"""""" "" 3 => 2125 // """"CONFMODE[3]"""" 4 => 2126 // """"IODEN"""" --> When level ‘1’ 2127 // this disables the PMOS xtors of 2128 // the output stages making them 2129 // open-drain type." it can be used 2130 // for I2C type of peripherals. 5 => 2131 // """"I2MAEN"""" --> Level ‘1’ 2132 // enables the approx 2mA output 2133 // stage""" """ 6 => """"I4MAEN"""" 2134 // --> Level ‘1’ enables the approx 2135 // 4mA output stage""" """ 7 => 2136 // """"I8MAEN"""" --> Level ‘1’ 2137 // enables the approx 8mA output 2138 // stage. Note: any drive strength 2139 // between 2mA and 14mA can be 2140 // obtained with combination of 2mA 2141 // 4mA and 8mA.""" """ 8 => 2142 // """"IWKPUEN"""" --> 10uA pull up 2143 // (weak strength)""" """ 9 => 2144 // """"IWKPDEN"""" --> 10uA pull 2145 // down (weak strength)""" """ 10 => 2146 // """"IOE_N"""" --> output enable 2147 // value. level ‘0’ enables the IDO 2148 // to PAD path. Else PAD is 2149 // tristated (except for the PU/PD 2150 // which are independent)." "Value 2151 // gets latched at rising edge of 2152 // RET33""" """ 11 =>"""" 2153 // IOE_N_OV"""" --> output enable 2154 // overirde. when bit is set to 2155 // logic '1' IOE_N (bit 4) value 2156 // will control IO IOE_N signal else 2157 // IOE_N is control via selected HW 2158 // logic. strong PULL UP and PULL 2159 // Down control is disabled for all 2160 // IO's. both controls are tied to 2161 // logic level '0'. 2162 2163 #define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_S 0 2164 //****************************************************************************** 2165 // 2166 // The following are defines for the bit fields in the 2167 // OCP_SHARED_O_GPIO_PAD_CONFIG_24 register. 2168 // 2169 //****************************************************************************** 2170 #define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_M \ 2171 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 2172 // used for PAD IO mode selection. 2173 // io_register={ "" 0 => 2174 // """"CONFMODE[0]"""""" "" 1 => 2175 // """"CONFMODE[1]"""""" "" 2 => 2176 // """"CONFMODE[2]"""""" "" 3 => 2177 // """"CONFMODE[3]"""" 4 => 2178 // """"IODEN"""" --> When level ‘1’ 2179 // this disables the PMOS xtors of 2180 // the output stages making them 2181 // open-drain type." it can be used 2182 // for I2C type of peripherals. 5 => 2183 // """"I2MAEN"""" --> Level ‘1’ 2184 // enables the approx 2mA output 2185 // stage""" """ 6 => """"I4MAEN"""" 2186 // --> Level ‘1’ enables the approx 2187 // 4mA output stage""" """ 7 => 2188 // """"I8MAEN"""" --> Level ‘1’ 2189 // enables the approx 8mA output 2190 // stage. Note: any drive strength 2191 // between 2mA and 14mA can be 2192 // obtained with combination of 2mA 2193 // 4mA and 8mA.""" """ 8 => 2194 // """"IWKPUEN"""" --> 10uA pull up 2195 // (weak strength)""" """ 9 => 2196 // """"IWKPDEN"""" --> 10uA pull 2197 // down (weak strength)""" """ 10 => 2198 // """"IOE_N"""" --> output enable 2199 // value. level ‘0’ enables the IDO 2200 // to PAD path. Else PAD is 2201 // tristated (except for the PU/PD 2202 // which are independent)." "Value 2203 // gets latched at rising edge of 2204 // RET33""" """ 11 =>"""" 2205 // IOE_N_OV"""" --> output enable 2206 // overirde. when bit is set to 2207 // logic '1' IOE_N (bit 4) value 2208 // will control IO IOE_N signal else 2209 // IOE_N is control via selected HW 2210 // logic. strong PULL UP and PULL 2211 // Down control is disabled for all 2212 // IO's. both controls are tied to 2213 // logic level '0'. 2214 2215 #define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_S 0 2216 //****************************************************************************** 2217 // 2218 // The following are defines for the bit fields in the 2219 // OCP_SHARED_O_GPIO_PAD_CONFIG_25 register. 2220 // 2221 //****************************************************************************** 2222 #define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_M \ 2223 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 2224 // used for PAD IO mode selection. 2225 // io_register={ "" 0 => 2226 // """"CONFMODE[0]"""""" "" 1 => 2227 // """"CONFMODE[1]"""""" "" 2 => 2228 // """"CONFMODE[2]"""""" "" 3 => 2229 // """"CONFMODE[3]"""" 4 => 2230 // """"IODEN"""" --> When level ‘1’ 2231 // this disables the PMOS xtors of 2232 // the output stages making them 2233 // open-drain type." it can be used 2234 // for I2C type of peripherals. 5 => 2235 // """"I2MAEN"""" --> Level ‘1’ 2236 // enables the approx 2mA output 2237 // stage""" """ 6 => """"I4MAEN"""" 2238 // --> Level ‘1’ enables the approx 2239 // 4mA output stage""" """ 7 => 2240 // """"I8MAEN"""" --> Level ‘1’ 2241 // enables the approx 8mA output 2242 // stage. Note: any drive strength 2243 // between 2mA and 14mA can be 2244 // obtained with combination of 2mA 2245 // 4mA and 8mA.""" """ 8 => 2246 // """"IWKPUEN"""" --> 10uA pull up 2247 // (weak strength)""" """ 9 => 2248 // """"IWKPDEN"""" --> 10uA pull 2249 // down (weak strength)""" """ 10 => 2250 // """"IOE_N"""" --> output enable 2251 // value. level ‘0’ enables the IDO 2252 // to PAD path. Else PAD is 2253 // tristated (except for the PU/PD 2254 // which are independent)." "Value 2255 // gets latched at rising edge of 2256 // RET33""" """ 11 =>"""" 2257 // IOE_N_OV"""" --> output enable 2258 // overirde. when bit is set to 2259 // logic '1' IOE_N (bit 4) value 2260 // will control IO IOE_N signal else 2261 // IOE_N is control via selected HW 2262 // logic. strong PULL UP and PULL 2263 // Down control is disabled for all 2264 // IO's. both controls are tied to 2265 // logic level '0'. 2266 2267 #define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_S 0 2268 //****************************************************************************** 2269 // 2270 // The following are defines for the bit fields in the 2271 // OCP_SHARED_O_GPIO_PAD_CONFIG_26 register. 2272 // 2273 //****************************************************************************** 2274 #define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_M \ 2275 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 2276 // used for PAD IO mode selection. 2277 // io_register={ "" 0 => 2278 // """"CONFMODE[0]"""""" "" 1 => 2279 // """"CONFMODE[1]"""""" "" 2 => 2280 // """"CONFMODE[2]"""""" "" 3 => 2281 // """"CONFMODE[3]"""" 4 => 2282 // """"IODEN"""" --> When level ‘1’ 2283 // this disables the PMOS xtors of 2284 // the output stages making them 2285 // open-drain type." it can be used 2286 // for I2C type of peripherals. 5 => 2287 // """"I2MAEN"""" --> Level ‘1’ 2288 // enables the approx 2mA output 2289 // stage""" """ 6 => """"I4MAEN"""" 2290 // --> Level ‘1’ enables the approx 2291 // 4mA output stage""" """ 7 => 2292 // """"I8MAEN"""" --> Level ‘1’ 2293 // enables the approx 8mA output 2294 // stage. Note: any drive strength 2295 // between 2mA and 14mA can be 2296 // obtained with combination of 2mA 2297 // 4mA and 8mA.""" """ 8 => 2298 // """"IWKPUEN"""" --> 10uA pull up 2299 // (weak strength)""" """ 9 => 2300 // """"IWKPDEN"""" --> 10uA pull 2301 // down (weak strength)""" """ 10 => 2302 // """"IOE_N"""" --> output enable 2303 // value. level ‘0’ enables the IDO 2304 // to PAD path. Else PAD is 2305 // tristated (except for the PU/PD 2306 // which are independent)." "Value 2307 // gets latched at rising edge of 2308 // RET33""" """ 11 =>"""" 2309 // IOE_N_OV"""" --> output enable 2310 // overirde. when bit is set to 2311 // logic '1' IOE_N (bit 4) value 2312 // will control IO IOE_N signal else 2313 // IOE_N is control via selected HW 2314 // logic. strong PULL UP and PULL 2315 // Down control is disabled for all 2316 // IO's. both controls are tied to 2317 // logic level '0'. 2318 2319 #define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_S 0 2320 //****************************************************************************** 2321 // 2322 // The following are defines for the bit fields in the 2323 // OCP_SHARED_O_GPIO_PAD_CONFIG_27 register. 2324 // 2325 //****************************************************************************** 2326 #define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_M \ 2327 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 2328 // used for PAD IO mode selection. 2329 // io_register={ "" 0 => 2330 // """"CONFMODE[0]"""""" "" 1 => 2331 // """"CONFMODE[1]"""""" "" 2 => 2332 // """"CONFMODE[2]"""""" "" 3 => 2333 // """"CONFMODE[3]"""" 4 => 2334 // """"IODEN"""" --> When level ‘1’ 2335 // this disables the PMOS xtors of 2336 // the output stages making them 2337 // open-drain type." it can be used 2338 // for I2C type of peripherals. 5 => 2339 // """"I2MAEN"""" --> Level ‘1’ 2340 // enables the approx 2mA output 2341 // stage""" """ 6 => """"I4MAEN"""" 2342 // --> Level ‘1’ enables the approx 2343 // 4mA output stage""" """ 7 => 2344 // """"I8MAEN"""" --> Level ‘1’ 2345 // enables the approx 8mA output 2346 // stage. Note: any drive strength 2347 // between 2mA and 14mA can be 2348 // obtained with combination of 2mA 2349 // 4mA and 8mA.""" """ 8 => 2350 // """"IWKPUEN"""" --> 10uA pull up 2351 // (weak strength)""" """ 9 => 2352 // """"IWKPDEN"""" --> 10uA pull 2353 // down (weak strength)""" """ 10 => 2354 // """"IOE_N"""" --> output enable 2355 // value. level ‘0’ enables the IDO 2356 // to PAD path. Else PAD is 2357 // tristated (except for the PU/PD 2358 // which are independent)." "Value 2359 // gets latched at rising edge of 2360 // RET33""" """ 11 =>"""" 2361 // IOE_N_OV"""" --> output enable 2362 // overirde. when bit is set to 2363 // logic '1' IOE_N (bit 4) value 2364 // will control IO IOE_N signal else 2365 // IOE_N is control via selected HW 2366 // logic. strong PULL UP and PULL 2367 // Down control is disabled for all 2368 // IO's. both controls are tied to 2369 // logic level '0'. 2370 2371 #define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_S 0 2372 //****************************************************************************** 2373 // 2374 // The following are defines for the bit fields in the 2375 // OCP_SHARED_O_GPIO_PAD_CONFIG_28 register. 2376 // 2377 //****************************************************************************** 2378 #define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_M \ 2379 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 2380 // used for PAD IO mode selection. 2381 // io_register={ "" 0 => 2382 // """"CONFMODE[0]"""""" "" 1 => 2383 // """"CONFMODE[1]"""""" "" 2 => 2384 // """"CONFMODE[2]"""""" "" 3 => 2385 // """"CONFMODE[3]"""" 4 => 2386 // """"IODEN"""" --> When level ‘1’ 2387 // this disables the PMOS xtors of 2388 // the output stages making them 2389 // open-drain type." it can be used 2390 // for I2C type of peripherals. 5 => 2391 // """"I2MAEN"""" --> Level ‘1’ 2392 // enables the approx 2mA output 2393 // stage""" """ 6 => """"I4MAEN"""" 2394 // --> Level ‘1’ enables the approx 2395 // 4mA output stage""" """ 7 => 2396 // """"I8MAEN"""" --> Level ‘1’ 2397 // enables the approx 8mA output 2398 // stage. Note: any drive strength 2399 // between 2mA and 14mA can be 2400 // obtained with combination of 2mA 2401 // 4mA and 8mA.""" """ 8 => 2402 // """"IWKPUEN"""" --> 10uA pull up 2403 // (weak strength)""" """ 9 => 2404 // """"IWKPDEN"""" --> 10uA pull 2405 // down (weak strength)""" """ 10 => 2406 // """"IOE_N"""" --> output enable 2407 // value. level ‘0’ enables the IDO 2408 // to PAD path. Else PAD is 2409 // tristated (except for the PU/PD 2410 // which are independent)." "Value 2411 // gets latched at rising edge of 2412 // RET33""" """ 11 =>"""" 2413 // IOE_N_OV"""" --> output enable 2414 // overirde. when bit is set to 2415 // logic '1' IOE_N (bit 4) value 2416 // will control IO IOE_N signal else 2417 // IOE_N is control via selected HW 2418 // logic. strong PULL UP and PULL 2419 // Down control is disabled for all 2420 // IO's. both controls are tied to 2421 // logic level '0'. 2422 2423 #define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_S 0 2424 //****************************************************************************** 2425 // 2426 // The following are defines for the bit fields in the 2427 // OCP_SHARED_O_GPIO_PAD_CONFIG_29 register. 2428 // 2429 //****************************************************************************** 2430 #define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_M \ 2431 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 2432 // used for PAD IO mode selection. 2433 // io_register={ "" 0 => 2434 // """"CONFMODE[0]"""""" "" 1 => 2435 // """"CONFMODE[1]"""""" "" 2 => 2436 // """"CONFMODE[2]"""""" "" 3 => 2437 // """"CONFMODE[3]"""" 4 => 2438 // """"IODEN"""" --> When level ‘1’ 2439 // this disables the PMOS xtors of 2440 // the output stages making them 2441 // open-drain type." it can be used 2442 // for I2C type of peripherals. 5 => 2443 // """"I2MAEN"""" --> Level ‘1’ 2444 // enables the approx 2mA output 2445 // stage""" """ 6 => """"I4MAEN"""" 2446 // --> Level ‘1’ enables the approx 2447 // 4mA output stage""" """ 7 => 2448 // """"I8MAEN"""" --> Level ‘1’ 2449 // enables the approx 8mA output 2450 // stage. Note: any drive strength 2451 // between 2mA and 14mA can be 2452 // obtained with combination of 2mA 2453 // 4mA and 8mA.""" """ 8 => 2454 // """"IWKPUEN"""" --> 10uA pull up 2455 // (weak strength)""" """ 9 => 2456 // """"IWKPDEN"""" --> 10uA pull 2457 // down (weak strength)""" """ 10 => 2458 // """"IOE_N"""" --> output enable 2459 // value. level ‘0’ enables the IDO 2460 // to PAD path. Else PAD is 2461 // tristated (except for the PU/PD 2462 // which are independent)." "Value 2463 // gets latched at rising edge of 2464 // RET33""" """ 11 =>"""" 2465 // IOE_N_OV"""" --> output enable 2466 // overirde. when bit is set to 2467 // logic '1' IOE_N (bit 4) value 2468 // will control IO IOE_N signal else 2469 // IOE_N is control via selected HW 2470 // logic. strong PULL UP and PULL 2471 // Down control is disabled for all 2472 // IO's. both controls are tied to 2473 // logic level '0'. 2474 2475 #define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_S 0 2476 //****************************************************************************** 2477 // 2478 // The following are defines for the bit fields in the 2479 // OCP_SHARED_O_GPIO_PAD_CONFIG_30 register. 2480 // 2481 //****************************************************************************** 2482 #define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_M \ 2483 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 2484 // used for PAD IO mode selection. 2485 // io_register={ "" 0 => 2486 // """"CONFMODE[0]"""""" "" 1 => 2487 // """"CONFMODE[1]"""""" "" 2 => 2488 // """"CONFMODE[2]"""""" "" 3 => 2489 // """"CONFMODE[3]"""" 4 => 2490 // """"IODEN"""" --> When level ‘1’ 2491 // this disables the PMOS xtors of 2492 // the output stages making them 2493 // open-drain type." it can be used 2494 // for I2C type of peripherals. 5 => 2495 // """"I2MAEN"""" --> Level ‘1’ 2496 // enables the approx 2mA output 2497 // stage""" """ 6 => """"I4MAEN"""" 2498 // --> Level ‘1’ enables the approx 2499 // 4mA output stage""" """ 7 => 2500 // """"I8MAEN"""" --> Level ‘1’ 2501 // enables the approx 8mA output 2502 // stage. Note: any drive strength 2503 // between 2mA and 14mA can be 2504 // obtained with combination of 2mA 2505 // 4mA and 8mA.""" """ 8 => 2506 // """"IWKPUEN"""" --> 10uA pull up 2507 // (weak strength)""" """ 9 => 2508 // """"IWKPDEN"""" --> 10uA pull 2509 // down (weak strength)""" """ 10 => 2510 // """"IOE_N"""" --> output enable 2511 // value. level ‘0’ enables the IDO 2512 // to PAD path. Else PAD is 2513 // tristated (except for the PU/PD 2514 // which are independent)." "Value 2515 // gets latched at rising edge of 2516 // RET33""" """ 11 =>"""" 2517 // IOE_N_OV"""" --> output enable 2518 // overirde. when bit is set to 2519 // logic '1' IOE_N (bit 4) value 2520 // will control IO IOE_N signal else 2521 // IOE_N is control via selected HW 2522 // logic. strong PULL UP and PULL 2523 // Down control is disabled for all 2524 // IO's. both controls are tied to 2525 // logic level '0'. 2526 2527 #define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_S 0 2528 //****************************************************************************** 2529 // 2530 // The following are defines for the bit fields in the 2531 // OCP_SHARED_O_GPIO_PAD_CONFIG_31 register. 2532 // 2533 //****************************************************************************** 2534 #define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_M \ 2535 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 2536 // used for PAD IO mode selection. 2537 // io_register={ "" 0 => 2538 // """"CONFMODE[0]"""""" "" 1 => 2539 // """"CONFMODE[1]"""""" "" 2 => 2540 // """"CONFMODE[2]"""""" "" 3 => 2541 // """"CONFMODE[3]"""" 4 => 2542 // """"IODEN"""" --> When level ‘1’ 2543 // this disables the PMOS xtors of 2544 // the output stages making them 2545 // open-drain type." it can be used 2546 // for I2C type of peripherals. 5 => 2547 // """"I2MAEN"""" --> Level ‘1’ 2548 // enables the approx 2mA output 2549 // stage""" """ 6 => """"I4MAEN"""" 2550 // --> Level ‘1’ enables the approx 2551 // 4mA output stage""" """ 7 => 2552 // """"I8MAEN"""" --> Level ‘1’ 2553 // enables the approx 8mA output 2554 // stage. Note: any drive strength 2555 // between 2mA and 14mA can be 2556 // obtained with combination of 2mA 2557 // 4mA and 8mA.""" """ 8 => 2558 // """"IWKPUEN"""" --> 10uA pull up 2559 // (weak strength)""" """ 9 => 2560 // """"IWKPDEN"""" --> 10uA pull 2561 // down (weak strength)""" """ 10 => 2562 // """"IOE_N"""" --> output enable 2563 // value. level ‘0’ enables the IDO 2564 // to PAD path. Else PAD is 2565 // tristated (except for the PU/PD 2566 // which are independent)." "Value 2567 // gets latched at rising edge of 2568 // RET33""" """ 11 =>"""" 2569 // IOE_N_OV"""" --> output enable 2570 // overirde. when bit is set to 2571 // logic '1' IOE_N (bit 4) value 2572 // will control IO IOE_N signal else 2573 // IOE_N is control via selected HW 2574 // logic. strong PULL UP and PULL 2575 // Down control is disabled for all 2576 // IO's. both controls are tied to 2577 // logic level '0'. 2578 2579 #define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_S 0 2580 //****************************************************************************** 2581 // 2582 // The following are defines for the bit fields in the 2583 // OCP_SHARED_O_GPIO_PAD_CONFIG_32 register. 2584 // 2585 //****************************************************************************** 2586 #define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_M \ 2587 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is 2588 // used for PAD IO mode selection. 2589 // io_register={ "" 0 => 2590 // """"CONFMODE[0]"""""" "" 1 => 2591 // """"CONFMODE[1]"""""" "" 2 => 2592 // """"CONFMODE[2]"""""" "" 3 => 2593 // """"CONFMODE[3]"""" 4 => 2594 // """"IODEN"""" --> When level ‘1’ 2595 // this disables the PMOS xtors of 2596 // the output stages making them 2597 // open-drain type." it can be used 2598 // for I2C type of peripherals. 5 => 2599 // """"I2MAEN"""" --> Level ‘1’ 2600 // enables the approx 2mA output 2601 // stage""" """ 6 => """"I4MAEN"""" 2602 // --> Level ‘1’ enables the approx 2603 // 4mA output stage""" """ 7 => 2604 // """"I8MAEN"""" --> Level ‘1’ 2605 // enables the approx 8mA output 2606 // stage. Note: any drive strength 2607 // between 2mA and 14mA can be 2608 // obtained with combination of 2mA 2609 // 4mA and 8mA.""" """ 8 => 2610 // """"IWKPUEN"""" --> 10uA pull up 2611 // (weak strength)""" """ 9 => 2612 // """"IWKPDEN"""" --> 10uA pull 2613 // down (weak strength)""" """ 10 => 2614 // """"IOE_N"""" --> output enable 2615 // value. level ‘0’ enables the IDO 2616 // to PAD path. Else PAD is 2617 // tristated (except for the PU/PD 2618 // which are independent)." "Value 2619 // gets latched at rising edge of 2620 // RET33""" """ 11 =>"""" 2621 // IOE_N_OV"""" --> output enable 2622 // overirde. when bit is set to 2623 // logic '1' IOE_N (bit 4) value 2624 // will control IO IOE_N signal else 2625 // IOE_N is control via selected HW 2626 // logic. strong PULL UP and PULL 2627 // Down control is disabled for all 2628 // IO's. both controls are tied to 2629 // logic level '0'. 2630 2631 #define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_S 0 2632 //****************************************************************************** 2633 // 2634 // The following are defines for the bit fields in the 2635 // OCP_SHARED_O_GPIO_PAD_CONFIG_33 register. 2636 // 2637 //****************************************************************************** 2638 #define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_M \ 2639 0x0000003F // GPIO 0 register: "Bit 0 - 3 is 2640 // used for PAD IO mode selection. 2641 // io_register={ "" 0 => 2642 // """"CONFMODE[0]"""""" "" 1 => 2643 // """"CONFMODE[1]"""""" "" 2 => 2644 // """"CONFMODE[2]"""""" "" 3 => 2645 // """"CONFMODE[3]"""" 4 => 2646 // """"IOE_N"""" --> output enable 2647 // value. level ‘0’ enables the IDO 2648 // to PAD path. Else PAD is 2649 // tristated (except for the PU/PD 2650 // which are independent)." "Value 2651 // gets latched at rising edge of 2652 // RET33""" """ 5 =>"""" 2653 // IOE_N_OV"""" --> output enable 2654 // overirde. when bit is set to 2655 // logic '1' IOE_N (bit 4) value 2656 // will control IO IOE_N signal else 2657 // IOE_N is control via selected HW 2658 // logic. strong PULL UP and PULL 2659 // Down control is disabled for all 2660 // IO's. both controls are tied to 2661 // logic level '0'. IODEN and I8MAEN 2662 // is diesabled for all development 2663 // IO's. These signals are tied to 2664 // logic level '0'. common control 2665 // is implemented for I2MAEN, 2666 // I4MAEN, WKPU, WKPD control . 2667 // refer dev_pad_cmn_config register 2668 // bits. 2669 2670 #define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_S 0 2671 //****************************************************************************** 2672 // 2673 // The following are defines for the bit fields in the 2674 // OCP_SHARED_O_GPIO_PAD_CONFIG_34 register. 2675 // 2676 //****************************************************************************** 2677 #define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_M \ 2678 0x0000003F // GPIO 0 register: "Bit 0 - 3 is 2679 // used for PAD IO mode selection. 2680 // io_register={ "" 0 => 2681 // """"CONFMODE[0]"""""" "" 1 => 2682 // """"CONFMODE[1]"""""" "" 2 => 2683 // """"CONFMODE[2]"""""" "" 3 => 2684 // """"CONFMODE[3]"""" 4 => 2685 // """"IOE_N"""" --> output enable 2686 // value. level ‘0’ enables the IDO 2687 // to PAD path. Else PAD is 2688 // tristated (except for the PU/PD 2689 // which are independent)." "Value 2690 // gets latched at rising edge of 2691 // RET33""" """ 5 =>"""" 2692 // IOE_N_OV"""" --> output enable 2693 // overirde. when bit is set to 2694 // logic '1' IOE_N (bit 4) value 2695 // will control IO IOE_N signal else 2696 // IOE_N is control via selected HW 2697 // logic. strong PULL UP and PULL 2698 // Down control is disabled for all 2699 // IO's. both controls are tied to 2700 // logic level '0'. IODEN and I8MAEN 2701 // is diesabled for all development 2702 // IO's. These signals are tied to 2703 // logic level '0'. common control 2704 // is implemented for I2MAEN, 2705 // I4MAEN, WKPU, WKPD control . 2706 // refer dev_pad_cmn_config register 2707 // bits. 2708 2709 #define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_S 0 2710 //****************************************************************************** 2711 // 2712 // The following are defines for the bit fields in the 2713 // OCP_SHARED_O_GPIO_PAD_CONFIG_35 register. 2714 // 2715 //****************************************************************************** 2716 #define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_M \ 2717 0x0000003F // GPIO 0 register: "Bit 0 - 3 is 2718 // used for PAD IO mode selection. 2719 // io_register={ "" 0 => 2720 // """"CONFMODE[0]"""""" "" 1 => 2721 // """"CONFMODE[1]"""""" "" 2 => 2722 // """"CONFMODE[2]"""""" "" 3 => 2723 // """"CONFMODE[3]"""" 4 => 2724 // """"IOE_N"""" --> output enable 2725 // value. level ‘0’ enables the IDO 2726 // to PAD path. Else PAD is 2727 // tristated (except for the PU/PD 2728 // which are independent)." "Value 2729 // gets latched at rising edge of 2730 // RET33""" """ 5 =>"""" 2731 // IOE_N_OV"""" --> output enable 2732 // overirde. when bit is set to 2733 // logic '1' IOE_N (bit 4) value 2734 // will control IO IOE_N signal else 2735 // IOE_N is control via selected HW 2736 // logic. strong PULL UP and PULL 2737 // Down control is disabled for all 2738 // IO's. both controls are tied to 2739 // logic level '0'. IODEN and I8MAEN 2740 // is diesabled for all development 2741 // IO's. These signals are tied to 2742 // logic level '0'. common control 2743 // is implemented for I2MAEN, 2744 // I4MAEN, WKPU, WKPD control . 2745 // refer dev_pad_cmn_config register 2746 // bits. 2747 2748 #define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_S 0 2749 //****************************************************************************** 2750 // 2751 // The following are defines for the bit fields in the 2752 // OCP_SHARED_O_GPIO_PAD_CONFIG_36 register. 2753 // 2754 //****************************************************************************** 2755 #define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_M \ 2756 0x0000003F // GPIO 0 register: "Bit 0 - 3 is 2757 // used for PAD IO mode selection. 2758 // io_register={ "" 0 => 2759 // """"CONFMODE[0]"""""" "" 1 => 2760 // """"CONFMODE[1]"""""" "" 2 => 2761 // """"CONFMODE[2]"""""" "" 3 => 2762 // """"CONFMODE[3]"""" 4 => 2763 // """"IOE_N"""" --> output enable 2764 // value. level ‘0’ enables the IDO 2765 // to PAD path. Else PAD is 2766 // tristated (except for the PU/PD 2767 // which are independent)." "Value 2768 // gets latched at rising edge of 2769 // RET33""" """ 5 =>"""" 2770 // IOE_N_OV"""" --> output enable 2771 // overirde. when bit is set to 2772 // logic '1' IOE_N (bit 4) value 2773 // will control IO IOE_N signal else 2774 // IOE_N is control via selected HW 2775 // logic. strong PULL UP and PULL 2776 // Down control is disabled for all 2777 // IO's. both controls are tied to 2778 // logic level '0'. IODEN and I8MAEN 2779 // is diesabled for all development 2780 // IO's. These signals are tied to 2781 // logic level '0'. common control 2782 // is implemented for I2MAEN, 2783 // I4MAEN, WKPU, WKPD control . 2784 // refer dev_pad_cmn_config register 2785 // bits. 2786 2787 #define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_S 0 2788 //****************************************************************************** 2789 // 2790 // The following are defines for the bit fields in the 2791 // OCP_SHARED_O_GPIO_PAD_CONFIG_37 register. 2792 // 2793 //****************************************************************************** 2794 #define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_M \ 2795 0x0000003F // GPIO 0 register: "Bit 0 - 3 is 2796 // used for PAD IO mode selection. 2797 // io_register={ "" 0 => 2798 // """"CONFMODE[0]"""""" "" 1 => 2799 // """"CONFMODE[1]"""""" "" 2 => 2800 // """"CONFMODE[2]"""""" "" 3 => 2801 // """"CONFMODE[3]"""" 4 => 2802 // """"IOE_N"""" --> output enable 2803 // value. level ‘0’ enables the IDO 2804 // to PAD path. Else PAD is 2805 // tristated (except for the PU/PD 2806 // which are independent)." "Value 2807 // gets latched at rising edge of 2808 // RET33""" """ 5 =>"""" 2809 // IOE_N_OV"""" --> output enable 2810 // overirde. when bit is set to 2811 // logic '1' IOE_N (bit 4) value 2812 // will control IO IOE_N signal else 2813 // IOE_N is control via selected HW 2814 // logic. strong PULL UP and PULL 2815 // Down control is disabled for all 2816 // IO's. both controls are tied to 2817 // logic level '0'. IODEN and I8MAEN 2818 // is diesabled for all development 2819 // IO's. These signals are tied to 2820 // logic level '0'. common control 2821 // is implemented for I2MAEN, 2822 // I4MAEN, WKPU, WKPD control . 2823 // refer dev_pad_cmn_config register 2824 // bits. 2825 2826 #define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_S 0 2827 //****************************************************************************** 2828 // 2829 // The following are defines for the bit fields in the 2830 // OCP_SHARED_O_GPIO_PAD_CONFIG_38 register. 2831 // 2832 //****************************************************************************** 2833 #define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_M \ 2834 0x0000003F // GPIO 0 register: "Bit 0 - 3 is 2835 // used for PAD IO mode selection. 2836 // io_register={ "" 0 => 2837 // """"CONFMODE[0]"""""" "" 1 => 2838 // """"CONFMODE[1]"""""" "" 2 => 2839 // """"CONFMODE[2]"""""" "" 3 => 2840 // """"CONFMODE[3]"""" 4 => 2841 // """"IOE_N"""" --> output enable 2842 // value. level ‘0’ enables the IDO 2843 // to PAD path. Else PAD is 2844 // tristated (except for the PU/PD 2845 // which are independent)." "Value 2846 // gets latched at rising edge of 2847 // RET33""" """ 5 =>"""" 2848 // IOE_N_OV"""" --> output enable 2849 // overirde. when bit is set to 2850 // logic '1' IOE_N (bit 4) value 2851 // will control IO IOE_N signal else 2852 // IOE_N is control via selected HW 2853 // logic. strong PULL UP and PULL 2854 // Down control is disabled for all 2855 // IO's. both controls are tied to 2856 // logic level '0'. IODEN and I8MAEN 2857 // is diesabled for all development 2858 // IO's. These signals are tied to 2859 // logic level '0'. common control 2860 // is implemented for I2MAEN, 2861 // I4MAEN, WKPU, WKPD control . 2862 // refer dev_pad_cmn_config register 2863 // bits. 2864 2865 #define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_S 0 2866 //****************************************************************************** 2867 // 2868 // The following are defines for the bit fields in the 2869 // OCP_SHARED_O_GPIO_PAD_CONFIG_39 register. 2870 // 2871 //****************************************************************************** 2872 #define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_M \ 2873 0x0000003F // GPIO 0 register: "Bit 0 - 3 is 2874 // used for PAD IO mode selection. 2875 // io_register={ "" 0 => 2876 // """"CONFMODE[0]"""""" "" 1 => 2877 // """"CONFMODE[1]"""""" "" 2 => 2878 // """"CONFMODE[2]"""""" "" 3 => 2879 // """"CONFMODE[3]"""" 4 => 2880 // """"IOE_N"""" --> output enable 2881 // value. level ‘0’ enables the IDO 2882 // to PAD path. Else PAD is 2883 // tristated (except for the PU/PD 2884 // which are independent)." "Value 2885 // gets latched at rising edge of 2886 // RET33""" """ 5 =>"""" 2887 // IOE_N_OV"""" --> output enable 2888 // overirde. when bit is set to 2889 // logic '1' IOE_N (bit 4) value 2890 // will control IO IOE_N signal else 2891 // IOE_N is control via selected HW 2892 // logic. strong PULL UP and PULL 2893 // Down control is disabled for all 2894 // IO's. both controls are tied to 2895 // logic level '0'. IODEN and I8MAEN 2896 // is diesabled for all development 2897 // IO's. These signals are tied to 2898 // logic level '0'. common control 2899 // is implemented for I2MAEN, 2900 // I4MAEN, WKPU, WKPD control . 2901 // refer dev_pad_cmn_config register 2902 // bits. 2903 2904 #define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_S 0 2905 //****************************************************************************** 2906 // 2907 // The following are defines for the bit fields in the 2908 // OCP_SHARED_O_GPIO_PAD_CONFIG_40 register. 2909 // 2910 //****************************************************************************** 2911 #define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_M \ 2912 0x0007FFFF // GPIO 0 register: "Bit 0 - 3 is 2913 // used for PAD IO mode selection. 2914 // io_register={ "" 0 => 2915 // """"CONFMODE[0]"""""" "" 1 => 2916 // """"CONFMODE[1]"""""" "" 2 => 2917 // """"CONFMODE[2]"""""" "" 3 => 2918 // """"CONFMODE[3]"""" 4 => 2919 // """"IODEN"""" --> When level ‘1’ 2920 // this disables the PMOS xtors of 2921 // the output stages making them 2922 // open-drain type." "For example in 2923 // case of I2C Value gets latched at 2924 // rising edge of RET33.""" """ 5 => 2925 // """"I2MAEN"""" --> Level ‘1’ 2926 // enables the approx 2mA output 2927 // stage""" """ 6 => """"I4MAEN"""" 2928 // --> Level ‘1’ enables the approx 2929 // 4mA output stage""" """ 7 => 2930 // """"I8MAEN"""" --> Level ‘1’ 2931 // enables the approx 8mA output 2932 // stage. Note: any drive strength 2933 // between 2mA and 14mA can be 2934 // obtained with combination of 2mA 2935 // 4mA and 8mA.""" """ 8 => 2936 // """"IWKPUEN"""" --> 10uA pull up 2937 // (weak strength)""" """ 9 => 2938 // """"IWKPDEN"""" --> 10uA pull 2939 // down (weak strength)""" """ 10 => 2940 // """"IOE_N"""" --> output enable 2941 // value. level ‘0’ enables the IDO 2942 // to PAD path. Else PAD is 2943 // tristated (except for the PU/PD 2944 // which are independent)." "Value 2945 // gets latched at rising edge of 2946 // RET33""" """ 11 =>"""" 2947 // IOE_N_OV"""" --> output enable 2948 // overirde. when bit is set to 2949 // logic '1' IOE_N (bit 4) value 2950 // will control IO IOE_N signal else 2951 // IOE_N is control via selected HW 2952 // logic. strong PULL UP and PULL 2953 // Down control is disabled for all 2954 // IO's. both controls are tied to 2955 // logic level '0'. 2956 2957 #define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_S 0 2958 //****************************************************************************** 2959 // 2960 // The following are defines for the bit fields in the 2961 // OCP_SHARED_O_GPIO_PAD_CMN_CONFIG register. 2962 // 2963 //****************************************************************************** 2964 #define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_A_EN \ 2965 0x00000080 // when '1' enable ISO A control to 2966 // D2D Pads else ISO is disabled. 2967 // For these PADS to be functional 2968 // this signals should be set 0. 2969 2970 #define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_Y_EN \ 2971 0x00000040 // when '1' enable ISO Y control to 2972 // D2D Pads else ISO is disabled. 2973 // For these PADS to be functional 2974 // this signals should be set 0. 2975 2976 #define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_JTAG_IDIEN \ 2977 0x00000020 // If level ‘1’ enables the PAD to 2978 // ODI path for JTAG PADS [PAD 23, 2979 // 24, 28, 29]. Else ODI is pulled 2980 // ‘Low’ regardless of PAD level." 2981 // "Value gets latched at rising 2982 // edge of RET33.""" """ 2983 2984 #define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_M \ 2985 0x00000018 // 00’: hysteriris = 10% of VDDS 2986 // (difference between upper and 2987 // lower threshold of the schmit 2988 // trigger) ‘01’: hysteriris = 20% 2989 // of VDDS (difference between upper 2990 // and lower threshold of the schmit 2991 // trigger) ‘10’: hysteriris = 30% 2992 // of VDDS (difference between upper 2993 // and lower threshold of the schmit 2994 // trigger) ‘11’: hysteriris = 40% 2995 // of VDDS (difference between upper 2996 // and lower threshold of the schmit 2997 // trigger)" """ 2998 2999 #define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_S 3 3000 #define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTEN \ 3001 0x00000004 // If logic ‘0’ there is no 3002 // hysteresis. Set to ‘1’ to enable 3003 // hysteresis. Leave the choice to 3004 // customers""" 3005 3006 #define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IBIASEN \ 3007 0x00000002 // Normal functional operation set 3008 // this to logic ‘1’ to increase the 3009 // speed of the o/p buffer at the 3010 // cost of 0.2uA static current 3011 // consumption per IO. During IDDQ 3012 // test and during Hibernate this 3013 // would be forced to logic ‘0’. 3014 // Value is not latched at rising 3015 // edge of RET33."" 3016 3017 #define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IDIEN \ 3018 0x00000001 // If level ‘1’ enables the PAD to 3019 // ODI path. Else ODI is pulled 3020 // ‘Low’ regardless of PAD level." 3021 // "Value gets latched at rising 3022 // edge of RET33.""" """ 3023 3024 //****************************************************************************** 3025 // 3026 // The following are defines for the bit fields in the 3027 // OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG register. 3028 // 3029 //****************************************************************************** 3030 #define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_M \ 3031 0x0000003F // this register implements common 3032 // IO control to all devement mode 3033 // PADs; these PADs are DEV_PAD33 to 3034 // DEV_PAD39. Bit [1:0] : Drive 3035 // strength control. These 2 bits 3036 // are connected to DEV PAD drive 3037 // strength control. possible drive 3038 // stregnths are 2MA, 4MA and 6 MA 3039 // for the these IO's. bit 0: when 3040 // set to logic value '1' enable 2MA 3041 // drive strength for DEVPAD01 to 07 3042 // bit 1: when set to logic value 3043 // '1' enable 4MA drive strength for 3044 // DEVPAD01 to 07. bit[3:2] : WK 3045 // PULL UP and PULL down control. 3046 // These 2 bits provide IWKPUEN and 3047 // IWKPDEN control for all DEV IO's. 3048 // bit 2: when set to logic value 3049 // '1' enable WKPU to DEVPAD01 to 07 3050 // bit 3: when set to logic value 3051 // '1' enable WKPD to DEVPAD01 to 3052 // 07. bit 4: WK PULL control for 3053 // DEV_PKG_DETECT pin. when '1' 3054 // pullup enabled else it is 3055 // disable. bit 5: when set to logic 3056 // value '1' enable 8MA drive 3057 // strength for DEVPAD01 to 07. 3058 3059 #define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_S 0 3060 //****************************************************************************** 3061 // 3062 // The following are defines for the bit fields in the 3063 // OCP_SHARED_O_D2D_TOSTACK_PAD_CONF register. 3064 // 3065 //****************************************************************************** 3066 #define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_M \ 3067 0x1FFFFFFF // OEN/OEN2X control. When 0 : Act 3068 // as input buffer else output 3069 // buffer with drive strength 2. 3070 // this register control OEN2X pin 3071 // of D2D TOSTACK PAD: OEN1X and 3072 // OEN2X decoding is as follows: 3073 // "when ""00"" :" "when ""01"" : 3074 // dirve strength is '1' and output 3075 // buffer enabled." "when ""10"" : 3076 // drive strength is 2 and output 3077 // buffer is disabled." "when ""11"" 3078 // : dirve strength is '3' and 3079 // output buffer enabled." 3080 3081 #define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_S 0 3082 //****************************************************************************** 3083 // 3084 // The following are defines for the bit fields in the 3085 // OCP_SHARED_O_D2D_MISC_PAD_CONF register. 3086 // 3087 //****************************************************************************** 3088 #define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_POR_RESET_N \ 3089 0x00000200 // This register provide OEN2X 3090 // control to D2D PADS OEN/OEN2X 3091 // control. When 0 : Act as input 3092 // buffer else output buffer with 3093 // drive strength 2. 3094 3095 #define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_RESET_N \ 3096 0x00000100 // OEN/OEN2X control. When 0 : Act 3097 // as input buffer else output 3098 // buffer with drive strength 2. 3099 3100 #define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_HCLK \ 3101 0x00000080 // OEN/OEN2X control. When 0 : Act 3102 // as input buffer else output 3103 // buffer with drive strength 2. 3104 3105 #define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TCK \ 3106 0x00000040 // OEN/OEN2X control. When 0 : Act 3107 // as input buffer else output 3108 // buffer with drive strength 2. 3109 3110 #define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TMS \ 3111 0x00000020 // OEN/OEN2X control. When 0 : Act 3112 // as input buffer else output 3113 // buffer with drive strength 2. 3114 3115 #define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TDI \ 3116 0x00000010 // OEN/OEN2X control. When 0 : Act 3117 // as input buffer else output 3118 // buffer with drive strength 2. 3119 3120 #define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_PIOSC \ 3121 0x00000008 // OEN/OEN2X control. When 0 : Act 3122 // as input buffer else output 3123 // buffer with drive strength 2. 3124 3125 #define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_M \ 3126 0x00000007 // D2D SPARE PAD OEN/OEN2X control. 3127 // When 0: Act as input buffer else 3128 // output buffer with drive strength 3129 // 2. 3130 3131 #define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_S 0 3132 //****************************************************************************** 3133 // 3134 // The following are defines for the bit fields in the 3135 // OCP_SHARED_O_SOP_CONF_OVERRIDE register. 3136 // 3137 //****************************************************************************** 3138 #define OCP_SHARED_SOP_CONF_OVERRIDE_MEM_SOP_CONF_OVERRIDE \ 3139 0x00000001 // when '1' : signal will ovberride 3140 // SoP setting of JTAG PADS. when 3141 // '0': SoP setting will control 3142 // JTAG PADs [ TDI, TDO, TMS, TCK] 3143 3144 //****************************************************************************** 3145 // 3146 // The following are defines for the bit fields in the 3147 // OCP_SHARED_O_CC3XX_DEBUGSS_STATUS register. 3148 // 3149 //****************************************************************************** 3150 #define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_MCU_JTAGNSW \ 3151 0x00000020 // This register contains debug 3152 // subsystem status bits From APPS 3153 // MCU status bit to indicates 3154 // whether serial wire or 4 pins 3155 // jtag select. 3156 3157 #define OCP_SHARED_CC3XX_DEBUGSS_STATUS_CJTAG_BYPASS_STATUS \ 3158 0x00000010 // cjtag bypass bit select 3159 3160 #define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SW_INTERFACE_SEL_STATUS \ 3161 0x00000008 // serial wire interface bit select 3162 3163 #define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_TAP_ENABLE_STATUS \ 3164 0x00000004 // apps tap enable status 3165 3166 #define OCP_SHARED_CC3XX_DEBUGSS_STATUS_TAPS_ENABLE_STATUS \ 3167 0x00000002 // tap enable status 3168 3169 #define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SSBD_UNLOCK \ 3170 0x00000001 // ssbd unlock status 3171 3172 //****************************************************************************** 3173 // 3174 // The following are defines for the bit fields in the 3175 // OCP_SHARED_O_CC3XX_DEBUGMUX_SEL register. 3176 // 3177 //****************************************************************************** 3178 #define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_M \ 3179 0x0000FFFF // debug mux select register. Upper 3180 // 8 bits are used for debug module 3181 // selection. Lower 8 bit [7:0] used 3182 // inside debug module for selecting 3183 // module specific signals. 3184 // Bits[15:8: when set x"00" : GPRCM 3185 // debug bus. When "o1" : SDIO debug 3186 // debug bus when x"02" : 3187 // autonoumous SPI when x"03" : 3188 // TOPIC when x"04": memss when 3189 // x"25": mcu debug bus : APPS debug 3190 // when x"45": mcu debug bus : NWP 3191 // debug when x"65": mcu debug bus : 3192 // AHB2VBUS debug when x"85": mcu 3193 // debug bus : VBUS2HAB debug when 3194 // x"95": mcu debug bus : RCM debug 3195 // when x"A5": mcu debug bus : 3196 // crypto debug when x"06": WLAN 3197 // debug bus when x"07": debugss bus 3198 // when x"08": ADC debug when x"09": 3199 // SDIO PHY debug bus then "others" 3200 // : no debug is selected 3201 3202 #define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_S 0 3203 //****************************************************************************** 3204 // 3205 // The following are defines for the bit fields in the 3206 // OCP_SHARED_O_ALT_PC_VAL_NW register. 3207 // 3208 //****************************************************************************** 3209 #define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_M \ 3210 0xFFFFFFFF // 32 bit. Program counter value 3211 // for 0x4 address when Alt_pc_en_nw 3212 // is set. 3213 3214 #define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_S 0 3215 //****************************************************************************** 3216 // 3217 // The following are defines for the bit fields in the 3218 // OCP_SHARED_O_ALT_PC_VAL_APPS register. 3219 // 3220 //****************************************************************************** 3221 #define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_M \ 3222 0xFFFFFFFF // 32 bit. Program counter value 3223 // for 0x4 address when 3224 // Alt_pc_en_apps is set 3225 3226 #define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_S 0 3227 //****************************************************************************** 3228 // 3229 // The following are defines for the bit fields in the 3230 // OCP_SHARED_O_SPARE_REG_4 register. 3231 // 3232 //****************************************************************************** 3233 #define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_M \ 3234 0xFFFFFFFE // HW register 3235 3236 #define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_S 1 3237 #define OCP_SHARED_SPARE_REG_4_INVERT_D2D_INTERFACE \ 3238 0x00000001 // Data to the top die launched at 3239 // negative edge instead of positive 3240 // edge. 3241 3242 //****************************************************************************** 3243 // 3244 // The following are defines for the bit fields in the 3245 // OCP_SHARED_O_SPARE_REG_5 register. 3246 // 3247 //****************************************************************************** 3248 #define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_M \ 3249 0xFFFFFFFF // HW register 3250 3251 #define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_S 0 3252 //****************************************************************************** 3253 // 3254 // The following are defines for the bit fields in the 3255 // OCP_SHARED_O_SH_SPI_CS_MASK register. 3256 // 3257 //****************************************************************************** 3258 #define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_M \ 3259 0x0000000F // ( chip select 0 is unmasked 3260 // after reset. When ‘1’ : CS is 3261 // unmasked or else masked. Valid 3262 // configurations are 1000, 0100, 3263 // 0010 or 0001. Any other setting 3264 // can lead to unpredictable 3265 // behavior. 3266 3267 #define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_S 0 3268 //****************************************************************************** 3269 // 3270 // The following are defines for the bit fields in the 3271 // OCP_SHARED_O_CC3XX_DEVICE_TYPE register. 3272 // 3273 //****************************************************************************** 3274 #define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_M \ 3275 0x00000060 // reserved bits tied off "00". 3276 3277 #define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_S 5 3278 #define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_M \ 3279 0x0000001F // CC3XX Device type information. 3280 3281 #define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_S 0 3282 //****************************************************************************** 3283 // 3284 // The following are defines for the bit fields in the 3285 // OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE register. 3286 // 3287 //****************************************************************************** 3288 #define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_M \ 3289 0x000000F0 // [4] 1: switch between 3290 // WLAN_I2C_SCL and 3291 // TOP_GPIO_PORT4_I2C closes 0: 3292 // switch opens [5] 1: switch 3293 // between WLAN_I2C_SCL and 3294 // TOP_VSENSE_PORT closes 0: switch 3295 // opens [6] 1: switch between 3296 // WLAN_I2C_SCL and WLAN_ANA_TP4 3297 // closes 0: switch opens [7] 3298 // Reserved 3299 3300 #define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_S 4 3301 #define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_M \ 3302 0x0000000F // [0] 1: switch between 3303 // WLAN_I2C_SDA and 3304 // TOP_GPIO_PORT3_I2C closes 0: 3305 // switch opens [1] 1: switch 3306 // between WLAN_I2C_SDA and 3307 // TOP_IFORCE_PORT closes 0: switch 3308 // opens [2] 1: switch between 3309 // WLAN_I2C_SDA and WLAN_ANA_TP3 3310 // closes 0: switch opens [3] 3311 // Reserved 3312 3313 #define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_S 0 3314 //****************************************************************************** 3315 // 3316 // The following are defines for the bit fields in the 3317 // OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT register. 3318 // 3319 //****************************************************************************** 3320 #define OCP_SHARED_CC3XX_DEV_PACKAGE_DETECT_DEV_PKG_DETECT \ 3321 0x00000001 // when '0' indicates package type 3322 // is development. 3323 3324 //****************************************************************************** 3325 // 3326 // The following are defines for the bit fields in the 3327 // OCP_SHARED_O_AUTONMS_SPICLK_SEL register. 3328 // 3329 //****************************************************************************** 3330 #define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONOMOUS_BYPASS \ 3331 0x00000002 // This bit is used to bypass MCPSI 3332 // autonomous mode .if this bit is 1 3333 // autonomous MCSPI logic will be 3334 // bypassed and it will act as link 3335 // SPI 3336 3337 #define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONMS_SPICLK_SEL \ 3338 0x00000001 // This bit is used in SPI 3339 // Autonomous mode to switch clock 3340 // from system clock to SPI clk that 3341 // is coming from PAD. When value 1 3342 // PAD SPI clk is used as system 3343 // clock in LPDS mode by SPI as well 3344 // as autonomous wrapper logic. 3345 3346 //****************************************************************************** 3347 // 3348 // The following are defines for the bit fields in the 3349 // OCP_SHARED_O_CC3XX_DEV_PADCONF register. 3350 // 3351 //****************************************************************************** 3352 #define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_M \ 3353 0x0000FFFF 3354 3355 #define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_S 0 3356 //****************************************************************************** 3357 // 3358 // The following are defines for the bit fields in the 3359 // OCP_SHARED_O_IDMEM_TIM_UPDATE register. 3360 // 3361 //****************************************************************************** 3362 #define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_M \ 3363 0xFFFFFFFF 3364 3365 #define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_S 0 3366 //****************************************************************************** 3367 // 3368 // The following are defines for the bit fields in the 3369 // OCP_SHARED_O_SPARE_REG_6 register. 3370 // 3371 //****************************************************************************** 3372 #define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_M \ 3373 0xFFFFFFFF // NWP Software register 3374 3375 #define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_S 0 3376 //****************************************************************************** 3377 // 3378 // The following are defines for the bit fields in the 3379 // OCP_SHARED_O_SPARE_REG_7 register. 3380 // 3381 //****************************************************************************** 3382 #define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_M \ 3383 0xFFFFFFFF // NWP Software register 3384 3385 #define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_S 0 3386 //****************************************************************************** 3387 // 3388 // The following are defines for the bit fields in the 3389 // OCP_SHARED_O_APPS_WLAN_ORBIT register. 3390 // 3391 //****************************************************************************** 3392 #define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_M \ 3393 0xFFFFFC00 // Spare bit 3394 3395 #define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_S 10 3396 #define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_status \ 3397 0x00000200 // A rising edge on this bit 3398 // indicates that the test case 3399 // passes. This bit would be brought 3400 // out on the pin interface during 3401 // ORBIT. 3402 3403 #define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_exec \ 3404 0x00000100 // This register bit is writable by 3405 // the FW and when set to 1 it 3406 // indicates the start of a test 3407 // execution. A failing edge on this 3408 // bit indicates that the test 3409 // execution is complete. This bit 3410 // would be brought out on the pin 3411 // interface during ORBIT. 3412 3413 #define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_M \ 3414 0x000000FC // Implies the test case ID that 3415 // needs to run. 3416 3417 #define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_S 2 3418 #define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_halt_proc \ 3419 0x00000002 // This bit is used to trigger the 3420 // execution of test cases within 3421 // the (ROM based) IP. 3422 3423 #define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_mode \ 3424 0x00000001 // When this bit is 1 it implies 3425 // ORBIT mode of operation and the 3426 // (ROM based) IP start the 3427 // execution from a test case 3428 // perspective 3429 3430 //****************************************************************************** 3431 // 3432 // The following are defines for the bit fields in the 3433 // OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD register. 3434 // 3435 //****************************************************************************** 3436 #define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_M \ 3437 0xFFFFFFFF // scratch pad register. 3438 3439 #define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_S 0 3440 3441 3442 3443 #endif // __HW_OCP_SHARED_H__ 3444
