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33 
34 #ifndef __HW_MMCHS_H__
35 #define __HW_MMCHS_H__
36 
37 //*****************************************************************************
38 //
39 // The following are defines for the MMCHS register offsets.
40 //
41 //*****************************************************************************
42 #define MMCHS_O_HL_REV          0x00000000  // IP Revision Identifier (X.Y.R)
43                                             // Used by software to track
44                                             // features bugs and compatibility
45 #define MMCHS_O_HL_HWINFO       0x00000004  // Information about the IP
46                                             // module's hardware configuration
47                                             // i.e. typically the module's HDL
48                                             // generics (if any). Actual field
49                                             // format and encoding is up to the
50                                             // module's designer to decide.
51 #define MMCHS_O_HL_SYSCONFIG    0x00000010  // Clock management configuration
52 #define MMCHS_O_SYSCONFIG       0x00000110  // System Configuration Register
53                                             // This register allows controlling
54                                             // various parameters of the OCP
55                                             // interface.
56 #define MMCHS_O_SYSSTATUS       0x00000114  // System Status Register This
57                                             // register provides status
58                                             // information about the module
59                                             // excluding the interrupt status
60                                             // information
61 #define MMCHS_O_CSRE            0x00000124  // Card status response error This
62                                             // register enables the host
63                                             // controller to detect card status
64                                             // errors of response type R1 R1b
65                                             // for all cards and of R5 R5b and
66                                             // R6 response for cards types SD or
67                                             // SDIO. When a bit MMCHS_CSRE[i] is
68                                             // set to 1 if the corresponding bit
69                                             // at the same position in the
70                                             // response MMCHS_RSP0[i] is set to
71                                             // 1 the host controller indicates a
72                                             // card error (MMCHS_STAT[CERR])
73                                             // interrupt status to avoid the
74                                             // host driver reading the response
75                                             // register (MMCHS_RSP0). Note: No
76                                             // automatic card error detection
77                                             // for autoCMD12 is implemented; the
78                                             // host system has to check
79                                             // autoCMD12 response register
80                                             // (MMCHS_RESP76) for possible card
81                                             // errors.
82 #define MMCHS_O_SYSTEST         0x00000128  // System Test register This
83                                             // register is used to control the
84                                             // signals that connect to I/O pins
85                                             // when the module is configured in
86                                             // system test (SYSTEST) mode for
87                                             // boundary connectivity
88                                             // verification. Note: In SYSTEST
89                                             // mode a write into MMCHS_CMD
90                                             // register will not start a
91                                             // transfer. The buffer behaves as a
92                                             // stack accessible only by the
93                                             // local host (push and pop
94                                             // operations). In this mode the
95                                             // Transfer Block Size
96                                             // (MMCHS_BLK[BLEN]) and the Blocks
97                                             // count for current transfer
98                                             // (MMCHS_BLK[NBLK]) are needed to
99                                             // generate a Buffer write ready
100                                             // interrupt (MMCHS_STAT[BWR]) or a
101                                             // Buffer read ready interrupt
102                                             // (MMCHS_STAT[BRR]) and DMA
103                                             // requests if enabled.
104 #define MMCHS_O_CON             0x0000012C  // Configuration register This
105                                             // register is used: - to select the
106                                             // functional mode or the SYSTEST
107                                             // mode for any card. - to send an
108                                             // initialization sequence to any
109                                             // card. - to enable the detection
110                                             // on DAT[1] of a card interrupt for
111                                             // SDIO cards only. and also to
112                                             // configure : - specific data and
113                                             // command transfers for MMC cards
114                                             // only. - the parameters related to
115                                             // the card detect and write protect
116                                             // input signals.
117 #define MMCHS_O_PWCNT           0x00000130  // Power counter register This
118                                             // register is used to program a mmc
119                                             // counter to delay command
120                                             // transfers after activating the
121                                             // PAD power this value depends on
122                                             // PAD characteristics and voltage.
123 #define MMCHS_O_BLK             0x00000204  // Transfer Length Configuration
124                                             // register MMCHS_BLK[BLEN] is the
125                                             // block size register.
126                                             // MMCHS_BLK[NBLK] is the block
127                                             // count register. This register
128                                             // shall be used for any card.
129 #define MMCHS_O_ARG             0x00000208  // Command argument Register This
130                                             // register contains command
131                                             // argument specified as bit 39-8 of
132                                             // Command-Format These registers
133                                             // must be initialized prior to
134                                             // sending the command itself to the
135                                             // card (write action into the
136                                             // register MMCHS_CMD register).
137                                             // Only exception is for a command
138                                             // index specifying stuff bits in
139                                             // arguments making a write
140                                             // unnecessary.
141 #define MMCHS_O_CMD             0x0000020C  // Command and transfer mode
142                                             // register MMCHS_CMD[31:16] = the
143                                             // command register MMCHS_CMD[15:0]
144                                             // = the transfer mode. This
145                                             // register configures the data and
146                                             // command transfers. A write into
147                                             // the most significant byte send
148                                             // the command. A write into
149                                             // MMCHS_CMD[15:0] registers during
150                                             // data transfer has no effect. This
151                                             // register shall be used for any
152                                             // card. Note: In SYSTEST mode a
153                                             // write into MMCHS_CMD register
154                                             // will not start a transfer.
155 #define MMCHS_O_RSP10           0x00000210  // Command response[31:0] Register
156                                             // This 32-bit register holds bits
157                                             // positions [31:0] of command
158                                             // response type
159                                             // R1/R1b/R2/R3/R4/R5/R5b/R6
160 #define MMCHS_O_RSP32           0x00000214  // Command response[63:32] Register
161                                             // This 32-bit register holds bits
162                                             // positions [63:32] of command
163                                             // response type R2
164 #define MMCHS_O_RSP54           0x00000218  // Command response[95:64] Register
165                                             // This 32-bit register holds bits
166                                             // positions [95:64] of command
167                                             // response type R2
168 #define MMCHS_O_RSP76           0x0000021C  // Command response[127:96]
169                                             // Register This 32-bit register
170                                             // holds bits positions [127:96] of
171                                             // command response type R2
172 #define MMCHS_O_DATA            0x00000220  // Data Register This register is
173                                             // the 32-bit entry point of the
174                                             // buffer for read or write data
175                                             // transfers. The buffer size is
176                                             // 32bits x256(1024 bytes). Bytes
177                                             // within a word are stored and read
178                                             // in little endian format. This
179                                             // buffer can be used as two 512
180                                             // byte buffers to transfer data
181                                             // efficiently without reducing the
182                                             // throughput. Sequential and
183                                             // contiguous access is necessary to
184                                             // increment the pointer correctly.
185                                             // Random or skipped access is not
186                                             // allowed. In little endian if the
187                                             // local host accesses this register
188                                             // byte-wise or 16bit-wise the least
189                                             // significant byte (bits [7:0])
190                                             // must always be written/read
191                                             // first. The update of the buffer
192                                             // address is done on the most
193                                             // significant byte write for full
194                                             // 32-bit DATA register or on the
195                                             // most significant byte of the last
196                                             // word of block transfer. Example
197                                             // 1: Byte or 16-bit access
198                                             // Mbyteen[3:0]=0001 (1-byte) =>
199                                             // Mbyteen[3:0]=0010 (1-byte) =>
200                                             // Mbyteen[3:0]=1100 (2-bytes) OK
201                                             // Mbyteen[3:0]=0001 (1-byte) =>
202                                             // Mbyteen[3:0]=0010 (1-byte) =>
203                                             // Mbyteen[3:0]=0100 (1-byte) OK
204                                             // Mbyteen[3:0]=0001 (1-byte) =>
205                                             // Mbyteen[3:0]=0010 (1-byte) =>
206                                             // Mbyteen[3:0]=1000 (1-byte) Bad
207 #define MMCHS_O_PSTATE          0x00000224  // Present state register The Host
208                                             // can get status of the Host
209                                             // Controller from this 32-bit read
210                                             // only register.
211 #define MMCHS_O_HCTL            0x00000228  // Control register This register
212                                             // defines the host controls to set
213                                             // power wakeup and transfer
214                                             // parameters. MMCHS_HCTL[31:24] =
215                                             // Wakeup control MMCHS_HCTL[23:16]
216                                             // = Block gap control
217                                             // MMCHS_HCTL[15:8] = Power control
218                                             // MMCHS_HCTL[7:0] = Host control
219 #define MMCHS_O_SYSCTL          0x0000022C  // SD system control register This
220                                             // register defines the system
221                                             // controls to set software resets
222                                             // clock frequency management and
223                                             // data timeout. MMCHS_SYSCTL[31:24]
224                                             // = Software resets
225                                             // MMCHS_SYSCTL[23:16] = Timeout
226                                             // control MMCHS_SYSCTL[15:0] =
227                                             // Clock control
228 #define MMCHS_O_STAT            0x00000230  // Interrupt status register The
229                                             // interrupt status regroups all the
230                                             // status of the module internal
231                                             // events that can generate an
232                                             // interrupt. MMCHS_STAT[31:16] =
233                                             // Error Interrupt Status
234                                             // MMCHS_STAT[15:0] = Normal
235                                             // Interrupt Status
236 #define MMCHS_O_IE              0x00000234  // Interrupt SD enable register
237                                             // This register allows to
238                                             // enable/disable the module to set
239                                             // status bits on an event-by-event
240                                             // basis. MMCHS_IE[31:16] = Error
241                                             // Interrupt Status Enable
242                                             // MMCHS_IE[15:0] = Normal Interrupt
243                                             // Status Enable
244 #define MMCHS_O_ISE             0x00000238  // Interrupt signal enable register
245                                             // This register allows to
246                                             // enable/disable the module
247                                             // internal sources of status on an
248                                             // event-by-event basis.
249                                             // MMCHS_ISE[31:16] = Error
250                                             // Interrupt Signal Enable
251                                             // MMCHS_ISE[15:0] = Normal
252                                             // Interrupt Signal Enable
253 #define MMCHS_O_AC12            0x0000023C  // Auto CMD12 Error Status Register
254                                             // The host driver may determine
255                                             // which of the errors cases related
256                                             // to Auto CMD12 has occurred by
257                                             // checking this MMCHS_AC12 register
258                                             // when an Auto CMD12 Error
259                                             // interrupt occurs. This register
260                                             // is valid only when Auto CMD12 is
261                                             // enabled (MMCHS_CMD[ACEN]) and
262                                             // Auto CMD12Error (MMCHS_STAT[ACE])
263                                             // is set to 1. Note: These bits are
264                                             // automatically reset when starting
265                                             // a new adtc command with data.
266 #define MMCHS_O_CAPA            0x00000240  // Capabilities register This
267                                             // register lists the capabilities
268                                             // of the MMC/SD/SDIO host
269                                             // controller.
270 #define MMCHS_O_CUR_CAPA        0x00000248  // Maximum current capabilities
271                                             // Register This register indicates
272                                             // the maximum current capability
273                                             // for each voltage. The value is
274                                             // meaningful if the voltage support
275                                             // is set in the capabilities
276                                             // register (MMCHS_CAPA).
277                                             // Initialization of this register
278                                             // (via a write access to this
279                                             // register) depends on the system
280                                             // capabilities. The host driver
281                                             // shall not modify this register
282                                             // after the initilaization. This
283                                             // register is only reinitialized by
284                                             // a hard reset (via RESETN signal)
285 #define MMCHS_O_FE              0x00000250  // Force Event Register for Error
286                                             // Interrupt status The force Event
287                                             // Register is not a physically
288                                             // implemented register. Rather it
289                                             // is an address at which the Error
290                                             // Interrupt Status register can be
291                                             // written. The effect of a write to
292                                             // this address will be reflected in
293                                             // the Error Interrupt Status
294                                             // Register if corresponding bit of
295                                             // the Error Interrupt Status Enable
296                                             // Register is set.
297 #define MMCHS_O_ADMAES          0x00000254  // ADMA Error Status Register When
298                                             // ADMA Error Interrupt is occurred
299                                             // the ADMA Error States field in
300                                             // this register holds the ADMA
301                                             // state and the ADMA System Address
302                                             // Register holds the address around
303                                             // the error descriptor. For
304                                             // recovering the error the Host
305                                             // Driver requires the ADMA state to
306                                             // identify the error descriptor
307                                             // address as follows: ST_STOP:
308                                             // Previous location set in the ADMA
309                                             // System Address register is the
310                                             // error descriptor address ST_FDS:
311                                             // Current location set in the ADMA
312                                             // System Address register is the
313                                             // error descriptor address ST_CADR:
314                                             // This sate is never set because do
315                                             // not generate ADMA error in this
316                                             // state. ST_TFR: Previous location
317                                             // set in the ADMA System Address
318                                             // register is the error descriptor
319                                             // address In case of write
320                                             // operation the Host Driver should
321                                             // use ACMD22 to get the number of
322                                             // written block rather than using
323                                             // this information since unwritten
324                                             // data may exist in the Host
325                                             // Controller. The Host Controller
326                                             // generates the ADMA Error
327                                             // Interrupt when it detects invalid
328                                             // descriptor data (Valid=0) at the
329                                             // ST_FDS state. In this case ADMA
330                                             // Error State indicates that an
331                                             // error occurs at ST_FDS state. The
332                                             // Host Driver may find that the
333                                             // Valid bit is not set in the error
334                                             // descriptor.
335 #define MMCHS_O_ADMASAL         0x00000258  // ADMA System address Low bits
336 #define MMCHS_O_REV             0x000002FC  // Versions Register This register
337                                             // contains the hard coded RTL
338                                             // vendor revision number the
339                                             // version number of SD
340                                             // specification compliancy and a
341                                             // slot status bit. MMCHS_REV[31:16]
342                                             // = Host controller version
343                                             // MMCHS_REV[15:0] = Slot Interrupt
344                                             // Status
345 
346 
347 
348 //******************************************************************************
349 //
350 // The following are defines for the bit fields in the MMCHS_O_HL_REV register.
351 //
352 //******************************************************************************
353 #define MMCHS_HL_REV_SCHEME_M   0xC0000000
354 #define MMCHS_HL_REV_SCHEME_S   30
355 #define MMCHS_HL_REV_FUNC_M     0x0FFF0000  // Function indicates a software
356                                             // compatible module family. If
357                                             // there is no level of software
358                                             // compatibility a new Func number
359                                             // (and hence REVISION) should be
360                                             // assigned.
361 #define MMCHS_HL_REV_FUNC_S     16
362 #define MMCHS_HL_REV_R_RTL_M    0x0000F800  // RTL Version (R) maintained by IP
363                                             // design owner. RTL follows a
364                                             // numbering such as X.Y.R.Z which
365                                             // are explained in this table. R
366                                             // changes ONLY when: (1) PDS
367                                             // uploads occur which may have been
368                                             // due to spec changes (2) Bug fixes
369                                             // occur (3) Resets to '0' when X or
370                                             // Y changes. Design team has an
371                                             // internal 'Z' (customer invisible)
372                                             // number which increments on every
373                                             // drop that happens due to DV and
374                                             // RTL updates. Z resets to 0 when R
375                                             // increments.
376 #define MMCHS_HL_REV_R_RTL_S    11
377 #define MMCHS_HL_REV_X_MAJOR_M  0x00000700  // Major Revision (X) maintained by
378                                             // IP specification owner. X changes
379                                             // ONLY when: (1) There is a major
380                                             // feature addition. An example
381                                             // would be adding Master Mode to
382                                             // Utopia Level2. The Func field (or
383                                             // Class/Type in old PID format)
384                                             // will remain the same. X does NOT
385                                             // change due to: (1) Bug fixes (2)
386                                             // Change in feature parameters.
387 #define MMCHS_HL_REV_X_MAJOR_S  8
388 #define MMCHS_HL_REV_CUSTOM_M   0x000000C0
389 #define MMCHS_HL_REV_CUSTOM_S   6
390 #define MMCHS_HL_REV_Y_MINOR_M  0x0000003F  // Minor Revision (Y) maintained by
391                                             // IP specification owner. Y changes
392                                             // ONLY when: (1) Features are
393                                             // scaled (up or down). Flexibility
394                                             // exists in that this feature
395                                             // scalability may either be
396                                             // represented in the Y change or a
397                                             // specific register in the IP that
398                                             // indicates which features are
399                                             // exactly available. (2) When
400                                             // feature creeps from Is-Not list
401                                             // to Is list. But this may not be
402                                             // the case once it sees silicon; in
403                                             // which case X will change. Y does
404                                             // NOT change due to: (1) Bug fixes
405                                             // (2) Typos or clarifications (3)
406                                             // major functional/feature
407                                             // change/addition/deletion. Instead
408                                             // these changes may be reflected
409                                             // via R S X as applicable. Spec
410                                             // owner maintains a
411                                             // customer-invisible number 'S'
412                                             // which changes due to: (1)
413                                             // Typos/clarifications (2) Bug
414                                             // documentation. Note that this bug
415                                             // is not due to a spec change but
416                                             // due to implementation.
417                                             // Nevertheless the spec tracks the
418                                             // IP bugs. An RTL release (say for
419                                             // silicon PG1.1) that occurs due to
420                                             // bug fix should document the
421                                             // corresponding spec number (X.Y.S)
422                                             // in its release notes.
423 #define MMCHS_HL_REV_Y_MINOR_S  0
424 //******************************************************************************
425 //
426 // The following are defines for the bit fields in the MMCHS_O_HL_HWINFO register.
427 //
428 //******************************************************************************
429 #define MMCHS_HL_HWINFO_RETMODE 0x00000040
430 #define MMCHS_HL_HWINFO_MEM_SIZE_M \
431                                 0x0000003C
432 
433 #define MMCHS_HL_HWINFO_MEM_SIZE_S 2
434 #define MMCHS_HL_HWINFO_MERGE_MEM \
435                                 0x00000002
436 
437 #define MMCHS_HL_HWINFO_MADMA_EN \
438                                 0x00000001
439 
440 //******************************************************************************
441 //
442 // The following are defines for the bit fields in the
443 // MMCHS_O_HL_SYSCONFIG register.
444 //
445 //******************************************************************************
446 #define MMCHS_HL_SYSCONFIG_STANDBYMODE_M \
447                                 0x00000030  // Configuration of the local
448                                             // initiator state management mode.
449                                             // By definition initiator may
450                                             // generate read/write transaction
451                                             // as long as it is out of STANDBY
452                                             // state. 0x0 Force-standby mode:
453                                             // local initiator is
454                                             // unconditionally placed in standby
455                                             // state.Backup mode for debug only.
456                                             // 0x1 No-standby mode: local
457                                             // initiator is unconditionally
458                                             // placed out of standby
459                                             // state.Backup mode for debug only.
460                                             // 0x2 Smart-standby mode: local
461                                             // initiator standby status depends
462                                             // on local conditions i.e. the
463                                             // module's functional requirement
464                                             // from the initiator.IP module
465                                             // shall not generate
466                                             // (initiator-related) wakeup
467                                             // events. 0x3 "Smart-Standby
468                                             // wakeup-capable mode: local
469                                             // initiator standby status depends
470                                             // on local conditions i.e. the
471                                             // module's functional requirement
472                                             // from the initiator. IP module may
473                                             // generate (master-related) wakeup
474                                             // events when in standby state.Mode
475                                             // is only relevant if the
476                                             // appropriate IP module ""mwakeup""
477                                             // output is implemented."
478 
479 #define MMCHS_HL_SYSCONFIG_STANDBYMODE_S 4
480 #define MMCHS_HL_SYSCONFIG_IDLEMODE_M \
481                                 0x0000000C  // Configuration of the local
482                                             // target state management mode. By
483                                             // definition target can handle
484                                             // read/write transaction as long as
485                                             // it is out of IDLE state. 0x0
486                                             // Force-idle mode: local target's
487                                             // idle state follows (acknowledges)
488                                             // the system's idle requests
489                                             // unconditionally i.e. regardless
490                                             // of the IP module's internal
491                                             // requirements.Backup mode for
492                                             // debug only. 0x1 No-idle mode:
493                                             // local target never enters idle
494                                             // state.Backup mode for debug only.
495                                             // 0x2 Smart-idle mode: local
496                                             // target's idle state eventually
497                                             // follows (acknowledges) the
498                                             // system's idle requests depending
499                                             // on the IP module's internal
500                                             // requirements.IP module shall not
501                                             // generate (IRQ- or
502                                             // DMA-request-related) wakeup
503                                             // events. 0x3 "Smart-idle
504                                             // wakeup-capable mode: local
505                                             // target's idle state eventually
506                                             // follows (acknowledges) the
507                                             // system's idle requests depending
508                                             // on the IP module's internal
509                                             // requirements.IP module may
510                                             // generate (IRQ- or
511                                             // DMA-request-related) wakeup
512                                             // events when in idle state.Mode is
513                                             // only relevant if the appropriate
514                                             // IP module ""swakeup"" output(s)
515                                             // is (are) implemented."
516 
517 #define MMCHS_HL_SYSCONFIG_IDLEMODE_S 2
518 #define MMCHS_HL_SYSCONFIG_FREEEMU \
519                                 0x00000002  // Sensitivity to emulation (debug)
520                                             // suspend input signal.
521                                             // Functionality NOT implemented in
522                                             // MMCHS. 0 IP module is sensitive
523                                             // to emulation suspend 1 IP module
524                                             // is not sensitive to emulation
525                                             // suspend
526 
527 #define MMCHS_HL_SYSCONFIG_SOFTRESET \
528                                 0x00000001
529 
530 //******************************************************************************
531 //
532 // The following are defines for the bit fields in the MMCHS_O_SYSCONFIG register.
533 //
534 //******************************************************************************
535 #define MMCHS_SYSCONFIG_STANDBYMODE_M \
536                                 0x00003000  // Master interface power
537                                             // Management standby/wait control.
538                                             // The bit field is only useful when
539                                             // generic parameter MADMA_EN
540                                             // (Master ADMA enable) is set as
541                                             // active otherwise it is a read
542                                             // only register read a '0'. 0x0
543                                             // Force-standby. Mstandby is forced
544                                             // unconditionnaly. 0x1 No-standby.
545                                             // Mstandby is never asserted. 0x2
546                                             // Smart-standby mode: local
547                                             // initiator standby status depends
548                                             // on local conditions i.e. the
549                                             // module's functional requirement
550                                             // from the initiator.IP module
551                                             // shall not generate
552                                             // (initiator-related) wakeup
553                                             // events. 0x3 Smart-Standby
554                                             // wakeup-capable mode: "local
555                                             // initiator standby status depends
556                                             // on local conditions i.e. the
557                                             // module's functional requirement
558                                             // from the initiator. IP module may
559                                             // generate (master-related) wakeup
560                                             // events when in standby state.Mode
561                                             // is only relevant if the
562                                             // appropriate IP module ""mwakeup""
563                                             // output is implemented."
564 
565 #define MMCHS_SYSCONFIG_STANDBYMODE_S 12
566 #define MMCHS_SYSCONFIG_CLOCKACTIVITY_M \
567                                 0x00000300  // Clocks activity during wake up
568                                             // mode period. Bit8: OCP interface
569                                             // clock Bit9: Functional clock 0x0
570                                             // OCP and Functional clock may be
571                                             // switched off. 0x1 OCP clock is
572                                             // maintained. Functional clock may
573                                             // be switched-off. 0x2 Functional
574                                             // clock is maintained. OCP clock
575                                             // may be switched-off. 0x3 OCP and
576                                             // Functional clocks are maintained.
577 
578 #define MMCHS_SYSCONFIG_CLOCKACTIVITY_S 8
579 #define MMCHS_SYSCONFIG_SIDLEMODE_M \
580                                 0x00000018  // Power management 0x0 If an idle
581                                             // request is detected the MMCHS
582                                             // acknowledges it unconditionally
583                                             // and goes in Inactive mode.
584                                             // Interrupt and DMA requests are
585                                             // unconditionally de-asserted. 0x1
586                                             // If an idle request is detected
587                                             // the request is ignored and the
588                                             // module keeps on behaving
589                                             // normally. 0x2 Smart-idle mode:
590                                             // local target's idle state
591                                             // eventually follows (acknowledges)
592                                             // the system's idle requests
593                                             // depending on the IP module's
594                                             // internal requirements.IP module
595                                             // shall not generate (IRQ- or
596                                             // DMA-request-related) wakeup
597                                             // events. 0x3 Smart-idle
598                                             // wakeup-capable mode: "local
599                                             // target's idle state eventually
600                                             // follows (acknowledges) the
601                                             // system's idle requests depending
602                                             // on the IP module's internal
603                                             // requirements.IP module may
604                                             // generate (IRQ- or
605                                             // DMA-request-related) wakeup
606                                             // events when in idle state.Mode is
607                                             // only relevant if the appropriate
608                                             // IP module ""swakeup"" output(s)
609                                             // is (are) implemented."
610 
611 #define MMCHS_SYSCONFIG_SIDLEMODE_S 3
612 #define MMCHS_SYSCONFIG_ENAWAKEUP \
613                                 0x00000004  // Wakeup feature control 0 Wakeup
614                                             // capability is disabled 1 Wakeup
615                                             // capability is enabled
616 
617 #define MMCHS_SYSCONFIG_SOFTRESET \
618                                 0x00000002
619 
620 #define MMCHS_SYSCONFIG_AUTOIDLE \
621                                 0x00000001  // Internal Clock gating strategy 0
622                                             // Clocks are free-running 1
623                                             // Automatic clock gating strategy
624                                             // is applied based on the OCP and
625                                             // MMC interface activity
626 
627 //******************************************************************************
628 //
629 // The following are defines for the bit fields in the MMCHS_O_SYSSTATUS register.
630 //
631 //******************************************************************************
632 #define MMCHS_SYSSTATUS_RESETDONE \
633                                 0x00000001
634 
635 //******************************************************************************
636 //
637 // The following are defines for the bit fields in the MMCHS_O_CSRE register.
638 //
639 //******************************************************************************
640 #define MMCHS_CSRE_CSRE_M       0xFFFFFFFF  // Card status response error
641 #define MMCHS_CSRE_CSRE_S       0
642 //******************************************************************************
643 //
644 // The following are defines for the bit fields in the MMCHS_O_SYSTEST register.
645 //
646 //******************************************************************************
647 #define MMCHS_SYSTEST_OBI       0x00010000
648 #define MMCHS_SYSTEST_SDCD      0x00008000
649 #define MMCHS_SYSTEST_SDWP      0x00004000
650 #define MMCHS_SYSTEST_WAKD      0x00002000
651 #define MMCHS_SYSTEST_SSB       0x00001000
652 #define MMCHS_SYSTEST_D7D       0x00000800
653 #define MMCHS_SYSTEST_D6D       0x00000400
654 #define MMCHS_SYSTEST_D5D       0x00000200
655 #define MMCHS_SYSTEST_D4D       0x00000100
656 #define MMCHS_SYSTEST_D3D       0x00000080
657 #define MMCHS_SYSTEST_D2D       0x00000040
658 #define MMCHS_SYSTEST_D1D       0x00000020
659 #define MMCHS_SYSTEST_D0D       0x00000010
660 #define MMCHS_SYSTEST_DDIR      0x00000008
661 #define MMCHS_SYSTEST_CDAT      0x00000004
662 #define MMCHS_SYSTEST_CDIR      0x00000002
663 #define MMCHS_SYSTEST_MCKD      0x00000001
664 //******************************************************************************
665 //
666 // The following are defines for the bit fields in the MMCHS_O_CON register.
667 //
668 //******************************************************************************
669 #define MMCHS_CON_SDMA_LNE      0x00200000  // Slave DMA Level/Edge Request:
670                                             // The waveform of the DMA request
671                                             // can be configured either edge
672                                             // sensitive with early de-assertion
673                                             // on first access to MMCHS_DATA
674                                             // register or late de-assertion
675                                             // request remains active until last
676                                             // allowed data written into
677                                             // MMCHS_DATA. 0 Slave DMA edge
678                                             // sensitive Early DMA de-assertion
679                                             // 1 Slave DMA level sensitive Late
680                                             // DMA de-assertion
681 #define MMCHS_CON_DMA_MNS       0x00100000  // DMA Master or Slave selection:
682                                             // When this bit is set and the
683                                             // controller is configured to use
684                                             // the DMA Ocp master interface is
685                                             // used to get datas from system
686                                             // using ADMA2 procedure (direct
687                                             // access to the memory).This option
688                                             // is only available if generic
689                                             // parameter MADMA_EN is asserted to
690                                             // '1'. 0 The controller is slave on
691                                             // data transfers with system. 1 The
692                                             // controller is master on data
693                                             // exchange with system controller
694                                             // must be configured as using DMA.
695 #define MMCHS_CON_DDR           0x00080000  // Dual Data Rate mode: When this
696                                             // register is set the controller
697                                             // uses both clock edge to emit or
698                                             // receive data. Odd bytes are
699                                             // transmitted on falling edges and
700                                             // even bytes are transmitted on
701                                             // rise edges. It only applies on
702                                             // Data bytes and CRC Start end bits
703                                             // and CRC status are kept full
704                                             // cycle. This bit field is only
705                                             // meaningful and active for even
706                                             // clock divider ratio of
707                                             // MMCHS_SYSCTL[CLKD] it is
708                                             // insensitive to MMCHS_HCTL[HSPE]
709                                             // setting. 0 Standard mode : data
710                                             // are transmitted on a single edge
711                                             // depending on MMCHS_HCTRL[HSPE]. 1
712                                             // Data Bytes and CRC are
713                                             // transmitted on both edge.
714 #define MMCHS_CON_BOOT_CF0      0x00040000
715 #define MMCHS_CON_BOOT_ACK      0x00020000  // Book acknowledge received: When
716                                             // this bit is set the controller
717                                             // should receive a boot status on
718                                             // DAT0 line after next command
719                                             // issued. If no status is received
720                                             // a data timeout will be generated.
721                                             // 0 No acknowledge to be received 1
722                                             // A boot status will be received on
723                                             // DAT0 line after issuing a
724                                             // command.
725 #define MMCHS_CON_CLKEXTFREE    0x00010000  // External clock free running:
726                                             // This register is used to maintain
727                                             // card clock out of transfer
728                                             // transaction to enable slave
729                                             // module for example to generate a
730                                             // synchronous interrupt on DAT[1].
731                                             // The Clock will be maintain only
732                                             // if MMCHS_SYSCTL[CEN] is set. 0
733                                             // External card clock is cut off
734                                             // outside active transaction
735                                             // period. 1 External card clock is
736                                             // maintain even out of active
737                                             // transaction period only if
738                                             // MMCHS_SYSCTL[CEN] is set.
739 #define MMCHS_CON_PADEN         0x00008000  // Control Power for MMC Lines:
740                                             // This register is only useful when
741                                             // MMC PADs contain power saving
742                                             // mechanism to minimize its leakage
743                                             // power. It works as a GPIO that
744                                             // directly control the ACTIVE pin
745                                             // of PADs. Excepted for DAT[1] the
746                                             // signal is also combine outside
747                                             // the module with the dedicated
748                                             // power control MMCHS_CON[CTPL]
749                                             // bit. 0 ADPIDLE module pin is not
750                                             // forced it is automatically
751                                             // generated by the MMC fsms. 1
752                                             // ADPIDLE module pin is forced to
753                                             // active state.
754 #define MMCHS_CON_OBIE          0x00004000  // Out-of-Band Interrupt Enable MMC
755                                             // cards only: This bit enables the
756                                             // detection of Out-of-Band
757                                             // Interrupt on MMCOBI input pin.
758                                             // The usage of the Out-of-Band
759                                             // signal (OBI) is optional and
760                                             // depends on the system
761                                             // integration. 0 Out-of-Band
762                                             // interrupt detection disabled 1
763                                             // Out-of-Band interrupt detection
764                                             // enabled
765 #define MMCHS_CON_OBIP          0x00002000  // Out-of-Band Interrupt Polarity
766                                             // MMC cards only: This bit selects
767                                             // the active level of the
768                                             // out-of-band interrupt coming from
769                                             // MMC cards. The usage of the
770                                             // Out-of-Band signal (OBI) is
771                                             // optional and depends on the
772                                             // system integration. 0 active high
773                                             // level 1 active low level
774 #define MMCHS_CON_CEATA         0x00001000  // CE-ATA control mode MMC cards
775                                             // compliant with CE-ATA:By default
776                                             // this bit is set to 0. It is use
777                                             // to indicate that next commands
778                                             // are considered as specific CE-ATA
779                                             // commands that potentially use
780                                             // 'command completion' features. 0
781                                             // Standard MMC/SD/SDIO mode. 1
782                                             // CE-ATA mode next commands are
783                                             // considered as CE-ATA commands.
784 #define MMCHS_CON_CTPL          0x00000800  // Control Power for DAT[1] line
785                                             // MMC and SD cards: By default this
786                                             // bit is set to 0 and the host
787                                             // controller automatically disables
788                                             // all the input buffers outside of
789                                             // a transaction to minimize the
790                                             // leakage current. SDIO cards: When
791                                             // this bit is set to 1 the host
792                                             // controller automatically disables
793                                             // all the input buffers except the
794                                             // buffer of DAT[1] outside of a
795                                             // transaction in order to detect
796                                             // asynchronous card interrupt on
797                                             // DAT[1] line and minimize the
798                                             // leakage current of the buffers. 0
799                                             // Disable all the input buffers
800                                             // outside of a transaction. 1
801                                             // Disable all the input buffers
802                                             // except the buffer of DAT[1]
803                                             // outside of a transaction.
804 #define MMCHS_CON_DVAL_M        0x00000600  // Debounce filter value All cards
805                                             // This register is used to define a
806                                             // debounce period to filter the
807                                             // card detect input signal (SDCD).
808                                             // The usage of the card detect
809                                             // input signal (SDCD) is optional
810                                             // and depends on the system
811                                             // integration and the type of the
812                                             // connector housing that
813                                             // accommodates the card. 0x0 33 us
814                                             // debounce period 0x1 231 us
815                                             // debounce period 0x2 1 ms debounce
816                                             // period 0x3 84 ms debounce period
817 #define MMCHS_CON_DVAL_S        9
818 #define MMCHS_CON_WPP           0x00000100  // Write protect polarity For SD
819                                             // and SDIO cards only This bit
820                                             // selects the active level of the
821                                             // write protect input signal
822                                             // (SDWP). The usage of the write
823                                             // protect input signal (SDWP) is
824                                             // optional and depends on the
825                                             // system integration and the type
826                                             // of the connector housing that
827                                             // accommodates the card. 0 active
828                                             // high level 1 active low level
829 #define MMCHS_CON_CDP           0x00000080  // Card detect polarity All cards
830                                             // This bit selects the active level
831                                             // of the card detect input signal
832                                             // (SDCD). The usage of the card
833                                             // detect input signal (SDCD) is
834                                             // optional and depends on the
835                                             // system integration and the type
836                                             // of the connector housing that
837                                             // accommodates the card. 0 active
838                                             // high level 1 active low level
839 #define MMCHS_CON_MIT           0x00000040  // MMC interrupt command Only for
840                                             // MMC cards. This bit must be set
841                                             // to 1 when the next write access
842                                             // to the command register
843                                             // (MMCHS_CMD) is for writing a MMC
844                                             // interrupt command (CMD40)
845                                             // requiring the command timeout
846                                             // detection to be disabled for the
847                                             // command response. 0 Command
848                                             // timeout enabled 1 Command timeout
849                                             // disabled
850 #define MMCHS_CON_DW8           0x00000020  // 8-bit mode MMC select For
851                                             // SD/SDIO cards this bit must be
852                                             // set to 0. For MMC card this bit
853                                             // must be set following a valid
854                                             // SWITCH command (CMD6) with the
855                                             // correct value and extend CSD
856                                             // index written in the argument.
857                                             // Prior to this command the MMC
858                                             // card configuration register (CSD
859                                             // and EXT_CSD) must be verified for
860                                             // compliancy with MMC standard
861                                             // specification 4.x (see section
862                                             // 3.6). 0 1-bit or 4-bit Data width
863                                             // (DAT[0] used MMC SD cards) 1
864                                             // 8-bit Data width (DAT[7:0] used
865                                             // MMC cards)
866 #define MMCHS_CON_MODE          0x00000010  // Mode select All cards These bits
867                                             // select between Functional mode
868                                             // and SYSTEST mode. 0 Functional
869                                             // mode. Transfers to the
870                                             // MMC/SD/SDIO cards follow the card
871                                             // protocol. MMC clock is enabled.
872                                             // MMC/SD transfers are operated
873                                             // under the control of the CMD
874                                             // register. 1 SYSTEST mode The
875                                             // signal pins are configured as
876                                             // general-purpose input/output and
877                                             // the 1024-byte buffer is
878                                             // configured as a stack memory
879                                             // accessible only by the local host
880                                             // or system DMA. The pins retain
881                                             // their default type (input output
882                                             // or in-out). SYSTEST mode is
883                                             // operated under the control of the
884                                             // SYSTEST register.
885 #define MMCHS_CON_STR           0x00000008  // Stream command Only for MMC
886                                             // cards. This bit must be set to 1
887                                             // only for the stream data
888                                             // transfers (read or write) of the
889                                             // adtc commands. Stream read is a
890                                             // class 1 command (CMD11:
891                                             // READ_DAT_UNTIL_STOP). Stream
892                                             // write is a class 3 command
893                                             // (CMD20: WRITE_DAT_UNTIL_STOP). 0
894                                             // Block oriented data transfer 1
895                                             // Stream oriented data transfer
896 #define MMCHS_CON_HR            0x00000004  // Broadcast host response Only for
897                                             // MMC cards. This register is used
898                                             // to force the host to generate a
899                                             // 48-bit response for bc command
900                                             // type. "It can be used to
901                                             // terminate the interrupt mode by
902                                             // generating a CMD40 response by
903                                             // the core (see section 4.3
904                                             // ""Interrupt Mode"" in the MMC [1]
905                                             // specification). In order to have
906                                             // the host response to be generated
907                                             // in open drain mode the register
908                                             // MMCHS_CON[OD] must be set to 1."
909                                             // When MMCHS_CON[CEATA] is set to 1
910                                             // and MMCHS_ARG set to 0x00000000
911                                             // when writing 0x00000000 into
912                                             // MMCHS_CMD register the host
913                                             // controller performs a 'command
914                                             // completion signal disable' token
915                                             // i.e. CMD line held to '0' during
916                                             // 47 cycles followed by a 1. 0 The
917                                             // host does not generate a 48-bit
918                                             // response instead of a command. 1
919                                             // The host generates a 48-bit
920                                             // response instead of a command or
921                                             // a command completion signal
922                                             // disable token.
923 #define MMCHS_CON_INIT          0x00000002  // Send initialization stream All
924                                             // cards. When this bit is set to 1
925                                             // and the card is idle an
926                                             // initialization sequence is sent
927                                             // to the card. "An initialization
928                                             // sequence consists of setting the
929                                             // CMD line to 1 during 80 clock
930                                             // cycles. The initialisation
931                                             // sequence is mandatory - but it is
932                                             // not required to do it through
933                                             // this bit - this bit makes it
934                                             // easier. Clock divider
935                                             // (MMCHS_SYSCTL[CLKD]) should be
936                                             // set to ensure that 80 clock
937                                             // periods are greater than 1ms.
938                                             // (see section 9.3 ""Power-Up"" in
939                                             // the MMC card specification [1] or
940                                             // section 6.4 in the SD card
941                                             // specification [2])." Note: in
942                                             // this mode there is no command
943                                             // sent to the card and no response
944                                             // is expected 0 The host does not
945                                             // send an initialization sequence.
946                                             // 1 The host sends an
947                                             // initialization sequence.
948 #define MMCHS_CON_OD            0x00000001  // Card open drain mode. Only for
949                                             // MMC cards. This bit must be set
950                                             // to 1 for MMC card commands 1 2 3
951                                             // and 40 and if the MMC card bus is
952                                             // operating in open-drain mode
953                                             // during the response phase to the
954                                             // command sent. Typically during
955                                             // card identification mode when the
956                                             // card is either in idle ready or
957                                             // ident state. It is also necessary
958                                             // to set this bit to 1 for a
959                                             // broadcast host response (see
960                                             // Broadcast host response register
961                                             // MMCHS_CON[HR]) 0 No Open Drain 1
962                                             // Open Drain or Broadcast host
963                                             // response
964 //******************************************************************************
965 //
966 // The following are defines for the bit fields in the MMCHS_O_PWCNT register.
967 //
968 //******************************************************************************
969 #define MMCHS_PWCNT_PWRCNT_M    0x0000FFFF  // Power counter register. This
970                                             // register is used to introduce a
971                                             // delay between the PAD ACTIVE pin
972                                             // assertion and the command issued.
973                                             // 0x0000 No additional delay added
974                                             // 0x0001 TCF delay (card clock
975                                             // period) 0x0002 TCF x 2 delay
976                                             // (card clock period) 0xFFFE TCF x
977                                             // 65534 delay (card clock period)
978                                             // 0xFFFF TCF x 65535 delay (card
979                                             // clock period)
980 #define MMCHS_PWCNT_PWRCNT_S    0
981 //******************************************************************************
982 //
983 // The following are defines for the bit fields in the MMCHS_O_BLK register.
984 //
985 //******************************************************************************
986 #define MMCHS_BLK_NBLK_M        0xFFFF0000  // Blocks count for current
987                                             // transfer This register is enabled
988                                             // when Block count Enable
989                                             // (MMCHS_CMD[BCE]) is set to 1 and
990                                             // is valid only for multiple block
991                                             // transfers. Setting the block
992                                             // count to 0 results no data blocks
993                                             // being transferred. Note: The host
994                                             // controller decrements the block
995                                             // count after each block transfer
996                                             // and stops when the count reaches
997                                             // zero. This register can be
998                                             // accessed only if no transaction
999                                             // is executing (i.e after a
1000                                             // transaction has stopped). Read
1001                                             // operations during transfers may
1002                                             // return an invalid value and write
1003                                             // operation will be ignored. In
1004                                             // suspend context the number of
1005                                             // blocks yet to be transferred can
1006                                             // be determined by reading this
1007                                             // register. When restoring transfer
1008                                             // context prior to issuing a Resume
1009                                             // command The local host shall
1010                                             // restore the previously saved
1011                                             // block count. 0x0000 Stop count
1012                                             // 0x0001 1 block 0x0002 2 blocks
1013                                             // 0xFFFF 65535 blocks
1014 #define MMCHS_BLK_NBLK_S        16
1015 #define MMCHS_BLK_BLEN_M        0x00000FFF  // Transfer Block Size. This
1016                                             // register specifies the block size
1017                                             // for block data transfers. Read
1018                                             // operations during transfers may
1019                                             // return an invalid value and write
1020                                             // operations are ignored. When a
1021                                             // CMD12 command is issued to stop
1022                                             // the transfer a read of the BLEN
1023                                             // field after transfer completion
1024                                             // (MMCHS_STAT[TC] set to 1) will
1025                                             // not return the true byte number
1026                                             // of data length while the stop
1027                                             // occurs but the value written in
1028                                             // this register before transfer is
1029                                             // launched. 0x000 No data transfer
1030                                             // 0x001 1 byte block length 0x002 2
1031                                             // bytes block length 0x003 3 bytes
1032                                             // block length 0x1FF 511 bytes
1033                                             // block length 0x200 512 bytes
1034                                             // block length 0x7FF 2047 bytes
1035                                             // block length 0x800 2048 bytes
1036                                             // block length
1037 #define MMCHS_BLK_BLEN_S        0
1038 //******************************************************************************
1039 //
1040 // The following are defines for the bit fields in the MMCHS_O_ARG register.
1041 //
1042 //******************************************************************************
1043 #define MMCHS_ARG_ARG_M         0xFFFFFFFF  // Command argument bits [31:0]
1044 #define MMCHS_ARG_ARG_S         0
1045 //******************************************************************************
1046 //
1047 // The following are defines for the bit fields in the MMCHS_O_CMD register.
1048 //
1049 //******************************************************************************
1050 #define MMCHS_CMD_INDX_M        0x3F000000  // Command index Binary encoded
1051                                             // value from 0 to 63 specifying the
1052                                             // command number send to card 0x00
1053                                             // CMD0 or ACMD0 0x01 CMD1 or ACMD1
1054                                             // 0x02 CMD2 or ACMD2 0x03 CMD3 or
1055                                             // ACMD3 0x04 CMD4 or ACMD4 0x05
1056                                             // CMD5 or ACMD5 0x06 CMD6 or ACMD6
1057                                             // 0x07 CMD7 or ACMD7 0x08 CMD8 or
1058                                             // ACMD8 0x09 CMD9 or ACMD9 0x0A
1059                                             // CMD10 or ACMD10 0x0B CMD11 or
1060                                             // ACMD11 0x0C CMD12 or ACMD12 0x0D
1061                                             // CMD13 or ACMD13 0x0E CMD14 or
1062                                             // ACMD14 0x0F CMD15 or ACMD15 0x10
1063                                             // CMD16 or ACMD16 0x11 CMD17 or
1064                                             // ACMD17 0x12 CMD18 or ACMD18 0x13
1065                                             // CMD19 or ACMD19 0x14 CMD20 or
1066                                             // ACMD20 0x15 CMD21 or ACMD21 0x16
1067                                             // CMD22 or ACMD22 0x17 CMD23 or
1068                                             // ACMD23 0x18 CMD24 or ACMD24 0x19
1069                                             // CMD25 or ACMD25 0x1A CMD26 or
1070                                             // ACMD26 0x1B CMD27 or ACMD27 0x1C
1071                                             // CMD28 or ACMD28 0x1D CMD29 or
1072                                             // ACMD29 0x1E CMD30 or ACMD30 0x1F
1073                                             // CMD31 or ACMD31 0x20 CMD32 or
1074                                             // ACMD32 0x21 CMD33 or ACMD33 0x22
1075                                             // CMD34 or ACMD34 0x23 CMD35 or
1076                                             // ACMD35 0x24 CMD36 or ACMD36 0x25
1077                                             // CMD37 or ACMD37 0x26 CMD38 or
1078                                             // ACMD38 0x27 CMD39 or ACMD39 0x28
1079                                             // CMD40 or ACMD40 0x29 CMD41 or
1080                                             // ACMD41 0x2A CMD42 or ACMD42 0x2B
1081                                             // CMD43 or ACMD43 0x2C CMD44 or
1082                                             // ACMD44 0x2D CMD45 or ACMD45 0x2E
1083                                             // CMD46 or ACMD46 0x2F CMD47 or
1084                                             // ACMD47 0x30 CMD48 or ACMD48 0x31
1085                                             // CMD49 or ACMD49 0x32 CMD50 or
1086                                             // ACMD50 0x33 CMD51 or ACMD51 0x34
1087                                             // CMD52 or ACMD52 0x35 CMD53 or
1088                                             // ACMD53 0x36 CMD54 or ACMD54 0x37
1089                                             // CMD55 or ACMD55 0x38 CMD56 or
1090                                             // ACMD56 0x39 CMD57 or ACMD57 0x3A
1091                                             // CMD58 or ACMD58 0x3B CMD59 or
1092                                             // ACMD59 0x3C CMD60 or ACMD60 0x3D
1093                                             // CMD61 or ACMD61 0x3E CMD62 or
1094                                             // ACMD62 0x3F CMD63 or ACMD63
1095 #define MMCHS_CMD_INDX_S        24
1096 #define MMCHS_CMD_CMD_TYPE_M    0x00C00000  // Command type This register
1097                                             // specifies three types of special
1098                                             // command: Suspend Resume and
1099                                             // Abort. These bits shall be set to
1100                                             // 00b for all other commands. 0x0
1101                                             // Others Commands 0x1 "CMD52 for
1102                                             // writing ""Bus Suspend"" in CCCR"
1103                                             // 0x2 "CMD52 for writing ""Function
1104                                             // Select"" in CCCR" 0x3 "Abort
1105                                             // command CMD12 CMD52 for writing
1106                                             // "" I/O Abort"" in CCCR"
1107 #define MMCHS_CMD_CMD_TYPE_S    22
1108 #define MMCHS_CMD_DP            0x00200000  // Data present select This
1109                                             // register indicates that data is
1110                                             // present and DAT line shall be
1111                                             // used. It must be set to 0 in the
1112                                             // following conditions: - command
1113                                             // using only CMD line - command
1114                                             // with no data transfer but using
1115                                             // busy signal on DAT[0] - Resume
1116                                             // command 0 Command with no data
1117                                             // transfer 1 Command with data
1118                                             // transfer
1119 #define MMCHS_CMD_CICE          0x00100000  // Command Index check enable This
1120                                             // bit must be set to 1 to enable
1121                                             // index check on command response
1122                                             // to compare the index field in the
1123                                             // response against the index of the
1124                                             // command. If the index is not the
1125                                             // same in the response as in the
1126                                             // command it is reported as a
1127                                             // command index error
1128                                             // (MMCHS_STAT[CIE] set to1) Note:
1129                                             // The register CICE cannot be
1130                                             // configured for an Auto CMD12 then
1131                                             // index check is automatically
1132                                             // checked when this command is
1133                                             // issued. 0 Index check disable 1
1134                                             // Index check enable
1135 #define MMCHS_CMD_CCCE          0x00080000  // Command CRC check enable This
1136                                             // bit must be set to 1 to enable
1137                                             // CRC7 check on command response to
1138                                             // protect the response against
1139                                             // transmission errors on the bus.
1140                                             // If an error is detected it is
1141                                             // reported as a command CRC error
1142                                             // (MMCHS_STAT[CCRC] set to 1).
1143                                             // Note: The register CCCE cannot be
1144                                             // configured for an Auto CMD12 and
1145                                             // then CRC check is automatically
1146                                             // checked when this command is
1147                                             // issued. 0 CRC7 check disable 1
1148                                             // CRC7 check enable
1149 #define MMCHS_CMD_RSP_TYPE_M    0x00030000  // Response type This bits defines
1150                                             // the response type of the command
1151                                             // 0x0 No response 0x1 Response
1152                                             // Length 136 bits 0x2 Response
1153                                             // Length 48 bits 0x3 Response
1154                                             // Length 48 bits with busy after
1155                                             // response
1156 #define MMCHS_CMD_RSP_TYPE_S    16
1157 #define MMCHS_CMD_MSBS          0x00000020  // Multi/Single block select This
1158                                             // bit must be set to 1 for data
1159                                             // transfer in case of multi block
1160                                             // command. For any others command
1161                                             // this bit shall be set to 0. 0
1162                                             // Single block. If this bit is 0 it
1163                                             // is not necessary to set the
1164                                             // register MMCHS_BLK[NBLK]. 1 Multi
1165                                             // block. When Block Count is
1166                                             // disabled (MMCHS_CMD[BCE] is set
1167                                             // to 0) in Multiple block transfers
1168                                             // (MMCHS_CMD[MSBS] is set to 1) the
1169                                             // module can perform infinite
1170                                             // transfer.
1171 #define MMCHS_CMD_DDIR          0x00000010  // Data transfer Direction Select
1172                                             // This bit defines either data
1173                                             // transfer will be a read or a
1174                                             // write. 0 Data Write (host to
1175                                             // card) 1 Data Read (card to host)
1176 #define MMCHS_CMD_ACEN          0x00000004  // Auto CMD12 Enable SD card only.
1177                                             // When this bit is set to 1 the
1178                                             // host controller issues a CMD12
1179                                             // automatically after the transfer
1180                                             // completion of the last block. The
1181                                             // Host Driver shall not set this
1182                                             // bit to issue commands that do not
1183                                             // require CMD12 to stop data
1184                                             // transfer. In particular secure
1185                                             // commands do not require CMD12. 0
1186                                             // Auto CMD12 disable 1 Auto CMD12
1187                                             // enable or CCS detection enabled.
1188 #define MMCHS_CMD_BCE           0x00000002  // Block Count Enable Multiple
1189                                             // block transfers only. This bit is
1190                                             // used to enable the block count
1191                                             // register (MMCHS_BLK[NBLK]). When
1192                                             // Block Count is disabled
1193                                             // (MMCHS_CMD[BCE] is set to 0) in
1194                                             // Multiple block transfers
1195                                             // (MMCHS_CMD[MSBS] is set to 1) the
1196                                             // module can perform infinite
1197                                             // transfer. 0 Block count disabled
1198                                             // for infinite transfer. 1 Block
1199                                             // count enabled for multiple block
1200                                             // transfer with known number of
1201                                             // blocks
1202 #define MMCHS_CMD_DE            0x00000001  // DMA Enable This bit is used to
1203                                             // enable DMA mode for host data
1204                                             // access. 0 DMA mode disable 1 DMA
1205                                             // mode enable
1206 //******************************************************************************
1207 //
1208 // The following are defines for the bit fields in the MMCHS_O_RSP10 register.
1209 //
1210 //******************************************************************************
1211 #define MMCHS_RSP10_RSP1_M      0xFFFF0000  // Command Response [31:16]
1212 #define MMCHS_RSP10_RSP1_S      16
1213 #define MMCHS_RSP10_RSP0_M      0x0000FFFF  // Command Response [15:0]
1214 #define MMCHS_RSP10_RSP0_S      0
1215 //******************************************************************************
1216 //
1217 // The following are defines for the bit fields in the MMCHS_O_RSP32 register.
1218 //
1219 //******************************************************************************
1220 #define MMCHS_RSP32_RSP3_M      0xFFFF0000  // Command Response [63:48]
1221 #define MMCHS_RSP32_RSP3_S      16
1222 #define MMCHS_RSP32_RSP2_M      0x0000FFFF  // Command Response [47:32]
1223 #define MMCHS_RSP32_RSP2_S      0
1224 //******************************************************************************
1225 //
1226 // The following are defines for the bit fields in the MMCHS_O_RSP54 register.
1227 //
1228 //******************************************************************************
1229 #define MMCHS_RSP54_RSP5_M      0xFFFF0000  // Command Response [95:80]
1230 #define MMCHS_RSP54_RSP5_S      16
1231 #define MMCHS_RSP54_RSP4_M      0x0000FFFF  // Command Response [79:64]
1232 #define MMCHS_RSP54_RSP4_S      0
1233 //******************************************************************************
1234 //
1235 // The following are defines for the bit fields in the MMCHS_O_RSP76 register.
1236 //
1237 //******************************************************************************
1238 #define MMCHS_RSP76_RSP7_M      0xFFFF0000  // Command Response [127:112]
1239 #define MMCHS_RSP76_RSP7_S      16
1240 #define MMCHS_RSP76_RSP6_M      0x0000FFFF  // Command Response [111:96]
1241 #define MMCHS_RSP76_RSP6_S      0
1242 //******************************************************************************
1243 //
1244 // The following are defines for the bit fields in the MMCHS_O_DATA register.
1245 //
1246 //******************************************************************************
1247 #define MMCHS_DATA_DATA_M       0xFFFFFFFF  // Data Register [31:0] In
1248                                             // functional mode (MMCHS_CON[MODE]
1249                                             // set to the default value 0) A
1250                                             // read access to this register is
1251                                             // allowed only when the buffer read
1252                                             // enable status is set to 1
1253                                             // (MMCHS_PSTATE[BRE]) otherwise a
1254                                             // bad access (MMCHS_STAT[BADA]) is
1255                                             // signaled. A write access to this
1256                                             // register is allowed only when the
1257                                             // buffer write enable status is set
1258                                             // to 1(MMCHS_STATE[BWE]) otherwise
1259                                             // a bad access (MMCHS_STAT[BADA])
1260                                             // is signaled and the data is not
1261                                             // written.
1262 #define MMCHS_DATA_DATA_S       0
1263 //******************************************************************************
1264 //
1265 // The following are defines for the bit fields in the MMCHS_O_PSTATE register.
1266 //
1267 //******************************************************************************
1268 #define MMCHS_PSTATE_CLEV       0x01000000
1269 #define MMCHS_PSTATE_DLEV_M     0x00F00000  // DAT[3:0] line signal level
1270                                             // DAT[3] => bit 23 DAT[2] => bit 22
1271                                             // DAT[1] => bit 21 DAT[0] => bit 20
1272                                             // This status is used to check DAT
1273                                             // line level to recover from errors
1274                                             // and for debugging. This is
1275                                             // especially useful in detecting
1276                                             // the busy signal level from
1277                                             // DAT[0]. The value of these
1278                                             // registers after reset depends on
1279                                             // the DAT lines level at that time.
1280 #define MMCHS_PSTATE_DLEV_S     20
1281 #define MMCHS_PSTATE_WP         0x00080000
1282 #define MMCHS_PSTATE_CDPL       0x00040000
1283 #define MMCHS_PSTATE_CSS        0x00020000
1284 #define MMCHS_PSTATE_CINS       0x00010000
1285 #define MMCHS_PSTATE_BRE        0x00000800
1286 #define MMCHS_PSTATE_BWE        0x00000400
1287 #define MMCHS_PSTATE_RTA        0x00000200
1288 #define MMCHS_PSTATE_WTA        0x00000100
1289 #define MMCHS_PSTATE_DLA        0x00000004
1290 #define MMCHS_PSTATE_DATI       0x00000002
1291 #define MMCHS_PSTATE_CMDI       0x00000001
1292 //******************************************************************************
1293 //
1294 // The following are defines for the bit fields in the MMCHS_O_HCTL register.
1295 //
1296 //******************************************************************************
1297 #define MMCHS_HCTL_OBWE         0x08000000  // Wakeup event enable for
1298                                             // 'Out-of-Band' Interrupt. This bit
1299                                             // enables wakeup events for
1300                                             // 'Out-of-Band' assertion. Wakeup
1301                                             // is generated if the wakeup
1302                                             // feature is enabled
1303                                             // (MMCHS_SYSCONFIG[ENAWAKEUP]). The
1304                                             // write to this register is ignored
1305                                             // when MMCHS_CON[OBIE] is not set.
1306                                             // 0 Disable wakeup on 'Out-of-Band'
1307                                             // Interrupt 1 Enable wakeup on
1308                                             // 'Out-of-Band' Interrupt
1309 #define MMCHS_HCTL_REM          0x04000000  // Wakeup event enable on SD card
1310                                             // removal This bit enables wakeup
1311                                             // events for card removal
1312                                             // assertion. Wakeup is generated if
1313                                             // the wakeup feature is enabled
1314                                             // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0
1315                                             // Disable wakeup on card removal 1
1316                                             // Enable wakeup on card removal
1317 #define MMCHS_HCTL_INS          0x02000000  // Wakeup event enable on SD card
1318                                             // insertion This bit enables wakeup
1319                                             // events for card insertion
1320                                             // assertion. Wakeup is generated if
1321                                             // the wakeup feature is enabled
1322                                             // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0
1323                                             // Disable wakeup on card insertion
1324                                             // 1 Enable wakeup on card insertion
1325 #define MMCHS_HCTL_IWE          0x01000000  // Wakeup event enable on SD card
1326                                             // interrupt This bit enables wakeup
1327                                             // events for card interrupt
1328                                             // assertion. Wakeup is generated if
1329                                             // the wakeup feature is enabled
1330                                             // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0
1331                                             // Disable wakeup on card interrupt
1332                                             // 1 Enable wakeup on card interrupt
1333 #define MMCHS_HCTL_IBG          0x00080000  // Interrupt block at gap This bit
1334                                             // is valid only in 4-bit mode of
1335                                             // SDIO card to enable interrupt
1336                                             // detection in the interrupt cycle
1337                                             // at block gap for a multiple block
1338                                             // transfer. For MMC cards and for
1339                                             // SD card this bit should be set to
1340                                             // 0. 0 Disable interrupt detection
1341                                             // at the block gap in 4-bit mode 1
1342                                             // Enable interrupt detection at the
1343                                             // block gap in 4-bit mode
1344 #define MMCHS_HCTL_RWC          0x00040000  // Read wait control The read wait
1345                                             // function is optional only for
1346                                             // SDIO cards. If the card supports
1347                                             // read wait this bit must be
1348                                             // enabled then requesting a stop at
1349                                             // block gap (MMCHS_HCTL[SBGR])
1350                                             // generates a read wait period
1351                                             // after the current end of block.
1352                                             // Be careful if read wait is not
1353                                             // supported it may cause a conflict
1354                                             // on DAT line. 0 Disable Read Wait
1355                                             // Control. Suspend/Resume cannot be
1356                                             // supported. 1 Enable Read Wait
1357                                             // Control
1358 #define MMCHS_HCTL_CR           0x00020000  // Continue request This bit is
1359                                             // used to restart a transaction
1360                                             // that was stopped by requesting a
1361                                             // stop at block gap
1362                                             // (MMCHS_HCTL[SBGR]). Set this bit
1363                                             // to 1 restarts the transfer. The
1364                                             // bit is automatically set to 0 by
1365                                             // the host controller when transfer
1366                                             // has restarted i.e DAT line is
1367                                             // active (MMCHS_PSTATE[DLA]) or
1368                                             // transferring data
1369                                             // (MMCHS_PSTATE[WTA]). The Stop at
1370                                             // block gap request must be
1371                                             // disabled (MMCHS_HCTL[SBGR]=0)
1372                                             // before setting this bit. 0 No
1373                                             // affect 1 transfer restart
1374 #define MMCHS_HCTL_SBGR         0x00010000  // Stop at block gap request This
1375                                             // bit is used to stop executing a
1376                                             // transaction at the next block
1377                                             // gap. The transfer can restart
1378                                             // with a continue request
1379                                             // (MMHS_HCTL[CR]) or during a
1380                                             // suspend/resume sequence. In case
1381                                             // of read transfer the card must
1382                                             // support read wait control. In
1383                                             // case of write transfer the host
1384                                             // driver shall set this bit after
1385                                             // all block data written. Until the
1386                                             // transfer completion
1387                                             // (MMCHS_STAT[TC] set to 1) the
1388                                             // host driver shall leave this bit
1389                                             // set to 1. If this bit is set the
1390                                             // local host shall not write to the
1391                                             // data register (MMCHS_DATA). 0
1392                                             // Transfer mode 1 Stop at block gap
1393 #define MMCHS_HCTL_SDVS_M       0x00000E00  // SD bus voltage select All cards.
1394                                             // The host driver should set to
1395                                             // these bits to select the voltage
1396                                             // level for the card according to
1397                                             // the voltage supported by the
1398                                             // system (MMCHS_CAPA[VS18VS30VS33])
1399                                             // before starting a transfer. 0x5
1400                                             // 1.8V (Typical) 0x6 3.0V (Typical)
1401                                             // 0x7 3.3V (Typical)
1402 #define MMCHS_HCTL_SDVS_S       9
1403 #define MMCHS_HCTL_SDBP         0x00000100  // SD bus power Before setting this
1404                                             // bit the host driver shall select
1405                                             // the SD bus voltage
1406                                             // (MMCHS_HCTL[SDVS]). If the host
1407                                             // controller detects the No card
1408                                             // state this bit is automatically
1409                                             // set to 0. If the module is power
1410                                             // off a write in the command
1411                                             // register (MMCHS_CMD) will not
1412                                             // start the transfer. A write to
1413                                             // this bit has no effect if the
1414                                             // selected SD bus voltage
1415                                             // MMCHS_HCTL[SDVS] is not supported
1416                                             // according to capability register
1417                                             // (MMCHS_CAPA[VS*]). 0 Power off 1
1418                                             // Power on
1419 #define MMCHS_HCTL_CDSS         0x00000080  // Card Detect Signal Selection
1420                                             // This bit selects source for the
1421                                             // card detection.When the source
1422                                             // for the card detection is
1423                                             // switched the interrupt should be
1424                                             // disabled during the switching
1425                                             // period by clearing the Interrupt
1426                                             // Status/Signal Enable register in
1427                                             // order to mask unexpected
1428                                             // interrupt being caused by the
1429                                             // glitch. The Interrupt
1430                                             // Status/Signal Enable should be
1431                                             // disabled during over the period
1432                                             // of debouncing. 0 SDCD# is
1433                                             // selected (for normal use) 1 The
1434                                             // Card Detect Test Level is
1435                                             // selected (for test purpose)
1436 #define MMCHS_HCTL_CDTL         0x00000040  // Card Detect Test Level: This bit
1437                                             // is enabled while the Card Detect
1438                                             // Signal Selection is set to 1 and
1439                                             // it indicates card inserted or
1440                                             // not. 0 No Card 1 Card Inserted
1441 #define MMCHS_HCTL_DMAS_M       0x00000018  // DMA Select Mode: One of
1442                                             // supported DMA modes can be
1443                                             // selected. The host driver shall
1444                                             // check support of DMA modes by
1445                                             // referring the Capabilities
1446                                             // register. Use of selected DMA is
1447                                             // determined by DMA Enable of the
1448                                             // Transfer Mode register. This
1449                                             // register is only meaningful when
1450                                             // MADMA_EN is set to 1. When
1451                                             // MADMA_EN is set to 0 the bit
1452                                             // field is read only and returned
1453                                             // value is 0. 0x0 Reserved 0x1
1454                                             // Reserved 0x2 32-bit Address ADMA2
1455                                             // is selected 0x3 Reserved
1456 #define MMCHS_HCTL_DMAS_S       3
1457 #define MMCHS_HCTL_HSPE         0x00000004  // High Speed Enable: Before
1458                                             // setting this bit the Host Driver
1459                                             // shall check the High Speed
1460                                             // Support in the Capabilities
1461                                             // register. If this bit is set to 0
1462                                             // (default) the Host Controller
1463                                             // outputs CMD line and DAT lines at
1464                                             // the falling edge of the SD Clock.
1465                                             // If this bit is set to 1 the Host
1466                                             // Controller outputs CMD line and
1467                                             // DAT lines at the rising edge of
1468                                             // the SD Clock.This bit shall not
1469                                             // be set when dual data rate mode
1470                                             // is activated in MMCHS_CON[DDR]. 0
1471                                             // Normal speed mode 1 High speed
1472                                             // mode
1473 #define MMCHS_HCTL_DTW          0x00000002  // Data transfer width For MMC card
1474                                             // this bit must be set following a
1475                                             // valid SWITCH command (CMD6) with
1476                                             // the correct value and extend CSD
1477                                             // index written in the argument.
1478                                             // Prior to this command the MMC
1479                                             // card configuration register (CSD
1480                                             // and EXT_CSD) must be verified for
1481                                             // compliance with MMC standard
1482                                             // specification 4.x (see section
1483                                             // 3.6). This register has no effect
1484                                             // when the MMC 8-bit mode is
1485                                             // selected (register MMCHS_CON[DW8]
1486                                             // set to1 ) For SD/SDIO cards this
1487                                             // bit must be set following a valid
1488                                             // SET_BUS_WIDTH command (ACMD6)
1489                                             // with the value written in bit 1
1490                                             // of the argument. Prior to this
1491                                             // command the SD card configuration
1492                                             // register (SCR) must be verified
1493                                             // for the supported bus width by
1494                                             // the SD card. 0 1-bit Data width
1495                                             // (DAT[0] used) 1 4-bit Data width
1496                                             // (DAT[3:0] used)
1497 //******************************************************************************
1498 //
1499 // The following are defines for the bit fields in the MMCHS_O_SYSCTL register.
1500 //
1501 //******************************************************************************
1502 #define MMCHS_SYSCTL_SRD        0x04000000  // Software reset for DAT line This
1503                                             // bit is set to 1 for reset and
1504                                             // released to 0 when completed. DAT
1505                                             // finite state machine in both
1506                                             // clock domain are also reset. Here
1507                                             // below are the registers cleared
1508                                             // by MMCHS_SYSCTL[SRD]: #VALUE! -
1509                                             // MMCHS_PSTATE: BRE BWE RTA WTA DLA
1510                                             // and DATI - MMCHS_HCTL: SBGR and
1511                                             // CR - MMCHS_STAT: BRR BWR BGE and
1512                                             // TC OCP and MMC buffer data
1513                                             // management is reinitialized. 0
1514                                             // Reset completed 1 Software reset
1515                                             // for DAT line
1516 #define MMCHS_SYSCTL_SRC        0x02000000  // Software reset for CMD line This
1517                                             // bit is set to 1 for reset and
1518                                             // released to 0 when completed. CMD
1519                                             // finite state machine in both
1520                                             // clock domain are also reset. Here
1521                                             // below the registers cleared by
1522                                             // MMCHS_SYSCTL[SRC]: -
1523                                             // MMCHS_PSTATE: CMDI - MMCHS_STAT:
1524                                             // CC OCP and MMC command status
1525                                             // management is reinitialized. 0
1526                                             // Reset completed 1 Software reset
1527                                             // for CMD line
1528 #define MMCHS_SYSCTL_SRA        0x01000000  // Software reset for all This bit
1529                                             // is set to 1 for reset and
1530                                             // released to 0 when completed.
1531                                             // This reset affects the entire
1532                                             // host controller except for the
1533                                             // card detection circuit and
1534                                             // capabilities registers. 0 Reset
1535                                             // completed 1 Software reset for
1536                                             // all the design
1537 #define MMCHS_SYSCTL_DTO_M      0x000F0000  // Data timeout counter value and
1538                                             // busy timeout. This value
1539                                             // determines the interval by which
1540                                             // DAT lines timeouts are detected.
1541                                             // The host driver needs to set this
1542                                             // bitfield based on - the maximum
1543                                             // read access time (NAC) (Refer to
1544                                             // the SD Specification Part1
1545                                             // Physical Layer) - the data read
1546                                             // access time values (TAAC and
1547                                             // NSAC) in the card specific data
1548                                             // register (CSD) of the card - the
1549                                             // timeout clock base frequency
1550                                             // (MMCHS_CAPA[TCF]). If the card
1551                                             // does not respond within the
1552                                             // specified number of cycles a data
1553                                             // timeout error occurs
1554                                             // (MMCHS_STA[DTO]). The
1555                                             // MMCHS_SYSCTL[DTO] register is
1556                                             // also used to check busy duration
1557                                             // to generate busy timeout for
1558                                             // commands with busy response or
1559                                             // for busy programming during a
1560                                             // write command. Timeout on CRC
1561                                             // status is generated if no CRC
1562                                             // token is present after a block
1563                                             // write. 0x0 TCF x 2^13 0x1 TCF x
1564                                             // 2^14 0xE TCF x 2^27 0xF Reserved
1565 #define MMCHS_SYSCTL_DTO_S      16
1566 #define MMCHS_SYSCTL_CLKD_M     0x0000FFC0  // Clock frequency select These
1567                                             // bits define the ratio between a
1568                                             // reference clock frequency (system
1569                                             // dependant) and the output clock
1570                                             // frequency on the CLK pin of
1571                                             // either the memory card (MMC SD or
1572                                             // SDIO). 0x000 Clock Ref bypass
1573                                             // 0x001 Clock Ref bypass 0x002
1574                                             // Clock Ref / 2 0x003 Clock Ref / 3
1575                                             // 0x3FF Clock Ref / 1023
1576 #define MMCHS_SYSCTL_CLKD_S     6
1577 #define MMCHS_SYSCTL_CEN        0x00000004  // Clock enable This bit controls
1578                                             // if the clock is provided to the
1579                                             // card or not. 0 The clock is not
1580                                             // provided to the card . Clock
1581                                             // frequency can be changed . 1 The
1582                                             // clock is provided to the card and
1583                                             // can be automatically gated when
1584                                             // MMCHS_SYSCONFIG[AUTOIDLE] is set
1585                                             // to 1 (default value) . The host
1586                                             // driver shall wait to set this bit
1587                                             // to 1 until the Internal clock is
1588                                             // stable (MMCHS_SYSCTL[ICS]).
1589 #define MMCHS_SYSCTL_ICS        0x00000002
1590 #define MMCHS_SYSCTL_ICE        0x00000001  // Internal clock enable This
1591                                             // register controls the internal
1592                                             // clock activity. In very low power
1593                                             // state the internal clock is
1594                                             // stopped. Note: The activity of
1595                                             // the debounce clock (used for
1596                                             // wakeup events) and the OCP clock
1597                                             // (used for reads and writes to the
1598                                             // module register map) are not
1599                                             // affected by this register. 0 The
1600                                             // internal clock is stopped (very
1601                                             // low power state). 1 The internal
1602                                             // clock oscillates and can be
1603                                             // automatically gated when
1604                                             // MMCHS_SYSCONFIG[AUTOIDLE] is set
1605                                             // to 1 (default value) .
1606 //******************************************************************************
1607 //
1608 // The following are defines for the bit fields in the MMCHS_O_STAT register.
1609 //
1610 //******************************************************************************
1611 #define MMCHS_STAT_BADA         0x20000000
1612 #define MMCHS_STAT_CERR         0x10000000
1613 #define MMCHS_STAT_ADMAE        0x02000000
1614 #define MMCHS_STAT_ACE          0x01000000
1615 #define MMCHS_STAT_DEB          0x00400000
1616 #define MMCHS_STAT_DCRC         0x00200000
1617 #define MMCHS_STAT_DTO          0x00100000
1618 #define MMCHS_STAT_CIE          0x00080000
1619 #define MMCHS_STAT_CEB          0x00040000
1620 #define MMCHS_STAT_CCRC         0x00020000
1621 #define MMCHS_STAT_CTO          0x00010000
1622 #define MMCHS_STAT_ERRI         0x00008000
1623 #define MMCHS_STAT_BSR          0x00000400
1624 #define MMCHS_STAT_OBI          0x00000200
1625 #define MMCHS_STAT_CIRQ         0x00000100
1626 #define MMCHS_STAT_CREM         0x00000080
1627 #define MMCHS_STAT_CINS         0x00000040
1628 #define MMCHS_STAT_BRR          0x00000020
1629 #define MMCHS_STAT_BWR          0x00000010
1630 #define MMCHS_STAT_DMA          0x00000008
1631 #define MMCHS_STAT_BGE          0x00000004
1632 #define MMCHS_STAT_TC           0x00000002
1633 #define MMCHS_STAT_CC           0x00000001
1634 //******************************************************************************
1635 //
1636 // The following are defines for the bit fields in the MMCHS_O_IE register.
1637 //
1638 //******************************************************************************
1639 #define MMCHS_IE_BADA_ENABLE    0x20000000  // Bad access to data space
1640                                             // Interrupt Enable 0 Masked 1
1641                                             // Enabled
1642 #define MMCHS_IE_CERR_ENABLE    0x10000000  // Card error interrupt Enable 0
1643                                             // Masked 1 Enabled
1644 #define MMCHS_IE_ADMAE_ENABLE   0x02000000  // ADMA error Interrupt Enable 0
1645                                             // Masked 1 Enabled
1646 #define MMCHS_IE_ACE_ENABLE     0x01000000  // Auto CMD12 error Interrupt
1647                                             // Enable 0 Masked 1 Enabled
1648 #define MMCHS_IE_DEB_ENABLE     0x00400000  // Data end bit error Interrupt
1649                                             // Enable 0 Masked 1 Enabled
1650 #define MMCHS_IE_DCRC_ENABLE    0x00200000  // Data CRC error Interrupt Enable
1651                                             // 0 Masked 1 Enabled
1652 #define MMCHS_IE_DTO_ENABLE     0x00100000  // Data timeout error Interrupt
1653                                             // Enable 0 The data timeout
1654                                             // detection is deactivated. The
1655                                             // host controller provides the
1656                                             // clock to the card until the card
1657                                             // sends the data or the transfer is
1658                                             // aborted. 1 The data timeout
1659                                             // detection is enabled.
1660 #define MMCHS_IE_CIE_ENABLE     0x00080000  // Command index error Interrupt
1661                                             // Enable 0 Masked 1 Enabled
1662 #define MMCHS_IE_CEB_ENABLE     0x00040000  // Command end bit error Interrupt
1663                                             // Enable 0 Masked 1 Enabled
1664 #define MMCHS_IE_CCRC_ENABLE    0x00020000  // Command CRC error Interrupt
1665                                             // Enable 0 Masked 1 Enabled
1666 #define MMCHS_IE_CTO_ENABLE     0x00010000  // Command timeout error Interrupt
1667                                             // Enable 0 Masked 1 Enabled
1668 #define MMCHS_IE_NULL           0x00008000  // Fixed to 0 The host driver shall
1669                                             // control error interrupts using
1670                                             // the Error Interrupt Signal Enable
1671                                             // register. Writes to this bit are
1672                                             // ignored
1673 #define MMCHS_IE_BSR_ENABLE     0x00000400  // Boot status interrupt Enable A
1674                                             // write to this register when
1675                                             // MMCHS_CON[BOOT_ACK] is set to 0x0
1676                                             // is ignored. 0 Masked 1 Enabled
1677 #define MMCHS_IE_OBI_ENABLE     0x00000200  // Out-of-Band interrupt Enable A
1678                                             // write to this register when
1679                                             // MMCHS_CON[OBIE] is set to '0' is
1680                                             // ignored. 0 Masked 1 Enabled
1681 #define MMCHS_IE_CIRQ_ENABLE    0x00000100  // Card interrupt Enable A clear of
1682                                             // this bit also clears the
1683                                             // corresponding status bit. During
1684                                             // 1-bit mode if the interrupt
1685                                             // routine doesn't remove the source
1686                                             // of a card interrupt in the SDIO
1687                                             // card the status bit is reasserted
1688                                             // when this bit is set to 1. 0
1689                                             // Masked 1 Enabled
1690 #define MMCHS_IE_CREM_ENABLE    0x00000080  // Card removal Interrupt Enable 0
1691                                             // Masked 1 Enabled
1692 #define MMCHS_IE_CINS_ENABLE    0x00000040  // Card insertion Interrupt Enable
1693                                             // 0 Masked 1 Enabled
1694 #define MMCHS_IE_BRR_ENABLE     0x00000020  // Buffer Read Ready Interrupt
1695                                             // Enable 0 Masked 1 Enabled
1696 #define MMCHS_IE_BWR_ENABLE     0x00000010  // Buffer Write Ready Interrupt
1697                                             // Enable 0 Masked 1 Enabled
1698 #define MMCHS_IE_DMA_ENABLE     0x00000008  // DMA interrupt Enable 0 Masked 1
1699                                             // Enabled
1700 #define MMCHS_IE_BGE_ENABLE     0x00000004  // Block Gap Event Interrupt Enable
1701                                             // 0 Masked 1 Enabled
1702 #define MMCHS_IE_TC_ENABLE      0x00000002  // Transfer completed Interrupt
1703                                             // Enable 0 Masked 1 Enabled
1704 #define MMCHS_IE_CC_ENABLE      0x00000001  // Command completed Interrupt
1705                                             // Enable 0 Masked 1 Enabled
1706 //******************************************************************************
1707 //
1708 // The following are defines for the bit fields in the MMCHS_O_ISE register.
1709 //
1710 //******************************************************************************
1711 #define MMCHS_ISE_BADA_SIGEN    0x20000000  // Bad access to data space signal
1712                                             // status Enable 0 Masked 1 Enabled
1713 #define MMCHS_ISE_CERR_SIGEN    0x10000000  // Card error interrupt signal
1714                                             // status Enable 0 Masked 1 Enabled
1715 #define MMCHS_ISE_ADMAE_SIGEN   0x02000000  // ADMA error signal status Enable
1716                                             // 0 Masked 1 Enabled
1717 #define MMCHS_ISE_ACE_SIGEN     0x01000000  // Auto CMD12 error signal status
1718                                             // Enable 0 Masked 1 Enabled
1719 #define MMCHS_ISE_DEB_SIGEN     0x00400000  // Data end bit error signal status
1720                                             // Enable 0 Masked 1 Enabled
1721 #define MMCHS_ISE_DCRC_SIGEN    0x00200000  // Data CRC error signal status
1722                                             // Enable 0 Masked 1 Enabled
1723 #define MMCHS_ISE_DTO_SIGEN     0x00100000  // Data timeout error signal status
1724                                             // Enable 0 Masked 1 Enabled
1725 #define MMCHS_ISE_CIE_SIGEN     0x00080000  // Command index error signal
1726                                             // status Enable 0 Masked 1 Enabled
1727 #define MMCHS_ISE_CEB_SIGEN     0x00040000  // Command end bit error signal
1728                                             // status Enable 0 Masked 1 Enabled
1729 #define MMCHS_ISE_CCRC_SIGEN    0x00020000  // Command CRC error signal status
1730                                             // Enable 0 Masked 1 Enabled
1731 #define MMCHS_ISE_CTO_SIGEN     0x00010000  // Command timeout error signal
1732                                             // status Enable 0 Masked 1 Enabled
1733 #define MMCHS_ISE_NULL          0x00008000  // Fixed to 0 The host driver shall
1734                                             // control error interrupts using
1735                                             // the Error Interrupt Signal Enable
1736                                             // register. Writes to this bit are
1737                                             // ignored
1738 #define MMCHS_ISE_BSR_SIGEN     0x00000400  // Boot status signal status
1739                                             // EnableA write to this register
1740                                             // when MMCHS_CON[BOOT_ACK] is set
1741                                             // to 0x0 is ignored. 0 Masked 1
1742                                             // Enabled
1743 #define MMCHS_ISE_OBI_SIGEN     0x00000200  // Out-Of-Band Interrupt signal
1744                                             // status Enable A write to this
1745                                             // register when MMCHS_CON[OBIE] is
1746                                             // set to '0' is ignored. 0 Masked 1
1747                                             // Enabled
1748 #define MMCHS_ISE_CIRQ_SIGEN    0x00000100  // Card interrupt signal status
1749                                             // Enable 0 Masked 1 Enabled
1750 #define MMCHS_ISE_CREM_SIGEN    0x00000080  // Card removal signal status
1751                                             // Enable 0 Masked 1 Enabled
1752 #define MMCHS_ISE_CINS_SIGEN    0x00000040  // Card insertion signal status
1753                                             // Enable 0 Masked 1 Enabled
1754 #define MMCHS_ISE_BRR_SIGEN     0x00000020  // Buffer Read Ready signal status
1755                                             // Enable 0 Masked 1 Enabled
1756 #define MMCHS_ISE_BWR_SIGEN     0x00000010  // Buffer Write Ready signal status
1757                                             // Enable 0 Masked 1 Enabled
1758 #define MMCHS_ISE_DMA_SIGEN     0x00000008  // DMA interrupt Signal status
1759                                             // enable 0 Masked 1 Enabled
1760 #define MMCHS_ISE_BGE_SIGEN     0x00000004  // Black Gap Event signal status
1761                                             // Enable 0 Masked 1 Enabled
1762 #define MMCHS_ISE_TC_SIGEN      0x00000002  // Transfer completed signal status
1763                                             // Enable 0 Masked 1 Enabled
1764 #define MMCHS_ISE_CC_SIGEN      0x00000001  // Command completed signal status
1765                                             // Enable 0 Masked 1 Enabled
1766 //******************************************************************************
1767 //
1768 // The following are defines for the bit fields in the MMCHS_O_AC12 register.
1769 //
1770 //******************************************************************************
1771 #define MMCHS_AC12_CNI          0x00000080
1772 #define MMCHS_AC12_ACIE         0x00000010
1773 #define MMCHS_AC12_ACEB         0x00000008
1774 #define MMCHS_AC12_ACCE         0x00000004
1775 #define MMCHS_AC12_ACTO         0x00000002
1776 #define MMCHS_AC12_ACNE         0x00000001
1777 //******************************************************************************
1778 //
1779 // The following are defines for the bit fields in the MMCHS_O_CAPA register.
1780 //
1781 //******************************************************************************
1782 #define MMCHS_CAPA_BIT64        0x10000000
1783 #define MMCHS_CAPA_VS18         0x04000000
1784 #define MMCHS_CAPA_VS30         0x02000000
1785 #define MMCHS_CAPA_VS33         0x01000000
1786 #define MMCHS_CAPA_SRS          0x00800000
1787 #define MMCHS_CAPA_DS           0x00400000
1788 #define MMCHS_CAPA_HSS          0x00200000
1789 #define MMCHS_CAPA_AD2S         0x00080000
1790 #define MMCHS_CAPA_MBL_M        0x00030000
1791 #define MMCHS_CAPA_MBL_S        16
1792 #define MMCHS_CAPA_BCF_M        0x00003F00
1793 #define MMCHS_CAPA_BCF_S        8
1794 #define MMCHS_CAPA_TCU          0x00000080
1795 #define MMCHS_CAPA_TCF_M        0x0000003F
1796 #define MMCHS_CAPA_TCF_S        0
1797 //******************************************************************************
1798 //
1799 // The following are defines for the bit fields in the MMCHS_O_CUR_CAPA register.
1800 //
1801 //******************************************************************************
1802 #define MMCHS_CUR_CAPA_CUR_1V8_M \
1803                                 0x00FF0000
1804 
1805 #define MMCHS_CUR_CAPA_CUR_1V8_S 16
1806 #define MMCHS_CUR_CAPA_CUR_3V0_M \
1807                                 0x0000FF00
1808 
1809 #define MMCHS_CUR_CAPA_CUR_3V0_S 8
1810 #define MMCHS_CUR_CAPA_CUR_3V3_M \
1811                                 0x000000FF
1812 
1813 #define MMCHS_CUR_CAPA_CUR_3V3_S 0
1814 //******************************************************************************
1815 //
1816 // The following are defines for the bit fields in the MMCHS_O_FE register.
1817 //
1818 //******************************************************************************
1819 #define MMCHS_FE_FE_BADA        0x20000000
1820 #define MMCHS_FE_FE_CERR        0x10000000
1821 #define MMCHS_FE_FE_ADMAE       0x02000000
1822 #define MMCHS_FE_FE_ACE         0x01000000
1823 #define MMCHS_FE_FE_DEB         0x00400000
1824 #define MMCHS_FE_FE_DCRC        0x00200000
1825 #define MMCHS_FE_FE_DTO         0x00100000
1826 #define MMCHS_FE_FE_CIE         0x00080000
1827 #define MMCHS_FE_FE_CEB         0x00040000
1828 #define MMCHS_FE_FE_CCRC        0x00020000
1829 #define MMCHS_FE_FE_CTO         0x00010000
1830 #define MMCHS_FE_FE_CNI         0x00000080
1831 #define MMCHS_FE_FE_ACIE        0x00000010
1832 #define MMCHS_FE_FE_ACEB        0x00000008
1833 #define MMCHS_FE_FE_ACCE        0x00000004
1834 #define MMCHS_FE_FE_ACTO        0x00000002
1835 #define MMCHS_FE_FE_ACNE        0x00000001
1836 //******************************************************************************
1837 //
1838 // The following are defines for the bit fields in the MMCHS_O_ADMAES register.
1839 //
1840 //******************************************************************************
1841 #define MMCHS_ADMAES_LME        0x00000004  // ADMA Length Mismatch Error: (1)
1842                                             // While Block Count Enable being
1843                                             // set the total data length
1844                                             // specified by the Descriptor table
1845                                             // is different from that specified
1846                                             // by the Block Count and Block
1847                                             // Length. (2) Total data length can
1848                                             // not be divided by the block
1849                                             // length. 0 No Error 1 Error
1850 #define MMCHS_ADMAES_AES_M      0x00000003  // ADMA Error State his field
1851                                             // indicates the state of ADMA when
1852                                             // error is occurred during ADMA
1853                                             // data transfer. "This field never
1854                                             // indicates ""10"" because ADMA
1855                                             // never stops in this state." 0x0
1856                                             // ST_STOP (Stop DMA)Contents of
1857                                             // SYS_SDR register 0x1 ST_STOP
1858                                             // (Stop DMA)Points the error
1859                                             // descriptor 0x2 Never set this
1860                                             // state(Not used) 0x3 ST_TFR
1861                                             // (Transfer Data)Points the next of
1862                                             // the error descriptor
1863 #define MMCHS_ADMAES_AES_S      0
1864 //******************************************************************************
1865 //
1866 // The following are defines for the bit fields in the MMCHS_O_ADMASAL register.
1867 //
1868 //******************************************************************************
1869 #define MMCHS_ADMASAL_ADMA_A32B_M \
1870                                 0xFFFFFFFF  // ADMA System address 32 bits.This
1871                                             // register holds byte address of
1872                                             // executing command of the
1873                                             // Descriptor table. 32-bit Address
1874                                             // Descriptor uses lower 32-bit of
1875                                             // this register. At the start of
1876                                             // ADMA the Host Driver shall set
1877                                             // start address of the Descriptor
1878                                             // table. The ADMA increments this
1879                                             // register address which points to
1880                                             // next line when every fetching a
1881                                             // Descriptor line. When the ADMA
1882                                             // Error Interrupt is generated this
1883                                             // register shall hold valid
1884                                             // Descriptor address depending on
1885                                             // the ADMA state. The Host Driver
1886                                             // shall program Descriptor Table on
1887                                             // 32-bit boundary and set 32-bit
1888                                             // boundary address to this
1889                                             // register. ADMA2 ignores lower
1890                                             // 2-bit of this register and
1891                                             // assumes it to be 00b.
1892 
1893 #define MMCHS_ADMASAL_ADMA_A32B_S 0
1894 //******************************************************************************
1895 //
1896 // The following are defines for the bit fields in the MMCHS_O_REV register.
1897 //
1898 //******************************************************************************
1899 #define MMCHS_REV_VREV_M        0xFF000000  // Vendor Version Number: IP
1900                                             // revision [7:4] Major revision
1901                                             // [3:0] Minor revision Examples:
1902                                             // 0x10 for 1.0 0x21 for 2.1
1903 #define MMCHS_REV_VREV_S        24
1904 #define MMCHS_REV_SREV_M        0x00FF0000
1905 #define MMCHS_REV_SREV_S        16
1906 #define MMCHS_REV_SIS           0x00000001  // Slot Interrupt Status This
1907                                             // status bit indicates the inverted
1908                                             // state of interrupt signal for the
1909                                             // module. By a power on reset or by
1910                                             // setting a software reset for all
1911                                             // (MMCHS_HCTL[SRA]) the interrupt
1912                                             // signal shall be de-asserted and
1913                                             // this status shall read 0.
1914 
1915 
1916 
1917 #endif // __HW_MMCHS_H__
1918