1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_MCSPI_H__ 35 #define __HW_MCSPI_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the MCSPI register offsets. 40 // 41 //***************************************************************************** 42 #define MCSPI_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) 43 // Used by software to track 44 // features bugs and compatibility 45 #define MCSPI_O_HL_HWINFO 0x00000004 // Information about the IP 46 // module's hardware configuration 47 // i.e. typically the module's HDL 48 // generics (if any). Actual field 49 // format and encoding is up to the 50 // module's designer to decide. 51 #define MCSPI_O_HL_SYSCONFIG 0x00000010 // 0x4402 1010 0x4402 2010 Clock 52 // management configuration 53 #define MCSPI_O_REVISION 0x00000100 // 0x4402 1100 0x4402 2100 This 54 // register contains the hard coded 55 // RTL revision number. 56 #define MCSPI_O_SYSCONFIG 0x00000110 // 0x4402 1110 0x4402 2110 This 57 // register allows controlling 58 // various parameters of the OCP 59 // interface. 60 #define MCSPI_O_SYSSTATUS 0x00000114 // 0x4402 1114 0x4402 2114 This 61 // register provides status 62 // information about the module 63 // excluding the interrupt status 64 // information 65 #define MCSPI_O_IRQSTATUS 0x00000118 // 0x4402 1118 0x4402 2118 The 66 // interrupt status regroups all the 67 // status of the module internal 68 // events that can generate an 69 // interrupt 70 #define MCSPI_O_IRQENABLE 0x0000011C // 0x4402 111C 0x4402 211C This 71 // register allows to enable/disable 72 // the module internal sources of 73 // interrupt on an event-by-event 74 // basis. 75 #define MCSPI_O_WAKEUPENABLE 0x00000120 // 0x4402 1120 0x4402 2120 The 76 // wakeup enable register allows to 77 // enable/disable the module 78 // internal sources of wakeup on 79 // event-by-event basis. 80 #define MCSPI_O_SYST 0x00000124 // 0x4402 1124 0x4402 2124 This 81 // register is used to check the 82 // correctness of the system 83 // interconnect either internally to 84 // peripheral bus or externally to 85 // device IO pads when the module is 86 // configured in system test 87 // (SYSTEST) mode. 88 #define MCSPI_O_MODULCTRL 0x00000128 // 0x4402 1128 0x4402 2128 This 89 // register is dedicated to the 90 // configuration of the serial port 91 // interface. 92 #define MCSPI_O_CH0CONF 0x0000012C // 0x4402 112C 0x4402 212C This 93 // register is dedicated to the 94 // configuration of the channel 0 95 #define MCSPI_O_CH0STAT 0x00000130 // 0x4402 1130 0x4402 2130 This 96 // register provides status 97 // information about transmitter and 98 // receiver registers of channel 0 99 #define MCSPI_O_CH0CTRL 0x00000134 // 0x4402 1134 0x4402 2134 This 100 // register is dedicated to enable 101 // the channel 0 102 #define MCSPI_O_TX0 0x00000138 // 0x4402 1138 0x4402 2138 This 103 // register contains a single SPI 104 // word to transmit on the serial 105 // link what ever SPI word length 106 // is. 107 #define MCSPI_O_RX0 0x0000013C // 0x4402 113C 0x4402 213C This 108 // register contains a single SPI 109 // word received through the serial 110 // link what ever SPI word length 111 // is. 112 #define MCSPI_O_CH1CONF 0x00000140 // 0x4402 1140 0x4402 2140 This 113 // register is dedicated to the 114 // configuration of the channel. 115 #define MCSPI_O_CH1STAT 0x00000144 // 0x4402 1144 0x4402 2144 This 116 // register provides status 117 // information about transmitter and 118 // receiver registers of channel 1 119 #define MCSPI_O_CH1CTRL 0x00000148 // 0x4402 1148 0x4402 2148 This 120 // register is dedicated to enable 121 // the channel 1 122 #define MCSPI_O_TX1 0x0000014C // 0x4402 114C 0x4402 214C This 123 // register contains a single SPI 124 // word to transmit on the serial 125 // link what ever SPI word length 126 // is. 127 #define MCSPI_O_RX1 0x00000150 // 0x4402 1150 0x4402 2150 This 128 // register contains a single SPI 129 // word received through the serial 130 // link what ever SPI word length 131 // is. 132 #define MCSPI_O_CH2CONF 0x00000154 // 0x4402 1154 0x4402 2154 This 133 // register is dedicated to the 134 // configuration of the channel 2 135 #define MCSPI_O_CH2STAT 0x00000158 // 0x4402 1158 0x4402 2158 This 136 // register provides status 137 // information about transmitter and 138 // receiver registers of channel 2 139 #define MCSPI_O_CH2CTRL 0x0000015C // 0x4402 115C 0x4402 215C This 140 // register is dedicated to enable 141 // the channel 2 142 #define MCSPI_O_TX2 0x00000160 // 0x4402 1160 0x4402 2160 This 143 // register contains a single SPI 144 // word to transmit on the serial 145 // link what ever SPI word length 146 // is. 147 #define MCSPI_O_RX2 0x00000164 // 0x4402 1164 0x4402 2164 This 148 // register contains a single SPI 149 // word received through the serial 150 // link what ever SPI word length 151 // is. 152 #define MCSPI_O_CH3CONF 0x00000168 // 0x4402 1168 0x4402 2168 This 153 // register is dedicated to the 154 // configuration of the channel 3 155 #define MCSPI_O_CH3STAT 0x0000016C // 0x4402 116C 0x4402 216C This 156 // register provides status 157 // information about transmitter and 158 // receiver registers of channel 3 159 #define MCSPI_O_CH3CTRL 0x00000170 // 0x4402 1170 0x4402 2170 This 160 // register is dedicated to enable 161 // the channel 3 162 #define MCSPI_O_TX3 0x00000174 // 0x4402 1174 0x4402 2174 This 163 // register contains a single SPI 164 // word to transmit on the serial 165 // link what ever SPI word length 166 // is. 167 #define MCSPI_O_RX3 0x00000178 // 0x4402 1178 0x4402 2178 This 168 // register contains a single SPI 169 // word received through the serial 170 // link what ever SPI word length 171 // is. 172 #define MCSPI_O_XFERLEVEL 0x0000017C // 0x4402 117C 0x4402 217C This 173 // register provides transfer levels 174 // needed while using FIFO buffer 175 // during transfer. 176 #define MCSPI_O_DAFTX 0x00000180 // 0x4402 1180 0x4402 2180 This 177 // register contains the SPI words 178 // to transmit on the serial link 179 // when FIFO used and DMA address is 180 // aligned on 256 bit.This register 181 // is an image of one of MCSPI_TX(i) 182 // register corresponding to the 183 // channel which have its FIFO 184 // enabled. 185 #define MCSPI_O_DAFRX 0x000001A0 // 0x4402 11A0 0x4402 21A0 This 186 // register contains the SPI words 187 // to received on the serial link 188 // when FIFO used and DMA address is 189 // aligned on 256 bit.This register 190 // is an image of one of MCSPI_RX(i) 191 // register corresponding to the 192 // channel which have its FIFO 193 // enabled. 194 195 196 197 //****************************************************************************** 198 // 199 // The following are defines for the bit fields in the MCSPI_O_HL_REV register. 200 // 201 //****************************************************************************** 202 #define MCSPI_HL_REV_SCHEME_M 0xC0000000 203 #define MCSPI_HL_REV_SCHEME_S 30 204 #define MCSPI_HL_REV_RSVD_M 0x30000000 // Reserved These bits are 205 // initialized to zero and writes to 206 // them are ignored. 207 #define MCSPI_HL_REV_RSVD_S 28 208 #define MCSPI_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software 209 // compatible module family. If 210 // there is no level of software 211 // compatibility a new Func number 212 // (and hence REVISION) should be 213 // assigned. 214 #define MCSPI_HL_REV_FUNC_S 16 215 #define MCSPI_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP 216 // design owner. RTL follows a 217 // numbering such as X.Y.R.Z which 218 // are explained in this table. R 219 // changes ONLY when: (1) PDS 220 // uploads occur which may have been 221 // due to spec changes (2) Bug fixes 222 // occur (3) Resets to '0' when X or 223 // Y changes. Design team has an 224 // internal 'Z' (customer invisible) 225 // number which increments on every 226 // drop that happens due to DV and 227 // RTL updates. Z resets to 0 when R 228 // increments. 229 #define MCSPI_HL_REV_R_RTL_S 11 230 #define MCSPI_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by 231 // IP specification owner. X changes 232 // ONLY when: (1) There is a major 233 // feature addition. An example 234 // would be adding Master Mode to 235 // Utopia Level2. The Func field (or 236 // Class/Type in old PID format) 237 // will remain the same. X does NOT 238 // change due to: (1) Bug fixes (2) 239 // Change in feature parameters. 240 #define MCSPI_HL_REV_X_MAJOR_S 8 241 #define MCSPI_HL_REV_CUSTOM_M 0x000000C0 242 #define MCSPI_HL_REV_CUSTOM_S 6 243 #define MCSPI_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by 244 // IP specification owner. Y changes 245 // ONLY when: (1) Features are 246 // scaled (up or down). Flexibility 247 // exists in that this feature 248 // scalability may either be 249 // represented in the Y change or a 250 // specific register in the IP that 251 // indicates which features are 252 // exactly available. (2) When 253 // feature creeps from Is-Not list 254 // to Is list. But this may not be 255 // the case once it sees silicon; in 256 // which case X will change. Y does 257 // NOT change due to: (1) Bug fixes 258 // (2) Typos or clarifications (3) 259 // major functional/feature 260 // change/addition/deletion. Instead 261 // these changes may be reflected 262 // via R S X as applicable. Spec 263 // owner maintains a 264 // customer-invisible number 'S' 265 // which changes due to: (1) 266 // Typos/clarifications (2) Bug 267 // documentation. Note that this bug 268 // is not due to a spec change but 269 // due to implementation. 270 // Nevertheless the spec tracks the 271 // IP bugs. An RTL release (say for 272 // silicon PG1.1) that occurs due to 273 // bug fix should document the 274 // corresponding spec number (X.Y.S) 275 // in its release notes. 276 #define MCSPI_HL_REV_Y_MINOR_S 0 277 //****************************************************************************** 278 // 279 // The following are defines for the bit fields in the MCSPI_O_HL_HWINFO register. 280 // 281 //****************************************************************************** 282 #define MCSPI_HL_HWINFO_RETMODE 0x00000040 283 #define MCSPI_HL_HWINFO_FFNBYTE_M \ 284 0x0000003E 285 286 #define MCSPI_HL_HWINFO_FFNBYTE_S 1 287 #define MCSPI_HL_HWINFO_USEFIFO 0x00000001 288 //****************************************************************************** 289 // 290 // The following are defines for the bit fields in the 291 // MCSPI_O_HL_SYSCONFIG register. 292 // 293 //****************************************************************************** 294 #define MCSPI_HL_SYSCONFIG_IDLEMODE_M \ 295 0x0000000C // Configuration of the local 296 // target state management mode. By 297 // definition target can handle 298 // read/write transaction as long as 299 // it is out of IDLE state. 0x0 300 // Force-idle mode: local target's 301 // idle state follows (acknowledges) 302 // the system's idle requests 303 // unconditionally i.e. regardless 304 // of the IP module's internal 305 // requirements.Backup mode for 306 // debug only. 0x1 No-idle mode: 307 // local target never enters idle 308 // state.Backup mode for debug only. 309 // 0x2 Smart-idle mode: local 310 // target's idle state eventually 311 // follows (acknowledges) the 312 // system's idle requests depending 313 // on the IP module's internal 314 // requirements.IP module shall not 315 // generate (IRQ- or 316 // DMA-request-related) wakeup 317 // events. 0x3 "Smart-idle 318 // wakeup-capable mode: local 319 // target's idle state eventually 320 // follows (acknowledges) the 321 // system's idle requests depending 322 // on the IP module's internal 323 // requirements.IP module may 324 // generate (IRQ- or 325 // DMA-request-related) wakeup 326 // events when in idle state.Mode is 327 // only relevant if the appropriate 328 // IP module ""swakeup"" output(s) 329 // is (are) implemented." 330 331 #define MCSPI_HL_SYSCONFIG_IDLEMODE_S 2 332 #define MCSPI_HL_SYSCONFIG_FREEEMU \ 333 0x00000002 // Sensitivity to emulation (debug) 334 // suspend input signal. 0 IP module 335 // is sensitive to emulation suspend 336 // 1 IP module is not sensitive to 337 // emulation suspend 338 339 #define MCSPI_HL_SYSCONFIG_SOFTRESET \ 340 0x00000001 341 342 //****************************************************************************** 343 // 344 // The following are defines for the bit fields in the MCSPI_O_REVISION register. 345 // 346 //****************************************************************************** 347 #define MCSPI_REVISION_REV_M 0x000000FF // IP revision [7:4] Major revision 348 // [3:0] Minor revision Examples: 349 // 0x10 for 1.0 0x21 for 2.1 350 #define MCSPI_REVISION_REV_S 0 351 //****************************************************************************** 352 // 353 // The following are defines for the bit fields in the MCSPI_O_SYSCONFIG register. 354 // 355 //****************************************************************************** 356 #define MCSPI_SYSCONFIG_CLOCKACTIVITY_M \ 357 0x00000300 // Clocks activity during wake up 358 // mode period 0x0 OCP and 359 // Functional clocks may be switched 360 // off. 0x1 OCP clock is maintained. 361 // Functional clock may be 362 // switched-off. 0x2 Functional 363 // clock is maintained. OCP clock 364 // may be switched-off. 0x3 OCP and 365 // Functional clocks are maintained. 366 367 #define MCSPI_SYSCONFIG_CLOCKACTIVITY_S 8 368 #define MCSPI_SYSCONFIG_SIDLEMODE_M \ 369 0x00000018 // Power management 0x0 If an idle 370 // request is detected the McSPI 371 // acknowledges it unconditionally 372 // and goes in Inactive mode. 373 // Interrupt DMA requests and wake 374 // up lines are unconditionally 375 // de-asserted and the module wakeup 376 // capability is deactivated even if 377 // the bit 378 // MCSPI_SYSCONFIG[EnaWakeUp] is 379 // set. 0x1 If an idle request is 380 // detected the request is ignored 381 // and the module does not switch to 382 // wake up mode and keeps on 383 // behaving normally. 0x2 If an idle 384 // request is detected the module 385 // will switch to idle mode based on 386 // its internal activity. The wake 387 // up capability cannot be used. 0x3 388 // If an idle request is detected 389 // the module will switch to idle 390 // mode based on its internal 391 // activity and the wake up 392 // capability can be used if the bit 393 // MCSPI_SYSCONFIG[EnaWakeUp] is 394 // set. 395 396 #define MCSPI_SYSCONFIG_SIDLEMODE_S 3 397 #define MCSPI_SYSCONFIG_ENAWAKEUP \ 398 0x00000004 // WakeUp feature control 0 WakeUp 399 // capability is disabled 1 WakeUp 400 // capability is enabled 401 402 #define MCSPI_SYSCONFIG_SOFTRESET \ 403 0x00000002 // Software reset. During reads it 404 // always returns 0. 0 (write) 405 // Normal mode 1 (write) Set this 406 // bit to 1 to trigger a module 407 // reset.The bit is automatically 408 // reset by the hardware. 409 410 #define MCSPI_SYSCONFIG_AUTOIDLE \ 411 0x00000001 // Internal OCP Clock gating 412 // strategy 0 OCP clock is 413 // free-running 1 Automatic OCP 414 // clock gating strategy is applied 415 // based on the OCP interface 416 // activity 417 418 //****************************************************************************** 419 // 420 // The following are defines for the bit fields in the MCSPI_O_SYSSTATUS register. 421 // 422 //****************************************************************************** 423 #define MCSPI_SYSSTATUS_RESETDONE \ 424 0x00000001 425 426 //****************************************************************************** 427 // 428 // The following are defines for the bit fields in the MCSPI_O_IRQSTATUS register. 429 // 430 //****************************************************************************** 431 #define MCSPI_IRQSTATUS_EOW 0x00020000 432 #define MCSPI_IRQSTATUS_WKS 0x00010000 433 #define MCSPI_IRQSTATUS_RX3_FULL \ 434 0x00004000 435 436 #define MCSPI_IRQSTATUS_TX3_UNDERFLOW \ 437 0x00002000 438 439 #define MCSPI_IRQSTATUS_TX3_EMPTY \ 440 0x00001000 441 442 #define MCSPI_IRQSTATUS_RX2_FULL \ 443 0x00000400 444 445 #define MCSPI_IRQSTATUS_TX2_UNDERFLOW \ 446 0x00000200 447 448 #define MCSPI_IRQSTATUS_TX2_EMPTY \ 449 0x00000100 450 451 #define MCSPI_IRQSTATUS_RX1_FULL \ 452 0x00000040 453 454 #define MCSPI_IRQSTATUS_TX1_UNDERFLOW \ 455 0x00000020 456 457 #define MCSPI_IRQSTATUS_TX1_EMPTY \ 458 0x00000010 459 460 #define MCSPI_IRQSTATUS_RX0_OVERFLOW \ 461 0x00000008 462 463 #define MCSPI_IRQSTATUS_RX0_FULL \ 464 0x00000004 465 466 #define MCSPI_IRQSTATUS_TX0_UNDERFLOW \ 467 0x00000002 468 469 #define MCSPI_IRQSTATUS_TX0_EMPTY \ 470 0x00000001 471 472 //****************************************************************************** 473 // 474 // The following are defines for the bit fields in the MCSPI_O_IRQENABLE register. 475 // 476 //****************************************************************************** 477 #define MCSPI_IRQENABLE_EOW_ENABLE \ 478 0x00020000 // End of Word count Interrupt 479 // Enable. 0 Interrupt disabled 1 480 // Interrupt enabled 481 482 #define MCSPI_IRQENABLE_WKE 0x00010000 // Wake Up event interrupt Enable 483 // in slave mode when an active 484 // control signal is detected on the 485 // SPIEN line programmed in the 486 // field MCSPI_CH0CONF[SPIENSLV] 0 487 // Interrupt disabled 1 Interrupt 488 // enabled 489 #define MCSPI_IRQENABLE_RX3_FULL_ENABLE \ 490 0x00004000 // Receiver register Full Interrupt 491 // Enable. Ch 3 0 Interrupt disabled 492 // 1 Interrupt enabled 493 494 #define MCSPI_IRQENABLE_TX3_UNDERFLOW_ENABLE \ 495 0x00002000 // Transmitter register Underflow 496 // Interrupt Enable. Ch 3 0 497 // Interrupt disabled 1 Interrupt 498 // enabled 499 500 #define MCSPI_IRQENABLE_TX3_EMPTY_ENABLE \ 501 0x00001000 // Transmitter register Empty 502 // Interrupt Enable. Ch3 0 Interrupt 503 // disabled 1 Interrupt enabled 504 505 #define MCSPI_IRQENABLE_RX2_FULL_ENABLE \ 506 0x00000400 // Receiver register Full Interrupt 507 // Enable. Ch 2 0 Interrupt disabled 508 // 1 Interrupt enabled 509 510 #define MCSPI_IRQENABLE_TX2_UNDERFLOW_ENABLE \ 511 0x00000200 // Transmitter register Underflow 512 // Interrupt Enable. Ch 2 0 513 // Interrupt disabled 1 Interrupt 514 // enabled 515 516 #define MCSPI_IRQENABLE_TX2_EMPTY_ENABLE \ 517 0x00000100 // Transmitter register Empty 518 // Interrupt Enable. Ch 2 0 519 // Interrupt disabled 1 Interrupt 520 // enabled 521 522 #define MCSPI_IRQENABLE_RX1_FULL_ENABLE \ 523 0x00000040 // Receiver register Full Interrupt 524 // Enable. Ch 1 0 Interrupt disabled 525 // 1 Interrupt enabled 526 527 #define MCSPI_IRQENABLE_TX1_UNDERFLOW_ENABLE \ 528 0x00000020 // Transmitter register Underflow 529 // Interrupt Enable. Ch 1 0 530 // Interrupt disabled 1 Interrupt 531 // enabled 532 533 #define MCSPI_IRQENABLE_TX1_EMPTY_ENABLE \ 534 0x00000010 // Transmitter register Empty 535 // Interrupt Enable. Ch 1 0 536 // Interrupt disabled 1 Interrupt 537 // enabled 538 539 #define MCSPI_IRQENABLE_RX0_OVERFLOW_ENABLE \ 540 0x00000008 // Receiver register Overflow 541 // Interrupt Enable. Ch 0 0 542 // Interrupt disabled 1 Interrupt 543 // enabled 544 545 #define MCSPI_IRQENABLE_RX0_FULL_ENABLE \ 546 0x00000004 // Receiver register Full Interrupt 547 // Enable. Ch 0 0 Interrupt disabled 548 // 1 Interrupt enabled 549 550 #define MCSPI_IRQENABLE_TX0_UNDERFLOW_ENABLE \ 551 0x00000002 // Transmitter register Underflow 552 // Interrupt Enable. Ch 0 0 553 // Interrupt disabled 1 Interrupt 554 // enabled 555 556 #define MCSPI_IRQENABLE_TX0_EMPTY_ENABLE \ 557 0x00000001 // Transmitter register Empty 558 // Interrupt Enable. Ch 0 0 559 // Interrupt disabled 1 Interrupt 560 // enabled 561 562 //****************************************************************************** 563 // 564 // The following are defines for the bit fields in the 565 // MCSPI_O_WAKEUPENABLE register. 566 // 567 //****************************************************************************** 568 #define MCSPI_WAKEUPENABLE_WKEN 0x00000001 // WakeUp functionality in slave 569 // mode when an active control 570 // signal is detected on the SPIEN 571 // line programmed in the field 572 // MCSPI_CH0CONF[SPIENSLV] 0 The 573 // event is not allowed to wakeup 574 // the system even if the global 575 // control bit 576 // MCSPI_SYSCONF[EnaWakeUp] is set. 577 // 1 The event is allowed to wakeup 578 // the system if the global control 579 // bit MCSPI_SYSCONF[EnaWakeUp] is 580 // set. 581 //****************************************************************************** 582 // 583 // The following are defines for the bit fields in the MCSPI_O_SYST register. 584 // 585 //****************************************************************************** 586 #define MCSPI_SYST_SSB 0x00000800 // Set status bit 0 No action. 587 // Writing 0 does not clear already 588 // set status bits; This bit must be 589 // cleared prior attempting to clear 590 // a status bit of the 591 // <MCSPI_IRQSTATUS> register. 1 592 // Force to 1 all status bits of 593 // MCSPI_IRQSTATUS register. Writing 594 // 1 into this bit sets to 1 all 595 // status bits contained in the 596 // <MCSPI_IRQSTATUS> register. 597 #define MCSPI_SYST_SPIENDIR 0x00000400 // Set the direction of the 598 // SPIEN[3:0] lines and SPICLK line 599 // 0 output (as in master mode) 1 600 // input (as in slave mode) 601 #define MCSPI_SYST_SPIDATDIR1 0x00000200 // Set the direction of the 602 // SPIDAT[1] 0 output 1 input 603 #define MCSPI_SYST_SPIDATDIR0 0x00000100 // Set the direction of the 604 // SPIDAT[0] 0 output 1 input 605 #define MCSPI_SYST_WAKD 0x00000080 // SWAKEUP output (signal data 606 // value of internal signal to 607 // system). The signal is driven 608 // high or low according to the 609 // value written into this register 610 // bit. 0 The pin is driven low. 1 611 // The pin is driven high. 612 #define MCSPI_SYST_SPICLK 0x00000040 // SPICLK line (signal data value) 613 // If MCSPI_SYST[SPIENDIR] = 1 614 // (input mode direction) this bit 615 // returns the value on the CLKSPI 616 // line (high or low) and a write 617 // into this bit has no effect. If 618 // MCSPI_SYST[SPIENDIR] = 0 (output 619 // mode direction) the CLKSPI line 620 // is driven high or low according 621 // to the value written into this 622 // register. 623 #define MCSPI_SYST_SPIDAT_1 0x00000020 // SPIDAT[1] line (signal data 624 // value) If MCSPI_SYST[SPIDATDIR1] 625 // = 0 (output mode direction) the 626 // SPIDAT[1] line is driven high or 627 // low according to the value 628 // written into this register. If 629 // MCSPI_SYST[SPIDATDIR1] = 1 (input 630 // mode direction) this bit returns 631 // the value on the SPIDAT[1] line 632 // (high or low) and a write into 633 // this bit has no effect. 634 #define MCSPI_SYST_SPIDAT_0 0x00000010 // SPIDAT[0] line (signal data 635 // value) If MCSPI_SYST[SPIDATDIR0] 636 // = 0 (output mode direction) the 637 // SPIDAT[0] line is driven high or 638 // low according to the value 639 // written into this register. If 640 // MCSPI_SYST[SPIDATDIR0] = 1 (input 641 // mode direction) this bit returns 642 // the value on the SPIDAT[0] line 643 // (high or low) and a write into 644 // this bit has no effect. 645 #define MCSPI_SYST_SPIEN_3 0x00000008 // SPIEN[3] line (signal data 646 // value) If MCSPI_SYST[SPIENDIR] = 647 // 0 (output mode direction) the 648 // SPIENT[3] line is driven high or 649 // low according to the value 650 // written into this register. If 651 // MCSPI_SYST[SPIENDIR] = 1 (input 652 // mode direction) this bit returns 653 // the value on the SPIEN[3] line 654 // (high or low) and a write into 655 // this bit has no effect. 656 #define MCSPI_SYST_SPIEN_2 0x00000004 // SPIEN[2] line (signal data 657 // value) If MCSPI_SYST[SPIENDIR] = 658 // 0 (output mode direction) the 659 // SPIENT[2] line is driven high or 660 // low according to the value 661 // written into this register. If 662 // MCSPI_SYST[SPIENDIR] = 1 (input 663 // mode direction) this bit returns 664 // the value on the SPIEN[2] line 665 // (high or low) and a write into 666 // this bit has no effect. 667 #define MCSPI_SYST_SPIEN_1 0x00000002 // SPIEN[1] line (signal data 668 // value) If MCSPI_SYST[SPIENDIR] = 669 // 0 (output mode direction) the 670 // SPIENT[1] line is driven high or 671 // low according to the value 672 // written into this register. If 673 // MCSPI_SYST[SPIENDIR] = 1 (input 674 // mode direction) this bit returns 675 // the value on the SPIEN[1] line 676 // (high or low) and a write into 677 // this bit has no effect. 678 #define MCSPI_SYST_SPIEN_0 0x00000001 // SPIEN[0] line (signal data 679 // value) If MCSPI_SYST[SPIENDIR] = 680 // 0 (output mode direction) the 681 // SPIENT[0] line is driven high or 682 // low according to the value 683 // written into this register. If 684 // MCSPI_SYST[SPIENDIR] = 1 (input 685 // mode direction) this bit returns 686 // the value on the SPIEN[0] line 687 // (high or low) and a write into 688 // this bit has no effect. 689 //****************************************************************************** 690 // 691 // The following are defines for the bit fields in the MCSPI_O_MODULCTRL register. 692 // 693 //****************************************************************************** 694 #define MCSPI_MODULCTRL_FDAA 0x00000100 // FIFO DMA Address 256-bit aligned 695 // This register is used when a FIFO 696 // is managed by the module and DMA 697 // connected to the controller 698 // provides only 256 bit aligned 699 // address. If this bit is set the 700 // enabled channel which uses the 701 // FIFO has its datas managed 702 // through MCSPI_DAFTX and 703 // MCSPI_DAFRX registers instead of 704 // MCSPI_TX(i) and MCSPI_RX(i) 705 // registers. 0 FIFO data managed by 706 // MCSPI_TX(i) and MCSPI_RX(i) 707 // registers. 1 FIFO data managed by 708 // MCSPI_DAFTX and MCSPI_DAFRX 709 // registers. 710 #define MCSPI_MODULCTRL_MOA 0x00000080 // Multiple word ocp access: This 711 // register can only be used when a 712 // channel is enabled using a FIFO. 713 // It allows the system to perform 714 // multiple SPI word access for a 715 // single 32-bit OCP word access. 716 // This is possible for WL < 16. 0 717 // Multiple word access disabled 1 718 // Multiple word access enabled with 719 // FIFO 720 #define MCSPI_MODULCTRL_INITDLY_M \ 721 0x00000070 // Initial spi delay for first 722 // transfer: This register is an 723 // option only available in SINGLE 724 // master mode The controller waits 725 // for a delay to transmit the first 726 // spi word after channel enabled 727 // and corresponding TX register 728 // filled. This Delay is based on 729 // SPI output frequency clock No 730 // clock output provided to the 731 // boundary and chip select is not 732 // active in 4 pin mode within this 733 // period. 0x0 No delay for first 734 // spi transfer. 0x1 The controller 735 // wait 4 spi bus clock 0x2 The 736 // controller wait 8 spi bus clock 737 // 0x3 The controller wait 16 spi 738 // bus clock 0x4 The controller wait 739 // 32 spi bus clock 740 741 #define MCSPI_MODULCTRL_INITDLY_S 4 742 #define MCSPI_MODULCTRL_SYSTEM_TEST \ 743 0x00000008 // Enables the system test mode 0 744 // Functional mode 1 System test 745 // mode (SYSTEST) 746 747 #define MCSPI_MODULCTRL_MS 0x00000004 // Master/ Slave 0 Master - The 748 // module generates the SPICLK and 749 // SPIEN[3:0] 1 Slave - The module 750 // receives the SPICLK and 751 // SPIEN[3:0] 752 #define MCSPI_MODULCTRL_PIN34 0x00000002 // Pin mode selection: This 753 // register is used to configure the 754 // SPI pin mode in master or slave 755 // mode. If asserted the controller 756 // only use SIMOSOMI and SPICLK 757 // clock pin for spi transfers. 0 758 // SPIEN is used as a chip select. 1 759 // SPIEN is not used.In this mode 760 // all related option to chip select 761 // have no meaning. 762 #define MCSPI_MODULCTRL_SINGLE 0x00000001 // Single channel / Multi Channel 763 // (master mode only) 0 More than 764 // one channel will be used in 765 // master mode. 1 Only one channel 766 // will be used in master mode. This 767 // bit must be set in Force SPIEN 768 // mode. 769 //****************************************************************************** 770 // 771 // The following are defines for the bit fields in the MCSPI_O_CH0CONF register. 772 // 773 //****************************************************************************** 774 #define MCSPI_CH0CONF_CLKG 0x20000000 // Clock divider granularity This 775 // register defines the granularity 776 // of channel clock divider: power 777 // of two or one clock cycle 778 // granularity. When this bit is set 779 // the register MCSPI_CHCTRL[EXTCLK] 780 // must be configured to reach a 781 // maximum of 4096 clock divider 782 // ratio. Then The clock divider 783 // ratio is a concatenation of 784 // MCSPI_CHCONF[CLKD] and 785 // MCSPI_CHCTRL[EXTCLK] values 0 786 // Clock granularity of power of two 787 // 1 One clock cycle ganularity 788 #define MCSPI_CH0CONF_FFER 0x10000000 // FIFO enabled for receive:Only 789 // one channel can have this bit 790 // field set. 0 The buffer is not 791 // used to receive data. 1 The 792 // buffer is used to receive data. 793 #define MCSPI_CH0CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only 794 // one channel can have this bit 795 // field set. 0 The buffer is not 796 // used to transmit data. 1 The 797 // buffer is used to transmit data. 798 #define MCSPI_CH0CONF_TCS0_M 0x06000000 // Chip Select Time Control This 799 // 2-bits field defines the number 800 // of interface clock cycles between 801 // CS toggling and first or last 802 // edge of SPI clock. 0x0 0.5 clock 803 // cycle 0x1 1.5 clock cycle 0x2 2.5 804 // clock cycle 0x3 3.5 clock cycle 805 #define MCSPI_CH0CONF_TCS0_S 25 806 #define MCSPI_CH0CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit 807 // polarity is held to 0 during SPI 808 // transfer. 1 Start bit polarity is 809 // held to 1 during SPI transfer. 810 #define MCSPI_CH0CONF_SBE 0x00800000 // Start bit enable for SPI 811 // transfer 0 Default SPI transfer 812 // length as specified by WL bit 813 // field 1 Start bit D/CX added 814 // before SPI transfer polarity is 815 // defined by MCSPI_CH0CONF[SBPOL] 816 #define MCSPI_CH0CONF_SPIENSLV_M \ 817 0x00600000 // Channel 0 only and slave mode 818 // only: SPI slave select signal 819 // detection. Reserved bits for 820 // other cases. 0x0 Detection 821 // enabled only on SPIEN[0] 0x1 822 // Detection enabled only on 823 // SPIEN[1] 0x2 Detection enabled 824 // only on SPIEN[2] 0x3 Detection 825 // enabled only on SPIEN[3] 826 827 #define MCSPI_CH0CONF_SPIENSLV_S 21 828 #define MCSPI_CH0CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep 829 // SPIEN active between SPI words. 830 // (single channel master mode only) 831 // 0 Writing 0 into this bit drives 832 // low the SPIEN line when 833 // MCSPI_CHCONF(i)[EPOL]=0 and 834 // drives it high when 835 // MCSPI_CHCONF(i)[EPOL]=1. 1 836 // Writing 1 into this bit drives 837 // high the SPIEN line when 838 // MCSPI_CHCONF(i)[EPOL]=0 and 839 // drives it low when 840 // MCSPI_CHCONF(i)[EPOL]=1 841 #define MCSPI_CH0CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is 842 // deactivated (recommended for 843 // single SPI word transfer) 1 Turbo 844 // is activated to maximize the 845 // throughput for multi SPI words 846 // transfer. 847 #define MCSPI_CH0CONF_IS 0x00040000 // Input Select 0 Data Line0 848 // (SPIDAT[0]) selected for 849 // reception. 1 Data Line1 850 // (SPIDAT[1]) selected for 851 // reception 852 #define MCSPI_CH0CONF_DPE1 0x00020000 // Transmission Enable for data 853 // line 1 (SPIDATAGZEN[1]) 0 Data 854 // Line1 (SPIDAT[1]) selected for 855 // transmission 1 No transmission on 856 // Data Line1 (SPIDAT[1]) 857 #define MCSPI_CH0CONF_DPE0 0x00010000 // Transmission Enable for data 858 // line 0 (SPIDATAGZEN[0]) 0 Data 859 // Line0 (SPIDAT[0]) selected for 860 // transmission 1 No transmission on 861 // Data Line0 (SPIDAT[0]) 862 #define MCSPI_CH0CONF_DMAR 0x00008000 // DMA Read request The DMA Read 863 // request line is asserted when the 864 // channel is enabled and a new data 865 // is available in the receive 866 // register of the channel. The DMA 867 // Read request line is deasserted 868 // on read completion of the receive 869 // register of the channel. 0 DMA 870 // Read Request disabled 1 DMA Read 871 // Request enabled 872 #define MCSPI_CH0CONF_DMAW 0x00004000 // DMA Write request. The DMA Write 873 // request line is asserted when The 874 // channel is enabled and the 875 // transmitter register of the 876 // channel is empty. The DMA Write 877 // request line is deasserted on 878 // load completion of the 879 // transmitter register of the 880 // channel. 0 DMA Write Request 881 // disabled 1 DMA Write Request 882 // enabled 883 #define MCSPI_CH0CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 884 // Transmit and Receive mode 0x1 885 // Receive only mode 0x2 Transmit 886 // only mode 0x3 Reserved 887 #define MCSPI_CH0CONF_TRM_S 12 888 #define MCSPI_CH0CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved 889 // 0x01 Reserved 0x02 Reserved 0x03 890 // The SPI word is 4-bits long 0x04 891 // The SPI word is 5-bits long 0x05 892 // The SPI word is 6-bits long 0x06 893 // The SPI word is 7-bits long 0x07 894 // The SPI word is 8-bits long 0x08 895 // The SPI word is 9-bits long 0x09 896 // The SPI word is 10-bits long 0x0A 897 // The SPI word is 11-bits long 0x0B 898 // The SPI word is 12-bits long 0x0C 899 // The SPI word is 13-bits long 0x0D 900 // The SPI word is 14-bits long 0x0E 901 // The SPI word is 15-bits long 0x0F 902 // The SPI word is 16-bits long 0x10 903 // The SPI word is 17-bits long 0x11 904 // The SPI word is 18-bits long 0x12 905 // The SPI word is 19-bits long 0x13 906 // The SPI word is 20-bits long 0x14 907 // The SPI word is 21-bits long 0x15 908 // The SPI word is 22-bits long 0x16 909 // The SPI word is 23-bits long 0x17 910 // The SPI word is 24-bits long 0x18 911 // The SPI word is 25-bits long 0x19 912 // The SPI word is 26-bits long 0x1A 913 // The SPI word is 27-bits long 0x1B 914 // The SPI word is 28-bits long 0x1C 915 // The SPI word is 29-bits long 0x1D 916 // The SPI word is 30-bits long 0x1E 917 // The SPI word is 31-bits long 0x1F 918 // The SPI word is 32-bits long 919 #define MCSPI_CH0CONF_WL_S 7 920 #define MCSPI_CH0CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held 921 // high during the active state. 1 922 // SPIEN is held low during the 923 // active state. 924 #define MCSPI_CH0CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. 925 // (only when the module is a Master 926 // SPI device). A programmable clock 927 // divider divides the SPI reference 928 // clock (CLKSPIREF) with a 4-bit 929 // value and results in a new clock 930 // SPICLK available to shift-in and 931 // shift-out data. By default the 932 // clock divider ratio has a power 933 // of two granularity when 934 // MCSPI_CHCONF[CLKG] is cleared 935 // Otherwise this register is the 4 936 // LSB bit of a 12-bit register 937 // concatenated with clock divider 938 // extension MCSPI_CHCTRL[EXTCLK] 939 // register.The value description 940 // below defines the clock ratio 941 // when MCSPI_CHCONF[CLKG] is set to 942 // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 943 // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 944 // 512 0xA 1024 0xB 2048 0xC 4096 945 // 0xD 8192 0xE 16384 0xF 32768 946 #define MCSPI_CH0CONF_CLKD_S 2 947 #define MCSPI_CH0CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held 948 // high during the active state 1 949 // SPICLK is held low during the 950 // active state 951 #define MCSPI_CH0CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched 952 // on odd numbered edges of SPICLK. 953 // 1 Data are latched on even 954 // numbered edges of SPICLK. 955 //****************************************************************************** 956 // 957 // The following are defines for the bit fields in the MCSPI_O_CH0STAT register. 958 // 959 //****************************************************************************** 960 #define MCSPI_CH0STAT_RXFFF 0x00000040 961 #define MCSPI_CH0STAT_RXFFE 0x00000020 962 #define MCSPI_CH0STAT_TXFFF 0x00000010 963 #define MCSPI_CH0STAT_TXFFE 0x00000008 964 #define MCSPI_CH0STAT_EOT 0x00000004 965 #define MCSPI_CH0STAT_TXS 0x00000002 966 #define MCSPI_CH0STAT_RXS 0x00000001 967 //****************************************************************************** 968 // 969 // The following are defines for the bit fields in the MCSPI_O_CH0CTRL register. 970 // 971 //****************************************************************************** 972 #define MCSPI_CH0CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This 973 // register is used to concatenate 974 // with MCSPI_CHCONF[CLKD] register 975 // for clock ratio only when 976 // granularity is one clock cycle 977 // (MCSPI_CHCONF[CLKG] set to 1). 978 // Then the max value reached is 979 // 4096 clock divider ratio. 0x00 980 // Clock ratio is CLKD + 1 0x01 981 // Clock ratio is CLKD + 1 + 16 0xFF 982 // Clock ratio is CLKD + 1 + 4080 983 #define MCSPI_CH0CTRL_EXTCLK_S 8 984 #define MCSPI_CH0CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" 985 // is not active" 1 "Channel ""i"" 986 // is active" 987 //****************************************************************************** 988 // 989 // The following are defines for the bit fields in the MCSPI_O_TX0 register. 990 // 991 //****************************************************************************** 992 #define MCSPI_TX0_TDATA_M 0xFFFFFFFF // Channel 0 Data to transmit 993 #define MCSPI_TX0_TDATA_S 0 994 //****************************************************************************** 995 // 996 // The following are defines for the bit fields in the MCSPI_O_RX0 register. 997 // 998 //****************************************************************************** 999 #define MCSPI_RX0_RDATA_M 0xFFFFFFFF // Channel 0 Received Data 1000 #define MCSPI_RX0_RDATA_S 0 1001 //****************************************************************************** 1002 // 1003 // The following are defines for the bit fields in the MCSPI_O_CH1CONF register. 1004 // 1005 //****************************************************************************** 1006 #define MCSPI_CH1CONF_CLKG 0x20000000 // Clock divider granularity This 1007 // register defines the granularity 1008 // of channel clock divider: power 1009 // of two or one clock cycle 1010 // granularity. When this bit is set 1011 // the register MCSPI_CHCTRL[EXTCLK] 1012 // must be configured to reach a 1013 // maximum of 4096 clock divider 1014 // ratio. Then The clock divider 1015 // ratio is a concatenation of 1016 // MCSPI_CHCONF[CLKD] and 1017 // MCSPI_CHCTRL[EXTCLK] values 0 1018 // Clock granularity of power of two 1019 // 1 One clock cycle ganularity 1020 #define MCSPI_CH1CONF_FFER 0x10000000 // FIFO enabled for receive:Only 1021 // one channel can have this bit 1022 // field set. 0 The buffer is not 1023 // used to receive data. 1 The 1024 // buffer is used to receive data. 1025 #define MCSPI_CH1CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only 1026 // one channel can have this bit 1027 // field set. 0 The buffer is not 1028 // used to transmit data. 1 The 1029 // buffer is used to transmit data. 1030 #define MCSPI_CH1CONF_TCS1_M 0x06000000 // Chip Select Time Control This 1031 // 2-bits field defines the number 1032 // of interface clock cycles between 1033 // CS toggling and first or last 1034 // edge of SPI clock. 0x0 0.5 clock 1035 // cycle 0x1 1.5 clock cycle 0x2 2.5 1036 // clock cycle 0x3 3.5 clock cycle 1037 #define MCSPI_CH1CONF_TCS1_S 25 1038 #define MCSPI_CH1CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit 1039 // polarity is held to 0 during SPI 1040 // transfer. 1 Start bit polarity is 1041 // held to 1 during SPI transfer. 1042 #define MCSPI_CH1CONF_SBE 0x00800000 // Start bit enable for SPI 1043 // transfer 0 Default SPI transfer 1044 // length as specified by WL bit 1045 // field 1 Start bit D/CX added 1046 // before SPI transfer polarity is 1047 // defined by MCSPI_CH1CONF[SBPOL] 1048 #define MCSPI_CH1CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep 1049 // SPIEN active between SPI words. 1050 // (single channel master mode only) 1051 // 0 Writing 0 into this bit drives 1052 // low the SPIEN line when 1053 // MCSPI_CHCONF(i)[EPOL]=0 and 1054 // drives it high when 1055 // MCSPI_CHCONF(i)[EPOL]=1. 1 1056 // Writing 1 into this bit drives 1057 // high the SPIEN line when 1058 // MCSPI_CHCONF(i)[EPOL]=0 and 1059 // drives it low when 1060 // MCSPI_CHCONF(i)[EPOL]=1 1061 #define MCSPI_CH1CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is 1062 // deactivated (recommended for 1063 // single SPI word transfer) 1 Turbo 1064 // is activated to maximize the 1065 // throughput for multi SPI words 1066 // transfer. 1067 #define MCSPI_CH1CONF_IS 0x00040000 // Input Select 0 Data Line0 1068 // (SPIDAT[0]) selected for 1069 // reception. 1 Data Line1 1070 // (SPIDAT[1]) selected for 1071 // reception 1072 #define MCSPI_CH1CONF_DPE1 0x00020000 // Transmission Enable for data 1073 // line 1 (SPIDATAGZEN[1]) 0 Data 1074 // Line1 (SPIDAT[1]) selected for 1075 // transmission 1 No transmission on 1076 // Data Line1 (SPIDAT[1]) 1077 #define MCSPI_CH1CONF_DPE0 0x00010000 // Transmission Enable for data 1078 // line 0 (SPIDATAGZEN[0]) 0 Data 1079 // Line0 (SPIDAT[0]) selected for 1080 // transmission 1 No transmission on 1081 // Data Line0 (SPIDAT[0]) 1082 #define MCSPI_CH1CONF_DMAR 0x00008000 // DMA Read request The DMA Read 1083 // request line is asserted when the 1084 // channel is enabled and a new data 1085 // is available in the receive 1086 // register of the channel. The DMA 1087 // Read request line is deasserted 1088 // on read completion of the receive 1089 // register of the channel. 0 DMA 1090 // Read Request disabled 1 DMA Read 1091 // Request enabled 1092 #define MCSPI_CH1CONF_DMAW 0x00004000 // DMA Write request. The DMA Write 1093 // request line is asserted when The 1094 // channel is enabled and the 1095 // transmitter register of the 1096 // channel is empty. The DMA Write 1097 // request line is deasserted on 1098 // load completion of the 1099 // transmitter register of the 1100 // channel. 0 DMA Write Request 1101 // disabled 1 DMA Write Request 1102 // enabled 1103 #define MCSPI_CH1CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 1104 // Transmit and Receive mode 0x1 1105 // Receive only mode 0x2 Transmit 1106 // only mode 0x3 Reserved 1107 #define MCSPI_CH1CONF_TRM_S 12 1108 #define MCSPI_CH1CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved 1109 // 0x01 Reserved 0x02 Reserved 0x03 1110 // The SPI word is 4-bits long 0x04 1111 // The SPI word is 5-bits long 0x05 1112 // The SPI word is 6-bits long 0x06 1113 // The SPI word is 7-bits long 0x07 1114 // The SPI word is 8-bits long 0x08 1115 // The SPI word is 9-bits long 0x09 1116 // The SPI word is 10-bits long 0x0A 1117 // The SPI word is 11-bits long 0x0B 1118 // The SPI word is 12-bits long 0x0C 1119 // The SPI word is 13-bits long 0x0D 1120 // The SPI word is 14-bits long 0x0E 1121 // The SPI word is 15-bits long 0x0F 1122 // The SPI word is 16-bits long 0x10 1123 // The SPI word is 17-bits long 0x11 1124 // The SPI word is 18-bits long 0x12 1125 // The SPI word is 19-bits long 0x13 1126 // The SPI word is 20-bits long 0x14 1127 // The SPI word is 21-bits long 0x15 1128 // The SPI word is 22-bits long 0x16 1129 // The SPI word is 23-bits long 0x17 1130 // The SPI word is 24-bits long 0x18 1131 // The SPI word is 25-bits long 0x19 1132 // The SPI word is 26-bits long 0x1A 1133 // The SPI word is 27-bits long 0x1B 1134 // The SPI word is 28-bits long 0x1C 1135 // The SPI word is 29-bits long 0x1D 1136 // The SPI word is 30-bits long 0x1E 1137 // The SPI word is 31-bits long 0x1F 1138 // The SPI word is 32-bits long 1139 #define MCSPI_CH1CONF_WL_S 7 1140 #define MCSPI_CH1CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held 1141 // high during the active state. 1 1142 // SPIEN is held low during the 1143 // active state. 1144 #define MCSPI_CH1CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. 1145 // (only when the module is a Master 1146 // SPI device). A programmable clock 1147 // divider divides the SPI reference 1148 // clock (CLKSPIREF) with a 4-bit 1149 // value and results in a new clock 1150 // SPICLK available to shift-in and 1151 // shift-out data. By default the 1152 // clock divider ratio has a power 1153 // of two granularity when 1154 // MCSPI_CHCONF[CLKG] is cleared 1155 // Otherwise this register is the 4 1156 // LSB bit of a 12-bit register 1157 // concatenated with clock divider 1158 // extension MCSPI_CHCTRL[EXTCLK] 1159 // register.The value description 1160 // below defines the clock ratio 1161 // when MCSPI_CHCONF[CLKG] is set to 1162 // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 1163 // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 1164 // 512 0xA 1024 0xB 2048 0xC 4096 1165 // 0xD 8192 0xE 16384 0xF 32768 1166 #define MCSPI_CH1CONF_CLKD_S 2 1167 #define MCSPI_CH1CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held 1168 // high during the active state 1 1169 // SPICLK is held low during the 1170 // active state 1171 #define MCSPI_CH1CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched 1172 // on odd numbered edges of SPICLK. 1173 // 1 Data are latched on even 1174 // numbered edges of SPICLK. 1175 //****************************************************************************** 1176 // 1177 // The following are defines for the bit fields in the MCSPI_O_CH1STAT register. 1178 // 1179 //****************************************************************************** 1180 #define MCSPI_CH1STAT_RXFFF 0x00000040 1181 #define MCSPI_CH1STAT_RXFFE 0x00000020 1182 #define MCSPI_CH1STAT_TXFFF 0x00000010 1183 #define MCSPI_CH1STAT_TXFFE 0x00000008 1184 #define MCSPI_CH1STAT_EOT 0x00000004 1185 #define MCSPI_CH1STAT_TXS 0x00000002 1186 #define MCSPI_CH1STAT_RXS 0x00000001 1187 //****************************************************************************** 1188 // 1189 // The following are defines for the bit fields in the MCSPI_O_CH1CTRL register. 1190 // 1191 //****************************************************************************** 1192 #define MCSPI_CH1CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This 1193 // register is used to concatenate 1194 // with MCSPI_CHCONF[CLKD] register 1195 // for clock ratio only when 1196 // granularity is one clock cycle 1197 // (MCSPI_CHCONF[CLKG] set to 1). 1198 // Then the max value reached is 1199 // 4096 clock divider ratio. 0x00 1200 // Clock ratio is CLKD + 1 0x01 1201 // Clock ratio is CLKD + 1 + 16 0xFF 1202 // Clock ratio is CLKD + 1 + 4080 1203 #define MCSPI_CH1CTRL_EXTCLK_S 8 1204 #define MCSPI_CH1CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" 1205 // is not active" 1 "Channel ""i"" 1206 // is active" 1207 //****************************************************************************** 1208 // 1209 // The following are defines for the bit fields in the MCSPI_O_TX1 register. 1210 // 1211 //****************************************************************************** 1212 #define MCSPI_TX1_TDATA_M 0xFFFFFFFF // Channel 1 Data to transmit 1213 #define MCSPI_TX1_TDATA_S 0 1214 //****************************************************************************** 1215 // 1216 // The following are defines for the bit fields in the MCSPI_O_RX1 register. 1217 // 1218 //****************************************************************************** 1219 #define MCSPI_RX1_RDATA_M 0xFFFFFFFF // Channel 1 Received Data 1220 #define MCSPI_RX1_RDATA_S 0 1221 //****************************************************************************** 1222 // 1223 // The following are defines for the bit fields in the MCSPI_O_CH2CONF register. 1224 // 1225 //****************************************************************************** 1226 #define MCSPI_CH2CONF_CLKG 0x20000000 // Clock divider granularity This 1227 // register defines the granularity 1228 // of channel clock divider: power 1229 // of two or one clock cycle 1230 // granularity. When this bit is set 1231 // the register MCSPI_CHCTRL[EXTCLK] 1232 // must be configured to reach a 1233 // maximum of 4096 clock divider 1234 // ratio. Then The clock divider 1235 // ratio is a concatenation of 1236 // MCSPI_CHCONF[CLKD] and 1237 // MCSPI_CHCTRL[EXTCLK] values 0 1238 // Clock granularity of power of two 1239 // 1 One clock cycle ganularity 1240 #define MCSPI_CH2CONF_FFER 0x10000000 // FIFO enabled for receive:Only 1241 // one channel can have this bit 1242 // field set. 0 The buffer is not 1243 // used to receive data. 1 The 1244 // buffer is used to receive data. 1245 #define MCSPI_CH2CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only 1246 // one channel can have this bit 1247 // field set. 0 The buffer is not 1248 // used to transmit data. 1 The 1249 // buffer is used to transmit data. 1250 #define MCSPI_CH2CONF_TCS2_M 0x06000000 // Chip Select Time Control This 1251 // 2-bits field defines the number 1252 // of interface clock cycles between 1253 // CS toggling and first or last 1254 // edge of SPI clock. 0x0 0.5 clock 1255 // cycle 0x1 1.5 clock cycle 0x2 2.5 1256 // clock cycle 0x3 3.5 clock cycle 1257 #define MCSPI_CH2CONF_TCS2_S 25 1258 #define MCSPI_CH2CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit 1259 // polarity is held to 0 during SPI 1260 // transfer. 1 Start bit polarity is 1261 // held to 1 during SPI transfer. 1262 #define MCSPI_CH2CONF_SBE 0x00800000 // Start bit enable for SPI 1263 // transfer 0 Default SPI transfer 1264 // length as specified by WL bit 1265 // field 1 Start bit D/CX added 1266 // before SPI transfer polarity is 1267 // defined by MCSPI_CH2CONF[SBPOL] 1268 #define MCSPI_CH2CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep 1269 // SPIEN active between SPI words. 1270 // (single channel master mode only) 1271 // 0 Writing 0 into this bit drives 1272 // low the SPIEN line when 1273 // MCSPI_CHCONF(i)[EPOL]=0 and 1274 // drives it high when 1275 // MCSPI_CHCONF(i)[EPOL]=1. 1 1276 // Writing 1 into this bit drives 1277 // high the SPIEN line when 1278 // MCSPI_CHCONF(i)[EPOL]=0 and 1279 // drives it low when 1280 // MCSPI_CHCONF(i)[EPOL]=1 1281 #define MCSPI_CH2CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is 1282 // deactivated (recommended for 1283 // single SPI word transfer) 1 Turbo 1284 // is activated to maximize the 1285 // throughput for multi SPI words 1286 // transfer. 1287 #define MCSPI_CH2CONF_IS 0x00040000 // Input Select 0 Data Line0 1288 // (SPIDAT[0]) selected for 1289 // reception. 1 Data Line1 1290 // (SPIDAT[1]) selected for 1291 // reception 1292 #define MCSPI_CH2CONF_DPE1 0x00020000 // Transmission Enable for data 1293 // line 1 (SPIDATAGZEN[1]) 0 Data 1294 // Line1 (SPIDAT[1]) selected for 1295 // transmission 1 No transmission on 1296 // Data Line1 (SPIDAT[1]) 1297 #define MCSPI_CH2CONF_DPE0 0x00010000 // Transmission Enable for data 1298 // line 0 (SPIDATAGZEN[0]) 0 Data 1299 // Line0 (SPIDAT[0]) selected for 1300 // transmission 1 No transmission on 1301 // Data Line0 (SPIDAT[0]) 1302 #define MCSPI_CH2CONF_DMAR 0x00008000 // DMA Read request The DMA Read 1303 // request line is asserted when the 1304 // channel is enabled and a new data 1305 // is available in the receive 1306 // register of the channel. The DMA 1307 // Read request line is deasserted 1308 // on read completion of the receive 1309 // register of the channel. 0 DMA 1310 // Read Request disabled 1 DMA Read 1311 // Request enabled 1312 #define MCSPI_CH2CONF_DMAW 0x00004000 // DMA Write request. The DMA Write 1313 // request line is asserted when The 1314 // channel is enabled and the 1315 // transmitter register of the 1316 // channel is empty. The DMA Write 1317 // request line is deasserted on 1318 // load completion of the 1319 // transmitter register of the 1320 // channel. 0 DMA Write Request 1321 // disabled 1 DMA Write Request 1322 // enabled 1323 #define MCSPI_CH2CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 1324 // Transmit and Receive mode 0x1 1325 // Receive only mode 0x2 Transmit 1326 // only mode 0x3 Reserved 1327 #define MCSPI_CH2CONF_TRM_S 12 1328 #define MCSPI_CH2CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved 1329 // 0x01 Reserved 0x02 Reserved 0x03 1330 // The SPI word is 4-bits long 0x04 1331 // The SPI word is 5-bits long 0x05 1332 // The SPI word is 6-bits long 0x06 1333 // The SPI word is 7-bits long 0x07 1334 // The SPI word is 8-bits long 0x08 1335 // The SPI word is 9-bits long 0x09 1336 // The SPI word is 10-bits long 0x0A 1337 // The SPI word is 11-bits long 0x0B 1338 // The SPI word is 12-bits long 0x0C 1339 // The SPI word is 13-bits long 0x0D 1340 // The SPI word is 14-bits long 0x0E 1341 // The SPI word is 15-bits long 0x0F 1342 // The SPI word is 16-bits long 0x10 1343 // The SPI word is 17-bits long 0x11 1344 // The SPI word is 18-bits long 0x12 1345 // The SPI word is 19-bits long 0x13 1346 // The SPI word is 20-bits long 0x14 1347 // The SPI word is 21-bits long 0x15 1348 // The SPI word is 22-bits long 0x16 1349 // The SPI word is 23-bits long 0x17 1350 // The SPI word is 24-bits long 0x18 1351 // The SPI word is 25-bits long 0x19 1352 // The SPI word is 26-bits long 0x1A 1353 // The SPI word is 27-bits long 0x1B 1354 // The SPI word is 28-bits long 0x1C 1355 // The SPI word is 29-bits long 0x1D 1356 // The SPI word is 30-bits long 0x1E 1357 // The SPI word is 31-bits long 0x1F 1358 // The SPI word is 32-bits long 1359 #define MCSPI_CH2CONF_WL_S 7 1360 #define MCSPI_CH2CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held 1361 // high during the active state. 1 1362 // SPIEN is held low during the 1363 // active state. 1364 #define MCSPI_CH2CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. 1365 // (only when the module is a Master 1366 // SPI device). A programmable clock 1367 // divider divides the SPI reference 1368 // clock (CLKSPIREF) with a 4-bit 1369 // value and results in a new clock 1370 // SPICLK available to shift-in and 1371 // shift-out data. By default the 1372 // clock divider ratio has a power 1373 // of two granularity when 1374 // MCSPI_CHCONF[CLKG] is cleared 1375 // Otherwise this register is the 4 1376 // LSB bit of a 12-bit register 1377 // concatenated with clock divider 1378 // extension MCSPI_CHCTRL[EXTCLK] 1379 // register.The value description 1380 // below defines the clock ratio 1381 // when MCSPI_CHCONF[CLKG] is set to 1382 // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 1383 // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 1384 // 512 0xA 1024 0xB 2048 0xC 4096 1385 // 0xD 8192 0xE 16384 0xF 32768 1386 #define MCSPI_CH2CONF_CLKD_S 2 1387 #define MCSPI_CH2CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held 1388 // high during the active state 1 1389 // SPICLK is held low during the 1390 // active state 1391 #define MCSPI_CH2CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched 1392 // on odd numbered edges of SPICLK. 1393 // 1 Data are latched on even 1394 // numbered edges of SPICLK. 1395 //****************************************************************************** 1396 // 1397 // The following are defines for the bit fields in the MCSPI_O_CH2STAT register. 1398 // 1399 //****************************************************************************** 1400 #define MCSPI_CH2STAT_RXFFF 0x00000040 1401 #define MCSPI_CH2STAT_RXFFE 0x00000020 1402 #define MCSPI_CH2STAT_TXFFF 0x00000010 1403 #define MCSPI_CH2STAT_TXFFE 0x00000008 1404 #define MCSPI_CH2STAT_EOT 0x00000004 1405 #define MCSPI_CH2STAT_TXS 0x00000002 1406 #define MCSPI_CH2STAT_RXS 0x00000001 1407 //****************************************************************************** 1408 // 1409 // The following are defines for the bit fields in the MCSPI_O_CH2CTRL register. 1410 // 1411 //****************************************************************************** 1412 #define MCSPI_CH2CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This 1413 // register is used to concatenate 1414 // with MCSPI_CHCONF[CLKD] register 1415 // for clock ratio only when 1416 // granularity is one clock cycle 1417 // (MCSPI_CHCONF[CLKG] set to 1). 1418 // Then the max value reached is 1419 // 4096 clock divider ratio. 0x00 1420 // Clock ratio is CLKD + 1 0x01 1421 // Clock ratio is CLKD + 1 + 16 0xFF 1422 // Clock ratio is CLKD + 1 + 4080 1423 #define MCSPI_CH2CTRL_EXTCLK_S 8 1424 #define MCSPI_CH2CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" 1425 // is not active" 1 "Channel ""i"" 1426 // is active" 1427 //****************************************************************************** 1428 // 1429 // The following are defines for the bit fields in the MCSPI_O_TX2 register. 1430 // 1431 //****************************************************************************** 1432 #define MCSPI_TX2_TDATA_M 0xFFFFFFFF // Channel 2 Data to transmit 1433 #define MCSPI_TX2_TDATA_S 0 1434 //****************************************************************************** 1435 // 1436 // The following are defines for the bit fields in the MCSPI_O_RX2 register. 1437 // 1438 //****************************************************************************** 1439 #define MCSPI_RX2_RDATA_M 0xFFFFFFFF // Channel 2 Received Data 1440 #define MCSPI_RX2_RDATA_S 0 1441 //****************************************************************************** 1442 // 1443 // The following are defines for the bit fields in the MCSPI_O_CH3CONF register. 1444 // 1445 //****************************************************************************** 1446 #define MCSPI_CH3CONF_CLKG 0x20000000 // Clock divider granularity This 1447 // register defines the granularity 1448 // of channel clock divider: power 1449 // of two or one clock cycle 1450 // granularity. When this bit is set 1451 // the register MCSPI_CHCTRL[EXTCLK] 1452 // must be configured to reach a 1453 // maximum of 4096 clock divider 1454 // ratio. Then The clock divider 1455 // ratio is a concatenation of 1456 // MCSPI_CHCONF[CLKD] and 1457 // MCSPI_CHCTRL[EXTCLK] values 0 1458 // Clock granularity of power of two 1459 // 1 One clock cycle ganularity 1460 #define MCSPI_CH3CONF_FFER 0x10000000 // FIFO enabled for receive:Only 1461 // one channel can have this bit 1462 // field set. 0 The buffer is not 1463 // used to receive data. 1 The 1464 // buffer is used to receive data. 1465 #define MCSPI_CH3CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only 1466 // one channel can have this bit 1467 // field set. 0 The buffer is not 1468 // used to transmit data. 1 The 1469 // buffer is used to transmit data. 1470 #define MCSPI_CH3CONF_TCS3_M 0x06000000 // Chip Select Time Control This 1471 // 2-bits field defines the number 1472 // of interface clock cycles between 1473 // CS toggling and first or last 1474 // edge of SPI clock. 0x0 0.5 clock 1475 // cycle 0x1 1.5 clock cycle 0x2 2.5 1476 // clock cycle 0x3 3.5 clock cycle 1477 #define MCSPI_CH3CONF_TCS3_S 25 1478 #define MCSPI_CH3CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit 1479 // polarity is held to 0 during SPI 1480 // transfer. 1 Start bit polarity is 1481 // held to 1 during SPI transfer. 1482 #define MCSPI_CH3CONF_SBE 0x00800000 // Start bit enable for SPI 1483 // transfer 0 Default SPI transfer 1484 // length as specified by WL bit 1485 // field 1 Start bit D/CX added 1486 // before SPI transfer polarity is 1487 // defined by MCSPI_CH3CONF[SBPOL] 1488 #define MCSPI_CH3CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep 1489 // SPIEN active between SPI words. 1490 // (single channel master mode only) 1491 // 0 Writing 0 into this bit drives 1492 // low the SPIEN line when 1493 // MCSPI_CHCONF(i)[EPOL]=0 and 1494 // drives it high when 1495 // MCSPI_CHCONF(i)[EPOL]=1. 1 1496 // Writing 1 into this bit drives 1497 // high the SPIEN line when 1498 // MCSPI_CHCONF(i)[EPOL]=0 and 1499 // drives it low when 1500 // MCSPI_CHCONF(i)[EPOL]=1 1501 #define MCSPI_CH3CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is 1502 // deactivated (recommended for 1503 // single SPI word transfer) 1 Turbo 1504 // is activated to maximize the 1505 // throughput for multi SPI words 1506 // transfer. 1507 #define MCSPI_CH3CONF_IS 0x00040000 // Input Select 0 Data Line0 1508 // (SPIDAT[0]) selected for 1509 // reception. 1 Data Line1 1510 // (SPIDAT[1]) selected for 1511 // reception 1512 #define MCSPI_CH3CONF_DPE1 0x00020000 // Transmission Enable for data 1513 // line 1 (SPIDATAGZEN[1]) 0 Data 1514 // Line1 (SPIDAT[1]) selected for 1515 // transmission 1 No transmission on 1516 // Data Line1 (SPIDAT[1]) 1517 #define MCSPI_CH3CONF_DPE0 0x00010000 // Transmission Enable for data 1518 // line 0 (SPIDATAGZEN[0]) 0 Data 1519 // Line0 (SPIDAT[0]) selected for 1520 // transmission 1 No transmission on 1521 // Data Line0 (SPIDAT[0]) 1522 #define MCSPI_CH3CONF_DMAR 0x00008000 // DMA Read request The DMA Read 1523 // request line is asserted when the 1524 // channel is enabled and a new data 1525 // is available in the receive 1526 // register of the channel. The DMA 1527 // Read request line is deasserted 1528 // on read completion of the receive 1529 // register of the channel. 0 DMA 1530 // Read Request disabled 1 DMA Read 1531 // Request enabled 1532 #define MCSPI_CH3CONF_DMAW 0x00004000 // DMA Write request. The DMA Write 1533 // request line is asserted when The 1534 // channel is enabled and the 1535 // transmitter register of the 1536 // channel is empty. The DMA Write 1537 // request line is deasserted on 1538 // load completion of the 1539 // transmitter register of the 1540 // channel. 0 DMA Write Request 1541 // disabled 1 DMA Write Request 1542 // enabled 1543 #define MCSPI_CH3CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 1544 // Transmit and Receive mode 0x1 1545 // Receive only mode 0x2 Transmit 1546 // only mode 0x3 Reserved 1547 #define MCSPI_CH3CONF_TRM_S 12 1548 #define MCSPI_CH3CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved 1549 // 0x01 Reserved 0x02 Reserved 0x03 1550 // The SPI word is 4-bits long 0x04 1551 // The SPI word is 5-bits long 0x05 1552 // The SPI word is 6-bits long 0x06 1553 // The SPI word is 7-bits long 0x07 1554 // The SPI word is 8-bits long 0x08 1555 // The SPI word is 9-bits long 0x09 1556 // The SPI word is 10-bits long 0x0A 1557 // The SPI word is 11-bits long 0x0B 1558 // The SPI word is 12-bits long 0x0C 1559 // The SPI word is 13-bits long 0x0D 1560 // The SPI word is 14-bits long 0x0E 1561 // The SPI word is 15-bits long 0x0F 1562 // The SPI word is 16-bits long 0x10 1563 // The SPI word is 17-bits long 0x11 1564 // The SPI word is 18-bits long 0x12 1565 // The SPI word is 19-bits long 0x13 1566 // The SPI word is 20-bits long 0x14 1567 // The SPI word is 21-bits long 0x15 1568 // The SPI word is 22-bits long 0x16 1569 // The SPI word is 23-bits long 0x17 1570 // The SPI word is 24-bits long 0x18 1571 // The SPI word is 25-bits long 0x19 1572 // The SPI word is 26-bits long 0x1A 1573 // The SPI word is 27-bits long 0x1B 1574 // The SPI word is 28-bits long 0x1C 1575 // The SPI word is 29-bits long 0x1D 1576 // The SPI word is 30-bits long 0x1E 1577 // The SPI word is 31-bits long 0x1F 1578 // The SPI word is 32-bits long 1579 #define MCSPI_CH3CONF_WL_S 7 1580 #define MCSPI_CH3CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held 1581 // high during the active state. 1 1582 // SPIEN is held low during the 1583 // active state. 1584 #define MCSPI_CH3CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. 1585 // (only when the module is a Master 1586 // SPI device). A programmable clock 1587 // divider divides the SPI reference 1588 // clock (CLKSPIREF) with a 4-bit 1589 // value and results in a new clock 1590 // SPICLK available to shift-in and 1591 // shift-out data. By default the 1592 // clock divider ratio has a power 1593 // of two granularity when 1594 // MCSPI_CHCONF[CLKG] is cleared 1595 // Otherwise this register is the 4 1596 // LSB bit of a 12-bit register 1597 // concatenated with clock divider 1598 // extension MCSPI_CHCTRL[EXTCLK] 1599 // register.The value description 1600 // below defines the clock ratio 1601 // when MCSPI_CHCONF[CLKG] is set to 1602 // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 1603 // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 1604 // 512 0xA 1024 0xB 2048 0xC 4096 1605 // 0xD 8192 0xE 16384 0xF 32768 1606 #define MCSPI_CH3CONF_CLKD_S 2 1607 #define MCSPI_CH3CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held 1608 // high during the active state 1 1609 // SPICLK is held low during the 1610 // active state 1611 #define MCSPI_CH3CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched 1612 // on odd numbered edges of SPICLK. 1613 // 1 Data are latched on even 1614 // numbered edges of SPICLK. 1615 //****************************************************************************** 1616 // 1617 // The following are defines for the bit fields in the MCSPI_O_CH3STAT register. 1618 // 1619 //****************************************************************************** 1620 #define MCSPI_CH3STAT_RXFFF 0x00000040 1621 #define MCSPI_CH3STAT_RXFFE 0x00000020 1622 #define MCSPI_CH3STAT_TXFFF 0x00000010 1623 #define MCSPI_CH3STAT_TXFFE 0x00000008 1624 #define MCSPI_CH3STAT_EOT 0x00000004 1625 #define MCSPI_CH3STAT_TXS 0x00000002 1626 #define MCSPI_CH3STAT_RXS 0x00000001 1627 //****************************************************************************** 1628 // 1629 // The following are defines for the bit fields in the MCSPI_O_CH3CTRL register. 1630 // 1631 //****************************************************************************** 1632 #define MCSPI_CH3CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This 1633 // register is used to concatenate 1634 // with MCSPI_CHCONF[CLKD] register 1635 // for clock ratio only when 1636 // granularity is one clock cycle 1637 // (MCSPI_CHCONF[CLKG] set to 1). 1638 // Then the max value reached is 1639 // 4096 clock divider ratio. 0x00 1640 // Clock ratio is CLKD + 1 0x01 1641 // Clock ratio is CLKD + 1 + 16 0xFF 1642 // Clock ratio is CLKD + 1 + 4080 1643 #define MCSPI_CH3CTRL_EXTCLK_S 8 1644 #define MCSPI_CH3CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" 1645 // is not active" 1 "Channel ""i"" 1646 // is active" 1647 //****************************************************************************** 1648 // 1649 // The following are defines for the bit fields in the MCSPI_O_TX3 register. 1650 // 1651 //****************************************************************************** 1652 #define MCSPI_TX3_TDATA_M 0xFFFFFFFF // Channel 3 Data to transmit 1653 #define MCSPI_TX3_TDATA_S 0 1654 //****************************************************************************** 1655 // 1656 // The following are defines for the bit fields in the MCSPI_O_RX3 register. 1657 // 1658 //****************************************************************************** 1659 #define MCSPI_RX3_RDATA_M 0xFFFFFFFF // Channel 3 Received Data 1660 #define MCSPI_RX3_RDATA_S 0 1661 //****************************************************************************** 1662 // 1663 // The following are defines for the bit fields in the MCSPI_O_XFERLEVEL register. 1664 // 1665 //****************************************************************************** 1666 #define MCSPI_XFERLEVEL_WCNT_M 0xFFFF0000 // Spi word counterThis register 1667 // holds the programmable value of 1668 // number of SPI word to be 1669 // transferred on channel which is 1670 // using the FIFO buffer.When 1671 // transfer had started a read back 1672 // in this register returns the 1673 // current SPI word transfer index. 1674 // 0x0000 Counter not used 0x0001 1675 // one word 0xFFFE 65534 spi word 1676 // 0xFFFF 65535 spi word 1677 #define MCSPI_XFERLEVEL_WCNT_S 16 1678 #define MCSPI_XFERLEVEL_AFL_M 0x0000FF00 // Buffer Almost Full This register 1679 // holds the programmable almost 1680 // full level value used to 1681 // determine almost full buffer 1682 // condition. If the user wants an 1683 // interrupt or a DMA read request 1684 // to be issued during a receive 1685 // operation when the data buffer 1686 // holds at least n bytes then the 1687 // buffer MCSPI_MODULCTRL[AFL] must 1688 // be set with n-1.The size of this 1689 // register is defined by the 1690 // generic parameter FFNBYTE. 0x00 1691 // one byte 0x01 2 bytes 0xFE 1692 // 255bytes 0xFF 256bytes 1693 #define MCSPI_XFERLEVEL_AFL_S 8 1694 #define MCSPI_XFERLEVEL_AEL_M 0x000000FF // Buffer Almost EmptyThis register 1695 // holds the programmable almost 1696 // empty level value used to 1697 // determine almost empty buffer 1698 // condition. If the user wants an 1699 // interrupt or a DMA write request 1700 // to be issued during a transmit 1701 // operation when the data buffer is 1702 // able to receive n bytes then the 1703 // buffer MCSPI_MODULCTRL[AEL] must 1704 // be set with n-1. 0x00 one byte 1705 // 0x01 2 bytes 0xFE 255 bytes 0xFF 1706 // 256bytes 1707 #define MCSPI_XFERLEVEL_AEL_S 0 1708 //****************************************************************************** 1709 // 1710 // The following are defines for the bit fields in the MCSPI_O_DAFTX register. 1711 // 1712 //****************************************************************************** 1713 #define MCSPI_DAFTX_DAFTDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA 1714 // 256 bit aligned address. "This 1715 // Register is only is used when 1716 // MCSPI_MODULCTRL[FDAA] is set to 1717 // ""1"" and only one of the 1718 // MCSPI_CH(i)CONF[FFEW] of enabled 1719 // channels is set. If these 1720 // conditions are not respected any 1721 // access to this register return a 1722 // null value." 1723 #define MCSPI_DAFTX_DAFTDATA_S 0 1724 //****************************************************************************** 1725 // 1726 // The following are defines for the bit fields in the MCSPI_O_DAFRX register. 1727 // 1728 //****************************************************************************** 1729 #define MCSPI_DAFRX_DAFRDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA 1730 // 256 bit aligned address. "This 1731 // Register is only is used when 1732 // MCSPI_MODULCTRL[FDAA] is set to 1733 // ""1"" and only one of the 1734 // MCSPI_CH(i)CONF[FFEW] of enabled 1735 // channels is set. If these 1736 // conditions are not respected any 1737 // access to this register return a 1738 // null value." 1739 #define MCSPI_DAFRX_DAFRDATA_S 0 1740 1741 1742 1743 #endif // __HW_MCSPI_H__ 1744
