1 /****************************************************************************** 2 * Filename: hw_i2c_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_I2C_H__ 38 #define __HW_I2C_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // I2C component 44 // 45 //***************************************************************************** 46 // Slave Own Address 47 #define I2C_O_SOAR 0x00000000 48 49 // Slave Status 50 #define I2C_O_SSTAT 0x00000004 51 52 // Slave Control 53 #define I2C_O_SCTL 0x00000004 54 55 // Slave Data 56 #define I2C_O_SDR 0x00000008 57 58 // Slave Interrupt Mask 59 #define I2C_O_SIMR 0x0000000C 60 61 // Slave Raw Interrupt Status 62 #define I2C_O_SRIS 0x00000010 63 64 // Slave Masked Interrupt Status 65 #define I2C_O_SMIS 0x00000014 66 67 // Slave Interrupt Clear 68 #define I2C_O_SICR 0x00000018 69 70 // Master Salve Address 71 #define I2C_O_MSA 0x00000800 72 73 // Master Status 74 #define I2C_O_MSTAT 0x00000804 75 76 // Master Control 77 #define I2C_O_MCTRL 0x00000804 78 79 // Master Data 80 #define I2C_O_MDR 0x00000808 81 82 // I2C Master Timer Period 83 #define I2C_O_MTPR 0x0000080C 84 85 // Master Interrupt Mask 86 #define I2C_O_MIMR 0x00000810 87 88 // Master Raw Interrupt Status 89 #define I2C_O_MRIS 0x00000814 90 91 // Master Masked Interrupt Status 92 #define I2C_O_MMIS 0x00000818 93 94 // Master Interrupt Clear 95 #define I2C_O_MICR 0x0000081C 96 97 // Master Configuration 98 #define I2C_O_MCR 0x00000820 99 100 //***************************************************************************** 101 // 102 // Register: I2C_O_SOAR 103 // 104 //***************************************************************************** 105 // Field: [6:0] OAR 106 // 107 // I2C slave own address 108 // This field specifies bits a6 through a0 of the slave address. 109 #define I2C_SOAR_OAR_W 7 110 #define I2C_SOAR_OAR_M 0x0000007F 111 #define I2C_SOAR_OAR_S 0 112 113 //***************************************************************************** 114 // 115 // Register: I2C_O_SSTAT 116 // 117 //***************************************************************************** 118 // Field: [2] FBR 119 // 120 // First byte received 121 // 122 // 0: The first byte has not been received. 123 // 1: The first byte following the slave's own address has been received. 124 // 125 // This bit is only valid when the RREQ bit is set and is automatically cleared 126 // when data has been read from the SDR register. 127 // Note: This bit is not used for slave transmit operations. 128 #define I2C_SSTAT_FBR 0x00000004 129 #define I2C_SSTAT_FBR_BITN 2 130 #define I2C_SSTAT_FBR_M 0x00000004 131 #define I2C_SSTAT_FBR_S 2 132 133 // Field: [1] TREQ 134 // 135 // Transmit request 136 // 137 // 0: No outstanding transmit request. 138 // 1: The I2C controller has been addressed as a slave transmitter and is using 139 // clock stretching to delay the master until data has been written to the SDR 140 // register. 141 #define I2C_SSTAT_TREQ 0x00000002 142 #define I2C_SSTAT_TREQ_BITN 1 143 #define I2C_SSTAT_TREQ_M 0x00000002 144 #define I2C_SSTAT_TREQ_S 1 145 146 // Field: [0] RREQ 147 // 148 // Receive request 149 // 150 // 0: No outstanding receive data 151 // 1: The I2C controller has outstanding receive data from the I2C master and 152 // is using clock stretching to delay the master until data has been read from 153 // the SDR register. 154 #define I2C_SSTAT_RREQ 0x00000001 155 #define I2C_SSTAT_RREQ_BITN 0 156 #define I2C_SSTAT_RREQ_M 0x00000001 157 #define I2C_SSTAT_RREQ_S 0 158 159 //***************************************************************************** 160 // 161 // Register: I2C_O_SCTL 162 // 163 //***************************************************************************** 164 // Field: [0] DA 165 // 166 // Device active 167 // 168 // 0: Disables the I2C slave operation 169 // 1: Enables the I2C slave operation 170 #define I2C_SCTL_DA 0x00000001 171 #define I2C_SCTL_DA_BITN 0 172 #define I2C_SCTL_DA_M 0x00000001 173 #define I2C_SCTL_DA_S 0 174 175 //***************************************************************************** 176 // 177 // Register: I2C_O_SDR 178 // 179 //***************************************************************************** 180 // Field: [7:0] DATA 181 // 182 // Data for transfer 183 // This field contains the data for transfer during a slave receive or transmit 184 // operation. When written the register data is used as transmit data. When 185 // read, this register returns the last data received. 186 // Data is stored until next update, either by a system write for transmit or 187 // by an external master for receive. 188 #define I2C_SDR_DATA_W 8 189 #define I2C_SDR_DATA_M 0x000000FF 190 #define I2C_SDR_DATA_S 0 191 192 //***************************************************************************** 193 // 194 // Register: I2C_O_SIMR 195 // 196 //***************************************************************************** 197 // Field: [2] STOPIM 198 // 199 // Stop condition interrupt mask 200 // 201 // 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt 202 // controller. 203 // 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt 204 // controller. 205 // ENUMs: 206 // EN Enable Interrupt 207 // DIS Disable Interrupt 208 #define I2C_SIMR_STOPIM 0x00000004 209 #define I2C_SIMR_STOPIM_BITN 2 210 #define I2C_SIMR_STOPIM_M 0x00000004 211 #define I2C_SIMR_STOPIM_S 2 212 #define I2C_SIMR_STOPIM_EN 0x00000004 213 #define I2C_SIMR_STOPIM_DIS 0x00000000 214 215 // Field: [1] STARTIM 216 // 217 // Start condition interrupt mask 218 // 219 // 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt 220 // controller. 221 // 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt 222 // controller. 223 // ENUMs: 224 // EN Enable Interrupt 225 // DIS Disable Interrupt 226 #define I2C_SIMR_STARTIM 0x00000002 227 #define I2C_SIMR_STARTIM_BITN 1 228 #define I2C_SIMR_STARTIM_M 0x00000002 229 #define I2C_SIMR_STARTIM_S 1 230 #define I2C_SIMR_STARTIM_EN 0x00000002 231 #define I2C_SIMR_STARTIM_DIS 0x00000000 232 233 // Field: [0] DATAIM 234 // 235 // Data interrupt mask 236 // 237 // 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt 238 // controller. 239 // 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt 240 // controller. 241 #define I2C_SIMR_DATAIM 0x00000001 242 #define I2C_SIMR_DATAIM_BITN 0 243 #define I2C_SIMR_DATAIM_M 0x00000001 244 #define I2C_SIMR_DATAIM_S 0 245 246 //***************************************************************************** 247 // 248 // Register: I2C_O_SRIS 249 // 250 //***************************************************************************** 251 // Field: [2] STOPRIS 252 // 253 // Stop condition raw interrupt status 254 // 255 // 0: No interrupt 256 // 1: A Stop condition interrupt is pending. 257 // 258 // This bit is cleared by writing a 1 to SICR.STOPIC. 259 #define I2C_SRIS_STOPRIS 0x00000004 260 #define I2C_SRIS_STOPRIS_BITN 2 261 #define I2C_SRIS_STOPRIS_M 0x00000004 262 #define I2C_SRIS_STOPRIS_S 2 263 264 // Field: [1] STARTRIS 265 // 266 // Start condition raw interrupt status 267 // 268 // 0: No interrupt 269 // 1: A Start condition interrupt is pending. 270 // 271 // This bit is cleared by writing a 1 to SICR.STARTIC. 272 #define I2C_SRIS_STARTRIS 0x00000002 273 #define I2C_SRIS_STARTRIS_BITN 1 274 #define I2C_SRIS_STARTRIS_M 0x00000002 275 #define I2C_SRIS_STARTRIS_S 1 276 277 // Field: [0] DATARIS 278 // 279 // Data raw interrupt status 280 // 281 // 0: No interrupt 282 // 1: A data received or data requested interrupt is pending. 283 // 284 // This bit is cleared by writing a 1 to the SICR.DATAIC. 285 #define I2C_SRIS_DATARIS 0x00000001 286 #define I2C_SRIS_DATARIS_BITN 0 287 #define I2C_SRIS_DATARIS_M 0x00000001 288 #define I2C_SRIS_DATARIS_S 0 289 290 //***************************************************************************** 291 // 292 // Register: I2C_O_SMIS 293 // 294 //***************************************************************************** 295 // Field: [2] STOPMIS 296 // 297 // Stop condition masked interrupt status 298 // 299 // 0: An interrupt has not occurred or is masked/disabled. 300 // 1: An unmasked Stop condition interrupt is pending. 301 // 302 // This bit is cleared by writing a 1 to the SICR.STOPIC. 303 #define I2C_SMIS_STOPMIS 0x00000004 304 #define I2C_SMIS_STOPMIS_BITN 2 305 #define I2C_SMIS_STOPMIS_M 0x00000004 306 #define I2C_SMIS_STOPMIS_S 2 307 308 // Field: [1] STARTMIS 309 // 310 // Start condition masked interrupt status 311 // 312 // 0: An interrupt has not occurred or is masked/disabled. 313 // 1: An unmasked Start condition interrupt is pending. 314 // 315 // This bit is cleared by writing a 1 to the SICR.STARTIC. 316 #define I2C_SMIS_STARTMIS 0x00000002 317 #define I2C_SMIS_STARTMIS_BITN 1 318 #define I2C_SMIS_STARTMIS_M 0x00000002 319 #define I2C_SMIS_STARTMIS_S 1 320 321 // Field: [0] DATAMIS 322 // 323 // Data masked interrupt status 324 // 325 // 0: An interrupt has not occurred or is masked/disabled. 326 // 1: An unmasked data received or data requested interrupt is pending. 327 // 328 // This bit is cleared by writing a 1 to the SICR.DATAIC. 329 #define I2C_SMIS_DATAMIS 0x00000001 330 #define I2C_SMIS_DATAMIS_BITN 0 331 #define I2C_SMIS_DATAMIS_M 0x00000001 332 #define I2C_SMIS_DATAMIS_S 0 333 334 //***************************************************************************** 335 // 336 // Register: I2C_O_SICR 337 // 338 //***************************************************************************** 339 // Field: [2] STOPIC 340 // 341 // Stop condition interrupt clear 342 // 343 // Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. 344 #define I2C_SICR_STOPIC 0x00000004 345 #define I2C_SICR_STOPIC_BITN 2 346 #define I2C_SICR_STOPIC_M 0x00000004 347 #define I2C_SICR_STOPIC_S 2 348 349 // Field: [1] STARTIC 350 // 351 // Start condition interrupt clear 352 // 353 // Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. 354 #define I2C_SICR_STARTIC 0x00000002 355 #define I2C_SICR_STARTIC_BITN 1 356 #define I2C_SICR_STARTIC_M 0x00000002 357 #define I2C_SICR_STARTIC_S 1 358 359 // Field: [0] DATAIC 360 // 361 // Data interrupt clear 362 // 363 // Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. 364 #define I2C_SICR_DATAIC 0x00000001 365 #define I2C_SICR_DATAIC_BITN 0 366 #define I2C_SICR_DATAIC_M 0x00000001 367 #define I2C_SICR_DATAIC_S 0 368 369 //***************************************************************************** 370 // 371 // Register: I2C_O_MSA 372 // 373 //***************************************************************************** 374 // Field: [7:1] SA 375 // 376 // I2C master slave address 377 // Defines which slave is addressed for the transaction in master mode 378 #define I2C_MSA_SA_W 7 379 #define I2C_MSA_SA_M 0x000000FE 380 #define I2C_MSA_SA_S 1 381 382 // Field: [0] RS 383 // 384 // Receive or Send 385 // This bit-field specifies if the next operation is a receive (high) or a 386 // transmit/send (low) from the addressed slave SA. 387 // ENUMs: 388 // RX Receive data from slave 389 // TX Transmit/send data to slave 390 #define I2C_MSA_RS 0x00000001 391 #define I2C_MSA_RS_BITN 0 392 #define I2C_MSA_RS_M 0x00000001 393 #define I2C_MSA_RS_S 0 394 #define I2C_MSA_RS_RX 0x00000001 395 #define I2C_MSA_RS_TX 0x00000000 396 397 //***************************************************************************** 398 // 399 // Register: I2C_O_MSTAT 400 // 401 //***************************************************************************** 402 // Field: [6] BUSBSY 403 // 404 // Bus busy 405 // 406 // 0: The I2C bus is idle. 407 // 1: The I2C bus is busy. 408 // 409 // The bit changes based on the MCTRL.START and MCTRL.STOP conditions. 410 #define I2C_MSTAT_BUSBSY 0x00000040 411 #define I2C_MSTAT_BUSBSY_BITN 6 412 #define I2C_MSTAT_BUSBSY_M 0x00000040 413 #define I2C_MSTAT_BUSBSY_S 6 414 415 // Field: [5] IDLE 416 // 417 // I2C idle 418 // 419 // 0: The I2C controller is not idle. 420 // 1: The I2C controller is idle. 421 #define I2C_MSTAT_IDLE 0x00000020 422 #define I2C_MSTAT_IDLE_BITN 5 423 #define I2C_MSTAT_IDLE_M 0x00000020 424 #define I2C_MSTAT_IDLE_S 5 425 426 // Field: [4] ARBLST 427 // 428 // Arbitration lost 429 // 430 // 0: The I2C controller won arbitration. 431 // 1: The I2C controller lost arbitration. 432 #define I2C_MSTAT_ARBLST 0x00000010 433 #define I2C_MSTAT_ARBLST_BITN 4 434 #define I2C_MSTAT_ARBLST_M 0x00000010 435 #define I2C_MSTAT_ARBLST_S 4 436 437 // Field: [3] DATACK_N 438 // 439 // Data Was Not Acknowledge 440 // 441 // 0: The transmitted data was acknowledged. 442 // 1: The transmitted data was not acknowledged. 443 #define I2C_MSTAT_DATACK_N 0x00000008 444 #define I2C_MSTAT_DATACK_N_BITN 3 445 #define I2C_MSTAT_DATACK_N_M 0x00000008 446 #define I2C_MSTAT_DATACK_N_S 3 447 448 // Field: [2] ADRACK_N 449 // 450 // Address Was Not Acknowledge 451 // 452 // 0: The transmitted address was acknowledged. 453 // 1: The transmitted address was not acknowledged. 454 #define I2C_MSTAT_ADRACK_N 0x00000004 455 #define I2C_MSTAT_ADRACK_N_BITN 2 456 #define I2C_MSTAT_ADRACK_N_M 0x00000004 457 #define I2C_MSTAT_ADRACK_N_S 2 458 459 // Field: [1] ERR 460 // 461 // Error 462 // 463 // 0: No error was detected on the last operation. 464 // 1: An error occurred on the last operation. 465 #define I2C_MSTAT_ERR 0x00000002 466 #define I2C_MSTAT_ERR_BITN 1 467 #define I2C_MSTAT_ERR_M 0x00000002 468 #define I2C_MSTAT_ERR_S 1 469 470 // Field: [0] BUSY 471 // 472 // I2C busy 473 // 474 // 0: The controller is idle. 475 // 1: The controller is busy. 476 // 477 // When this bit-field is set, the other status bits are not valid. 478 // 479 // Note: The I2C controller requires four SYSBUS clock cycles to assert the 480 // BUSY status after I2C master operation has been initiated through MCTRL 481 // register. 482 // Hence after programming MCTRL register, application is requested to wait for 483 // four SYSBUS clock cycles before issuing a controller status inquiry through 484 // MSTAT register. 485 // Any prior inquiry would result in wrong status being reported. 486 #define I2C_MSTAT_BUSY 0x00000001 487 #define I2C_MSTAT_BUSY_BITN 0 488 #define I2C_MSTAT_BUSY_M 0x00000001 489 #define I2C_MSTAT_BUSY_S 0 490 491 //***************************************************************************** 492 // 493 // Register: I2C_O_MCTRL 494 // 495 //***************************************************************************** 496 // Field: [3] ACK 497 // 498 // Data acknowledge enable 499 // 500 // 0: The received data byte is not acknowledged automatically by the master. 501 // 1: The received data byte is acknowledged automatically by the master. 502 // 503 // This bit-field must be cleared when the I2C bus controller requires no 504 // further data to be transmitted from the slave transmitter. 505 // ENUMs: 506 // EN Enable acknowledge 507 // DIS Disable acknowledge 508 #define I2C_MCTRL_ACK 0x00000008 509 #define I2C_MCTRL_ACK_BITN 3 510 #define I2C_MCTRL_ACK_M 0x00000008 511 #define I2C_MCTRL_ACK_S 3 512 #define I2C_MCTRL_ACK_EN 0x00000008 513 #define I2C_MCTRL_ACK_DIS 0x00000000 514 515 // Field: [2] STOP 516 // 517 // This bit-field determines if the cycle stops at the end of the data cycle or 518 // continues on to a repeated START condition. 519 // 520 // 0: The controller does not generate the Stop condition. 521 // 1: The controller generates the Stop condition. 522 // ENUMs: 523 // EN Enable STOP 524 // DIS Disable STOP 525 #define I2C_MCTRL_STOP 0x00000004 526 #define I2C_MCTRL_STOP_BITN 2 527 #define I2C_MCTRL_STOP_M 0x00000004 528 #define I2C_MCTRL_STOP_S 2 529 #define I2C_MCTRL_STOP_EN 0x00000004 530 #define I2C_MCTRL_STOP_DIS 0x00000000 531 532 // Field: [1] START 533 // 534 // This bit-field generates the Start or Repeated Start condition. 535 // 536 // 0: The controller does not generate the Start condition. 537 // 1: The controller generates the Start condition. 538 // ENUMs: 539 // EN Enable START 540 // DIS Disable START 541 #define I2C_MCTRL_START 0x00000002 542 #define I2C_MCTRL_START_BITN 1 543 #define I2C_MCTRL_START_M 0x00000002 544 #define I2C_MCTRL_START_S 1 545 #define I2C_MCTRL_START_EN 0x00000002 546 #define I2C_MCTRL_START_DIS 0x00000000 547 548 // Field: [0] RUN 549 // 550 // I2C master enable 551 // 552 // 0: The master is disabled. 553 // 1: The master is enabled to transmit or receive data. 554 // ENUMs: 555 // EN Enable Master 556 // DIS Disable Master 557 #define I2C_MCTRL_RUN 0x00000001 558 #define I2C_MCTRL_RUN_BITN 0 559 #define I2C_MCTRL_RUN_M 0x00000001 560 #define I2C_MCTRL_RUN_S 0 561 #define I2C_MCTRL_RUN_EN 0x00000001 562 #define I2C_MCTRL_RUN_DIS 0x00000000 563 564 //***************************************************************************** 565 // 566 // Register: I2C_O_MDR 567 // 568 //***************************************************************************** 569 // Field: [7:0] DATA 570 // 571 // When Read: Last RX Data is returned 572 // When Written: Data is transferred during TX transaction 573 #define I2C_MDR_DATA_W 8 574 #define I2C_MDR_DATA_M 0x000000FF 575 #define I2C_MDR_DATA_S 0 576 577 //***************************************************************************** 578 // 579 // Register: I2C_O_MTPR 580 // 581 //***************************************************************************** 582 // Field: [7] TPR_7 583 // 584 // Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. 585 #define I2C_MTPR_TPR_7 0x00000080 586 #define I2C_MTPR_TPR_7_BITN 7 587 #define I2C_MTPR_TPR_7_M 0x00000080 588 #define I2C_MTPR_TPR_7_S 7 589 590 // Field: [6:0] TPR 591 // 592 // SCL clock period 593 // This field specifies the period of the SCL clock. 594 // SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD 595 // where: 596 // SCL_PRD is the SCL line period (I2C clock). 597 // TPR is the timer period register value (range of 1 to 127) 598 // SCL_LP is the SCL low period (fixed at 6). 599 // SCL_HP is the SCL high period (fixed at 4). 600 // CLK_PRD is the system clock period in ns. 601 #define I2C_MTPR_TPR_W 7 602 #define I2C_MTPR_TPR_M 0x0000007F 603 #define I2C_MTPR_TPR_S 0 604 605 //***************************************************************************** 606 // 607 // Register: I2C_O_MIMR 608 // 609 //***************************************************************************** 610 // Field: [0] IM 611 // 612 // Interrupt mask 613 // 614 // 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt 615 // controller. 616 // 1: The master interrupt is sent to the interrupt controller when the 617 // MRIS.RIS is set. 618 // ENUMs: 619 // EN Enable Interrupt 620 // DIS Disable Interrupt 621 #define I2C_MIMR_IM 0x00000001 622 #define I2C_MIMR_IM_BITN 0 623 #define I2C_MIMR_IM_M 0x00000001 624 #define I2C_MIMR_IM_S 0 625 #define I2C_MIMR_IM_EN 0x00000001 626 #define I2C_MIMR_IM_DIS 0x00000000 627 628 //***************************************************************************** 629 // 630 // Register: I2C_O_MRIS 631 // 632 //***************************************************************************** 633 // Field: [0] RIS 634 // 635 // Raw interrupt status 636 // 637 // 0: No interrupt 638 // 1: A master interrupt is pending. 639 // 640 // This bit is cleared by writing 1 to the MICR.IC bit . 641 #define I2C_MRIS_RIS 0x00000001 642 #define I2C_MRIS_RIS_BITN 0 643 #define I2C_MRIS_RIS_M 0x00000001 644 #define I2C_MRIS_RIS_S 0 645 646 //***************************************************************************** 647 // 648 // Register: I2C_O_MMIS 649 // 650 //***************************************************************************** 651 // Field: [0] MIS 652 // 653 // Masked interrupt status 654 // 655 // 0: An interrupt has not occurred or is masked. 656 // 1: A master interrupt is pending. 657 // 658 // This bit is cleared by writing 1 to the MICR.IC bit . 659 #define I2C_MMIS_MIS 0x00000001 660 #define I2C_MMIS_MIS_BITN 0 661 #define I2C_MMIS_MIS_M 0x00000001 662 #define I2C_MMIS_MIS_S 0 663 664 //***************************************************************************** 665 // 666 // Register: I2C_O_MICR 667 // 668 //***************************************************************************** 669 // Field: [0] IC 670 // 671 // Interrupt clear 672 // Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . 673 // 674 // Reading this register returns no meaningful data. 675 #define I2C_MICR_IC 0x00000001 676 #define I2C_MICR_IC_BITN 0 677 #define I2C_MICR_IC_M 0x00000001 678 #define I2C_MICR_IC_S 0 679 680 //***************************************************************************** 681 // 682 // Register: I2C_O_MCR 683 // 684 //***************************************************************************** 685 // Field: [5] SFE 686 // 687 // I2C slave function enable 688 // ENUMs: 689 // EN Slave mode is enabled. 690 // DIS Slave mode is disabled. 691 #define I2C_MCR_SFE 0x00000020 692 #define I2C_MCR_SFE_BITN 5 693 #define I2C_MCR_SFE_M 0x00000020 694 #define I2C_MCR_SFE_S 5 695 #define I2C_MCR_SFE_EN 0x00000020 696 #define I2C_MCR_SFE_DIS 0x00000000 697 698 // Field: [4] MFE 699 // 700 // I2C master function enable 701 // ENUMs: 702 // EN Master mode is enabled. 703 // DIS Master mode is disabled. 704 #define I2C_MCR_MFE 0x00000010 705 #define I2C_MCR_MFE_BITN 4 706 #define I2C_MCR_MFE_M 0x00000010 707 #define I2C_MCR_MFE_S 4 708 #define I2C_MCR_MFE_EN 0x00000010 709 #define I2C_MCR_MFE_DIS 0x00000000 710 711 // Field: [0] LPBK 712 // 713 // I2C loopback 714 // 715 // 0: Normal operation 716 // 1: Loopback operation (test mode) 717 // ENUMs: 718 // EN Enable Test Mode 719 // DIS Disable Test Mode 720 #define I2C_MCR_LPBK 0x00000001 721 #define I2C_MCR_LPBK_BITN 0 722 #define I2C_MCR_LPBK_M 0x00000001 723 #define I2C_MCR_LPBK_S 0 724 #define I2C_MCR_LPBK_EN 0x00000001 725 #define I2C_MCR_LPBK_DIS 0x00000000 726 727 728 #endif // __I2C__ 729
