1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_HIB3P3_H__ 35 #define __HW_HIB3P3_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the HIB3P3 register offsets. 40 // 41 //***************************************************************************** 42 #define HIB3P3_O_MEM_HIB_REQ 0x00000000 43 #define HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE \ 44 0x00000004 45 46 #define HIB3P3_O_MEM_HIB_RTC_TIMER_RESET \ 47 0x00000008 48 49 #define HIB3P3_O_MEM_HIB_RTC_TIMER_READ \ 50 0x0000000C 51 52 #define HIB3P3_O_MEM_HIB_RTC_TIMER_LSW \ 53 0x00000010 54 55 #define HIB3P3_O_MEM_HIB_RTC_TIMER_MSW \ 56 0x00000014 57 58 #define HIB3P3_O_MEM_HIB_RTC_WAKE_EN \ 59 0x00000018 60 61 #define HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF \ 62 0x0000001C 63 64 #define HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF \ 65 0x00000020 66 67 #define HIB3P3_O_MEM_INT_OSC_CONF \ 68 0x0000002C 69 70 #define HIB3P3_O_MEM_XTAL_OSC_CONF \ 71 0x00000034 72 73 #define HIB3P3_O_MEM_BGAP_PARAMETERS0 \ 74 0x00000038 75 76 #define HIB3P3_O_MEM_BGAP_PARAMETERS1 \ 77 0x0000003C 78 79 #define HIB3P3_O_MEM_HIB_DETECTION_STATUS \ 80 0x00000040 81 82 #define HIB3P3_O_MEM_HIB_MISC_CONTROLS \ 83 0x00000044 84 85 #define HIB3P3_O_MEM_HIB_CONFIG 0x00000050 86 #define HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE \ 87 0x00000054 88 89 #define HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF \ 90 0x00000058 91 92 #define HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF \ 93 0x0000005C 94 95 #define HIB3P3_O_MEM_HIB_UART_CONF \ 96 0x00000400 97 98 #define HIB3P3_O_MEM_GPIO_WAKE_EN \ 99 0x00000404 100 101 #define HIB3P3_O_MEM_GPIO_WAKE_CONF \ 102 0x00000408 103 104 #define HIB3P3_O_MEM_PAD_OEN_RET33_CONF \ 105 0x0000040C 106 107 #define HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF \ 108 0x00000410 109 110 #define HIB3P3_O_MEM_JTAG_CONF 0x00000414 111 #define HIB3P3_O_MEM_HIB_REG0 0x00000418 112 #define HIB3P3_O_MEM_HIB_REG1 0x0000041C 113 #define HIB3P3_O_MEM_HIB_REG2 0x00000420 114 #define HIB3P3_O_MEM_HIB_REG3 0x00000424 115 #define HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 \ 116 0x0000045C 117 118 #define HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 \ 119 0x00000460 120 121 #define HIB3P3_O_MEM_HIB_MISC_CONFIG \ 122 0x00000464 123 124 #define HIB3P3_O_MEM_HIB_WAKE_STATUS \ 125 0x00000468 126 127 #define HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL \ 128 0x0000046C 129 130 #define HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 \ 131 0x00000470 132 133 #define HIB3P3_O_HIBANA_SPARE_LOWV \ 134 0x00000474 135 136 #define HIB3P3_O_HIB_TMUX_CTRL 0x00000478 137 #define HIB3P3_O_HIB_1P2_1P8_LDO_TRIM \ 138 0x0000047C 139 140 #define HIB3P3_O_HIB_COMP_TRIM 0x00000480 141 #define HIB3P3_O_HIB_EN_TS 0x00000484 142 #define HIB3P3_O_HIB_1P8V_DET_EN \ 143 0x00000488 144 145 #define HIB3P3_O_HIB_VBAT_MON_EN \ 146 0x0000048C 147 148 #define HIB3P3_O_HIB_NHIB_ENABLE \ 149 0x00000490 150 151 #define HIB3P3_O_HIB_UART_RTS_SW_ENABLE \ 152 0x00000494 153 154 155 156 157 //****************************************************************************** 158 // 159 // The following are defines for the bit fields in the 160 // HIB3P3_O_MEM_HIB_REQ register. 161 // 162 //****************************************************************************** 163 #define HIB3P3_MEM_HIB_REQ_reserved_M \ 164 0xFFFFFE00 165 166 #define HIB3P3_MEM_HIB_REQ_reserved_S 9 167 #define HIB3P3_MEM_HIB_REQ_NU1_M \ 168 0x000001FC 169 170 #define HIB3P3_MEM_HIB_REQ_NU1_S 2 171 #define HIB3P3_MEM_HIB_REQ_mem_hib_clk_disable \ 172 0x00000002 // 1 - Specifies that the Hiberante 173 // mode is without clocks ; 0 - 174 // Specified that the Hibernate mode 175 // is with clocks This register will 176 // be reset during Hibernate 177 // -WO-Clks mode (but not during 178 // Hibernate-W-Clks mode). 179 180 #define HIB3P3_MEM_HIB_REQ_mem_hib_req \ 181 0x00000001 // 1 - Request for hibernate mode 182 // (This is an auto-clear bit) ; 0 - 183 // Donot request for hibernate mode 184 // This register will be reset 185 // during Hibernate -WO-Clks mode 186 // (but not during Hibernate-W-Clks 187 // mode). 188 189 //****************************************************************************** 190 // 191 // The following are defines for the bit fields in the 192 // HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE register. 193 // 194 //****************************************************************************** 195 #define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_M \ 196 0xFFFFFFFE 197 198 #define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_S 1 199 #define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_mem_hib_rtc_timer_enable \ 200 0x00000001 // 1 - Enable the RTC timer to 201 // start running ; 0 - Keep the RTC 202 // timer disabled This register will 203 // be reset during Hibernate 204 // -WO-Clks mode (but not during 205 // Hibernate-W-Clks mode). 206 207 //****************************************************************************** 208 // 209 // The following are defines for the bit fields in the 210 // HIB3P3_O_MEM_HIB_RTC_TIMER_RESET register. 211 // 212 //****************************************************************************** 213 #define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_M \ 214 0xFFFFFFFE 215 216 #define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_S 1 217 #define HIB3P3_MEM_HIB_RTC_TIMER_RESET_mem_hib_rtc_timer_reset \ 218 0x00000001 // 1 - Reset the RTC timer ; 0 - 219 // Donot reset the RTC timer. This 220 // is an auto-clear bit. This 221 // register will be reset during 222 // Hibernate -WO-Clks mode (but not 223 // during Hibernate-W-Clks mode). 224 225 //****************************************************************************** 226 // 227 // The following are defines for the bit fields in the 228 // HIB3P3_O_MEM_HIB_RTC_TIMER_READ register. 229 // 230 //****************************************************************************** 231 #define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_M \ 232 0xFFFFFFFE 233 234 #define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_S 1 235 #define HIB3P3_MEM_HIB_RTC_TIMER_READ_mem_hib_rtc_timer_read \ 236 0x00000001 // 1 - Latch the running RTC timer 237 // into local registers. After 238 // programming this bit to 1, the 239 // F/w can read the latched RTC 240 // timer values from 241 // MEM_HIB_RTC_TIMER_LSW and 242 // MEM_HIB_RTC_TIMER_MSW. Before the 243 // F/w (APPS or NWP) wants to read 244 // the RTC-Timer, it has to program 245 // this bit to 1, then only read the 246 // MSW and LSW values. This is an 247 // auto-clear bit. This register 248 // will be reset during Hibernate 249 // -WO-Clks mode (but not during 250 // Hibernate-W-Clks mode). 251 252 //****************************************************************************** 253 // 254 // The following are defines for the bit fields in the 255 // HIB3P3_O_MEM_HIB_RTC_TIMER_LSW register. 256 // 257 //****************************************************************************** 258 #define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_M \ 259 0xFFFFFFFF // Lower 32b value of the latched 260 // RTC-Timer. 261 262 #define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_S 0 263 //****************************************************************************** 264 // 265 // The following are defines for the bit fields in the 266 // HIB3P3_O_MEM_HIB_RTC_TIMER_MSW register. 267 // 268 //****************************************************************************** 269 #define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_M \ 270 0xFFFF0000 271 272 #define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_S 16 273 #define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_M \ 274 0x0000FFFF // Upper 32b value of the latched 275 // RTC-Timer. 276 277 #define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_S 0 278 //****************************************************************************** 279 // 280 // The following are defines for the bit fields in the 281 // HIB3P3_O_MEM_HIB_RTC_WAKE_EN register. 282 // 283 //****************************************************************************** 284 #define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_M \ 285 0xFFFFFFFE 286 287 #define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_S 1 288 #define HIB3P3_MEM_HIB_RTC_WAKE_EN_mem_hib_rtc_wake_en \ 289 0x00000001 // 1 - Enable the RTC timer based 290 // wakeup during Hibernate mode ; 0 291 // - Disable the RTC timer based 292 // wakeup during Hibernate mode This 293 // register will be reset during 294 // Hibernate-WO-Clks mode (but not 295 // during Hibernate-W-Clks mode). 296 297 //****************************************************************************** 298 // 299 // The following are defines for the bit fields in the 300 // HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF register. 301 // 302 //****************************************************************************** 303 #define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_M \ 304 0xFFFFFFFF // Configuration for RTC-Timer 305 // Wakeup (Lower 32b word) 306 307 #define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_S 0 308 //****************************************************************************** 309 // 310 // The following are defines for the bit fields in the 311 // HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF register. 312 // 313 //****************************************************************************** 314 #define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_M \ 315 0xFFFF0000 316 317 #define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_S 16 318 #define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_M \ 319 0x0000FFFF // Configuration for RTC-Timer 320 // Wakeup (Upper 16b word) 321 322 #define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_S 0 323 //****************************************************************************** 324 // 325 // The following are defines for the bit fields in the 326 // HIB3P3_O_MEM_INT_OSC_CONF register. 327 // 328 //****************************************************************************** 329 #define HIB3P3_MEM_INT_OSC_CONF_reserved_M \ 330 0xFFFF0000 331 332 #define HIB3P3_MEM_INT_OSC_CONF_reserved_S 16 333 #define HIB3P3_MEM_INT_OSC_CONF_cm_clk_good_32k_int \ 334 0x00008000 // 1 - Internal 32kHz Oscillator is 335 // valid ; 0 - Internal 32k 336 // oscillator clk is not valid 337 338 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_M \ 339 0x00007E00 340 341 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_S 9 342 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k_override_ctrl \ 343 0x00000100 // When 1, the INT_32K_OSC_EN comes 344 // from bit [0] of this register, 345 // else comes from the FSM. This 346 // register will be reset during 347 // Hibernate-WO-Clks mode (but not 348 // during Hibernate-W-Clks mode) 349 350 #define HIB3P3_MEM_INT_OSC_CONF_NU1 \ 351 0x00000080 352 353 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_M \ 354 0x0000007E 355 356 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_S 1 357 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k \ 358 0x00000001 // Override value for INT_OSC_EN. 359 // Applicable only when bit [3] of 360 // this register is set to 1. 361 362 //****************************************************************************** 363 // 364 // The following are defines for the bit fields in the 365 // HIB3P3_O_MEM_XTAL_OSC_CONF register. 366 // 367 //****************************************************************************** 368 #define HIB3P3_MEM_XTAL_OSC_CONF_reserved_M \ 369 0xFFF00000 370 371 #define HIB3P3_MEM_XTAL_OSC_CONF_reserved_S 20 372 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k_override_ctrl \ 373 0x00080000 // When 1, the SLICER_EN comes from 374 // bit [10] of this register, else 375 // comes from the FSM. 376 377 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k_override_ctrl \ 378 0x00040000 // When 1, the XTAL_EN comes from 379 // bit [0] of this register, else 380 // comes from the FSM. 381 382 #define HIB3P3_MEM_XTAL_OSC_CONF_cm_clk_good_xtal \ 383 0x00020000 // 1 - XTAL Clk is good ; 0 - XTAL 384 // Clk is yet to be valid. 385 386 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_M \ 387 0x0001F800 388 389 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_S 11 390 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k \ 391 0x00000400 // SLICER_EN Override value : 392 // Applicable only when bit [19] of 393 // this register is set to 1. 394 395 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_M \ 396 0x00000380 397 398 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_S 7 399 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_M \ 400 0x00000070 401 402 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_S 4 403 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_fref_32k_slicer \ 404 0x00000008 405 406 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_M \ 407 0x00000006 408 409 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_S 1 410 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k \ 411 0x00000001 // XTAL_EN Override value : 412 // Applicable only when bit [18] of 413 // this register is set to 1. 414 415 //****************************************************************************** 416 // 417 // The following are defines for the bit fields in the 418 // HIB3P3_O_MEM_BGAP_PARAMETERS0 register. 419 // 420 //****************************************************************************** 421 #define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_M \ 422 0xFFF80000 423 424 #define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_S 19 425 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_en_seq \ 426 0x00040000 427 428 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_M \ 429 0x0001C000 430 431 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_S 14 432 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbat_ok_4bg \ 433 0x00001000 434 435 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp \ 436 0x00000800 437 438 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp_ref \ 439 0x00000400 440 441 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_M \ 442 0x000003FF 443 444 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_S 0 445 //****************************************************************************** 446 // 447 // The following are defines for the bit fields in the 448 // HIB3P3_O_MEM_BGAP_PARAMETERS1 register. 449 // 450 //****************************************************************************** 451 #define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_M \ 452 0xE0000000 453 454 #define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_S 29 455 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_M \ 456 0x1F000000 457 458 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_S 24 459 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_act_iref \ 460 0x00000008 461 462 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_v2i \ 463 0x00000004 464 465 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_cap_sw \ 466 0x00000002 467 468 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en \ 469 0x00000001 470 471 //****************************************************************************** 472 // 473 // The following are defines for the bit fields in the 474 // HIB3P3_O_MEM_HIB_DETECTION_STATUS register. 475 // 476 //****************************************************************************** 477 #define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_M \ 478 0xFFFFFF80 479 480 #define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_S 7 481 #define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_ana_status \ 482 0x00000040 // 1 - 1.8 V supply forced mode. 483 484 #define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_flash_status \ 485 0x00000004 // 1 - 3.3 V supply forced mode for 486 // Flash supply 487 488 #define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_ext_clk_det_out_status \ 489 0x00000002 // 1 - Forced clock mode 490 491 #define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_xtal_det_out_status \ 492 0x00000001 // 1 - XTAL clock mode 493 494 //****************************************************************************** 495 // 496 // The following are defines for the bit fields in the 497 // HIB3P3_O_MEM_HIB_MISC_CONTROLS register. 498 // 499 //****************************************************************************** 500 #define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_M \ 501 0xFFFFF800 502 503 #define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_S 11 504 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp \ 505 0x00000400 506 507 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp_ref \ 508 0x00000200 509 510 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_M \ 511 0x000001C0 512 513 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_S 6 514 #define HIB3P3_MEM_HIB_MISC_CONTROLS_NU1 \ 515 0x00000020 516 517 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_flash_det_en \ 518 0x00000010 519 520 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_tmux \ 521 0x00000001 522 523 //****************************************************************************** 524 // 525 // The following are defines for the bit fields in the 526 // HIB3P3_O_MEM_HIB_CONFIG register. 527 // 528 //****************************************************************************** 529 #define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_M \ 530 0xFF000000 531 532 #define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_S 24 533 #define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED3 \ 534 0x00080000 // 1 - Enable VDD_FLASH_INDP_PAD 535 // for digital path (SHARED4) ; 0 - 536 // Disable VDD_FLASH_INDP_PAD for 537 // digital path (SHARED4) ; Before 538 // programming this bit to 1, ensure 539 // that the device is in FORCED 3.3 540 // supply Mode, which can be 541 // inferred from the register : 542 // MEM_HIB_DETECTION_STATUS : 0x0040 543 544 #define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED2 \ 545 0x00040000 // 1 - Enable the 546 // VDD_FB_GPIO_MUX_PAD for digital 547 // path (SHARED3) ; 0 - Disable the 548 // VDD_FB_GPIO_MUX_PAD for digital 549 // path (SHARED3) ; This pin can be 550 // used only in modes other than 551 // SOP("111") 552 553 #define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED1 \ 554 0x00020000 // 1 - Enable the PM_TEST_PAD for 555 // digital GPIO path (SHARED2) ; 0 - 556 // Disable the PM_TEST_PAD for 557 // digital GPIO path (SHARED2) This 558 // pin can be used for digital only 559 // in modes other then SOP-111 560 561 #define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED0 \ 562 0x00010000 // 1 - Enable the XTAL_N pin 563 // digital GPIO path (SHARED1); 0 - 564 // Disable the XTAL_N pin digital 565 // GPIO path (SHARED1). Before 566 // programming this bit to 1, ensure 567 // that the device is in FORCED CLK 568 // Mode, which can inferred from the 569 // register : 570 // MEM_HIB_DETECTION_STATUS : 571 // 0x0040. 572 573 #define HIB3P3_MEM_HIB_CONFIG_mem_hib_xtal_enable \ 574 0x00000100 // 1 - Enable the XTAL Clock ; 0 - 575 // Donot enable the XTAL Clock. This 576 // bit has to be programmed to 1 (by 577 // APPS Devinit F/w), during exit 578 // from OFF or Hib_wo_clks modes, 579 // after checking if the slow_clk 580 // mode is XTAL_CLK mode. Once 581 // enabled the XTAL will be disabled 582 // only after entering HIB_WO_CLKS 583 // mode. This register will be reset 584 // during Hibernate -WO-Clks mode 585 // (but not during Hibernate-W-Clks 586 // mode). 587 588 //****************************************************************************** 589 // 590 // The following are defines for the bit fields in the 591 // HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE register. 592 // 593 //****************************************************************************** 594 #define HIB3P3_MEM_HIB_RTC_IRQ_ENABLE_HIB_RTC_IRQ_ENABLE \ 595 0x00000001 // 1 - Enable the HIB RTC - IRQ ; 0 596 // - Disable the HIB RTC - IRQ 597 598 //****************************************************************************** 599 // 600 // The following are defines for the bit fields in the 601 // HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF register. 602 // 603 //****************************************************************************** 604 #define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_M \ 605 0xFFFFFFFF // Configuration for LSW of the 606 // RTC-Timestamp at which interrupt 607 // need to be generated 608 609 #define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_S 0 610 //****************************************************************************** 611 // 612 // The following are defines for the bit fields in the 613 // HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF register. 614 // 615 //****************************************************************************** 616 #define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_M \ 617 0x0000FFFF // Configuration for MSW of thr 618 // RTC-Timestamp at which the 619 // interrupt need to be generated 620 621 #define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_S 0 622 //****************************************************************************** 623 // 624 // The following are defines for the bit fields in the 625 // HIB3P3_O_MEM_HIB_UART_CONF register. 626 // 627 //****************************************************************************** 628 #define HIB3P3_MEM_HIB_UART_CONF_reserved_M \ 629 0xFFFFFFFE 630 631 #define HIB3P3_MEM_HIB_UART_CONF_reserved_S 1 632 #define HIB3P3_MEM_HIB_UART_CONF_mem_hib_uart_wake_en \ 633 0x00000001 // 1 - Enable the UART-Autonomous 634 // mode wakeup during Hibernate mode 635 // ; This is an auto-clear bit, once 636 // programmed to 1, it will latched 637 // into an internal register which 638 // remain asserted until the 639 // Hib-wakeup is initiated. 640 641 //****************************************************************************** 642 // 643 // The following are defines for the bit fields in the 644 // HIB3P3_O_MEM_GPIO_WAKE_EN register. 645 // 646 //****************************************************************************** 647 #define HIB3P3_MEM_GPIO_WAKE_EN_reserved_M \ 648 0xFFFFFF00 649 650 #define HIB3P3_MEM_GPIO_WAKE_EN_reserved_S 8 651 #define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_M \ 652 0x000000FF // 1 - Enable the GPIO-Autonomous 653 // mode wakeup during Hibernate mode 654 // ; This is an auto-clear bit, once 655 // programmed to 1, it will latched 656 // into an internal register which 657 // remain asserted until the 658 // Hib-wakeup is initiated. 659 660 #define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_S 0 661 //****************************************************************************** 662 // 663 // The following are defines for the bit fields in the 664 // HIB3P3_O_MEM_GPIO_WAKE_CONF register. 665 // 666 //****************************************************************************** 667 #define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_M \ 668 0xFFFF0000 669 670 #define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_S 16 671 #define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_M \ 672 0x0000FFFF // Configuration to say whether the 673 // GPIO wakeup has to happen on 674 // Level0 or falling-edge for the 675 // given group. “00�? – Level0 “01�? – 676 // Level1 “10�?- Fall-edge “11�?- 677 // Rise-edge [1:0] – Conf for GPIO0 678 // [3:2] – Conf for GPIO1 [5:4] – 679 // Conf for GPIO2 [7:6] – Conf for 680 // GPIO3 [9:8] – Conf for GPIO4 681 // [11:10] – Conf for GPIO5 [13:12] 682 // – Conf for GPIO6 683 684 #define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_S 0 685 //****************************************************************************** 686 // 687 // The following are defines for the bit fields in the 688 // HIB3P3_O_MEM_PAD_OEN_RET33_CONF register. 689 // 690 //****************************************************************************** 691 #define HIB3P3_MEM_PAD_OEN_RET33_CONF_mem_pad_oen_ret33_override_ctrl \ 692 0x00000004 // 1 - Override the OEN33 and RET33 693 // controls of GPIOs during 694 // SOP-Bootdebug mode ; 0 - Donot 695 // override the OEN33 and RET33 696 // controls of GPIOs during 697 // SOP-Bootdebug mode 698 699 #define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_OEN33_CONF \ 700 0x00000002 701 702 #define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_RET33_CONF \ 703 0x00000001 704 705 //****************************************************************************** 706 // 707 // The following are defines for the bit fields in the 708 // HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF register. 709 // 710 //****************************************************************************** 711 #define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_mem_uart_nrts_oen_ret33_override_ctrl \ 712 0x00000004 // 1 - Override the OEN33 and RET33 713 // controls of UART NRTS GPIO during 714 // SOP-Bootdebug mode ; 0 - Donot 715 // override the OEN33 and RET33 716 // controls of UART NRTS GPIO during 717 // SOP-Bootdebug mode 718 719 #define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_OEN33_CONF \ 720 0x00000002 721 722 #define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_RET33_CONF \ 723 0x00000001 724 725 //****************************************************************************** 726 // 727 // The following are defines for the bit fields in the 728 // HIB3P3_O_MEM_JTAG_CONF register. 729 // 730 //****************************************************************************** 731 #define HIB3P3_MEM_JTAG_CONF_mem_jtag1_oen_ret33_override_ctrl \ 732 0x00000200 733 734 #define HIB3P3_MEM_JTAG_CONF_mem_jtag0_oen_ret33_override_ctrl \ 735 0x00000100 736 737 #define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_OEN33_CONF \ 738 0x00000008 739 740 #define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_RET33_CONF \ 741 0x00000004 742 743 #define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_OEN33_CONF \ 744 0x00000002 745 746 #define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_RET33_CONF \ 747 0x00000001 748 749 //****************************************************************************** 750 // 751 // The following are defines for the bit fields in the 752 // HIB3P3_O_MEM_HIB_REG0 register. 753 // 754 //****************************************************************************** 755 #define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_M \ 756 0xFFFFFFFF 757 758 #define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_S 0 759 //****************************************************************************** 760 // 761 // The following are defines for the bit fields in the 762 // HIB3P3_O_MEM_HIB_REG1 register. 763 // 764 //****************************************************************************** 765 #define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_M \ 766 0xFFFFFFFF 767 768 #define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_S 0 769 //****************************************************************************** 770 // 771 // The following are defines for the bit fields in the 772 // HIB3P3_O_MEM_HIB_REG2 register. 773 // 774 //****************************************************************************** 775 #define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_M \ 776 0xFFFFFFFF 777 778 #define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_S 0 779 //****************************************************************************** 780 // 781 // The following are defines for the bit fields in the 782 // HIB3P3_O_MEM_HIB_REG3 register. 783 // 784 //****************************************************************************** 785 #define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_M \ 786 0xFFFFFFFF 787 788 #define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_S 0 789 //****************************************************************************** 790 // 791 // The following are defines for the bit fields in the 792 // HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 register. 793 // 794 //****************************************************************************** 795 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_M \ 796 0xFFFF0000 // Configuration for the number of 797 // slow-clks between de-assertion of 798 // EN_BG_3P3V to assertion of 799 // EN_BG_3P3V 800 801 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_S 16 802 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_NU1 \ 803 0x00008000 804 805 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_M \ 806 0x00006000 // Configuration for the number of 807 // slow-clks between assertion of 808 // EN_COMP_3P3V and assertion of 809 // EN_COMP_LATCH_3P3V 810 811 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_S 13 812 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_M \ 813 0x00001800 // Configuration for the number of 814 // slow-clks between assertion of 815 // (EN_CAP_SW_3P3V,EN_COMP_REF) and 816 // assertion of (EN_COMP_3P3V) 817 818 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_S 11 819 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_M \ 820 0x00000600 // Configuration for the number of 821 // slow-clks between assertion of 822 // (EN_BG_3P3V) and assertion of 823 // (EN_CAP_SW_3P3V, 824 // EN_COMP_REF_3P3V) 825 826 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_S 9 827 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_crude_ref_comp \ 828 0x00000100 829 830 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_ref_override_ctrl \ 831 0x00000080 // 1 - EN_VBOK4BG_REF comes from 832 // bit[10] of the register 833 // MEM_BGAP_PARAMETERS0 [0x0038]. 0 834 // - EN_VBOK4BG_REF comes directly 835 // from the Hib-Sequencer. 836 837 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_comp_override_ctrl \ 838 0x00000040 // 1 - EN_VBOK4BG comes from 839 // bit[11] of the register 840 // MEM_BGAP_PARAMETERS0 [0x0038]. 0 841 // - EN_VBOK4BG comes directly from 842 // the Hib-Sequencer. 843 844 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_v2i_override_ctrl \ 845 0x00000020 // 1 - EN_V2I comes from bit[2] of 846 // the register MEM_BGAP_PARAMETERS1 847 // [0x003C]. 0 - EN_V2I comes 848 // directly from the Hib-Sequencer. 849 850 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_por_comp_ref_override_ctrl \ 851 0x00000010 // 1 - EN_POR_COMP_REF comes from 852 // bit[9] of the register 853 // MEM_HIB_MISC_CONTROLS [0x0044]. 0 854 // - EN_POR_COMP_REF comes directly 855 // from the Hib-Sequencer. 856 857 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_por_comp_override_ctrl \ 858 0x00000008 // 1 - EN_POR_COMP comes from 859 // bit[10] of the register 860 // MEM_HIB_MISC_CONTROLS [0x044]. 0 861 // - EN_POR_COMP comes directly from 862 // the Hib-Sequencer. 863 864 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_cap_sw_override_ctrl \ 865 0x00000004 // 1 - EN_CAP_SW comes from bit[1] 866 // of the register 867 // MEM_BGAP_PARAMETERS1 [0x003C]. 0 868 // - EN_CAP_SW comes directly from 869 // Hib-Sequencer. 870 871 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bg_override_ctrl \ 872 0x00000002 // 1 - EN_BGAP comes from bit[0] of 873 // the register MEM_BGAP_PARAMETERS1 874 // [0x003C]. 0 - EN_BGAP comes 875 // directly from Hib-Sequencer. 876 877 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_act_iref_override_ctrl \ 878 0x00000001 879 880 //****************************************************************************** 881 // 882 // The following are defines for the bit fields in the 883 // HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 register. 884 // 885 //****************************************************************************** 886 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_M \ 887 0xFFFF0000 888 889 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_S 16 890 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_M \ 891 0x0000C000 // Configuration for number of 892 // slow-clks between de-assertion of 893 // EN_COMP_LATCH and assertion of 894 895 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_S 14 896 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_M \ 897 0x00003000 // Configuration for number of 898 // slow-clks between assertion of 899 // EN_COMP_REF to assertion of 900 // EN_COMP during HIB-Exit 901 902 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_S 12 903 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_M \ 904 0x00000C00 // TBD 905 906 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_S 10 907 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_M \ 908 0x00000300 // Configuration in number of 909 // slow-clks between assertion of 910 // (EN_BGAP_3P3V, EN_CAP_SW_3P3V, 911 // EN_ACT_IREF_3P3V, EN_COMP_REF) to 912 // assertion of EN_COMP_3P3V 913 914 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_S 8 915 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_M \ 916 0x000000C0 // Configuration in number of 917 // slow-clks between de-assertion of 918 // (EN_COMP_3P3V, EN_COMP_REF_3P3V, 919 // EN_ACT_IREF_3P3V, EN_CAP_SW_3P3V) 920 // to deassertion of EN_BGAP_3P3V. 921 922 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_S 6 923 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_M \ 924 0x0000003F 925 926 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_S 0 927 //****************************************************************************** 928 // 929 // The following are defines for the bit fields in the 930 // HIB3P3_O_MEM_HIB_MISC_CONFIG register. 931 // 932 //****************************************************************************** 933 #define HIB3P3_MEM_HIB_MISC_CONFIG_mem_en_pll_untrim_current \ 934 0x00000001 935 936 //****************************************************************************** 937 // 938 // The following are defines for the bit fields in the 939 // HIB3P3_O_MEM_HIB_WAKE_STATUS register. 940 // 941 //****************************************************************************** 942 #define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_M \ 943 0x0000001E // "0100" - GPIO ; "0010" - RTC ; 944 // "0001" - UART Others - Reserved 945 946 #define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_S 1 947 #define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_status \ 948 0x00000001 // 1 - Wake from Hibernate ; 0 - 949 // Wake from OFF 950 951 //****************************************************************************** 952 // 953 // The following are defines for the bit fields in the 954 // HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL register. 955 // 956 //****************************************************************************** 957 #define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_M \ 958 0x00000007 959 960 #define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_S 0 961 //****************************************************************************** 962 // 963 // The following are defines for the bit fields in the 964 // HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 register. 965 // 966 //****************************************************************************** 967 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_M \ 968 0xFFFFF800 969 970 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_S 11 971 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_M \ 972 0x00000600 // Deassertion of EN_COMP_LATCH_3P3 973 // to deassertion of (EN_COMP_3P3, 974 // EN_COMP_REF_3P3, EN_ACT_IREF_3P3, 975 // EN_CAP_SW_3P3) 976 977 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_S 9 978 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_M \ 979 0x000001C0 // Assertion of EN_COMP_LATCH_3P3 980 // to deassertion of 981 // EN_COMP_LATCH_3P3 982 983 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_S 6 984 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_M \ 985 0x00000030 // Deassertion of (EN_CAP_SW_3P3, 986 // EN_COMP_REF_3P3, EN_COMP_3P3, 987 // EN_COMP_OUT_LATCH_3P3) to 988 // deassertion of EN_BGAP_3P3 989 990 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_S 4 991 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_M \ 992 0x0000000C // Assertion of EN_COMP_3P3 to 993 // assertion of EN_COMPOUT_LATCH_3P3 994 995 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_S 2 996 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_M \ 997 0x00000003 // Assertion of EN_COMP_3P3 to 998 // assertion of EN_COMPOUT_LATCH_3P3 999 1000 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_S 0 1001 //****************************************************************************** 1002 // 1003 // The following are defines for the bit fields in the 1004 // HIB3P3_O_HIBANA_SPARE_LOWV register. 1005 // 1006 //****************************************************************************** 1007 #define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_M \ 1008 0xFFC00000 1009 1010 #define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_S 22 1011 #define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_M \ 1012 0x0001FFFF 1013 1014 #define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_S 0 1015 //****************************************************************************** 1016 // 1017 // The following are defines for the bit fields in the 1018 // HIB3P3_O_HIB_TMUX_CTRL register. 1019 // 1020 //****************************************************************************** 1021 #define HIB3P3_HIB_TMUX_CTRL_reserved_M \ 1022 0xFFFFFC00 1023 1024 #define HIB3P3_HIB_TMUX_CTRL_reserved_S 10 1025 #define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_M \ 1026 0x000003FF 1027 1028 #define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_S 0 1029 //****************************************************************************** 1030 // 1031 // The following are defines for the bit fields in the 1032 // HIB3P3_O_HIB_1P2_1P8_LDO_TRIM register. 1033 // 1034 //****************************************************************************** 1035 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_M \ 1036 0xFFFFF000 1037 1038 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_S 12 1039 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override_ctrl \ 1040 0x00000800 1041 1042 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override_ctrl \ 1043 0x00000400 1044 1045 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override \ 1046 0x00000200 1047 1048 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override \ 1049 0x00000100 1050 1051 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_M \ 1052 0x000000F0 1053 1054 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_S 4 1055 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_M \ 1056 0x0000000F 1057 1058 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_S 0 1059 //****************************************************************************** 1060 // 1061 // The following are defines for the bit fields in the 1062 // HIB3P3_O_HIB_COMP_TRIM register. 1063 // 1064 //****************************************************************************** 1065 #define HIB3P3_HIB_COMP_TRIM_reserved_M \ 1066 0xFFFFFFF8 1067 1068 #define HIB3P3_HIB_COMP_TRIM_reserved_S 3 1069 #define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_M \ 1070 0x00000007 1071 1072 #define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_S 0 1073 //****************************************************************************** 1074 // 1075 // The following are defines for the bit fields in the 1076 // HIB3P3_O_HIB_EN_TS register. 1077 // 1078 //****************************************************************************** 1079 #define HIB3P3_HIB_EN_TS_reserved_M \ 1080 0xFFFFFFFE 1081 1082 #define HIB3P3_HIB_EN_TS_reserved_S 1 1083 #define HIB3P3_HIB_EN_TS_mem_hd_en_ts \ 1084 0x00000001 1085 1086 //****************************************************************************** 1087 // 1088 // The following are defines for the bit fields in the 1089 // HIB3P3_O_HIB_1P8V_DET_EN register. 1090 // 1091 //****************************************************************************** 1092 #define HIB3P3_HIB_1P8V_DET_EN_reserved_M \ 1093 0xFFFFFFFE 1094 1095 #define HIB3P3_HIB_1P8V_DET_EN_reserved_S 1 1096 #define HIB3P3_HIB_1P8V_DET_EN_mem_hib_1p8v_det_en \ 1097 0x00000001 1098 1099 //****************************************************************************** 1100 // 1101 // The following are defines for the bit fields in the 1102 // HIB3P3_O_HIB_VBAT_MON_EN register. 1103 // 1104 //****************************************************************************** 1105 #define HIB3P3_HIB_VBAT_MON_EN_reserved_M \ 1106 0xFFFFFFFC 1107 1108 #define HIB3P3_HIB_VBAT_MON_EN_reserved_S 2 1109 #define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_del_en \ 1110 0x00000002 1111 1112 #define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_en \ 1113 0x00000001 1114 1115 //****************************************************************************** 1116 // 1117 // The following are defines for the bit fields in the 1118 // HIB3P3_O_HIB_NHIB_ENABLE register. 1119 // 1120 //****************************************************************************** 1121 #define HIB3P3_HIB_NHIB_ENABLE_mem_hib_nhib_enable \ 1122 0x00000001 1123 1124 //****************************************************************************** 1125 // 1126 // The following are defines for the bit fields in the 1127 // HIB3P3_O_HIB_UART_RTS_SW_ENABLE register. 1128 // 1129 //****************************************************************************** 1130 #define HIB3P3_HIB_UART_RTS_SW_ENABLE_mem_hib_uart_rts_sw_enable \ 1131 0x00000001 1132 1133 1134 1135 1136 #endif // __HW_HIB3P3_H__ 1137
