1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_HIB1P2_H__ 35 #define __HW_HIB1P2_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the HIB1P2 register offsets. 40 // 41 //***************************************************************************** 42 #define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 \ 43 0x00000000 44 45 #define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 \ 46 0x00000004 47 48 #define HIB1P2_O_DIG_DCDC_PARAMETERS0 \ 49 0x00000008 50 51 #define HIB1P2_O_DIG_DCDC_PARAMETERS1 \ 52 0x0000000C 53 54 #define HIB1P2_O_DIG_DCDC_PARAMETERS2 \ 55 0x00000010 56 57 #define HIB1P2_O_DIG_DCDC_PARAMETERS3 \ 58 0x00000014 59 60 #define HIB1P2_O_DIG_DCDC_PARAMETERS4 \ 61 0x00000018 62 63 #define HIB1P2_O_DIG_DCDC_PARAMETERS5 \ 64 0x0000001C 65 66 #define HIB1P2_O_DIG_DCDC_PARAMETERS6 \ 67 0x00000020 68 69 #define HIB1P2_O_ANA_DCDC_PARAMETERS0 \ 70 0x00000024 71 72 #define HIB1P2_O_ANA_DCDC_PARAMETERS1 \ 73 0x00000028 74 75 #define HIB1P2_O_ANA_DCDC_PARAMETERS16 \ 76 0x00000064 77 78 #define HIB1P2_O_ANA_DCDC_PARAMETERS17 \ 79 0x00000068 80 81 #define HIB1P2_O_ANA_DCDC_PARAMETERS18 \ 82 0x0000006C 83 84 #define HIB1P2_O_ANA_DCDC_PARAMETERS19 \ 85 0x00000070 86 87 #define HIB1P2_O_FLASH_DCDC_PARAMETERS0 \ 88 0x00000074 89 90 #define HIB1P2_O_FLASH_DCDC_PARAMETERS1 \ 91 0x00000078 92 93 #define HIB1P2_O_FLASH_DCDC_PARAMETERS2 \ 94 0x0000007C 95 96 #define HIB1P2_O_FLASH_DCDC_PARAMETERS3 \ 97 0x00000080 98 99 #define HIB1P2_O_FLASH_DCDC_PARAMETERS4 \ 100 0x00000084 101 102 #define HIB1P2_O_FLASH_DCDC_PARAMETERS5 \ 103 0x00000088 104 105 #define HIB1P2_O_FLASH_DCDC_PARAMETERS6 \ 106 0x0000008C 107 108 #define HIB1P2_O_PMBIST_PARAMETERS0 \ 109 0x00000094 110 111 #define HIB1P2_O_PMBIST_PARAMETERS1 \ 112 0x00000098 113 114 #define HIB1P2_O_PMBIST_PARAMETERS2 \ 115 0x0000009C 116 117 #define HIB1P2_O_PMBIST_PARAMETERS3 \ 118 0x000000A0 119 120 #define HIB1P2_O_FLASH_DCDC_PARAMETERS8 \ 121 0x000000A4 122 123 #define HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE \ 124 0x000000A8 125 126 #define HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE \ 127 0x000000AC 128 129 #define HIB1P2_O_DIG_DCDC_VTRIM_CFG \ 130 0x000000B0 131 132 #define HIB1P2_O_DIG_DCDC_FSM_PARAMETERS \ 133 0x000000B4 134 135 #define HIB1P2_O_ANA_DCDC_FSM_PARAMETERS \ 136 0x000000B8 137 138 #define HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS \ 139 0x000000BC 140 141 #define HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG \ 142 0x000000C0 143 144 #define HIB1P2_O_CM_OSC_16M_CONFIG \ 145 0x000000C4 146 147 #define HIB1P2_O_SOP_SENSE_VALUE \ 148 0x000000C8 149 150 #define HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 \ 151 0x000000CC 152 153 #define HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 \ 154 0x000000D0 155 156 #define HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES \ 157 0x000000D4 158 159 #define HIB1P2_O_HIB1P2_EFUSE_READ_REG0 \ 160 0x000000D8 161 162 #define HIB1P2_O_HIB1P2_EFUSE_READ_REG1 \ 163 0x000000DC 164 165 #define HIB1P2_O_HIB1P2_POR_TEST_CTRL \ 166 0x000000E0 167 168 #define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 \ 169 0x000000E4 170 171 #define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 \ 172 0x000000E8 173 174 #define HIB1P2_O_HIB_TIMER_SYNC_CFG2 \ 175 0x000000EC 176 177 #define HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL \ 178 0x000000F0 179 180 #define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW \ 181 0x000000F4 182 183 #define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW \ 184 0x000000F8 185 186 #define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW \ 187 0x000000FC 188 189 #define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW \ 190 0x00000100 191 192 #define HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR \ 193 0x00000104 194 195 #define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW \ 196 0x00000108 197 198 #define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW \ 199 0x0000010C 200 201 #define HIB1P2_O_CM_SPARE 0x00000110 202 #define HIB1P2_O_PORPOL_SPARE 0x00000114 203 #define HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG \ 204 0x00000118 205 206 #define HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG \ 207 0x0000011C 208 209 #define HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG \ 210 0x00000120 211 212 #define HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG \ 213 0x00000124 214 215 #define HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE \ 216 0x00000128 217 218 #define HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE \ 219 0x0000012C 220 221 #define HIB1P2_O_MEM_HIB_FSM_DEBUG \ 222 0x00000130 223 224 #define HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL \ 225 0x00000134 226 227 #define HIB1P2_O_MEM_SLDO_WEAK_PROCESS \ 228 0x00000138 229 230 #define HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS \ 231 0x0000013C 232 233 #define HIB1P2_O_MEM_CM_TEST_MODE \ 234 0x00000140 235 236 237 238 239 //****************************************************************************** 240 // 241 // The following are defines for the bit fields in the 242 // HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 register. 243 // 244 //****************************************************************************** 245 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_M \ 246 0xC0000000 247 248 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_S 30 249 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_M \ 250 0x30000000 251 252 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_S 28 253 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_prot_lowv \ 254 0x08000000 255 256 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_override \ 257 0x04000000 // FSM Override value for SLDO_EN : 258 // Applicable only when bit [4] of 259 // this register is set to 1. 260 261 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_low_pwr_lowv \ 262 0x02000000 263 264 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_int_cap_sel_lowv \ 265 0x01000000 266 267 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_M \ 268 0x00FC0000 269 270 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_S 18 271 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_M \ 272 0x0003FF00 273 274 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_S 8 275 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_override \ 276 0x00000080 // FSM Override value for 277 // SKA_LDO_EN : Applicable only when 278 // bit [3] of this register is set 279 // to 1. 280 281 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_cap_ref_lowv \ 282 0x00000040 283 284 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_resdiv_ref_lowv \ 285 0x00000020 286 287 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_fsm_override_ctrl \ 288 0x00000010 // When 1, bit[26] of this register 289 // will be used as SLDO_EN 290 291 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_fsm_override_ctrl \ 292 0x00000008 // When 1, bit[26] of this register 293 // will be used as SKA_LDO_EN 294 295 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_M \ 296 0x00000007 297 298 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_S 0 299 //****************************************************************************** 300 // 301 // The following are defines for the bit fields in the 302 // HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 register. 303 // 304 //****************************************************************************** 305 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_M \ 306 0xFFC00000 307 308 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_S 22 309 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_M \ 310 0x003F0000 311 312 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_S 16 313 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_sldo_en_tload_lowv \ 314 0x00008000 315 316 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_tload_lowv \ 317 0x00004000 318 319 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_cap_sw_en_lowv \ 320 0x00002000 321 322 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_hib_lowv \ 323 0x00001000 324 325 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_vref_buf_lowv \ 326 0x00000800 327 328 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_M \ 329 0x000007FF 330 331 #define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_S 0 332 //****************************************************************************** 333 // 334 // The following are defines for the bit fields in the 335 // HIB1P2_O_DIG_DCDC_PARAMETERS0 register. 336 // 337 //****************************************************************************** 338 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_lowv_override \ 339 0x80000000 // Override value for DCDC_DIG_EN : 340 // Applicable only when bit [31] of 341 // DIG_DCDC_PARAMETERS1 [0x000C] is 342 // set to 1. Else from FSM 343 344 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_delayed_en_lowv \ 345 0x40000000 346 347 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p8v_lowv_override \ 348 0x20000000 // Override value for 349 // DCDC_DIG_EN_SUBREG_1P8V : 350 // Applicable only when bit [30] of 351 // DIG_DCDC_PARAMETERS1 [0x000C] is 352 // set to 1. Else from FSM 353 354 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p2v_lowv_override \ 355 0x10000000 // Override value for 356 // DCDC_DIG_EN_SUBREG_1P2V : 357 // Applicable only when bit [29] of 358 // DIG_DCDC_PARAMETERS1 [0x000C] is 359 // set to 1. Else from FSM 360 361 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_slp_mode_lowv_override \ 362 0x08000000 // Override value for 363 // DCDC_DIG_SLP_EN : Applicable only 364 // when bit [28] of 365 // DIG_DCDC_PARAMETERS1 [0x000C] is 366 // set to 1. Else from FSM 367 368 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_ldo_mode_lowv \ 369 0x04000000 370 371 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_nfet_rds_mode_lowv \ 372 0x02000000 373 374 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_pfet_rds_mode_lowv \ 375 0x01000000 376 377 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_ext_smps_override_mode_lowv \ 378 0x00800000 379 380 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_clk_in_lowv_enable \ 381 0x00400000 382 383 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_M \ 384 0x003F0000 // Override value for 385 // DCDC_DIG_VTRIM : Applicable only 386 // when bit [27] of 387 // DIG_DCDC_PARAMETERS1 [0x000C] is 388 // set to 1. 389 390 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_S 16 391 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_M \ 392 0x0000C000 393 394 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_S 14 395 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_M \ 396 0x00003000 397 398 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_S 12 399 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_cl_non_ov_lowv \ 400 0x00000800 401 402 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_M \ 403 0x00000780 404 405 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_S 7 406 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_M \ 407 0x00000078 408 409 #define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_S 3 410 #define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_M \ 411 0x00000007 412 413 #define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_S 0 414 //****************************************************************************** 415 // 416 // The following are defines for the bit fields in the 417 // HIB1P2_O_DIG_DCDC_PARAMETERS1 register. 418 // 419 //****************************************************************************** 420 #define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_lowv_fsm_override_ctrl \ 421 0x80000000 422 423 #define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p8v_fsm_override_ctrl \ 424 0x40000000 425 426 #define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p2v_fsm_override_ctrl \ 427 0x20000000 428 429 #define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_slp_mode_lowv_fsm_override_ctrl \ 430 0x10000000 431 432 #define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_vtrim_fsm_override_ctrl \ 433 0x08000000 434 435 #define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_cot_mode_en_lowv_fsm_override_ctrl \ 436 0x04000000 437 438 #define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_ilim_trim_lowv_efc_override_ctrl \ 439 0x02000000 440 441 #define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_M \ 442 0x01FFFFFF 443 444 #define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_S 0 445 //****************************************************************************** 446 // 447 // The following are defines for the bit fields in the 448 // HIB1P2_O_DIG_DCDC_PARAMETERS2 register. 449 // 450 //****************************************************************************** 451 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_M \ 452 0xF0000000 453 454 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_S 28 455 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_M \ 456 0x0F000000 457 458 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_S 24 459 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_M \ 460 0x00C00000 461 462 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_S 22 463 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_M \ 464 0x00300000 465 466 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_S 20 467 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_M \ 468 0x000F0000 469 470 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_S 16 471 #define HIB1P2_DIG_DCDC_PARAMETERS2_NA5 \ 472 0x00008000 473 474 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_M \ 475 0x00007800 476 477 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_S 11 478 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_en_shootthru_ctrl_lowv \ 479 0x00000400 480 481 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_M \ 482 0x000003FC 483 484 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_S 2 485 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_swcap_res_hf_clk_lowv \ 486 0x00000002 487 488 #define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_cot_mode_en_lowv_override \ 489 0x00000001 // Override value for 490 // DCDC_DIG_COT_EN : Applicable only 491 // when bit[26] of 492 // DIG_DCDC_PARAMETERS1 [0x000C] is 493 // set to 1. 494 495 //****************************************************************************** 496 // 497 // The following are defines for the bit fields in the 498 // HIB1P2_O_DIG_DCDC_PARAMETERS3 register. 499 // 500 //****************************************************************************** 501 #define HIB1P2_DIG_DCDC_PARAMETERS3_NA6 \ 502 0x80000000 503 504 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_M \ 505 0x7F800000 506 507 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_S 23 508 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_lowv \ 509 0x00400000 510 511 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_hib_lowv \ 512 0x00200000 513 514 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_M \ 515 0x001FE000 // Override value for 516 // DCDC_DIG_ILIM_TRIM : Applicable 517 // only when bit [25] of 518 // DIG_DCDC_PARAMETERS1 [0x000C] is 519 // set to 1 520 521 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_S 13 522 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_M \ 523 0x00001800 524 525 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_S 11 526 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_lowv \ 527 0x00000400 528 529 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_hib_lowv \ 530 0x00000200 531 532 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_M \ 533 0x000001F0 534 535 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_S 4 536 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_M \ 537 0x0000000C 538 539 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_S 2 540 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_uv_prot_lowv \ 541 0x00000002 542 543 #define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ov_prot_lowv \ 544 0x00000001 545 546 //****************************************************************************** 547 // 548 // The following are defines for the bit fields in the 549 // HIB1P2_O_DIG_DCDC_PARAMETERS4 register. 550 // 551 //****************************************************************************** 552 #define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_uv_prot_out_lowv \ 553 0x80000000 554 555 #define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_ov_prot_out_lowv \ 556 0x40000000 557 558 #define HIB1P2_DIG_DCDC_PARAMETERS4_mem_dcdc_dig_en_tmux_lowv \ 559 0x20000000 560 561 #define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_M \ 562 0x1FFFFFFF 563 564 #define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_S 0 565 //****************************************************************************** 566 // 567 // The following are defines for the bit fields in the 568 // HIB1P2_O_DIG_DCDC_PARAMETERS5 register. 569 // 570 //****************************************************************************** 571 #define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_M \ 572 0xFFFFFFFF 573 574 #define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_S 0 575 //****************************************************************************** 576 // 577 // The following are defines for the bit fields in the 578 // HIB1P2_O_DIG_DCDC_PARAMETERS6 register. 579 // 580 //****************************************************************************** 581 #define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_M \ 582 0xFFFFFFFF 583 584 #define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_S 0 585 //****************************************************************************** 586 // 587 // The following are defines for the bit fields in the 588 // HIB1P2_O_ANA_DCDC_PARAMETERS0 register. 589 // 590 //****************************************************************************** 591 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_lowv_override \ 592 0x80000000 // Override for ANA DCDC EN 593 594 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_delayed_en_lowv \ 595 0x40000000 596 597 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p8v_lowv \ 598 0x20000000 599 600 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p2v_lowv \ 601 0x10000000 602 603 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pwm_mode_lowv_override \ 604 0x08000000 // Override for ANA DCDC PWM 605 606 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_slp_mode_lowv_override \ 607 0x04000000 // Override for ANA DCDC SLP 608 609 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_ldo_mode_lowv \ 610 0x02000000 611 612 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pfet_rds_mode_lowv \ 613 0x01000000 614 615 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_nfet_rds_mode_lowv \ 616 0x00800000 617 618 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_ext_smps_override_mode_lowv \ 619 0x00400000 620 621 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_clk_in_lowv_enable \ 622 0x00200000 623 624 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_M \ 625 0x001E0000 626 627 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_S 17 628 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_M \ 629 0x00018000 630 631 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_S 15 632 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_M \ 633 0x00006000 634 635 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_S 13 636 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_cl_non_ov_lowv \ 637 0x00001000 638 639 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_M \ 640 0x00000F00 641 642 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_S 8 643 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_M \ 644 0x000000F0 645 646 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_S 4 647 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_M \ 648 0x0000000F 649 650 #define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_S 0 651 //****************************************************************************** 652 // 653 // The following are defines for the bit fields in the 654 // HIB1P2_O_ANA_DCDC_PARAMETERS1 register. 655 // 656 //****************************************************************************** 657 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_M \ 658 0xF0000000 659 660 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_S 28 661 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_M \ 662 0x0C000000 663 664 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_S 26 665 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_M \ 666 0x03000000 667 668 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_S 24 669 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_M \ 670 0x00F00000 671 672 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_S 20 673 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_M \ 674 0x000F0000 675 676 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_S 16 677 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_rtrim_lowv \ 678 0x00008000 // (Earlier SHOOTTHRU CTRL) 679 680 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_apwm_en_lowv \ 681 0x00004000 682 683 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_M \ 684 0x00003E00 685 686 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_S 9 687 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_anti_glitch_lowv \ 688 0x00000100 689 690 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_hi_clamp_lowv \ 691 0x00000080 692 693 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_M \ 694 0x00000060 695 696 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_S 5 697 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_lo_clamp_lowv \ 698 0x00000010 699 700 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_M \ 701 0x0000000C 702 703 #define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_S 2 704 #define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_M \ 705 0x00000003 706 707 #define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_S 0 708 //****************************************************************************** 709 // 710 // The following are defines for the bit fields in the 711 // HIB1P2_O_ANA_DCDC_PARAMETERS16 register. 712 // 713 //****************************************************************************** 714 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_lowv \ 715 0x00200000 716 717 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_hib_lowv \ 718 0x00100000 719 720 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_M \ 721 0x000FF000 722 723 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_S 12 724 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_M \ 725 0x00000C00 726 727 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_S 10 728 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_lowv \ 729 0x00000200 730 731 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_hib_lowv \ 732 0x00000100 733 734 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_M \ 735 0x000000F8 736 737 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_S 3 738 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_M \ 739 0x00000006 740 741 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_S 1 742 #define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ov_prot_lowv \ 743 0x00000001 744 745 //****************************************************************************** 746 // 747 // The following are defines for the bit fields in the 748 // HIB1P2_O_ANA_DCDC_PARAMETERS17 register. 749 // 750 //****************************************************************************** 751 #define HIB1P2_ANA_DCDC_PARAMETERS17_dcdc_ana_ov_prot_out_lowv \ 752 0x80000000 753 754 #define HIB1P2_ANA_DCDC_PARAMETERS17_mem_dcdc_ana_en_tmux_lowv \ 755 0x40000000 756 757 #define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_M \ 758 0x3FFFFFFF 759 760 #define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_S 0 761 //****************************************************************************** 762 // 763 // The following are defines for the bit fields in the 764 // HIB1P2_O_ANA_DCDC_PARAMETERS18 register. 765 // 766 //****************************************************************************** 767 #define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_M \ 768 0xFFFFFFFF 769 770 #define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_S 0 771 //****************************************************************************** 772 // 773 // The following are defines for the bit fields in the 774 // HIB1P2_O_ANA_DCDC_PARAMETERS19 register. 775 // 776 //****************************************************************************** 777 #define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_M \ 778 0xFFFFFFFF 779 780 #define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_S 0 781 //****************************************************************************** 782 // 783 // The following are defines for the bit fields in the 784 // HIB1P2_O_FLASH_DCDC_PARAMETERS0 register. 785 // 786 //****************************************************************************** 787 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_lowv \ 788 0x80000000 789 790 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_delayed_en_lowv \ 791 0x40000000 792 793 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_clk_in_lowv_enable \ 794 0x20000000 795 796 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_M \ 797 0x18000000 798 799 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_S 27 800 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_mode_lowv \ 801 0x04000000 802 803 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_boost_mode_lowv \ 804 0x02000000 805 806 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_boost_mode_lowv \ 807 0x01000000 808 809 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_bb_alt_cycles_lowv \ 810 0x00800000 811 812 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_cl_non_ov_lowv \ 813 0x00400000 814 815 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_M \ 816 0x003C0000 817 818 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_S 18 819 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_drv_lowv \ 820 0x00020000 821 822 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pwm_mode_lowv \ 823 0x00010000 824 825 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pfm_comp_lowv \ 826 0x00008000 827 828 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_slp_mode_lowv \ 829 0x00004000 830 831 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n1fet_rds_mode_lowv \ 832 0x00002000 833 834 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n2fet_rds_mode_lowv \ 835 0x00001000 836 837 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p1fet_rds_mode_lowv \ 838 0x00000800 839 840 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p2fet_rds_mode_lowv \ 841 0x00000400 842 843 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_ext_smps_mode_override_lowv \ 844 0x00000200 845 846 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_M \ 847 0x000001E0 848 849 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_S 5 850 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_M \ 851 0x0000001E 852 853 #define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_S 1 854 #define HIB1P2_FLASH_DCDC_PARAMETERS0_NA18 \ 855 0x00000001 856 857 //****************************************************************************** 858 // 859 // The following are defines for the bit fields in the 860 // HIB1P2_O_FLASH_DCDC_PARAMETERS1 register. 861 // 862 //****************************************************************************** 863 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_M \ 864 0xF0000000 865 866 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_S 28 867 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_M \ 868 0x0F000000 869 870 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_S 24 871 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_M \ 872 0x00F00000 873 874 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_S 20 875 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_M \ 876 0x000F0000 877 878 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_S 16 879 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_M \ 880 0x0000F000 881 882 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_S 12 883 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_M \ 884 0x00000F00 885 886 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_S 8 887 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_M \ 888 0x000000C0 889 890 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_S 6 891 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_M \ 892 0x00000030 893 894 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_S 4 895 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_M \ 896 0x0000000C 897 898 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_S 2 899 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_M \ 900 0x00000003 901 902 #define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_S 0 903 //****************************************************************************** 904 // 905 // The following are defines for the bit fields in the 906 // HIB1P2_O_FLASH_DCDC_PARAMETERS2 register. 907 // 908 //****************************************************************************** 909 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_M \ 910 0xC0000000 911 912 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_S 30 913 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_M \ 914 0x30000000 915 916 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_S 28 917 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_M \ 918 0x0C000000 919 920 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_S 26 921 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_M \ 922 0x03000000 923 924 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_S 24 925 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_shoot_thru_ctrl_lowv \ 926 0x00800000 927 928 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_lowv \ 929 0x00400000 930 931 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_hib_lowv \ 932 0x00200000 933 934 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_M \ 935 0x001F0000 936 937 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_S 16 938 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_M \ 939 0x0000F000 940 941 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_S 12 942 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_lowv \ 943 0x00000800 944 945 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_hib_lowv \ 946 0x00000400 947 948 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_M \ 949 0x000003FC 950 951 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_S 2 952 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_M \ 953 0x00000003 954 955 #define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_S 0 956 //****************************************************************************** 957 // 958 // The following are defines for the bit fields in the 959 // HIB1P2_O_FLASH_DCDC_PARAMETERS3 register. 960 // 961 //****************************************************************************** 962 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_anti_glitch_lowv \ 963 0x80000000 964 965 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_hi_clamp_lowv \ 966 0x40000000 967 968 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_lo_clamp_lowv \ 969 0x20000000 970 971 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_M \ 972 0x1F000000 973 974 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_S 24 975 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_M \ 976 0x00E00000 977 978 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_S 21 979 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_M \ 980 0x001C0000 981 982 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_S 18 983 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_M \ 984 0x0003C000 985 986 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_S 14 987 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_M \ 988 0x00003C00 989 990 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_S 10 991 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_M \ 992 0x00000300 993 994 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_S 8 995 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_ov_prot_lowv \ 996 0x00000080 997 998 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_uv_prot_lowv \ 999 0x00000040 1000 1001 #define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_tmux_lowv \ 1002 0x00000020 1003 1004 #define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_M \ 1005 0x0000001F 1006 1007 #define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_S 0 1008 //****************************************************************************** 1009 // 1010 // The following are defines for the bit fields in the 1011 // HIB1P2_O_FLASH_DCDC_PARAMETERS4 register. 1012 // 1013 //****************************************************************************** 1014 #define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_M \ 1015 0xFFFFFFFF 1016 1017 #define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_S 0 1018 //****************************************************************************** 1019 // 1020 // The following are defines for the bit fields in the 1021 // HIB1P2_O_FLASH_DCDC_PARAMETERS5 register. 1022 // 1023 //****************************************************************************** 1024 #define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_M \ 1025 0xFFFFFFFF 1026 1027 #define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_S 0 1028 //****************************************************************************** 1029 // 1030 // The following are defines for the bit fields in the 1031 // HIB1P2_O_FLASH_DCDC_PARAMETERS6 register. 1032 // 1033 //****************************************************************************** 1034 #define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_ov_prot_out_lowv \ 1035 0x80000000 1036 1037 #define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_uv_prot_out_lowv \ 1038 0x40000000 1039 1040 #define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_M \ 1041 0x3FFFFFFF 1042 1043 #define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_S 0 1044 //****************************************************************************** 1045 // 1046 // The following are defines for the bit fields in the 1047 // HIB1P2_O_PMBIST_PARAMETERS0 register. 1048 // 1049 //****************************************************************************** 1050 #define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_en_lowv \ 1051 0x80000000 1052 1053 #define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_M \ 1054 0x7FFFF800 1055 1056 #define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_S 11 1057 #define HIB1P2_PMBIST_PARAMETERS0_NA21_M \ 1058 0x000007FF 1059 1060 #define HIB1P2_PMBIST_PARAMETERS0_NA21_S 0 1061 //****************************************************************************** 1062 // 1063 // The following are defines for the bit fields in the 1064 // HIB1P2_O_PMBIST_PARAMETERS1 register. 1065 // 1066 //****************************************************************************** 1067 #define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_M \ 1068 0xFFFF0000 1069 1070 #define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_S 16 1071 #define HIB1P2_PMBIST_PARAMETERS1_mem_pmtest_en_lowv \ 1072 0x00008000 1073 1074 #define HIB1P2_PMBIST_PARAMETERS1_NA22_M \ 1075 0x00007FFF 1076 1077 #define HIB1P2_PMBIST_PARAMETERS1_NA22_S 0 1078 //****************************************************************************** 1079 // 1080 // The following are defines for the bit fields in the 1081 // HIB1P2_O_PMBIST_PARAMETERS2 register. 1082 // 1083 //****************************************************************************** 1084 #define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_M \ 1085 0xFFFFFFFF 1086 1087 #define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_S 0 1088 //****************************************************************************** 1089 // 1090 // The following are defines for the bit fields in the 1091 // HIB1P2_O_PMBIST_PARAMETERS3 register. 1092 // 1093 //****************************************************************************** 1094 #define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_M \ 1095 0xFFFF0000 1096 1097 #define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_S 16 1098 #define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_M \ 1099 0x0000E000 1100 1101 #define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_S 13 1102 #define HIB1P2_PMBIST_PARAMETERS3_mem_rnwell_calib_en_lowv \ 1103 0x00001000 1104 1105 #define HIB1P2_PMBIST_PARAMETERS3_NA23_M \ 1106 0x00000FFF 1107 1108 #define HIB1P2_PMBIST_PARAMETERS3_NA23_S 0 1109 //****************************************************************************** 1110 // 1111 // The following are defines for the bit fields in the 1112 // HIB1P2_O_FLASH_DCDC_PARAMETERS8 register. 1113 // 1114 //****************************************************************************** 1115 #define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_en_flash_sup_comp_lowv \ 1116 0x80000000 1117 1118 #define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_M \ 1119 0x7C000000 1120 1121 #define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_S 26 1122 #define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_M \ 1123 0x03E00000 1124 1125 #define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_S 21 1126 #define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_M \ 1127 0x001FFFFF 1128 1129 #define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_S 0 1130 //****************************************************************************** 1131 // 1132 // The following are defines for the bit fields in the 1133 // HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE register. 1134 // 1135 //****************************************************************************** 1136 #define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_M \ 1137 0xFFFFFFC0 1138 1139 #define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_S 6 1140 #define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p2v_lowv_override_ctrl \ 1141 0x00000020 1142 1143 #define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p8v_lowv_override_ctrl \ 1144 0x00000010 1145 1146 #define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_ilim_trim_lowv_efc_override_ctrl \ 1147 0x00000008 1148 1149 #define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_slp_mode_lowv_fsm_override_ctrl \ 1150 0x00000004 1151 1152 #define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_pwm_mode_lowv_fsm_override_ctrl \ 1153 0x00000002 1154 1155 #define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_lowv_fsm_override_ctrl \ 1156 0x00000001 1157 1158 //****************************************************************************** 1159 // 1160 // The following are defines for the bit fields in the 1161 // HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE register. 1162 // 1163 //****************************************************************************** 1164 #define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_M \ 1165 0xFFFFFFFC 1166 1167 #define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_S 2 1168 #define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_en_lowv_override_ctrl \ 1169 0x00000002 1170 1171 #define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_ilim_trim_lowv_override_ctrl \ 1172 0x00000001 1173 1174 //****************************************************************************** 1175 // 1176 // The following are defines for the bit fields in the 1177 // HIB1P2_O_DIG_DCDC_VTRIM_CFG register. 1178 // 1179 //****************************************************************************** 1180 #define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_M \ 1181 0xFF000000 1182 1183 #define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_S 24 1184 #define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_M \ 1185 0x00FC0000 1186 1187 #define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_S 18 1188 #define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_M \ 1189 0x0003F000 1190 1191 #define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_S 12 1192 #define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_M \ 1193 0x00000FC0 1194 1195 #define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_S 6 1196 #define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_M \ 1197 0x0000003F 1198 1199 #define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_S 0 1200 //****************************************************************************** 1201 // 1202 // The following are defines for the bit fields in the 1203 // HIB1P2_O_DIG_DCDC_FSM_PARAMETERS register. 1204 // 1205 //****************************************************************************** 1206 #define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_M \ 1207 0xFFFF8000 1208 1209 #define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_S 15 1210 #define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_M \ 1211 0x00007000 1212 1213 #define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_S 12 1214 #define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_M \ 1215 0x00000E00 1216 1217 #define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_S 9 1218 #define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_M \ 1219 0x000001C0 1220 1221 #define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_S 6 1222 #define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_M \ 1223 0x00000038 1224 1225 #define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_S 3 1226 #define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_M \ 1227 0x00000007 1228 1229 #define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_S 0 1230 //****************************************************************************** 1231 // 1232 // The following are defines for the bit fields in the 1233 // HIB1P2_O_ANA_DCDC_FSM_PARAMETERS register. 1234 // 1235 //****************************************************************************** 1236 #define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_M \ 1237 0xFFFFFFF8 1238 1239 #define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_S 3 1240 #define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_M \ 1241 0x00000007 1242 1243 #define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_S 0 1244 //****************************************************************************** 1245 // 1246 // The following are defines for the bit fields in the 1247 // HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS register. 1248 // 1249 //****************************************************************************** 1250 #define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_M \ 1251 0xFFFFFFC0 1252 1253 #define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_S 6 1254 #define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_M \ 1255 0x00000038 1256 1257 #define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_S 3 1258 #define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_M \ 1259 0x00000007 1260 1261 #define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_S 0 1262 //****************************************************************************** 1263 // 1264 // The following are defines for the bit fields in the 1265 // HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG register. 1266 // 1267 //****************************************************************************** 1268 #define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_M \ 1269 0xFFFFFFF8 1270 1271 #define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_S 3 1272 #define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_M \ 1273 0x00000007 1274 1275 #define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_S 0 1276 //****************************************************************************** 1277 // 1278 // The following are defines for the bit fields in the 1279 // HIB1P2_O_CM_OSC_16M_CONFIG register. 1280 // 1281 //****************************************************************************** 1282 #define HIB1P2_CM_OSC_16M_CONFIG_reserved_M \ 1283 0xFFFC0000 1284 1285 #define HIB1P2_CM_OSC_16M_CONFIG_reserved_S 18 1286 #define HIB1P2_CM_OSC_16M_CONFIG_cm_clk_good_16m \ 1287 0x00020000 1288 1289 #define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_en_osc_16m \ 1290 0x00010000 1291 1292 #define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_M \ 1293 0x0000FC00 1294 1295 #define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_S 10 1296 #define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_M \ 1297 0x000003F0 1298 1299 #define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_S 4 1300 #define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_en_sli_16m \ 1301 0x00000008 1302 1303 #define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_M \ 1304 0x00000007 1305 1306 #define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_S 0 1307 //****************************************************************************** 1308 // 1309 // The following are defines for the bit fields in the 1310 // HIB1P2_O_SOP_SENSE_VALUE register. 1311 // 1312 //****************************************************************************** 1313 #define HIB1P2_SOP_SENSE_VALUE_reserved_M \ 1314 0xFFFFFF00 1315 1316 #define HIB1P2_SOP_SENSE_VALUE_reserved_S 8 1317 #define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_M \ 1318 0x000000FF 1319 1320 #define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_S 0 1321 //****************************************************************************** 1322 // 1323 // The following are defines for the bit fields in the 1324 // HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 register. 1325 // 1326 //****************************************************************************** 1327 #define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_M \ 1328 0xFFFFFFFF 1329 1330 #define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_S 0 1331 //****************************************************************************** 1332 // 1333 // The following are defines for the bit fields in the 1334 // HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 register. 1335 // 1336 //****************************************************************************** 1337 #define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_M \ 1338 0x0000FFFF 1339 1340 #define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_S 0 1341 //****************************************************************************** 1342 // 1343 // The following are defines for the bit fields in the 1344 // HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES register. 1345 // 1346 //****************************************************************************** 1347 #define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_M \ 1348 0xFF800000 1349 1350 #define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_S 23 1351 #define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_ctrl \ 1352 0x00400000 1353 1354 #define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_M \ 1355 0x003FC000 1356 1357 #define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_S 14 1358 #define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_ctrl \ 1359 0x00002000 1360 1361 #define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_M \ 1362 0x00001FC0 1363 1364 #define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_S 6 1365 #define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_ctrl \ 1366 0x00000020 1367 1368 #define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_M \ 1369 0x0000001F 1370 1371 #define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_S 0 1372 //****************************************************************************** 1373 // 1374 // The following are defines for the bit fields in the 1375 // HIB1P2_O_HIB1P2_EFUSE_READ_REG0 register. 1376 // 1377 //****************************************************************************** 1378 #define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_M \ 1379 0xFFFFFFFF // Corresponds to ROW_12 of 1380 // FUSEFARM. [7:0] : 1381 // DCDC_DIG_ILIM_TRIM_LOWV(7:0) 1382 // [15:8] : 1383 // DCDC_ANA_ILIM_TRIM_LOWV(7:0) 1384 // [23:16] : 1385 // DCDC_FLASH_ILIM_TRIM_LOWV(7:0) 1386 // [24:24] : DTHE SHA DISABLE 1387 // [25:25] : DTHE DES DISABLE 1388 // [26:26] : DTHE AES DISABLE 1389 // [31:27] : HD_BG_RTRIM (4:0) 1390 1391 #define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_S 0 1392 //****************************************************************************** 1393 // 1394 // The following are defines for the bit fields in the 1395 // HIB1P2_O_HIB1P2_EFUSE_READ_REG1 register. 1396 // 1397 //****************************************************************************** 1398 #define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_M \ 1399 0xFFFFFFFF // Corresponds to ROW_13 of the 1400 // FUSEFARM. [7:0] : HD_BG_MAG_TRIM 1401 // (7:0) [14:8] : HD_BG_TEMP_TRIM 1402 // (6:0) [15:15] : GREYOUT ENABLE 1403 // DUTY CYCLING [31:16] : 1404 // Reserved/Checksum 1405 1406 #define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_S 0 1407 //****************************************************************************** 1408 // 1409 // The following are defines for the bit fields in the 1410 // HIB1P2_O_HIB1P2_POR_TEST_CTRL register. 1411 // 1412 //****************************************************************************** 1413 #define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_M \ 1414 0xFFFFFF00 1415 1416 #define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_S 8 1417 #define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_M \ 1418 0x000000FF 1419 1420 #define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_S 0 1421 //****************************************************************************** 1422 // 1423 // The following are defines for the bit fields in the 1424 // HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 register. 1425 // 1426 //****************************************************************************** 1427 #define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_M \ 1428 0xFFFF0000 1429 1430 #define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_S 16 1431 #define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_M \ 1432 0x0000FF00 1433 1434 #define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_S 8 1435 #define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_M \ 1436 0x000000FE 1437 1438 #define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_S 1 1439 #define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_start \ 1440 0x00000001 1441 1442 //****************************************************************************** 1443 // 1444 // The following are defines for the bit fields in the 1445 // HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 register. 1446 // 1447 //****************************************************************************** 1448 #define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_M \ 1449 0xFFF00000 1450 1451 #define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_S 20 1452 #define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_M \ 1453 0x000FFFFF 1454 1455 #define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_S 0 1456 //****************************************************************************** 1457 // 1458 // The following are defines for the bit fields in the 1459 // HIB1P2_O_HIB_TIMER_SYNC_CFG2 register. 1460 // 1461 //****************************************************************************** 1462 #define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_M \ 1463 0xFFFFFE00 1464 1465 #define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_S 9 1466 #define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_hib_unload \ 1467 0x00000100 1468 1469 #define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_M \ 1470 0x000000FC 1471 1472 #define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_S 2 1473 #define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_tsf_adj \ 1474 0x00000002 1475 1476 #define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_update_tsf \ 1477 0x00000001 1478 1479 //****************************************************************************** 1480 // 1481 // The following are defines for the bit fields in the 1482 // HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL register. 1483 // 1484 //****************************************************************************** 1485 #define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_M \ 1486 0xFFFFFFFF 1487 1488 #define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_S 0 1489 //****************************************************************************** 1490 // 1491 // The following are defines for the bit fields in the 1492 // HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW register. 1493 // 1494 //****************************************************************************** 1495 #define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_M \ 1496 0xFFFFFFFF 1497 1498 #define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_S 0 1499 //****************************************************************************** 1500 // 1501 // The following are defines for the bit fields in the 1502 // HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW register. 1503 // 1504 //****************************************************************************** 1505 #define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_M \ 1506 0xFFFF0000 1507 1508 #define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_S 16 1509 #define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_M \ 1510 0x0000FFFF 1511 1512 #define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_S 0 1513 //****************************************************************************** 1514 // 1515 // The following are defines for the bit fields in the 1516 // HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW register. 1517 // 1518 //****************************************************************************** 1519 #define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_M \ 1520 0xFFFFFFFF 1521 1522 #define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_S 0 1523 //****************************************************************************** 1524 // 1525 // The following are defines for the bit fields in the 1526 // HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW register. 1527 // 1528 //****************************************************************************** 1529 #define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_M \ 1530 0xFFFF0000 1531 1532 #define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_S 16 1533 #define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_M \ 1534 0x0000FFFF 1535 1536 #define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_S 0 1537 //****************************************************************************** 1538 // 1539 // The following are defines for the bit fields in the 1540 // HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR register. 1541 // 1542 //****************************************************************************** 1543 #define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_M \ 1544 0xFFFFF000 1545 1546 #define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_S 12 1547 #define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_M \ 1548 0x00000FFF 1549 1550 #define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_S 0 1551 //****************************************************************************** 1552 // 1553 // The following are defines for the bit fields in the 1554 // HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW register. 1555 // 1556 //****************************************************************************** 1557 #define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_M \ 1558 0xFFFFFFFF 1559 1560 #define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_S 0 1561 //****************************************************************************** 1562 // 1563 // The following are defines for the bit fields in the 1564 // HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW register. 1565 // 1566 //****************************************************************************** 1567 #define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_M \ 1568 0xFFFFFFFF 1569 1570 #define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_S 0 1571 //****************************************************************************** 1572 // 1573 // The following are defines for the bit fields in the HIB1P2_O_CM_SPARE register. 1574 // 1575 //****************************************************************************** 1576 #define HIB1P2_CM_SPARE_CM_SPARE_OUT_M \ 1577 0xFF000000 1578 1579 #define HIB1P2_CM_SPARE_CM_SPARE_OUT_S 24 1580 #define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_M \ 1581 0x00FF0000 1582 1583 #define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_S 16 1584 #define HIB1P2_CM_SPARE_MEM_CM_SPARE_M \ 1585 0x0000FFFF 1586 1587 #define HIB1P2_CM_SPARE_MEM_CM_SPARE_S 0 1588 //****************************************************************************** 1589 // 1590 // The following are defines for the bit fields in the 1591 // HIB1P2_O_PORPOL_SPARE register. 1592 // 1593 //****************************************************************************** 1594 #define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_M \ 1595 0xFFFFFFFF 1596 1597 #define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_S 0 1598 //****************************************************************************** 1599 // 1600 // The following are defines for the bit fields in the 1601 // HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG register. 1602 // 1603 //****************************************************************************** 1604 #define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_ENABLE \ 1605 0x00000100 1606 1607 #define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_M \ 1608 0x000000F0 1609 1610 #define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_S 4 1611 #define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_M \ 1612 0x0000000F 1613 1614 #define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_S 0 1615 //****************************************************************************** 1616 // 1617 // The following are defines for the bit fields in the 1618 // HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG register. 1619 // 1620 //****************************************************************************** 1621 #define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_ENABLE \ 1622 0x00000100 1623 1624 #define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_M \ 1625 0x000000F0 1626 1627 #define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 1628 #define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_M \ 1629 0x0000000F 1630 1631 #define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_S 0 1632 //****************************************************************************** 1633 // 1634 // The following are defines for the bit fields in the 1635 // HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG register. 1636 // 1637 //****************************************************************************** 1638 #define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_ENABLE \ 1639 0x00000100 1640 1641 #define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_M \ 1642 0x000000F0 1643 1644 #define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_S 4 1645 #define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_M \ 1646 0x0000000F 1647 1648 #define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_S 0 1649 //****************************************************************************** 1650 // 1651 // The following are defines for the bit fields in the 1652 // HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG register. 1653 // 1654 //****************************************************************************** 1655 #define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_ENABLE \ 1656 0x00000100 1657 1658 #define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_M \ 1659 0x000000F0 1660 1661 #define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 1662 #define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_M \ 1663 0x0000000F 1664 1665 #define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_S 0 1666 //****************************************************************************** 1667 // 1668 // The following are defines for the bit fields in the 1669 // HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE register. 1670 // 1671 //****************************************************************************** 1672 #define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE_CTRL \ 1673 0x00000002 1674 1675 #define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE \ 1676 0x00000001 1677 1678 //****************************************************************************** 1679 // 1680 // The following are defines for the bit fields in the 1681 // HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE register. 1682 // 1683 //****************************************************************************** 1684 #define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE_CTRL \ 1685 0x00000002 1686 1687 #define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE \ 1688 0x00000001 1689 1690 //****************************************************************************** 1691 // 1692 // The following are defines for the bit fields in the 1693 // HIB1P2_O_MEM_HIB_FSM_DEBUG register. 1694 // 1695 //****************************************************************************** 1696 #define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_M \ 1697 0x00000700 1698 1699 #define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_S 8 1700 #define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_M \ 1701 0x000000F0 1702 1703 #define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_S 4 1704 #define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_M \ 1705 0x0000000F 1706 1707 #define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_S 0 1708 //****************************************************************************** 1709 // 1710 // The following are defines for the bit fields in the 1711 // HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL register. 1712 // 1713 //****************************************************************************** 1714 #define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_M \ 1715 0x000FFFFF 1716 1717 #define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_S 0 1718 //****************************************************************************** 1719 // 1720 // The following are defines for the bit fields in the 1721 // HIB1P2_O_MEM_SLDO_WEAK_PROCESS register. 1722 // 1723 //****************************************************************************** 1724 #define HIB1P2_MEM_SLDO_WEAK_PROCESS_MEM_SLDO_WEAK_PROCESS \ 1725 0x00000001 1726 1727 //****************************************************************************** 1728 // 1729 // The following are defines for the bit fields in the 1730 // HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS register. 1731 // 1732 //****************************************************************************** 1733 #define HIB1P2_MEM_PA_DCDC_OV_UV_STATUS_dcdc_pa_ov_prot_out_lowv \ 1734 0x00000002 1735 1736 //****************************************************************************** 1737 // 1738 // The following are defines for the bit fields in the 1739 // HIB1P2_O_MEM_CM_TEST_MODE register. 1740 // 1741 //****************************************************************************** 1742 #define HIB1P2_MEM_CM_TEST_MODE_mem_cm_test_mode \ 1743 0x00000001 1744 1745 1746 1747 1748 #endif // __HW_HIB1P2_H__ 1749
