1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_GPRCM_H__ 35 #define __HW_GPRCM_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the GPRCM register offsets. 40 // 41 //***************************************************************************** 42 #define GPRCM_O_APPS_SOFT_RESET 0x00000000 43 #define GPRCM_O_APPS_LPDS_WAKEUP_CFG \ 44 0x00000004 45 46 #define GPRCM_O_APPS_LPDS_WAKEUP_SRC \ 47 0x00000008 48 49 #define GPRCM_O_APPS_RESET_CAUSE \ 50 0x0000000C 51 52 #define GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG \ 53 0x00000010 54 55 #define GPRCM_O_APPS_SRAM_DSLP_CFG \ 56 0x00000018 57 58 #define GPRCM_O_APPS_SRAM_LPDS_CFG \ 59 0x0000001C 60 61 #define GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG \ 62 0x00000020 63 64 #define GPRCM_O_TOP_DIE_ENABLE 0x00000100 65 #define GPRCM_O_TOP_DIE_ENABLE_PARAMETERS \ 66 0x00000104 67 68 #define GPRCM_O_MCU_GLOBAL_SOFT_RESET \ 69 0x00000108 70 71 #define GPRCM_O_ADC_CLK_CONFIG 0x0000010C 72 #define GPRCM_O_APPS_GPIO_WAKE_CONF \ 73 0x00000110 74 75 #define GPRCM_O_EN_NWP_BOOT_WO_DEVINIT \ 76 0x00000114 77 78 #define GPRCM_O_MEM_HCLK_DIV_CFG \ 79 0x00000118 80 81 #define GPRCM_O_MEM_SYSCLK_DIV_CFG \ 82 0x0000011C 83 84 #define GPRCM_O_APLLMCS_LOCK_TIME_CONF \ 85 0x00000120 86 87 #define GPRCM_O_NWP_SOFT_RESET 0x00000400 88 #define GPRCM_O_NWP_LPDS_WAKEUP_CFG \ 89 0x00000404 90 91 #define GPRCM_O_NWP_LPDS_WAKEUP_SRC \ 92 0x00000408 93 94 #define GPRCM_O_NWP_RESET_CAUSE 0x0000040C 95 #define GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG \ 96 0x00000410 97 98 #define GPRCM_O_NWP_SRAM_DSLP_CFG \ 99 0x00000418 100 101 #define GPRCM_O_NWP_SRAM_LPDS_CFG \ 102 0x0000041C 103 104 #define GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG \ 105 0x00000420 106 107 #define GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL \ 108 0x00000424 109 110 #define GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ \ 111 0x00000428 112 113 #define GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST \ 114 0x0000042C 115 116 #define GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST \ 117 0x00000430 118 119 #define GPRCM_O_NWP_GPIO_WAKE_CONF \ 120 0x00000434 121 122 #define GPRCM_O_GPRCM_EFUSE_READ_REG12 \ 123 0x00000438 124 125 #define GPRCM_O_GPRCM_DIEID_READ_REG5 \ 126 0x00000448 127 128 #define GPRCM_O_GPRCM_DIEID_READ_REG6 \ 129 0x0000044C 130 131 #define GPRCM_O_REF_FSM_CFG0 0x00000800 132 #define GPRCM_O_REF_FSM_CFG1 0x00000804 133 #define GPRCM_O_APLLMCS_WLAN_CONFIG0_40 \ 134 0x00000808 135 136 #define GPRCM_O_APLLMCS_WLAN_CONFIG1_40 \ 137 0x0000080C 138 139 #define GPRCM_O_APLLMCS_WLAN_CONFIG0_26 \ 140 0x00000810 141 142 #define GPRCM_O_APLLMCS_WLAN_CONFIG1_26 \ 143 0x00000814 144 145 #define GPRCM_O_APLLMCS_WLAN_OVERRIDES \ 146 0x00000818 147 148 #define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 \ 149 0x0000081C 150 151 #define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 \ 152 0x00000820 153 154 #define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 \ 155 0x00000824 156 157 #define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 \ 158 0x00000828 159 160 #define GPRCM_O_SPARE_RW0 0x0000082C 161 #define GPRCM_O_SPARE_RW1 0x00000830 162 #define GPRCM_O_APLLMCS_MCU_OVERRIDES \ 163 0x00000834 164 165 #define GPRCM_O_SYSCLK_SWITCH_STATUS \ 166 0x00000838 167 168 #define GPRCM_O_REF_LDO_CONTROLS \ 169 0x0000083C 170 171 #define GPRCM_O_REF_RTRIM_CONTROL \ 172 0x00000840 173 174 #define GPRCM_O_REF_SLICER_CONTROLS0 \ 175 0x00000844 176 177 #define GPRCM_O_REF_SLICER_CONTROLS1 \ 178 0x00000848 179 180 #define GPRCM_O_REF_ANA_BGAP_CONTROLS0 \ 181 0x0000084C 182 183 #define GPRCM_O_REF_ANA_BGAP_CONTROLS1 \ 184 0x00000850 185 186 #define GPRCM_O_REF_ANA_SPARE_CONTROLS0 \ 187 0x00000854 188 189 #define GPRCM_O_REF_ANA_SPARE_CONTROLS1 \ 190 0x00000858 191 192 #define GPRCM_O_MEMSS_PSCON_OVERRIDES0 \ 193 0x0000085C 194 195 #define GPRCM_O_MEMSS_PSCON_OVERRIDES1 \ 196 0x00000860 197 198 #define GPRCM_O_PLL_REF_LOCK_OVERRIDES \ 199 0x00000864 200 201 #define GPRCM_O_MCU_PSCON_DEBUG 0x00000868 202 #define GPRCM_O_MEMSS_PWR_PS 0x0000086C 203 #define GPRCM_O_REF_FSM_DEBUG 0x00000870 204 #define GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE \ 205 0x00000874 206 207 #define GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG \ 208 0x00000878 209 210 #define GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES \ 211 0x0000087C 212 213 #define GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES \ 214 0x00000880 215 216 #define GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES \ 217 0x00000884 218 219 #define GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES \ 220 0x00000888 221 222 #define GPRCM_O_MEM_REF_FSM_CFG2 \ 223 0x0000088C 224 225 #define GPRCM_O_TESTCTRL_POWER_CTRL \ 226 0x00000C10 227 228 #define GPRCM_O_SSDIO_POWER_CTRL \ 229 0x00000C14 230 231 #define GPRCM_O_MCSPI_N1_POWER_CTRL \ 232 0x00000C18 233 234 #define GPRCM_O_WELP_POWER_CTRL 0x00000C1C 235 #define GPRCM_O_WL_SDIO_POWER_CTRL \ 236 0x00000C20 237 238 #define GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG \ 239 0x00000C24 240 241 #define GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG \ 242 0x00000C28 243 244 #define GPRCM_O_APPS_SECURE_INIT_DONE \ 245 0x00000C30 246 247 #define GPRCM_O_APPS_DEV_MODE_INIT_DONE \ 248 0x00000C34 249 250 #define GPRCM_O_EN_APPS_REBOOT 0x00000C38 251 #define GPRCM_O_MEM_APPS_PERIPH_PRESENT \ 252 0x00000C3C 253 254 #define GPRCM_O_MEM_NWP_PERIPH_PRESENT \ 255 0x00000C40 256 257 #define GPRCM_O_MEM_SHARED_PERIPH_PRESENT \ 258 0x00000C44 259 260 #define GPRCM_O_NWP_PWR_STATE 0x00000C48 261 #define GPRCM_O_APPS_PWR_STATE 0x00000C4C 262 #define GPRCM_O_MCU_PWR_STATE 0x00000C50 263 #define GPRCM_O_WTOP_PM_PS 0x00000C54 264 #define GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG \ 265 0x00000C58 266 267 #define GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG \ 268 0x00000C5C 269 270 #define GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG \ 271 0x00000C60 272 273 #define GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG \ 274 0x00000C64 275 276 #define GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG \ 277 0x00000C68 278 279 #define GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG \ 280 0x00000C6C 281 282 #define GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG \ 283 0x00000C70 284 285 #define GPRCM_O_GPRCM_EFUSE_READ_REG0 \ 286 0x00000C78 287 288 #define GPRCM_O_GPRCM_EFUSE_READ_REG1 \ 289 0x00000C7C 290 291 #define GPRCM_O_GPRCM_EFUSE_READ_REG2 \ 292 0x00000C80 293 294 #define GPRCM_O_GPRCM_EFUSE_READ_REG3 \ 295 0x00000C84 296 297 #define GPRCM_O_WTOP_MEM_RET_CFG \ 298 0x00000C88 299 300 #define GPRCM_O_COEX_CLK_SWALLOW_CFG0 \ 301 0x00000C8C 302 303 #define GPRCM_O_COEX_CLK_SWALLOW_CFG1 \ 304 0x00000C90 305 306 #define GPRCM_O_COEX_CLK_SWALLOW_CFG2 \ 307 0x00000C94 308 309 #define GPRCM_O_COEX_CLK_SWALLOW_ENABLE \ 310 0x00000C98 311 312 #define GPRCM_O_DCDC_CLK_GEN_CONFIG \ 313 0x00000C9C 314 315 #define GPRCM_O_GPRCM_EFUSE_READ_REG4 \ 316 0x00000CA0 317 318 #define GPRCM_O_GPRCM_EFUSE_READ_REG5 \ 319 0x00000CA4 320 321 #define GPRCM_O_GPRCM_EFUSE_READ_REG6 \ 322 0x00000CA8 323 324 #define GPRCM_O_GPRCM_EFUSE_READ_REG7 \ 325 0x00000CAC 326 327 #define GPRCM_O_GPRCM_EFUSE_READ_REG8 \ 328 0x00000CB0 329 330 #define GPRCM_O_GPRCM_EFUSE_READ_REG9 \ 331 0x00000CB4 332 333 #define GPRCM_O_GPRCM_EFUSE_READ_REG10 \ 334 0x00000CB8 335 336 #define GPRCM_O_GPRCM_EFUSE_READ_REG11 \ 337 0x00000CBC 338 339 #define GPRCM_O_GPRCM_DIEID_READ_REG0 \ 340 0x00000CC0 341 342 #define GPRCM_O_GPRCM_DIEID_READ_REG1 \ 343 0x00000CC4 344 345 #define GPRCM_O_GPRCM_DIEID_READ_REG2 \ 346 0x00000CC8 347 348 #define GPRCM_O_GPRCM_DIEID_READ_REG3 \ 349 0x00000CCC 350 351 #define GPRCM_O_GPRCM_DIEID_READ_REG4 \ 352 0x00000CD0 353 354 #define GPRCM_O_APPS_SS_OVERRIDES \ 355 0x00000CD4 356 357 #define GPRCM_O_NWP_SS_OVERRIDES \ 358 0x00000CD8 359 360 #define GPRCM_O_SHARED_SS_OVERRIDES \ 361 0x00000CDC 362 363 #define GPRCM_O_IDMEM_CORE_RST_OVERRIDES \ 364 0x00000CE0 365 366 #define GPRCM_O_TOP_DIE_FSM_OVERRIDES \ 367 0x00000CE4 368 369 #define GPRCM_O_MCU_PSCON_OVERRIDES \ 370 0x00000CE8 371 372 #define GPRCM_O_WTOP_PSCON_OVERRIDES \ 373 0x00000CEC 374 375 #define GPRCM_O_WELP_PSCON_OVERRIDES \ 376 0x00000CF0 377 378 #define GPRCM_O_WL_SDIO_PSCON_OVERRIDES \ 379 0x00000CF4 380 381 #define GPRCM_O_MCSPI_PSCON_OVERRIDES \ 382 0x00000CF8 383 384 #define GPRCM_O_SSDIO_PSCON_OVERRIDES \ 385 0x00000CFC 386 387 388 389 390 //****************************************************************************** 391 // 392 // The following are defines for the bit fields in the 393 // GPRCM_O_APPS_SOFT_RESET register. 394 // 395 //****************************************************************************** 396 #define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET1 \ 397 0x00000002 // Soft-reset1 for APPS : Cortex 398 // sysrstn is asserted and in 399 // addition to that the associated 400 // APPS Peripherals are also reset. 401 // This is an auto-clear bit. 402 403 #define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET0 \ 404 0x00000001 // Soft-reset0 for APPS : Only 405 // sys-resetn for Cortex will be 406 // asserted. This is an auto-clear 407 // bit. 408 409 //****************************************************************************** 410 // 411 // The following are defines for the bit fields in the 412 // GPRCM_O_APPS_LPDS_WAKEUP_CFG register. 413 // 414 //****************************************************************************** 415 #define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_M \ 416 0x000000FF // Mask for LPDS Wakeup interrupt : 417 // [7] - Host IRQ from NWP [6] - 418 // NWP_LPDS_Wake_irq (TRUE_LPDS) [5] 419 // - NWP Wake-request to APPS [4] - 420 // GPIO [3:1] - Reserved [0] - LPDS 421 // Wakeup-timer 422 423 #define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_S 0 424 //****************************************************************************** 425 // 426 // The following are defines for the bit fields in the 427 // GPRCM_O_APPS_LPDS_WAKEUP_SRC register. 428 // 429 //****************************************************************************** 430 #define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_M \ 431 0x000000FF // Indicates the cause for wakeup 432 // from LPDS : [7] - Host IRQ from 433 // NWP [6] - NWP_LPDS_Wake_irq 434 // (TRUE_LPDS) [5] - NWP 435 // Wake-request to APPS [4] - GPIO 436 // [3:1] - Reserved [0] - LPDS 437 // Wakeup-timer 438 439 #define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_S 0 440 //****************************************************************************** 441 // 442 // The following are defines for the bit fields in the 443 // GPRCM_O_APPS_RESET_CAUSE register. 444 // 445 //****************************************************************************** 446 #define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_M \ 447 0x000000FF // Indicates the reset cause for 448 // APPS : "0000" - Wake from HIB/OFF 449 // mode; "0001" - Wake from LPDS ; 450 // "0010" - Reserved ; "0011" - 451 // Soft-reset0 (Only APPS 452 // Cortex-sysrstn is asserted); 453 // "0100" - Soft-reset1 (APPS 454 // Cortex-sysrstn and APPS 455 // peripherals are reset); "0101" - 456 // WDOG0 (APPS Cortex-sysrstn and 457 // APPS peripherals are reset); 458 // "0110" - MCU Soft-reset (APPS + 459 // NWP Cortex-sysrstn + Peripherals 460 // are reset); "0111" - Secure Init 461 // done (Indication that reset has 462 // happened after DevInit); "1000" - 463 // Dev Mode Patch Init done (During 464 // development mode, patch 465 // downloading and Cortex 466 // re-vectoring is completed) 467 468 #define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_S 0 469 //****************************************************************************** 470 // 471 // The following are defines for the bit fields in the 472 // GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG register. 473 // 474 //****************************************************************************** 475 #define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_M \ 476 0xFFFFFFFF // OPP Request Configuration 477 // (Number of slow-clk cycles) for 478 // LPDS Wake-timer : This 479 // configuration implies the RTC 480 // time-stamp, which must be few 481 // slow-clks prior to 482 // APPS_LPDS_WAKETIME_WAKE_CFG, such 483 // that by the time actual wakeup is 484 // given, OPP is already switched to 485 // ACTIVE (RUN). 486 487 #define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_S 0 488 //****************************************************************************** 489 // 490 // The following are defines for the bit fields in the 491 // GPRCM_O_APPS_SRAM_DSLP_CFG register. 492 // 493 //****************************************************************************** 494 #define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_M \ 495 0x000FFFFF // Configuration of APPS Memories 496 // during Deep-sleep : 0 - SRAMs are 497 // OFF ; 1 - SRAMs are Retained. 498 // APPS SRAM Cluster information : 499 // [0] - 1st column in MEMSS 500 // (Applicable only when owned by 501 // APPS); [1] - 2nd column in MEMSS 502 // (Applicable only when owned by 503 // APPS); [2] - 3rd column in MEMSS 504 // (Applicable only when owned by 505 // APPS) ; [3] - 4th column in MEMSS 506 // (Applicable only when owned by 507 // APPS) ; [16] - MCU-PD - Apps 508 // cluster 0 (TBD); [19:18] - 509 // Reserved. 510 511 #define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_S 0 512 //****************************************************************************** 513 // 514 // The following are defines for the bit fields in the 515 // GPRCM_O_APPS_SRAM_LPDS_CFG register. 516 // 517 //****************************************************************************** 518 #define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_M \ 519 0x000FFFFF // Configuration of APPS Memories 520 // during LPDS : 0 - SRAMs are OFF ; 521 // 1 - SRAMs are Retained. APPS SRAM 522 // Cluster information : [0] - 1st 523 // column in MEMSS (Applicable only 524 // when owned by APPS); [1] - 2nd 525 // column in MEMSS (Applicable only 526 // when owned by APPS); [2] - 3rd 527 // column in MEMSS (Applicable only 528 // when owned by APPS) ; [3] - 4th 529 // column in MEMSS (Applicable only 530 // when owned by APPS) ; [16] - 531 // MCU-PD - Apps cluster 0 (TBD); 532 // [19:18] - Reserved. 533 534 #define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_S 0 535 //****************************************************************************** 536 // 537 // The following are defines for the bit fields in the 538 // GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG register. 539 // 540 //****************************************************************************** 541 #define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_M \ 542 0xFFFFFFFF // Configuration (in no of 543 // slow_clks) which says when the 544 // actual wakeup request for 545 // removing the PD-reset be given. 546 547 #define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_S 0 548 //****************************************************************************** 549 // 550 // The following are defines for the bit fields in the 551 // GPRCM_O_TOP_DIE_ENABLE register. 552 // 553 //****************************************************************************** 554 #define GPRCM_TOP_DIE_ENABLE_FLASH_BUSY \ 555 0x00001000 556 557 #define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_M \ 558 0x00000F00 559 560 #define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_S 8 561 #define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE_STATUS \ 562 0x00000002 // 1 - Top-die is enabled ; 563 564 #define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE \ 565 0x00000001 // 1 - Enable the top-die ; 0 - 566 // Disable the top-die 567 568 //****************************************************************************** 569 // 570 // The following are defines for the bit fields in the 571 // GPRCM_O_TOP_DIE_ENABLE_PARAMETERS register. 572 // 573 //****************************************************************************** 574 #define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_M \ 575 0xF0000000 // Configuration (in slow_clks) for 576 // number of clks between 577 // Flash-3p3-rstn to D2D POR Resetn. 578 579 #define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_S 28 580 #define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_M \ 581 0x00FF0000 // Configuration (in slow_clks) for 582 // number of clks between Top-die 583 // Switch-Enable and Top-die Flash 584 // 3p3 Reset removal 585 586 #define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_S 16 587 #define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_M \ 588 0x000000FF // Configuration (in slow_clks) for 589 // number of clks between D2D POR 590 // Reset removal and bottom die FMC 591 // reset removal 592 593 #define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_S 0 594 //****************************************************************************** 595 // 596 // The following are defines for the bit fields in the 597 // GPRCM_O_MCU_GLOBAL_SOFT_RESET register. 598 // 599 //****************************************************************************** 600 #define GPRCM_MCU_GLOBAL_SOFT_RESET_MCU_GLOBAL_SOFT_RESET \ 601 0x00000001 // 1 - Assert the global reset for 602 // MCU (APPS + NWP) ; Asserts both 603 // Cortex sysrstn and its 604 // peripherals 0 - Deassert the 605 // global reset for MCU (APPS + NWP) 606 // ; Asserts both Cortex sysrstn and 607 // its peripherals Note : Reset for 608 // shared peripherals is not 609 // affected here. 610 611 //****************************************************************************** 612 // 613 // The following are defines for the bit fields in the 614 // GPRCM_O_ADC_CLK_CONFIG register. 615 // 616 //****************************************************************************** 617 #define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_M \ 618 0x000007C0 // Configuration (in number of 38.4 619 // MHz clks) for the OFF-Time in 620 // generation of ADC_CLK 621 622 #define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_S 6 623 #define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_M \ 624 0x0000003E // Configuration (in number of 38.4 625 // MHz clks) for the ON-Time in 626 // generation of ADC_CLK 627 628 #define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_S 1 629 #define GPRCM_ADC_CLK_CONFIG_ADC_CLK_ENABLE \ 630 0x00000001 // 1 - Enable the ADC_CLK ; 0 - 631 // Disable the ADC_CLK 632 633 //****************************************************************************** 634 // 635 // The following are defines for the bit fields in the 636 // GPRCM_O_APPS_GPIO_WAKE_CONF register. 637 // 638 //****************************************************************************** 639 #define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_M \ 640 0x00000003 // "00" - Wake on Level0 on 641 // selected GPIO pin (GPIO is 642 // selected inside the HIB3p3 643 // module); "01" - Wakeup on 644 // fall-edge of GPIO pin. 645 646 #define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_S 0 647 //****************************************************************************** 648 // 649 // The following are defines for the bit fields in the 650 // GPRCM_O_EN_NWP_BOOT_WO_DEVINIT register. 651 // 652 //****************************************************************************** 653 #define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_M \ 654 0xFFFFFFFE 655 656 #define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_S 1 657 #define GPRCM_EN_NWP_BOOT_WO_DEVINIT_mem_en_nwp_boot_wo_devinit \ 658 0x00000001 // 1 - Override the secure-mode 659 // done for booting up NWP (Wakeup 660 // NWP on its event independent of 661 // CM4 state) ; 0 - Donot override 662 // the secure-mode done for NWP boot 663 // (NWP must be enabled by CM4 only) 664 665 //****************************************************************************** 666 // 667 // The following are defines for the bit fields in the 668 // GPRCM_O_MEM_HCLK_DIV_CFG register. 669 // 670 //****************************************************************************** 671 #define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_M \ 672 0x00000007 // Division configuration for 673 // HCLKDIVOUT : "000" - Divide by 1 674 // ; "001" - Divide by 2 ; "010" - 675 // Divide by 3 ; "011" - Divide by 4 676 // ; "100" - Divide by 5 ; "101" - 677 // Divide by 6 ; "110" - Divide by 7 678 // ; "111" - Divide by 8 679 680 #define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_S 0 681 //****************************************************************************** 682 // 683 // The following are defines for the bit fields in the 684 // GPRCM_O_MEM_SYSCLK_DIV_CFG register. 685 // 686 //****************************************************************************** 687 #define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_M \ 688 0x00000038 689 690 #define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_S 3 691 #define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_M \ 692 0x00000007 693 694 #define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_S 0 695 //****************************************************************************** 696 // 697 // The following are defines for the bit fields in the 698 // GPRCM_O_APLLMCS_LOCK_TIME_CONF register. 699 // 700 //****************************************************************************** 701 #define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_M \ 702 0x0000FF00 703 704 #define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_S 8 705 #define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_M \ 706 0x000000FF 707 708 #define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_S 0 709 //****************************************************************************** 710 // 711 // The following are defines for the bit fields in the 712 // GPRCM_O_NWP_SOFT_RESET register. 713 // 714 //****************************************************************************** 715 #define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET1 \ 716 0x00000002 // Soft-reset1 for NWP - Cortex 717 // sysrstn and NWP associated 718 // peripherals are - This is an 719 // auto-clr bit. 720 721 #define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET0 \ 722 0x00000001 // Soft-reset0 for NWP - Only 723 // Cortex-sysrstn is asserted - This 724 // is an auto-clear bit. 725 726 //****************************************************************************** 727 // 728 // The following are defines for the bit fields in the 729 // GPRCM_O_NWP_LPDS_WAKEUP_CFG register. 730 // 731 //****************************************************************************** 732 #define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_M \ 733 0x000000FF // Mask for LPDS Wakeup interrupt : 734 // 7 - WLAN Host Interrupt ; 6 - 735 // WLAN to NWP Wake request ; 5 - 736 // APPS to NWP Wake request; 4 - 737 // GPIO Wakeup ; 3 - Autonomous UART 738 // Wakeup ; 2 - SSDIO Wakeup ; 1 - 739 // Autonomous SPI Wakeup ; 0 - LPDS 740 // Wakeup-timer 741 742 #define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_S 0 743 //****************************************************************************** 744 // 745 // The following are defines for the bit fields in the 746 // GPRCM_O_NWP_LPDS_WAKEUP_SRC register. 747 // 748 //****************************************************************************** 749 #define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_M \ 750 0x000000FF // Indicates the cause for NWP 751 // LPDS-Wakeup : 7 - WLAN Host 752 // Interrupt ; 6 - WLAN to NWP Wake 753 // request ; 5 - APPS to NWP Wake 754 // request; 4 - GPIO Wakeup ; 3 - 755 // Autonomous UART Wakeup ; 2 - 756 // SSDIO Wakeup ; 1 - Autonomous SPI 757 // Wakeup ; 0 - LPDS Wakeup-timer 758 759 #define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_S 0 760 //****************************************************************************** 761 // 762 // The following are defines for the bit fields in the 763 // GPRCM_O_NWP_RESET_CAUSE register. 764 // 765 //****************************************************************************** 766 #define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_M \ 767 0x000000FF // Indicates the reset cause for 768 // NWP : "0000" - Wake from HIB/OFF 769 // mode; "0001" - Wake from LPDS ; 770 // "0010" - Reserved ; "0011" - 771 // Soft-reset0 (Only NWP 772 // Cortex-sysrstn is asserted); 773 // "0100" - Soft-reset1 (NWP 774 // Cortex-sysrstn and NWP 775 // peripherals are reset); "0101" - 776 // WDOG0 (NWP Cortex-sysrstn and NWP 777 // peripherals are reset); "0110" - 778 // MCU Soft-reset (APPS + NWP 779 // Cortex-sysrstn + Peripherals are 780 // reset); "0111" - SSDIO Function2 781 // reset (Only Cortex-sysrstn is 782 // asserted) ; "1000" - Reset due to 783 // WDOG of APPS (NWP Cortex-sysrstn 784 // and NWP peripherals are reset); 785 786 #define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_S 0 787 //****************************************************************************** 788 // 789 // The following are defines for the bit fields in the 790 // GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG register. 791 // 792 //****************************************************************************** 793 #define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_M \ 794 0xFFFFFFFF // OPP Request Configuration 795 // (Number of slow-clk cycles) for 796 // LPDS Wake-timer 797 798 #define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_S 0 799 //****************************************************************************** 800 // 801 // The following are defines for the bit fields in the 802 // GPRCM_O_NWP_SRAM_DSLP_CFG register. 803 // 804 //****************************************************************************** 805 #define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_M \ 806 0x000FFFFF // Configuration of NWP Memories 807 // during DSLP : 0 - SRAMs are OFF ; 808 // 1 - SRAMs are Retained. NWP SRAM 809 // Cluster information : [2] - 3rd 810 // column in MEMSS (Applicable only 811 // when owned by NWP) ; [3] - 4th 812 // column in MEMSS (Applicable only 813 // when owned by NWP) ; [4] - 5th 814 // column in MEMSS (Applicable only 815 // when owned by NWP) ; [5] - 6th 816 // column in MEMSS (Applicable only 817 // when owned by NWP) ; [6] - 7th 818 // column in MEMSS (Applicable only 819 // when owned by NWP) ; [7] - 8th 820 // column in MEMSS (Applicable only 821 // when owned by NWP) ; [8] - 9th 822 // column in MEMSS (Applicable only 823 // when owned by NWP) ; [9] - 10th 824 // column in MEMSS (Applicable only 825 // when owned by NWP) ; [10] - 11th 826 // column in MEMSS (Applicable only 827 // when owned by NWP) ; [11] - 12th 828 // column in MEMSS (Applicable only 829 // when owned by NWP) ; [12] - 13th 830 // column in MEMSS (Applicable only 831 // when owned by NWP) ; [13] - 14th 832 // column in MEMSS (Applicable only 833 // when owned by NWP) ; [14] - 15th 834 // column in MEMSS (Applicable only 835 // when owned by NWP) ; [19:18] - 836 // Reserved. 837 838 #define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_S 0 839 //****************************************************************************** 840 // 841 // The following are defines for the bit fields in the 842 // GPRCM_O_NWP_SRAM_LPDS_CFG register. 843 // 844 //****************************************************************************** 845 #define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_M \ 846 0x000FFFFF // Configuration of NWP Memories 847 // during LPDS : 0 - SRAMs are OFF ; 848 // 1 - SRAMs are Retained. NWP SRAM 849 // Cluster information : [2] - 3rd 850 // column in MEMSS (Applicable only 851 // when owned by NWP) ; [3] - 4th 852 // column in MEMSS (Applicable only 853 // when owned by NWP) ; [4] - 5th 854 // column in MEMSS (Applicable only 855 // when owned by NWP) ; [5] - 6th 856 // column in MEMSS (Applicable only 857 // when owned by NWP) ; [6] - 7th 858 // column in MEMSS (Applicable only 859 // when owned by NWP) ; [7] - 8th 860 // column in MEMSS (Applicable only 861 // when owned by NWP) ; [8] - 9th 862 // column in MEMSS (Applicable only 863 // when owned by NWP) ; [9] - 10th 864 // column in MEMSS (Applicable only 865 // when owned by NWP) ; [10] - 11th 866 // column in MEMSS (Applicable only 867 // when owned by NWP) ; [11] - 12th 868 // column in MEMSS (Applicable only 869 // when owned by NWP) ; [12] - 13th 870 // column in MEMSS (Applicable only 871 // when owned by NWP) ; [13] - 14th 872 // column in MEMSS (Applicable only 873 // when owned by NWP) ; [14] - 15th 874 // column in MEMSS (Applicable only 875 // when owned by NWP) ; [19:18] - 876 // Reserved. 877 878 #define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_S 0 879 //****************************************************************************** 880 // 881 // The following are defines for the bit fields in the 882 // GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG register. 883 // 884 //****************************************************************************** 885 #define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_M \ 886 0xFFFFFFFF // Wake time configuration (no of 887 // slow clks) for NWP wake from 888 // LPDS. 889 890 #define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_S 0 891 //****************************************************************************** 892 // 893 // The following are defines for the bit fields in the 894 // GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL register. 895 // 896 //****************************************************************************** 897 #define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_M \ 898 0xFFFE0000 899 900 #define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_S 17 901 #define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_MEM_AUTONMS_SPI_MASTER_SEL \ 902 0x00010000 // 0 - APPS is selected as host for 903 // Autonms SPI ; 1 - External host 904 // is selected as host for Autonms 905 // SPI 906 907 //****************************************************************************** 908 // 909 // The following are defines for the bit fields in the 910 // GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ register. 911 // 912 //****************************************************************************** 913 #define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_WAKEUP \ 914 0x00010000 915 916 #define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_ACK \ 917 0x00000002 // When 1 => IDLE-mode is 918 // acknowledged by the SPI-IP. (This 919 // is for MCSPI_N1) 920 921 #define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_REQ \ 922 0x00000001 // When 1 => Request for IDLE-mode 923 // for autonomous SPI. (This is for 924 // MCSPI_N1) 925 926 //****************************************************************************** 927 // 928 // The following are defines for the bit fields in the 929 // GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST register. 930 // 931 //****************************************************************************** 932 #define GPRCM_WLAN_TO_NWP_WAKE_REQUEST_WLAN_TO_NWP_WAKE_REQUEST \ 933 0x00000001 // 1 - Request for waking up NWP 934 // from any of its low-power modes 935 // (SLP/DSLP/LPDS) 936 937 //****************************************************************************** 938 // 939 // The following are defines for the bit fields in the 940 // GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST register. 941 // 942 //****************************************************************************** 943 #define GPRCM_NWP_TO_WLAN_WAKE_REQUEST_NWP_TO_WLAN_WAKE_REQUEST \ 944 0x00000001 // 1 - Request for wakinp up WLAN 945 // from its ELP Mode (This gets 946 // triggered to ELP-logic of WLAN) 947 948 //****************************************************************************** 949 // 950 // The following are defines for the bit fields in the 951 // GPRCM_O_NWP_GPIO_WAKE_CONF register. 952 // 953 //****************************************************************************** 954 #define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_M \ 955 0x00000003 // "00" - Wakeup on level0 of the 956 // selected GPIO (GPIO gets selected 957 // inside HIB3P3-module); "01" - 958 // Wakeup on fall-edge of selected 959 // GPIO. 960 961 #define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_S 0 962 //****************************************************************************** 963 // 964 // The following are defines for the bit fields in the 965 // GPRCM_O_GPRCM_EFUSE_READ_REG12 register. 966 // 967 //****************************************************************************** 968 #define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_M \ 969 0x0000FFFF // This corrsponds to ROW_32 970 // [31:16] of the FUSEFARM. SPARE 971 972 #define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_S 0 973 //****************************************************************************** 974 // 975 // The following are defines for the bit fields in the 976 // GPRCM_O_GPRCM_DIEID_READ_REG5 register. 977 // 978 //****************************************************************************** 979 #define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_M \ 980 0xFFFFFFFF // Corresponds to ROW10 of FUSEFARM 981 // : [5:0] - ADC OFFSET ; [13:6] - 982 // TEMP_SENSE ; [14:14] - DFT_GSG ; 983 // [15:15] - FMC_DISABLE ; [31:16] - 984 // WLAN_MAC ID 985 986 #define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_S 0 987 //****************************************************************************** 988 // 989 // The following are defines for the bit fields in the 990 // GPRCM_O_GPRCM_DIEID_READ_REG6 register. 991 // 992 //****************************************************************************** 993 #define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_M \ 994 0xFFFFFFFF // Corresponds to ROW11 of FUSEFARM 995 // : [31:0] : WLAN MAC ID 996 997 #define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_S 0 998 //****************************************************************************** 999 // 1000 // The following are defines for the bit fields in the 1001 // GPRCM_O_REF_FSM_CFG0 register. 1002 // 1003 //****************************************************************************** 1004 #define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_M \ 1005 0x00FF0000 // ANA-BGAP Settling time (In 1006 // number of slow_clks) 1007 1008 #define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_S 16 1009 #define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_M \ 1010 0x0000FF00 // Slicer LDO settling time (In 1011 // number of slow clks) 1012 1013 #define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_S 8 1014 #define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_M \ 1015 0x000000FF // Dig-buffer settling time (In 1016 // number of slow clks) 1017 1018 #define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_S 0 1019 //****************************************************************************** 1020 // 1021 // The following are defines for the bit fields in the 1022 // GPRCM_O_REF_FSM_CFG1 register. 1023 // 1024 //****************************************************************************** 1025 #define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_M \ 1026 0xFF000000 // XTAL settling time (In number of 1027 // slow clks) 1028 1029 #define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_S 24 1030 #define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_M \ 1031 0x00FF0000 // LV Slicer settling time 1032 1033 #define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_S 16 1034 #define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_M \ 1035 0x0000FF00 // HV Slicer Pull-down settling 1036 // time 1037 1038 #define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_S 8 1039 #define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_M \ 1040 0x000000FF // HV Slicer settling time 1041 1042 #define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_S 0 1043 //****************************************************************************** 1044 // 1045 // The following are defines for the bit fields in the 1046 // GPRCM_O_APLLMCS_WLAN_CONFIG0_40 register. 1047 // 1048 //****************************************************************************** 1049 #define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_M \ 1050 0x00007F00 // Configuration for WLAN APLLMCS - 1051 // N[6:0], if the XTAL frequency is 1052 // 40 MHz (Selected by efuse) 1053 1054 #define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_S 8 1055 #define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_M \ 1056 0x000000FF // Configuration for WLAN APLLMCS - 1057 // M[7:0], if the XTAL frequency is 1058 // 40 MHz (Selected by efuse) 1059 1060 #define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_S 0 1061 //****************************************************************************** 1062 // 1063 // The following are defines for the bit fields in the 1064 // GPRCM_O_APLLMCS_WLAN_CONFIG1_40 register. 1065 // 1066 //****************************************************************************** 1067 #define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_HISPEED_40 \ 1068 0x00000010 // Configuration for WLAN APLLMCS - 1069 // if the XTAL frequency if 40 MHz 1070 // (Selected by Efuse) 1071 1072 #define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SEL96_40 \ 1073 0x00000008 // Configuration for WLAN APLLMCS - 1074 // Sel96, if the XTAL frequency is 1075 // 40 MHz (Selected by Efuse) 1076 1077 #define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_M \ 1078 0x00000007 // Configuration for WLAN APLLMCS - 1079 // Selinpfreq, if the XTAL frequency 1080 // is 40 MHz (Selected by Efuse) 1081 1082 #define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_S 0 1083 //****************************************************************************** 1084 // 1085 // The following are defines for the bit fields in the 1086 // GPRCM_O_APLLMCS_WLAN_CONFIG0_26 register. 1087 // 1088 //****************************************************************************** 1089 #define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_M \ 1090 0x00007F00 // Configuration for WLAN APLLMCS - 1091 // N[6:0], if the XTAL frequency is 1092 // 26 MHz (Selected by efuse) 1093 1094 #define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_S 8 1095 #define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_M \ 1096 0x000000FF // Configuration for WLAN APLLMCS - 1097 // M[7:0], if the XTAL frequency is 1098 // 26 MHz (Selected by efuse) 1099 1100 #define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_S 0 1101 //****************************************************************************** 1102 // 1103 // The following are defines for the bit fields in the 1104 // GPRCM_O_APLLMCS_WLAN_CONFIG1_26 register. 1105 // 1106 //****************************************************************************** 1107 #define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_HISPEED_26 \ 1108 0x00000010 // Configuration for WLAN APLLMCS - 1109 // if the XTAL frequency if 26 MHz 1110 // (Selected by Efuse) 1111 1112 #define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SEL96_26 \ 1113 0x00000008 // Configuration for WLAN APLLMCS - 1114 // Sel96, if the XTAL frequency is 1115 // 26 MHz (Selected by Efuse) 1116 1117 #define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_M \ 1118 0x00000007 // Configuration for WLAN APLLMCS - 1119 // Selinpfreq, if the XTAL frequency 1120 // is 26 MHz (Selected by Efuse) 1121 1122 #define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_S 0 1123 //****************************************************************************** 1124 // 1125 // The following are defines for the bit fields in the 1126 // GPRCM_O_APLLMCS_WLAN_OVERRIDES register. 1127 // 1128 //****************************************************************************** 1129 #define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_CTRL \ 1130 0x00080000 1131 1132 #define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_M \ 1133 0x00070000 1134 1135 #define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_S 16 1136 #define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_M \ 1137 0x00000700 1138 1139 #define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_S 8 1140 #define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE_CTRL \ 1141 0x00000020 // Override control for 1142 // WLAN_APLLMCS_M[8]. When set to1, 1143 // M[8] will be selected by bit [3]. 1144 // (Else controlled from WTOP) 1145 1146 #define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE \ 1147 0x00000010 // Override for WLAN_APLLMCS_M[8]. 1148 // Applicable only when bit [4] is 1149 // set to 1. (Else controlled from 1150 // WTOP) 1151 1152 #define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_CTRL \ 1153 0x00000004 // Override control for 1154 // WLAN_APLLMCS_N[8:7]. When set 1155 // to1, N[8:7] will be selected by 1156 // bits [2:1]. (Else controlled from 1157 // WTOP) 1158 1159 #define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_M \ 1160 0x00000003 // Override value for 1161 // WLAN_APLLMCS_N[8:7] bits. 1162 // Applicable only when bit [1] is 1163 // set to 1. (Else controlled from 1164 // WTOP) 1165 1166 #define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_S 0 1167 //****************************************************************************** 1168 // 1169 // The following are defines for the bit fields in the 1170 // GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 register. 1171 // 1172 //****************************************************************************** 1173 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_M \ 1174 0x38000000 1175 1176 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_S 27 1177 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_M \ 1178 0x07000000 1179 1180 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_S 24 1181 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_M \ 1182 0x007F0000 // Configuration for MCU-APLLMCS : 1183 // N during RUN mode. Selected if 1184 // the XTAL frequency is 38.4 MHz 1185 // (from Efuse) 1186 1187 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_S 16 1188 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_M \ 1189 0x0000FF00 // Configuration for MCU-APLLMCS : 1190 // M during RUN mode. Selected if 1191 // the XTAL frequency is 38.4 MHz 1192 // (from Efuse) 1193 1194 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_S 8 1195 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_8_38P4 \ 1196 0x00000010 // Configuration for MCU-APLLMCS : 1197 // M[8] during RUN mode. Selected if 1198 // the XTAL frequency is 38.4 MHz 1199 // (From Efuse) 1200 1201 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_M \ 1202 0x00000003 // Configuration for MCU-APLLMCS : 1203 // N[8:7] during RUN mode. Selected 1204 // if the XTAL frequency is 38.4 MHz 1205 // (From Efuse) 1206 1207 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_S 0 1208 //****************************************************************************** 1209 // 1210 // The following are defines for the bit fields in the 1211 // GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 register. 1212 // 1213 //****************************************************************************** 1214 #define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_HISPEED_38P4 \ 1215 0x00000010 // Configuration for MCU-APLLMCS : 1216 // HISPEED during RUN mode. Selected 1217 // if the XTAL frequency is 38.4 MHz 1218 // (from Efuse) 1219 1220 #define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SEL96_38P4 \ 1221 0x00000008 // Configuration for MCU-APLLMCS : 1222 // SEL96 during RUN mode. Selected 1223 // if the XTAL frequency is 38.4 MHz 1224 // (from Efuse) 1225 1226 #define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_M \ 1227 0x00000007 // Configuration for MCU-APLLMCS : 1228 // SELINPFREQ during RUN mode. 1229 // Selected if the XTAL frequency is 1230 // 38.4 MHz (from Efuse) 1231 1232 #define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_S 0 1233 //****************************************************************************** 1234 // 1235 // The following are defines for the bit fields in the 1236 // GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 register. 1237 // 1238 //****************************************************************************** 1239 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_M \ 1240 0x007F0000 // Configuration for MCU-APLLMCS : 1241 // N during RUN mode. Selected if 1242 // the XTAL frequency is 26 MHz 1243 // (from Efuse) 1244 1245 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_S 16 1246 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_M \ 1247 0x0000FF00 // Configuration for MCU-APLLMCS : 1248 // M during RUN mode. Selected if 1249 // the XTAL frequency is 26 MHz 1250 // (from Efuse) 1251 1252 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_S 8 1253 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_8_26 \ 1254 0x00000010 // Configuration for MCU-APLLMCS : 1255 // M[8] during RUN mode. Selected if 1256 // the XTAL frequency is 26 MHz 1257 // (From Efuse) 1258 1259 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_M \ 1260 0x00000003 // Configuration for MCU-APLLMCS : 1261 // N[8:7] during RUN mode. Selected 1262 // if the XTAL frequency is 26 MHz 1263 // (From Efuse) 1264 1265 #define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_S 0 1266 //****************************************************************************** 1267 // 1268 // The following are defines for the bit fields in the 1269 // GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 register. 1270 // 1271 //****************************************************************************** 1272 #define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_HISPEED_26 \ 1273 0x00000010 // Configuration for MCU-APLLMCS : 1274 // HISPEED during RUN mode. Selected 1275 // if the XTAL frequency is 26 MHz 1276 // (from Efuse) 1277 1278 #define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SEL96_26 \ 1279 0x00000008 // Configuration for MCU-APLLMCS : 1280 // SEL96 during RUN mode. Selected 1281 // if the XTAL frequency is 26 MHz 1282 // (from Efuse) 1283 1284 #define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_M \ 1285 0x00000007 // Configuration for MCU-APLLMCS : 1286 // SELINPFREQ during RUN mode. 1287 // Selected if the XTAL frequency is 1288 // 26 MHz (from Efuse) 1289 1290 #define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_S 0 1291 //****************************************************************************** 1292 // 1293 // The following are defines for the bit fields in the GPRCM_O_SPARE_RW0 register. 1294 // 1295 //****************************************************************************** 1296 //****************************************************************************** 1297 // 1298 // The following are defines for the bit fields in the GPRCM_O_SPARE_RW1 register. 1299 // 1300 //****************************************************************************** 1301 //****************************************************************************** 1302 // 1303 // The following are defines for the bit fields in the 1304 // GPRCM_O_APLLMCS_MCU_OVERRIDES register. 1305 // 1306 //****************************************************************************** 1307 #define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_LOCK \ 1308 0x00000400 // 1 - APLLMCS_MCU is locked ; 0 - 1309 // APLLMCS_MCU is not locked 1310 1311 #define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE \ 1312 0x00000200 // Override for APLLMCS_MCU Enable. 1313 // Applicable if bit [8] is set 1314 1315 #define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE_CTRL \ 1316 0x00000100 // 1 - Enable for APLLMCS_MCU comes 1317 // from bit [9]. 0 - Enable for 1318 // APLLMCS_MCU comes from FSM. 1319 1320 #define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_M \ 1321 0x00000006 // Override for sysclk src 1322 // (applicable only if bit [0] is 1323 // set to 1. "00"- SLOW_CLK "01"- 1324 // XTAL_CLK "10"- PLL_CLK 1325 1326 #define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_S 1 1327 #define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_CTRL \ 1328 0x00000001 // 1 - Sysclk src is selected from 1329 // bits [2:1] of this register. 0 - 1330 // Sysclk src is selected from FSM 1331 1332 //****************************************************************************** 1333 // 1334 // The following are defines for the bit fields in the 1335 // GPRCM_O_SYSCLK_SWITCH_STATUS register. 1336 // 1337 //****************************************************************************** 1338 #define GPRCM_SYSCLK_SWITCH_STATUS_SYSCLK_SWITCH_STATUS \ 1339 0x00000001 // 1 - Sysclk switching is 1340 // complete. 0 - Sysclk switching is 1341 // in progress. 1342 1343 //****************************************************************************** 1344 // 1345 // The following are defines for the bit fields in the 1346 // GPRCM_O_REF_LDO_CONTROLS register. 1347 // 1348 //****************************************************************************** 1349 #define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE_OVERRIDE_CTRL \ 1350 0x00010000 // 1 - Enable for REF_LDO comes 1351 // from bit [0] of this register ; 0 1352 // - Enable for REF_LDO comes from 1353 // the FSM. Note : Final REF_LDO_EN 1354 // reaches on the port 1355 // TOP_PM_REG2[0] of gprcm. 1356 1357 #define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_M \ 1358 0x0000C000 // Spare bits for REF_CTRL_FSM. 1359 // Reaches directly on port 1360 // TOP_PM_REG2[15:14] of gprcm. 1361 1362 #define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_S 14 1363 #define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_M \ 1364 0x00003800 // REF TLOAD Enable. Reaches 1365 // directly on port 1366 // TOP_PM_REG2[13:11] of gprcm. 1367 1368 #define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_S 11 1369 #define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_M \ 1370 0x00000700 // REF_LDO Test-mux control. 1371 // Reaches directly on port 1372 // TOP_PM_REG2[10:8] of gprcm. 1373 1374 #define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_S 8 1375 #define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_M \ 1376 0x000000C0 // REF BW Control. Reaches directly 1377 // on port TOP_PM_REG2[7:6] of 1378 // gprcm. 1379 1380 #define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_S 6 1381 #define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_M \ 1382 0x0000003C // REF VTRIM Control. Reaches 1383 // directly on port TOP_PM_REG2[5:2] 1384 // of gprcm. 1385 1386 #define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_S 2 1387 #define GPRCM_REF_LDO_CONTROLS_REF_LDO_BYPASS_ENABLE \ 1388 0x00000002 // REF LDO Bypass Enable. Reaches 1389 // directly on port TOP_PM_REG2[1] 1390 // of gprcm. 1391 1392 #define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE \ 1393 0x00000001 // Override for REF_LDO Enable. 1394 // Applicable only if bit [16] of 1395 // this register is set. Note : 1396 // Final REF_LDO_EN reaches on the 1397 // port TOP_PM_REG2[0] of gprcm. 1398 1399 //****************************************************************************** 1400 // 1401 // The following are defines for the bit fields in the 1402 // GPRCM_O_REF_RTRIM_CONTROL register. 1403 // 1404 //****************************************************************************** 1405 #define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_M \ 1406 0x18000000 // This is [5:4] bits of 1407 // TOP_PM_REG0 1408 1409 #define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_S 27 1410 #define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_M \ 1411 0x07FF0000 // This is [15:5] bits of 1412 // TOP_CLKM_REG0 1413 1414 #define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_S 16 1415 #define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_OVERRIDE_CTRL \ 1416 0x00000100 // 1 - CLKM_RTRIM comes for 1417 // bits[4:0] of this register. 0 - 1418 // CLKM_RTRIM comes from Efuse 1419 // (after efuse_done = 1). 1420 1421 #define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_M \ 1422 0x0000001F // CLKM_TRIM Override. Applicable 1423 // when efuse_done = 0 or bit[8] is 1424 // set to 1. 1425 1426 #define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_S 0 1427 //****************************************************************************** 1428 // 1429 // The following are defines for the bit fields in the 1430 // GPRCM_O_REF_SLICER_CONTROLS0 register. 1431 // 1432 //****************************************************************************** 1433 #define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV_OVERRIDE_CTRL \ 1434 0x00200000 // 1 - EN_DIG_BUF_TOP comes from 1435 // bit [14] of this register. 0 - 1436 // EN_DIG_BUF_TOP comes from the 1437 // FSM. Note : Final EN_DIG_BUF_WLAN 1438 // reaches on TOP_CLKM_REG1_IN[14] 1439 // port of gprcm 1440 1441 #define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV_OVERRIDE_CTRL \ 1442 0x00100000 // 1 - EN_DIG_BUF_TOP comes from 1443 // bit [15] of this register. 0 - 1444 // EN_DIG_BUF_TOP comes from the 1445 // FSM. Note : Final EN_DIG_BUF_TOP 1446 // reaches on TOP_CLKM_REG1_IN[15] 1447 // port of gprcm 1448 1449 #define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL_OVERRIDE_CTRL \ 1450 0x00080000 // 1 - EN_XTAL comes from bit [3] 1451 // of this register. 0 - EN_XTAL 1452 // comes from FSM. Note : Final 1453 // XTAL_EN reaches on 1454 // TOP_CLKM_REG1_IN[3] of gprcm. 1455 1456 #define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_OVERRIDE_CTRL \ 1457 0x00040000 // 1 - Enable HV Slicer comes from 1458 // bit [2] of this register. 0 - 1459 // Enable HV Slicer comes from FSM. 1460 // Note : Final HV_SLICER_EN reaches 1461 // on port TOP_CLKM_REG1_IN[1] of 1462 // gprcm. 1463 1464 #define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_LV_OVERRIDE_CTRL \ 1465 0x00020000 // 1 - Enable LV Slicer comes from 1466 // bit[1] of this register. 0 - 1467 // Enable LV Slicer comes from FSM. 1468 // Note : final LV_SLICER_EN reaches 1469 // on port TOP_CLKM_REG1_IN[2] of 1470 // gprcm. 1471 1472 #define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_PDN_OVERRIDE_CTRL \ 1473 0x00010000 // 1 - Enable HV Pull-down comes 1474 // from bit[0] of this register. 0 - 1475 // Enable HV Pull-down comes from 1476 // FSM. Note : Final HV_PULL_DOWN 1477 // reaches on port 1478 // TOP_CLKM_REG1_IN[0] of gprcm. 1479 1480 #define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV \ 1481 0x00008000 // Override for EN_DIG_BUF_TOP. 1482 // Applicable if bit[20] is set to 1483 // 1. Note : Final EN_DIG_BUF_TOP 1484 // reaches on TOP_CLKM_REG1_IN[15] 1485 // port of gprcm 1486 1487 #define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV \ 1488 0x00004000 // Override for EN_DIG_BUF_WLAN. 1489 // Applicable if bit[19] is set to 1490 // 1. Note : Final EN_DIG_BUF_WLAN 1491 // reaches on TOP_CLKM_REG1_IN[14] 1492 // port of gprcm 1493 1494 #define GPRCM_REF_SLICER_CONTROLS0_CLKOUT_FLIP_EN \ 1495 0x00002000 // CLKOUT Flip Enable. Reaches on 1496 // bit[13] of TOP_CLKM_REG1_IN[13] 1497 // port of gprcm. 1498 1499 #define GPRCM_REF_SLICER_CONTROLS0_EN_DIV2_WLAN_CLK \ 1500 0x00001000 // Enable divide2 in WLAN Clk-path. 1501 // Reaches on TOP_CLKM_REG1_IN[12] 1502 // port of gprcm 1503 1504 #define GPRCM_REF_SLICER_CONTROLS0_EN_DIV3_WLAN_CLK \ 1505 0x00000800 // Enable divide3 in WLAN Clk-path. 1506 // Reaches on TOP_CLKM_REG1_IN[11] 1507 // port of gprcm 1508 1509 #define GPRCM_REF_SLICER_CONTROLS0_EN_DIV4_WLAN_CLK \ 1510 0x00000400 // Enable divide4 in WLAN Clk-path. 1511 // Reaches on TOP_CLKM_REG1_IN[10] 1512 // port of gprcm 1513 1514 #define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_M \ 1515 0x000003C0 // CM Test-mux select. Reaches on 1516 // TOP_CLMM_REG1_IN[9:6] port of 1517 // gprcm 1518 1519 #define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_S 6 1520 #define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_M \ 1521 0x00000030 // Slicer spare0 control. Reaches 1522 // on TOP_CLKM_REG1_IN[5:4] port of 1523 // gprcm 1524 1525 #define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_S 4 1526 #define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL \ 1527 0x00000008 // Enable XTAL override. Reaches on 1528 // TOP_CLKM_REG1_IN[3] port of gprcm 1529 1530 #define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV \ 1531 0x00000004 // Enable HV Slicer override. 1532 // Reaches on TOP_CLKM_REG1_IN[1] 1533 // port of gprcm 1534 1535 #define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_LV \ 1536 0x00000002 // Enable LV Slicer override. 1537 // Reaches on TOP_CLKM_REG1_IN[2] 1538 // port of gprcm 1539 1540 #define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV_PDN \ 1541 0x00000001 // Enable HV Pull-down override. 1542 // Reaches on TOP_CLKM_REG1_IN[0] 1543 // port of gprcm 1544 1545 //****************************************************************************** 1546 // 1547 // The following are defines for the bit fields in the 1548 // GPRCM_O_REF_SLICER_CONTROLS1 register. 1549 // 1550 //****************************************************************************** 1551 #define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_M \ 1552 0x0000FC00 // Slicer spare1. Reaches on port 1553 // TOP_CLKM_REG2_IN[15:10] of gprcm. 1554 1555 #define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_S 10 1556 #define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_M \ 1557 0x000003F0 // XOSC Trim. Reaches on port 1558 // TOP_CLKM_REG2_IN[9:4] of gprcm 1559 1560 #define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_S 4 1561 #define GPRCM_REF_SLICER_CONTROLS1_SLICER_ITRIM_CHANGE_TOGGLE \ 1562 0x00000008 // Slicer ITRIM Toggle. Reaches on 1563 // port TOP_CLKM_REG2_IN[3] of 1564 // gprcm. 1565 1566 #define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_M \ 1567 0x00000007 // LV Slicer trim. Reaches on port 1568 // TOP_CLKM_REG2_IN[2:0] of gprcm. 1569 1570 #define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_S 0 1571 //****************************************************************************** 1572 // 1573 // The following are defines for the bit fields in the 1574 // GPRCM_O_REF_ANA_BGAP_CONTROLS0 register. 1575 // 1576 //****************************************************************************** 1577 #define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_M \ 1578 0xFF800000 1579 1580 #define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_S 23 1581 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_mag_trim_override_ctrl \ 1582 0x00400000 // 1 - REF_MAG_TRIM comes from 1583 // bit[4:0] of register 1584 // REF_ANA_BGAP_CONTROLS1 [Addr : 1585 // 0x0850]; 0 - REF_MAG_TRIM comes 1586 // from efuse (After efc_done = 1). 1587 // Note : Final REF_MAG_TRIM reaches 1588 // on port TOP_PM_REG1[4:0] of gprcm 1589 1590 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_override_ctrl \ 1591 0x00200000 // 1 - REF_V2I_TRIM comes from 1592 // bit[9:6] of this register ; 0 - 1593 // REF_V2I_TRIM comes from efuse 1594 // (After efc_done = 1). Note : 1595 // Final REF_V2I_TRIM reaches on 1596 // port TOP_PM_REG0[9:6] of gprcm. 1597 1598 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_override_ctrl \ 1599 0x00100000 // 1 - REF_TEMP_TRIM comes from 1600 // bit[15:10] of this register ; 0 - 1601 // REF_TEMP_TRIM comes from efuse 1602 // (After efc_done = 1). Note : 1603 // Final REF_TEMP_TRIM reaches on 1604 // port TOP_PM_REG0[15:10] of gprcm. 1605 1606 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en_override_ctrl \ 1607 0x00080000 // 1 - REF_STARTUP_EN comes from 1608 // bit [3] of this register ; 0 - 1609 // REF_STARTUP_EN comes from FSM. 1610 // Note : Final REF_STARTUP_EN 1611 // reaches on port TOP_PM_REG0[3] of 1612 // gprcm 1613 1614 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en_override_ctrl \ 1615 0x00040000 // 1 - REF_V2I_EN comes from bit 1616 // [2] of this register ; 0 - 1617 // REF_V2I_EN comes from FSM. Note : 1618 // Final REF_V2I_EN reaches on port 1619 // TOP_PM_REG0[2] of gprcm. 1620 1621 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en_override_ctrl \ 1622 0x00020000 // 1 - REF_FC_EN comes from bit [1] 1623 // of this register ; 0 - REF_FC_EN 1624 // comes from FSM. Note : Final 1625 // REF_FC_EN reaches on port 1626 // TOP_PM_REG0[1] of gprcm. 1627 1628 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en_override_ctrl \ 1629 0x00010000 // 1 - REF_BGAP_EN comes from bit 1630 // [0] of this register ; 0 - 1631 // REF_BGAP_EN comes from FSM. Note 1632 // : Final REF_BGAP_EN reaches on 1633 // port TOP_PM_REG0[0] of gprcm. 1634 1635 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_M \ 1636 0x0000FC00 // REF_TEMP_TRIM override. 1637 // Applicable when bit [20] of this 1638 // register set to 1. (or efc_done = 1639 // 0) Note : Final REF_TEMP_TRIM 1640 // reaches on port 1641 // TOP_PM_REG0[15:10] of gprcm. 1642 1643 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_S 10 1644 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_M \ 1645 0x000003C0 // REF_V2I_TRIM Override. 1646 // Applicable when bit [21] of this 1647 // register set to 1 . (of efc_done 1648 // = 0) Note : Final REF_V2I_TRIM 1649 // reaches on port TOP_PM_REG0[9:6] 1650 // of gprcm. 1651 1652 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_S 6 1653 #define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_M \ 1654 0x00000030 1655 1656 #define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_S 4 1657 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en \ 1658 0x00000008 // REF_STARTUP_EN override. 1659 // Applicable when bit [19] of this 1660 // register is set to 1. Note : 1661 // Final REF_STARTUP_EN reaches on 1662 // port TOP_PM_REG0[3] of gprcm 1663 1664 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en \ 1665 0x00000004 // REF_V2I_EN override. Applicable 1666 // when bit [21] of this register is 1667 // set to 1. Note : Final REF_V2I_EN 1668 // reaches on port TOP_PM_REG0[2] of 1669 // gprcm. 1670 1671 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en \ 1672 0x00000002 // REF_FC_EN override. Applicable 1673 // when bit [17] of this register is 1674 // set to 1. Note : Final REF_FC_EN 1675 // reaches on port TOP_PM_REG0[1] of 1676 // gprcm. 1677 1678 #define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en \ 1679 0x00000001 // REF_BGAP_EN override. Applicable 1680 // when bit [16] of this register 1681 // set to 1. Note : Final 1682 // REF_BGAP_EN reaches on port 1683 // TOP_PM_REG0[0] of gprcm. 1684 1685 //****************************************************************************** 1686 // 1687 // The following are defines for the bit fields in the 1688 // GPRCM_O_REF_ANA_BGAP_CONTROLS1 register. 1689 // 1690 //****************************************************************************** 1691 #define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_M \ 1692 0xFFFF0000 1693 1694 #define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_S 16 1695 #define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_M \ 1696 0x0000C000 // REF_BGAP_SPARE. Reaches on port 1697 // TOP_PM_REG1[15:14] of gprcm. 1698 1699 #define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_S 14 1700 #define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_M \ 1701 0x00003E00 // REF_BGAP_TMUX_CTRL. Reaches on 1702 // port TOP_PM_REG1[13:9] of gprcm. 1703 1704 #define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_S 9 1705 #define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_M \ 1706 0x000001E0 // REF_FILT_TRIM. Reaches on port 1707 // TOP_PM_REG1[8:5] of gprcm. 1708 1709 #define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_S 5 1710 #define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_M \ 1711 0x0000001F // REF_MAG_TRIM Override. 1712 // Applicable when bit[22] of 1713 // REF_ANA_BGAP_CONTROLS0 [0x084C] 1714 // set to 1 (of efc_done = 0). Note 1715 // : Final REF_MAG_TRIM reaches on 1716 // port TOP_PM_REG1[4:0] of gprcm 1717 1718 #define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_S 0 1719 //****************************************************************************** 1720 // 1721 // The following are defines for the bit fields in the 1722 // GPRCM_O_REF_ANA_SPARE_CONTROLS0 register. 1723 // 1724 //****************************************************************************** 1725 #define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_M \ 1726 0xFFFF0000 1727 1728 #define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_S 16 1729 #define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_M \ 1730 0x0000FFFF // Spare control. Reaches on 1731 // TOP_PM_REG3 [15:0] of gprcm. 1732 1733 #define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_S 0 1734 //****************************************************************************** 1735 // 1736 // The following are defines for the bit fields in the 1737 // GPRCM_O_REF_ANA_SPARE_CONTROLS1 register. 1738 // 1739 //****************************************************************************** 1740 #define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_M \ 1741 0xFFFF0000 // Spare control. Reaches on 1742 // TOP_CLKM_REG3 [15:0] of gprcm. 1743 1744 #define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_S 16 1745 #define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_M \ 1746 0x0000FFFF // Spare control. Reaches on 1747 // TOP_CLKM_REG4 [15:0] of gprcm. 1748 1749 #define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_S 0 1750 //****************************************************************************** 1751 // 1752 // The following are defines for the bit fields in the 1753 // GPRCM_O_MEMSS_PSCON_OVERRIDES0 register. 1754 // 1755 //****************************************************************************** 1756 #define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_M \ 1757 0xFFFF0000 1758 1759 #define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_S 16 1760 #define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_M \ 1761 0x0000FFFF 1762 1763 #define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_S 0 1764 //****************************************************************************** 1765 // 1766 // The following are defines for the bit fields in the 1767 // GPRCM_O_MEMSS_PSCON_OVERRIDES1 register. 1768 // 1769 //****************************************************************************** 1770 #define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_M \ 1771 0xFFFFFFC0 1772 1773 #define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_S 6 1774 #define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override_ctrl \ 1775 0x00000020 1776 1777 #define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override \ 1778 0x00000010 1779 1780 #define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override_ctrl \ 1781 0x00000008 1782 1783 #define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override \ 1784 0x00000004 1785 1786 #define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_off_override_ctrl \ 1787 0x00000002 1788 1789 #define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memms_pscon_mem_retain_override_ctrl \ 1790 0x00000001 1791 1792 //****************************************************************************** 1793 // 1794 // The following are defines for the bit fields in the 1795 // GPRCM_O_PLL_REF_LOCK_OVERRIDES register. 1796 // 1797 //****************************************************************************** 1798 #define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_M \ 1799 0xFFFFFFF8 1800 1801 #define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_S 3 1802 #define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_mcu_apllmcs_lock_override \ 1803 0x00000004 1804 1805 #define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_wlan_apllmcs_lock_override \ 1806 0x00000002 1807 1808 #define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_ref_clk_valid_override \ 1809 0x00000001 1810 1811 //****************************************************************************** 1812 // 1813 // The following are defines for the bit fields in the 1814 // GPRCM_O_MCU_PSCON_DEBUG register. 1815 // 1816 //****************************************************************************** 1817 #define GPRCM_MCU_PSCON_DEBUG_reserved_M \ 1818 0xFFFFFFC0 1819 1820 #define GPRCM_MCU_PSCON_DEBUG_reserved_S 6 1821 #define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_M \ 1822 0x00000038 // MCU_PSCON_RTC_ON = "0000"; 1823 // MCU_PSCON_RTC_OFF = "0001"; 1824 // MCU_PSCON_RTC_RET = "0010"; 1825 // MCU_PSCON_RTC_OFF_TO_ON = "0011"; 1826 // MCU_PSCON_RTC_RET_TO_ON = "0100"; 1827 // MCU_PSCON_RTC_ON_TO_RET = "0101"; 1828 // MCU_PSCON_RTC_ON_TO_OFF = "0110"; 1829 // MCU_PSCON_RTC_RET_TO_ON_WAIT_OPP 1830 // = "0111"; 1831 // MCU_PSCON_RTC_OFF_TO_ON_WAIT_OPP 1832 // = "1000"; 1833 1834 #define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_S 3 1835 #define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_M \ 1836 0x00000007 1837 1838 #define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_S 0 1839 //****************************************************************************** 1840 // 1841 // The following are defines for the bit fields in the 1842 // GPRCM_O_MEMSS_PWR_PS register. 1843 // 1844 //****************************************************************************** 1845 #define GPRCM_MEMSS_PWR_PS_reserved_M \ 1846 0xFFFFFFF8 1847 1848 #define GPRCM_MEMSS_PWR_PS_reserved_S 3 1849 #define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_M \ 1850 0x00000007 // MEMSS_PM_SLEEP = "000"; 1851 // MEMSS_PM_WAIT_OPP = "010"; 1852 // MEMSS_PM_ACTIVE = "011"; 1853 // MEMSS_PM_SLEEP_TO_ACTIVE = "100"; 1854 // MEMSS_PM_ACTIVE_TO_SLEEP = "101"; 1855 1856 #define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_S 0 1857 //****************************************************************************** 1858 // 1859 // The following are defines for the bit fields in the 1860 // GPRCM_O_REF_FSM_DEBUG register. 1861 // 1862 //****************************************************************************** 1863 #define GPRCM_REF_FSM_DEBUG_reserved_M \ 1864 0xFFFFFFC0 1865 1866 #define GPRCM_REF_FSM_DEBUG_reserved_S 6 1867 #define GPRCM_REF_FSM_DEBUG_fref_mode_M \ 1868 0x00000030 // 01 - HV Mode ; 10 - LV Mode ; 11 1869 // - XTAL Mode 1870 1871 #define GPRCM_REF_FSM_DEBUG_fref_mode_S 4 1872 #define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_M \ 1873 0x0000000F // constant FREF_CLK_OFF = "00000"; 1874 // constant FREF_EN_BGAP = "00001"; 1875 // constant FREF_EN_LDO = "00010"; 1876 // constant FREF_EN_SLI_HV = 1877 // "00011"; constant 1878 // FREF_EN_SLI_HV_PD = "00100"; 1879 // constant FREF_EN_DIG_BUF = 1880 // "00101"; constant FREF_EN_OSC = 1881 // "00110"; constant FREF_EN_SLI_LV 1882 // = "00111"; constant 1883 // FREF_EN_CLK_REQ = "01000"; 1884 // constant FREF_CLK_VALID = 1885 // "01001"; constant FREF_MODE_DET0 1886 // = "01010"; constant 1887 // FREF_MODE_DET1 = "01011"; 1888 // constant FREF_MODE_DET2 = 1889 // "10010"; constant FREF_MODE_DET3 1890 // = "10011"; constant FREF_VALID = 1891 // "01100"; constant FREF_VALID0 = 1892 // "01101"; constant FREF_VALID1 = 1893 // "01110"; constant FREF_VALID2 = 1894 // "01111"; constant 1895 // FREF_WAIT_EXT_TCXO0 = "10000"; 1896 // constant FREF_WAIT_EXT_TCXO1 = 1897 // "10001"; 1898 1899 #define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_S 0 1900 //****************************************************************************** 1901 // 1902 // The following are defines for the bit fields in the 1903 // GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE register. 1904 // 1905 //****************************************************************************** 1906 #define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_M \ 1907 0xFFFFFFE0 1908 1909 #define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_S 5 1910 #define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_ctrl \ 1911 0x00000010 // 1 - Override the sytem-opp 1912 // request to ANATOP using bit0 of 1913 // this register 1914 1915 #define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_M \ 1916 0x0000000F // "0001" - RUN ; "0010" - DSLP ; 1917 // "0100" - LPDS ; Others - NA 1918 1919 #define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_S 0 1920 //****************************************************************************** 1921 // 1922 // The following are defines for the bit fields in the 1923 // GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG register. 1924 // 1925 //****************************************************************************** 1926 #define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_M \ 1927 0xFFFFFFFE 1928 1929 #define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_S 1 1930 #define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_mem_sleep_opp_enter_with_testpd_on \ 1931 0x00000001 // 1 - Enable sleep-opp (DSLP/LPDS) 1932 // entry even if Test-Pd is kept ON 1933 // ; 0 - Donot enable sleep-opp 1934 // (DSLP/LPDS) entry with Test-Pd 1935 // ON. 1936 1937 //****************************************************************************** 1938 // 1939 // The following are defines for the bit fields in the 1940 // GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES register. 1941 // 1942 //****************************************************************************** 1943 #define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_M \ 1944 0xFFFFFFF8 1945 1946 #define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_S 3 1947 #define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override_ctrl \ 1948 0x00000004 // NA 1949 1950 #define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override \ 1951 0x00000002 // NA 1952 1953 #define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_sleep_with_clk_req_override \ 1954 0x00000001 // NA 1955 1956 //****************************************************************************** 1957 // 1958 // The following are defines for the bit fields in the 1959 // GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES register. 1960 // 1961 //****************************************************************************** 1962 #define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_mode_req_override_ctrl \ 1963 0x00000004 // 1 - Override the MCU-PD power 1964 // modes using bits [1] & [0] ; 1965 1966 #define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_pwrdn_req_override \ 1967 0x00000002 // 1 - Request for power-down of 1968 // MCU-PD ; 1969 1970 #define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_ret_req_override \ 1971 0x00000001 // 1 - Request for retention mode 1972 // of MCU-PD. 1973 1974 //****************************************************************************** 1975 // 1976 // The following are defines for the bit fields in the 1977 // GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES register. 1978 // 1979 //****************************************************************************** 1980 #define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override_ctrl \ 1981 0x00000002 // 1- Override the MCSPI 1982 // (Autonomous SPI) memory state 1983 // using bit [0] 1984 1985 #define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override \ 1986 0x00000001 // 1 - Request for power-down of 1987 // Autonomous SPI 8k memory ; 0 - 1988 // Donot request power-down of 1989 // Autonomous SPI 8k Memory 1990 1991 //****************************************************************************** 1992 // 1993 // The following are defines for the bit fields in the 1994 // GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES register. 1995 // 1996 //****************************************************************************** 1997 #define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_wlan_apllmcs_lock \ 1998 0x00000100 1999 2000 #define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override \ 2001 0x00000002 2002 2003 #define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override_ctrl \ 2004 0x00000001 2005 2006 //****************************************************************************** 2007 // 2008 // The following are defines for the bit fields in the 2009 // GPRCM_O_MEM_REF_FSM_CFG2 register. 2010 // 2011 //****************************************************************************** 2012 #define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_M \ 2013 0x00380000 // Number of RTC clocks for keeping 2014 // the FC_EN asserted high 2015 2016 #define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_S 19 2017 #define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_M \ 2018 0x00070000 // Number of RTC clocks for keeping 2019 // the STARTUP_EN asserted high 2020 2021 #define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_S 16 2022 #define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_M \ 2023 0x0000FFFF // Number of RTC clocks for waiting 2024 // for clock to settle. 2025 2026 #define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_S 0 2027 //****************************************************************************** 2028 // 2029 // The following are defines for the bit fields in the 2030 // GPRCM_O_TESTCTRL_POWER_CTRL register. 2031 // 2032 //****************************************************************************** 2033 #define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_M \ 2034 0x00000006 2035 2036 #define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_S 1 2037 #define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_ENABLE \ 2038 0x00000001 // 0 - Disable the TestCtrl-pd ; 1 2039 // - Enable the TestCtrl-pd. 2040 2041 //****************************************************************************** 2042 // 2043 // The following are defines for the bit fields in the 2044 // GPRCM_O_SSDIO_POWER_CTRL register. 2045 // 2046 //****************************************************************************** 2047 #define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_M \ 2048 0x00000006 // 1 - SSDIO-PD is ON ; 0 - 2049 // SSDIO-PD is OFF 2050 2051 #define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_S 1 2052 #define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_ENABLE \ 2053 0x00000001 // 0 - Disable the SSDIO-pd ; 1 - 2054 // Enable the SSDIO-pd. 2055 2056 //****************************************************************************** 2057 // 2058 // The following are defines for the bit fields in the 2059 // GPRCM_O_MCSPI_N1_POWER_CTRL register. 2060 // 2061 //****************************************************************************** 2062 #define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_M \ 2063 0x00000006 // 1 - MCSPI_N1-PD is ON ; 0 - 2064 // MCSPI_N1-PD if OFF 2065 2066 #define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_S 1 2067 #define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_ENABLE \ 2068 0x00000001 // 0 - Disable the MCSPI_N1-pd ; 1 2069 // - Enable the MCSPI_N1-pd. 2070 2071 //****************************************************************************** 2072 // 2073 // The following are defines for the bit fields in the 2074 // GPRCM_O_WELP_POWER_CTRL register. 2075 // 2076 //****************************************************************************** 2077 #define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_M \ 2078 0x00001C00 2079 2080 #define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_S 10 2081 #define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE \ 2082 0x00000200 2083 2084 #define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE_CTRL \ 2085 0x00000100 2086 2087 #define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_M \ 2088 0x00000006 2089 2090 #define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_S 1 2091 #define GPRCM_WELP_POWER_CTRL_WELP_PD_ENABLE \ 2092 0x00000001 // 0 - Disable the WELP-pd ; 1 - 2093 // Enable the WELP-pd. 2094 2095 //****************************************************************************** 2096 // 2097 // The following are defines for the bit fields in the 2098 // GPRCM_O_WL_SDIO_POWER_CTRL register. 2099 // 2100 //****************************************************************************** 2101 #define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_M \ 2102 0x00000006 2103 2104 #define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_S 1 2105 #define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_ENABLE \ 2106 0x00000001 // 0 - Disable the WL_SDIO-pd ; 1 - 2107 // Enable the WL_SDIO-pd. 2108 2109 //****************************************************************************** 2110 // 2111 // The following are defines for the bit fields in the 2112 // GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG register. 2113 // 2114 //****************************************************************************** 2115 #define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_M \ 2116 0x00FFFFFF // SRAM (WTOP+DRP) state during 2117 // Active-mode : 1 - SRAMs are ON ; 2118 // 0 - SRAMs are OFF. Cluster 2119 // information : [0] - 1st column of 2120 // MEMSS (Applicable only when owned 2121 // by WTOP/PHY) [1] - 2nd column of 2122 // MEMSS (Applicable only when owned 2123 // by WTOP/PHY) ; [2] - 3rd column 2124 // of MEMSS (Applicable only when 2125 // owned by WTOP/PHY) ; [3] - 4th 2126 // column of MEMSS (Applicable only 2127 // when owned by WTOP/PHY) ; [4] - 2128 // 5th column of MEMSS (Applicable 2129 // only when owned by WTOP/PHY) ; 2130 // [5] - 6th column of MEMSS 2131 // (Applicable only when owned by 2132 // WTOP/PHY) ; [6] - 7th column of 2133 // MEMSS (Applicable only when owned 2134 // by WTOP/PHY) ; [7] - 8th column 2135 // of MEMSS (Applicable only when 2136 // owned by WTOP/PHY) ; [8] - 9th 2137 // column of MEMSS (Applicable only 2138 // when owned by WTOP/PHY) ; [9] - 2139 // 10th column of MEMSS (Applicable 2140 // only when owned by WTOP/PHY) ; 2141 // [10] - 11th column of MEMSS 2142 // (Applicable only when owned by 2143 // WTOP/PHY) ; [11] - 12th column of 2144 // MEMSS (Applicable only when owned 2145 // by WTOP/PHY) ; [12] - 13th column 2146 // of MEMSS (Applicable only when 2147 // owned by WTOP/PHY) ; [13] - 14th 2148 // column of MEMSS (Applicable only 2149 // when owned by WTOP/PHY) ; [14] - 2150 // 15th column of MEMSS (Applicable 2151 // only when owned by WTOP/PHY) ; 2152 // [15] - 16th column of MEMSS 2153 // (Applicable only when owned by 2154 // WTOP/PHY) ; [23:16] - Internal to 2155 // WTOP Cluster 2156 2157 #define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_S 0 2158 //****************************************************************************** 2159 // 2160 // The following are defines for the bit fields in the 2161 // GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG register. 2162 // 2163 //****************************************************************************** 2164 #define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_M \ 2165 0x00FFFFFF // SRAM (WTOP+DRP) state during 2166 // Sleep-mode : 1 - SRAMs are RET ; 2167 // 0 - SRAMs are OFF. Cluster 2168 // information : [0] - 1st column of 2169 // MEMSS (Applicable only when owned 2170 // by WTOP/PHY) [1] - 2nd column of 2171 // MEMSS (Applicable only when owned 2172 // by WTOP/PHY) ; [2] - 3rd column 2173 // of MEMSS (Applicable only when 2174 // owned by WTOP/PHY) ; [3] - 4th 2175 // column of MEMSS (Applicable only 2176 // when owned by WTOP/PHY) ; [4] - 2177 // 5th column of MEMSS (Applicable 2178 // only when owned by WTOP/PHY) ; 2179 // [5] - 6th column of MEMSS 2180 // (Applicable only when owned by 2181 // WTOP/PHY) ; [6] - 7th column of 2182 // MEMSS (Applicable only when owned 2183 // by WTOP/PHY) ; [7] - 8th column 2184 // of MEMSS (Applicable only when 2185 // owned by WTOP/PHY) ; [8] - 9th 2186 // column of MEMSS (Applicable only 2187 // when owned by WTOP/PHY) ; [9] - 2188 // 10th column of MEMSS (Applicable 2189 // only when owned by WTOP/PHY) ; 2190 // [10] - 11th column of MEMSS 2191 // (Applicable only when owned by 2192 // WTOP/PHY) ; [11] - 12th column of 2193 // MEMSS (Applicable only when owned 2194 // by WTOP/PHY) ; [12] - 13th column 2195 // of MEMSS (Applicable only when 2196 // owned by WTOP/PHY) ; [13] - 14th 2197 // column of MEMSS (Applicable only 2198 // when owned by WTOP/PHY) ; [14] - 2199 // 15th column of MEMSS (Applicable 2200 // only when owned by WTOP/PHY) ; 2201 // [15] - 16th column of MEMSS 2202 // (Applicable only when owned by 2203 // WTOP/PHY) ; [23:16] - Internal to 2204 // WTOP Cluster 2205 2206 #define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_S 0 2207 //****************************************************************************** 2208 // 2209 // The following are defines for the bit fields in the 2210 // GPRCM_O_APPS_SECURE_INIT_DONE register. 2211 // 2212 //****************************************************************************** 2213 #define GPRCM_APPS_SECURE_INIT_DONE_SECURE_INIT_DONE_STATUS \ 2214 0x00000002 // 1-Secure mode init is done ; 2215 // 0-Secure mode init is not done 2216 2217 #define GPRCM_APPS_SECURE_INIT_DONE_APPS_SECURE_INIT_DONE \ 2218 0x00000001 // Must be programmed 1 in order to 2219 // say that secure-mode device init 2220 // is done 2221 2222 //****************************************************************************** 2223 // 2224 // The following are defines for the bit fields in the 2225 // GPRCM_O_APPS_DEV_MODE_INIT_DONE register. 2226 // 2227 //****************************************************************************** 2228 #define GPRCM_APPS_DEV_MODE_INIT_DONE_APPS_DEV_MODE_INIT_DONE \ 2229 0x00000001 // 1 - Patch download and other 2230 // initializations are done (before 2231 // removing APPS resetn) for 2232 // development mode (#3) . 0 - 2233 // Development mode (#3) init is not 2234 // done yet 2235 2236 //****************************************************************************** 2237 // 2238 // The following are defines for the bit fields in the 2239 // GPRCM_O_EN_APPS_REBOOT register. 2240 // 2241 //****************************************************************************** 2242 #define GPRCM_EN_APPS_REBOOT_EN_APPS_REBOOT \ 2243 0x00000001 // 1 - When 1, disable the reboot 2244 // of APPS after DevInit is 2245 // completed. In this case, APPS 2246 // will permanantly help in reset. 0 2247 // - When 0, enable the reboot of 2248 // APPS after DevInit is completed. 2249 2250 //****************************************************************************** 2251 // 2252 // The following are defines for the bit fields in the 2253 // GPRCM_O_MEM_APPS_PERIPH_PRESENT register. 2254 // 2255 //****************************************************************************** 2256 #define GPRCM_MEM_APPS_PERIPH_PRESENT_WLAN_GEM_PP \ 2257 0x00010000 // 1 - Enable ; 0 - Disable 2258 2259 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_AES_PP \ 2260 0x00008000 2261 2262 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_DES_PP \ 2263 0x00004000 2264 2265 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_SHA_PP \ 2266 0x00002000 2267 2268 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_CAMERA_PP \ 2269 0x00001000 2270 2271 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MMCHS_PP \ 2272 0x00000800 2273 2274 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCASP_PP \ 2275 0x00000400 2276 2277 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A1_PP \ 2278 0x00000200 2279 2280 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A2_PP \ 2281 0x00000100 2282 2283 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UDMA_PP \ 2284 0x00000080 2285 2286 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_WDOG_PP \ 2287 0x00000040 2288 2289 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A0_PP \ 2290 0x00000020 2291 2292 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A1_PP \ 2293 0x00000010 2294 2295 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A0_PP \ 2296 0x00000008 2297 2298 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A1_PP \ 2299 0x00000004 2300 2301 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A2_PP \ 2302 0x00000002 2303 2304 #define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A3_PP \ 2305 0x00000001 2306 2307 //****************************************************************************** 2308 // 2309 // The following are defines for the bit fields in the 2310 // GPRCM_O_MEM_NWP_PERIPH_PRESENT register. 2311 // 2312 //****************************************************************************** 2313 #define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_ASYNC_BRIDGE_PP \ 2314 0x00000200 2315 2316 #define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N2_PP \ 2317 0x00000100 2318 2319 #define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N0_PP \ 2320 0x00000080 2321 2322 #define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N1_PP \ 2323 0x00000040 2324 2325 #define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_WDOG_PP \ 2326 0x00000020 2327 2328 #define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UDMA_PP \ 2329 0x00000010 2330 2331 #define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N0_PP \ 2332 0x00000008 2333 2334 #define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N1_PP \ 2335 0x00000004 2336 2337 #define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_SSDIO_PP \ 2338 0x00000002 2339 2340 #define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N1_PP \ 2341 0x00000001 2342 2343 //****************************************************************************** 2344 // 2345 // The following are defines for the bit fields in the 2346 // GPRCM_O_MEM_SHARED_PERIPH_PRESENT register. 2347 // 2348 //****************************************************************************** 2349 2350 #define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_MCSPI_PP \ 2351 0x00000040 2352 2353 #define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_I2C_PP \ 2354 0x00000020 2355 2356 #define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_A_PP \ 2357 0x00000010 2358 2359 #define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_B_PP \ 2360 0x00000008 2361 2362 #define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_C_PP \ 2363 0x00000004 2364 2365 #define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_D_PP \ 2366 0x00000002 2367 2368 #define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_E_PP \ 2369 0x00000001 2370 2371 //****************************************************************************** 2372 // 2373 // The following are defines for the bit fields in the 2374 // GPRCM_O_NWP_PWR_STATE register. 2375 // 2376 //****************************************************************************** 2377 #define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_M \ 2378 0x00000F00 // "0000"- PORZ :- NWP is yet to be 2379 // enabled by APPS during powerup 2380 // (from HIB/OFF) ; "0011"- ACTIVE 2381 // :- NWP is enabled, clocks and 2382 // resets to NWP-SubSystem are 2383 // enabled ; "0010"- LPDS :- NWP is 2384 // in LPDS-mode ; Clocks and reset 2385 // to NWP-SubSystem are gated ; 2386 // "0101"- WAIT_FOR_OPP :- NWP is in 2387 // transition from LPDS to ACTIVE, 2388 // where it is waiting for OPP to be 2389 // stable ; "1000"- 2390 // WAKE_TIMER_OPP_REQ :- NWP is in 2391 // transition from LPDS, where the 2392 // wakeup cause is LPDS_Wake timer 2393 // OTHERS : NA 2394 2395 #define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_S 8 2396 #define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_M \ 2397 0x00000007 // "000" - NWP_RUN : NWP is in RUN 2398 // state (default) - Applicable only 2399 // when NWP_PWR_STATE_PS = ACTIVE ; 2400 // "001" - NWP_SLP : NWP is in SLEEP 2401 // state (default) - Applicable only 2402 // when NWP_PWR_STATE_PS = ACTIVE ; 2403 // "010" - NWP_DSLP : NWP is in 2404 // Deep-Sleep state (default) - 2405 // Applicable only when 2406 // NWP_PWR_STATE_PS = ACTIVE ; "011" 2407 // - WAIT_FOR_ACTIVE : NWP is in 2408 // transition from Deep-sleep to 2409 // Run, where it is waiting for OPP 2410 // to be stable ; "100" - 2411 // WAIT_FOR_DSLP_TIMER_WAKE_REQ : 2412 // NWP is in transition from 2413 // Deep-sleep to Run, where the 2414 // wakeup cause is deep-sleep 2415 // wake-timer 2416 2417 #define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_S 0 2418 //****************************************************************************** 2419 // 2420 // The following are defines for the bit fields in the 2421 // GPRCM_O_APPS_PWR_STATE register. 2422 // 2423 //****************************************************************************** 2424 #define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_M \ 2425 0x00000F00 // "0000"- PORZ :- APPS is waiting 2426 // for PLL_clock during powerup 2427 // (from HIB/OFF) ; "0011"- ACTIVE 2428 // :- APPS is enabled, clocks and 2429 // resets to APPS-SubSystem are 2430 // enabled ; APPS might be either in 2431 // Secure or Un-secure mode during 2432 // this state. "1001" - 2433 // SECURE_MODE_LPDS :- While in 2434 // ACTIVE (Secure-mode), APPS had to 2435 // program the DevInit_done bit at 2436 // the end, after which it enters 2437 // into this state, where the reset 2438 // to APPS will be asserted. From 2439 // this state APPS might either 2440 // re-boot itself or enter into LPDS 2441 // depending upon whether the device 2442 // is 3200 or 3100. "0010"- LPDS :- 2443 // APPS is in LPDS-mode ; Clocks and 2444 // reset to APPS-SubSystem are gated 2445 // ; "0101"- WAIT_FOR_OPP :- APPS is 2446 // in transition from LPDS to 2447 // ACTIVE, where it is waiting for 2448 // OPP to be stable ; "1000" - 2449 // WAKE_TIMER_OPP_REQ : APPS is in 2450 // transition from LPDS, where the 2451 // wakeup cause is LPDS_Wake timer ; 2452 // "1010" - WAIT_FOR_PATCH_INIT : 2453 // APPS enters into this state 2454 // during development-mode #3 (SOP = 2455 // 3), where it is waiting for patch 2456 // download to complete and 0x4 hack 2457 // is programmed. OTHERS : NA 2458 2459 #define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_S 8 2460 #define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_M \ 2461 0x00000007 // "000" - APPS_RUN : APPS is in 2462 // RUN state (default) - Applicable 2463 // only when APPS_PWR_STATE_PS = 2464 // ACTIVE ; "001" - APPS_SLP : APPS 2465 // is in SLEEP state (default) - 2466 // Applicable only when 2467 // APPS_PWR_STATE_PS = ACTIVE ; 2468 // "010" - APPS_DSLP : APPS is in 2469 // Deep-Sleep state (default) - 2470 // Applicable only when 2471 // APPS_PWR_STATE_PS = ACTIVE ; 2472 // "011" - WAIT_FOR_ACTIVE : APPS is 2473 // in transition from Deep-sleep to 2474 // Run, where it is waiting for OPP 2475 // to be stable ; "100" - 2476 // WAIT_FOR_DSLP_TIMER_WAKE_REQ : 2477 // APPS is in transition from 2478 // Deep-sleep to Run, where the 2479 // wakeup cause is deep-sleep 2480 // wake-timer 2481 2482 #define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_S 0 2483 //****************************************************************************** 2484 // 2485 // The following are defines for the bit fields in the 2486 // GPRCM_O_MCU_PWR_STATE register. 2487 // 2488 //****************************************************************************** 2489 #define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_M \ 2490 0x0000001F // TBD 2491 2492 #define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_S 0 2493 //****************************************************************************** 2494 // 2495 // The following are defines for the bit fields in the 2496 // GPRCM_O_WTOP_PM_PS register. 2497 // 2498 //****************************************************************************** 2499 #define GPRCM_WTOP_PM_PS_WTOP_PM_PS_M \ 2500 0x00000007 // "011" - WTOP_PM_ACTIVE (Default) 2501 // :- WTOP_Pd is in ACTIVE mode; 2502 // "100" - WTOP_PM_ACTIVE_TO_SLEEP 2503 // :- WTOP_Pd is in transition from 2504 // ACTIVE to SLEEP ; "000" - 2505 // WTOP_PM_SLEEP : WTOP-Pd is in 2506 // Sleep-state ; "100" - 2507 // WTOP_PM_SLEEP_TO_ACTIVE : WTOP_Pd 2508 // is in transition from SLEEP to 2509 // ACTIVE ; "000" - 2510 // WTOP_PM_WAIT_FOR_OPP : Wait for 2511 // OPP to be stable ; 2512 2513 #define GPRCM_WTOP_PM_PS_WTOP_PM_PS_S 0 2514 //****************************************************************************** 2515 // 2516 // The following are defines for the bit fields in the 2517 // GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG register. 2518 // 2519 //****************************************************************************** 2520 #define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE_CTRL \ 2521 0x00000100 // Override control for WTOP PD 2522 // Resetz. When set to 1, 2523 // WTOP_Resetz will be controlled by 2524 // bit [0] 2525 2526 #define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE \ 2527 0x00000001 // Override for WTOP PD Resetz. 2528 // Applicable only when bit[8] is 2529 // set to 1 2530 2531 //****************************************************************************** 2532 // 2533 // The following are defines for the bit fields in the 2534 // GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG register. 2535 // 2536 //****************************************************************************** 2537 #define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE_CTRL \ 2538 0x00000100 // Override control for WELP PD 2539 // Resetz. When set to 1, 2540 // WELP_Resetz will be controlled by 2541 // bit [0] 2542 2543 #define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE \ 2544 0x00000001 // Override for WELP PD Resetz. 2545 // Applicable only when bit[8] is 2546 // set to 1 2547 2548 //****************************************************************************** 2549 // 2550 // The following are defines for the bit fields in the 2551 // GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG register. 2552 // 2553 //****************************************************************************** 2554 #define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE_CTRL \ 2555 0x00000100 // Override control for WL_SDIO 2556 // Resetz. When set to 1, 2557 // WL_SDIO_Resetz will be controlled 2558 // by bit [0] 2559 2560 #define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE \ 2561 0x00000001 // Override for WL_SDIO Resetz. 2562 // Applicable only when bit[8] is 2563 // set to 1 2564 2565 //****************************************************************************** 2566 // 2567 // The following are defines for the bit fields in the 2568 // GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG register. 2569 // 2570 //****************************************************************************** 2571 #define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE_CTRL \ 2572 0x00000100 // Override control for SSDIO 2573 // Resetz. When set to 1, 2574 // SSDIO_Resetz will be controlled 2575 // by bit [0] 2576 2577 #define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE \ 2578 0x00000001 // Override for SSDIO Resetz. 2579 // Applicable only when bit[8] is 2580 // set to 1 2581 2582 //****************************************************************************** 2583 // 2584 // The following are defines for the bit fields in the 2585 // GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG register. 2586 // 2587 //****************************************************************************** 2588 #define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE_CTRL \ 2589 0x00000100 // Override control for MCSPI_N1 2590 // Resetz. When set to 1, 2591 // MCSPI_N1_Resetz will be 2592 // controlled by bit [0] 2593 2594 #define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE \ 2595 0x00000001 // Override for MCSPI_N1 Resetz. 2596 // Applicable only when bit[8] is 2597 // set to 1 2598 2599 //****************************************************************************** 2600 // 2601 // The following are defines for the bit fields in the 2602 // GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG register. 2603 // 2604 //****************************************************************************** 2605 #define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE_CTRL \ 2606 0x00000100 // Override control for TESTCTRL-PD 2607 // Resetz. When set to 1, 2608 // TESTCTRL_Resetz will be 2609 // controlled by bit [0] 2610 2611 #define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE \ 2612 0x00000001 // Override for TESTCTRL Resetz. 2613 // Applicable only when bit[8] is 2614 // set to 1 2615 2616 //****************************************************************************** 2617 // 2618 // The following are defines for the bit fields in the 2619 // GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG register. 2620 // 2621 //****************************************************************************** 2622 #define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE_CTRL \ 2623 0x00000100 // Override control for MCU-PD 2624 // Resetz. When set to 1, MCU_Resetz 2625 // will be controlled by bit [0] 2626 2627 #define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE \ 2628 0x00000001 // Override for MCU Resetz. 2629 // Applicable only when bit[8] is 2630 // set to 1 2631 2632 //****************************************************************************** 2633 // 2634 // The following are defines for the bit fields in the 2635 // GPRCM_O_GPRCM_EFUSE_READ_REG0 register. 2636 // 2637 //****************************************************************************** 2638 #define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_M \ 2639 0xFFFFFFFF // This is ROW_14 [31:0] of 2640 // FUSEFARM. [0:0] : XTAL_IS_26MHZ 2641 // [5:1] : TOP_CLKM_RTRIM[4:0] 2642 // [10:6] : ANA_BGAP_MAG_TRIM[4:0] 2643 // [16:11] : ANA_BGAP_TEMP_TRIM[5:0] 2644 // [20:17] : ANA_BGAP_V2I_TRIM[3:0] 2645 // [25:22] : PROCESS INDICATOR 2646 // [26:26] : Reserved [31:27] : 2647 // FUSEROM Version 2648 2649 #define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_S 0 2650 //****************************************************************************** 2651 // 2652 // The following are defines for the bit fields in the 2653 // GPRCM_O_GPRCM_EFUSE_READ_REG1 register. 2654 // 2655 //****************************************************************************** 2656 #define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_M \ 2657 0x0000FFFF // This is ROW_15[15:0] of FUSEFARM 2658 // 1. NWP Peripheral Present bits 2659 // [15:8] NWP_GPT_N0_PP [15:15] 2660 // NWP_GPT_N1_PP [14:14] NWP_WDOG_PP 2661 // [13:13] NWP_UDMA_PP [12:12] 2662 // NWP_UART_N0_PP [11:11] 2663 // NWP_UART_N1_PP [10:10] 2664 // NWP_SSDIO_PP [9:9] 2665 // NWP_MCSPI_N1_PP [8:8] 2. Shared 2666 // Peripheral Present bits [7:0] 2667 // SHARED SPI PP [6:6] 2668 // SHARED I2C PP [5:5] SHARED 2669 // GPIO-A PP [4:4] SHARED GPIO-B PP 2670 // [3:3] SHARED GPIO-C PP [2:2] 2671 // SHARED GPIO-D PP [1:1] SHARED 2672 // GPIO-E PP [0:0] 2673 2674 #define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_S 0 2675 //****************************************************************************** 2676 // 2677 // The following are defines for the bit fields in the 2678 // GPRCM_O_GPRCM_EFUSE_READ_REG2 register. 2679 // 2680 //****************************************************************************** 2681 #define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_M \ 2682 0xFFFFFFFF // This is ROW_16[15:0] & 2683 // ROW_15[31:16] of FUSEFARM. 2684 // [31:21] - Reserved [20:16] - 2685 // CHIP_ID [15:15] - SSBD SOP 2686 // Control [14:14] - SSBD TAP 2687 // Control [13:2] - APPS Peripheral 2688 // Present bits : APPS_CAMERA_PP 2689 // [13:13] APPS_MMCHS_PP [12:12] 2690 // APPS_MCASP_PP [11:11] 2691 // APPS_MCSPI_A1_PP [10:10] 2692 // APPS_MCSPI_A2_PP [9:9] 2693 // APPS_UDMA_PP [8:8] APPS_WDOG_PP 2694 // [7:7] APPS_UART_A0_PP [6:6] 2695 // APPS_UART_A1_PP [5:5] 2696 // APPS_GPT_A0_PP [4:4] 2697 // APPS_GPT_A1_PP [3:3] 2698 // APPS_GPT_A2_PP [2:2] 2699 // APPS_GPT_A3_PP [1:1] [0:0] - NWP 2700 // Peripheral present bits 2701 // NWP_ACSPI_PP [0:0] 2702 2703 #define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_S 0 2704 //****************************************************************************** 2705 // 2706 // The following are defines for the bit fields in the 2707 // GPRCM_O_GPRCM_EFUSE_READ_REG3 register. 2708 // 2709 //****************************************************************************** 2710 #define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_M \ 2711 0xFFFFFFFF // This is ROW_17[15:0] & 2712 // ROW_16[31:16] of FUSEFARM : 2713 // [31:16] - TEST_TAP_KEY(15:0) 2714 // [15:0] - Reserved 2715 2716 #define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_S 0 2717 //****************************************************************************** 2718 // 2719 // The following are defines for the bit fields in the 2720 // GPRCM_O_WTOP_MEM_RET_CFG register. 2721 // 2722 //****************************************************************************** 2723 #define GPRCM_WTOP_MEM_RET_CFG_WTOP_MEM_RET_CFG \ 2724 0x00000001 // 1 - Soft-compile memories in 2725 // WTOP can be turned-off during 2726 // WTOP-sleep mode ; 0 - 2727 // Soft-compile memories in WTOP 2728 // must be kept on during WTOP-sleep 2729 // mode. 2730 2731 //****************************************************************************** 2732 // 2733 // The following are defines for the bit fields in the 2734 // GPRCM_O_COEX_CLK_SWALLOW_CFG0 register. 2735 // 2736 //****************************************************************************** 2737 #define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_M \ 2738 0x007FFFFF // TBD 2739 2740 #define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_S 0 2741 //****************************************************************************** 2742 // 2743 // The following are defines for the bit fields in the 2744 // GPRCM_O_COEX_CLK_SWALLOW_CFG1 register. 2745 // 2746 //****************************************************************************** 2747 #define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_M \ 2748 0x000FFFFF // TBD 2749 2750 #define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_S 0 2751 //****************************************************************************** 2752 // 2753 // The following are defines for the bit fields in the 2754 // GPRCM_O_COEX_CLK_SWALLOW_CFG2 register. 2755 // 2756 //****************************************************************************** 2757 #define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_M \ 2758 0x00000018 2759 2760 #define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_S 3 2761 #define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_GAIN \ 2762 0x00000004 2763 2764 #define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_ENABLE \ 2765 0x00000002 2766 2767 #define GPRCM_COEX_CLK_SWALLOW_CFG2_SWALLOW_ENABLE \ 2768 0x00000001 // TBD 2769 2770 //****************************************************************************** 2771 // 2772 // The following are defines for the bit fields in the 2773 // GPRCM_O_COEX_CLK_SWALLOW_ENABLE register. 2774 // 2775 //****************************************************************************** 2776 #define GPRCM_COEX_CLK_SWALLOW_ENABLE_COEX_CLK_SWALLOW_ENABLE \ 2777 0x00000001 // 1 - Enable switching of sysclk 2778 // to Coex-clk path ; 0 - Disable 2779 // switching of sysclk to Coex-clk 2780 // path. 2781 2782 //****************************************************************************** 2783 // 2784 // The following are defines for the bit fields in the 2785 // GPRCM_O_DCDC_CLK_GEN_CONFIG register. 2786 // 2787 //****************************************************************************** 2788 #define GPRCM_DCDC_CLK_GEN_CONFIG_DCDC_CLK_ENABLE \ 2789 0x00000001 // 1 - Enable the clock for DCDC 2790 // (PWM-mode) ; 0 - Disable the 2791 // clock for DCDC (PWM-mode) 2792 2793 //****************************************************************************** 2794 // 2795 // The following are defines for the bit fields in the 2796 // GPRCM_O_GPRCM_EFUSE_READ_REG4 register. 2797 // 2798 //****************************************************************************** 2799 #define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_M \ 2800 0x0000FFFF // This corresponds to 2801 // ROW_17[31:16] of the FUSEFARM : 2802 // [15:0] : TEST_TAP_KEY(31:16) 2803 2804 #define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_S 0 2805 //****************************************************************************** 2806 // 2807 // The following are defines for the bit fields in the 2808 // GPRCM_O_GPRCM_EFUSE_READ_REG5 register. 2809 // 2810 //****************************************************************************** 2811 #define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_M \ 2812 0xFFFFFFFF // Corresponds to ROW_18 of 2813 // FUSEFARM. [29:0] - 2814 // MEMSS_COLUMN_SEL_LSW ; [30:30] - 2815 // WLAN GEM DISABLE ; [31:31] - 2816 // SERIAL WIRE JTAG SELECT 2817 2818 #define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_S 0 2819 //****************************************************************************** 2820 // 2821 // The following are defines for the bit fields in the 2822 // GPRCM_O_GPRCM_EFUSE_READ_REG6 register. 2823 // 2824 //****************************************************************************** 2825 #define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_M \ 2826 0x0000FFFF // Corresponds to ROW_19[15:0] of 2827 // FUSEFARM. [15:0] : 2828 // MEMSS_COLUMN_SEL_MSW 2829 2830 #define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_S 0 2831 //****************************************************************************** 2832 // 2833 // The following are defines for the bit fields in the 2834 // GPRCM_O_GPRCM_EFUSE_READ_REG7 register. 2835 // 2836 //****************************************************************************** 2837 #define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_M \ 2838 0xFFFFFFFF // Corresponds to ROW_20[15:0] & 2839 // ROW_19[31:16] of FUSEFARM. 2840 // FLASH_REGION0 2841 2842 #define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_S 0 2843 //****************************************************************************** 2844 // 2845 // The following are defines for the bit fields in the 2846 // GPRCM_O_GPRCM_EFUSE_READ_REG8 register. 2847 // 2848 //****************************************************************************** 2849 #define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_M \ 2850 0xFFFFFFFF // Corresponds to ROW_21[15:0] & 2851 // ROW_20[31:16] of FUSEFARM. 2852 // FLASH_REGION1 2853 2854 #define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_S 0 2855 //****************************************************************************** 2856 // 2857 // The following are defines for the bit fields in the 2858 // GPRCM_O_GPRCM_EFUSE_READ_REG9 register. 2859 // 2860 //****************************************************************************** 2861 #define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_M \ 2862 0xFFFFFFFF // Corresponds to ROW_22[15:0] & 2863 // ROW_21[31:16] of FUSEFARM. 2864 // FLASH_REGION2 2865 2866 #define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_S 0 2867 //****************************************************************************** 2868 // 2869 // The following are defines for the bit fields in the 2870 // GPRCM_O_GPRCM_EFUSE_READ_REG10 register. 2871 // 2872 //****************************************************************************** 2873 #define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_M \ 2874 0xFFFFFFFF // Corresponds to ROW_23[15:0] & 2875 // ROW_22[31:16] of FUSEFARM. 2876 // FLASH_REGION3 2877 2878 #define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_S 0 2879 //****************************************************************************** 2880 // 2881 // The following are defines for the bit fields in the 2882 // GPRCM_O_GPRCM_EFUSE_READ_REG11 register. 2883 // 2884 //****************************************************************************** 2885 #define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_M \ 2886 0xFFFFFFFF // Corresponds to ROW_24[15:0] & 2887 // ROW_23[31:16] of FUSEFARM. 2888 // FLASH_DESCRIPTOR 2889 2890 #define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_S 0 2891 //****************************************************************************** 2892 // 2893 // The following are defines for the bit fields in the 2894 // GPRCM_O_GPRCM_DIEID_READ_REG0 register. 2895 // 2896 //****************************************************************************** 2897 #define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_M \ 2898 0xFFFFFFFF // Corresponds to bits [191:160] of 2899 // the FUSEFARM. This is ROW_5 of 2900 // FUSEFARM [191:160] : [31:0] : 2901 // DIE_ID0 [31:0] : DEVX [11:0] DEVY 2902 // [23:12] DEVWAF [29:24] DEV_SPARE 2903 // [31:30] 2904 2905 #define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_S 0 2906 //****************************************************************************** 2907 // 2908 // The following are defines for the bit fields in the 2909 // GPRCM_O_GPRCM_DIEID_READ_REG1 register. 2910 // 2911 //****************************************************************************** 2912 #define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_M \ 2913 0xFFFFFFFF // Corresponds to bits [223:192] of 2914 // the FUSEFARM. This is ROW_6 of 2915 // FUSEFARM :- DEVLOT [23:0] DEVFAB 2916 // [28:24] DEVFABBE [31:29] 2917 2918 #define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_S 0 2919 //****************************************************************************** 2920 // 2921 // The following are defines for the bit fields in the 2922 // GPRCM_O_GPRCM_DIEID_READ_REG2 register. 2923 // 2924 //****************************************************************************** 2925 #define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_M \ 2926 0xFFFFFFFF // Corresponds to bits [255:224] of 2927 // the FUSEFARM. This is ROW_7 of 2928 // FUSEFARM:- DEVDESREV[4:0] 2929 // Memrepair[5:5] MakeDefined[16:6] 2930 // CHECKSUM[30:17] Reserved : 2931 // [31:31] 2932 2933 #define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_S 0 2934 //****************************************************************************** 2935 // 2936 // The following are defines for the bit fields in the 2937 // GPRCM_O_GPRCM_DIEID_READ_REG3 register. 2938 // 2939 //****************************************************************************** 2940 #define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_M \ 2941 0xFFFFFFFF // Corresponds to bits [287:256] of 2942 // the FUSEFARM. This is ROW_8 of 2943 // FUSEFARM :- DIEID0 - DEVREG 2944 // [31:0] 2945 2946 #define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_S 0 2947 //****************************************************************************** 2948 // 2949 // The following are defines for the bit fields in the 2950 // GPRCM_O_GPRCM_DIEID_READ_REG4 register. 2951 // 2952 //****************************************************************************** 2953 #define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_M \ 2954 0xFFFFFFFF // Corresponds to bits [319:288] of 2955 // the FUSEFARM. This is ROW_9 of 2956 // FUSEFARM :- [7:0] - VBATMON ; 2957 // [13:8] - BUFF_OFFSET ; [15:15] - 2958 // DFT_GXG ; [14:14] - DFT_GLX ; 2959 // [19:16] - PHY ROM Version ; 2960 // [23:20] - MAC ROM Version ; 2961 // [27:24] - NWP ROM Version ; 2962 // [31:28] - APPS ROM Version 2963 2964 #define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_S 0 2965 //****************************************************************************** 2966 // 2967 // The following are defines for the bit fields in the 2968 // GPRCM_O_APPS_SS_OVERRIDES register. 2969 // 2970 //****************************************************************************** 2971 #define GPRCM_APPS_SS_OVERRIDES_reserved_M \ 2972 0xFFFFFC00 2973 2974 #define GPRCM_APPS_SS_OVERRIDES_reserved_S 10 2975 #define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override \ 2976 0x00000200 2977 2978 #define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override_ctrl \ 2979 0x00000100 2980 2981 #define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override \ 2982 0x00000080 2983 2984 #define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override_ctrl \ 2985 0x00000040 2986 2987 #define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override \ 2988 0x00000020 2989 2990 #define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override \ 2991 0x00000010 2992 2993 #define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override \ 2994 0x00000008 2995 2996 #define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override_ctrl \ 2997 0x00000004 2998 2999 #define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override_ctrl \ 3000 0x00000002 3001 3002 #define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override_ctrl \ 3003 0x00000001 3004 3005 //****************************************************************************** 3006 // 3007 // The following are defines for the bit fields in the 3008 // GPRCM_O_NWP_SS_OVERRIDES register. 3009 // 3010 //****************************************************************************** 3011 #define GPRCM_NWP_SS_OVERRIDES_reserved_M \ 3012 0xFFFFFC00 3013 3014 #define GPRCM_NWP_SS_OVERRIDES_reserved_S 10 3015 #define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override \ 3016 0x00000200 3017 3018 #define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override_ctrl \ 3019 0x00000100 3020 3021 #define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override \ 3022 0x00000080 3023 3024 #define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override_ctrl \ 3025 0x00000040 3026 3027 #define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override \ 3028 0x00000020 3029 3030 #define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override \ 3031 0x00000010 3032 3033 #define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override \ 3034 0x00000008 3035 3036 #define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override_ctrl \ 3037 0x00000004 3038 3039 #define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override_ctrl \ 3040 0x00000002 3041 3042 #define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override_ctrl \ 3043 0x00000001 3044 3045 //****************************************************************************** 3046 // 3047 // The following are defines for the bit fields in the 3048 // GPRCM_O_SHARED_SS_OVERRIDES register. 3049 // 3050 //****************************************************************************** 3051 #define GPRCM_SHARED_SS_OVERRIDES_reserved_M \ 3052 0xFFFFFF00 3053 3054 #define GPRCM_SHARED_SS_OVERRIDES_reserved_S 8 3055 #define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override_ctrl \ 3056 0x00000080 3057 3058 #define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override \ 3059 0x00000040 3060 3061 #define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override_ctrl \ 3062 0x00000020 3063 3064 #define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override \ 3065 0x00000010 3066 3067 #define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override \ 3068 0x00000008 3069 3070 #define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override \ 3071 0x00000004 3072 3073 #define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override_ctrl \ 3074 0x00000002 3075 3076 #define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override_ctrl \ 3077 0x00000001 3078 3079 //****************************************************************************** 3080 // 3081 // The following are defines for the bit fields in the 3082 // GPRCM_O_IDMEM_CORE_RST_OVERRIDES register. 3083 // 3084 //****************************************************************************** 3085 #define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_M \ 3086 0xFFFFFF00 3087 3088 #define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_S 8 3089 #define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override \ 3090 0x00000080 3091 3092 #define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override \ 3093 0x00000040 3094 3095 #define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW1 \ 3096 0x00000020 3097 3098 #define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override \ 3099 0x00000010 3100 3101 #define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override_ctrl \ 3102 0x00000008 3103 3104 #define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override_ctrl \ 3105 0x00000004 3106 3107 #define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW0 \ 3108 0x00000002 3109 3110 #define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override_ctrl \ 3111 0x00000001 3112 3113 //****************************************************************************** 3114 // 3115 // The following are defines for the bit fields in the 3116 // GPRCM_O_TOP_DIE_FSM_OVERRIDES register. 3117 // 3118 //****************************************************************************** 3119 #define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_M \ 3120 0xFFFFF000 3121 3122 #define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_S 12 3123 #define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override_ctrl \ 3124 0x00000800 3125 3126 #define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override \ 3127 0x00000400 3128 3129 #define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override \ 3130 0x00000200 3131 3132 #define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override \ 3133 0x00000100 3134 3135 #define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override \ 3136 0x00000080 3137 3138 #define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override \ 3139 0x00000040 3140 3141 #define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override \ 3142 0x00000020 3143 3144 #define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override_ctrl \ 3145 0x00000010 3146 3147 #define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override_ctrl \ 3148 0x00000008 3149 3150 #define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override_ctrl \ 3151 0x00000004 3152 3153 #define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override_ctrl \ 3154 0x00000002 3155 3156 #define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override_ctrl \ 3157 0x00000001 3158 3159 //****************************************************************************** 3160 // 3161 // The following are defines for the bit fields in the 3162 // GPRCM_O_MCU_PSCON_OVERRIDES register. 3163 // 3164 //****************************************************************************** 3165 #define GPRCM_MCU_PSCON_OVERRIDES_reserved_M \ 3166 0xFFF00000 3167 3168 #define GPRCM_MCU_PSCON_OVERRIDES_reserved_S 20 3169 #define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_sleep_override_ctrl \ 3170 0x00080000 3171 3172 #define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override_ctrl \ 3173 0x00040000 3174 3175 #define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_ctrl \ 3176 0x00020000 3177 3178 #define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_ctrl \ 3179 0x00010000 3180 3181 #define GPRCM_MCU_PSCON_OVERRIDES_NU1_M \ 3182 0x0000FC00 3183 3184 #define GPRCM_MCU_PSCON_OVERRIDES_NU1_S 10 3185 #define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_sleep_override \ 3186 0x00000200 3187 3188 #define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override \ 3189 0x00000100 3190 3191 #define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_M \ 3192 0x000000F0 3193 3194 #define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_S 4 3195 #define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_M \ 3196 0x0000000F 3197 3198 #define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_S 0 3199 //****************************************************************************** 3200 // 3201 // The following are defines for the bit fields in the 3202 // GPRCM_O_WTOP_PSCON_OVERRIDES register. 3203 // 3204 //****************************************************************************** 3205 #define GPRCM_WTOP_PSCON_OVERRIDES_reserved_M \ 3206 0xFFC00000 3207 3208 #define GPRCM_WTOP_PSCON_OVERRIDES_reserved_S 22 3209 #define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override_ctrl \ 3210 0x00200000 3211 3212 #define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override_ctrl \ 3213 0x00100000 3214 3215 #define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_ctrl \ 3216 0x00080000 3217 3218 #define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_ctrl \ 3219 0x00040000 3220 3221 #define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override \ 3222 0x00020000 3223 3224 #define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override \ 3225 0x00010000 3226 3227 #define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_M \ 3228 0x0000FF00 3229 3230 #define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_S 8 3231 #define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_M \ 3232 0x000000FF 3233 3234 #define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_S 0 3235 //****************************************************************************** 3236 // 3237 // The following are defines for the bit fields in the 3238 // GPRCM_O_WELP_PSCON_OVERRIDES register. 3239 // 3240 //****************************************************************************** 3241 #define GPRCM_WELP_PSCON_OVERRIDES_reserved_M \ 3242 0xFFFFFFFC 3243 3244 #define GPRCM_WELP_PSCON_OVERRIDES_reserved_S 2 3245 #define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override_ctrl \ 3246 0x00000002 3247 3248 #define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override \ 3249 0x00000001 3250 3251 //****************************************************************************** 3252 // 3253 // The following are defines for the bit fields in the 3254 // GPRCM_O_WL_SDIO_PSCON_OVERRIDES register. 3255 // 3256 //****************************************************************************** 3257 #define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_M \ 3258 0xFFFFFFFC 3259 3260 #define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_S 2 3261 #define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override_ctrl \ 3262 0x00000002 3263 3264 #define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override \ 3265 0x00000001 3266 3267 //****************************************************************************** 3268 // 3269 // The following are defines for the bit fields in the 3270 // GPRCM_O_MCSPI_PSCON_OVERRIDES register. 3271 // 3272 //****************************************************************************** 3273 #define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_M \ 3274 0xFFFFFF00 3275 3276 #define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_S 8 3277 #define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override_ctrl \ 3278 0x00000080 3279 3280 #define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override_ctrl \ 3281 0x00000040 3282 3283 #define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override \ 3284 0x00000020 3285 3286 #define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override \ 3287 0x00000010 3288 3289 #define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override_ctrl \ 3290 0x00000008 3291 3292 #define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override \ 3293 0x00000004 3294 3295 #define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override_ctrl \ 3296 0x00000002 3297 3298 #define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override \ 3299 0x00000001 3300 3301 //****************************************************************************** 3302 // 3303 // The following are defines for the bit fields in the 3304 // GPRCM_O_SSDIO_PSCON_OVERRIDES register. 3305 // 3306 //****************************************************************************** 3307 #define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_M \ 3308 0xFFFFFFFC 3309 3310 #define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_S 2 3311 #define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override_ctrl \ 3312 0x00000002 3313 3314 #define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override \ 3315 0x00000001 3316 3317 3318 3319 3320 #endif // __HW_GPRCM_H__ 3321
