1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_FLASH_CTRL_H__ 35 #define __HW_FLASH_CTRL_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the FLASH_CTRL register offsets. 40 // 41 //***************************************************************************** 42 #define FLASH_CTRL_O_FMA 0x00000000 // Flash Memory Address (FMA) 43 // offset 0x000 During a write 44 // operation this register contains 45 // a 4-byte-aligned address and 46 // specifies where the data is 47 // written. During erase operations 48 // this register contains a 1 49 // KB-aligned CPU byte address and 50 // specifies which block is erased. 51 // Note that the alignment 52 // requirements must be met by 53 // software or the results of the 54 // operation are unpredictable. 55 #define FLASH_CTRL_O_FMD 0x00000004 // Flash Memory Data (FMD) offset 56 // 0x004 This register contains the 57 // data to be written during the 58 // programming cycle or read during 59 // the read cycle. Note that the 60 // contents of this register are 61 // undefined for a read access of an 62 // execute-only block. This register 63 // is not used during erase cycles. 64 #define FLASH_CTRL_O_FMC 0x00000008 // Flash Memory Control (FMC) 65 // offset 0x008 When this register 66 // is written the Flash memory 67 // controller initiates the 68 // appropriate access cycle for the 69 // location specified by the Flash 70 // Memory Address (FMA) register . 71 // If the access is a write access 72 // the data contained in the Flash 73 // Memory Data (FMD) register is 74 // written to the specified address. 75 // This register must be the final 76 // register written and initiates 77 // the memory operation. The four 78 // control bits in the lower byte of 79 // this register are used to 80 // initiate memory operations. 81 #define FLASH_CTRL_O_FCRIS 0x0000000C // Flash Controller Raw Interrupt 82 // Status (FCRIS) offset 0x00C This 83 // register indicates that the Flash 84 // memory controller has an 85 // interrupt condition. An interrupt 86 // is sent to the interrupt 87 // controller only if the 88 // corresponding FCIM register bit 89 // is set. 90 #define FLASH_CTRL_O_FCIM 0x00000010 // Flash Controller Interrupt Mask 91 // (FCIM) offset 0x010 This register 92 // controls whether the Flash memory 93 // controller generates interrupts 94 // to the controller. 95 #define FLASH_CTRL_O_FCMISC 0x00000014 // Flash Controller Masked 96 // Interrupt Status and Clear 97 // (FCMISC) offset 0x014 This 98 // register provides two functions. 99 // First it reports the cause of an 100 // interrupt by indicating which 101 // interrupt source or sources are 102 // signalling the interrupt. Second 103 // it serves as the method to clear 104 // the interrupt reporting. 105 #define FLASH_CTRL_O_FMC2 0x00000020 // Flash Memory Control 2 (FMC2) 106 // offset 0x020 When this register 107 // is written the Flash memory 108 // controller initiates the 109 // appropriate access cycle for the 110 // location specified by the Flash 111 // Memory Address (FMA) register . 112 // If the access is a write access 113 // the data contained in the Flash 114 // Write Buffer (FWB) registers is 115 // written. This register must be 116 // the final register written as it 117 // initiates the memory operation. 118 #define FLASH_CTRL_O_FWBVAL 0x00000030 // Flash Write Buffer Valid 119 // (FWBVAL) offset 0x030 This 120 // register provides a bitwise 121 // status of which FWBn registers 122 // have been written by the 123 // processor since the last write of 124 // the Flash memory write buffer. 125 // The entries with a 1 are written 126 // on the next write of the Flash 127 // memory write buffer. This 128 // register is cleared after the 129 // write operation by hardware. A 130 // protection violation on the write 131 // operation also clears this 132 // status. Software can program the 133 // same 32 words to various Flash 134 // memory locations by setting the 135 // FWB[n] bits after they are 136 // cleared by the write operation. 137 // The next write operation then 138 // uses the same data as the 139 // previous one. In addition if a 140 // FWBn register change should not 141 // be written to Flash memory 142 // software can clear the 143 // corresponding FWB[n] bit to 144 // preserve the existing data when 145 // the next write operation occurs. 146 #define FLASH_CTRL_O_FWB1 0x00000100 // Flash Write Buffer n (FWBn) 147 // offset 0x100 - 0x17C These 32 148 // registers hold the contents of 149 // the data to be written into the 150 // Flash memory on a buffered Flash 151 // memory write operation. The 152 // offset selects one of the 32-bit 153 // registers. Only FWBn registers 154 // that have been updated since the 155 // preceding buffered Flash memory 156 // write operation are written into 157 // the Flash memory so it is not 158 // necessary to write the entire 159 // bank of registers in order to 160 // write 1 or 2 words. The FWBn 161 // registers are written into the 162 // Flash memory with the FWB0 163 // register corresponding to the 164 // address contained in FMA. FWB1 is 165 // written to the address FMA+0x4 166 // etc. Note that only data bits 167 // that are 0 result in the Flash 168 // memory being modified. A data bit 169 // that is 1 leaves the content of 170 // the Flash memory bit at its 171 // previous value. 172 #define FLASH_CTRL_O_FWB2 0x00000104 // Flash Write Buffer n (FWBn) 173 // offset 0x100 - 0x17C These 32 174 // registers hold the contents of 175 // the data to be written into the 176 // Flash memory on a buffered Flash 177 // memory write operation. The 178 // offset selects one of the 32-bit 179 // registers. Only FWBn registers 180 // that have been updated since the 181 // preceding buffered Flash memory 182 // write operation are written into 183 // the Flash memory so it is not 184 // necessary to write the entire 185 // bank of registers in order to 186 // write 1 or 2 words. The FWBn 187 // registers are written into the 188 // Flash memory with the FWB0 189 // register corresponding to the 190 // address contained in FMA. FWB1 is 191 // written to the address FMA+0x4 192 // etc. Note that only data bits 193 // that are 0 result in the Flash 194 // memory being modified. A data bit 195 // that is 1 leaves the content of 196 // the Flash memory bit at its 197 // previous value. 198 #define FLASH_CTRL_O_FWB3 0x00000108 // Flash Write Buffer n (FWBn) 199 // offset 0x100 - 0x17C These 32 200 // registers hold the contents of 201 // the data to be written into the 202 // Flash memory on a buffered Flash 203 // memory write operation. The 204 // offset selects one of the 32-bit 205 // registers. Only FWBn registers 206 // that have been updated since the 207 // preceding buffered Flash memory 208 // write operation are written into 209 // the Flash memory so it is not 210 // necessary to write the entire 211 // bank of registers in order to 212 // write 1 or 2 words. The FWBn 213 // registers are written into the 214 // Flash memory with the FWB0 215 // register corresponding to the 216 // address contained in FMA. FWB1 is 217 // written to the address FMA+0x4 218 // etc. Note that only data bits 219 // that are 0 result in the Flash 220 // memory being modified. A data bit 221 // that is 1 leaves the content of 222 // the Flash memory bit at its 223 // previous value. 224 #define FLASH_CTRL_O_FWB4 0x0000010C // Flash Write Buffer n (FWBn) 225 // offset 0x100 - 0x17C These 32 226 // registers hold the contents of 227 // the data to be written into the 228 // Flash memory on a buffered Flash 229 // memory write operation. The 230 // offset selects one of the 32-bit 231 // registers. Only FWBn registers 232 // that have been updated since the 233 // preceding buffered Flash memory 234 // write operation are written into 235 // the Flash memory so it is not 236 // necessary to write the entire 237 // bank of registers in order to 238 // write 1 or 2 words. The FWBn 239 // registers are written into the 240 // Flash memory with the FWB0 241 // register corresponding to the 242 // address contained in FMA. FWB1 is 243 // written to the address FMA+0x4 244 // etc. Note that only data bits 245 // that are 0 result in the Flash 246 // memory being modified. A data bit 247 // that is 1 leaves the content of 248 // the Flash memory bit at its 249 // previous value. 250 #define FLASH_CTRL_O_FWB5 0x00000110 // Flash Write Buffer n (FWBn) 251 // offset 0x100 - 0x17C These 32 252 // registers hold the contents of 253 // the data to be written into the 254 // Flash memory on a buffered Flash 255 // memory write operation. The 256 // offset selects one of the 32-bit 257 // registers. Only FWBn registers 258 // that have been updated since the 259 // preceding buffered Flash memory 260 // write operation are written into 261 // the Flash memory so it is not 262 // necessary to write the entire 263 // bank of registers in order to 264 // write 1 or 2 words. The FWBn 265 // registers are written into the 266 // Flash memory with the FWB0 267 // register corresponding to the 268 // address contained in FMA. FWB1 is 269 // written to the address FMA+0x4 270 // etc. Note that only data bits 271 // that are 0 result in the Flash 272 // memory being modified. A data bit 273 // that is 1 leaves the content of 274 // the Flash memory bit at its 275 // previous value. 276 #define FLASH_CTRL_O_FWB6 0x00000114 // Flash Write Buffer n (FWBn) 277 // offset 0x100 - 0x17C These 32 278 // registers hold the contents of 279 // the data to be written into the 280 // Flash memory on a buffered Flash 281 // memory write operation. The 282 // offset selects one of the 32-bit 283 // registers. Only FWBn registers 284 // that have been updated since the 285 // preceding buffered Flash memory 286 // write operation are written into 287 // the Flash memory so it is not 288 // necessary to write the entire 289 // bank of registers in order to 290 // write 1 or 2 words. The FWBn 291 // registers are written into the 292 // Flash memory with the FWB0 293 // register corresponding to the 294 // address contained in FMA. FWB1 is 295 // written to the address FMA+0x4 296 // etc. Note that only data bits 297 // that are 0 result in the Flash 298 // memory being modified. A data bit 299 // that is 1 leaves the content of 300 // the Flash memory bit at its 301 // previous value. 302 #define FLASH_CTRL_O_FWB7 0x00000118 // Flash Write Buffer n (FWBn) 303 // offset 0x100 - 0x17C These 32 304 // registers hold the contents of 305 // the data to be written into the 306 // Flash memory on a buffered Flash 307 // memory write operation. The 308 // offset selects one of the 32-bit 309 // registers. Only FWBn registers 310 // that have been updated since the 311 // preceding buffered Flash memory 312 // write operation are written into 313 // the Flash memory so it is not 314 // necessary to write the entire 315 // bank of registers in order to 316 // write 1 or 2 words. The FWBn 317 // registers are written into the 318 // Flash memory with the FWB0 319 // register corresponding to the 320 // address contained in FMA. FWB1 is 321 // written to the address FMA+0x4 322 // etc. Note that only data bits 323 // that are 0 result in the Flash 324 // memory being modified. A data bit 325 // that is 1 leaves the content of 326 // the Flash memory bit at its 327 // previous value. 328 #define FLASH_CTRL_O_FWB8 0x0000011C // Flash Write Buffer n (FWBn) 329 // offset 0x100 - 0x17C These 32 330 // registers hold the contents of 331 // the data to be written into the 332 // Flash memory on a buffered Flash 333 // memory write operation. The 334 // offset selects one of the 32-bit 335 // registers. Only FWBn registers 336 // that have been updated since the 337 // preceding buffered Flash memory 338 // write operation are written into 339 // the Flash memory so it is not 340 // necessary to write the entire 341 // bank of registers in order to 342 // write 1 or 2 words. The FWBn 343 // registers are written into the 344 // Flash memory with the FWB0 345 // register corresponding to the 346 // address contained in FMA. FWB1 is 347 // written to the address FMA+0x4 348 // etc. Note that only data bits 349 // that are 0 result in the Flash 350 // memory being modified. A data bit 351 // that is 1 leaves the content of 352 // the Flash memory bit at its 353 // previous value. 354 #define FLASH_CTRL_O_FWB9 0x00000120 // Flash Write Buffer n (FWBn) 355 // offset 0x100 - 0x17C These 32 356 // registers hold the contents of 357 // the data to be written into the 358 // Flash memory on a buffered Flash 359 // memory write operation. The 360 // offset selects one of the 32-bit 361 // registers. Only FWBn registers 362 // that have been updated since the 363 // preceding buffered Flash memory 364 // write operation are written into 365 // the Flash memory so it is not 366 // necessary to write the entire 367 // bank of registers in order to 368 // write 1 or 2 words. The FWBn 369 // registers are written into the 370 // Flash memory with the FWB0 371 // register corresponding to the 372 // address contained in FMA. FWB1 is 373 // written to the address FMA+0x4 374 // etc. Note that only data bits 375 // that are 0 result in the Flash 376 // memory being modified. A data bit 377 // that is 1 leaves the content of 378 // the Flash memory bit at its 379 // previous value. 380 #define FLASH_CTRL_O_FWB10 0x00000124 // Flash Write Buffer n (FWBn) 381 // offset 0x100 - 0x17C These 32 382 // registers hold the contents of 383 // the data to be written into the 384 // Flash memory on a buffered Flash 385 // memory write operation. The 386 // offset selects one of the 32-bit 387 // registers. Only FWBn registers 388 // that have been updated since the 389 // preceding buffered Flash memory 390 // write operation are written into 391 // the Flash memory so it is not 392 // necessary to write the entire 393 // bank of registers in order to 394 // write 1 or 2 words. The FWBn 395 // registers are written into the 396 // Flash memory with the FWB0 397 // register corresponding to the 398 // address contained in FMA. FWB1 is 399 // written to the address FMA+0x4 400 // etc. Note that only data bits 401 // that are 0 result in the Flash 402 // memory being modified. A data bit 403 // that is 1 leaves the content of 404 // the Flash memory bit at its 405 // previous value. 406 #define FLASH_CTRL_O_FWB11 0x00000128 // Flash Write Buffer n (FWBn) 407 // offset 0x100 - 0x17C These 32 408 // registers hold the contents of 409 // the data to be written into the 410 // Flash memory on a buffered Flash 411 // memory write operation. The 412 // offset selects one of the 32-bit 413 // registers. Only FWBn registers 414 // that have been updated since the 415 // preceding buffered Flash memory 416 // write operation are written into 417 // the Flash memory so it is not 418 // necessary to write the entire 419 // bank of registers in order to 420 // write 1 or 2 words. The FWBn 421 // registers are written into the 422 // Flash memory with the FWB0 423 // register corresponding to the 424 // address contained in FMA. FWB1 is 425 // written to the address FMA+0x4 426 // etc. Note that only data bits 427 // that are 0 result in the Flash 428 // memory being modified. A data bit 429 // that is 1 leaves the content of 430 // the Flash memory bit at its 431 // previous value. 432 #define FLASH_CTRL_O_FWB12 0x0000012C // Flash Write Buffer n (FWBn) 433 // offset 0x100 - 0x17C These 32 434 // registers hold the contents of 435 // the data to be written into the 436 // Flash memory on a buffered Flash 437 // memory write operation. The 438 // offset selects one of the 32-bit 439 // registers. Only FWBn registers 440 // that have been updated since the 441 // preceding buffered Flash memory 442 // write operation are written into 443 // the Flash memory so it is not 444 // necessary to write the entire 445 // bank of registers in order to 446 // write 1 or 2 words. The FWBn 447 // registers are written into the 448 // Flash memory with the FWB0 449 // register corresponding to the 450 // address contained in FMA. FWB1 is 451 // written to the address FMA+0x4 452 // etc. Note that only data bits 453 // that are 0 result in the Flash 454 // memory being modified. A data bit 455 // that is 1 leaves the content of 456 // the Flash memory bit at its 457 // previous value. 458 #define FLASH_CTRL_O_FWB13 0x00000130 // Flash Write Buffer n (FWBn) 459 // offset 0x100 - 0x17C These 32 460 // registers hold the contents of 461 // the data to be written into the 462 // Flash memory on a buffered Flash 463 // memory write operation. The 464 // offset selects one of the 32-bit 465 // registers. Only FWBn registers 466 // that have been updated since the 467 // preceding buffered Flash memory 468 // write operation are written into 469 // the Flash memory so it is not 470 // necessary to write the entire 471 // bank of registers in order to 472 // write 1 or 2 words. The FWBn 473 // registers are written into the 474 // Flash memory with the FWB0 475 // register corresponding to the 476 // address contained in FMA. FWB1 is 477 // written to the address FMA+0x4 478 // etc. Note that only data bits 479 // that are 0 result in the Flash 480 // memory being modified. A data bit 481 // that is 1 leaves the content of 482 // the Flash memory bit at its 483 // previous value. 484 #define FLASH_CTRL_O_FWB14 0x00000134 // Flash Write Buffer n (FWBn) 485 // offset 0x100 - 0x17C These 32 486 // registers hold the contents of 487 // the data to be written into the 488 // Flash memory on a buffered Flash 489 // memory write operation. The 490 // offset selects one of the 32-bit 491 // registers. Only FWBn registers 492 // that have been updated since the 493 // preceding buffered Flash memory 494 // write operation are written into 495 // the Flash memory so it is not 496 // necessary to write the entire 497 // bank of registers in order to 498 // write 1 or 2 words. The FWBn 499 // registers are written into the 500 // Flash memory with the FWB0 501 // register corresponding to the 502 // address contained in FMA. FWB1 is 503 // written to the address FMA+0x4 504 // etc. Note that only data bits 505 // that are 0 result in the Flash 506 // memory being modified. A data bit 507 // that is 1 leaves the content of 508 // the Flash memory bit at its 509 // previous value. 510 #define FLASH_CTRL_O_FWB15 0x00000138 // Flash Write Buffer n (FWBn) 511 // offset 0x100 - 0x17C These 32 512 // registers hold the contents of 513 // the data to be written into the 514 // Flash memory on a buffered Flash 515 // memory write operation. The 516 // offset selects one of the 32-bit 517 // registers. Only FWBn registers 518 // that have been updated since the 519 // preceding buffered Flash memory 520 // write operation are written into 521 // the Flash memory so it is not 522 // necessary to write the entire 523 // bank of registers in order to 524 // write 1 or 2 words. The FWBn 525 // registers are written into the 526 // Flash memory with the FWB0 527 // register corresponding to the 528 // address contained in FMA. FWB1 is 529 // written to the address FMA+0x4 530 // etc. Note that only data bits 531 // that are 0 result in the Flash 532 // memory being modified. A data bit 533 // that is 1 leaves the content of 534 // the Flash memory bit at its 535 // previous value. 536 #define FLASH_CTRL_O_FWB16 0x0000013C // Flash Write Buffer n (FWBn) 537 // offset 0x100 - 0x17C These 32 538 // registers hold the contents of 539 // the data to be written into the 540 // Flash memory on a buffered Flash 541 // memory write operation. The 542 // offset selects one of the 32-bit 543 // registers. Only FWBn registers 544 // that have been updated since the 545 // preceding buffered Flash memory 546 // write operation are written into 547 // the Flash memory so it is not 548 // necessary to write the entire 549 // bank of registers in order to 550 // write 1 or 2 words. The FWBn 551 // registers are written into the 552 // Flash memory with the FWB0 553 // register corresponding to the 554 // address contained in FMA. FWB1 is 555 // written to the address FMA+0x4 556 // etc. Note that only data bits 557 // that are 0 result in the Flash 558 // memory being modified. A data bit 559 // that is 1 leaves the content of 560 // the Flash memory bit at its 561 // previous value. 562 #define FLASH_CTRL_O_FWB17 0x00000140 // Flash Write Buffer n (FWBn) 563 // offset 0x100 - 0x17C These 32 564 // registers hold the contents of 565 // the data to be written into the 566 // Flash memory on a buffered Flash 567 // memory write operation. The 568 // offset selects one of the 32-bit 569 // registers. Only FWBn registers 570 // that have been updated since the 571 // preceding buffered Flash memory 572 // write operation are written into 573 // the Flash memory so it is not 574 // necessary to write the entire 575 // bank of registers in order to 576 // write 1 or 2 words. The FWBn 577 // registers are written into the 578 // Flash memory with the FWB0 579 // register corresponding to the 580 // address contained in FMA. FWB1 is 581 // written to the address FMA+0x4 582 // etc. Note that only data bits 583 // that are 0 result in the Flash 584 // memory being modified. A data bit 585 // that is 1 leaves the content of 586 // the Flash memory bit at its 587 // previous value. 588 #define FLASH_CTRL_O_FWB18 0x00000144 // Flash Write Buffer n (FWBn) 589 // offset 0x100 - 0x17C These 32 590 // registers hold the contents of 591 // the data to be written into the 592 // Flash memory on a buffered Flash 593 // memory write operation. The 594 // offset selects one of the 32-bit 595 // registers. Only FWBn registers 596 // that have been updated since the 597 // preceding buffered Flash memory 598 // write operation are written into 599 // the Flash memory so it is not 600 // necessary to write the entire 601 // bank of registers in order to 602 // write 1 or 2 words. The FWBn 603 // registers are written into the 604 // Flash memory with the FWB0 605 // register corresponding to the 606 // address contained in FMA. FWB1 is 607 // written to the address FMA+0x4 608 // etc. Note that only data bits 609 // that are 0 result in the Flash 610 // memory being modified. A data bit 611 // that is 1 leaves the content of 612 // the Flash memory bit at its 613 // previous value. 614 #define FLASH_CTRL_O_FWB19 0x00000148 // Flash Write Buffer n (FWBn) 615 // offset 0x100 - 0x17C These 32 616 // registers hold the contents of 617 // the data to be written into the 618 // Flash memory on a buffered Flash 619 // memory write operation. The 620 // offset selects one of the 32-bit 621 // registers. Only FWBn registers 622 // that have been updated since the 623 // preceding buffered Flash memory 624 // write operation are written into 625 // the Flash memory so it is not 626 // necessary to write the entire 627 // bank of registers in order to 628 // write 1 or 2 words. The FWBn 629 // registers are written into the 630 // Flash memory with the FWB0 631 // register corresponding to the 632 // address contained in FMA. FWB1 is 633 // written to the address FMA+0x4 634 // etc. Note that only data bits 635 // that are 0 result in the Flash 636 // memory being modified. A data bit 637 // that is 1 leaves the content of 638 // the Flash memory bit at its 639 // previous value. 640 #define FLASH_CTRL_O_FWB20 0x0000014C // Flash Write Buffer n (FWBn) 641 // offset 0x100 - 0x17C These 32 642 // registers hold the contents of 643 // the data to be written into the 644 // Flash memory on a buffered Flash 645 // memory write operation. The 646 // offset selects one of the 32-bit 647 // registers. Only FWBn registers 648 // that have been updated since the 649 // preceding buffered Flash memory 650 // write operation are written into 651 // the Flash memory so it is not 652 // necessary to write the entire 653 // bank of registers in order to 654 // write 1 or 2 words. The FWBn 655 // registers are written into the 656 // Flash memory with the FWB0 657 // register corresponding to the 658 // address contained in FMA. FWB1 is 659 // written to the address FMA+0x4 660 // etc. Note that only data bits 661 // that are 0 result in the Flash 662 // memory being modified. A data bit 663 // that is 1 leaves the content of 664 // the Flash memory bit at its 665 // previous value. 666 #define FLASH_CTRL_O_FWB21 0x00000150 // Flash Write Buffer n (FWBn) 667 // offset 0x100 - 0x17C These 32 668 // registers hold the contents of 669 // the data to be written into the 670 // Flash memory on a buffered Flash 671 // memory write operation. The 672 // offset selects one of the 32-bit 673 // registers. Only FWBn registers 674 // that have been updated since the 675 // preceding buffered Flash memory 676 // write operation are written into 677 // the Flash memory so it is not 678 // necessary to write the entire 679 // bank of registers in order to 680 // write 1 or 2 words. The FWBn 681 // registers are written into the 682 // Flash memory with the FWB0 683 // register corresponding to the 684 // address contained in FMA. FWB1 is 685 // written to the address FMA+0x4 686 // etc. Note that only data bits 687 // that are 0 result in the Flash 688 // memory being modified. A data bit 689 // that is 1 leaves the content of 690 // the Flash memory bit at its 691 // previous value. 692 #define FLASH_CTRL_O_FWB22 0x00000154 // Flash Write Buffer n (FWBn) 693 // offset 0x100 - 0x17C These 32 694 // registers hold the contents of 695 // the data to be written into the 696 // Flash memory on a buffered Flash 697 // memory write operation. The 698 // offset selects one of the 32-bit 699 // registers. Only FWBn registers 700 // that have been updated since the 701 // preceding buffered Flash memory 702 // write operation are written into 703 // the Flash memory so it is not 704 // necessary to write the entire 705 // bank of registers in order to 706 // write 1 or 2 words. The FWBn 707 // registers are written into the 708 // Flash memory with the FWB0 709 // register corresponding to the 710 // address contained in FMA. FWB1 is 711 // written to the address FMA+0x4 712 // etc. Note that only data bits 713 // that are 0 result in the Flash 714 // memory being modified. A data bit 715 // that is 1 leaves the content of 716 // the Flash memory bit at its 717 // previous value. 718 #define FLASH_CTRL_O_FWB23 0x00000158 // Flash Write Buffer n (FWBn) 719 // offset 0x100 - 0x17C These 32 720 // registers hold the contents of 721 // the data to be written into the 722 // Flash memory on a buffered Flash 723 // memory write operation. The 724 // offset selects one of the 32-bit 725 // registers. Only FWBn registers 726 // that have been updated since the 727 // preceding buffered Flash memory 728 // write operation are written into 729 // the Flash memory so it is not 730 // necessary to write the entire 731 // bank of registers in order to 732 // write 1 or 2 words. The FWBn 733 // registers are written into the 734 // Flash memory with the FWB0 735 // register corresponding to the 736 // address contained in FMA. FWB1 is 737 // written to the address FMA+0x4 738 // etc. Note that only data bits 739 // that are 0 result in the Flash 740 // memory being modified. A data bit 741 // that is 1 leaves the content of 742 // the Flash memory bit at its 743 // previous value. 744 #define FLASH_CTRL_O_FWB24 0x0000015C // Flash Write Buffer n (FWBn) 745 // offset 0x100 - 0x17C These 32 746 // registers hold the contents of 747 // the data to be written into the 748 // Flash memory on a buffered Flash 749 // memory write operation. The 750 // offset selects one of the 32-bit 751 // registers. Only FWBn registers 752 // that have been updated since the 753 // preceding buffered Flash memory 754 // write operation are written into 755 // the Flash memory so it is not 756 // necessary to write the entire 757 // bank of registers in order to 758 // write 1 or 2 words. The FWBn 759 // registers are written into the 760 // Flash memory with the FWB0 761 // register corresponding to the 762 // address contained in FMA. FWB1 is 763 // written to the address FMA+0x4 764 // etc. Note that only data bits 765 // that are 0 result in the Flash 766 // memory being modified. A data bit 767 // that is 1 leaves the content of 768 // the Flash memory bit at its 769 // previous value. 770 #define FLASH_CTRL_O_FWB25 0x00000160 // Flash Write Buffer n (FWBn) 771 // offset 0x100 - 0x17C These 32 772 // registers hold the contents of 773 // the data to be written into the 774 // Flash memory on a buffered Flash 775 // memory write operation. The 776 // offset selects one of the 32-bit 777 // registers. Only FWBn registers 778 // that have been updated since the 779 // preceding buffered Flash memory 780 // write operation are written into 781 // the Flash memory so it is not 782 // necessary to write the entire 783 // bank of registers in order to 784 // write 1 or 2 words. The FWBn 785 // registers are written into the 786 // Flash memory with the FWB0 787 // register corresponding to the 788 // address contained in FMA. FWB1 is 789 // written to the address FMA+0x4 790 // etc. Note that only data bits 791 // that are 0 result in the Flash 792 // memory being modified. A data bit 793 // that is 1 leaves the content of 794 // the Flash memory bit at its 795 // previous value. 796 #define FLASH_CTRL_O_FWB26 0x00000164 // Flash Write Buffer n (FWBn) 797 // offset 0x100 - 0x17C These 32 798 // registers hold the contents of 799 // the data to be written into the 800 // Flash memory on a buffered Flash 801 // memory write operation. The 802 // offset selects one of the 32-bit 803 // registers. Only FWBn registers 804 // that have been updated since the 805 // preceding buffered Flash memory 806 // write operation are written into 807 // the Flash memory so it is not 808 // necessary to write the entire 809 // bank of registers in order to 810 // write 1 or 2 words. The FWBn 811 // registers are written into the 812 // Flash memory with the FWB0 813 // register corresponding to the 814 // address contained in FMA. FWB1 is 815 // written to the address FMA+0x4 816 // etc. Note that only data bits 817 // that are 0 result in the Flash 818 // memory being modified. A data bit 819 // that is 1 leaves the content of 820 // the Flash memory bit at its 821 // previous value. 822 #define FLASH_CTRL_O_FWB27 0x00000168 // Flash Write Buffer n (FWBn) 823 // offset 0x100 - 0x17C These 32 824 // registers hold the contents of 825 // the data to be written into the 826 // Flash memory on a buffered Flash 827 // memory write operation. The 828 // offset selects one of the 32-bit 829 // registers. Only FWBn registers 830 // that have been updated since the 831 // preceding buffered Flash memory 832 // write operation are written into 833 // the Flash memory so it is not 834 // necessary to write the entire 835 // bank of registers in order to 836 // write 1 or 2 words. The FWBn 837 // registers are written into the 838 // Flash memory with the FWB0 839 // register corresponding to the 840 // address contained in FMA. FWB1 is 841 // written to the address FMA+0x4 842 // etc. Note that only data bits 843 // that are 0 result in the Flash 844 // memory being modified. A data bit 845 // that is 1 leaves the content of 846 // the Flash memory bit at its 847 // previous value. 848 #define FLASH_CTRL_O_FWB28 0x0000016C // Flash Write Buffer n (FWBn) 849 // offset 0x100 - 0x17C These 32 850 // registers hold the contents of 851 // the data to be written into the 852 // Flash memory on a buffered Flash 853 // memory write operation. The 854 // offset selects one of the 32-bit 855 // registers. Only FWBn registers 856 // that have been updated since the 857 // preceding buffered Flash memory 858 // write operation are written into 859 // the Flash memory so it is not 860 // necessary to write the entire 861 // bank of registers in order to 862 // write 1 or 2 words. The FWBn 863 // registers are written into the 864 // Flash memory with the FWB0 865 // register corresponding to the 866 // address contained in FMA. FWB1 is 867 // written to the address FMA+0x4 868 // etc. Note that only data bits 869 // that are 0 result in the Flash 870 // memory being modified. A data bit 871 // that is 1 leaves the content of 872 // the Flash memory bit at its 873 // previous value. 874 #define FLASH_CTRL_O_FWB29 0x00000170 // Flash Write Buffer n (FWBn) 875 // offset 0x100 - 0x17C These 32 876 // registers hold the contents of 877 // the data to be written into the 878 // Flash memory on a buffered Flash 879 // memory write operation. The 880 // offset selects one of the 32-bit 881 // registers. Only FWBn registers 882 // that have been updated since the 883 // preceding buffered Flash memory 884 // write operation are written into 885 // the Flash memory so it is not 886 // necessary to write the entire 887 // bank of registers in order to 888 // write 1 or 2 words. The FWBn 889 // registers are written into the 890 // Flash memory with the FWB0 891 // register corresponding to the 892 // address contained in FMA. FWB1 is 893 // written to the address FMA+0x4 894 // etc. Note that only data bits 895 // that are 0 result in the Flash 896 // memory being modified. A data bit 897 // that is 1 leaves the content of 898 // the Flash memory bit at its 899 // previous value. 900 #define FLASH_CTRL_O_FWB30 0x00000174 // Flash Write Buffer n (FWBn) 901 // offset 0x100 - 0x17C These 32 902 // registers hold the contents of 903 // the data to be written into the 904 // Flash memory on a buffered Flash 905 // memory write operation. The 906 // offset selects one of the 32-bit 907 // registers. Only FWBn registers 908 // that have been updated since the 909 // preceding buffered Flash memory 910 // write operation are written into 911 // the Flash memory so it is not 912 // necessary to write the entire 913 // bank of registers in order to 914 // write 1 or 2 words. The FWBn 915 // registers are written into the 916 // Flash memory with the FWB0 917 // register corresponding to the 918 // address contained in FMA. FWB1 is 919 // written to the address FMA+0x4 920 // etc. Note that only data bits 921 // that are 0 result in the Flash 922 // memory being modified. A data bit 923 // that is 1 leaves the content of 924 // the Flash memory bit at its 925 // previous value. 926 #define FLASH_CTRL_O_FWB31 0x00000178 // Flash Write Buffer n (FWBn) 927 // offset 0x100 - 0x17C These 32 928 // registers hold the contents of 929 // the data to be written into the 930 // Flash memory on a buffered Flash 931 // memory write operation. The 932 // offset selects one of the 32-bit 933 // registers. Only FWBn registers 934 // that have been updated since the 935 // preceding buffered Flash memory 936 // write operation are written into 937 // the Flash memory so it is not 938 // necessary to write the entire 939 // bank of registers in order to 940 // write 1 or 2 words. The FWBn 941 // registers are written into the 942 // Flash memory with the FWB0 943 // register corresponding to the 944 // address contained in FMA. FWB1 is 945 // written to the address FMA+0x4 946 // etc. Note that only data bits 947 // that are 0 result in the Flash 948 // memory being modified. A data bit 949 // that is 1 leaves the content of 950 // the Flash memory bit at its 951 // previous value. 952 #define FLASH_CTRL_O_FWB32 0x0000017C // Flash Write Buffer n (FWBn) 953 // offset 0x100 - 0x17C These 32 954 // registers hold the contents of 955 // the data to be written into the 956 // Flash memory on a buffered Flash 957 // memory write operation. The 958 // offset selects one of the 32-bit 959 // registers. Only FWBn registers 960 // that have been updated since the 961 // preceding buffered Flash memory 962 // write operation are written into 963 // the Flash memory so it is not 964 // necessary to write the entire 965 // bank of registers in order to 966 // write 1 or 2 words. The FWBn 967 // registers are written into the 968 // Flash memory with the FWB0 969 // register corresponding to the 970 // address contained in FMA. FWB1 is 971 // written to the address FMA+0x4 972 // etc. Note that only data bits 973 // that are 0 result in the Flash 974 // memory being modified. A data bit 975 // that is 1 leaves the content of 976 // the Flash memory bit at its 977 // previous value. 978 #define FLASH_CTRL_O_FSIZE 0x00000FC0 // Flash Size (FSIZE) offset 0xFC0 979 // This register indicates the size 980 // of the on-chip Flash memory. 981 // Important: This register should 982 // be used to determine the size of 983 // the Flash memory that is 984 // implemented on this 985 // microcontroller. However to 986 // support legacy software the DC0 987 // register is available. A read of 988 // the DC0 register correctly 989 // identifies legacy memory sizes. 990 // Software must use the FSIZE 991 // register for memory sizes that 992 // are not listed in the DC0 993 // register description. 994 #define FLASH_CTRL_O_SSIZE 0x00000FC4 // SRAM Size (SSIZE) offset 0xFC4 995 // This register indicates the size 996 // of the on-chip SRAM. Important: 997 // This register should be used to 998 // determine the size of the SRAM 999 // that is implemented on this 1000 // microcontroller. However to 1001 // support legacy software the DC0 1002 // register is available. A read of 1003 // the DC0 register correctly 1004 // identifies legacy memory sizes. 1005 // Software must use the SSIZE 1006 // register for memory sizes that 1007 // are not listed in the DC0 1008 // register description. 1009 1010 1011 1012 //****************************************************************************** 1013 // 1014 // The following are defines for the bit fields in the FLASH_CTRL_O_FMA register. 1015 // 1016 //****************************************************************************** 1017 #define FLASH_CTRL_FMA_OFFSET_M 0x0003FFFF // Address Offset Address offset in 1018 // Flash memory where operation is 1019 // performed except for nonvolatile 1020 // registers 1021 #define FLASH_CTRL_FMA_OFFSET_S 0 1022 //****************************************************************************** 1023 // 1024 // The following are defines for the bit fields in the FLASH_CTRL_O_FMD register. 1025 // 1026 //****************************************************************************** 1027 #define FLASH_CTRL_FMD_DATA_M 0xFFFFFFFF // Data Value Data value for write 1028 // operation. 1029 #define FLASH_CTRL_FMD_DATA_S 0 1030 //****************************************************************************** 1031 // 1032 // The following are defines for the bit fields in the FLASH_CTRL_O_FMC register. 1033 // 1034 //****************************************************************************** 1035 #define FLASH_CTRL_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This 1036 // field contains a write key which 1037 // is used to minimize the incidence 1038 // of accidental Flash memory 1039 // writes. The value 0xA442 must be 1040 // written into this field for a 1041 // Flash memory write to occur. 1042 // Writes to the FMC register 1043 // without this WRKEY value are 1044 // ignored. A read of this field 1045 // returns the value 0. 1046 #define FLASH_CTRL_FMC_WRKEY_S 16 1047 #define FLASH_CTRL_FMC_COMT 0x00000008 // Commit Register Value This bit 1048 // is used to commit writes to 1049 // Flash-memory-resident registers 1050 // and to monitor the progress of 1051 // that process. Value Description 1 1052 // Set this bit to commit (write) 1053 // the register value to a 1054 // Flash-memory-resident register. 1055 // When read a 1 indicates that the 1056 // previous commit access is not 1057 // complete. 0 A write of 0 has no 1058 // effect on the state of this bit. 1059 // When read a 0 indicates that the 1060 // previous commit access is 1061 // complete. 1062 #define FLASH_CTRL_FMC_MERASE1 0x00000004 // Mass Erase Flash Memory This bit 1063 // is used to mass erase the Flash 1064 // main memory and to monitor the 1065 // progress of that process. Value 1066 // Description 1 Set this bit to 1067 // erase the Flash main memory. When 1068 // read a 1 indicates that the 1069 // previous mass erase access is not 1070 // complete. 0 A write of 0 has no 1071 // effect on the state of this bit. 1072 // When read a 0 indicates that the 1073 // previous mass erase access is 1074 // complete. 1075 #define FLASH_CTRL_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory 1076 // This bit is used to erase a page 1077 // of Flash memory and to monitor 1078 // the progress of that process. 1079 // Value Description 1 Set this bit 1080 // to erase the Flash memory page 1081 // specified by the contents of the 1082 // FMA register. When read a 1 1083 // indicates that the previous page 1084 // erase access is not complete. 0 A 1085 // write of 0 has no effect on the 1086 // state of this bit. When read a 0 1087 // indicates that the previous page 1088 // erase access is complete. 1089 #define FLASH_CTRL_FMC_WRITE 0x00000001 // Write a Word into Flash Memory 1090 // This bit is used to write a word 1091 // into Flash memory and to monitor 1092 // the progress of that process. 1093 // Value Description 1 Set this bit 1094 // to write the data stored in the 1095 // FMD register into the Flash 1096 // memory location specified by the 1097 // contents of the FMA register. 1098 // When read a 1 indicates that the 1099 // write update access is not 1100 // complete. 0 A write of 0 has no 1101 // effect on the state of this bit. 1102 // When read a 0 indicates that the 1103 // previous write update access is 1104 // complete. 1105 //****************************************************************************** 1106 // 1107 // The following are defines for the bit fields in the 1108 // FLASH_CTRL_O_FCRIS register. 1109 // 1110 //****************************************************************************** 1111 #define FLASH_CTRL_FCRIS_PROGRIS \ 1112 0x00002000 // Program Verify Error Raw 1113 // Interrupt Status Value 1114 // Description 1 An interrupt is 1115 // pending because the verify of a 1116 // PROGRAM operation failed. 0 An 1117 // interrupt has not occurred. This 1118 // bit is cleared by writing a 1 to 1119 // the PROGMISC bit in the FCMISC 1120 // register. 1121 1122 #define FLASH_CTRL_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt 1123 // Status Value Description 1 An 1124 // interrupt is pending because the 1125 // verify of an ERASE operation 1126 // failed. 0 An interrupt has not 1127 // occurred. This bit is cleared by 1128 // writing a 1 to the ERMISC bit in 1129 // the FCMISC register. 1130 #define FLASH_CTRL_FCRIS_INVDRIS \ 1131 0x00000400 // Invalid Data Raw Interrupt 1132 // Status Value Description 1 An 1133 // interrupt is pending because a 1134 // bit that was previously 1135 // programmed as a 0 is now being 1136 // requested to be programmed as a 1137 // 1. 0 An interrupt has not 1138 // occurred. This bit is cleared by 1139 // writing a 1 to the INVMISC bit in 1140 // the FCMISC register. 1141 1142 #define FLASH_CTRL_FCRIS_VOLTRIS \ 1143 0x00000200 // Pump Voltage Raw Interrupt 1144 // Status Value Description 1 An 1145 // interrupt is pending because the 1146 // regulated voltage of the pump 1147 // went out of spec during the Flash 1148 // operation and the operation was 1149 // terminated. 0 An interrupt has 1150 // not occurred. This bit is cleared 1151 // by writing a 1 to the VOLTMISC 1152 // bit in the FCMISC register. 1153 1154 #define FLASH_CTRL_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status This 1155 // bit provides status EEPROM 1156 // operation. Value Description 1 An 1157 // EEPROM interrupt has occurred. 0 1158 // An EEPROM interrupt has not 1159 // occurred. This bit is cleared by 1160 // writing a 1 to the EMISC bit in 1161 // the FCMISC register. 1162 #define FLASH_CTRL_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status 1163 // This bit provides status on 1164 // programming cycles which are 1165 // write or erase actions generated 1166 // through the FMC or FMC2 register 1167 // bits (see page 537 and page 549). 1168 // Value Description 1 The 1169 // programming or erase cycle has 1170 // completed. 0 The programming or 1171 // erase cycle has not completed. 1172 // This status is sent to the 1173 // interrupt controller when the 1174 // PMASK bit in the FCIM register is 1175 // set. This bit is cleared by 1176 // writing a 1 to the PMISC bit in 1177 // the FCMISC register. 1178 #define FLASH_CTRL_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status 1179 // Value Description 1 A program or 1180 // erase action was attempted on a 1181 // block of Flash memory that 1182 // contradicts the protection policy 1183 // for that block as set in the 1184 // FMPPEn registers. 0 No access has 1185 // tried to improperly program or 1186 // erase the Flash memory. This 1187 // status is sent to the interrupt 1188 // controller when the AMASK bit in 1189 // the FCIM register is set. This 1190 // bit is cleared by writing a 1 to 1191 // the AMISC bit in the FCMISC 1192 // register. 1193 //****************************************************************************** 1194 // 1195 // The following are defines for the bit fields in the FLASH_CTRL_O_FCIM register. 1196 // 1197 //****************************************************************************** 1198 #define FLASH_CTRL_FCIM_ILLMASK 0x00004000 // Illegal Address Interrupt Mask 1199 // Value Description 1 An interrupt 1200 // is sent to the interrupt 1201 // controller when the ILLARIS bit 1202 // is set. 0 The ILLARIS interrupt 1203 // is suppressed and not sent to the 1204 // interrupt controller. 1205 #define FLASH_CTRL_FCIM_PROGMASK \ 1206 0x00002000 // PROGVER Interrupt Mask Value 1207 // Description 1 An interrupt is 1208 // sent to the interrupt controller 1209 // when the PROGRIS bit is set. 0 1210 // The PROGRIS interrupt is 1211 // suppressed and not sent to the 1212 // interrupt controller. 1213 1214 #define FLASH_CTRL_FCIM_PREMASK 0x00001000 // PREVER Interrupt Mask Value 1215 // Description 1 An interrupt is 1216 // sent to the interrupt controller 1217 // when the PRERIS bit is set. 0 The 1218 // PRERIS interrupt is suppressed 1219 // and not sent to the interrupt 1220 // controller. 1221 #define FLASH_CTRL_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask Value 1222 // Description 1 An interrupt is 1223 // sent to the interrupt controller 1224 // when the ERRIS bit is set. 0 The 1225 // ERRIS interrupt is suppressed and 1226 // not sent to the interrupt 1227 // controller. 1228 #define FLASH_CTRL_FCIM_INVDMASK \ 1229 0x00000400 // Invalid Data Interrupt Mask 1230 // Value Description 1 An interrupt 1231 // is sent to the interrupt 1232 // controller when the INVDRIS bit 1233 // is set. 0 The INVDRIS interrupt 1234 // is suppressed and not sent to the 1235 // interrupt controller. 1236 1237 #define FLASH_CTRL_FCIM_VOLTMASK \ 1238 0x00000200 // VOLT Interrupt Mask Value 1239 // Description 1 An interrupt is 1240 // sent to the interrupt controller 1241 // when the VOLTRIS bit is set. 0 1242 // The VOLTRIS interrupt is 1243 // suppressed and not sent to the 1244 // interrupt controller. 1245 1246 #define FLASH_CTRL_FCIM_LOCKMASK \ 1247 0x00000100 // LOCK Interrupt Mask Value 1248 // Description 1 An interrupt is 1249 // sent to the interrupt controller 1250 // when the LOCKRIS bit is set. 0 1251 // The LOCKRIS interrupt is 1252 // suppressed and not sent to the 1253 // interrupt controller. 1254 1255 #define FLASH_CTRL_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask Value 1256 // Description 1 An interrupt is 1257 // sent to the interrupt controller 1258 // when the ERIS bit is set. 0 The 1259 // ERIS interrupt is suppressed and 1260 // not sent to the interrupt 1261 // controller. 1262 #define FLASH_CTRL_FCIM_PMASK 0x00000002 // Programming Interrupt Mask This 1263 // bit controls the reporting of the 1264 // programming raw interrupt status 1265 // to the interrupt controller. 1266 // Value Description 1 An interrupt 1267 // is sent to the interrupt 1268 // controller when the PRIS bit is 1269 // set. 0 The PRIS interrupt is 1270 // suppressed and not sent to the 1271 // interrupt controller. 1272 #define FLASH_CTRL_FCIM_AMASK 0x00000001 // Access Interrupt Mask This bit 1273 // controls the reporting of the 1274 // access raw interrupt status to 1275 // the interrupt controller. Value 1276 // Description 1 An interrupt is 1277 // sent to the interrupt controller 1278 // when the ARIS bit is set. 0 The 1279 // ARIS interrupt is suppressed and 1280 // not sent to the interrupt 1281 // controller. 1282 //****************************************************************************** 1283 // 1284 // The following are defines for the bit fields in the 1285 // FLASH_CTRL_O_FCMISC register. 1286 // 1287 //****************************************************************************** 1288 #define FLASH_CTRL_FCMISC_ILLMISC \ 1289 0x00004000 // Illegal Address Masked Interrupt 1290 // Status and Clear Value 1291 // Description 1 When read a 1 1292 // indicates that an unmasked 1293 // interrupt was signaled. Writing a 1294 // 1 to this bit clears ILLAMISC and 1295 // also the ILLARIS bit in the FCRIS 1296 // register (see page 540). 0 When 1297 // read a 0 indicates that an 1298 // interrupt has not occurred. A 1299 // write of 0 has no effect on the 1300 // state of this bit. 1301 1302 #define FLASH_CTRL_FCMISC_PROGMISC \ 1303 0x00002000 // PROGVER Masked Interrupt Status 1304 // and Clear Value Description 1 1305 // When read a 1 indicates that an 1306 // unmasked interrupt was signaled. 1307 // Writing a 1 to this bit clears 1308 // PROGMISC and also the PROGRIS bit 1309 // in the FCRIS register (see page 1310 // 540). 0 When read a 0 indicates 1311 // that an interrupt has not 1312 // occurred. A write of 0 has no 1313 // effect on the state of this bit. 1314 1315 #define FLASH_CTRL_FCMISC_PREMISC \ 1316 0x00001000 // PREVER Masked Interrupt Status 1317 // and Clear Value Description 1 1318 // When read a 1 indicates that an 1319 // unmasked interrupt was signaled. 1320 // Writing a 1 to this bit clears 1321 // PREMISC and also the PRERIS bit 1322 // in the FCRIS register . 0 When 1323 // read a 0 indicates that an 1324 // interrupt has not occurred. A 1325 // write of 0 has no effect on the 1326 // state of this bit. 1327 1328 #define FLASH_CTRL_FCMISC_ERMISC \ 1329 0x00000800 // ERVER Masked Interrupt Status 1330 // and Clear Value Description 1 1331 // When read a 1 indicates that an 1332 // unmasked interrupt was signaled. 1333 // Writing a 1 to this bit clears 1334 // ERMISC and also the ERRIS bit in 1335 // the FCRIS register 0 When read a 1336 // 0 indicates that an interrupt has 1337 // not occurred. A write of 0 has no 1338 // effect on the state of this bit. 1339 1340 #define FLASH_CTRL_FCMISC_INVDMISC \ 1341 0x00000400 // Invalid Data Masked Interrupt 1342 // Status and Clear Value 1343 // Description 1 When read a 1 1344 // indicates that an unmasked 1345 // interrupt was signaled. Writing a 1346 // 1 to this bit clears INVDMISC and 1347 // also the INVDRIS bit in the FCRIS 1348 // register (see page 540). 0 When 1349 // read a 0 indicates that an 1350 // interrupt has not occurred. A 1351 // write of 0 has no effect on the 1352 // state of this bit. 1353 1354 #define FLASH_CTRL_FCMISC_VOLTMISC \ 1355 0x00000200 // VOLT Masked Interrupt Status and 1356 // Clear Value Description 1 When 1357 // read a 1 indicates that an 1358 // unmasked interrupt was signaled. 1359 // Writing a 1 to this bit clears 1360 // VOLTMISC and also the VOLTRIS bit 1361 // in the FCRIS register (see page 1362 // 540). 0 When read a 0 indicates 1363 // that an interrupt has not 1364 // occurred. A write of 0 has no 1365 // effect on the state of this bit. 1366 1367 #define FLASH_CTRL_FCMISC_LOCKMISC \ 1368 0x00000100 // LOCK Masked Interrupt Status and 1369 // Clear Value Description 1 When 1370 // read a 1 indicates that an 1371 // unmasked interrupt was signaled. 1372 // Writing a 1 to this bit clears 1373 // LOCKMISC and also the LOCKRIS bit 1374 // in the FCRIS register (see page 1375 // 540). 0 When read a 0 indicates 1376 // that an interrupt has not 1377 // occurred. A write of 0 has no 1378 // effect on the state of this bit. 1379 1380 #define FLASH_CTRL_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status 1381 // and Clear Value Description 1 1382 // When read a 1 indicates that an 1383 // unmasked interrupt was signaled. 1384 // Writing a 1 to this bit clears 1385 // EMISC and also the ERIS bit in 1386 // the FCRIS register 0 When read a 1387 // 0 indicates that an interrupt has 1388 // not occurred. A write of 0 has no 1389 // effect on the state of this bit. 1390 #define FLASH_CTRL_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt 1391 // Status and Clear Value 1392 // Description 1 When read a 1 1393 // indicates that an unmasked 1394 // interrupt was signaled because a 1395 // programming cycle completed. 1396 // Writing a 1 to this bit clears 1397 // PMISC and also the PRIS bit in 1398 // the FCRIS register 0 When read a 1399 // 0 indicates that a programming 1400 // cycle complete interrupt has not 1401 // occurred. A write of 0 has no 1402 // effect on the state of this bit. 1403 #define FLASH_CTRL_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status 1404 // and Clear Value Description 1 1405 // When read a 1 indicates that an 1406 // unmasked interrupt was signaled 1407 // because a program or erase action 1408 // was attempted on a block of Flash 1409 // memory that contradicts the 1410 // protection policy for that block 1411 // as set in the FMPPEn registers. 1412 // Writing a 1 to this bit clears 1413 // AMISC and also the ARIS bit in 1414 // the FCRIS register 0 When read a 1415 // 0 indicates that no improper 1416 // accesses have occurred. A write 1417 // of 0 has no effect on the state 1418 // of this bit. 1419 //****************************************************************************** 1420 // 1421 // The following are defines for the bit fields in the FLASH_CTRL_O_FMC2 register. 1422 // 1423 //****************************************************************************** 1424 #define FLASH_CTRL_FMC2_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This 1425 // field contains a write key which 1426 // is used to minimize the incidence 1427 // of accidental Flash memory 1428 // writes. The value 0xA442 must be 1429 // written into this field for a 1430 // write to occur. Writes to the 1431 // FMC2 register without this WRKEY 1432 // value are ignored. A read of this 1433 // field returns the value 0. 1434 #define FLASH_CTRL_FMC2_WRKEY_S 16 1435 #define FLASH_CTRL_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write This 1436 // bit is used to start a buffered 1437 // write to Flash memory. Value 1438 // Description 1 Set this bit to 1439 // write the data stored in the FWBn 1440 // registers to the location 1441 // specified by the contents of the 1442 // FMA register. When read a 1 1443 // indicates that the previous 1444 // buffered Flash memory write 1445 // access is not complete. 0 A write 1446 // of 0 has no effect on the state 1447 // of this bit. When read a 0 1448 // indicates that the previous 1449 // buffered Flash memory write 1450 // access is complete. 1451 //****************************************************************************** 1452 // 1453 // The following are defines for the bit fields in the 1454 // FLASH_CTRL_O_FWBVAL register. 1455 // 1456 //****************************************************************************** 1457 #define FLASH_CTRL_FWBVAL_FWBN_M \ 1458 0xFFFFFFFF // Flash Memory Write Buffer Value 1459 // Description 1 The corresponding 1460 // FWBn register has been updated 1461 // since the last buffer write 1462 // operation and is ready to be 1463 // written to Flash memory. 0 The 1464 // corresponding FWBn register has 1465 // no new data to be written. Bit 0 1466 // corresponds to FWB0 offset 0x100 1467 // and bit 31 corresponds to FWB31 1468 // offset 0x13C. 1469 1470 #define FLASH_CTRL_FWBVAL_FWBN_S 0 1471 //****************************************************************************** 1472 // 1473 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB1 register. 1474 // 1475 //****************************************************************************** 1476 #define FLASH_CTRL_FWB1_DATA_M 0xFFFFFFFF // Data Data to be written into the 1477 // Flash memory. 1478 #define FLASH_CTRL_FWB1_DATA_S 0 1479 //****************************************************************************** 1480 // 1481 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB2 register. 1482 // 1483 //****************************************************************************** 1484 #define FLASH_CTRL_FWB2_DATA_M 0xFFFFFFFF // Data Data to be written into the 1485 // Flash memory. 1486 #define FLASH_CTRL_FWB2_DATA_S 0 1487 //****************************************************************************** 1488 // 1489 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB3 register. 1490 // 1491 //****************************************************************************** 1492 #define FLASH_CTRL_FWB3_DATA_M 0xFFFFFFFF // Data Data to be written into the 1493 // Flash memory. 1494 #define FLASH_CTRL_FWB3_DATA_S 0 1495 //****************************************************************************** 1496 // 1497 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB4 register. 1498 // 1499 //****************************************************************************** 1500 #define FLASH_CTRL_FWB4_DATA_M 0xFFFFFFFF // Data Data to be written into the 1501 // Flash memory. 1502 #define FLASH_CTRL_FWB4_DATA_S 0 1503 //****************************************************************************** 1504 // 1505 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB5 register. 1506 // 1507 //****************************************************************************** 1508 #define FLASH_CTRL_FWB5_DATA_M 0xFFFFFFFF // Data Data to be written into the 1509 // Flash memory. 1510 #define FLASH_CTRL_FWB5_DATA_S 0 1511 //****************************************************************************** 1512 // 1513 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB6 register. 1514 // 1515 //****************************************************************************** 1516 #define FLASH_CTRL_FWB6_DATA_M 0xFFFFFFFF // Data Data to be written into the 1517 // Flash memory. 1518 #define FLASH_CTRL_FWB6_DATA_S 0 1519 //****************************************************************************** 1520 // 1521 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB7 register. 1522 // 1523 //****************************************************************************** 1524 #define FLASH_CTRL_FWB7_DATA_M 0xFFFFFFFF // Data Data to be written into the 1525 // Flash memory. 1526 #define FLASH_CTRL_FWB7_DATA_S 0 1527 //****************************************************************************** 1528 // 1529 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB8 register. 1530 // 1531 //****************************************************************************** 1532 #define FLASH_CTRL_FWB8_DATA_M 0xFFFFFFFF // Data Data to be written into the 1533 // Flash memory. 1534 #define FLASH_CTRL_FWB8_DATA_S 0 1535 //****************************************************************************** 1536 // 1537 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB9 register. 1538 // 1539 //****************************************************************************** 1540 #define FLASH_CTRL_FWB9_DATA_M 0xFFFFFFFF // Data Data to be written into the 1541 // Flash memory. 1542 #define FLASH_CTRL_FWB9_DATA_S 0 1543 //****************************************************************************** 1544 // 1545 // The following are defines for the bit fields in the 1546 // FLASH_CTRL_O_FWB10 register. 1547 // 1548 //****************************************************************************** 1549 #define FLASH_CTRL_FWB10_DATA_M 0xFFFFFFFF // Data Data to be written into the 1550 // Flash memory. 1551 #define FLASH_CTRL_FWB10_DATA_S 0 1552 //****************************************************************************** 1553 // 1554 // The following are defines for the bit fields in the 1555 // FLASH_CTRL_O_FWB11 register. 1556 // 1557 //****************************************************************************** 1558 #define FLASH_CTRL_FWB11_DATA_M 0xFFFFFFFF // Data Data to be written into the 1559 // Flash memory. 1560 #define FLASH_CTRL_FWB11_DATA_S 0 1561 //****************************************************************************** 1562 // 1563 // The following are defines for the bit fields in the 1564 // FLASH_CTRL_O_FWB12 register. 1565 // 1566 //****************************************************************************** 1567 #define FLASH_CTRL_FWB12_DATA_M 0xFFFFFFFF // Data Data to be written into the 1568 // Flash memory. 1569 #define FLASH_CTRL_FWB12_DATA_S 0 1570 //****************************************************************************** 1571 // 1572 // The following are defines for the bit fields in the 1573 // FLASH_CTRL_O_FWB13 register. 1574 // 1575 //****************************************************************************** 1576 #define FLASH_CTRL_FWB13_DATA_M 0xFFFFFFFF // Data Data to be written into the 1577 // Flash memory. 1578 #define FLASH_CTRL_FWB13_DATA_S 0 1579 //****************************************************************************** 1580 // 1581 // The following are defines for the bit fields in the 1582 // FLASH_CTRL_O_FWB14 register. 1583 // 1584 //****************************************************************************** 1585 #define FLASH_CTRL_FWB14_DATA_M 0xFFFFFFFF // Data Data to be written into the 1586 // Flash memory. 1587 #define FLASH_CTRL_FWB14_DATA_S 0 1588 //****************************************************************************** 1589 // 1590 // The following are defines for the bit fields in the 1591 // FLASH_CTRL_O_FWB15 register. 1592 // 1593 //****************************************************************************** 1594 #define FLASH_CTRL_FWB15_DATA_M 0xFFFFFFFF // Data Data to be written into the 1595 // Flash memory. 1596 #define FLASH_CTRL_FWB15_DATA_S 0 1597 //****************************************************************************** 1598 // 1599 // The following are defines for the bit fields in the 1600 // FLASH_CTRL_O_FWB16 register. 1601 // 1602 //****************************************************************************** 1603 #define FLASH_CTRL_FWB16_DATA_M 0xFFFFFFFF // Data Data to be written into the 1604 // Flash memory. 1605 #define FLASH_CTRL_FWB16_DATA_S 0 1606 //****************************************************************************** 1607 // 1608 // The following are defines for the bit fields in the 1609 // FLASH_CTRL_O_FWB17 register. 1610 // 1611 //****************************************************************************** 1612 #define FLASH_CTRL_FWB17_DATA_M 0xFFFFFFFF // Data Data to be written into the 1613 // Flash memory. 1614 #define FLASH_CTRL_FWB17_DATA_S 0 1615 //****************************************************************************** 1616 // 1617 // The following are defines for the bit fields in the 1618 // FLASH_CTRL_O_FWB18 register. 1619 // 1620 //****************************************************************************** 1621 #define FLASH_CTRL_FWB18_DATA_M 0xFFFFFFFF // Data Data to be written into the 1622 // Flash memory. 1623 #define FLASH_CTRL_FWB18_DATA_S 0 1624 //****************************************************************************** 1625 // 1626 // The following are defines for the bit fields in the 1627 // FLASH_CTRL_O_FWB19 register. 1628 // 1629 //****************************************************************************** 1630 #define FLASH_CTRL_FWB19_DATA_M 0xFFFFFFFF // Data Data to be written into the 1631 // Flash memory. 1632 #define FLASH_CTRL_FWB19_DATA_S 0 1633 //****************************************************************************** 1634 // 1635 // The following are defines for the bit fields in the 1636 // FLASH_CTRL_O_FWB20 register. 1637 // 1638 //****************************************************************************** 1639 #define FLASH_CTRL_FWB20_DATA_M 0xFFFFFFFF // Data Data to be written into the 1640 // Flash memory. 1641 #define FLASH_CTRL_FWB20_DATA_S 0 1642 //****************************************************************************** 1643 // 1644 // The following are defines for the bit fields in the 1645 // FLASH_CTRL_O_FWB21 register. 1646 // 1647 //****************************************************************************** 1648 #define FLASH_CTRL_FWB21_DATA_M 0xFFFFFFFF // Data Data to be written into the 1649 // Flash memory. 1650 #define FLASH_CTRL_FWB21_DATA_S 0 1651 //****************************************************************************** 1652 // 1653 // The following are defines for the bit fields in the 1654 // FLASH_CTRL_O_FWB22 register. 1655 // 1656 //****************************************************************************** 1657 #define FLASH_CTRL_FWB22_DATA_M 0xFFFFFFFF // Data Data to be written into the 1658 // Flash memory. 1659 #define FLASH_CTRL_FWB22_DATA_S 0 1660 //****************************************************************************** 1661 // 1662 // The following are defines for the bit fields in the 1663 // FLASH_CTRL_O_FWB23 register. 1664 // 1665 //****************************************************************************** 1666 #define FLASH_CTRL_FWB23_DATA_M 0xFFFFFFFF // Data Data to be written into the 1667 // Flash memory. 1668 #define FLASH_CTRL_FWB23_DATA_S 0 1669 //****************************************************************************** 1670 // 1671 // The following are defines for the bit fields in the 1672 // FLASH_CTRL_O_FWB24 register. 1673 // 1674 //****************************************************************************** 1675 #define FLASH_CTRL_FWB24_DATA_M 0xFFFFFFFF // Data Data to be written into the 1676 // Flash memory. 1677 #define FLASH_CTRL_FWB24_DATA_S 0 1678 //****************************************************************************** 1679 // 1680 // The following are defines for the bit fields in the 1681 // FLASH_CTRL_O_FWB25 register. 1682 // 1683 //****************************************************************************** 1684 #define FLASH_CTRL_FWB25_DATA_M 0xFFFFFFFF // Data Data to be written into the 1685 // Flash memory. 1686 #define FLASH_CTRL_FWB25_DATA_S 0 1687 //****************************************************************************** 1688 // 1689 // The following are defines for the bit fields in the 1690 // FLASH_CTRL_O_FWB26 register. 1691 // 1692 //****************************************************************************** 1693 #define FLASH_CTRL_FWB26_DATA_M 0xFFFFFFFF // Data Data to be written into the 1694 // Flash memory. 1695 #define FLASH_CTRL_FWB26_DATA_S 0 1696 //****************************************************************************** 1697 // 1698 // The following are defines for the bit fields in the 1699 // FLASH_CTRL_O_FWB27 register. 1700 // 1701 //****************************************************************************** 1702 #define FLASH_CTRL_FWB27_DATA_M 0xFFFFFFFF // Data Data to be written into the 1703 // Flash memory. 1704 #define FLASH_CTRL_FWB27_DATA_S 0 1705 //****************************************************************************** 1706 // 1707 // The following are defines for the bit fields in the 1708 // FLASH_CTRL_O_FWB28 register. 1709 // 1710 //****************************************************************************** 1711 #define FLASH_CTRL_FWB28_DATA_M 0xFFFFFFFF // Data Data to be written into the 1712 // Flash memory. 1713 #define FLASH_CTRL_FWB28_DATA_S 0 1714 //****************************************************************************** 1715 // 1716 // The following are defines for the bit fields in the 1717 // FLASH_CTRL_O_FWB29 register. 1718 // 1719 //****************************************************************************** 1720 #define FLASH_CTRL_FWB29_DATA_M 0xFFFFFFFF // Data Data to be written into the 1721 // Flash memory. 1722 #define FLASH_CTRL_FWB29_DATA_S 0 1723 //****************************************************************************** 1724 // 1725 // The following are defines for the bit fields in the 1726 // FLASH_CTRL_O_FWB30 register. 1727 // 1728 //****************************************************************************** 1729 #define FLASH_CTRL_FWB30_DATA_M 0xFFFFFFFF // Data Data to be written into the 1730 // Flash memory. 1731 #define FLASH_CTRL_FWB30_DATA_S 0 1732 //****************************************************************************** 1733 // 1734 // The following are defines for the bit fields in the 1735 // FLASH_CTRL_O_FWB31 register. 1736 // 1737 //****************************************************************************** 1738 #define FLASH_CTRL_FWB31_DATA_M 0xFFFFFFFF // Data Data to be written into the 1739 // Flash memory. 1740 #define FLASH_CTRL_FWB31_DATA_S 0 1741 //****************************************************************************** 1742 // 1743 // The following are defines for the bit fields in the 1744 // FLASH_CTRL_O_FWB32 register. 1745 // 1746 //****************************************************************************** 1747 #define FLASH_CTRL_FWB32_DATA_M 0xFFFFFFFF // Data Data to be written into the 1748 // Flash memory. 1749 #define FLASH_CTRL_FWB32_DATA_S 0 1750 //****************************************************************************** 1751 // 1752 // The following are defines for the bit fields in the 1753 // FLASH_CTRL_O_FSIZE register. 1754 // 1755 //****************************************************************************** 1756 #define FLASH_CTRL_FSIZE_SIZE_M 0x0000FFFF // Flash Size Indicates the size of 1757 // the on-chip Flash memory. Value 1758 // Description 0x0003 8 KB of Flash 1759 // 0x0007 16 KB of Flash 0x000F 32 1760 // KB of Flash 0x001F 64 KB of Flash 1761 // 0x002F 96 KB of Flash 0x003F 128 1762 // KB of Flash 0x005F 192 KB of 1763 // Flash 0x007F 256 KB of Flash 1764 #define FLASH_CTRL_FSIZE_SIZE_S 0 1765 //****************************************************************************** 1766 // 1767 // The following are defines for the bit fields in the 1768 // FLASH_CTRL_O_SSIZE register. 1769 // 1770 //****************************************************************************** 1771 #define FLASH_CTRL_SSIZE_SRAM_SIZE_M \ 1772 0x0000FFFF // SRAM Size Indicates the size of 1773 // the on-chip SRAM. Value 1774 // Description 0x0007 2 KB of SRAM 1775 // 0x000F 4 KB of SRAM 0x0017 6 KB 1776 // of SRAM 0x001F 8 KB of SRAM 1777 // 0x002F 12 KB of SRAM 0x003F 16 KB 1778 // of SRAM 0x004F 20 KB of SRAM 1779 // 0x005F 24 KB of SRAM 0x007F 32 KB 1780 // of SRAM 1781 1782 #define FLASH_CTRL_SSIZE_SRAM_SIZE_S 0 1783 #define FLASH_CTRL_FMC_WRKEY 0xA4420000 // FLASH write key 1784 #define FLASH_CTRL_FMC2_WRKEY 0xA4420000 // FLASH write key 1785 #define FLASH_CTRL_O_FWBN FLASH_CTRL_O_FWB1 1786 #define FLASH_ERASE_SIZE 0x00000400 1787 #define FLASH_PROTECT_SIZE 0x00000800 1788 #define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 1789 1790 #define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read 1791 // Enable 0 1792 #define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read 1793 // Enable 1 1794 #define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read 1795 // Enable 2 1796 #define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read 1797 // Enable 3 1798 #define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read 1799 // Enable 4 1800 #define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read 1801 // Enable 5 1802 #define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read 1803 // Enable 6 1804 #define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read 1805 // Enable 7 1806 #define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read 1807 // Enable 8 1808 #define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read 1809 // Enable 9 1810 #define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read 1811 // Enable 10 1812 #define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read 1813 // Enable 11 1814 #define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read 1815 // Enable 12 1816 #define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read 1817 // Enable 13 1818 #define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read 1819 // Enable 14 1820 #define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read 1821 // Enable 15 1822 1823 #define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program 1824 // Enable 0 1825 #define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program 1826 // Enable 1 1827 #define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program 1828 // Enable 2 1829 #define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program 1830 // Enable 3 1831 #define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program 1832 // Enable 4 1833 #define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program 1834 // Enable 5 1835 #define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program 1836 // Enable 6 1837 #define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program 1838 // Enable 7 1839 #define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program 1840 // Enable 8 1841 #define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program 1842 // Enable 9 1843 #define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program 1844 // Enable 10 1845 #define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program 1846 // Enable 11 1847 #define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program 1848 // Enable 12 1849 #define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program 1850 // Enable 13 1851 #define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program 1852 // Enable 14 1853 #define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program 1854 // Enable 15 1855 1856 #define FLASH_USECRL 0x400FE140 // USec Reload 1857 #define FLASH_CTRL_ERASE_SIZE 0x00000400 1858 1859 1860 #endif // __HW_FLASH_CTRL_H__ 1861
