1 /****************************************************************************** 2 * Filename: hw_fcfg1_h 3 * Revised: 2018-11-06 14:08:24 +0100 (Tue, 06 Nov 2018) 4 * Revision: 53237 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_FCFG1_H__ 38 #define __HW_FCFG1_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // FCFG1 component 44 // 45 //***************************************************************************** 46 // Misc configurations 47 #define FCFG1_O_MISC_CONF_1 0x000000A0 48 49 // Internal 50 #define FCFG1_O_MISC_CONF_2 0x000000A4 51 52 // Internal 53 #define FCFG1_O_HPOSC_MEAS_5 0x000000B0 54 55 // Internal 56 #define FCFG1_O_HPOSC_MEAS_4 0x000000B4 57 58 // Internal 59 #define FCFG1_O_HPOSC_MEAS_3 0x000000B8 60 61 // Internal 62 #define FCFG1_O_HPOSC_MEAS_2 0x000000BC 63 64 // Internal 65 #define FCFG1_O_HPOSC_MEAS_1 0x000000C0 66 67 // Internal 68 #define FCFG1_O_CONFIG_CC26_FE 0x000000C4 69 70 // Internal 71 #define FCFG1_O_CONFIG_CC13_FE 0x000000C8 72 73 // Internal 74 #define FCFG1_O_CONFIG_RF_COMMON 0x000000CC 75 76 // Internal 77 #define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 0x000000D0 78 79 // Internal 80 #define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 0x000000D4 81 82 // Internal 83 #define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G 0x000000D8 84 85 // Internal 86 #define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G 0x000000DC 87 88 // Internal 89 #define FCFG1_O_CONFIG_SYNTH_DIV4_CC26 0x000000E0 90 91 // Internal 92 #define FCFG1_O_CONFIG_SYNTH_DIV4_CC13 0x000000E4 93 94 // Internal 95 #define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000E8 96 97 // Internal 98 #define FCFG1_O_CONFIG_SYNTH_DIV6_CC26 0x000000EC 99 100 // Internal 101 #define FCFG1_O_CONFIG_SYNTH_DIV6_CC13 0x000000F0 102 103 // Internal 104 #define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000F4 105 106 // Internal 107 #define FCFG1_O_CONFIG_SYNTH_DIV12_CC26 0x000000F8 108 109 // Internal 110 #define FCFG1_O_CONFIG_SYNTH_DIV12_CC13 0x000000FC 111 112 // Internal 113 #define FCFG1_O_CONFIG_SYNTH_DIV15 0x00000100 114 115 // Internal 116 #define FCFG1_O_CONFIG_SYNTH_DIV30 0x00000104 117 118 // Flash information 119 #define FCFG1_O_FLASH_NUMBER 0x00000164 120 121 // Flash information 122 #define FCFG1_O_FLASH_COORDINATE 0x0000016C 123 124 // Internal 125 #define FCFG1_O_FLASH_E_P 0x00000170 126 127 // Internal 128 #define FCFG1_O_FLASH_C_E_P_R 0x00000174 129 130 // Internal 131 #define FCFG1_O_FLASH_P_R_PV 0x00000178 132 133 // Internal 134 #define FCFG1_O_FLASH_EH_SEQ 0x0000017C 135 136 // Internal 137 #define FCFG1_O_FLASH_VHV_E 0x00000180 138 139 // Internal 140 #define FCFG1_O_FLASH_PP 0x00000184 141 142 // Internal 143 #define FCFG1_O_FLASH_PROG_EP 0x00000188 144 145 // Internal 146 #define FCFG1_O_FLASH_ERA_PW 0x0000018C 147 148 // Internal 149 #define FCFG1_O_FLASH_VHV 0x00000190 150 151 // Internal 152 #define FCFG1_O_FLASH_VHV_PV 0x00000194 153 154 // Internal 155 #define FCFG1_O_FLASH_V 0x00000198 156 157 // User Identification. 158 #define FCFG1_O_USER_ID 0x00000294 159 160 // Internal 161 #define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 162 163 // Internal 164 #define FCFG1_O_ANA2_TRIM 0x000002B4 165 166 // Internal 167 #define FCFG1_O_LDO_TRIM 0x000002B8 168 169 // MAC BLE Address 0 170 #define FCFG1_O_MAC_BLE_0 0x000002E8 171 172 // MAC BLE Address 1 173 #define FCFG1_O_MAC_BLE_1 0x000002EC 174 175 // MAC IEEE 802.15.4 Address 0 176 #define FCFG1_O_MAC_15_4_0 0x000002F0 177 178 // MAC IEEE 802.15.4 Address 1 179 #define FCFG1_O_MAC_15_4_1 0x000002F4 180 181 // Internal 182 #define FCFG1_O_FLASH_OTP_DATA4 0x00000308 183 184 // Miscellaneous Trim Parameters 185 #define FCFG1_O_MISC_TRIM 0x0000030C 186 187 // Internal 188 #define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 189 190 // IcePick Device Identification 191 #define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 192 193 // Factory Configuration (FCFG1) Revision 194 #define FCFG1_O_FCFG1_REVISION 0x0000031C 195 196 // Misc OTP Data 197 #define FCFG1_O_MISC_OTP_DATA 0x00000320 198 199 // IO Configuration 200 #define FCFG1_O_IOCONF 0x00000344 201 202 // Internal 203 #define FCFG1_O_CONFIG_IF_ADC 0x0000034C 204 205 // Internal 206 #define FCFG1_O_CONFIG_OSC_TOP 0x00000350 207 208 // AUX_ADC Gain in Absolute Reference Mode 209 #define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C 210 211 // AUX_ADC Gain in Relative Reference Mode 212 #define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 213 214 // AUX_ADC Temperature Offsets in Absolute Reference Mode 215 #define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 216 217 // Internal 218 #define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C 219 220 // Internal 221 #define FCFG1_O_AMPCOMP_TH1 0x00000370 222 223 // Internal 224 #define FCFG1_O_AMPCOMP_TH2 0x00000374 225 226 // Internal 227 #define FCFG1_O_AMPCOMP_CTRL1 0x00000378 228 229 // Internal 230 #define FCFG1_O_ANABYPASS_VALUE2 0x0000037C 231 232 // Internal 233 #define FCFG1_O_VOLT_TRIM 0x00000388 234 235 // OSC Configuration 236 #define FCFG1_O_OSC_CONF 0x0000038C 237 238 // Internal 239 #define FCFG1_O_FREQ_OFFSET 0x00000390 240 241 // Internal 242 #define FCFG1_O_MISC_OTP_DATA_1 0x00000398 243 244 // Shadow of EFUSE:DIE_ID_0 register 245 #define FCFG1_O_SHDW_DIE_ID_0 0x000003D0 246 247 // Shadow of EFUSE:DIE_ID_1 register 248 #define FCFG1_O_SHDW_DIE_ID_1 0x000003D4 249 250 // Shadow of EFUSE:DIE_ID_2 register 251 #define FCFG1_O_SHDW_DIE_ID_2 0x000003D8 252 253 // Shadow of EFUSE:DIE_ID_3 register 254 #define FCFG1_O_SHDW_DIE_ID_3 0x000003DC 255 256 // Internal 257 #define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x000003F8 258 259 // Internal 260 #define FCFG1_O_SHDW_ANA_TRIM 0x000003FC 261 262 // Internal 263 #define FCFG1_O_DAC_BIAS_CNF 0x0000040C 264 265 // Internal 266 #define FCFG1_O_TFW_PROBE 0x00000418 267 268 // Internal 269 #define FCFG1_O_TFW_FT 0x0000041C 270 271 // Internal 272 #define FCFG1_O_DAC_CAL0 0x00000420 273 274 // Internal 275 #define FCFG1_O_DAC_CAL1 0x00000424 276 277 // Internal 278 #define FCFG1_O_DAC_CAL2 0x00000428 279 280 // Internal 281 #define FCFG1_O_DAC_CAL3 0x0000042C 282 283 //***************************************************************************** 284 // 285 // Register: FCFG1_O_MISC_CONF_1 286 // 287 //***************************************************************************** 288 // Field: [7:0] DEVICE_MINOR_REV 289 // 290 // HW minor revision number (a value of 0xFF shall be treated equally to 0x00). 291 // Any test of this field by SW should be implemented as a 'greater or equal' 292 // comparison as signed integer. 293 // Value may change without warning. 294 #define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 295 #define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF 296 #define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 297 298 //***************************************************************************** 299 // 300 // Register: FCFG1_O_MISC_CONF_2 301 // 302 //***************************************************************************** 303 // Field: [7:0] HPOSC_COMP_P3 304 // 305 // Internal. Only to be used through TI provided API. 306 #define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 307 #define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF 308 #define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 309 310 //***************************************************************************** 311 // 312 // Register: FCFG1_O_HPOSC_MEAS_5 313 // 314 //***************************************************************************** 315 // Field: [31:16] HPOSC_D5 316 // 317 // Internal. Only to be used through TI provided API. 318 #define FCFG1_HPOSC_MEAS_5_HPOSC_D5_W 16 319 #define FCFG1_HPOSC_MEAS_5_HPOSC_D5_M 0xFFFF0000 320 #define FCFG1_HPOSC_MEAS_5_HPOSC_D5_S 16 321 322 // Field: [15:8] HPOSC_T5 323 // 324 // Internal. Only to be used through TI provided API. 325 #define FCFG1_HPOSC_MEAS_5_HPOSC_T5_W 8 326 #define FCFG1_HPOSC_MEAS_5_HPOSC_T5_M 0x0000FF00 327 #define FCFG1_HPOSC_MEAS_5_HPOSC_T5_S 8 328 329 // Field: [7:0] HPOSC_DT5 330 // 331 // Internal. Only to be used through TI provided API. 332 #define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_W 8 333 #define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_M 0x000000FF 334 #define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_S 0 335 336 //***************************************************************************** 337 // 338 // Register: FCFG1_O_HPOSC_MEAS_4 339 // 340 //***************************************************************************** 341 // Field: [31:16] HPOSC_D4 342 // 343 // Internal. Only to be used through TI provided API. 344 #define FCFG1_HPOSC_MEAS_4_HPOSC_D4_W 16 345 #define FCFG1_HPOSC_MEAS_4_HPOSC_D4_M 0xFFFF0000 346 #define FCFG1_HPOSC_MEAS_4_HPOSC_D4_S 16 347 348 // Field: [15:8] HPOSC_T4 349 // 350 // Internal. Only to be used through TI provided API. 351 #define FCFG1_HPOSC_MEAS_4_HPOSC_T4_W 8 352 #define FCFG1_HPOSC_MEAS_4_HPOSC_T4_M 0x0000FF00 353 #define FCFG1_HPOSC_MEAS_4_HPOSC_T4_S 8 354 355 // Field: [7:0] HPOSC_DT4 356 // 357 // Internal. Only to be used through TI provided API. 358 #define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_W 8 359 #define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_M 0x000000FF 360 #define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_S 0 361 362 //***************************************************************************** 363 // 364 // Register: FCFG1_O_HPOSC_MEAS_3 365 // 366 //***************************************************************************** 367 // Field: [31:16] HPOSC_D3 368 // 369 // Internal. Only to be used through TI provided API. 370 #define FCFG1_HPOSC_MEAS_3_HPOSC_D3_W 16 371 #define FCFG1_HPOSC_MEAS_3_HPOSC_D3_M 0xFFFF0000 372 #define FCFG1_HPOSC_MEAS_3_HPOSC_D3_S 16 373 374 // Field: [15:8] HPOSC_T3 375 // 376 // Internal. Only to be used through TI provided API. 377 #define FCFG1_HPOSC_MEAS_3_HPOSC_T3_W 8 378 #define FCFG1_HPOSC_MEAS_3_HPOSC_T3_M 0x0000FF00 379 #define FCFG1_HPOSC_MEAS_3_HPOSC_T3_S 8 380 381 // Field: [7:0] HPOSC_DT3 382 // 383 // Internal. Only to be used through TI provided API. 384 #define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_W 8 385 #define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_M 0x000000FF 386 #define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_S 0 387 388 //***************************************************************************** 389 // 390 // Register: FCFG1_O_HPOSC_MEAS_2 391 // 392 //***************************************************************************** 393 // Field: [31:16] HPOSC_D2 394 // 395 // Internal. Only to be used through TI provided API. 396 #define FCFG1_HPOSC_MEAS_2_HPOSC_D2_W 16 397 #define FCFG1_HPOSC_MEAS_2_HPOSC_D2_M 0xFFFF0000 398 #define FCFG1_HPOSC_MEAS_2_HPOSC_D2_S 16 399 400 // Field: [15:8] HPOSC_T2 401 // 402 // Internal. Only to be used through TI provided API. 403 #define FCFG1_HPOSC_MEAS_2_HPOSC_T2_W 8 404 #define FCFG1_HPOSC_MEAS_2_HPOSC_T2_M 0x0000FF00 405 #define FCFG1_HPOSC_MEAS_2_HPOSC_T2_S 8 406 407 // Field: [7:0] HPOSC_DT2 408 // 409 // Internal. Only to be used through TI provided API. 410 #define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_W 8 411 #define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_M 0x000000FF 412 #define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_S 0 413 414 //***************************************************************************** 415 // 416 // Register: FCFG1_O_HPOSC_MEAS_1 417 // 418 //***************************************************************************** 419 // Field: [31:16] HPOSC_D1 420 // 421 // Internal. Only to be used through TI provided API. 422 #define FCFG1_HPOSC_MEAS_1_HPOSC_D1_W 16 423 #define FCFG1_HPOSC_MEAS_1_HPOSC_D1_M 0xFFFF0000 424 #define FCFG1_HPOSC_MEAS_1_HPOSC_D1_S 16 425 426 // Field: [15:8] HPOSC_T1 427 // 428 // Internal. Only to be used through TI provided API. 429 #define FCFG1_HPOSC_MEAS_1_HPOSC_T1_W 8 430 #define FCFG1_HPOSC_MEAS_1_HPOSC_T1_M 0x0000FF00 431 #define FCFG1_HPOSC_MEAS_1_HPOSC_T1_S 8 432 433 // Field: [7:0] HPOSC_DT1 434 // 435 // Internal. Only to be used through TI provided API. 436 #define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_W 8 437 #define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_M 0x000000FF 438 #define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_S 0 439 440 //***************************************************************************** 441 // 442 // Register: FCFG1_O_CONFIG_CC26_FE 443 // 444 //***************************************************************************** 445 // Field: [31:28] IFAMP_IB 446 // 447 // Internal. Only to be used through TI provided API. 448 #define FCFG1_CONFIG_CC26_FE_IFAMP_IB_W 4 449 #define FCFG1_CONFIG_CC26_FE_IFAMP_IB_M 0xF0000000 450 #define FCFG1_CONFIG_CC26_FE_IFAMP_IB_S 28 451 452 // Field: [27:24] LNA_IB 453 // 454 // Internal. Only to be used through TI provided API. 455 #define FCFG1_CONFIG_CC26_FE_LNA_IB_W 4 456 #define FCFG1_CONFIG_CC26_FE_LNA_IB_M 0x0F000000 457 #define FCFG1_CONFIG_CC26_FE_LNA_IB_S 24 458 459 // Field: [23:19] IFAMP_TRIM 460 // 461 // Internal. Only to be used through TI provided API. 462 #define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_W 5 463 #define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_M 0x00F80000 464 #define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_S 19 465 466 // Field: [18:14] CTL_PA0_TRIM 467 // 468 // Internal. Only to be used through TI provided API. 469 #define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_W 5 470 #define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_M 0x0007C000 471 #define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_S 14 472 473 // Field: [13] PATRIMCOMPLETE_N 474 // 475 // Internal. Only to be used through TI provided API. 476 #define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N 0x00002000 477 #define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_BITN 13 478 #define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_M 0x00002000 479 #define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_S 13 480 481 // Field: [12] RSSITRIMCOMPLETE_N 482 // 483 // Internal. Only to be used through TI provided API. 484 #define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N 0x00001000 485 #define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_BITN 12 486 #define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_M 0x00001000 487 #define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_S 12 488 489 // Field: [7:0] RSSI_OFFSET 490 // 491 // Internal. Only to be used through TI provided API. 492 #define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_W 8 493 #define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_M 0x000000FF 494 #define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_S 0 495 496 //***************************************************************************** 497 // 498 // Register: FCFG1_O_CONFIG_CC13_FE 499 // 500 //***************************************************************************** 501 // Field: [31:28] IFAMP_IB 502 // 503 // Internal. Only to be used through TI provided API. 504 #define FCFG1_CONFIG_CC13_FE_IFAMP_IB_W 4 505 #define FCFG1_CONFIG_CC13_FE_IFAMP_IB_M 0xF0000000 506 #define FCFG1_CONFIG_CC13_FE_IFAMP_IB_S 28 507 508 // Field: [27:24] LNA_IB 509 // 510 // Internal. Only to be used through TI provided API. 511 #define FCFG1_CONFIG_CC13_FE_LNA_IB_W 4 512 #define FCFG1_CONFIG_CC13_FE_LNA_IB_M 0x0F000000 513 #define FCFG1_CONFIG_CC13_FE_LNA_IB_S 24 514 515 // Field: [23:19] IFAMP_TRIM 516 // 517 // Internal. Only to be used through TI provided API. 518 #define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_W 5 519 #define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_M 0x00F80000 520 #define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_S 19 521 522 // Field: [18:14] CTL_PA0_TRIM 523 // 524 // Internal. Only to be used through TI provided API. 525 #define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_W 5 526 #define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_M 0x0007C000 527 #define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_S 14 528 529 // Field: [13] PATRIMCOMPLETE_N 530 // 531 // Internal. Only to be used through TI provided API. 532 #define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N 0x00002000 533 #define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_BITN 13 534 #define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_M 0x00002000 535 #define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_S 13 536 537 // Field: [12] RSSITRIMCOMPLETE_N 538 // 539 // Internal. Only to be used through TI provided API. 540 #define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N 0x00001000 541 #define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_BITN 12 542 #define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_M 0x00001000 543 #define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_S 12 544 545 // Field: [7:0] RSSI_OFFSET 546 // 547 // Internal. Only to be used through TI provided API. 548 #define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_W 8 549 #define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_M 0x000000FF 550 #define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_S 0 551 552 //***************************************************************************** 553 // 554 // Register: FCFG1_O_CONFIG_RF_COMMON 555 // 556 //***************************************************************************** 557 // Field: [31] DISABLE_CORNER_CAP 558 // 559 // Internal. Only to be used through TI provided API. 560 #define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP 0x80000000 561 #define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_BITN 31 562 #define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_M 0x80000000 563 #define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_S 31 564 565 // Field: [30:25] SLDO_TRIM_OUTPUT 566 // 567 // Internal. Only to be used through TI provided API. 568 #define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_W 6 569 #define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_M 0x7E000000 570 #define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_S 25 571 572 // Field: [21] PA20DBMTRIMCOMPLETE_N 573 // 574 // Internal. Only to be used through TI provided API. 575 #define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N 0x00200000 576 #define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_BITN 21 577 #define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_M 0x00200000 578 #define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_S 21 579 580 // Field: [20:16] CTL_PA_20DBM_TRIM 581 // 582 // Internal. Only to be used through TI provided API. 583 #define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_W 5 584 #define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_M 0x001F0000 585 #define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_S 16 586 587 // Field: [15:9] RFLDO_TRIM_OUTPUT 588 // 589 // Internal. Only to be used through TI provided API. 590 #define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_W 7 591 #define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_M 0x0000FE00 592 #define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_S 9 593 594 // Field: [8:6] QUANTCTLTHRES 595 // 596 // Internal. Only to be used through TI provided API. 597 #define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_W 3 598 #define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_M 0x000001C0 599 #define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_S 6 600 601 // Field: [5:0] DACTRIM 602 // 603 // Internal. Only to be used through TI provided API. 604 #define FCFG1_CONFIG_RF_COMMON_DACTRIM_W 6 605 #define FCFG1_CONFIG_RF_COMMON_DACTRIM_M 0x0000003F 606 #define FCFG1_CONFIG_RF_COMMON_DACTRIM_S 0 607 608 //***************************************************************************** 609 // 610 // Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 611 // 612 //***************************************************************************** 613 // Field: [31:28] MIN_ALLOWED_RTRIM 614 // 615 // Internal. Only to be used through TI provided API. 616 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_W 4 617 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 618 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_S 28 619 620 // Field: [27:12] RFC_MDM_DEMIQMC0 621 // 622 // Internal. Only to be used through TI provided API. 623 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_W 16 624 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 625 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_S 12 626 627 // Field: [11:6] LDOVCO_TRIM_OUTPUT 628 // 629 // Internal. Only to be used through TI provided API. 630 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_W 6 631 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 632 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_S 6 633 634 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 635 // 636 // Internal. Only to be used through TI provided API. 637 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 638 0x00000020 639 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 640 5 641 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 642 0x00000020 643 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 644 5 645 646 //***************************************************************************** 647 // 648 // Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 649 // 650 //***************************************************************************** 651 // Field: [31:28] MIN_ALLOWED_RTRIM 652 // 653 // Internal. Only to be used through TI provided API. 654 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_W 4 655 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 656 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_S 28 657 658 // Field: [27:12] RFC_MDM_DEMIQMC0 659 // 660 // Internal. Only to be used through TI provided API. 661 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_W 16 662 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 663 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_S 12 664 665 // Field: [11:6] LDOVCO_TRIM_OUTPUT 666 // 667 // Internal. Only to be used through TI provided API. 668 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_W 6 669 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 670 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_S 6 671 672 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 673 // 674 // Internal. Only to be used through TI provided API. 675 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 676 0x00000020 677 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 678 5 679 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 680 0x00000020 681 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 682 5 683 684 //***************************************************************************** 685 // 686 // Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G 687 // 688 //***************************************************************************** 689 // Field: [31:28] MIN_ALLOWED_RTRIM 690 // 691 // Internal. Only to be used through TI provided API. 692 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_W 4 693 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 694 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_S 28 695 696 // Field: [27:12] RFC_MDM_DEMIQMC0 697 // 698 // Internal. Only to be used through TI provided API. 699 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_W 16 700 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 701 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_S 12 702 703 // Field: [11:6] LDOVCO_TRIM_OUTPUT 704 // 705 // Internal. Only to be used through TI provided API. 706 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_W 6 707 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 708 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_S 6 709 710 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 711 // 712 // Internal. Only to be used through TI provided API. 713 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 714 0x00000020 715 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 716 5 717 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 718 0x00000020 719 #define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 720 5 721 722 //***************************************************************************** 723 // 724 // Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G 725 // 726 //***************************************************************************** 727 // Field: [31:28] MIN_ALLOWED_RTRIM 728 // 729 // Internal. Only to be used through TI provided API. 730 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_W 4 731 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 732 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_S 28 733 734 // Field: [27:12] RFC_MDM_DEMIQMC0 735 // 736 // Internal. Only to be used through TI provided API. 737 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_W 16 738 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 739 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_S 12 740 741 // Field: [11:6] LDOVCO_TRIM_OUTPUT 742 // 743 // Internal. Only to be used through TI provided API. 744 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_W 6 745 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 746 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_S 6 747 748 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 749 // 750 // Internal. Only to be used through TI provided API. 751 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 752 0x00000020 753 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 754 5 755 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 756 0x00000020 757 #define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 758 5 759 760 //***************************************************************************** 761 // 762 // Register: FCFG1_O_CONFIG_SYNTH_DIV4_CC26 763 // 764 //***************************************************************************** 765 // Field: [31:28] MIN_ALLOWED_RTRIM 766 // 767 // Internal. Only to be used through TI provided API. 768 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_W 4 769 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 770 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_S 28 771 772 // Field: [27:12] RFC_MDM_DEMIQMC0 773 // 774 // Internal. Only to be used through TI provided API. 775 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_W 16 776 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 777 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_S 12 778 779 // Field: [11:6] LDOVCO_TRIM_OUTPUT 780 // 781 // Internal. Only to be used through TI provided API. 782 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_W 6 783 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 784 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_S 6 785 786 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 787 // 788 // Internal. Only to be used through TI provided API. 789 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 790 0x00000020 791 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 792 5 793 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 794 0x00000020 795 #define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 796 5 797 798 //***************************************************************************** 799 // 800 // Register: FCFG1_O_CONFIG_SYNTH_DIV4_CC13 801 // 802 //***************************************************************************** 803 // Field: [31:28] MIN_ALLOWED_RTRIM 804 // 805 // Internal. Only to be used through TI provided API. 806 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_W 4 807 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 808 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_S 28 809 810 // Field: [27:12] RFC_MDM_DEMIQMC0 811 // 812 // Internal. Only to be used through TI provided API. 813 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_W 16 814 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 815 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_S 12 816 817 // Field: [11:6] LDOVCO_TRIM_OUTPUT 818 // 819 // Internal. Only to be used through TI provided API. 820 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_W 6 821 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 822 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_S 6 823 824 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 825 // 826 // Internal. Only to be used through TI provided API. 827 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 828 0x00000020 829 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 830 5 831 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 832 0x00000020 833 #define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 834 5 835 836 //***************************************************************************** 837 // 838 // Register: FCFG1_O_CONFIG_SYNTH_DIV5 839 // 840 //***************************************************************************** 841 // Field: [31:28] MIN_ALLOWED_RTRIM 842 // 843 // Internal. Only to be used through TI provided API. 844 #define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_W 4 845 #define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_M 0xF0000000 846 #define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_S 28 847 848 // Field: [27:12] RFC_MDM_DEMIQMC0 849 // 850 // Internal. Only to be used through TI provided API. 851 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 852 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 853 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 854 855 // Field: [11:6] LDOVCO_TRIM_OUTPUT 856 // 857 // Internal. Only to be used through TI provided API. 858 #define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 859 #define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 860 #define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 861 862 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 863 // 864 // Internal. Only to be used through TI provided API. 865 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 0x00000020 866 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 867 5 868 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 869 0x00000020 870 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 871 5 872 873 //***************************************************************************** 874 // 875 // Register: FCFG1_O_CONFIG_SYNTH_DIV6_CC26 876 // 877 //***************************************************************************** 878 // Field: [31:28] MIN_ALLOWED_RTRIM 879 // 880 // Internal. Only to be used through TI provided API. 881 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_W 4 882 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 883 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_S 28 884 885 // Field: [27:12] RFC_MDM_DEMIQMC0 886 // 887 // Internal. Only to be used through TI provided API. 888 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_W 16 889 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 890 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_S 12 891 892 // Field: [11:6] LDOVCO_TRIM_OUTPUT 893 // 894 // Internal. Only to be used through TI provided API. 895 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_W 6 896 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 897 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_S 6 898 899 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 900 // 901 // Internal. Only to be used through TI provided API. 902 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 903 0x00000020 904 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 905 5 906 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 907 0x00000020 908 #define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 909 5 910 911 //***************************************************************************** 912 // 913 // Register: FCFG1_O_CONFIG_SYNTH_DIV6_CC13 914 // 915 //***************************************************************************** 916 // Field: [31:28] MIN_ALLOWED_RTRIM 917 // 918 // Internal. Only to be used through TI provided API. 919 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_W 4 920 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 921 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_S 28 922 923 // Field: [27:12] RFC_MDM_DEMIQMC0 924 // 925 // Internal. Only to be used through TI provided API. 926 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_W 16 927 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 928 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_S 12 929 930 // Field: [11:6] LDOVCO_TRIM_OUTPUT 931 // 932 // Internal. Only to be used through TI provided API. 933 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_W 6 934 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 935 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_S 6 936 937 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 938 // 939 // Internal. Only to be used through TI provided API. 940 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 941 0x00000020 942 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 943 5 944 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 945 0x00000020 946 #define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 947 5 948 949 //***************************************************************************** 950 // 951 // Register: FCFG1_O_CONFIG_SYNTH_DIV10 952 // 953 //***************************************************************************** 954 // Field: [31:28] MIN_ALLOWED_RTRIM 955 // 956 // Internal. Only to be used through TI provided API. 957 #define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_W 4 958 #define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_M 0xF0000000 959 #define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_S 28 960 961 // Field: [27:12] RFC_MDM_DEMIQMC0 962 // 963 // Internal. Only to be used through TI provided API. 964 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 965 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 966 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 967 968 // Field: [11:6] LDOVCO_TRIM_OUTPUT 969 // 970 // Internal. Only to be used through TI provided API. 971 #define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 972 #define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 973 #define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 974 975 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 976 // 977 // Internal. Only to be used through TI provided API. 978 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 979 0x00000020 980 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 981 5 982 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 983 0x00000020 984 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 985 5 986 987 //***************************************************************************** 988 // 989 // Register: FCFG1_O_CONFIG_SYNTH_DIV12_CC26 990 // 991 //***************************************************************************** 992 // Field: [31:28] MIN_ALLOWED_RTRIM 993 // 994 // Internal. Only to be used through TI provided API. 995 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_W 4 996 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 997 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_S 28 998 999 // Field: [27:12] RFC_MDM_DEMIQMC0 1000 // 1001 // Internal. Only to be used through TI provided API. 1002 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_W 16 1003 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 1004 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_S 12 1005 1006 // Field: [11:6] LDOVCO_TRIM_OUTPUT 1007 // 1008 // Internal. Only to be used through TI provided API. 1009 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_W 6 1010 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 1011 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_S 6 1012 1013 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 1014 // 1015 // Internal. Only to be used through TI provided API. 1016 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 1017 0x00000020 1018 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 1019 5 1020 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 1021 0x00000020 1022 #define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 1023 5 1024 1025 //***************************************************************************** 1026 // 1027 // Register: FCFG1_O_CONFIG_SYNTH_DIV12_CC13 1028 // 1029 //***************************************************************************** 1030 // Field: [31:28] MIN_ALLOWED_RTRIM 1031 // 1032 // Internal. Only to be used through TI provided API. 1033 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_W 4 1034 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 1035 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_S 28 1036 1037 // Field: [27:12] RFC_MDM_DEMIQMC0 1038 // 1039 // Internal. Only to be used through TI provided API. 1040 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_W 16 1041 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 1042 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_S 12 1043 1044 // Field: [11:6] LDOVCO_TRIM_OUTPUT 1045 // 1046 // Internal. Only to be used through TI provided API. 1047 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_W 6 1048 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 1049 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_S 6 1050 1051 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 1052 // 1053 // Internal. Only to be used through TI provided API. 1054 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 1055 0x00000020 1056 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 1057 5 1058 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 1059 0x00000020 1060 #define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 1061 5 1062 1063 //***************************************************************************** 1064 // 1065 // Register: FCFG1_O_CONFIG_SYNTH_DIV15 1066 // 1067 //***************************************************************************** 1068 // Field: [31:28] MIN_ALLOWED_RTRIM 1069 // 1070 // Internal. Only to be used through TI provided API. 1071 #define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_W 4 1072 #define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_M 0xF0000000 1073 #define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_S 28 1074 1075 // Field: [27:12] RFC_MDM_DEMIQMC0 1076 // 1077 // Internal. Only to be used through TI provided API. 1078 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 1079 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 1080 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 1081 1082 // Field: [11:6] LDOVCO_TRIM_OUTPUT 1083 // 1084 // Internal. Only to be used through TI provided API. 1085 #define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 1086 #define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 1087 #define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 1088 1089 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 1090 // 1091 // Internal. Only to be used through TI provided API. 1092 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 1093 0x00000020 1094 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 1095 5 1096 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 1097 0x00000020 1098 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 1099 5 1100 1101 //***************************************************************************** 1102 // 1103 // Register: FCFG1_O_CONFIG_SYNTH_DIV30 1104 // 1105 //***************************************************************************** 1106 // Field: [31:28] MIN_ALLOWED_RTRIM 1107 // 1108 // Internal. Only to be used through TI provided API. 1109 #define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_W 4 1110 #define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_M 0xF0000000 1111 #define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_S 28 1112 1113 // Field: [27:12] RFC_MDM_DEMIQMC0 1114 // 1115 // Internal. Only to be used through TI provided API. 1116 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 1117 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 1118 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 1119 1120 // Field: [11:6] LDOVCO_TRIM_OUTPUT 1121 // 1122 // Internal. Only to be used through TI provided API. 1123 #define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 1124 #define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 1125 #define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 1126 1127 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 1128 // 1129 // Internal. Only to be used through TI provided API. 1130 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 1131 0x00000020 1132 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 1133 5 1134 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 1135 0x00000020 1136 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 1137 5 1138 1139 //***************************************************************************** 1140 // 1141 // Register: FCFG1_O_FLASH_NUMBER 1142 // 1143 //***************************************************************************** 1144 // Field: [31:0] LOT_NUMBER 1145 // 1146 // Number of the manufacturing lot that produced this unit. 1147 #define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 1148 #define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF 1149 #define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 1150 1151 //***************************************************************************** 1152 // 1153 // Register: FCFG1_O_FLASH_COORDINATE 1154 // 1155 //***************************************************************************** 1156 // Field: [31:16] XCOORDINATE 1157 // 1158 // X coordinate of this unit on the wafer. 1159 #define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 1160 #define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 1161 #define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 1162 1163 // Field: [15:0] YCOORDINATE 1164 // 1165 // Y coordinate of this unit on the wafer. 1166 #define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 1167 #define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF 1168 #define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 1169 1170 //***************************************************************************** 1171 // 1172 // Register: FCFG1_O_FLASH_E_P 1173 // 1174 //***************************************************************************** 1175 // Field: [31:24] PSU 1176 // 1177 // Internal. Only to be used through TI provided API. 1178 #define FCFG1_FLASH_E_P_PSU_W 8 1179 #define FCFG1_FLASH_E_P_PSU_M 0xFF000000 1180 #define FCFG1_FLASH_E_P_PSU_S 24 1181 1182 // Field: [23:16] ESU 1183 // 1184 // Internal. Only to be used through TI provided API. 1185 #define FCFG1_FLASH_E_P_ESU_W 8 1186 #define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 1187 #define FCFG1_FLASH_E_P_ESU_S 16 1188 1189 // Field: [15:8] PVSU 1190 // 1191 // Internal. Only to be used through TI provided API. 1192 #define FCFG1_FLASH_E_P_PVSU_W 8 1193 #define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 1194 #define FCFG1_FLASH_E_P_PVSU_S 8 1195 1196 // Field: [7:0] EVSU 1197 // 1198 // Internal. Only to be used through TI provided API. 1199 #define FCFG1_FLASH_E_P_EVSU_W 8 1200 #define FCFG1_FLASH_E_P_EVSU_M 0x000000FF 1201 #define FCFG1_FLASH_E_P_EVSU_S 0 1202 1203 //***************************************************************************** 1204 // 1205 // Register: FCFG1_O_FLASH_C_E_P_R 1206 // 1207 //***************************************************************************** 1208 // Field: [31:24] RVSU 1209 // 1210 // Internal. Only to be used through TI provided API. 1211 #define FCFG1_FLASH_C_E_P_R_RVSU_W 8 1212 #define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 1213 #define FCFG1_FLASH_C_E_P_R_RVSU_S 24 1214 1215 // Field: [23:16] PV_ACCESS 1216 // 1217 // Internal. Only to be used through TI provided API. 1218 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 1219 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 1220 #define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 1221 1222 // Field: [15:12] A_EXEZ_SETUP 1223 // 1224 // Internal. Only to be used through TI provided API. 1225 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 1226 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 1227 #define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 1228 1229 // Field: [11:0] CVSU 1230 // 1231 // Internal. Only to be used through TI provided API. 1232 #define FCFG1_FLASH_C_E_P_R_CVSU_W 12 1233 #define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF 1234 #define FCFG1_FLASH_C_E_P_R_CVSU_S 0 1235 1236 //***************************************************************************** 1237 // 1238 // Register: FCFG1_O_FLASH_P_R_PV 1239 // 1240 //***************************************************************************** 1241 // Field: [31:24] PH 1242 // 1243 // Internal. Only to be used through TI provided API. 1244 #define FCFG1_FLASH_P_R_PV_PH_W 8 1245 #define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 1246 #define FCFG1_FLASH_P_R_PV_PH_S 24 1247 1248 // Field: [23:16] RH 1249 // 1250 // Internal. Only to be used through TI provided API. 1251 #define FCFG1_FLASH_P_R_PV_RH_W 8 1252 #define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 1253 #define FCFG1_FLASH_P_R_PV_RH_S 16 1254 1255 // Field: [15:8] PVH 1256 // 1257 // Internal. Only to be used through TI provided API. 1258 #define FCFG1_FLASH_P_R_PV_PVH_W 8 1259 #define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 1260 #define FCFG1_FLASH_P_R_PV_PVH_S 8 1261 1262 // Field: [7:0] PVH2 1263 // 1264 // Internal. Only to be used through TI provided API. 1265 #define FCFG1_FLASH_P_R_PV_PVH2_W 8 1266 #define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF 1267 #define FCFG1_FLASH_P_R_PV_PVH2_S 0 1268 1269 //***************************************************************************** 1270 // 1271 // Register: FCFG1_O_FLASH_EH_SEQ 1272 // 1273 //***************************************************************************** 1274 // Field: [31:24] EH 1275 // 1276 // Internal. Only to be used through TI provided API. 1277 #define FCFG1_FLASH_EH_SEQ_EH_W 8 1278 #define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 1279 #define FCFG1_FLASH_EH_SEQ_EH_S 24 1280 1281 // Field: [23:16] SEQ 1282 // 1283 // Internal. Only to be used through TI provided API. 1284 #define FCFG1_FLASH_EH_SEQ_SEQ_W 8 1285 #define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 1286 #define FCFG1_FLASH_EH_SEQ_SEQ_S 16 1287 1288 // Field: [15:12] VSTAT 1289 // 1290 // Internal. Only to be used through TI provided API. 1291 #define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 1292 #define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 1293 #define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 1294 1295 // Field: [11:0] SM_FREQUENCY 1296 // 1297 // Internal. Only to be used through TI provided API. 1298 #define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 1299 #define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF 1300 #define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 1301 1302 //***************************************************************************** 1303 // 1304 // Register: FCFG1_O_FLASH_VHV_E 1305 // 1306 //***************************************************************************** 1307 // Field: [31:16] VHV_E_START 1308 // 1309 // Internal. Only to be used through TI provided API. 1310 #define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 1311 #define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 1312 #define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 1313 1314 // Field: [15:0] VHV_E_STEP_HIGHT 1315 // 1316 // Internal. Only to be used through TI provided API. 1317 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 1318 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF 1319 #define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 1320 1321 //***************************************************************************** 1322 // 1323 // Register: FCFG1_O_FLASH_PP 1324 // 1325 //***************************************************************************** 1326 // Field: [31:24] PUMP_SU 1327 // 1328 // Internal. Only to be used through TI provided API. 1329 #define FCFG1_FLASH_PP_PUMP_SU_W 8 1330 #define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 1331 #define FCFG1_FLASH_PP_PUMP_SU_S 24 1332 1333 // Field: [23:16] TRIM3P4 1334 // 1335 // Internal. Only to be used through TI provided API. 1336 #define FCFG1_FLASH_PP_TRIM3P4_W 8 1337 #define FCFG1_FLASH_PP_TRIM3P4_M 0x00FF0000 1338 #define FCFG1_FLASH_PP_TRIM3P4_S 16 1339 1340 // Field: [15:0] MAX_PP 1341 // 1342 // Internal. Only to be used through TI provided API. 1343 #define FCFG1_FLASH_PP_MAX_PP_W 16 1344 #define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF 1345 #define FCFG1_FLASH_PP_MAX_PP_S 0 1346 1347 //***************************************************************************** 1348 // 1349 // Register: FCFG1_O_FLASH_PROG_EP 1350 // 1351 //***************************************************************************** 1352 // Field: [31:16] MAX_EP 1353 // 1354 // Internal. Only to be used through TI provided API. 1355 #define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 1356 #define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 1357 #define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 1358 1359 // Field: [15:0] PROGRAM_PW 1360 // 1361 // Internal. Only to be used through TI provided API. 1362 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 1363 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF 1364 #define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 1365 1366 //***************************************************************************** 1367 // 1368 // Register: FCFG1_O_FLASH_ERA_PW 1369 // 1370 //***************************************************************************** 1371 // Field: [31:0] ERASE_PW 1372 // 1373 // Internal. Only to be used through TI provided API. 1374 #define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 1375 #define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF 1376 #define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 1377 1378 //***************************************************************************** 1379 // 1380 // Register: FCFG1_O_FLASH_VHV 1381 // 1382 //***************************************************************************** 1383 // Field: [27:24] TRIM13_P 1384 // 1385 // Internal. Only to be used through TI provided API. 1386 #define FCFG1_FLASH_VHV_TRIM13_P_W 4 1387 #define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 1388 #define FCFG1_FLASH_VHV_TRIM13_P_S 24 1389 1390 // Field: [19:16] VHV_P 1391 // 1392 // Internal. Only to be used through TI provided API. 1393 #define FCFG1_FLASH_VHV_VHV_P_W 4 1394 #define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 1395 #define FCFG1_FLASH_VHV_VHV_P_S 16 1396 1397 // Field: [11:8] TRIM13_E 1398 // 1399 // Internal. Only to be used through TI provided API. 1400 #define FCFG1_FLASH_VHV_TRIM13_E_W 4 1401 #define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 1402 #define FCFG1_FLASH_VHV_TRIM13_E_S 8 1403 1404 // Field: [3:0] VHV_E 1405 // 1406 // Internal. Only to be used through TI provided API. 1407 #define FCFG1_FLASH_VHV_VHV_E_W 4 1408 #define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F 1409 #define FCFG1_FLASH_VHV_VHV_E_S 0 1410 1411 //***************************************************************************** 1412 // 1413 // Register: FCFG1_O_FLASH_VHV_PV 1414 // 1415 //***************************************************************************** 1416 // Field: [27:24] TRIM13_PV 1417 // 1418 // Internal. Only to be used through TI provided API. 1419 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 1420 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 1421 #define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 1422 1423 // Field: [19:16] VHV_PV 1424 // 1425 // Internal. Only to be used through TI provided API. 1426 #define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 1427 #define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 1428 #define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 1429 1430 // Field: [15:8] VCG2P5 1431 // 1432 // Internal. Only to be used through TI provided API. 1433 #define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 1434 #define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 1435 #define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 1436 1437 // Field: [7:0] VINH 1438 // 1439 // Internal. Only to be used through TI provided API. 1440 #define FCFG1_FLASH_VHV_PV_VINH_W 8 1441 #define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF 1442 #define FCFG1_FLASH_VHV_PV_VINH_S 0 1443 1444 //***************************************************************************** 1445 // 1446 // Register: FCFG1_O_FLASH_V 1447 // 1448 //***************************************************************************** 1449 // Field: [31:24] VSL_P 1450 // 1451 // Internal. Only to be used through TI provided API. 1452 #define FCFG1_FLASH_V_VSL_P_W 8 1453 #define FCFG1_FLASH_V_VSL_P_M 0xFF000000 1454 #define FCFG1_FLASH_V_VSL_P_S 24 1455 1456 // Field: [23:16] VWL_P 1457 // 1458 // Internal. Only to be used through TI provided API. 1459 #define FCFG1_FLASH_V_VWL_P_W 8 1460 #define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 1461 #define FCFG1_FLASH_V_VWL_P_S 16 1462 1463 // Field: [15:8] V_READ 1464 // 1465 // Internal. Only to be used through TI provided API. 1466 #define FCFG1_FLASH_V_V_READ_W 8 1467 #define FCFG1_FLASH_V_V_READ_M 0x0000FF00 1468 #define FCFG1_FLASH_V_V_READ_S 8 1469 1470 // Field: [7:0] TRIM0P8 1471 // 1472 // Internal. Only to be used through TI provided API. 1473 #define FCFG1_FLASH_V_TRIM0P8_W 8 1474 #define FCFG1_FLASH_V_TRIM0P8_M 0x000000FF 1475 #define FCFG1_FLASH_V_TRIM0P8_S 0 1476 1477 //***************************************************************************** 1478 // 1479 // Register: FCFG1_O_USER_ID 1480 // 1481 //***************************************************************************** 1482 // Field: [31:28] PG_REV 1483 // 1484 // Field used to distinguish revisions of the device 1485 #define FCFG1_USER_ID_PG_REV_W 4 1486 #define FCFG1_USER_ID_PG_REV_M 0xF0000000 1487 #define FCFG1_USER_ID_PG_REV_S 28 1488 1489 // Field: [27:26] VER 1490 // 1491 // Version number. 1492 // 1493 // 0x0: Bits [25:12] of this register has the stated meaning. 1494 // 1495 // Any other setting indicate a different encoding of these bits. 1496 #define FCFG1_USER_ID_VER_W 2 1497 #define FCFG1_USER_ID_VER_M 0x0C000000 1498 #define FCFG1_USER_ID_VER_S 26 1499 1500 // Field: [25] PA 1501 // 1502 // 0: Does not support 20dBm PA 1503 // 1: Supports 20dBM PA 1504 #define FCFG1_USER_ID_PA 0x02000000 1505 #define FCFG1_USER_ID_PA_BITN 25 1506 #define FCFG1_USER_ID_PA_M 0x02000000 1507 #define FCFG1_USER_ID_PA_S 25 1508 1509 // Field: [23] CC13 1510 // 1511 // 0: CC26xx device type 1512 // 1: CC13xx device type 1513 #define FCFG1_USER_ID_CC13 0x00800000 1514 #define FCFG1_USER_ID_CC13_BITN 23 1515 #define FCFG1_USER_ID_CC13_M 0x00800000 1516 #define FCFG1_USER_ID_CC13_S 23 1517 1518 // Field: [22:19] SEQUENCE 1519 // 1520 // Sequence. 1521 // 1522 // Used to differentiate between marketing/orderable product where other fields 1523 // of this register are the same (temp range, flash size, voltage range etc) 1524 #define FCFG1_USER_ID_SEQUENCE_W 4 1525 #define FCFG1_USER_ID_SEQUENCE_M 0x00780000 1526 #define FCFG1_USER_ID_SEQUENCE_S 19 1527 1528 // Field: [18:16] PKG 1529 // 1530 // Package type. 1531 // 1532 // 0x0: 4x4mm QFN (RHB) package 1533 // 0x1: 5x5mm QFN (RSM) package 1534 // 0x2: 7x7mm QFN (RGZ) package 1535 // 0x3: Wafer sale package (naked die) 1536 // 0x4: WCSP (YFV) 1537 // 0x5: 7x7mm QFN package with Wettable Flanks 1538 // 1539 // Other values are reserved for future use. 1540 // Packages available for a specific device are shown in the device datasheet. 1541 #define FCFG1_USER_ID_PKG_W 3 1542 #define FCFG1_USER_ID_PKG_M 0x00070000 1543 #define FCFG1_USER_ID_PKG_S 16 1544 1545 // Field: [15:12] PROTOCOL 1546 // 1547 // Protocols supported. 1548 // 1549 // 0x1: BLE 1550 // 0x2: RF4CE 1551 // 0x4: Zigbee/6lowpan 1552 // 0x8: Proprietary 1553 // 1554 // More than one protocol can be supported on same device - values above are 1555 // then combined. 1556 #define FCFG1_USER_ID_PROTOCOL_W 4 1557 #define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 1558 #define FCFG1_USER_ID_PROTOCOL_S 12 1559 1560 //***************************************************************************** 1561 // 1562 // Register: FCFG1_O_FLASH_OTP_DATA3 1563 // 1564 //***************************************************************************** 1565 // Field: [31:23] EC_STEP_SIZE 1566 // 1567 // Internal. Only to be used through TI provided API. 1568 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 1569 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 1570 #define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 1571 1572 // Field: [22] DO_PRECOND 1573 // 1574 // Internal. Only to be used through TI provided API. 1575 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 1576 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 1577 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 1578 #define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 1579 1580 // Field: [21:18] MAX_EC_LEVEL 1581 // 1582 // Internal. Only to be used through TI provided API. 1583 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 1584 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 1585 #define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 1586 1587 // Field: [17:16] TRIM_1P7 1588 // 1589 // Internal. Only to be used through TI provided API. 1590 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 1591 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 1592 #define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 1593 1594 // Field: [15:8] FLASH_SIZE 1595 // 1596 // Internal. Only to be used through TI provided API. 1597 #define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 1598 #define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 1599 #define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 1600 1601 // Field: [7:0] WAIT_SYSCODE 1602 // 1603 // Internal. Only to be used through TI provided API. 1604 #define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 1605 #define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF 1606 #define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 1607 1608 //***************************************************************************** 1609 // 1610 // Register: FCFG1_O_ANA2_TRIM 1611 // 1612 //***************************************************************************** 1613 // Field: [31] RCOSCHFCTRIMFRACT_EN 1614 // 1615 // Internal. Only to be used through TI provided API. 1616 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 1617 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 1618 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 1619 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 1620 1621 // Field: [30:26] RCOSCHFCTRIMFRACT 1622 // 1623 // Internal. Only to be used through TI provided API. 1624 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 1625 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 1626 #define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 1627 1628 // Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR 1629 // 1630 // Internal. Only to be used through TI provided API. 1631 #define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 1632 #define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 1633 #define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 1634 1635 // Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM 1636 // 1637 // Internal. Only to be used through TI provided API. 1638 #define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 1639 #define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 1640 #define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 1641 #define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 1642 1643 // Field: [21:15] NANOAMP_RES_TRIM 1644 // 1645 // Internal. Only to be used through TI provided API. 1646 #define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 7 1647 #define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F8000 1648 #define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 15 1649 1650 // Field: [11] DITHER_EN 1651 // 1652 // Internal. Only to be used through TI provided API. 1653 #define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 1654 #define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 1655 #define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 1656 #define FCFG1_ANA2_TRIM_DITHER_EN_S 11 1657 1658 // Field: [10:8] DCDC_IPEAK 1659 // 1660 // Internal. Only to be used through TI provided API. 1661 #define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 1662 #define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 1663 #define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 1664 1665 // Field: [7:6] DEAD_TIME_TRIM 1666 // 1667 // Internal. Only to be used through TI provided API. 1668 #define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 1669 #define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 1670 #define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 1671 1672 // Field: [5:3] DCDC_LOW_EN_SEL 1673 // 1674 // Internal. Only to be used through TI provided API. 1675 #define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 1676 #define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 1677 #define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 1678 1679 // Field: [2:0] DCDC_HIGH_EN_SEL 1680 // 1681 // Internal. Only to be used through TI provided API. 1682 #define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 1683 #define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 1684 #define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 1685 1686 //***************************************************************************** 1687 // 1688 // Register: FCFG1_O_LDO_TRIM 1689 // 1690 //***************************************************************************** 1691 // Field: [28:24] VDDR_TRIM_SLEEP 1692 // 1693 // Internal. Only to be used through TI provided API. 1694 #define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 1695 #define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 1696 #define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 1697 1698 // Field: [18:16] GLDO_CURSRC 1699 // 1700 // Internal. Only to be used through TI provided API. 1701 #define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 1702 #define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 1703 #define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 1704 1705 // Field: [12:11] ITRIM_DIGLDO_LOAD 1706 // 1707 // Internal. Only to be used through TI provided API. 1708 #define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 1709 #define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 1710 #define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 1711 1712 // Field: [10:8] ITRIM_UDIGLDO 1713 // 1714 // Internal. Only to be used through TI provided API. 1715 #define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 1716 #define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 1717 #define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 1718 1719 // Field: [2:0] VTRIM_DELTA 1720 // 1721 // Internal. Only to be used through TI provided API. 1722 #define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 1723 #define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 1724 #define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 1725 1726 //***************************************************************************** 1727 // 1728 // Register: FCFG1_O_MAC_BLE_0 1729 // 1730 //***************************************************************************** 1731 // Field: [31:0] ADDR_0_31 1732 // 1733 // The first 32-bits of the 64-bit MAC BLE address 1734 #define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 1735 #define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF 1736 #define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 1737 1738 //***************************************************************************** 1739 // 1740 // Register: FCFG1_O_MAC_BLE_1 1741 // 1742 //***************************************************************************** 1743 // Field: [31:0] ADDR_32_63 1744 // 1745 // The last 32-bits of the 64-bit MAC BLE address 1746 #define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 1747 #define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF 1748 #define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 1749 1750 //***************************************************************************** 1751 // 1752 // Register: FCFG1_O_MAC_15_4_0 1753 // 1754 //***************************************************************************** 1755 // Field: [31:0] ADDR_0_31 1756 // 1757 // The first 32-bits of the 64-bit MAC 15.4 address 1758 #define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 1759 #define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF 1760 #define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 1761 1762 //***************************************************************************** 1763 // 1764 // Register: FCFG1_O_MAC_15_4_1 1765 // 1766 //***************************************************************************** 1767 // Field: [31:0] ADDR_32_63 1768 // 1769 // The last 32-bits of the 64-bit MAC 15.4 address 1770 #define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 1771 #define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF 1772 #define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 1773 1774 //***************************************************************************** 1775 // 1776 // Register: FCFG1_O_FLASH_OTP_DATA4 1777 // 1778 //***************************************************************************** 1779 // Field: [31] STANDBY_MODE_SEL_INT_WRT 1780 // 1781 // Internal. Only to be used through TI provided API. 1782 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 1783 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 1784 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 1785 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 1786 1787 // Field: [30:29] STANDBY_PW_SEL_INT_WRT 1788 // 1789 // Internal. Only to be used through TI provided API. 1790 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 1791 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 1792 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 1793 1794 // Field: [28] DIS_STANDBY_INT_WRT 1795 // 1796 // Internal. Only to be used through TI provided API. 1797 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 1798 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 1799 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 1800 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 1801 1802 // Field: [27] DIS_IDLE_INT_WRT 1803 // 1804 // Internal. Only to be used through TI provided API. 1805 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 1806 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 1807 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 1808 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 1809 1810 // Field: [26:24] VIN_AT_X_INT_WRT 1811 // 1812 // Internal. Only to be used through TI provided API. 1813 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 1814 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 1815 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 1816 1817 // Field: [23] STANDBY_MODE_SEL_EXT_WRT 1818 // 1819 // Internal. Only to be used through TI provided API. 1820 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 1821 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 1822 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 1823 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 1824 1825 // Field: [22:21] STANDBY_PW_SEL_EXT_WRT 1826 // 1827 // Internal. Only to be used through TI provided API. 1828 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 1829 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 1830 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 1831 1832 // Field: [20] DIS_STANDBY_EXT_WRT 1833 // 1834 // Internal. Only to be used through TI provided API. 1835 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 1836 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 1837 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 1838 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 1839 1840 // Field: [19] DIS_IDLE_EXT_WRT 1841 // 1842 // Internal. Only to be used through TI provided API. 1843 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 1844 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 1845 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 1846 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 1847 1848 // Field: [18:16] VIN_AT_X_EXT_WRT 1849 // 1850 // Internal. Only to be used through TI provided API. 1851 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 1852 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 1853 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 1854 1855 // Field: [15] STANDBY_MODE_SEL_INT_RD 1856 // 1857 // Internal. Only to be used through TI provided API. 1858 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 1859 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 1860 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 1861 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 1862 1863 // Field: [14:13] STANDBY_PW_SEL_INT_RD 1864 // 1865 // Internal. Only to be used through TI provided API. 1866 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 1867 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 1868 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 1869 1870 // Field: [12] DIS_STANDBY_INT_RD 1871 // 1872 // Internal. Only to be used through TI provided API. 1873 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 1874 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 1875 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 1876 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 1877 1878 // Field: [11] DIS_IDLE_INT_RD 1879 // 1880 // Internal. Only to be used through TI provided API. 1881 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 1882 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 1883 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 1884 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 1885 1886 // Field: [10:8] VIN_AT_X_INT_RD 1887 // 1888 // Internal. Only to be used through TI provided API. 1889 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 1890 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 1891 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 1892 1893 // Field: [7] STANDBY_MODE_SEL_EXT_RD 1894 // 1895 // Internal. Only to be used through TI provided API. 1896 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 1897 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 1898 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 1899 #define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 1900 1901 // Field: [6:5] STANDBY_PW_SEL_EXT_RD 1902 // 1903 // Internal. Only to be used through TI provided API. 1904 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 1905 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 1906 #define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 1907 1908 // Field: [4] DIS_STANDBY_EXT_RD 1909 // 1910 // Internal. Only to be used through TI provided API. 1911 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 1912 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 1913 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 1914 #define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 1915 1916 // Field: [3] DIS_IDLE_EXT_RD 1917 // 1918 // Internal. Only to be used through TI provided API. 1919 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 1920 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 1921 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 1922 #define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 1923 1924 // Field: [2:0] VIN_AT_X_EXT_RD 1925 // 1926 // Internal. Only to be used through TI provided API. 1927 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 1928 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 1929 #define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 1930 1931 //***************************************************************************** 1932 // 1933 // Register: FCFG1_O_MISC_TRIM 1934 // 1935 //***************************************************************************** 1936 // Field: [16:12] TRIM_RECHARGE_COMP_OFFSET 1937 // 1938 // Internal. Only to be used through TI provided API. 1939 #define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_W 5 1940 #define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_M 0x0001F000 1941 #define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_S 12 1942 1943 // Field: [11:8] TRIM_RECHARGE_COMP_REFLEVEL 1944 // 1945 // Internal. Only to be used through TI provided API. 1946 #define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_W 4 1947 #define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_M 0x00000F00 1948 #define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_S 8 1949 1950 // Field: [7:0] TEMPVSLOPE 1951 // 1952 // Signed byte value representing the TEMP slope with battery voltage, in 1953 // degrees C / V, with four fractional bits. 1954 #define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 1955 #define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF 1956 #define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 1957 1958 //***************************************************************************** 1959 // 1960 // Register: FCFG1_O_RCOSC_HF_TEMPCOMP 1961 // 1962 //***************************************************************************** 1963 // Field: [31:24] FINE_RESISTOR 1964 // 1965 // Internal. Only to be used through TI provided API. 1966 #define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 1967 #define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 1968 #define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 1969 1970 // Field: [23:16] CTRIM 1971 // 1972 // Internal. Only to be used through TI provided API. 1973 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 1974 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 1975 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 1976 1977 // Field: [15:8] CTRIMFRACT_QUAD 1978 // 1979 // Internal. Only to be used through TI provided API. 1980 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 1981 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 1982 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 1983 1984 // Field: [7:0] CTRIMFRACT_SLOPE 1985 // 1986 // Internal. Only to be used through TI provided API. 1987 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 1988 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF 1989 #define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 1990 1991 //***************************************************************************** 1992 // 1993 // Register: FCFG1_O_ICEPICK_DEVICE_ID 1994 // 1995 //***************************************************************************** 1996 // Field: [31:28] PG_REV 1997 // 1998 // Field used to distinguish revisions of the device. 1999 #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 2000 #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 2001 #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 2002 2003 // Field: [27:12] WAFER_ID 2004 // 2005 // Field used to identify silicon die. 2006 #define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 2007 #define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 2008 #define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 2009 2010 // Field: [11:0] MANUFACTURER_ID 2011 // 2012 // Manufacturer code. 2013 // 2014 // 0x02F: Texas Instruments 2015 #define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 2016 #define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF 2017 #define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 2018 2019 //***************************************************************************** 2020 // 2021 // Register: FCFG1_O_FCFG1_REVISION 2022 // 2023 //***************************************************************************** 2024 // Field: [31:0] REV 2025 // 2026 // The revision number of the FCFG1 layout. This value will be read by 2027 // application SW in order to determine which FCFG1 parameters that have valid 2028 // values. This revision number must be incremented by 1 before any devices are 2029 // to be produced if the FCFG1 layout has changed since the previous production 2030 // of devices. 2031 // Value migth change without warning. 2032 #define FCFG1_FCFG1_REVISION_REV_W 32 2033 #define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF 2034 #define FCFG1_FCFG1_REVISION_REV_S 0 2035 2036 //***************************************************************************** 2037 // 2038 // Register: FCFG1_O_MISC_OTP_DATA 2039 // 2040 //***************************************************************************** 2041 // Field: [31:28] RCOSC_HF_ITUNE 2042 // 2043 // Internal. Only to be used through TI provided API. 2044 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 2045 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 2046 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 2047 2048 // Field: [27:20] RCOSC_HF_CRIM 2049 // 2050 // Internal. Only to be used through TI provided API. 2051 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 2052 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 2053 #define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 2054 2055 // Field: [19:15] PER_M 2056 // 2057 // Internal. Only to be used through TI provided API. 2058 #define FCFG1_MISC_OTP_DATA_PER_M_W 5 2059 #define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 2060 #define FCFG1_MISC_OTP_DATA_PER_M_S 15 2061 2062 // Field: [14:12] PER_E 2063 // 2064 // Internal. Only to be used through TI provided API. 2065 #define FCFG1_MISC_OTP_DATA_PER_E_W 3 2066 #define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 2067 #define FCFG1_MISC_OTP_DATA_PER_E_S 12 2068 2069 //***************************************************************************** 2070 // 2071 // Register: FCFG1_O_IOCONF 2072 // 2073 //***************************************************************************** 2074 // Field: [6:0] GPIO_CNT 2075 // 2076 // Number of available DIOs. 2077 #define FCFG1_IOCONF_GPIO_CNT_W 7 2078 #define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F 2079 #define FCFG1_IOCONF_GPIO_CNT_S 0 2080 2081 //***************************************************************************** 2082 // 2083 // Register: FCFG1_O_CONFIG_IF_ADC 2084 // 2085 //***************************************************************************** 2086 // Field: [31:28] FF2ADJ 2087 // 2088 // Internal. Only to be used through TI provided API. 2089 #define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 2090 #define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 2091 #define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 2092 2093 // Field: [27:24] FF3ADJ 2094 // 2095 // Internal. Only to be used through TI provided API. 2096 #define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 2097 #define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 2098 #define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 2099 2100 // Field: [23:20] INT3ADJ 2101 // 2102 // Internal. Only to be used through TI provided API. 2103 #define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 2104 #define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 2105 #define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 2106 2107 // Field: [19:16] FF1ADJ 2108 // 2109 // Internal. Only to be used through TI provided API. 2110 #define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 2111 #define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 2112 #define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 2113 2114 // Field: [15:14] AAFCAP 2115 // 2116 // Internal. Only to be used through TI provided API. 2117 #define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 2118 #define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 2119 #define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 2120 2121 // Field: [13:10] INT2ADJ 2122 // 2123 // Internal. Only to be used through TI provided API. 2124 #define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 2125 #define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 2126 #define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 2127 2128 // Field: [9:5] IFDIGLDO_TRIM_OUTPUT 2129 // 2130 // Internal. Only to be used through TI provided API. 2131 #define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 2132 #define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 2133 #define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 2134 2135 // Field: [4:0] IFANALDO_TRIM_OUTPUT 2136 // 2137 // Internal. Only to be used through TI provided API. 2138 #define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 2139 #define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F 2140 #define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 2141 2142 //***************************************************************************** 2143 // 2144 // Register: FCFG1_O_CONFIG_OSC_TOP 2145 // 2146 //***************************************************************************** 2147 // Field: [29:26] XOSC_HF_ROW_Q12 2148 // 2149 // Internal. Only to be used through TI provided API. 2150 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 2151 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 2152 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 2153 2154 // Field: [25:10] XOSC_HF_COLUMN_Q12 2155 // 2156 // Internal. Only to be used through TI provided API. 2157 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 2158 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 2159 #define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 2160 2161 // Field: [9:2] RCOSCLF_CTUNE_TRIM 2162 // 2163 // Internal. Only to be used through TI provided API. 2164 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 2165 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC 2166 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 2167 2168 // Field: [1:0] RCOSCLF_RTUNE_TRIM 2169 // 2170 // Internal. Only to be used through TI provided API. 2171 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 2172 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 2173 #define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 2174 2175 //***************************************************************************** 2176 // 2177 // Register: FCFG1_O_SOC_ADC_ABS_GAIN 2178 // 2179 //***************************************************************************** 2180 // Field: [15:0] SOC_ADC_ABS_GAIN_TEMP1 2181 // 2182 // SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated 2183 // in production test.. 2184 #define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 2185 #define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF 2186 #define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 2187 2188 //***************************************************************************** 2189 // 2190 // Register: FCFG1_O_SOC_ADC_REL_GAIN 2191 // 2192 //***************************************************************************** 2193 // Field: [15:0] SOC_ADC_REL_GAIN_TEMP1 2194 // 2195 // SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated 2196 // in production test.. 2197 #define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 2198 #define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF 2199 #define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 2200 2201 //***************************************************************************** 2202 // 2203 // Register: FCFG1_O_SOC_ADC_OFFSET_INT 2204 // 2205 //***************************************************************************** 2206 // Field: [23:16] SOC_ADC_REL_OFFSET_TEMP1 2207 // 2208 // SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed 2209 // 8-bit number. Calculated in production test.. 2210 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 2211 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 2212 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 2213 2214 // Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 2215 // 2216 // SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed 2217 // 8-bit number. Calculated in production test.. 2218 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 2219 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF 2220 #define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 2221 2222 //***************************************************************************** 2223 // 2224 // Register: FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 2225 // 2226 //***************************************************************************** 2227 // Field: [5:0] SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 2228 // 2229 // Internal. Only to be used through TI provided API. 2230 #define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_W \ 2231 6 2232 #define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_M \ 2233 0x0000003F 2234 #define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S \ 2235 0 2236 2237 //***************************************************************************** 2238 // 2239 // Register: FCFG1_O_AMPCOMP_TH1 2240 // 2241 //***************************************************************************** 2242 // Field: [23:18] HPMRAMP3_LTH 2243 // 2244 // Internal. Only to be used through TI provided API. 2245 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 2246 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 2247 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 2248 2249 // Field: [15:10] HPMRAMP3_HTH 2250 // 2251 // Internal. Only to be used through TI provided API. 2252 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 2253 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 2254 #define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 2255 2256 // Field: [9:6] IBIASCAP_LPTOHP_OL_CNT 2257 // 2258 // Internal. Only to be used through TI provided API. 2259 #define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 2260 #define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 2261 #define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 2262 2263 // Field: [5:0] HPMRAMP1_TH 2264 // 2265 // Internal. Only to be used through TI provided API. 2266 #define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 2267 #define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F 2268 #define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 2269 2270 //***************************************************************************** 2271 // 2272 // Register: FCFG1_O_AMPCOMP_TH2 2273 // 2274 //***************************************************************************** 2275 // Field: [31:26] LPMUPDATE_LTH 2276 // 2277 // Internal. Only to be used through TI provided API. 2278 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 2279 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 2280 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 2281 2282 // Field: [23:18] LPMUPDATE_HTM 2283 // 2284 // Internal. Only to be used through TI provided API. 2285 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 2286 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 2287 #define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 2288 2289 // Field: [15:10] ADC_COMP_AMPTH_LPM 2290 // 2291 // Internal. Only to be used through TI provided API. 2292 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 2293 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 2294 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 2295 2296 // Field: [7:2] ADC_COMP_AMPTH_HPM 2297 // 2298 // Internal. Only to be used through TI provided API. 2299 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 2300 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC 2301 #define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 2302 2303 //***************************************************************************** 2304 // 2305 // Register: FCFG1_O_AMPCOMP_CTRL1 2306 // 2307 //***************************************************************************** 2308 // Field: [30] AMPCOMP_REQ_MODE 2309 // 2310 // Internal. Only to be used through TI provided API. 2311 #define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 2312 #define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 2313 #define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 2314 #define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 2315 2316 // Field: [23:20] IBIAS_OFFSET 2317 // 2318 // Internal. Only to be used through TI provided API. 2319 #define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 2320 #define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 2321 #define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 2322 2323 // Field: [19:16] IBIAS_INIT 2324 // 2325 // Internal. Only to be used through TI provided API. 2326 #define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 2327 #define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 2328 #define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 2329 2330 // Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL 2331 // 2332 // Internal. Only to be used through TI provided API. 2333 #define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 2334 #define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 2335 #define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 2336 2337 // Field: [7:4] CAP_STEP 2338 // 2339 // Internal. Only to be used through TI provided API. 2340 #define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 2341 #define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 2342 #define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 2343 2344 // Field: [3:0] IBIASCAP_HPTOLP_OL_CNT 2345 // 2346 // Internal. Only to be used through TI provided API. 2347 #define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 2348 #define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F 2349 #define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 2350 2351 //***************************************************************************** 2352 // 2353 // Register: FCFG1_O_ANABYPASS_VALUE2 2354 // 2355 //***************************************************************************** 2356 // Field: [13:0] XOSC_HF_IBIASTHERM 2357 // 2358 // Internal. Only to be used through TI provided API. 2359 #define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 2360 #define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF 2361 #define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 2362 2363 //***************************************************************************** 2364 // 2365 // Register: FCFG1_O_VOLT_TRIM 2366 // 2367 //***************************************************************************** 2368 // Field: [28:24] VDDR_TRIM_HH 2369 // 2370 // Internal. Only to be used through TI provided API. 2371 #define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 2372 #define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 2373 #define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 2374 2375 // Field: [20:16] VDDR_TRIM_H 2376 // 2377 // Internal. Only to be used through TI provided API. 2378 #define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 2379 #define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 2380 #define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 2381 2382 // Field: [12:8] VDDR_TRIM_SLEEP_H 2383 // 2384 // Internal. Only to be used through TI provided API. 2385 #define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 2386 #define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 2387 #define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 2388 2389 // Field: [4:0] TRIMBOD_H 2390 // 2391 // Internal. Only to be used through TI provided API. 2392 #define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 2393 #define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F 2394 #define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 2395 2396 //***************************************************************************** 2397 // 2398 // Register: FCFG1_O_OSC_CONF 2399 // 2400 //***************************************************************************** 2401 // Field: [29] ADC_SH_VBUF_EN 2402 // 2403 // Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. 2404 #define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 2405 #define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 2406 #define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 2407 #define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 2408 2409 // Field: [28] ADC_SH_MODE_EN 2410 // 2411 // Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. 2412 #define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 2413 #define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 2414 #define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 2415 #define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 2416 2417 // Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM 2418 // 2419 // Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. 2420 #define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 2421 #define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 2422 #define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 2423 #define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 2424 2425 // Field: [26:25] XOSCLF_REGULATOR_TRIM 2426 // 2427 // Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. 2428 #define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 2429 #define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 2430 #define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 2431 2432 // Field: [24:21] XOSCLF_CMIRRWR_RATIO 2433 // 2434 // Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. 2435 #define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 2436 #define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 2437 #define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 2438 2439 // Field: [20:19] XOSC_HF_FAST_START 2440 // 2441 // Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. 2442 #define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 2443 #define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 2444 #define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 2445 2446 // Field: [18] XOSC_OPTION 2447 // 2448 // 0: XOSC_HF unavailable (may not be bonded out) 2449 // 1: XOSC_HF available (default) 2450 #define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 2451 #define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 2452 #define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 2453 #define FCFG1_OSC_CONF_XOSC_OPTION_S 18 2454 2455 // Field: [17] HPOSC_OPTION 2456 // 2457 // Internal. Only to be used through TI provided API. 2458 #define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 2459 #define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 2460 #define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 2461 #define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 2462 2463 // Field: [16] HPOSC_BIAS_HOLD_MODE_EN 2464 // 2465 // Internal. Only to be used through TI provided API. 2466 #define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 2467 #define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 2468 #define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 2469 #define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 2470 2471 // Field: [15:12] HPOSC_CURRMIRR_RATIO 2472 // 2473 // Internal. Only to be used through TI provided API. 2474 #define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 2475 #define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 2476 #define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 2477 2478 // Field: [11:8] HPOSC_BIAS_RES_SET 2479 // 2480 // Internal. Only to be used through TI provided API. 2481 #define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 2482 #define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 2483 #define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 2484 2485 // Field: [7] HPOSC_FILTER_EN 2486 // 2487 // Internal. Only to be used through TI provided API. 2488 #define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 2489 #define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 2490 #define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 2491 #define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 2492 2493 // Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY 2494 // 2495 // Internal. Only to be used through TI provided API. 2496 #define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 2497 #define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 2498 #define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 2499 2500 // Field: [2:1] HPOSC_SERIES_CAP 2501 // 2502 // Internal. Only to be used through TI provided API. 2503 #define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 2504 #define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 2505 #define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 2506 2507 // Field: [0] HPOSC_DIV3_BYPASS 2508 // 2509 // Internal. Only to be used through TI provided API. 2510 #define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 2511 #define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 2512 #define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 2513 #define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 2514 2515 //***************************************************************************** 2516 // 2517 // Register: FCFG1_O_FREQ_OFFSET 2518 // 2519 //***************************************************************************** 2520 // Field: [31:16] HPOSC_COMP_P0 2521 // 2522 // Internal. Only to be used through TI provided API. 2523 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 2524 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 2525 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 2526 2527 // Field: [15:8] HPOSC_COMP_P1 2528 // 2529 // Internal. Only to be used through TI provided API. 2530 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 2531 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 2532 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 2533 2534 // Field: [7:0] HPOSC_COMP_P2 2535 // 2536 // Internal. Only to be used through TI provided API. 2537 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 2538 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF 2539 #define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 2540 2541 //***************************************************************************** 2542 // 2543 // Register: FCFG1_O_MISC_OTP_DATA_1 2544 // 2545 //***************************************************************************** 2546 // Field: [28:27] PEAK_DET_ITRIM 2547 // 2548 // Internal. Only to be used through TI provided API. 2549 #define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 2550 #define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 2551 #define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 2552 2553 // Field: [26:24] HP_BUF_ITRIM 2554 // 2555 // Internal. Only to be used through TI provided API. 2556 #define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 2557 #define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 2558 #define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 2559 2560 // Field: [23:22] LP_BUF_ITRIM 2561 // 2562 // Internal. Only to be used through TI provided API. 2563 #define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 2564 #define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 2565 #define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 2566 2567 // Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE 2568 // 2569 // Internal. Only to be used through TI provided API. 2570 #define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 2571 #define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 2572 #define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 2573 2574 // Field: [19:10] HPM_IBIAS_WAIT_CNT 2575 // 2576 // Internal. Only to be used through TI provided API. 2577 #define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 2578 #define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 2579 #define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 2580 2581 // Field: [9:4] LPM_IBIAS_WAIT_CNT 2582 // 2583 // Internal. Only to be used through TI provided API. 2584 #define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 2585 #define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 2586 #define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 2587 2588 // Field: [3:0] IDAC_STEP 2589 // 2590 // Internal. Only to be used through TI provided API. 2591 #define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 2592 #define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F 2593 #define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 2594 2595 //***************************************************************************** 2596 // 2597 // Register: FCFG1_O_SHDW_DIE_ID_0 2598 // 2599 //***************************************************************************** 2600 // Field: [31:0] ID_31_0 2601 // 2602 // Shadow of DIE_ID_0 register in eFuse row number 5 2603 #define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 2604 #define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF 2605 #define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 2606 2607 //***************************************************************************** 2608 // 2609 // Register: FCFG1_O_SHDW_DIE_ID_1 2610 // 2611 //***************************************************************************** 2612 // Field: [31:0] ID_63_32 2613 // 2614 // Shadow of DIE_ID_1 register in eFuse row number 6 2615 #define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 2616 #define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF 2617 #define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 2618 2619 //***************************************************************************** 2620 // 2621 // Register: FCFG1_O_SHDW_DIE_ID_2 2622 // 2623 //***************************************************************************** 2624 // Field: [31:0] ID_95_64 2625 // 2626 // Shadow of DIE_ID_2 register in eFuse row number 7 2627 #define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 2628 #define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF 2629 #define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 2630 2631 //***************************************************************************** 2632 // 2633 // Register: FCFG1_O_SHDW_DIE_ID_3 2634 // 2635 //***************************************************************************** 2636 // Field: [31:0] ID_127_96 2637 // 2638 // Shadow of DIE_ID_3 register in eFuse row number 8 2639 #define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 2640 #define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF 2641 #define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 2642 2643 //***************************************************************************** 2644 // 2645 // Register: FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 2646 // 2647 //***************************************************************************** 2648 // Field: [26:23] TRIMMAG 2649 // 2650 // Internal. Only to be used through TI provided API. 2651 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 2652 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 2653 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 2654 2655 // Field: [22:18] TRIMIREF 2656 // 2657 // Internal. Only to be used through TI provided API. 2658 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 2659 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 2660 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 2661 2662 // Field: [17:16] ITRIM_DIG_LDO 2663 // 2664 // Internal. Only to be used through TI provided API. 2665 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 2666 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 2667 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 2668 2669 // Field: [15:12] VTRIM_DIG 2670 // 2671 // Internal. Only to be used through TI provided API. 2672 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 2673 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 2674 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 2675 2676 // Field: [11:8] VTRIM_COARSE 2677 // 2678 // Internal. Only to be used through TI provided API. 2679 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 2680 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 2681 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 2682 2683 // Field: [7:0] RCOSCHF_CTRIM 2684 // 2685 // Internal. Only to be used through TI provided API. 2686 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 2687 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF 2688 #define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 2689 2690 //***************************************************************************** 2691 // 2692 // Register: FCFG1_O_SHDW_ANA_TRIM 2693 // 2694 //***************************************************************************** 2695 // Field: [30] ALT_VDDR_TRIM 2696 // 2697 // Internal. Only to be used through TI provided API. 2698 #define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM 0x40000000 2699 #define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_BITN 30 2700 #define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_M 0x40000000 2701 #define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_S 30 2702 2703 // Field: [29] DET_LOGIC_DIS 2704 // 2705 // Internal. Only to be used through TI provided API. 2706 #define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS 0x20000000 2707 #define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_BITN 29 2708 #define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_M 0x20000000 2709 #define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_S 29 2710 2711 // Field: [28:27] BOD_BANDGAP_TRIM_CNF_EXT 2712 // 2713 // Internal. Only to be used through TI provided API. 2714 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_W 2 2715 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_M 0x18000000 2716 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_S 27 2717 2718 // Field: [26:25] BOD_BANDGAP_TRIM_CNF 2719 // 2720 // Internal. Only to be used through TI provided API. 2721 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 2722 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 2723 #define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 2724 2725 // Field: [24] VDDR_ENABLE_PG1 2726 // 2727 // Internal. Only to be used through TI provided API. 2728 #define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 2729 #define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 2730 #define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 2731 #define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 2732 2733 // Field: [23] VDDR_OK_HYS 2734 // 2735 // Internal. Only to be used through TI provided API. 2736 #define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 2737 #define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 2738 #define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 2739 #define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 2740 2741 // Field: [22:21] IPTAT_TRIM 2742 // 2743 // Internal. Only to be used through TI provided API. 2744 #define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 2745 #define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 2746 #define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 2747 2748 // Field: [20:16] VDDR_TRIM 2749 // 2750 // Internal. Only to be used through TI provided API. 2751 #define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 2752 #define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 2753 #define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 2754 2755 // Field: [15:11] TRIMBOD_INTMODE 2756 // 2757 // Internal. Only to be used through TI provided API. 2758 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 2759 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 2760 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 2761 2762 // Field: [10:6] TRIMBOD_EXTMODE 2763 // 2764 // Internal. Only to be used through TI provided API. 2765 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 2766 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 2767 #define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 2768 2769 // Field: [5:0] TRIMTEMP 2770 // 2771 // Internal. Only to be used through TI provided API. 2772 #define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 2773 #define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F 2774 #define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 2775 2776 //***************************************************************************** 2777 // 2778 // Register: FCFG1_O_DAC_BIAS_CNF 2779 // 2780 //***************************************************************************** 2781 // Field: [17:12] LPM_TRIM_IOUT 2782 // 2783 // Internal. Only to be used through TI provided API. 2784 #define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_W 6 2785 #define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M 0x0003F000 2786 #define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S 12 2787 2788 // Field: [11:9] LPM_BIAS_WIDTH_TRIM 2789 // 2790 // Internal. Only to be used through TI provided API. 2791 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_W 3 2792 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M 0x00000E00 2793 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S 9 2794 2795 // Field: [8] LPM_BIAS_BACKUP_EN 2796 // 2797 // Internal. Only to be used through TI provided API. 2798 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN 0x00000100 2799 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_BITN 8 2800 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_M 0x00000100 2801 #define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_S 8 2802 2803 //***************************************************************************** 2804 // 2805 // Register: FCFG1_O_TFW_PROBE 2806 // 2807 //***************************************************************************** 2808 // Field: [31:0] REV 2809 // 2810 // Internal. Only to be used through TI provided API. 2811 #define FCFG1_TFW_PROBE_REV_W 32 2812 #define FCFG1_TFW_PROBE_REV_M 0xFFFFFFFF 2813 #define FCFG1_TFW_PROBE_REV_S 0 2814 2815 //***************************************************************************** 2816 // 2817 // Register: FCFG1_O_TFW_FT 2818 // 2819 //***************************************************************************** 2820 // Field: [31:0] REV 2821 // 2822 // Internal. Only to be used through TI provided API. 2823 #define FCFG1_TFW_FT_REV_W 32 2824 #define FCFG1_TFW_FT_REV_M 0xFFFFFFFF 2825 #define FCFG1_TFW_FT_REV_S 0 2826 2827 //***************************************************************************** 2828 // 2829 // Register: FCFG1_O_DAC_CAL0 2830 // 2831 //***************************************************************************** 2832 // Field: [31:16] SOC_DAC_VOUT_CAL_DECOUPLE_C2 2833 // 2834 // Internal. Only to be used through TI provided API. 2835 #define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_W 16 2836 #define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_M 0xFFFF0000 2837 #define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_S 16 2838 2839 // Field: [15:0] SOC_DAC_VOUT_CAL_DECOUPLE_C1 2840 // 2841 // Internal. Only to be used through TI provided API. 2842 #define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_W 16 2843 #define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_M 0x0000FFFF 2844 #define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_S 0 2845 2846 //***************************************************************************** 2847 // 2848 // Register: FCFG1_O_DAC_CAL1 2849 // 2850 //***************************************************************************** 2851 // Field: [31:16] SOC_DAC_VOUT_CAL_PRECH_C2 2852 // 2853 // Internal. Only to be used through TI provided API. 2854 #define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_W 16 2855 #define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_M 0xFFFF0000 2856 #define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_S 16 2857 2858 // Field: [15:0] SOC_DAC_VOUT_CAL_PRECH_C1 2859 // 2860 // Internal. Only to be used through TI provided API. 2861 #define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_W 16 2862 #define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_M 0x0000FFFF 2863 #define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_S 0 2864 2865 //***************************************************************************** 2866 // 2867 // Register: FCFG1_O_DAC_CAL2 2868 // 2869 //***************************************************************************** 2870 // Field: [31:16] SOC_DAC_VOUT_CAL_ADCREF_C2 2871 // 2872 // Internal. Only to be used through TI provided API. 2873 #define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_W 16 2874 #define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_M 0xFFFF0000 2875 #define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_S 16 2876 2877 // Field: [15:0] SOC_DAC_VOUT_CAL_ADCREF_C1 2878 // 2879 // Internal. Only to be used through TI provided API. 2880 #define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_W 16 2881 #define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_M 0x0000FFFF 2882 #define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_S 0 2883 2884 //***************************************************************************** 2885 // 2886 // Register: FCFG1_O_DAC_CAL3 2887 // 2888 //***************************************************************************** 2889 // Field: [31:16] SOC_DAC_VOUT_CAL_VDDS_C2 2890 // 2891 // Internal. Only to be used through TI provided API. 2892 #define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_W 16 2893 #define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_M 0xFFFF0000 2894 #define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_S 16 2895 2896 // Field: [15:0] SOC_DAC_VOUT_CAL_VDDS_C1 2897 // 2898 // Internal. Only to be used through TI provided API. 2899 #define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_W 16 2900 #define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_M 0x0000FFFF 2901 #define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_S 0 2902 2903 2904 #endif // __FCFG1__ 2905
