1 /* --COPYRIGHT--,BSD 2 * Copyright (c) 2017, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * --/COPYRIGHT--*/ 32 #ifndef SPI_H_ 33 #define SPI_H_ 34 35 //***************************************************************************** 36 // 37 //! \addtogroup spi_api 38 //! @{ 39 // 40 //***************************************************************************** 41 42 //***************************************************************************** 43 // 44 // If building with a C++ compiler, make all of the definitions in this header 45 // have a C binding. 46 // 47 //***************************************************************************** 48 #ifdef __cplusplus 49 extern "C" 50 { 51 #endif 52 53 #include <stdbool.h> 54 #include <stdint.h> 55 #include <ti/devices/msp432p4xx/inc/msp.h> 56 #include <ti/devices/msp432p4xx/driverlib/eusci.h> 57 58 /* Configuration Defines */ 59 #define EUSCI_SPI_CLOCKSOURCE_ACLK EUSCI_B_CTLW0_SSEL__ACLK 60 #define EUSCI_SPI_CLOCKSOURCE_SMCLK EUSCI_B_CTLW0_SSEL__SMCLK 61 62 #define EUSCI_SPI_MSB_FIRST EUSCI_B_CTLW0_MSB 63 #define EUSCI_SPI_LSB_FIRST 0x00 64 65 #define EUSCI_SPI_BUSY EUSCI_A_STATW_BUSY 66 #define EUSCI_SPI_NOT_BUSY 0x00 67 68 #define EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 69 #define EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT EUSCI_B_CTLW0_CKPH 70 71 #define EUSCI_SPI_3PIN EUSCI_B_CTLW0_MODE_0 72 #define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH EUSCI_B_CTLW0_MODE_1 73 #define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW EUSCI_B_CTLW0_MODE_2 74 75 #define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH EUSCI_B_CTLW0_CKPL 76 #define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 77 78 #define EUSCI_SPI_TRANSMIT_INTERRUPT EUSCI_B_IE_TXIE_OFS 79 #define EUSCI_SPI_RECEIVE_INTERRUPT EUSCI_B_IE_RXIE_OFS 80 81 #define EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE EUSCI_B_CTLW0_STEM 82 #define EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00 83 84 //***************************************************************************** 85 // 86 //! ypedef eUSCI_SPI_MasterConfig 87 //! \brief Type definition for \link _eUSCI_SPI_MasterConfig \endlink structure 88 //! 89 //! \struct _eUSCI_SPI_MasterConfig 90 //! \brief Configuration structure for master mode in the \b SPI module. See 91 //! \link SPI_initMaster \endlink for parameter documentation. 92 // 93 //***************************************************************************** 94 typedef struct _eUSCI_SPI_MasterConfig 95 { 96 uint_fast8_t selectClockSource; 97 uint32_t clockSourceFrequency; 98 uint32_t desiredSpiClock; 99 uint_fast16_t msbFirst; 100 uint_fast16_t clockPhase; 101 uint_fast16_t clockPolarity; 102 uint_fast16_t spiMode; 103 } eUSCI_SPI_MasterConfig; 104 105 //***************************************************************************** 106 // 107 //! ypedef eUSCI_SPI_SlaveConfig 108 //! \brief Type definition for \link _eUSCI_SPI_SlaveConfig \endlink structure 109 //! 110 //! \struct _eUSCI_SPI_SlaveConfig 111 //! \brief Configuration structure for slave mode in the \b SPI module. See 112 //! \link SPI_initSlave \endlink for parameter documentation. 113 // 114 //***************************************************************************** 115 typedef struct _eUSCI_SPI_SlaveConfig 116 { 117 uint_fast16_t msbFirst; 118 uint_fast16_t clockPhase; 119 uint_fast16_t clockPolarity; 120 uint_fast16_t spiMode; 121 } eUSCI_SPI_SlaveConfig; 122 123 //***************************************************************************** 124 // 125 //! Initializes the SPI Master block. 126 //! 127 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 128 //! parameters vary from part to part, but can include: 129 //! - \b EUSCI_A0_BASE 130 //! - \b EUSCI_A1_BASE 131 //! - \b EUSCI_A2_BASE 132 //! - \b EUSCI_A3_BASE 133 //! - \b EUSCI_B0_BASE 134 //! - \b EUSCI_B1_BASE 135 //! - \b EUSCI_B2_BASE 136 //! - \b EUSCI_B3_BASE 137 //! \param config Configuration structure for SPI master mode 138 //! 139 //! <hr> 140 //! <b>Configuration options for \link eUSCI_SPI_MasterConfig \endlink structure.</b> 141 //! <hr> 142 //! 143 //! \param selectClockSource selects clock source. Valid values are 144 //! - \b EUSCI_SPI_CLOCKSOURCE_ACLK 145 //! - \b EUSCI_SPI_CLOCKSOURCE_SMCLK 146 //! \param clockSourceFrequency is the frequency of the selected clock source 147 //! \param desiredSpiClock is the desired clock rate for SPI communication 148 //! \param msbFirst controls the direction of the receive and transmit shift 149 //! register. Valid values are 150 //! - \b EUSCI_SPI_MSB_FIRST 151 //! - \b EUSCI_SPI_LSB_FIRST [Default Value] 152 //! \param clockPhase is clock phase select. 153 //! Valid values are 154 //! - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 155 //! [Default Value] 156 //! - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT 157 //! \param clockPolarity is clock polarity select. 158 //! Valid values are 159 //! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH 160 //! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default Value] 161 //! \param spiMode is SPI mode select. 162 //! Valid values are 163 //! - \b EUSCI_SPI_3PIN [Default Value] 164 //! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH 165 //! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW 166 //! Upon successful initialization of the SPI master block, this function 167 //! will have set the bus speed for the master, but the SPI Master block 168 //! still remains disabled and must be enabled with SPI_enableModule() 169 //! 170 //! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB,\b UCSSELx, 171 //! \b UCSWRST bits of \b UCAxCTLW0 register 172 //! 173 //! \return true 174 // 175 //***************************************************************************** 176 extern bool SPI_initMaster(uint32_t moduleInstance, 177 const eUSCI_SPI_MasterConfig *config); 178 179 //***************************************************************************** 180 // 181 //! Selects 4Pin Functionality 182 //! 183 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 184 //! parameters vary from part to part, but can include: 185 //! - \b EUSCI_A0_BASE 186 //! - \b EUSCI_A1_BASE 187 //! - \b EUSCI_A2_BASE 188 //! - \b EUSCI_A3_BASE 189 //! - \b EUSCI_B0_BASE 190 //! - \b EUSCI_B1_BASE 191 //! - \b EUSCI_B2_BASE 192 //! - \b EUSCI_B3_BASE 193 //! 194 //! \param select4PinFunctionality selects Clock source. Valid values are 195 //! - \b EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 196 //! - \b EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE 197 //! This function should be invoked only in 4-wire mode. Invoking this function 198 //! has no effect in 3-wire mode. 199 //! 200 //! Modified bits are \b UCSTEM bit of \b UCAxCTLW0 register 201 //! 202 //! \return true 203 // 204 //***************************************************************************** 205 extern void SPI_selectFourPinFunctionality(uint32_t moduleInstance, 206 uint_fast8_t select4PinFunctionality); 207 208 //***************************************************************************** 209 // 210 //! Initializes the SPI Master clock.At the end of this function call, SPI 211 //! module is left enabled. 212 //! 213 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 214 //! parameters vary from part to part, but can include: 215 //! - \b EUSCI_A0_BASE 216 //! - \b EUSCI_A1_BASE 217 //! - \b EUSCI_A2_BASE 218 //! - \b EUSCI_A3_BASE 219 //! - \b EUSCI_B0_BASE 220 //! - \b EUSCI_B1_BASE 221 //! - \b EUSCI_B2_BASE 222 //! - \b EUSCI_B3_BASE 223 //! 224 //! \param clockSourceFrequency is the frequency of the selected clock source 225 //! \param desiredSpiClock is the desired clock rate for SPI communication. 226 //! 227 //! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register and 228 //! \b UCAxBRW register 229 //! 230 //! \return None 231 // 232 //***************************************************************************** 233 extern void SPI_changeMasterClock(uint32_t moduleInstance, 234 uint32_t clockSourceFrequency, uint32_t desiredSpiClock); 235 236 //***************************************************************************** 237 // 238 //! Initializes the SPI Slave block. 239 //! 240 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 241 //! parameters vary from part to part, but can include: 242 //! - \b EUSCI_A0_BASE 243 //! - \b EUSCI_A1_BASE 244 //! - \b EUSCI_A2_BASE 245 //! - \b EUSCI_A3_BASE 246 //! - \b EUSCI_B0_BASE 247 //! - \b EUSCI_B1_BASE 248 //! - \b EUSCI_B2_BASE 249 //! - \b EUSCI_B3_BASE 250 //! \param config Configuration structure for SPI slave mode 251 //! 252 //! <hr> 253 //! <b>Configuration options for \link eUSCI_SPI_SlaveConfig \endlink structure.</b> 254 //! <hr> 255 //! 256 //! \param msbFirst controls the direction of the receive and transmit shift 257 //! register. Valid values are 258 //! - \b EUSCI_SPI_MSB_FIRST 259 //! - \b EUSCI_SPI_LSB_FIRST [Default Value] 260 //! \param clockPhase is clock phase select. 261 //! Valid values are 262 //! - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 263 //! [Default Value] 264 //! - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT 265 //! \param clockPolarity is clock polarity select. 266 //! Valid values are 267 //! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH 268 //! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default Value] 269 //! \param spiMode is SPI mode select. 270 //! Valid values are 271 //! - \b EUSCI_SPI_3PIN [Default Value] 272 //! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH 273 //! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW 274 //! Upon successful initialization of the SPI slave block, this function 275 //! will have initialized the slave block, but the SPI Slave block 276 //! still remains disabled and must be enabled with SPI_enableModule() 277 //! 278 //! Modified bits are \b UCMSB, \b UC7BIT, \b UCMST, \b UCCKPL, \b UCCKPH, 279 //! \b UCMODE, \b UCSWRST bits of \b UCAxCTLW0 280 //! 281 //! \return true 282 //***************************************************************************** 283 extern bool SPI_initSlave(uint32_t moduleInstance, 284 const eUSCI_SPI_SlaveConfig *config); 285 286 //***************************************************************************** 287 // 288 //! Changes the SPI clock phase and polarity.At the end of this function call, 289 //! SPI module is left enabled. 290 //! 291 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 292 //! parameters vary from part to part, but can include: 293 //! - \b EUSCI_A0_BASE 294 //! - \b EUSCI_A1_BASE 295 //! - \b EUSCI_A2_BASE 296 //! - \b EUSCI_A3_BASE 297 //! - \b EUSCI_B0_BASE 298 //! - \b EUSCI_B1_BASE 299 //! - \b EUSCI_B2_BASE 300 //! - \b EUSCI_B3_BASE 301 //! 302 //! \param clockPhase is clock phase select. 303 //! Valid values are: 304 //! - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 305 //! [Default Value] 306 //! - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT 307 //! \param clockPolarity is clock polarity select. 308 //! Valid values are: 309 //! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH 310 //! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default Value] 311 //! 312 //! Modified bits are \b UCSWRST, \b UCCKPH, \b UCCKPL, \b UCSWRST bits of 313 //! \b UCAxCTLW0 314 //! 315 //! \return None 316 // 317 //***************************************************************************** 318 extern void SPI_changeClockPhasePolarity(uint32_t moduleInstance, 319 uint_fast16_t clockPhase, uint_fast16_t clockPolarity); 320 321 //***************************************************************************** 322 // 323 //! Transmits a byte from the SPI Module. 324 //! 325 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 326 //! parameters vary from part to part, but can include: 327 //! - \b EUSCI_A0_BASE 328 //! - \b EUSCI_A1_BASE 329 //! - \b EUSCI_A2_BASE 330 //! - \b EUSCI_A3_BASE 331 //! - \b EUSCI_B0_BASE 332 //! - \b EUSCI_B1_BASE 333 //! - \b EUSCI_B2_BASE 334 //! - \b EUSCI_B3_BASE 335 //! 336 //! \param transmitData data to be transmitted from the SPI module 337 //! 338 //! This function will place the supplied data into SPI transmit data register 339 //! to start transmission 340 //! 341 //! Modified register is \b UCAxTXBUF 342 //! 343 //! \return None. 344 // 345 //***************************************************************************** 346 extern void SPI_transmitData(uint32_t moduleInstance, 347 uint_fast8_t transmitData); 348 349 //***************************************************************************** 350 // 351 //! Receives a byte that has been sent to the SPI Module. 352 //! 353 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 354 //! parameters vary from part to part, but can include: 355 //! - \b EUSCI_A0_BASE 356 //! - \b EUSCI_A1_BASE 357 //! - \b EUSCI_A2_BASE 358 //! - \b EUSCI_A3_BASE 359 //! - \b EUSCI_B0_BASE 360 //! - \b EUSCI_B1_BASE 361 //! - \b EUSCI_B2_BASE 362 //! - \b EUSCI_B3_BASE 363 //! 364 //! 365 //! This function reads a byte of data from the SPI receive data Register. 366 //! 367 //! \return Returns the byte received from by the SPI module, cast as an 368 //! uint8_t. 369 // 370 //***************************************************************************** 371 extern uint8_t SPI_receiveData(uint32_t moduleInstance); 372 373 //***************************************************************************** 374 // 375 //! Enables the SPI block. 376 //! 377 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 378 //! parameters vary from part to part, but can include: 379 //! - \b EUSCI_A0_BASE 380 //! - \b EUSCI_A1_BASE 381 //! - \b EUSCI_A2_BASE 382 //! - \b EUSCI_A3_BASE 383 //! - \b EUSCI_B0_BASE 384 //! - \b EUSCI_B1_BASE 385 //! - \b EUSCI_B2_BASE 386 //! - \b EUSCI_B3_BASE 387 //! 388 //! 389 //! This will enable operation of the SPI block. 390 //! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register. 391 //! 392 //! \return None. 393 // 394 //***************************************************************************** 395 extern void SPI_enableModule(uint32_t moduleInstance); 396 397 //***************************************************************************** 398 // 399 //! Disables the SPI block. 400 //! 401 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 402 //! parameters vary from part to part, but can include: 403 //! - \b EUSCI_A0_BASE 404 //! - \b EUSCI_A1_BASE 405 //! - \b EUSCI_A2_BASE 406 //! - \b EUSCI_A3_BASE 407 //! - \b EUSCI_B0_BASE 408 //! - \b EUSCI_B1_BASE 409 //! - \b EUSCI_B2_BASE 410 //! - \b EUSCI_B3_BASE 411 //! 412 //! 413 //! This will disable operation of the SPI block. 414 //! 415 //! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register. 416 //! 417 //! \return None. 418 // 419 //***************************************************************************** 420 extern void SPI_disableModule(uint32_t moduleInstance); 421 422 //***************************************************************************** 423 // 424 //! Returns the address of the RX Buffer of the SPI for the DMA module. 425 //! 426 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 427 //! parameters vary from part to part, but can include: 428 //! - \b EUSCI_A0_BASE 429 //! - \b EUSCI_A1_BASE 430 //! - \b EUSCI_A2_BASE 431 //! - \b EUSCI_A3_BASE 432 //! - \b EUSCI_B0_BASE 433 //! - \b EUSCI_B1_BASE 434 //! - \b EUSCI_B2_BASE 435 //! - \b EUSCI_B3_BASE 436 //! 437 //! 438 //! Returns the address of the SPI RX Buffer. This can be used in conjunction 439 //! with the DMA to store the received data directly to memory. 440 //! 441 //! \return NONE 442 // 443 //***************************************************************************** 444 extern uint32_t SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance); 445 446 //***************************************************************************** 447 // 448 //! Returns the address of the TX Buffer of the SPI for the DMA module. 449 //! 450 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 451 //! parameters vary from part to part, but can include: 452 //! - \b EUSCI_A0_BASE 453 //! - \b EUSCI_A1_BASE 454 //! - \b EUSCI_A2_BASE 455 //! - \b EUSCI_A3_BASE 456 //! - \b EUSCI_B0_BASE 457 //! - \b EUSCI_B1_BASE 458 //! - \b EUSCI_B2_BASE 459 //! - \b EUSCI_B3_BASE 460 //! 461 //! 462 //! Returns the address of the SPI TX Buffer. This can be used in conjunction 463 //! with the DMA to obtain transmitted data directly from memory. 464 //! 465 //! \return NONE 466 // 467 //***************************************************************************** 468 extern uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance); 469 470 //***************************************************************************** 471 // 472 //! Indicates whether or not the SPI bus is busy. 473 //! 474 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 475 //! parameters vary from part to part, but can include: 476 //! - \b EUSCI_A0_BASE 477 //! - \b EUSCI_A1_BASE 478 //! - \b EUSCI_A2_BASE 479 //! - \b EUSCI_A3_BASE 480 //! - \b EUSCI_B0_BASE 481 //! - \b EUSCI_B1_BASE 482 //! - \b EUSCI_B2_BASE 483 //! - \b EUSCI_B3_BASE 484 //! 485 //! 486 //! This function returns an indication of whether or not the SPI bus is 487 //! busy.This function checks the status of the bus via UCBBUSY bit 488 //! 489 //! \return EUSCI_SPI_BUSY if the SPI module transmitting or receiving 490 //! is busy; otherwise, returns EUSCI_SPI_NOT_BUSY. 491 // 492 //***************************************************************************** 493 extern uint_fast8_t SPI_isBusy(uint32_t moduleInstance); 494 495 //***************************************************************************** 496 // 497 //! Enables individual SPI interrupt sources. 498 //! 499 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 500 //! parameters vary from part to part, but can include: 501 //! - \b EUSCI_A0_BASE 502 //! - \b EUSCI_A1_BASE 503 //! - \b EUSCI_A2_BASE 504 //! - \b EUSCI_A3_BASE 505 //! - \b EUSCI_B0_BASE 506 //! - \b EUSCI_B1_BASE 507 //! - \b EUSCI_B2_BASE 508 //! - \b EUSCI_B3_BASE 509 //! 510 //! \param mask is the bit mask of the interrupt sources to be enabled. 511 //! 512 //! Enables the indicated SPI interrupt sources. Only the sources that 513 //! are enabled can be reflected to the processor interrupt; disabled sources 514 //! have no effect on the processor. 515 //! 516 //! The mask parameter is the logical OR of any of the following: 517 //! - \b EUSCI_SPI_RECEIVE_INTERRUPT Receive interrupt 518 //! - \b EUSCI_SPI_TRANSMIT_INTERRUPT Transmit interrupt 519 //! 520 //! Modified registers are \b UCAxIFG and \b UCAxIE 521 //! 522 //! \return None. 523 // 524 //***************************************************************************** 525 extern void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask); 526 527 //***************************************************************************** 528 // 529 //! Disables individual SPI interrupt sources. 530 //! 531 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 532 //! parameters vary from part to part, but can include: 533 //! - \b EUSCI_A0_BASE 534 //! - \b EUSCI_A1_BASE 535 //! - \b EUSCI_A2_BASE 536 //! - \b EUSCI_A3_BASE 537 //! - \b EUSCI_B0_BASE 538 //! - \b EUSCI_B1_BASE 539 //! - \b EUSCI_B2_BASE 540 //! - \b EUSCI_B3_BASE 541 //! 542 //! \param mask is the bit mask of the interrupt sources to be 543 //! disabled. 544 //! 545 //! Disables the indicated SPI interrupt sources. Only the sources that 546 //! are enabled can be reflected to the processor interrupt; disabled sources 547 //! have no effect on the processor. 548 //! 549 //! The mask parameter is the logical OR of any of the following: 550 //! - \b EUSCI_SPI_RECEIVE_INTERRUPT Receive interrupt 551 //! - \b EUSCI_SPI_TRANSMIT_INTERRUPT Transmit interrupt 552 //! 553 //! Modified register is \b UCAxIE 554 //! 555 //! \return None. 556 // 557 //***************************************************************************** 558 extern void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask); 559 560 //***************************************************************************** 561 // 562 //! Gets the current SPI interrupt status. 563 //! 564 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 565 //! parameters vary from part to part, but can include: 566 //! - \b EUSCI_A0_BASE 567 //! - \b EUSCI_A1_BASE 568 //! - \b EUSCI_A2_BASE 569 //! - \b EUSCI_A3_BASE 570 //! - \b EUSCI_B0_BASE 571 //! - \b EUSCI_B1_BASE 572 //! - \b EUSCI_B2_BASE 573 //! - \b EUSCI_B3_BASE 574 //! \param mask Mask of interrupt to filter. This can include: 575 //! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt 576 //! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt 577 //! 578 //! Modified registers are \b UCAxIFG. 579 //! 580 //! \return The current interrupt status as the mask of the set flags 581 //! Mask parameter can be either any of the following selection: 582 //! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt 583 //! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt 584 // 585 //***************************************************************************** 586 extern uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance, 587 uint16_t mask); 588 589 //***************************************************************************** 590 // 591 //! Gets the current SPI interrupt status masked with the enabled interrupts. 592 //! This function is useful to call in ISRs to get a list of pending 593 //! interrupts that are actually enabled and could have caused 594 //! the ISR. 595 //! 596 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 597 //! parameters vary from part to part, but can include: 598 //! - \b EUSCI_A0_BASE 599 //! - \b EUSCI_A1_BASE 600 //! - \b EUSCI_A2_BASE 601 //! - \b EUSCI_A3_BASE 602 //! - \b EUSCI_B0_BASE 603 //! - \b EUSCI_B1_BASE 604 //! - \b EUSCI_B2_BASE 605 //! - \b EUSCI_B3_BASE 606 //! 607 //! Modified registers are \b UCAxIFG. 608 //! 609 //! \return The current interrupt status as the mask of the set flags 610 //! Mask parameter can be either any of the following selection: 611 //! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt 612 //! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt 613 // 614 //***************************************************************************** 615 extern uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance); 616 617 //***************************************************************************** 618 // 619 //! Clears the selected SPI interrupt status flag. 620 //! 621 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 622 //! parameters vary from part to part, but can include: 623 //! - \b EUSCI_A0_BASE 624 //! - \b EUSCI_A1_BASE 625 //! - \b EUSCI_A2_BASE 626 //! - \b EUSCI_A3_BASE 627 //! - \b EUSCI_B0_BASE 628 //! - \b EUSCI_B1_BASE 629 //! - \b EUSCI_B2_BASE 630 //! - \b EUSCI_B3_BASE 631 //! 632 //! \param mask is the masked interrupt flag to be cleared. 633 //! 634 //! The mask parameter is the logical OR of any of the following: 635 //! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt 636 //! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt 637 //! Modified registers are \b UCAxIFG. 638 //! 639 //! \return None 640 // 641 //***************************************************************************** 642 extern void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask); 643 644 //***************************************************************************** 645 // 646 //! Registers an interrupt handler for the timer capture compare interrupt. 647 //! 648 //! \param moduleInstance is the instance of the eUSCI (SPI) module. Valid 649 //! parameters vary from part to part, but can include: 650 //! - \b EUSCI_A0_BASE 651 //! - \b EUSCI_A1_BASE 652 //! - \b EUSCI_A2_BASE 653 //! - \b EUSCI_A3_BASE 654 //! - \b EUSCI_B0_BASE 655 //! - \b EUSCI_B1_BASE 656 //! - \b EUSCI_B2_BASE 657 //! - \b EUSCI_B3_BASE 658 //! It is important to note that for eUSCI modules, only "B" modules such as 659 //! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the 660 //! I2C mode. 661 //! 662 //! \param intHandler is a pointer to the function to be called when the 663 //! timer capture compare interrupt occurs. 664 //! 665 //! This function registers the handler to be called when a timer 666 //! interrupt occurs. This function enables the global interrupt in the 667 //! interrupt controller; specific SPI interrupts must be enabled 668 //! via SPI_enableInterrupt(). It is the interrupt handler's responsibility to 669 //! clear the interrupt source via SPI_clearInterruptFlag(). 670 //! 671 //! \return None. 672 // 673 //***************************************************************************** 674 extern void SPI_registerInterrupt(uint32_t moduleInstance, 675 void (*intHandler)(void)); 676 677 //***************************************************************************** 678 // 679 //! Unregisters the interrupt handler for the timer 680 //! 681 //! \param moduleInstance is the instance of the eUSCI A/B module. Valid 682 //! parameters vary from part to part, but can include: 683 //! - \b EUSCI_A0_BASE 684 //! - \b EUSCI_A1_BASE 685 //! - \b EUSCI_A2_BASE 686 //! - \b EUSCI_A3_BASE 687 //! - \b EUSCI_B0_BASE 688 //! - \b EUSCI_B1_BASE 689 //! - \b EUSCI_B2_BASE 690 //! - \b EUSCI_B3_BASE 691 //! 692 //! This function unregisters the handler to be called when timer 693 //! interrupt occurs. This function also masks off the interrupt in the 694 //! interrupt controller so that the interrupt handler no longer is called. 695 //! 696 //! \sa Interrupt_registerInterrupt() for important information about 697 //! registering interrupt handlers. 698 //! 699 //! \return None. 700 // 701 //***************************************************************************** 702 extern void SPI_unregisterInterrupt(uint32_t moduleInstance); 703 704 /* Backwards Compatibility Layer */ 705 #define EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 706 #define EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT EUSCI_B_CTLW0_CKPH 707 708 #define EUSCI_B_SPI_MSB_FIRST EUSCI_B_CTLW0_MSB 709 #define EUSCI_B_SPI_LSB_FIRST 0x00 710 711 #define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH EUSCI_B_CTLW0_CKPL 712 #define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 713 714 #define EUSCI_B_SPI_CLOCKSOURCE_ACLK EUSCI_B_CTLW0_SSEL__ACLK 715 #define EUSCI_B_SPI_CLOCKSOURCE_SMCLK EUSCI_B_CTLW0_SSEL__SMCLK 716 717 #define EUSCI_B_SPI_3PIN EUSCI_B_CTLW0_MODE_0 718 #define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH EUSCI_B_CTLW0_MODE_1 719 #define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW EUSCI_B_CTLW0_MODE_2 720 721 #define EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00 722 #define EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE EUSCI_B_CTLW0_STEM 723 724 #define EUSCI_B_SPI_TRANSMIT_INTERRUPT EUSCI_B_IE_TXIE0 725 #define EUSCI_B_SPI_RECEIVE_INTERRUPT EUSCI_B_IE_RXIE0 726 727 #define EUSCI_B_SPI_BUSY EUSCI_B_STATW_BBUSY 728 #define EUSCI_B_SPI_NOT_BUSY 0x00 729 730 #define EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 731 #define EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT EUSCI_A_CTLW0_CKPH 732 733 #define EUSCI_A_SPI_MSB_FIRST EUSCI_A_CTLW0_MSB 734 #define EUSCI_A_SPI_LSB_FIRST 0x00 735 736 #define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH EUSCI_A_CTLW0_CKPL 737 #define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 738 739 #define EUSCI_A_SPI_CLOCKSOURCE_ACLK EUSCI_A_CTLW0_SSEL__ACLK 740 #define EUSCI_A_SPI_CLOCKSOURCE_SMCLK EUSCI_A_CTLW0_SSEL__SMCLK 741 742 #define EUSCI_A_SPI_3PIN EUSCI_A_CTLW0_MODE_0 743 #define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH EUSCI_A_CTLW0_MODE_1 744 #define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW EUSCI_A_CTLW0_MODE_2 745 746 #define EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00 747 #define EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE EUSCI_A_CTLW0_STEM 748 749 #define EUSCI_A_SPI_TRANSMIT_INTERRUPT EUSCI_A_IE_TXIE 750 #define EUSCI_A_SPI_RECEIVE_INTERRUPT EUSCI_A_IE_RXIE 751 752 #define EUSCI_A_SPI_BUSY EUSCI_B_STATW_BBUSY 753 #define EUSCI_A_SPI_NOT_BUSY 0x00 754 755 extern void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress, 756 uint8_t select4PinFunctionality); 757 extern void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress, 758 uint32_t clockSourceFrequency, uint32_t desiredSpiClock); 759 extern bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst, 760 uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode); 761 extern void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress, 762 uint16_t clockPhase, uint16_t clockPolarity); 763 extern void EUSCI_A_SPI_transmitData(uint32_t baseAddress, 764 uint8_t transmitData); 765 extern uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress); 766 extern void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask); 767 extern void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask); 768 extern uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress, 769 uint8_t mask); 770 extern void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask); 771 extern void EUSCI_A_SPI_enable(uint32_t baseAddress); 772 extern void EUSCI_A_SPI_disable(uint32_t baseAddress); 773 extern uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress); 774 extern uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA( 775 uint32_t baseAddress); 776 extern bool EUSCI_A_SPI_isBusy(uint32_t baseAddress); 777 extern void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress, 778 uint8_t select4PinFunctionality); 779 extern void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress, 780 uint32_t clockSourceFrequency, uint32_t desiredSpiClock); 781 extern bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst, 782 uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode); 783 extern void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress, 784 uint16_t clockPhase, uint16_t clockPolarity); 785 extern void EUSCI_B_SPI_transmitData(uint32_t baseAddress, 786 uint8_t transmitData); 787 extern uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress); 788 extern void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask); 789 extern void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask); 790 extern uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress, 791 uint8_t mask); 792 extern void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask); 793 extern void EUSCI_B_SPI_enable(uint32_t baseAddress); 794 extern void EUSCI_B_SPI_disable(uint32_t baseAddress); 795 extern uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress); 796 extern uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA( 797 uint32_t baseAddress); 798 extern bool EUSCI_B_SPI_isBusy(uint32_t baseAddress); 799 800 //***************************************************************************** 801 // 802 // Mark the end of the C bindings section for C++ compilers. 803 // 804 //***************************************************************************** 805 #ifdef __cplusplus 806 } 807 #endif 808 809 //***************************************************************************** 810 // 811 // Close the Doxygen group. 812 //! @} 813 // 814 //***************************************************************************** 815 816 #endif /* SPI_H_ */ 817 818
