1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_DES_H__ 35 #define __HW_DES_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the DES_P register offsets. 40 // 41 //***************************************************************************** 42 #define DES_O_KEY3_L 0x00000000 // KEY3 (LSW) for 192-bit key 43 #define DES_O_KEY3_H 0x00000004 // KEY3 (MSW) for 192-bit key 44 #define DES_O_KEY2_L 0x00000008 // KEY2 (LSW) for 192-bit key 45 #define DES_O_KEY2_H 0x0000000C // KEY2 (MSW) for 192-bit key 46 #define DES_O_KEY1_L 0x00000010 // KEY1 (LSW) for 128-bit 47 // key/192-bit key 48 #define DES_O_KEY1_H 0x00000014 // KEY1 (LSW) for 128-bit 49 // key/192-bit key 50 #define DES_O_IV_L 0x00000018 // Initialization vector LSW 51 #define DES_O_IV_H 0x0000001C // Initialization vector MSW 52 #define DES_O_CTRL 0x00000020 53 #define DES_O_LENGTH 0x00000024 // Indicates the cryptographic data 54 // length in bytes for all modes. 55 // Once processing is started with 56 // this context this length 57 // decrements to zero. Data lengths 58 // up to (2^32 – 1) bytes are 59 // allowed. A write to this register 60 // triggers the engine to start 61 // using this context. For a Host 62 // read operation these registers 63 // return all-zeroes. 64 #define DES_O_DATA_L 0x00000028 // Data register(LSW) to read/write 65 // encrypted/decrypted data. 66 #define DES_O_DATA_H 0x0000002C // Data register(MSW) to read/write 67 // encrypted/decrypted data. 68 #define DES_O_REVISION 0x00000030 69 #define DES_O_SYSCONFIG 0x00000034 70 #define DES_O_SYSSTATUS 0x00000038 71 #define DES_O_IRQSTATUS 0x0000003C // This register indicates the 72 // interrupt status. If one of the 73 // interrupt bits is set the 74 // interrupt output will be asserted 75 #define DES_O_IRQENABLE 0x00000040 // This register contains an enable 76 // bit for each unique interrupt 77 // generated by the module. It 78 // matches the layout of 79 // DES_IRQSTATUS register. An 80 // interrupt is enabled when the bit 81 // in this register is set to 1 82 83 84 85 //****************************************************************************** 86 // 87 // The following are defines for the bit fields in the DES_O_KEY3_L register. 88 // 89 //****************************************************************************** 90 #define DES_KEY3_L_KEY3_L_M 0xFFFFFFFF // data for key3 91 #define DES_KEY3_L_KEY3_L_S 0 92 //****************************************************************************** 93 // 94 // The following are defines for the bit fields in the DES_O_KEY3_H register. 95 // 96 //****************************************************************************** 97 #define DES_KEY3_H_KEY3_H_M 0xFFFFFFFF // data for key3 98 #define DES_KEY3_H_KEY3_H_S 0 99 //****************************************************************************** 100 // 101 // The following are defines for the bit fields in the DES_O_KEY2_L register. 102 // 103 //****************************************************************************** 104 #define DES_KEY2_L_KEY2_L_M 0xFFFFFFFF // data for key2 105 #define DES_KEY2_L_KEY2_L_S 0 106 //****************************************************************************** 107 // 108 // The following are defines for the bit fields in the DES_O_KEY2_H register. 109 // 110 //****************************************************************************** 111 #define DES_KEY2_H_KEY2_H_M 0xFFFFFFFF // data for key2 112 #define DES_KEY2_H_KEY2_H_S 0 113 //****************************************************************************** 114 // 115 // The following are defines for the bit fields in the DES_O_KEY1_L register. 116 // 117 //****************************************************************************** 118 #define DES_KEY1_L_KEY1_L_M 0xFFFFFFFF // data for key1 119 #define DES_KEY1_L_KEY1_L_S 0 120 //****************************************************************************** 121 // 122 // The following are defines for the bit fields in the DES_O_KEY1_H register. 123 // 124 //****************************************************************************** 125 #define DES_KEY1_H_KEY1_H_M 0xFFFFFFFF // data for key1 126 #define DES_KEY1_H_KEY1_H_S 0 127 //****************************************************************************** 128 // 129 // The following are defines for the bit fields in the DES_O_IV_L register. 130 // 131 //****************************************************************************** 132 #define DES_IV_L_IV_L_M 0xFFFFFFFF // initialization vector for CBC 133 // CFB modes 134 #define DES_IV_L_IV_L_S 0 135 //****************************************************************************** 136 // 137 // The following are defines for the bit fields in the DES_O_IV_H register. 138 // 139 //****************************************************************************** 140 #define DES_IV_H_IV_H_M 0xFFFFFFFF // initialization vector for CBC 141 // CFB modes 142 #define DES_IV_H_IV_H_S 0 143 //****************************************************************************** 144 // 145 // The following are defines for the bit fields in the DES_O_CTRL register. 146 // 147 //****************************************************************************** 148 #define DES_CTRL_CONTEXT 0x80000000 // If ‘1’ this read-only status bit 149 // indicates that the context data 150 // registers can be overwritten and 151 // the host is permitted to write 152 // the next context. 153 #define DES_CTRL_MODE_M 0x00000030 // Select CBC ECB or CFB mode 0x0 154 // ecb mode 0x1 cbc mode 0x2 cfb 155 // mode 0x3 reserved 156 #define DES_CTRL_MODE_S 4 157 #define DES_CTRL_TDES 0x00000008 // Select DES or triple DES 158 // encryption/decryption. 0 des mode 159 // 1 tdes mode 160 #define DES_CTRL_DIRECTION 0x00000004 // select encryption/decryption 0 161 // decryption is selected 1 162 // Encryption is selected 163 #define DES_CTRL_INPUT_READY 0x00000002 // When '1' ready to 164 // encrypt/decrypt data 165 #define DES_CTRL_OUTPUT_READY 0x00000001 // When '1' Data 166 // decrypted/encrypted ready 167 //****************************************************************************** 168 // 169 // The following are defines for the bit fields in the DES_O_LENGTH register. 170 // 171 //****************************************************************************** 172 #define DES_LENGTH_LENGTH_M 0xFFFFFFFF 173 #define DES_LENGTH_LENGTH_S 0 174 //****************************************************************************** 175 // 176 // The following are defines for the bit fields in the DES_O_DATA_L register. 177 // 178 //****************************************************************************** 179 #define DES_DATA_L_DATA_L_M 0xFFFFFFFF // data for encryption/decryption 180 #define DES_DATA_L_DATA_L_S 0 181 //****************************************************************************** 182 // 183 // The following are defines for the bit fields in the DES_O_DATA_H register. 184 // 185 //****************************************************************************** 186 #define DES_DATA_H_DATA_H_M 0xFFFFFFFF // data for encryption/decryption 187 #define DES_DATA_H_DATA_H_S 0 188 //****************************************************************************** 189 // 190 // The following are defines for the bit fields in the DES_O_REVISION register. 191 // 192 //****************************************************************************** 193 #define DES_REVISION_SCHEME_M 0xC0000000 194 #define DES_REVISION_SCHEME_S 30 195 #define DES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software 196 // compatible module family. If 197 // there is no level of software 198 // compatibility a new Func number 199 // (and hence REVISION) should be 200 // assigned. 201 #define DES_REVISION_FUNC_S 16 202 #define DES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP 203 // design owner. RTL follows a 204 // numbering such as X.Y.R.Z which 205 // are explained in this table. R 206 // changes ONLY when: (1) PDS 207 // uploads occur which may have been 208 // due to spec changes (2) Bug fixes 209 // occur (3) Resets to '0' when X or 210 // Y changes. Design team has an 211 // internal 'Z' (customer invisible) 212 // number which increments on every 213 // drop that happens due to DV and 214 // RTL updates. Z resets to 0 when R 215 // increments. 216 #define DES_REVISION_R_RTL_S 11 217 #define DES_REVISION_X_MAJOR_M \ 218 0x00000700 // Major Revision (X) maintained by 219 // IP specification owner. X changes 220 // ONLY when: (1) There is a major 221 // feature addition. An example 222 // would be adding Master Mode to 223 // Utopia Level2. The Func field (or 224 // Class/Type in old PID format) 225 // will remain the same. X does NOT 226 // change due to: (1) Bug fixes (2) 227 // Change in feature parameters. 228 229 #define DES_REVISION_X_MAJOR_S 8 230 #define DES_REVISION_CUSTOM_M 0x000000C0 231 #define DES_REVISION_CUSTOM_S 6 232 #define DES_REVISION_Y_MINOR_M \ 233 0x0000003F // Minor Revision (Y) maintained by 234 // IP specification owner. Y changes 235 // ONLY when: (1) Features are 236 // scaled (up or down). Flexibility 237 // exists in that this feature 238 // scalability may either be 239 // represented in the Y change or a 240 // specific register in the IP that 241 // indicates which features are 242 // exactly available. (2) When 243 // feature creeps from Is-Not list 244 // to Is list. But this may not be 245 // the case once it sees silicon; in 246 // which case X will change. Y does 247 // NOT change due to: (1) Bug fixes 248 // (2) Typos or clarifications (3) 249 // major functional/feature 250 // change/addition/deletion. Instead 251 // these changes may be reflected 252 // via R S X as applicable. Spec 253 // owner maintains a 254 // customer-invisible number 'S' 255 // which changes due to: (1) 256 // Typos/clarifications (2) Bug 257 // documentation. Note that this bug 258 // is not due to a spec change but 259 // due to implementation. 260 // Nevertheless the spec tracks the 261 // IP bugs. An RTL release (say for 262 // silicon PG1.1) that occurs due to 263 // bug fix should document the 264 // corresponding spec number (X.Y.S) 265 // in its release notes. 266 267 #define DES_REVISION_Y_MINOR_S 0 268 //****************************************************************************** 269 // 270 // The following are defines for the bit fields in the DES_O_SYSCONFIG register. 271 // 272 //****************************************************************************** 273 #define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ 274 0x00000080 // If set to ‘1’ the DMA context 275 // request is enabled. 0 Dma 276 // disabled 1 Dma enabled 277 278 #define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ 279 0x00000040 // If set to ‘1’ the DMA output 280 // request is enabled. 0 Dma 281 // disabled 1 Dma enabled 282 283 #define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ 284 0x00000020 // If set to ‘1’ the DMA input 285 // request is enabled. 0 Dma 286 // disabled 1 Dma enabled 287 288 //****************************************************************************** 289 // 290 // The following are defines for the bit fields in the DES_O_SYSSTATUS register. 291 // 292 //****************************************************************************** 293 #define DES_SYSSTATUS_RESETDONE \ 294 0x00000001 295 296 //****************************************************************************** 297 // 298 // The following are defines for the bit fields in the DES_O_IRQSTATUS register. 299 // 300 //****************************************************************************** 301 #define DES_IRQSTATUS_DATA_OUT \ 302 0x00000004 // This bit indicates data output 303 // interrupt is active and triggers 304 // the interrupt output. 305 306 #define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input 307 // interrupt is active and triggers 308 // the interrupt output. 309 #define DES_IRQSTATUS_CONTEX_IN \ 310 0x00000001 // This bit indicates context 311 // interrupt is active and triggers 312 // the interrupt output. 313 314 //****************************************************************************** 315 // 316 // The following are defines for the bit fields in the DES_O_IRQENABLE register. 317 // 318 //****************************************************************************** 319 #define DES_IRQENABLE_M_DATA_OUT \ 320 0x00000004 // If this bit is set to ‘1’ the 321 // secure data output interrupt is 322 // enabled. 323 324 #define DES_IRQENABLE_M_DATA_IN \ 325 0x00000002 // If this bit is set to ‘1’ the 326 // secure data input interrupt is 327 // enabled. 328 329 #define DES_IRQENABLE_M_CONTEX_IN \ 330 0x00000001 // If this bit is set to ‘1’ the 331 // secure context interrupt is 332 // enabled. 333 334 335 336 337 #endif // __HW_DES_H__ 338
